diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json new file mode 100644 index 000000000..c2235983d --- /dev/null +++ b/.devcontainer/devcontainer.json @@ -0,0 +1,8 @@ +{ + "name": "Verilator Build Environment", + + "build": { + "dockerfile": "../ci/docker/buildenv/Dockerfile" + } + +} diff --git a/.github/ISSUE_TEMPLATE/bug_report.md b/.github/ISSUE_TEMPLATE/bug_report.md index 630291446..deec5b713 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.md +++ b/.github/ISSUE_TEMPLATE/bug_report.md @@ -11,6 +11,8 @@ Thanks for taking the time to report this. Can you attach an example that shows the issue? (Must be openly licensed, ideally in test_regress format.) +What 'verilator' command line do we use to run your example? + What 'verilator --version' are you using? Did you try it with the git master version? What OS and distribution are you using? diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index ca68a4957..42eb92003 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -167,3 +167,30 @@ jobs: env: TESTS: ${{ matrix.suite }} run: ./ci/ci-script.bash + + lint-py: + runs-on: ubuntu-22.04 + name: Lint Python + env: + CI_BUILD_STAGE_NAME: build + CI_RUNS_ON: ubuntu-22.04 + CI_M32: 0 + steps: + - name: Checkout + uses: actions/checkout@v3 + with: + path: repo + + - name: Install packages for build + run: ./ci/ci-install.bash + + # We use specific version numbers, otherwise a Python package + # update may add a warning and break our build + - name: Install packages for lint + run: sudo pip3 install pylint==3.0.2 ruff==0.1.3 clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff + + - name: Configure + run: autoconf && ./configure --enable-longtests --enable-ccwarn + + - name: Lint + run: make -k lint-py diff --git a/.github/workflows/lint.yaml b/.github/workflows/lint.yaml deleted file mode 100644 index cb64707f4..000000000 --- a/.github/workflows/lint.yaml +++ /dev/null @@ -1,53 +0,0 @@ -# DESCRIPTION: Github actions config -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -name: lint - -on: - push: - pull_request: - workflow_dispatch: - schedule: - - cron: '0 0 * * 0' # weekly - -env: - CI_OS_NAME: linux - CI_COMMIT: ${{ github.sha }} - -defaults: - run: - shell: bash - working-directory: repo - -concurrency: - group: ${{ github.workflow }}-${{ github.event_name == 'pull_request' && github.ref || github.run_id }} - cancel-in-progress: true - -jobs: - - lint-py: - runs-on: ubuntu-22.04 - name: Lint Python - env: - CI_BUILD_STAGE_NAME: build - CI_RUNS_ON: ubuntu-22.04 - CI_M32: 0 - steps: - - name: Checkout - uses: actions/checkout@v3 - with: - path: repo - - - name: Install packages for build - run: ./ci/ci-install.bash - - # We use specific version numbers, otherwise a Python package - # update may add a warning and break our build - - name: Install packages for lint - run: sudo pip3 install pylint==3.0.2 ruff==0.1.3 clang sphinx sphinx_rtd_theme sphinxcontrib-spelling breathe ruff - - - name: Configure - run: autoconf && ./configure --enable-longtests --enable-ccwarn - - - name: Lint - run: make -k lint-py diff --git a/CMakeLists.txt b/CMakeLists.txt index 63510641a..af9bdf1e0 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -4,7 +4,7 @@ # #***************************************************************************** # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -15,7 +15,7 @@ cmake_minimum_required(VERSION 3.15) cmake_policy(SET CMP0091 NEW) # Use MSVC_RUNTIME_LIBRARY to select the runtime project(Verilator - VERSION 5.018 + VERSION 5.020 HOMEPAGE_URL https://verilator.org LANGUAGES CXX ) @@ -35,7 +35,7 @@ if (NOT WIN32) message(WARNING "CMake support on Linux/OSX is experimental.") endif() -if (MSVC) +if (WIN32) if (DEFINED ENV{WIN_FLEX_BISON}) set(WIN_FLEX_BISON "$ENV{WIN_FLEX_BISON}") endif() @@ -48,6 +48,27 @@ if (MSVC) set(CMAKE_CXX_STANDARD 20) endif() +set(OBJCACHE "" CACHE STRING "Path for ccache, auto-detected if empty") +option(OBJCACHE_ENABLED "Compile Verilator with ccache" ON) + +if (OBJCACHE_ENABLED) + if (OBJCACHE STREQUAL "") + find_program(OBJCACHE_PATH ccache) + if (OBJCACHE_PATH STREQUAL "OBJCACHE_PATH-NOTFOUND") + set(OBJCACHE_PATH "") + endif() + else() + set(OBJCACHE_PATH "${OBJCACHE}") + endif() + if (NOT OBJCACHE_PATH STREQUAL "") + execute_process(COMMAND "${OBJCACHE_PATH}" --version + OUTPUT_VARIABLE objcache_version) + string(REGEX MATCH "[^\n\r]+" objcache_version "${objcache_version}") + message(STATUS "Found ccache: ${OBJCACHE_PATH} (\"${objcache_version}\")") + set(CMAKE_CXX_COMPILER_LAUNCHER "${OBJCACHE_PATH}") + endif() +endif() + find_package(BISON) find_package(FLEX) diff --git a/Changes b/Changes index ee1167e6f..f40ca5aa1 100644 --- a/Changes +++ b/Changes @@ -8,6 +8,71 @@ The changes in each Verilator version are described below. The contributors that suggested a given feature are shown in []. Thanks! +Verilator 5.020 2024-01-01 +========================== + +**Major:** + +* Support compilation with precompiled headers with Make and GCC or CLang. +* Change include to systemc instead of systemc.h (#4622) (#4623). [Chih-Mao Chen] + This may require that SystemC programs add 'using namespace sc_core', 'using namespace sc_dt'. + +**Minor:** + +* Add devcontainer support (#4748). [Stefan Wallentowitz] +* Support `iff` in sensitivity list (#1482) (#4626). [Krzysztof Bieganski, Antmicro Ltd.] +* Support parameterized virtual interfaces (#4047) (#4743). [Ryszard Rozak, Antmicro Ltd.] +* Support --timing triggers for virtual interfaces (#4673). [Krzysztof Bieganski, Antmicro Ltd.] +* Support ccache when compiling Verilator with CMake (#4678). [Anthony Donlon] +* Support passing constraints to --xml-only output (still otherwise unsupported) (#4683). [Shahid Ikram] +* Support node memory usage information in --stats (#4684). [Geza Lore] +* Support vpiConstType in vpi_get() (#4761). [Todd Strader] +* Support vpi_iterate on packages with vpiInstance (#4726). [Todd Strader] +* Support multiple parameters in virtual interfaces (#4745). [Ryszard Rozak, Antmicro Ltd.] +* Support user C/C++ code in final archive, and make a lib{model}.a (#4749) (#4754). [Fan Shupei] +* Support inside operator on unpacked arrays and queues (#4751). [Ryszard Rozak, Antmicro Ltd.] +* Support VPI parameter iteration (#4765). [Todd Strader] +* Support packages in vpi_handle_by_name() (#4768). [Todd Strader] +* Support invoking interface methods on virtual interface variables (#4774) (#4775). [Jordan McConnon] +* Remove deprecated options (#4663). [Geza Lore] +* Remove older compiler support; require C++14 or newer (#4784) (#4786). +* Optimize timing-delayed queue (#4584). [qrqiuren] +* Optimize substitute optimization memory usage (#4687). [Geza Lore] +* Optimize wide primitive operations with -Oz (#4733). [Geza Lore] +* Optimize V3Premit performance etc. (#4736). [Geza Lore] +* Fix VPI TOP level variable iteration (#3919) (#4618). [Marlon James] +* Fix display with no % printing assoc array (#4376). [Alex Solomatnikov] +* Fix scheduling of external force signals (#4577) (#4668). [Geza Lore] +* Fix a memory leak in V3Fork (#4628). [Krzysztof Boroński] +* Fix linking parameterized hierarchical blocks and recursive hierarchical blocks (#4654). [Anthony Donlon] +* Fix identifiers that end with '_' on Windows (#4655). [Anthony Donlon] +* Fix 'for' loop with outside variable reference (#4660). [David Harris] +* Fix tracing FST enums (#4661) (#4756). [Todd Strader] +* Fix interface parameters used in loop generate constructs (#4664) (#4665). [Anthony Donlon] +* Fix C++20 compilation errors (#4670). +* Fix deadlocks in error handler (#4672). [Mariusz Glebocki, Antmicro Ltd.] +* Fix MingW compilation (#4675). [David Ledger] +* Fix trace when using SystemC with certain configurations (#4676). [Anthony Donlon] +* Fix range access to classes depending on parameter resolution (#4681). [Krzysztof Boroński] +* Fix select into constant And/Or/Xor pattern (#4689). [Geza Lore] +* Fix access type of function arguments (#4692) (#4694). [Ryszard Rozak, Antmicro Ltd.] +* Fix dynamic NBAs with automatic vars (#4696). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix # 0 delays for process resumption, etc. (#4697). [Krzysztof Boroński] +* Fix conflicted namespace for coroutines (#4701) (#4707). [Jinyan Xu] +* Fix compilers seeing empty input due to file system races (#4708). [Flavien Solt] +* Fix shift of > 32-bit number (#4719). [Flavien Solt] +* Fix Windows include gates in filesystem Flush implementation. (#4720). [William D. Jones] +* Fix power operator with wide numbers and constants (#4721) (#4763). [Flavien Solt] +* Fix parameter passing to ports (#4723). [Ryszard Rozak, Antmicro Ltd.] +* Fix block names of nested do..while loops (#4728). [Ryszard Rozak, Antmicro Ltd.] +* Fix class name in error on 'new' on virtual class (#4739). [Ryszard Rozak, Antmicro Ltd.] +* Fix typedefs pointing to parameterized classes (#4747). [Ryszard Rozak, Antmicro Ltd.] +* Fix $finish twice to no longer exit (#4757). [Tim Hutt] +* Fix dynamic NBA conditions (#4773). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix `V3Fork` stage to run only if `--timing` is set (#4778). [Krzysztof Bieganski, Antmicro Ltd.] +* Fix max multiply width and add runtime assertions if too small. (#4781) + + Verilator 5.018 2023-10-30 ========================== @@ -510,7 +575,7 @@ Verilator 5.002 2022-10-29 * Fix null access on optimized-out fork statements (#3658). [Krzysztof Bieganski, Antmicro Ltd] * Fix VPI inline module naming mismatch (#3690) (#3694). [Jiuyang Liu] * Fix deadlock in timeprecision when using SystemC (#3707). [Kamil Rakoczy, Antmicro Ltd] -* Fix width mismatch on inside operator (#3714). [Alex Torregrosa] +* Fix width mismatch on inside operator (#3714). [Àlex Torregrosa] Verilator 4.228 2022-10-01 @@ -740,7 +805,7 @@ Verilator 4.214 2021-10-17 * Fix removing if statement with side effect in condition (#3131). [Alexander Grobman] * Fix --waiver-output for multiline warnings (#2429) (#3141). [Keith Colbert] * Fix internal error on bad widths (#3140) (#3145). [Zhanglei Wang] -* Fix crash on clang 12/13 (#3148). [Kouping Hsu] +* Fix crash on clang 12/13 (#3148). [Kuoping Hsu] * Fix cygwin compile error due to missing -std=gnu++14 (#3149). [Sun Kim] * Fix $urandom_range when the range is 0 ... UINT_MAX (#3161). [Iru Cai] * Fix constructor-parameter argument comma-separation in C++ (#3162). [Matthew Ballance] @@ -855,12 +920,12 @@ Verilator 4.202 2021-04-24 * Mark --no-relative-cfuncs as scheduled for deprecation. * Add --coverage-max-width (#2853). [xuejiazidi] * Add VerilatedCovContext::forcePerInstance (#2793). [Kevin Laeufer] -* Add FST SystemC tracing (#2806). [Alex Torregrosa] +* Add FST SystemC tracing (#2806). [Àlex Torregrosa] * Add PINNOTFOUND warning in place of error (#2868). [Udi Finkelstein] * Support overlaps in priority case statements (#2864). [Rupert Swarbrick] * Support for null ports (#2875). [Udi Finkelstein] * Fix class unpacked-array compile error (#2774). [Iru Cai] -* Fix scope types in FST and VCD traces (#2805). [Alex Torregrosa] +* Fix scope types in FST and VCD traces (#2805). [Àlex Torregrosa] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] * Fix false $dumpfile warning on model save (#2834). [Yinan Xu] * Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett] @@ -917,7 +982,7 @@ Verilator 4.110 2021-02-25 **Minor:** * Support concat selection (#2721). -* Support struct scopes when dumping structs to VCD (#2776) [Alex Torregrosa] +* Support struct scopes when dumping structs to VCD (#2776) [Àlex Torregrosa] * Generate SELRANGE for potentially unreachable code (#2625) (#2754) [Pierre-Henri Horrein] * For --flatten, override inlining of public and no_inline modules (#2761) [James Hanlon] * Fix little endian interface pin swizzling (#2475). [Don Owen] @@ -928,7 +993,7 @@ Verilator 4.110 2021-02-25 * Fix class extends with VM_PARALLEL_BUILDS (#2775). [Iru Cai] * Fix shifts by > 32 bit values (#2785). [qrq992] * Fix examples not flushing vcd (#2787). [Richard E George] -* Fix little endian packed array pattern assignment (#2795). [Alex Torregrosa] +* Fix little endian packed array pattern assignment (#2795). [Àlex Torregrosa] Verilator 4.108 2021-01-10 @@ -1404,7 +1469,7 @@ Verilator 4.014 2019-05-08 **Minor:** * Add --trace-fst-thread. -* Support '#' comments in $readmem. (#1411) [Frederick Requin] +* Support '#' comments in $readmem. (#1411) [Frédéric Requin] * Support "'dx" constants. (#1423) [Udi Finkelstein] * For FST tracing use LZ4 compression. [Tony Bybell] * Add error when use parameters without value. (#1424) [Peter Gerst] @@ -1674,19 +1739,19 @@ Verilator 3.912 2017-09-23 **Minor:** -* Support or/and/xor array intrinsic methods. (#1210) [Mike Popoloski] +* Support or/and/xor array intrinsic methods. (#1210) [Michael Popoloski] * Support package export. (#1217) [Usuario Eda] -* Support module port parameters without defaults. (#1213) [Mike Popoloski] +* Support module port parameters without defaults. (#1213) [Michael Popoloski] * Add performance information to --stats file. * Simplify VL_CONST_W macro generation for faster compiles. * Optimize improvements for Shift-And, and replication constructs. -* Fix ordering of arrayed cell wide connections. (#1202 partial) [Mike Popoloski] -* Fix LITENDIAN warning on arrayed cells. (#1202) [Mike Popoloski] -* Fix enum ranges without colons. (#1204) [Mike Popoloski] -* Fix GCC noreturn compile error. (#1209) [Mike Popoloski] -* Fix constant function default parameters. (#1211) [Mike Popoloski] -* Fix non-colon array of interface modports. (#1212) [Mike Popoloski] -* Fix .name connections on interfaces. (#1214) [Mike Popoloski] +* Fix ordering of arrayed cell wide connections. (#1202 partial) [Michael Popoloski] +* Fix LITENDIAN warning on arrayed cells. (#1202) [Michael Popoloski] +* Fix enum ranges without colons. (#1204) [Michael Popoloski] +* Fix GCC noreturn compile error. (#1209) [Michael Popoloski] +* Fix constant function default parameters. (#1211) [Michael Popoloski] +* Fix non-colon array of interface modports. (#1212) [Michael Popoloski] +* Fix .name connections on interfaces. (#1214) [Michael Popoloski] * Fix wide array indices causing compile error. @@ -1808,8 +1873,8 @@ Verilator 3.888 2016-10-14 **Minor:** -* Add --no-decoration to remove output comments, msg2015. [Frederic Requin] -* If VM_PARALLEL_BUILDS=1, use OPT_FAST and OPT_SLOW. [Frederic Requin] +* Add --no-decoration to remove output comments, msg2015. [Frédéric Requin] +* If VM_PARALLEL_BUILDS=1, use OPT_FAST and OPT_SLOW. [Frédéric Requin] Set VM_DEFAULT_RULES=0 for old behavior. * Add error on DPI functions > 32 bits. (#1898) [Elliot Mednick] * Improve Verilation performance on internal strings. (#1896) [Johan Bjork] @@ -1845,7 +1910,7 @@ Verilator 3.884 2016-05-18 * Fix --output-split of constructors. (#1035) [Johan Bjork] * Fix removal of empty packages, modules and cells. (#1034) [Johan Bjork] * Fix core dump on Arch Linux/GCC 6.1.1. (#1058) [Jannis Harder] -* Fix $value$plusargs to string. (#1880) [Frederic Requin] +* Fix $value$plusargs to string. (#1880) [Frédéric Requin] Verilator 3.882 2016-03-01 @@ -1924,13 +1989,13 @@ Verilator 3.876 2015-08-12 **Minor:** -* Add tracing_on, etc to vlt files. (#932) [Frederic Requin] +* Add tracing_on, etc to vlt files. (#932) [Frédéric Requin] * Support extraction of enum bits. (#951) [Jonathon Donaldson] * Fix MinGW compiler error. (#927) (#929) [Hans Tichelaar] * Fix .c files to be treated as .cpp. (#930) [Jonathon Donaldson] * Fix string-to-int space conversion. (#931) [Fabrizio Ferrandi] * Fix dpi imports inside generates. [Michael Tresidder] -* Fix rounding in trace $timescale. (#946) [Frederic Requin] +* Fix rounding in trace $timescale. (#946) [Frédéric Requin] * Fix $fopen with SV string. (#947) [Sven Stucki] * Fix hashed error with typedef inside block. (#948) [Sven Stucki] * Fix makefile with --coverage. (#953) [Eivind Liland] @@ -2170,7 +2235,7 @@ Verilator 3.852 2013-09-29 * Support named function and task arguments. [Chris Randall] * Report SELRANGE warning for non-generate if. (#675) [Roland Kruse] -* Fix ordering of $fgetc. (#1808) [Frederic Requin] +* Fix ordering of $fgetc. (#1808) [Frédéric Requin] * Fix --output-split-cfunc to count internal functions. [Chris Randall] * Fix crash on 32-bit Ubuntu. (#670) [Mark Jackson Pulver] @@ -2238,7 +2303,7 @@ Verilator 3.846 2013-03-09 * Fix DETECTARRAY on packed structures. (#610) [Jeremy Bennett] * Fix LITENDIAN on unpacked structures. (#614) [Wai Sum Mong] * Fix 32-bit OS VPI scan issue. (#615) [Jeremy Bennett, Rich Porter] -* Fix opening a VerilatedVcdC file multiple times. (#1774) [Frederic Requin] +* Fix opening a VerilatedVcdC file multiple times. (#1774) [Frédéric Requin] * Fix UNOPTFLAT circular array bounds crossing. (#630) [Jie Xu] @@ -3550,7 +3615,7 @@ Verilator 3.460 2005-07-27 Beta * Fix false warning when a clock is constant. * Fix X/Z in decimal numbers. [Wim Michiels] * Fix genvar statements in non-named generate blocks. -* Fix core dump when missing newline in `define. [David van der bokke] +* Fix core dump when missing newline in `define. [David van der Bokke] Verilator 3.450 2005-07-12 @@ -4446,7 +4511,7 @@ Verilator 0.0 1994-07-08 Copyright ========= -Copyright 2001-2023 by Wilson Snyder. This program is free software; you +Copyright 2001-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/Makefile.in b/Makefile.in index 8eb581f1e..205c912d9 100644 --- a/Makefile.in +++ b/Makefile.in @@ -7,7 +7,7 @@ # #***************************************************************************** # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/README.rst b/README.rst index d6fed5975..6fb7c5e4d 100644 --- a/README.rst +++ b/README.rst @@ -142,7 +142,7 @@ Related Projects Open License ============ -Verilator is Copyright 2003-2023 by Wilson Snyder. (Report bugs to +Verilator is Copyright 2003-2024 by Wilson Snyder. (Report bugs to `Verilator Issues `_.) Verilator is free software; you can redistribute it and/or modify it under diff --git a/bin/verilator b/bin/verilator index 92ba9dde5..56e4008b3 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1,7 +1,7 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -501,7 +501,7 @@ description of these arguments. The latest version is available from L. -Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +Copyright 2003-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_ccache_report b/bin/verilator_ccache_report index 31e3b9cdb..43c4543f9 100755 --- a/bin/verilator_ccache_report +++ b/bin/verilator_ccache_report @@ -17,7 +17,7 @@ parser = argparse.ArgumentParser( For documentation see https://verilator.org/guide/latest/exe_verilator_ccache_report.html""", epilog= - """Copyright 2002-2023 by Wilson Snyder. This program is free software; you + """Copyright 2002-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_coverage b/bin/verilator_coverage index 19493d44b..ab28cc5b9 100755 --- a/bin/verilator_coverage +++ b/bin/verilator_coverage @@ -1,7 +1,7 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -188,7 +188,7 @@ L. The latest version is available from L. -Copyright 2003-2023 by Wilson Snyder. This program is free software; you +Copyright 2003-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_difftree b/bin/verilator_difftree index 63112a592..9bc590213 100755 --- a/bin/verilator_difftree +++ b/bin/verilator_difftree @@ -110,7 +110,7 @@ Verilator_difftree is used for debugging Verilator tree output files. It performs a diff between two files, or all files common between two directories, ignoring irrelevant pointer differences.""", epilog= - """Copyright 2005-2023 by Wilson Snyder. This program is free software; you + """Copyright 2005-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 60814b209..8f0c166e1 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -546,7 +546,7 @@ Verilator_gantt creates a visual representation to help analyze Verilator For documentation see https://verilator.org/guide/latest/exe_verilator_gantt.html""", epilog= - """Copyright 2018-2023 by Wilson Snyder. This program is free software; you + """Copyright 2018-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/bin/verilator_includer b/bin/verilator_includer index 08076063e..e704723d6 100755 --- a/bin/verilator_includer +++ b/bin/verilator_includer @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # pylint: disable=C0114,C0209 # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify the Verilator internals under the terms # of either the GNU Lesser General Public License Version 3 or the Perl # Artistic License Version 2.0. diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index cd72060df..e5487f127 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -181,7 +181,7 @@ in each Verilog block. For documentation see https://verilator.org/guide/latest/exe_verilator_profcfunc.html""", epilog= - """Copyright 2002-2023 by Wilson Snyder. This program is free software; you + """Copyright 2002-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/ci/ci-script.bash b/ci/ci-script.bash index 1ce2da5e5..ea2389faf 100755 --- a/ci/ci-script.bash +++ b/ci/ci-script.bash @@ -90,8 +90,8 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then export VERILATOR_TEST_NO_GPROF=1 # gprof is a bit different on FreeBSD, disable fi - # Run sanitize on Ubuntu 20.04 only - [ "$CI_RUNS_ON" = 'ubuntu-20.04' ] && [ "$CI_M32" = "" ] && sanitize='--sanitize' || sanitize='' + # Run sanitize on Ubuntu 22.04 only + [ "$CI_RUNS_ON" = 'ubuntu-22.04' ] && [ "$CI_M32" = "" ] && sanitize='--sanitize' || sanitize='' # Run the specified test ccache -z diff --git a/ci/docker/buildenv/Dockerfile b/ci/docker/buildenv/Dockerfile index 3e3fbe177..385e0b088 100644 --- a/ci/docker/buildenv/Dockerfile +++ b/ci/docker/buildenv/Dockerfile @@ -8,6 +8,16 @@ FROM ubuntu:22.04 +# Create the user +RUN groupadd verilator \ + && useradd -g verilator -m verilator -s /bin/bash \ + && apt-get update \ + && apt-get install --no-install-recommends -y sudo \ + && apt-get clean \ + && rm -rf /var/lib/apt/lists/* \ + && echo verilator ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/verilator \ + && chmod 0440 /etc/sudoers.d/verilator + RUN apt-get update \ && DEBIAN_FRONTEND=noninteractive \ apt-get install --no-install-recommends -y \ @@ -33,7 +43,6 @@ RUN apt-get update \ perl \ python3 \ wget \ - zlibc \ zlib1g \ zlib1g-dev \ && apt-get clean \ @@ -52,6 +61,8 @@ COPY build.sh /tmp/build.sh ENV VERILATOR_AUTHOR_SITE=1 +USER verilator + WORKDIR /work ENTRYPOINT [ "/tmp/build.sh" ] diff --git a/ci/docker/buildenv/README.rst b/ci/docker/buildenv/README.rst index e131917ac..1bb317e47 100644 --- a/ci/docker/buildenv/README.rst +++ b/ci/docker/buildenv/README.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Verilator Build Docker Container diff --git a/ci/docker/run/README.rst b/ci/docker/run/README.rst index db9d0de1d..347af0482 100644 --- a/ci/docker/run/README.rst +++ b/ci/docker/run/README.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Verilator Executable Docker Container diff --git a/codecov.yml b/codecov.yml index a6705db0a..c03de64cb 100644 --- a/codecov.yml +++ b/codecov.yml @@ -1,6 +1,6 @@ # DESCRIPTION: codecov.io config # -# Copyright 2020-2023 by Wilson Snyder. This program is free software; you +# Copyright 2020-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/configure.ac b/configure.ac index 17c4b15d9..cb82e3e7b 100644 --- a/configure.ac +++ b/configure.ac @@ -1,6 +1,6 @@ # DESCRIPTION: Process this file with autoconf to produce a configure script. # -# Copyright 2003-2023 by Wilson Snyder. Verilator is free software; you +# Copyright 2003-2024 by Wilson Snyder. Verilator is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @@ -10,7 +10,7 @@ # Then 'make maintainer-dist' #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[5.018 2023-10-30], +AC_INIT([Verilator],[5.020 2024-01-01], [https://verilator.org], [verilator],[https://verilator.org]) @@ -354,7 +354,7 @@ AC_SUBST(CFG_CXXFLAGS_PROFILE) # Macros work such that first option that passes is the one we take # Currently enable c++17/c++14 due to packaged SystemC dependency # c++17 is the newest that Verilator is regularly tested to support -# c++11 is the oldest that Verilator supports +# c++14 is the oldest that Verilator supports # gnu is required for Cygwin to compile verilated.h successfully #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++20) #_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++20) @@ -362,8 +362,6 @@ _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++17) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++17) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++14) _MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++14) -_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=gnu++11) -_MY_CXX_CHECK_SET(CFG_CXXFLAGS_STD_NEWEST,-std=c++11) AC_SUBST(CFG_CXXFLAGS_STD_NEWEST) # Flags for compiling Verilator internals including parser, and Verilated files @@ -521,14 +519,14 @@ _MY_LDLIBS_CHECK_IFELSE( fi]) AC_SUBST(CFG_LIBS) -# Need C++11 at least -#Alternative: AX_CXX_COMPILE_STDCXX([11]) +# Need C++14 at least +#Alternative: AX_CXX_COMPILE_STDCXX([14]) AC_DEFUN([_MY_CXX_CHECK_CXX_VER], - [# _MY_CXX_CHECK_CXX_VER(flag) -- Check if compiler runs C++11 + [# _MY_CXX_CHECK_CXX_VER(flag) -- Check if compiler runs C++14 # Set $_my_result AC_LINK_IFELSE( [AC_LANG_PROGRAM([#include -#if (__cplusplus < 201103L) +#if (__cplusplus < 201402L) # error "Too old" #endif ], [[ ]])], @@ -544,13 +542,13 @@ AC_DEFUN([_MY_CXX_CHECK_CXX_VER], # Add $CFG_CXXFLAGS_STD only if can't compile correctly otherwise, # as adding std= when not needed can cause errors with the C++ std library. CFG_CXXFLAGS_STD=$CFG_CXXFLAGS_STD_NEWEST -AC_MSG_CHECKING(whether $CXX supports C++11) +AC_MSG_CHECKING(whether $CXX supports C++14) _MY_CXX_CHECK_CXX_VER() AC_MSG_RESULT($_my_result) if test "$_my_result" = "no" ; then CXXFLAGS="$CXXFLAGS $CFG_CXXFLAGS_STD" CFG_CXX_FLAGS_CMAKE="$CFG_CXX_FLAGS_CMAKE $CFG_CXXFLAGS_STD" - AC_MSG_CHECKING(whether $CXX supports C++11 with $CFG_CXXFLAGS_STD) + AC_MSG_CHECKING(whether $CXX supports C++14 with $CFG_CXXFLAGS_STD) _MY_CXX_CHECK_CXX_VER() AC_MSG_RESULT($_my_result) else @@ -560,9 +558,9 @@ else fi if test "$_my_result" = "no" ; then AC_MSG_NOTICE([[]]) - AC_MSG_ERROR([[the $CXX compiler appears to not support C++11. + AC_MSG_ERROR([[the $CXX compiler appears to not support C++14. -Verilator requires a C++11 or newer compiler.]]) +Verilator requires a C++14 or newer compiler.]]) fi AC_SUBST(CFG_CXXFLAGS_STD) diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 44dfd678c..522941a52 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -26,6 +26,7 @@ Conor McCullough Dan Petrisko Daniel Bates David Horton +David Ledger David Metz David Stanford David Turner @@ -78,12 +79,14 @@ Jesse Taube Jevin Sweval Jiacheng Qian Jiamin Zhu +Jinyan Xu Jiuyang Liu Joey Liu John Coiner John Demme John Wehle Jonathan Drolet +Jordan McConnon Jose Loyola Josep Sans Joseph Nwabueze @@ -141,6 +144,7 @@ Piotr Binkowski Qingyao Sun Quentin Corradi Rafal Kapuscik +Rasfunk Raynard Qiao Richard Myers Risto Pejašinović diff --git a/docs/Makefile b/docs/Makefile index 3a44a656a..70ebe1da3 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -5,7 +5,7 @@ # # Code available from: https://verilator.org # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/docs/README.rst b/docs/README.rst new file mode 100644 index 000000000..3e5949f15 --- /dev/null +++ b/docs/README.rst @@ -0,0 +1,21 @@ +Verilator Documentation +======================= + +This folder contains sources for Verilator documentation. + +For formatted documentation see: + +- `Verilator README `_ + +- `Verilator installation and package directory structure + `_ + +- `Verilator manual (HTML) `_, + or `Verilator manual (PDF) `_ + +- `Subscribe to Verilator announcements + `_ + +- `Verilator forum `_ + +- `Verilator issues `_ diff --git a/docs/bin/vl_sphinx_extract b/docs/bin/vl_sphinx_extract index b607bd9d0..6762d7886 100755 --- a/docs/bin/vl_sphinx_extract +++ b/docs/bin/vl_sphinx_extract @@ -40,7 +40,7 @@ parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, description="""Read a file and extract documentation data.""", epilog= - """ Copyright 2021-2023 by Wilson Snyder. This package is free software; + """ Copyright 2021-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/docs/bin/vl_sphinx_fix b/docs/bin/vl_sphinx_fix index 780250d44..51eda1c4c 100755 --- a/docs/bin/vl_sphinx_fix +++ b/docs/bin/vl_sphinx_fix @@ -55,7 +55,7 @@ parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, description="""Post-process Sphinx HTML.""", epilog= - """ Copyright 2021-2023 by Wilson Snyder. This package is free software; + """ Copyright 2021-2024 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/docs/guide/changes.rst b/docs/guide/changes.rst index 315d2abea..c9f86a5c1 100644 --- a/docs/guide/changes.rst +++ b/docs/guide/changes.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 **************** diff --git a/docs/guide/conf.py b/docs/guide/conf.py index e8d5c0234..0bb6097a7 100644 --- a/docs/guide/conf.py +++ b/docs/guide/conf.py @@ -1,7 +1,7 @@ # pylint: disable=C0103,C0114,C0116,C0301,E0402,W0622 # # Configuration file for Verilator's Sphinx documentation builder. -# Copyright 2003-2023 by Wilson Snyder. +# Copyright 2003-2024 by Wilson Snyder. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # # This file only contains overridden options. For a full list: diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index e66fb938d..9d677c23a 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Connecting: diff --git a/docs/guide/contributing.rst b/docs/guide/contributing.rst index 215b58a83..d8f6dc35e 100644 --- a/docs/guide/contributing.rst +++ b/docs/guide/contributing.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******************************* diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst index 2af72be9d..ff223257a 100644 --- a/docs/guide/contributors.rst +++ b/docs/guide/contributors.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ************************ @@ -27,107 +27,137 @@ Alliance `_, `Antmicro Ltd `_ and `Shunyao CAD `_. Previous major corporate sponsors of Verilator, by providing significant -contributions of time or funds include: Atmel Corporation, Cavium -Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., -Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune -Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc., -SiCortex Inc, and Shunyao CAD. +contributions of time or funds include: Antmicro Ltd., Atmel Corporation, +Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., Hicamp +Systems, Intel Corporation, Marvell Inc., Mindspeed Technologies Inc., +MicroTune Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus +Networks Inc., SiCortex Inc, Shunyao CAD, and Western Digital Inc. -The contributors of major functionality are: Krzysztof -Bieganski, Byron Bradley, Jeremy Bennett, Lane Brooks, John Coiner, Duane -Galbi, Geza Lore, Todd Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, -and Wilson Snyder. Major testers included Jeff Dutton, Jonathon Donaldson, -Ralf Karge, David Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, -Sebastien Van Cauwenberghe, Gene Weber, and Clifford Wolf. +The contributors of major functionality are: Jeremy Bennett, Krzysztof +Bieganski, Byron Bradley, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, +Todd Strader, Yutetsu Takatsukasa, Stefan Wallentowitz, Paul Wasson, Jie +Xu, and Wilson Snyder. Some of the people who have provided ideas, and feedback for Verilator include: -David Addison, Tariq B. Ahmad, Nikana Anastasiadis, Vasu Arasanipalai, Jens -Arm, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew Barr, Geoff -Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael Berman, Jean -Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof Bieganski, -David Binderman, Piotr Binkowski, Johan Bjork, David Black, Tymoteusz -Blazejczyk, Daniel Bone, Gregg Bouchard, Christopher Boumenot, Nick Bowler, -Byron Bradley, Bryan Brady, Maarten De Braekeleer, Charlie Brej, J Briquet, -Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, Tony Bybell, Iru -Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal Casey, Alex -Chadwick, Marcel Chang, Aliaksei Chapyzhenka, Guokai Chen, Terry Chen, -Yi-Chung Chen, Enzo Chi, Robert A. Clark, Ryan Clarke, Allan Cochrane, John -Coiner, Keith Colbert, Gianfranco Costamagna, Sean Cross, George Cuan, Joe -DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh Das, Bernard Deadman, -John Demme, Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben -Diez, Danny Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Larry -Doolittle, Sebastian Dressler, Jonathan Drolet, Alex Duller, Jeff Dutton, -Tomas Dzetkulic, Usuario Eda, Charles Eddleston, Chandan Egbert, Joe Eiler, -Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Robert Farrell, Eugen -Fekete, Fabrizio Ferrandi, Udi Finkelstein, Brian Flachs, Bill Flynn, -Andrea Foletto, Bob Fredieu, Duane Galbi, Mostafa Gamal, Benjamin Gartner, -Christian Gelinek, Richard E George, Peter Gerst, Glen Gibb, Michael -Gielda, Barbara Gigerl, Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam -Gladstone, Mariusz Glebocki, Andrew Goessling, Amir Gonnen, Chitlesh -Goorah, Tomasz Gorochowik, Kai Gossner, Sergi Granell, Al Grant, Nathan -Graybeal, Alexander Grobman, Graham Rushton, Xuan Guo, Driss Hafdi, Neil -Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto, -Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry, Stephen -Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki -Honda, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath, Jae -Hossell, Kuoping Hsu, Teng Huang, Steven Hugg, Alan Hunter, James -Hutchinson, Ehab Ibrahim, Edgar E. Iglesias, Jamie Iles, Vighnesh Iyer, Ben -Jackson, Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong, -Iztok Jeras, Alexandre Joannou, James Johnson, Christophe Joly, Franck -Jullien, James Jung, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand +David Addison, Tariq B. Ahmad, Nikana Anastasiadis, John David Anglin, +Frederic Antonin, Hans Van Antwerpen, Vasu Arasanipalai, Jens Arm, Rohan +Arshid, Gökçe Aydos, Adam Bagley, Sharad Bagri, Robert Balas, Marco +Balboni, Matthew Ballance, Andrew Bardsley, Ilya Barkov, Matthew Barr, +Geoff Barrett, Kaleb Barrett, Daniel Bates, Julius Baxter, Michael Berman, +Jean Berniolles, Victor Besyakov, Narayan Bhagavatula, Moinak +Bhattacharyya, Kritik Bhimani, David Biancolin, David Binderman, Piotr +Binkowski, Johan Björk, David Black, Tymoteusz Blazejczyk, Scott Bleiweiss, +David van der Bokke, Daniel Bone, Guy Bonneau, Krzysztof Boroński, Gregg +Bouchard, Christopher Boumenot, Nick Bowler, Bryan Brady, Maarten De +Braekeleer, Charlie Brej, J Briquet, John Brownlee, KC Buckenmaier, Jeff +Bush, Lawrence Butcher, Tony Bybell, Iru Cai, Ted Campbell, Anthony Campos, +Chris Candler, Lauren Carlson, Gregory Carver, Donal Casey, Sebastien Van +Cauwenberghe, Alex Chadwick, Greg Chadwick, Marcel Chang, Aliaksei +Chapyzhenka, Chih-Mao Chen, Guokai Chen, Terry Chen, Yi-Chung Chen, Yurii +Cherkasov, Hennadii Chernyshchyk, Enzo Chi, Robert A. Clark, Ryan Clarke, +Allan Cochrane, Keith Colbert, Quentin Corradi, Nassim Corteggiani, +Gianfranco Costamagna, February Cozzocrea, Sean Cross, George Cuan, Michal +Czyz, Joe DErrico, Jim Dai, Lukasz Dalek, Laurens van Dam, Gunter +Dannoritzer, Ashutosh Das, Julian Daube, Bernard Deadman, Peter Debacker, +John Demme, Mike Denio, John Deroo, Philip Derrick, Aadi Desai, John +Dickol, Ruben Diez, Danny Ding, Jacko Dirks, Ivan Djordjevic, Brad Dobbie, +Paul Donahue, Jonathon Donaldson, Anthony Donlon, Caleb Donovick, Larry +Doolittle, Leendert van Doorn, Sebastian Dressler, Jonathan Drolet, Maciej +Dudek, Alex Duller, Jeff Dutton, Tomas Dzetkulic, Usuario Eda, Charles +Eddleston, Chandan Egbert, Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, +Mats Engstrom, Robert Farrell, Julien Faucher, Olivier Faure, Eugen Fekete, +Fabrizio Ferrandi, Udi Finkelstein, Brian Flachs, Bill Flynn, Andrea +Foletto, Alex Forencich, Aurelien Francillon, Bob Fredieu, Manuel +Freiberger, Mostafa Gamal, Vito Gamberini, Mostafa Garnal, Benjamin +Gartner, Christian Gelinek, Richard E George, Peter Gerst, Glen Gibb, +Michael Gielda, Barbara Gigerl, Nimrod Gileadi, Shankar Giri, Dan +Gisselquist, Petr Gladkikh, Sam Gladstone, Mariusz Glebocki, Embedded Go, +Andrew Goessling, Amir Gonnen, Chitlesh Goorah, Tomasz Gorochowik, Kai +Gossner, Tarik Graba, Sergi Granell, Al Grant, Nathan Graybeal, Alexander +Grobman, Qian Gu, Xuan Guo, Prabhat Gupta, Driss Hafdi, Neil Hamilton, +James Hanlon, Tang Haojin, Øyvind Harboe, Jannis Harder, David Harris, +Junji Hashimoto, Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert +Henry, Stephen Henry, Sebastian Hesselbarth, David Hewson, Jamey Hicks, +Joel Holdsworth, Andrew Holme, Peter Holmes, Hiroki Honda, Alex Hornung, +Pierre-Henri Horrein, David Horton, Peter Horvath, Jae Hossell, Kuoping +Hsu, Teng Huang, Steven Hugg, Huanghuang Zhou, Alan Hunter, James +Hutchinson, Tim Hutt, Ehab Ibrahim, Edgar E. Iglesias, Shahid Ikram, Jamie +Iles, Vighnesh Iyer, Ben Jackson, Daniel Jacques, Shareef Jalloq, Marlon +James, Krzysztof Jankowski, Eyck Jentzsch, HyungKi Jeong, Iztok Jeras, +Alexandre Joannou, James Johnson, Christophe Joly, Justin Jones, +William D. Jones, Larry Darryl Lee Jr., Franck Jullien, James Jung, +Yoshitomo Kaneda, Mike Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf Karge, Per Karlsson, Dan Katz, Sol Katzman, Ian -Kennedy, Michael Killough, Sun Kim, Jonathan Kimmitt, Olof Kindgren, Kevin -Kiningham, Dan Kirkham, Aleksander Kiryk, Sobhan Klnv, Gernot Koch, Jack -Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, Will -Korteland, Wojciech Koszek, Varun Koyyalagunta, Arkadiusz Kozdra, Markus -Krause, David Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok, -Charles Eric LaForest, Ed Lander, Steve Lang, Stephane Laurent, Walter -Lavino, Christian Leber, Larry Lee, Yoda Lee, Michaël Lefebvre, Igor Lesik, -John Li, Eivind Liland, Yu Sheng Lin, Charlie Lind, Andrew Ling, Jiuyang -Liu, Paul Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan -Ludwig, Dan Lussier, Fred Ma, Duraid Madina, Affe Mao, Julien Margetts, +Kennedy, Ami Keren, Michael Killough, Sun Kim, Jonathan Kimmitt, Olof +Kindgren, Kevin Kiningham, Cameron Kirk, Dan Kirkham, Aleksander Kiryk, +Sobhan Klnv, Gernot Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Steve +Kolecki, Brett Koonce, Will Korteland, Andrei Kostovski, Wojciech Koszek, +Varun Koyyalagunta, Arkadiusz Kozdra, Markus Krause, David Kravitz, Adam +Krolnik, Roland Kruse, Mahesh Kumashikar, Andreas Kuster, Sergey Kvachonok, +Charles Eric LaForest, Kevin Laeufer, Ed Lander, Steve Lang, Pierre +Laroche, Stephane Laurent, Walter Lavino, Christian Leber, David Ledger, +Alex Lee, Larry Lee, Yoda Lee, Michaël Lefebvre, Dag Lem, Igor Lesik, John +Li, Kay Li, Zixi Li, Davide Libenzi, Nandor Licker, Eivind Liland, Ícaro +Lima, Kevin Lin, Yu-Sheng Lin, Charlie Lind, Andrew Ling, Jiuyang Liu, Joey +Liu, Paul Liu, Derek Lockhart, Jake Longo, Arthur Low, Jose Loyola, Stefan +Ludwig, Dan Lussier, Konstantin Lübeck, Fred Ma, Liwei Ma, Duraid Madina, +Oleh Maksymenko, Affe Mao, Julien Margetts, Chick Markley, Alexis Marquet, Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Adrien Le Masle, -Yves Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot -Mednick, David Metz, Wim Michiels, Miodrag Milanovic, Kevin Millis, Wai Sum -Mong, Peter Monsson, Sean Moore, Dennis Muhlestein, John Murphy, Matt -Myers, Nathan Myers, Richard Myers, Dimitris Nalbantis, Peter Nelson, Bob -Newgard, Rachit Nigam, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack, -Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz, Aleksander Osman, -Don Owen, James Pallister, Vassilis Papaefstathiou, Brad Parker, Morten -Borup Petersen, Dan Petrisko, Maciej Piechotka, David Pierce, Cody -Piersall, Michael Platzer, Dominic Plunkett, David Poole, Mike Popoloski, -Roman Popov, Rich Porter, Stefan Post, Niranjan Prabhu, Damien Pretet, Usha -Priyadharshini, Mark Jackson Pulver, Prateek Puri, Marshal Qiao, Nandu Raj, -Kamil Rakoczy, Danilo Ramos, Drew Ranck, Chris Randall, Anton Rapp, Josh -Redford, Odd Magne Reitan, Frederic Requin, Dustin Richmond, Samuel Riedel, -Alberto Del Rio, Eric Rippey, Oleg Rodionov, Ludwig Rogiers, Paul Rolfe, -Arjen Roodselaar, Tobias Rosenkranz, Ryszard Rozak, Huang Rui, Graham -Rushton, Jan Egil Ruud, Denis Rystsov, John Sanguinetti, Martin Schmidt, -Julie Schwartz, Galen Seitz, Joseph Shaker, Salman Sheikh, Hao Shi, Mike -Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan Shupei, Anderson Ignacio -da Silva, Rodney Sinclair, Ameya Vikram Singh, Steven Slatter, Mladen -Slijepcevic, Brian Small, Garrett Smith, Tim Snyder, Wilson Snyder, Maciej +Yves Mathieu, Vladimir Matveyenko, Patrick Maupin, Stan Mayer, Conor +McCullough, Jason McMullan, Elliot Mednick, Yuan Mei, Andy Meier, +Rodrigo A. Melo, Benjamin Menküc, Jake Merdich, David Metz, Wim Michiels, +Miodrag Milanović, Darryl Miles, Kevin Millis, Andrew Miloradovsky, Wai Sum +Mong, Peter Monsson, Sean Moore, Stuart Morris, Dennis Muhlestein, John +Murphy, Matt Myers, Nathan Myers, Richard Myers, Alex Mykyta, Dimitris +Nalbantis, Peter Nelson, Felix Neumärker, Bob Newgard, Cong Van Nguyen, +Rachit Nigam, Toru Niina, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack, +Mark Nodine, Michael Nolan, Andrew Nolte, Joseph Nwabueze, Kuba Ober, +Andreas Olofsson, Baltazar Ortiz, Aleksander Osman, Don Owen, Tim Paine, +Deepa Palaniappan, James Pallister, Vassilis Papaefstathiou, Sanggyu Park, +Brad Parker, Risto Pejašinović, Morten Borup Petersen, Dan Petrisko, Wesley +Piard, Maciej Piechotka, David Pierce, Cody Piersall, T. Platz, Michael +Platzer, Dominic Plunkett, David Poole, Michael Popoloski, Roman Popov, +Aylon Chaim Porat, Oron Port, Rich Porter, Rick Porter, Stefan Post, +Niranjan Prabhu, Damien Pretet, Harald Pretl, Bill Pringlemeir, Usha +Priyadharshini, Mark Jackson Pulver, Prateek Puri, Jiacheng Qian, Marshal +Qiao, Raynard Qiao, Yujia Qiao, Jasen Qin, Frank Qiu, Nandu Raj, Kamil +Rakoczy, Danilo Ramos, Drew Ranck, Chris Randall, Anton Rapp, Josh Redford, +Odd Magne Reitan, Frédéric Requin, Dustin Richmond, Samuel Riedel, Alberto +Del Rio, Eric Rippey, Oleg Rodionov, Ludwig Rogiers, Paul Rolfe, Michail +Rontionov, Arjen Roodselaar, Tobias Rosenkranz, Yernagula Roshit, Ryszard +Rozak, Huang Rui, Graham Rushton, Jan Egil Ruud, Denis Rystsov, Pawel +Sagan, Robert Sammelson, John Sanguinetti, Josep Sans, Luca Sasselli, +Martin Scharrer, Martin Schmidt, Julie Schwartz, Galen Seitz, Joseph +Shaker, Mark Shaw, Salman Sheikh, Zhou Shen, Hao Shi, James Shi, Michael +Shinkarovsky, Rafael Shirakawa, Jeffrey Short, S Shuba, Fan Shupei, Ethan +Sifferman, Anderson Ignacio da Silva, Rodney Sinclair, Ameya Vikram Singh, +Sanjay Singh, Frans Skarman, Nate Slager, Steven Slatter, Mladen +Slijepcevic, Brian Small, Garrett Smith, Gus Smith, Tim Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, Flavien Solt, Wei Song, Trefor Southwell, Martin Stadler, Art Stamness, David Stanford, John Stevenson, -Pete Stevenson, Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, -Sven Stucki, Howard Su, Emerson Suguimoto, Gene Sullivan, Qingyao Sun, -Renga Sundararajan, Gustav Svensk, Rupert Swarbrick, Yutetsu Takatsukasa, -Thierry Tambe, Drew Taussig, Jose Tejada, Peter Tengstrand, Wesley -Terpstra, Rui Terra, Stefan Thiede, Gary Thomas, Ian Thompson, Kevin -Thompson, Mike Thyer, Hans Tichelaar, Viktor Tomov, Steve Tong, Topa -Topino, Alex Torregrosa, Michael Tresidder, David Turner, Neil Turton, Mike -Urbach, Hans Van Antwerpen, Sebastien Van Cauwenberghe, Laurens van Dam, -Leendert van Doorn, Cong Van Nguyen, Jan Van Winkel, Srini Vemuri, Yuri -Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan -Wallentowitz, Shawn Wang, Zhanglei Wang, Paul Wasson, Greg Waters, Thomas -Watts, Eugene Weber, David Welch, Thomas J Whatson, Martin Whitaker, Marco -Widmer, Leon Wildman, Daniel Wilkerson, Gerald Williams, Trevor Williams, -Jeff Winston, Joshua Wise, Clifford Wolf, Tobias Wolfel, Johan Wouters, -Paul Wright, Junyi Xi, Ding Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke -Yang, Amir Yazdanbakhsh, Keyi Zhang, and Xi Zhang. +Pete Stevenson, Patrick Stewart, Rob Stoddard, Tood Strader, John Stroebel, +Ray Strouble, Sven Stucki, Howard Su, Emerson Suguimoto, Gene Sullivan, +Qingyao Sun, Renga Sundararajan, Kuba Sunderland-Ober, Gustav Svensk, +Rupert Swarbrick, Jevin Sweval, Shinya T-Y, Thierry Tambe, Jesse Taube, +Drew Taussig, Jose Tejada, Sören Tempel, Peter Tengstrand, Wesley Terpstra, +Rui Terra, Stefan Thiede, Justin Thiel, Gary Thomas, Ian Thompson, Kevin +Thompson, Mike Thyer, Hans Tichelaar, Tudor Timi, Viktor Tomov, Steve Tong, +Topa Topino, Àlex Torregrosa, Topa Tota, Michael Tresidder, Lenny Truong, +David Turner, Neil Turton, Hideto Ueno, Mike Urbach, Joel Vandergriendt, +Srini Vemuri, Srinivasan Venkataramanan, Yuri Victorovich, Ivan Vnučec, +Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Johannes Walter, CY +Wang, Chuxuan Wang, Shawn Wang, Zhanglei Wang, Greg Waters, Thomas Watts, +Eugene Weber, John Wehle, Tianrui Wei, David Welch, Thomas J Whatson, +Martin Whitaker, Marco Widmer, Leon Wildman, Daniel S. Wilkerson, Daniel +Wilkerson, Gerald Williams, Trevor Williams, Don Williamson, Jan Van +Winkel, Jeff Winston, Joshua Wise, Clifford Wolf, Johan Wouters, Paul +Wright, Tobias Wölfel, Junyi Xi, Ding Xiaoliang, Liu Xiaoyi, Mandy Xu, +Shanshan Xu, Yinan Xu, SU YANG, Felix Yan, Luke Yang, Amir Yazdanbakhsh, +Chentai (Seven) Yuan, Florian Zaruba, Mat Zeno, Keyi Zhang, Xi Zhang, Yike +Zhou, Jiamin Zhu. Thanks to them, and all those we've missed mentioning above, and to those whom have wished to remain anonymous. diff --git a/docs/guide/copyright.rst b/docs/guide/copyright.rst index 2eba06d51..5eb6d516c 100644 --- a/docs/guide/copyright.rst +++ b/docs/guide/copyright.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ********* @@ -8,7 +8,7 @@ Copyright The latest version of Verilator is available from `https://verilator.org `_. -Copyright 2003-2023 by Wilson Snyder. This program is free software; you +Copyright 2003-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst index df4c7d2ac..149cbd370 100644 --- a/docs/guide/deprecations.rst +++ b/docs/guide/deprecations.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Deprecations @@ -8,11 +8,8 @@ The following deprecated items are scheduled for future removal: C++11 compiler support Verilator currently requires a C++20 or newer compiler for timing, and a - C++11 or newer compiler for no-timing. - - Verilator will require C++14 or newer compilers for both compiling - Verilator and compiling Verilated models with --no-timing no sooner than - January 2023. + C++14 or newer compiler for both compiling Verilator and compiling + Verilated models with --no-timing. Verilator will require C++20 or newer compilers for both compiling Verilator and compiling all Verilated models no sooner than January 2025. @@ -21,19 +18,3 @@ C++11 compiler support Verilator currently regresses both 64-bit and 32-bit pointer modes (GCC's `-m64` and `-m32`). Support for 32-bit `-m32` mode will be deprecated no sooner than January 2024. - -Option `-O` - The debug `-O` options have been replaced with - `-fno-` debug options to match GCC. The old options are - planned for removal no sooner than June 2023. - -Option `--prof-threads` - The `--prof-threads` option has been superseded by the `--prof-exec` and - `--prof-pgo` options and is planned for removal no sooner than April 2023. - -Verilated model options `+verilator+prof+threads+*` - The `+verilator+prof+threads+start`, `+verilator+prof+threads+window` and - `+verilator+prof+threads+file` options have been superseded by the - `+verilator+prof+exec+start`, `+verilator+prof+exec+window` and - `+verilator+prof+exec+file` options respectively and are planned for removal - no sooner than April 2023. diff --git a/docs/guide/environment.rst b/docs/guide/environment.rst index 4cfe4c535..3afb8bf2f 100644 --- a/docs/guide/environment.rst +++ b/docs/guide/environment.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Environment @@ -7,21 +7,6 @@ Environment This section describes the environment variables used by Verilator and associated programs. -.. option:: AR - - Optionally overrides the default :command:`ar` (archive) binary used by - the Verilated makefiles. If AR is not set, the version found at - configure time is used. - -.. option:: CXX - - Optionally overrides the default compiler binary used by the Verilated - makefiles. If CXX is not set, the version found at configure time is - used. Note the default flags passed to the compiler are determined at - configuration time, so changing the CXX compiler version using this - variable, as opposed to passing it at configuration time, may not give - desired results. - .. option:: LD_LIBRARY_PATH A generic Linux/OS variable specifying what directories have shared @@ -44,18 +29,12 @@ associated programs. .. option:: OBJCACHE Optionally specifies a caching or distribution program to place in front - of all runs of the C++ compiler. For example, "ccache". If using + of all runs of the C++ compiler. For example, "ccache" or "sccache". If using :command:`distcc` or :command:`icecc`/:command:`icecream`, they would generally be run under :command:`ccache`; see the documentation for those programs. If OBJCACHE is not set, and at configure time ccache was present, ccache will be used as a default. -.. option:: PYTHON3 - - Optionally overrides the default :command:`python3` binary used by the - Verilated makefiles. If PYTHON3 is not set, the version found at - configure time is used. - .. option:: SYSTEMC Deprecated. Used only if :option:`SYSTEMC_INCLUDE` or @@ -138,3 +117,46 @@ associated programs. ``VERILATOR_ROOT`` to point to the new version. See :ref:`Installation` for more details. + + +Make Variables +============== + +This section describes the make variables used by Verilator. These may be +set by passing them to make e.g. ``make CXX=my-gcc ...``. + +.. option:: AR + + Optionally overrides the default :command:`ar` (archive) binary used by + the Verilated makefiles. If AR is not set, the version found at + configure time is used. + +.. option:: CXX + + Optionally overrides the default compiler binary used by the Verilated + makefiles. If CXX is not set, the version found at configure time is + used. Note the default flags passed to the compiler are determined at + configuration time, so changing the CXX compiler version using this + variable, as opposed to passing it at configuration time, may not give + desired results. + +.. option:: LINK + + Optionally overrides the default linker binary used by the Verilated + makefiles. If LINK is not set, the version found at configure time is + used. Note the default flags passed to the linker are determined at + configuration time, so changing the LINK version using this variable, as + opposed to passing it at configuration time, may not give desired + results. + +.. option:: PERL + + Optionally overrides the default :command:`perl` binary used by the + Verilated makefiles. If PERL is not set, the version found at configure + time, and compiled into the Verilator binary, is used. + +.. option:: PYTHON3 + + Optionally overrides the default :command:`python3` binary used by the + Verilated makefiles. If PYTHON3 is not set, the version found at + configure time is used. diff --git a/docs/guide/example_binary.rst b/docs/guide/example_binary.rst index 4a238c922..43f895b9b 100644 --- a/docs/guide/example_binary.rst +++ b/docs/guide/example_binary.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Example Create-Binary Execution: diff --git a/docs/guide/example_cc.rst b/docs/guide/example_cc.rst index 6e5d7f465..11c7d706f 100644 --- a/docs/guide/example_cc.rst +++ b/docs/guide/example_cc.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Example C++ Execution: diff --git a/docs/guide/example_common_install.rst b/docs/guide/example_common_install.rst index 916d7ce31..d7ddb0bab 100644 --- a/docs/guide/example_common_install.rst +++ b/docs/guide/example_common_install.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 First you need Verilator installed, see :ref:`Installation`. In brief, if diff --git a/docs/guide/example_dist.rst b/docs/guide/example_dist.rst index b776ecdfd..4b15464b6 100644 --- a/docs/guide/example_dist.rst +++ b/docs/guide/example_dist.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Examples in the Distribution: diff --git a/docs/guide/example_sc.rst b/docs/guide/example_sc.rst index b482b1ffd..441c8e542 100644 --- a/docs/guide/example_sc.rst +++ b/docs/guide/example_sc.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Example SystemC Execution: diff --git a/docs/guide/examples.rst b/docs/guide/examples.rst index 7eca1c636..71b65ae97 100644 --- a/docs/guide/examples.rst +++ b/docs/guide/examples.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Examples: diff --git a/docs/guide/exe_sim.rst b/docs/guide/exe_sim.rst index f538d4836..7fbeaff0c 100644 --- a/docs/guide/exe_sim.rst +++ b/docs/guide/exe_sim.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Simulation Runtime Arguments: @@ -64,15 +64,18 @@ Summary: .. option:: +verilator+prof+threads+file+ - Deprecated. Alias for :vlopt:`+verilator+prof+exec+file+\` + Removed in 5.020. Was an alias for + :vlopt:`+verilator+prof+exec+file+\` .. option:: +verilator+prof+threads+start+ - Deprecated. Alias for :vlopt:`+verilator+prof+exec+start+\` + Removed in 5.020. Was an alias for + :vlopt:`+verilator+prof+exec+start+\` .. option:: +verilator+prof+threads+window+ - Deprecated. Alias for :vlopt:`+verilator+prof+exec+window+\` + Removed in 5.020. Was an alias for + :vlopt:`+verilator+prof+exec+window+\` .. option:: +verilator+prof+vlt+file+ diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 644d11557..3b580d197 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator Arguments @@ -1036,7 +1036,7 @@ Summary: .. option:: --prof-threads - Deprecated. Same as --prof-exec and --prof-pgo together. + Removed in 5.020. Was an alias for --prof-exec and --prof-pgo together. .. option:: --protect-ids @@ -1363,13 +1363,13 @@ Summary: Enable FST waveform tracing in the model. This overrides :vlopt:`--trace`. See also :vlopt:`--trace-threads` option. -.. option:: --trace-max-array *depth* +.. option:: --trace-max-array Rarely needed. Specify the maximum array depth of a signal that may be traced. Defaults to 32, as tracing large arrays may greatly slow traced simulations. -.. option:: --trace-max-width *width* +.. option:: --trace-max-width Rarely needed. Specify the maximum bit width of a signal that may be traced. Defaults to 256, as tracing large vectors may greatly slow @@ -1386,7 +1386,7 @@ Summary: format constraints, this may result in significantly slower trace times and larger trace files. -.. option:: --trace-threads *threads* +.. option:: --trace-threads Enable waveform tracing using separate threads. This is typically faster in simulation runtime but uses more total compute. This option only @@ -1427,12 +1427,12 @@ Summary: Rarely needed. Specifies the maximum number of loop iterations that may be unrolled. See also :option:`BLKLOOPINIT` warning. -.. option:: --unroll-stmts *statements* +.. option:: --unroll-stmts Rarely needed. Specifies the maximum number of statements in a loop for that loop to be unrolled. See also :option:`BLKLOOPINIT` warning. -.. option:: --unused-regexp *regexp* +.. option:: --unused-regexp Rarely needed. Specifies a simple regexp with \* and ? that, if a signal name matches, will suppress the :option:`UNUSED` warning. Defaults to @@ -1444,7 +1444,7 @@ Summary: into Verilator. (Similar to :command:`perl -V`.) See also :vlopt:`--getenv` option. -.. option:: -v *filename* +.. option:: -v Read the filename as a Verilog library. Any modules in the file may be used to resolve instances in the top-level module, otherwise, they are @@ -1481,7 +1481,7 @@ Summary: Enable the use of VPI and linking against the :file:`verilated_vpi.cpp` files. -.. option:: --waiver-output *filename* +.. option:: --waiver-output Generate a waiver file that contains all waiver statements to suppress the warnings emitted during this Verilator run. This, in particular, is diff --git a/docs/guide/exe_verilator_coverage.rst b/docs/guide/exe_verilator_coverage.rst index a9ae9a044..0ca163d89 100644 --- a/docs/guide/exe_verilator_coverage.rst +++ b/docs/guide/exe_verilator_coverage.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator_coverage diff --git a/docs/guide/exe_verilator_gantt.rst b/docs/guide/exe_verilator_gantt.rst index 75fbe0e03..6088154b2 100644 --- a/docs/guide/exe_verilator_gantt.rst +++ b/docs/guide/exe_verilator_gantt.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator_gantt diff --git a/docs/guide/exe_verilator_profcfunc.rst b/docs/guide/exe_verilator_profcfunc.rst index 900f7e2e2..815109dab 100644 --- a/docs/guide/exe_verilator_profcfunc.rst +++ b/docs/guide/exe_verilator_profcfunc.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 verilator_profcfunc diff --git a/docs/guide/executables.rst b/docs/guide/executables.rst index 11b1173a5..fee757f8a 100644 --- a/docs/guide/executables.rst +++ b/docs/guide/executables.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ********************************* diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index 26e1bc425..1583a5993 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******************* @@ -23,7 +23,8 @@ or "`ifdef`"'s may break other tools. .. option:: `error [string] - This will report an error when encountered, like C++'s #error. + This will report an error when the preprocessor emits it, similar to + C++'s #error. .. option:: `line diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst index d02559a7b..a6067eb61 100644 --- a/docs/guide/faq.rst +++ b/docs/guide/faq.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ****************************** @@ -220,12 +220,6 @@ This is done for you if you are using the Verilator :vlopt:`--binary` or You can call :code:`->trace()` on multiple Verilated objects with the same trace file if you want all data to land in the same output file. -When using SystemC 2.3, the SystemC library must have been built with the -experimental simulation phase callback-based tracing disabled. This is -disabled by default when building SystemC with its configure based build -system, but when building SystemC with CMake, you must pass -``-DENABLE_PHASE_CALLBACKS_TRACING=OFF`` to disable this feature. - How do I generate FST waveforms (traces) in C++ or SystemC? """"""""""""""""""""""""""""""""""""""""""""""""""""""""""" @@ -401,7 +395,7 @@ How do I get faster build times? * Use a recent compiler. Newer compilers tend to be faster. * Compile in parallel on many machines and use caching; see the web for the - ccache, distcc, and icecream packages. ccache will skip GCC runs between + ccache, sccache, distcc, or icecream packages. ccache will skip GCC runs between identical source builds, even across different users. If ccache was installed when Verilator was built, it is used, or see OBJCACHE environment variable to override this. Also see the diff --git a/docs/guide/files.rst b/docs/guide/files.rst index 219979350..ff400947b 100644 --- a/docs/guide/files.rst +++ b/docs/guide/files.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ***** @@ -50,9 +50,9 @@ For --cc/--sc, it creates: - Make include file with class names (from --make gmake) * - *{prefix}*\ _hier.mk - Make file for hierarchy blocks (from --make gmake) - * - *{prefix}*\ _hierMkArgs.f + * - *{prefix}*\ __hierMkArgs.f - Arguments for hierarchical Verilation (from --make gmake) - * - *{prefix}*\ _hierCMakeArgs.f + * - *{prefix}*\ __hierCMakeArgs.f - Arguments for hierarchical Verilation (from --make cmake) * - *{prefix}*\ .h - Model header @@ -145,6 +145,10 @@ After running Make, the C++ compiler may produce the following: - Intermediate objects * - *{prefix}*\ - Final executable (from --exe) + * - lib\ *{prefix}*\ .a + - Final archive (default lib mode) + * - libverilated.a + - Runtime for verilated model (default lib mode) * - *{prefix}*\ __ALL.a - Library of all Verilated objects * - *{prefix}*\ __ALL.cpp diff --git a/docs/guide/index.rst b/docs/guide/index.rst index e828272a8..7d6a3f1c8 100644 --- a/docs/guide/index.rst +++ b/docs/guide/index.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################### diff --git a/docs/guide/install-cmake.rst b/docs/guide/install-cmake.rst index 8da441329..2120ee951 100644 --- a/docs/guide/install-cmake.rst +++ b/docs/guide/install-cmake.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _CMakeInstallation: diff --git a/docs/guide/install.rst b/docs/guide/install.rst index 33a90f92c..d1518e6d7 100644 --- a/docs/guide/install.rst +++ b/docs/guide/install.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Installation: diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst index 21b18914d..201f37fec 100644 --- a/docs/guide/languages.rst +++ b/docs/guide/languages.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 *************** diff --git a/docs/guide/overview.rst b/docs/guide/overview.rst index 101c97faa..3a6a8b7bd 100644 --- a/docs/guide/overview.rst +++ b/docs/guide/overview.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******** diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst index 2fc6bc5e3..aadf5deab 100644 --- a/docs/guide/simulating.rst +++ b/docs/guide/simulating.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 .. _Simulating: diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst index 7c1aa361b..2a22d3e37 100644 --- a/docs/guide/verilating.rst +++ b/docs/guide/verilating.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ********** @@ -7,9 +7,13 @@ Verilating Verilator may be used in five major ways: +* With the :vlopt:`--binary` option, Verilator will translate the design + into an executable, via generating C++ and compiling it. See + :ref:`Binary, C++ and SystemC Generation`. + * With the :vlopt:`--cc` or :vlopt:`--sc` options, Verilator will translate - the design into C++ or SystemC code, respectively. See :ref:`C++ and - SystemC Generation`. + the design into C++ or SystemC code, respectively. See :ref:`Binary, C++ + and SystemC Generation`. * With the :vlopt:`--lint-only` option, Verilator will lint the design to check for warnings but will not typically create any output files. @@ -24,13 +28,15 @@ Verilator may be used in five major ways: expanded. -.. _C++ and SystemC Generation: +.. _Binary, C++ and SystemC Generation: -C++ and SystemC Generation -========================== +Binary, C++ and SystemC Generation +================================== Verilator will translate a SystemVerilog design into C++ with the -:vlopt:`--cc` option, or into SystemC with the :vlopt:`--sc` option. +:vlopt:`--cc` option, or into SystemC with the :vlopt:`--sc` option. It +will translate into C++ and compile it into an executable binary with the +:vlopt:`--binary` option. When using these options: @@ -45,14 +51,19 @@ When using these options: The prefix is set with :vlopt:`--prefix`, or defaults to the name of the top module. -#. If :vlopt:`--exe` is used, Verilator creates makefiles to generate a - simulation executable, otherwise, it creates makefiles to generate an - archive (.a) containing the objects. +#. If :vlopt:`--binary` or :vlopt:`--main` is used, Verilator creates a C++ + top wrapper to read command line arguments, create the model, and + execute the model. -#. If :vlopt:`--build` option was used, it calls :ref:`GNU Make` or - :ref:`CMake` to build the model. +#. If :vlopt:`--binary` or :vlopt:`--exe` is used, Verilator creates + makefiles to generate a simulation executable, otherwise, it creates + makefiles to generate an archive (.a) containing the objects. -Once a model is built, it is then typically run, see :ref:`Simulating`. +#. If :vlopt:`--binary` or :vlopt:`--build` is used, it calls :ref:`GNU + Make` or :ref:`CMake` to build the model. + +Once a model is built, the next step is typically for the user to run it, +see :ref:`Simulating`. .. _Hierarchical Verilation: diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 0a85765c7..12e854f35 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -1,4 +1,4 @@ -.. Copyright 2003-2023 by Wilson Snyder. +.. Copyright 2003-2024 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ******************* diff --git a/docs/internals.rst b/docs/internals.rst index 30a27bb5e..b864badd4 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -1035,11 +1035,11 @@ Coding Conventions ================== -Compiler Version and C++11 +Compiler Version and C++14 -------------------------- -Verilator requires C11. Verilator does not require any newer versions, but -is maintained to build successfully with C14/C17/C20. +Verilator requires C14. Verilator does not require any newer versions, but +is maintained to build successfully with C17/C20. Indentation and Naming Style @@ -2237,7 +2237,7 @@ xsim_flags / xsim_flags2 / xsim_run_flags Distribution ============ -Copyright 2008-2023 by Wilson Snyder. Verilator is free software; you can +Copyright 2008-2024 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/docs/spelling.txt b/docs/spelling.txt index 0cfdd2f23..dfa90efdf 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -1,4 +1,5 @@ ABCp +Aadi Accellera Affe Aleksander @@ -13,21 +14,26 @@ Antonin Antwerpen Arasanipalai Arjen +Arshid Asciidoc Ashutosh Ast Atmel Aurelien Bagri +Balboni Baltazar Bardsley Benchmarking Berman Bhagavatula Bhattacharyya +Biancolin Binderman +Björk Bleiweiss Bogdan +Bonneau Bouchard Boumenot Brej @@ -41,20 +47,25 @@ Cai Cavium Cfuncs Chandan +Chentai +Cherkasov Chih Chitlesh Christophe Cochrane Conda Corteggiani +Cozzocrea Cuan Cygwin DErrico DFG Da +Dai Danilo Dannoritzer Das +Davide Dcache Deadman Debacker @@ -63,6 +74,7 @@ Defparams Denio Deprecations Deroo +Desai Dickol Diez Dimitris @@ -71,9 +83,11 @@ Djordjevic Dobbie Dockerfile Donal +Donovick Doorn Doxygen Dressler +Dudek Duraid Dutton Dzetkulic @@ -92,14 +106,19 @@ Enzo Eugen Fabrizio Faucher +Faure Fekete Ferrandi Flachs Flavien +Florian Foletto +Forencich Forker Francillon Fredieu +Freiberger +Frédéric GTKWave Galbi Gantt @@ -119,18 +138,23 @@ Goessling Gonnen Goorah Gossner +Graba Graphviz Graybeal Grobman Grulfen +Gu Gunter Guo Hao +Haojin Harboe Hashimoto Hayenga +Hesselbarth Hewson Hicamp +Hideto Hiroki Holdsworth Holme @@ -138,8 +162,10 @@ Homebrew Hornung Hossell Hsu +Hutt Hyperthreading Ibrahim +Ikram Iles Inlines Inout @@ -151,6 +177,7 @@ Jae Jalloq Jankowski Jannis +Jasen Jens Jeras Jiuyang @@ -166,6 +193,7 @@ Kahn Kai Kamendje Kandadi +Kaneda Kaplan Karge Karlsson @@ -181,6 +209,7 @@ Klnv Koenig Koh Kolecki +Konstantin Koonce Korteland Koszek @@ -192,17 +221,23 @@ Kumashikar Kuoping Kurachi Laeufer +Laroche Laurens Lavino Leber Leendert Lem Lesik +Libenzi +Licker Liland Liu +Liwei Lockhart Longo +Luca Lussier +Lübeck MMD MODDUP MTasks @@ -212,10 +247,15 @@ Mahesh Mahmoudy Makefile Makefiles +Maksymenko +Markley +Marquet Matveyenko Maupin Mdir Mednick +Mei +Melo Menküc Michail Michiels @@ -237,6 +277,7 @@ Mykyta NOUNOPTFLAT NaN Nalbantis +Nandor Narayan Nassim Nauticus @@ -247,16 +288,20 @@ Niranjan Nitza Noack Nodine +Ober Oleg Olof Olofsson +Oron Oyvind PLI Palaniappan Patricio Petr +Piard Piechotka Piersall +Platz Platzer Plunkett Popolon @@ -273,6 +318,8 @@ Priyadharshini Pullup Pulver Puri +Qin +Qiu Questa Rachit Ralf @@ -282,28 +329,37 @@ Reitan Renga Requin Rodionov +Rohan Rolfe Rontionov Roodselaar +Roshit Runtime Ruud Rystsov STandarD Salman +Sammelson +Sanggyu Sanguinetti Sanjay +Sasselli Scharrer Seitz +Shahid Shankar Shanshan Sharad Shareef +Shen Sheng Shi Shinkarovsky +Shinya Shirakawa Shuba Shunyao +Slager Slatter SoC Sobhan @@ -323,6 +379,7 @@ Stucki Su Suguimoto Sundararajan +Sunderland Suse Syms Synopsys @@ -330,6 +387,7 @@ SystemC SystemVerilog Takatsukasa Tambe +Tarik Tariq Tejada Tengstrand @@ -337,6 +395,7 @@ Terpstra Thiede Thierry Thyer +Tianrui Tichelaar Timi Tomov @@ -347,9 +406,11 @@ Trefor Tresidder Tri Tristate +Truong Turton UNOPTFLAT Ubixum +Ueno Uints Undefines Unsized @@ -358,6 +419,7 @@ Uselib Usha Usuario VERILATOR +Vandergriendt Vasu Vdeeptemp Vdly @@ -395,14 +457,20 @@ Wwarn XSim Xcelium Xiaoliang +Xiaoyi Xuan Xuanqi Yazdanbakhsh +Yernagula Yi Yike Yinan +Yoshitomo Yosys Yu +Yujia +Yurii +Zaruba Zhang abirkmanis accessor @@ -517,6 +585,7 @@ desassign destructor detections dev +devcontainer devel dir displayb @@ -675,6 +744,7 @@ libext libgoogle libsystemc libtcmalloc +libverilated linkers linter linux @@ -703,6 +773,7 @@ miree mis misconnected misconversion +misoptimized missized mk mno @@ -810,6 +881,7 @@ pvalue pwd py qrq +qrqiuren radix randc randcase @@ -843,6 +915,7 @@ sVerilator sawatzke sc scalared +sccache sccanf seg setuphold @@ -965,7 +1038,9 @@ vlt vltstd vluint vpi +vpiConstType vpiDefName +vpiInstance vpiLeftRange vpiModule vpiSize @@ -995,3 +1070,5 @@ ypq yurivict zdave Øyvind +Алексеевич +Исаак diff --git a/docs/xml.rst b/docs/xml.rst index 9d18a93d1..76c358edf 100644 --- a/docs/xml.rst +++ b/docs/xml.rst @@ -70,7 +70,7 @@ The XML document consists of 4 sections within the top level Distribution ============ -Copyright 2020-2023 by Wilson Snyder. Verilator is free software; you can +Copyright 2020-2024 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/include/verilated.cpp b/include/verilated.cpp index dd574a93e..4631e8644 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -107,16 +107,9 @@ thread_local Verilated::ThreadLocal Verilated::t_s; #ifndef VL_USER_FINISH ///< Define this to override the vl_finish function void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { - if (false && hier) {} + if (false && hier) {} // Unused argument VL_PRINTF( // Not VL_PRINTF_MT, already on main thread "- %s:%d: Verilog $finish\n", filename, linenum); - if (Verilated::threadContextp()->gotFinish()) { - VL_PRINTF( // Not VL_PRINTF_MT, already on main thread - "- %s:%d: Second verilog $finish, exiting\n", filename, linenum); - Verilated::runFlushCallbacks(); - Verilated::runExitCallbacks(); - std::exit(0); - } Verilated::threadContextp()->gotFinish(true); } #endif @@ -451,6 +444,8 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData const int uw = VL_WORDS_I(umsbp1); // aka "m" in the algorithm const int vw = VL_WORDS_I(vmsbp1); // aka "n" in the algorithm + VL_DEBUG_IFDEF(assert(uw <= VL_MULS_MAX_WORDS);); + VL_DEBUG_IFDEF(assert(vw <= VL_MULS_MAX_WORDS);); if (vw == 1) { // Single divisor word breaks rest of algorithm uint64_t k = 0; @@ -472,27 +467,25 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData // Zero for ease of debugging and to save having to zero for shifts // Note +1 as loop will use extra word - for (int i = 0; i < words + 1; ++i) { un[i] = vn[i] = 0; } + for (int i = 0; i < words + 1; ++i) un[i] = vn[i] = 0; // Algorithm requires divisor MSB to be set // Copy and shift to normalize divisor so MSB of vn[vw-1] is set const int s = 31 - VL_BITBIT_I(vmsbp1 - 1); // shift amount (0...31) - const uint32_t shift_mask = s ? 0xffffffff : 0; // otherwise >> 32 won't mask the value - for (int i = vw - 1; i > 0; --i) { - vn[i] = (rwp[i] << s) | (shift_mask & (rwp[i - 1] >> (32 - s))); - } - vn[0] = rwp[0] << s; - // Copy and shift dividend by same amount; may set new upper word if (s) { + for (int i = vw - 1; i > 0; --i) vn[i] = (rwp[i] << s) | (rwp[i - 1] >> (32 - s)); + vn[0] = rwp[0] << s; un[uw] = lwp[uw - 1] >> (32 - s); + for (int i = uw - 1; i > 0; --i) un[i] = (lwp[i] << s) | (lwp[i - 1] >> (32 - s)); + un[0] = lwp[0] << s; } else { + for (int i = vw - 1; i > 0; --i) vn[i] = rwp[i]; + vn[0] = rwp[0]; un[uw] = 0; + for (int i = uw - 1; i > 0; --i) un[i] = lwp[i]; + un[0] = lwp[0]; } - for (int i = uw - 1; i > 0; --i) { - un[i] = (lwp[i] << s) | (shift_mask & (lwp[i - 1] >> (32 - s))); - } - un[0] = lwp[0] << s; // Main loop for (int j = uw - vw; j >= 0; --j) { @@ -536,8 +529,10 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData if (is_modulus) { // modulus // Need to reverse normalization on copy to output - for (int i = 0; i < vw; ++i) { - owp[i] = (un[i] >> s) | (shift_mask & (un[i + 1] << (32 - s))); + if (s) { + for (int i = 0; i < vw; ++i) owp[i] = (un[i] >> s) | (un[i + 1] << (32 - s)); + } else { + for (int i = 0; i < vw; ++i) owp[i] = un[i]; } for (int i = vw; i < words; ++i) owp[i] = 0; return owp; @@ -549,6 +544,8 @@ WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, const WDataInP lwp, const WData WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, const WDataInP lwp, const WDataInP rwp) VL_MT_SAFE { // obits==lbits, rbits can be different + const int owords = VL_WORDS_I(obits); + VL_DEBUG_IFDEF(assert(owords <= VL_MULS_MAX_WORDS);); owp[0] = 1; for (int i = 1; i < VL_WORDS_I(obits); i++) owp[i] = 0; // cppcheck-has-bug-suppress variableScope @@ -560,11 +557,11 @@ WDataOutP VL_POW_WWW(int obits, int, int rbits, WDataOutP owp, const WDataInP lw for (int bit = 0; bit < rbits; bit++) { if (bit > 0) { // power = power*power VL_ASSIGN_W(obits, lastpowstore, powstore); - VL_MUL_W(VL_WORDS_I(obits), powstore, lastpowstore, lastpowstore); + VL_MUL_W(owords, powstore, lastpowstore, lastpowstore); } if (VL_BITISSET_W(rwp, bit)) { // out *= power VL_ASSIGN_W(obits, lastoutstore, owp); - VL_MUL_W(VL_WORDS_I(obits), owp, lastoutstore, powstore); + VL_MUL_W(owords, owp, lastoutstore, powstore); } } return owp; @@ -576,7 +573,10 @@ WDataOutP VL_POW_WWQ(int obits, int lbits, int rbits, WDataOutP owp, const WData return VL_POW_WWW(obits, lbits, rbits, owp, lwp, rhsw); } QData VL_POW_QQW(int, int, int rbits, QData lhs, const WDataInP rwp) VL_MT_SAFE { - // Skip check for rhs == 0, as short-circuit doesn't save time + const int rwords = VL_WORDS_I(rbits); + EData rnz = rwp[0]; + for (int w = 1; w < rwords; ++w) rnz |= rwp[w]; + if (!rnz) return 1; // rwp == 0 if (VL_UNLIKELY(lhs == 0)) return 0; QData power = lhs; QData result = 1ULL; @@ -657,8 +657,10 @@ double VL_ITOR_D_W(int lbits, const WDataInP lwp) VL_PURE { } double VL_ISTOR_D_W(int lbits, const WDataInP lwp) VL_MT_SAFE { if (!VL_SIGN_W(lbits, lwp)) return VL_ITOR_D_W(lbits, lwp); + const int words = VL_WORDS_I(lbits); + VL_DEBUG_IFDEF(assert(words <= VL_MULS_MAX_WORDS);); uint32_t pos[VL_MULS_MAX_WORDS + 1]; // Fixed size, as MSVC++ doesn't allow [words] here - VL_NEGATE_W(VL_WORDS_I(lbits), pos, lwp); + VL_NEGATE_W(words, pos, lwp); _vl_clean_inplace_w(lbits, pos); return -VL_ITOR_D_W(lbits, pos); } @@ -2710,14 +2712,11 @@ void VerilatedContextImp::commandArgVl(const std::string& arg) { "Exiting due to command line argument (not an error)"); } else if (arg == "+verilator+noassert") { assertOn(false); - } else if (commandArgVlUint64(arg, "+verilator+prof+exec+start+", u64) - || commandArgVlUint64(arg, "+verilator+prof+threads+start+", u64)) { + } else if (commandArgVlUint64(arg, "+verilator+prof+exec+start+", u64)) { profExecStart(u64); - } else if (commandArgVlUint64(arg, "+verilator+prof+exec+window+", u64, 1) - || commandArgVlUint64(arg, "+verilator+prof+threads+window+", u64, 1)) { + } else if (commandArgVlUint64(arg, "+verilator+prof+exec+window+", u64, 1)) { profExecWindow(u64); - } else if (commandArgVlString(arg, "+verilator+prof+exec+file+", str) - || commandArgVlString(arg, "+verilator+prof+threads+file+", str)) { + } else if (commandArgVlString(arg, "+verilator+prof+exec+file+", str)) { profExecFilename(str); } else if (commandArgVlString(arg, "+verilator+prof+vlt+file+", str)) { profVltFilename(str); @@ -3249,11 +3248,11 @@ void VlDeleter::deleteAll() VL_EXCLUDES(m_mutex) VL_EXCLUDES(m_deleteMutex) VL_M VerilatedLockGuard lock{m_mutex}; if (m_newGarbage.empty()) break; m_deleteMutex.lock(); - std::swap(m_newGarbage, m_toDelete); + std::swap(m_newGarbage, m_deleteNow); // m_mutex is unlocked here, so destructors can enqueue new objects } - for (VlDeletable* const objp : m_toDelete) delete objp; - m_toDelete.clear(); + for (VlDeletable* const objp : m_deleteNow) delete objp; + m_deleteNow.clear(); m_deleteMutex.unlock(); } } diff --git a/include/verilated.h b/include/verilated.h index 77deeefb1..e82b75e80 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -627,8 +627,9 @@ class VerilatedScope final { public: enum Type : uint8_t { SCOPE_MODULE, - SCOPE_OTHER - }; // Type of a scope, currently module is only interesting + SCOPE_OTHER, + SCOPE_PACKAGE + }; // Type of a scope, currently only module and package are interesting private: // Fastpath: VerilatedSyms* m_symsp = nullptr; // Symbol table diff --git a/include/verilated.mk.in b/include/verilated.mk.in index 59a94486f..cc9e615c8 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -2,7 +2,7 @@ ###################################################################### # DESCRIPTION: Makefile commands for all verilated target files # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -11,7 +11,7 @@ # Tool names. # These are computed at configuration time, and most are not ?= -# to avoid picking up potentilly incorrect Make implicit variables +# to avoid picking up potentially incorrect Make implicit variables AR = @AR@ CXX = @CXX@ LINK = @CXX@ @@ -154,7 +154,7 @@ ifeq ($(VM_SC),1) LDFLAGS += $(SYSTEMC_CXX_FLAGS) $(addprefix -L, $(SYSTEMC_LIBDIR)) SC_LIBS = -lsystemc ifneq ($(wildcard $(SYSTEMC_LIBDIR)/*numeric_bit*),) - # Systemc 1.2.1beta + # SystemC 1.2.1beta SC_LIBS += -lnumeric_bit -lqt endif endif diff --git a/include/verilated.v b/include/verilated.v index e55dbc99d..dcdb10ccd 100644 --- a/include/verilated.v +++ b/include/verilated.v @@ -2,7 +2,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_config.h.in b/include/verilated_config.h.in index 524ee861f..352dc057c 100644 --- a/include/verilated_config.h.in +++ b/include/verilated_config.h.in @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index 8fe4e99be..ea5d738fd 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -211,7 +211,7 @@ private: std::string result = prefix + "*" + suffix; // std::cout << "\nch pre=" << prefix << " s=" << suffix << "\nch a=" - // << old << "\nch b=" << add << "\ncho=" << result << std::endl; + // << old << "\nch b=" << add << "\ncho=" << result << "\n"; return result; } bool itemMatchesString(VerilatedCovImpItem* itemp, const std::string& match) @@ -337,7 +337,7 @@ public: const std::string key = keys[i]; if (!keys[i].empty()) { const std::string val = valps[i]; - // std::cout << " " << __FUNCTION__ << " " << key << " = " << val << std::endl; + // std::cout << " " << __FUNCTION__ << " " << key << " = " << val << "\n"; m_insertp->m_keys[addKeynum] = valueIndex(key); m_insertp->m_vals[addKeynum] = valueIndex(val); ++addKeynum; diff --git a/include/verilated_cov.h b/include/verilated_cov.h index 447ddf6fb..d759e1a9f 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_cov_key.h b/include/verilated_cov_key.h index e81abecb4..7f956c145 100644 --- a/include/verilated_cov_key.h +++ b/include/verilated_cov_key.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp index afd7b6f67..86e2a20a3 100644 --- a/include/verilated_dpi.cpp +++ b/include/verilated_dpi.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_dpi.h b/include/verilated_dpi.h index 18af2fcb1..56e9e7fd3 100644 --- a/include/verilated_dpi.h +++ b/include/verilated_dpi.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index 5dc3a2b11..79c5c9ee9 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 0331ca5e9..403f9ede8 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -210,7 +210,7 @@ public: /// Return if file is open bool isOpen() const VL_MT_SAFE { return m_sptrace.isOpen(); } /// Open a new FST file - void open(const char* filename) VL_MT_SAFE { m_sptrace.open(filename); } + virtual void open(const char* filename) VL_MT_SAFE { m_sptrace.open(filename); } /// Close dump void close() VL_MT_SAFE { m_sptrace.close(); } /// Flush dump @@ -230,12 +230,12 @@ public: // Set time units (s/ms, defaults to ns) // Users should not need to call this, as for Verilated models, these - // propage from the Verilated default timeunit + // propagate from the Verilated default timeunit void set_time_unit(const char* unitp) VL_MT_SAFE { m_sptrace.set_time_unit(unitp); } void set_time_unit(const std::string& unit) VL_MT_SAFE { m_sptrace.set_time_unit(unit); } // Set time resolution (s/ms, defaults to ns) // Users should not need to call this, as for Verilated models, these - // propage from the Verilated default timeprecision + // propagate from the Verilated default timeprecision void set_time_resolution(const char* unitp) VL_MT_SAFE { m_sptrace.set_time_resolution(unitp); } diff --git a/include/verilated_fst_sc.cpp b/include/verilated_fst_sc.cpp index fca25f937..5d375e5c8 100644 --- a/include/verilated_fst_sc.cpp +++ b/include/verilated_fst_sc.cpp @@ -3,7 +3,7 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_fst_sc.h b/include/verilated_fst_sc.h index af288f11b..4cda7e548 100644 --- a/include/verilated_fst_sc.h +++ b/include/verilated_fst_sc.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -12,8 +12,7 @@ /// \file /// \brief Verilated tracing in FST format for SystemC header /// -/// User wrapper code should use this header when creating FST SystemC -/// traces. +/// User wrapper code should use this header when creating FST SystemC traces. /// /// This class is not threadsafe, as the SystemC kernel is not threadsafe. /// @@ -25,115 +24,33 @@ #include "verilatedos.h" #include "verilated_fst_c.h" -#include "verilated_sc.h" - -#include +#include "verilated_sc_trace.h" //============================================================================= // VerilatedFstSc -/// -/// Class representing a Verilator-friendly FST trace format registered -/// with the SystemC simulation kernel, just like a SystemC-documented -/// trace format. +/// Trace file used to create FST dump for SystemC version of Verilated models. It's very similar +/// to its C version (see the class VerilatedFstC) -class VerilatedFstSc final : sc_core::sc_trace_file, public VerilatedFstC { +class VerilatedFstSc final : VerilatedScTraceBase, public VerilatedFstC { // CONSTRUCTORS VL_UNCOPYABLE(VerilatedFstSc); public: - /// Construct a SC trace object, and register with the SystemC kernel VerilatedFstSc() { - sc_core::sc_get_curr_simcontext()->add_trace_file(this); - // We want to avoid a depreciated warning, but still be back compatible. - // Turning off the message just for this still results in an - // annoying "to turn off" message. - const sc_core::sc_time t1sec{1, sc_core::SC_SEC}; - if (t1sec.to_default_time_units() != 0) { - const sc_core::sc_time tunits{1.0 / t1sec.to_default_time_units(), sc_core::SC_SEC}; - spTrace()->set_time_unit(tunits.to_string()); - } - spTrace()->set_time_resolution(sc_core::sc_get_time_resolution().to_string()); - } - /// Destruct, flush, and close the dump - ~VerilatedFstSc() override { close(); } - - // METHODS - for SC kernel - // Called by SystemC simulate() - void cycle(bool delta_cycle) override { - if (!delta_cycle) this->dump(sc_core::sc_time_stamp().to_double()); + spTrace()->set_time_unit(VerilatedScTraceBase::getScTimeUnit()); + spTrace()->set_time_resolution(VerilatedScTraceBase::getScTimeResolution()); } + // METHODS // Override VerilatedFstC. Must be called after starting simulation. - // Note: this is not a virtual function in the base class, so no 'override' - virtual void open(const char* filename) VL_MT_SAFE { - if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) { - Verilated::scTraceBeforeElaborationError(); - } + void open(const char* filename) override VL_MT_SAFE { + VerilatedScTraceBase::checkScElaborationDone(); VerilatedFstC::open(filename); } -private: - // METHODS - Fake outs for linker - -#ifdef NC_SYSTEMC - // Cadence Incisive has these as abstract functions so we must create them - void set_time_unit(int exponent10_seconds) override {} // deprecated -#endif - void set_time_unit(double v, sc_core::sc_time_unit tu) override {} // LCOV_EXCL_LINE - - //-------------------------------------------------- - // SystemC 2.1.v1 - - void write_comment(const std::string&) override {} - void trace(const unsigned int&, const std::string&, const char**) override {} - -#define DECL_TRACE_METHOD_A(tp) \ - void trace(const tp& object, const std::string& name) override {} -#define DECL_TRACE_METHOD_B(tp) \ - void trace(const tp& object, const std::string& name, int width) override {} - - // clang-format off - // Formatting matches that of sc_trace.h - // LCOV_EXCL_START -#if (SYSTEMC_VERSION >= 20171012) - DECL_TRACE_METHOD_A( sc_core::sc_event ) - DECL_TRACE_METHOD_A( sc_core::sc_time ) -#endif - - DECL_TRACE_METHOD_A( bool ) - DECL_TRACE_METHOD_A( sc_dt::sc_bit ) - DECL_TRACE_METHOD_A( sc_dt::sc_logic ) - - DECL_TRACE_METHOD_B( unsigned char ) - DECL_TRACE_METHOD_B( unsigned short ) - DECL_TRACE_METHOD_B( unsigned int ) - DECL_TRACE_METHOD_B( unsigned long ) - DECL_TRACE_METHOD_B( char ) - DECL_TRACE_METHOD_B( short ) - DECL_TRACE_METHOD_B( int ) - DECL_TRACE_METHOD_B( long ) - DECL_TRACE_METHOD_B( sc_dt::int64 ) - DECL_TRACE_METHOD_B( sc_dt::uint64 ) - - DECL_TRACE_METHOD_A( float ) - DECL_TRACE_METHOD_A( double ) - DECL_TRACE_METHOD_A( sc_dt::sc_int_base ) - DECL_TRACE_METHOD_A( sc_dt::sc_uint_base ) - DECL_TRACE_METHOD_A( sc_dt::sc_signed ) - DECL_TRACE_METHOD_A( sc_dt::sc_unsigned ) - - DECL_TRACE_METHOD_A( sc_dt::sc_fxval ) - DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast ) - DECL_TRACE_METHOD_A( sc_dt::sc_fxnum ) - DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast ) - - DECL_TRACE_METHOD_A( sc_dt::sc_bv_base ) - DECL_TRACE_METHOD_A( sc_dt::sc_lv_base ) - // LCOV_EXCL_STOP - // clang-format on - -#undef DECL_TRACE_METHOD_A -#undef DECL_TRACE_METHOD_B + // METHODS - for SC kernel + // Called from SystemC kernel + void cycle() override { VerilatedFstC::dump(sc_core::sc_time_stamp().to_double()); } }; #endif // Guard diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index 673cf822a..9ad3dec61 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -284,6 +284,8 @@ inline uint64_t vl_time_stamp64() VL_MT_SAFE { # endif #endif +// clang-format on + uint64_t VerilatedContext::time() const VL_MT_SAFE { // When using non-default context, fastest path is return time if (VL_LIKELY(m_s.m_time)) return m_s.m_time; @@ -311,25 +313,6 @@ double vl_time_multiplier(int scale) VL_PURE; // Return power of 10. e.g. returns 100 if n==2 uint64_t vl_time_pow10(int n) VL_PURE; -#ifdef VL_DEBUG -/// Evaluate statement if VL_DEBUG defined -# define VL_DEBUG_IFDEF(stmt) \ - do { \ - stmt \ - } while (false) -/// Evaluate statement if VL_DEBUG defined and Verilated::debug() enabled -# define VL_DEBUG_IF(stmt) \ - do { \ - if (VL_UNLIKELY(Verilated::debug())) {stmt} \ - } while (false) -#else -// We intentionally do not compile the stmt to improve compile speed -# define VL_DEBUG_IFDEF(stmt) do {} while (false) -# define VL_DEBUG_IF(stmt) do {} while (false) -#endif - -// clang-format on - //========================================================================= // Functional macros/routines // These all take the form @@ -342,6 +325,19 @@ uint64_t vl_time_pow10(int n) VL_PURE; //=================================================================== // SETTING OPERATORS +VL_ATTR_ALWINLINE +static WDataOutP VL_MEMSET_ZERO_W(WDataOutP owp, int words) VL_MT_SAFE { + return static_cast(std::memset(owp, 0, words * sizeof(EData))); +} +VL_ATTR_ALWINLINE +static WDataOutP VL_MEMSET_ONES_W(WDataOutP owp, int words) VL_MT_SAFE { + return static_cast(std::memset(owp, 0xff, words * sizeof(EData))); +} +VL_ATTR_ALWINLINE +static WDataOutP VL_MEMCPY_W(WDataOutP owp, WDataInP const iwp, int words) VL_MT_SAFE { + return static_cast(std::memcpy(owp, iwp, words * sizeof(EData))); +} + // Output clean // EMIT_RULE: VL_CLEAN: oclean=clean; obits=lbits; #define VL_CLEAN_II(obits, lbits, lhs) ((lhs) & (VL_MASK_I(obits))) @@ -356,18 +352,16 @@ static inline WDataOutP _vl_clean_inplace_w(int obits, WDataOutP owp) VL_MT_SAFE } static inline WDataOutP VL_CLEAN_WW(int obits, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { const int words = VL_WORDS_I(obits); - for (int i = 0; (i < (words - 1)); ++i) owp[i] = lwp[i]; + VL_MEMCPY_W(owp, lwp, words - 1); owp[words - 1] = lwp[words - 1] & VL_MASK_E(obits); return owp; } static inline WDataOutP VL_ZERO_W(int obits, WDataOutP owp) VL_MT_SAFE { - const int words = VL_WORDS_I(obits); - for (int i = 0; i < words; ++i) owp[i] = 0; - return owp; + return VL_MEMSET_ZERO_W(owp, VL_WORDS_I(obits)); } static inline WDataOutP VL_ALLONES_W(int obits, WDataOutP owp) VL_MT_SAFE { const int words = VL_WORDS_I(obits); - for (int i = 0; i < (words - 1); ++i) owp[i] = ~VL_EUL(0); + VL_MEMSET_ONES_W(owp, words - 1); owp[words - 1] = VL_MASK_E(obits); return owp; } @@ -376,9 +370,7 @@ static inline WDataOutP VL_ALLONES_W(int obits, WDataOutP owp) VL_MT_SAFE { // For now, we always have a clean rhs. // Note: If a ASSIGN isn't clean, use VL_ASSIGNCLEAN instead to do the same thing. static inline WDataOutP VL_ASSIGN_W(int obits, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { - const int words = VL_WORDS_I(obits); - for (int i = 0; i < words; ++i) owp[i] = lwp[i]; - return owp; + return VL_MEMCPY_W(owp, lwp, VL_WORDS_I(obits)); } // EMIT_RULE: VL_ASSIGNBIT: rclean=clean; @@ -536,19 +528,20 @@ static inline void VL_ASSIGNBIT_WO(int bit, WDataOutP owp) VL_MT_SAFE { static inline WDataOutP VL_EXTEND_WI(int obits, int, WDataOutP owp, IData ld) VL_MT_SAFE { // Note for extracts that obits != lbits owp[0] = ld; - for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = 0; + VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); return owp; } static inline WDataOutP VL_EXTEND_WQ(int obits, int, WDataOutP owp, QData ld) VL_MT_SAFE { VL_SET_WQ(owp, ld); - for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = 0; + VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); return owp; } static inline WDataOutP VL_EXTEND_WW(int obits, int lbits, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { - for (int i = 0; i < VL_WORDS_I(lbits); ++i) owp[i] = lwp[i]; - for (int i = VL_WORDS_I(lbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0; - return owp; + const int lwords = VL_WORDS_I(lbits); + VL_PREFETCH_RD(lwp); + VL_MEMSET_ZERO_W(owp + lwords, VL_WORDS_I(obits) - lwords); + return VL_MEMCPY_W(owp, lwp, lwords); } // EMIT_RULE: VL_EXTENDS: oclean=*dirty*; obits=lbits; @@ -564,26 +557,37 @@ static inline QData VL_EXTENDS_QQ(int, int lbits, QData lhs) VL_PURE { } static inline WDataOutP VL_EXTENDS_WI(int obits, int lbits, WDataOutP owp, IData ld) VL_MT_SAFE { - const EData sign = VL_SIGNONES_E(lbits, static_cast(ld)); - owp[0] = ld | (sign & ~VL_MASK_E(lbits)); - for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = sign; + owp[0] = ld; + if (VL_SIGN_E(lbits, owp[0])) { + owp[0] |= ~VL_MASK_E(lbits); + VL_MEMSET_ONES_W(owp + 1, VL_WORDS_I(obits) - 1); + } else { + VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); + } return owp; } static inline WDataOutP VL_EXTENDS_WQ(int obits, int lbits, WDataOutP owp, QData ld) VL_MT_SAFE { VL_SET_WQ(owp, ld); - const EData sign = VL_SIGNONES_E(lbits, owp[1]); - owp[1] |= sign & ~VL_MASK_E(lbits); - for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = sign; + if (VL_SIGN_E(lbits, owp[1])) { + owp[1] |= ~VL_MASK_E(lbits); + VL_MEMSET_ONES_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); + } else { + VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); + } return owp; } static inline WDataOutP VL_EXTENDS_WW(int obits, int lbits, WDataOutP owp, WDataInP const lwp) VL_MT_SAFE { - for (int i = 0; i < VL_WORDS_I(lbits) - 1; ++i) owp[i] = lwp[i]; - const int lmsw = VL_WORDS_I(lbits) - 1; - const EData sign = VL_SIGNONES_E(lbits, lwp[lmsw]); - owp[lmsw] = lwp[lmsw] | (sign & ~VL_MASK_E(lbits)); - for (int i = VL_WORDS_I(lbits); i < VL_WORDS_I(obits); ++i) owp[i] = sign; - return owp; + const int lwords = VL_WORDS_I(lbits); + VL_PREFETCH_RD(lwp); + owp[lwords - 1] = lwp[lwords - 1]; + if (VL_SIGN_E(lbits, lwp[lwords - 1])) { + owp[lwords - 1] |= ~VL_MASK_E(lbits); + VL_MEMSET_ONES_W(owp + lwords, VL_WORDS_I(obits) - lwords); + } else { + VL_MEMSET_ZERO_W(owp + lwords, VL_WORDS_I(obits) - lwords); + } + return VL_MEMCPY_W(owp, lwp, lwords - 1); } //=================================================================== @@ -1028,6 +1032,7 @@ static inline QData VL_MULS_QQQ(int lbits, QData lhs, QData rhs) VL_PURE { static inline WDataOutP VL_MULS_WWW(int lbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { const int words = VL_WORDS_I(lbits); + VL_DEBUG_IFDEF(assert(words <= VL_MULS_MAX_WORDS);); // cppcheck-suppress variableScope WData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here // cppcheck-suppress variableScope @@ -1098,21 +1103,22 @@ static inline QData VL_MODDIVS_QQQ(int lbits, QData lhs, QData rhs) VL_PURE { static inline WDataOutP VL_DIVS_WWW(int lbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { - const int words = VL_WORDS_I(lbits); - const EData lsign = VL_SIGN_E(lbits, lwp[words - 1]); - const EData rsign = VL_SIGN_E(lbits, rwp[words - 1]); + const int lwords = VL_WORDS_I(lbits); + const EData lsign = VL_SIGN_E(lbits, lwp[lwords - 1]); + const EData rsign = VL_SIGN_E(lbits, rwp[lwords - 1]); + VL_DEBUG_IFDEF(assert(lwords <= VL_MULS_MAX_WORDS);); // cppcheck-suppress variableScope WData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here // cppcheck-suppress variableScope WData rwstore[VL_MULS_MAX_WORDS]; WDataInP ltup = lwp; WDataInP rtup = rwp; - if (lsign) ltup = _vl_clean_inplace_w(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), lwstore, lwp)); - if (rsign) rtup = _vl_clean_inplace_w(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), rwstore, rwp)); + if (lsign) ltup = _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, lwstore, lwp)); + if (rsign) rtup = _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, rwstore, rwp)); if ((lsign && !rsign) || (!lsign && rsign)) { WData qNoSign[VL_MULS_MAX_WORDS]; VL_DIV_WWW(lbits, qNoSign, ltup, rtup); - _vl_clean_inplace_w(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), owp, qNoSign)); + _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, owp, qNoSign)); return owp; } else { return VL_DIV_WWW(lbits, owp, ltup, rtup); @@ -1120,21 +1126,22 @@ static inline WDataOutP VL_DIVS_WWW(int lbits, WDataOutP owp, WDataInP const lwp } static inline WDataOutP VL_MODDIVS_WWW(int lbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { - const int words = VL_WORDS_I(lbits); - const EData lsign = VL_SIGN_E(lbits, lwp[words - 1]); - const EData rsign = VL_SIGN_E(lbits, rwp[words - 1]); + const int lwords = VL_WORDS_I(lbits); + const EData lsign = VL_SIGN_E(lbits, lwp[lwords - 1]); + const EData rsign = VL_SIGN_E(lbits, rwp[lwords - 1]); + VL_DEBUG_IFDEF(assert(lwords <= VL_MULS_MAX_WORDS);); // cppcheck-suppress variableScope WData lwstore[VL_MULS_MAX_WORDS]; // Fixed size, as MSVC++ doesn't allow [words] here // cppcheck-suppress variableScope WData rwstore[VL_MULS_MAX_WORDS]; WDataInP ltup = lwp; WDataInP rtup = rwp; - if (lsign) ltup = _vl_clean_inplace_w(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), lwstore, lwp)); - if (rsign) rtup = _vl_clean_inplace_w(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), rwstore, rwp)); + if (lsign) ltup = _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, lwstore, lwp)); + if (rsign) rtup = _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, rwstore, rwp)); if (lsign) { // Only dividend sign matters for modulus WData qNoSign[VL_MULS_MAX_WORDS]; VL_MODDIV_WWW(lbits, qNoSign, ltup, rtup); - _vl_clean_inplace_w(lbits, VL_NEGATE_W(VL_WORDS_I(lbits), owp, qNoSign)); + _vl_clean_inplace_w(lbits, VL_NEGATE_W(lwords, owp, qNoSign)); return owp; } else { return VL_MODDIV_WWW(lbits, owp, ltup, rtup); @@ -1566,63 +1573,66 @@ static inline QData VL_DYN_TO_Q(const VlQueue& q, int elem_size) { static inline WDataOutP VL_CONCAT_WII(int obits, int lbits, int rbits, WDataOutP owp, IData ld, IData rd) VL_MT_SAFE { owp[0] = rd; - for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = 0; + VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); _vl_insert_WI(owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WWI(int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, IData rd) VL_MT_SAFE { owp[0] = rd; - for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = 0; + VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); _vl_insert_WW(owp, lwp, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WIW(int obits, int lbits, int rbits, WDataOutP owp, IData ld, WDataInP const rwp) VL_MT_SAFE { - for (int i = 0; i < VL_WORDS_I(rbits); ++i) owp[i] = rwp[i]; - for (int i = VL_WORDS_I(rbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0; + const int rwords = VL_WORDS_I(rbits); + VL_MEMCPY_W(owp, rwp, rwords); + VL_MEMSET_ZERO_W(owp + rwords, VL_WORDS_I(obits) - rwords); _vl_insert_WI(owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WIQ(int obits, int lbits, int rbits, WDataOutP owp, IData ld, QData rd) VL_MT_SAFE { VL_SET_WQ(owp, rd); - for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = 0; + VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); _vl_insert_WI(owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WQI(int obits, int lbits, int rbits, WDataOutP owp, QData ld, IData rd) VL_MT_SAFE { owp[0] = rd; - for (int i = 1; i < VL_WORDS_I(obits); ++i) owp[i] = 0; + VL_MEMSET_ZERO_W(owp + 1, VL_WORDS_I(obits) - 1); _vl_insert_WQ(owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WQQ(int obits, int lbits, int rbits, WDataOutP owp, QData ld, QData rd) VL_MT_SAFE { VL_SET_WQ(owp, rd); - for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = 0; + VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); _vl_insert_WQ(owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WWQ(int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, QData rd) VL_MT_SAFE { VL_SET_WQ(owp, rd); - for (int i = VL_WQ_WORDS_E; i < VL_WORDS_I(obits); ++i) owp[i] = 0; + VL_MEMSET_ZERO_W(owp + VL_WQ_WORDS_E, VL_WORDS_I(obits) - VL_WQ_WORDS_E); _vl_insert_WW(owp, lwp, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WQW(int obits, int lbits, int rbits, WDataOutP owp, QData ld, WDataInP const rwp) VL_MT_SAFE { - for (int i = 0; i < VL_WORDS_I(rbits); ++i) owp[i] = rwp[i]; - for (int i = VL_WORDS_I(rbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0; + const int rwords = VL_WORDS_I(rbits); + VL_MEMCPY_W(owp, rwp, rwords); + VL_MEMSET_ZERO_W(owp + rwords, VL_WORDS_I(obits) - rwords); _vl_insert_WQ(owp, ld, rbits + lbits - 1, rbits); return owp; } static inline WDataOutP VL_CONCAT_WWW(int obits, int lbits, int rbits, WDataOutP owp, WDataInP const lwp, WDataInP const rwp) VL_MT_SAFE { - for (int i = 0; i < VL_WORDS_I(rbits); ++i) owp[i] = rwp[i]; - for (int i = VL_WORDS_I(rbits); i < VL_WORDS_I(obits); ++i) owp[i] = 0; + const int rwords = VL_WORDS_I(rbits); + VL_MEMCPY_W(owp, rwp, rwords); + VL_MEMSET_ZERO_W(owp + rwords, VL_WORDS_I(obits) - rwords); _vl_insert_WW(owp, lwp, rbits + lbits - 1, rbits); return owp; } @@ -1846,10 +1856,13 @@ static inline WDataOutP VL_SHIFTRS_WWW(int obits, int lbits, int rbits, WDataOut EData overshift = 0; // Huge shift 1>>32 or more for (int i = 1; i < VL_WORDS_I(rbits); ++i) overshift |= rwp[i]; if (VL_UNLIKELY(overshift || rwp[0] >= static_cast(obits))) { - const int lmsw = VL_WORDS_I(obits) - 1; - const EData sign = VL_SIGNONES_E(lbits, lwp[lmsw]); - for (int j = 0; j <= lmsw; ++j) owp[j] = sign; - owp[lmsw] &= VL_MASK_E(lbits); + const int owords = VL_WORDS_I(obits); + if (VL_SIGN_E(lbits, lwp[owords - 1])) { + VL_MEMSET_ONES_W(owp, owords); + owp[owords - 1] &= VL_MASK_E(lbits); + } else { + VL_MEMSET_ZERO_W(owp, owords); + } return owp; } return VL_SHIFTRS_WWI(obits, lbits, 32, owp, lwp, rwp[0]); @@ -2060,9 +2073,7 @@ static inline void VL_ASSIGNSEL_WW(int rbits, int obits, int lsb, WDataOutP iowp static inline WDataOutP VL_COND_WIWW(int obits, WDataOutP owp, int cond, WDataInP const w1p, WDataInP const w2p) VL_MT_SAFE { - const int words = VL_WORDS_I(obits); - for (int i = 0; i < words; ++i) owp[i] = cond ? w1p[i] : w2p[i]; - return owp; + return VL_MEMCPY_W(owp, cond ? w1p : w2p, VL_WORDS_I(obits)); } //====================================================================== @@ -2075,7 +2086,7 @@ static inline WDataOutP VL_COND_WIWW(int obits, WDataOutP owp, int cond, WDataIn // If changing the number of functions here, also change EMITCINLINES_NUM_CONSTW #define VL_C_END_(obits, wordsSet) \ - for (int i = (wordsSet); i < VL_WORDS_I(obits); ++i) o[i] = 0; \ + VL_MEMSET_ZERO_W(o + (wordsSet), VL_WORDS_I(obits) - (wordsSet)); \ return o // clang-format off diff --git a/include/verilated_imp.h b/include/verilated_imp.h index dfc1cdf92..1cb19dcc5 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_intrinsics.h b/include/verilated_intrinsics.h index c1e2fea11..a8c153e49 100644 --- a/include/verilated_intrinsics.h +++ b/include/verilated_intrinsics.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_probdist.cpp b/include/verilated_probdist.cpp index b367d5a82..de4ca6308 100644 --- a/include/verilated_probdist.cpp +++ b/include/verilated_probdist.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_profiler.cpp b/include/verilated_profiler.cpp index d6301ec24..f17db8ca6 100644 --- a/include/verilated_profiler.cpp +++ b/include/verilated_profiler.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2012-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_profiler.h b/include/verilated_profiler.h index 7c0f1f886..6938c338d 100644 --- a/include/verilated_profiler.h +++ b/include/verilated_profiler.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2023 by Wilson Snyder. This program is free software; you +// Copyright 2012-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp index 26387afc7..53518278e 100644 --- a/include/verilated_save.cpp +++ b/include/verilated_save.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_save.h b/include/verilated_save.h index 212c28a67..4ff97a154 100644 --- a/include/verilated_save.h +++ b/include/verilated_save.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2000-2023 by Wilson Snyder. This program is free software; you +// Copyright 2000-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_sc.h b/include/verilated_sc.h index 81777c3c9..3f7b901b4 100644 --- a/include/verilated_sc.h +++ b/include/verilated_sc.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_sc_trace.h b/include/verilated_sc_trace.h new file mode 100644 index 000000000..dd24b0624 --- /dev/null +++ b/include/verilated_sc_trace.h @@ -0,0 +1,212 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//============================================================================= +// +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//============================================================================= +/// +/// \file +/// \brief Verilated tracing for SystemC implementation code +/// +/// +/// +//============================================================================= + +#ifndef VERILATOR_VERILATED_SC_TRACE_H_ +#define VERILATOR_VERILATED_SC_TRACE_H_ + +#include "verilatedos.h" + +#include "verilated.h" +#include "verilated_sc.h" + +#if SYSTEMC_VERSION < 20140417 // SystemC's simulation phase callback introduced in 2.3.1 +#define _VERILATOR_SYSTEMC_NO_PHASE_CALLBACK +#endif + +//============================================================================= +// VerilatedScTraceBase +// Base class for VCD/FST trace format on SystemC +// This is an internally used class - see VerilatedVcdSc and VerilatedFstSc for what to call from +// applications +// +/// This class utilizes SystemC's callbacks, which allows to dump signals inside the Verilated +/// module automatically as time advances. +/// +/// For SystemC prior to 2.3.1, the only approach for being notified after each update is by adding +/// a trace file (sc_trace_file) to the simulation context. And after this version the simulation +/// phase callback approach has been introduced (sc_trace_file also utilizes this), which is +/// presented only if it's enabled with the `--enable-phase-callbacks` option. However, when it's +/// enabled with `--enable-phase-callbacks=tracing`, trace files will be therefore disabled, thus +/// failing to provide its functionality. +/// +/// To provide a universal way for tracing, the class attempts to register a phase callback first. +/// If it fails (proving that the feature has been disabled), it'll use the trace file approach +/// instead. + +class VerilatedScTraceBase VL_NOT_FINAL : private sc_core::sc_object, + private sc_core::sc_trace_file { + bool m_enableDeltaCycles = false; + bool m_traceFileAdded = false; + static void stubReportHandler(const sc_core::sc_report&, const sc_core::sc_actions&){}; + +public: + void enableDeltaCycles(bool flag = true) { +#ifndef _VERILATOR_SYSTEMC_NO_PHASE_CALLBACK + using namespace sc_core; + // Save old report handler before overriding it + const auto oldHandler = sc_report_handler::get_handler(); + // Override the old handler to hide 'phase callbacks not enabled' message + sc_report_handler::set_handler(&stubReportHandler); + if (flag) { + // Register simulation phase callback for delta cycles + sc_object::register_simulation_phase_callback(SC_END_OF_UPDATE); + } else { + sc_object::unregister_simulation_phase_callback(SC_END_OF_UPDATE); + } + // Restore the old handler + sc_report_handler::set_handler(oldHandler); +#endif + m_enableDeltaCycles = flag; + } + +protected: + VerilatedScTraceBase() + : sc_object(sc_core::sc_gen_unique_name("$$$$verilator_sc_trace$$$$")) + , sc_trace_file() { + registerTraceCallback(); + }; + ~VerilatedScTraceBase() override { +#if SYSTEMC_VERSION >= 20140417 // remove_trace_file added in 2.3.1 + // Phase callback is automatically unregistered in ~sc_object(). Only the trace file is + // needed to be removed here + if (m_traceFileAdded) simcontext()->remove_trace_file(this); +#endif + }; + void registerTraceCallback() { +#ifndef _VERILATOR_SYSTEMC_NO_PHASE_CALLBACK + using namespace sc_core; + // Save old report handler before overriding it + const auto oldHandler = sc_report_handler::get_handler(); + // Override the old handler to hide 'phase callbacks not enabled' message + sc_report_handler::set_handler(&stubReportHandler); + // Register regular simulation phase (non-delta cycle) callback + phase_cb_mask cb_mask = sc_object::register_simulation_phase_callback(SC_BEFORE_TIMESTEP); + if (cb_mask == SC_UNITIALIZED) { +#endif + // Phase callback not enabled, use trace file instead + simcontext()->add_trace_file(this); + m_traceFileAdded = true; +#ifndef _VERILATOR_SYSTEMC_NO_PHASE_CALLBACK + } + // Restore the old handler + sc_report_handler::set_handler(oldHandler); +#endif + } + static std::string getScTimeUnit() { + // We want to avoid a depreciated warning, but still be back compatible. + // Turning off the message just for this still results in an + // annoying "to turn off" message. + const sc_core::sc_time t1sec{1, sc_core::SC_SEC}; + if (t1sec.to_default_time_units() == 0) { + VL_FATAL_MT(__FILE__, __LINE__, "", // LCOV_EXCL_LINE + "Cannot to get valid SystemC default time unit for trace file"); + } + const sc_core::sc_time tunits{1.0 / t1sec.to_default_time_units(), sc_core::SC_SEC}; + return tunits.to_string(); + } + static std::string getScTimeResolution() { + return sc_core::sc_get_time_resolution().to_string(); + } + static void checkScElaborationDone() { + if (!sc_core::sc_get_curr_simcontext()->elaboration_done()) { + Verilated::scTraceBeforeElaborationError(); + } + } + + // METHODS - for SC kernel +#ifndef _VERILATOR_SYSTEMC_NO_PHASE_CALLBACK + // Override sc_object. Called if using phase callback + void simulation_phase_callback() final { cycle(); } +#endif + // Override sc_trace_file. Called if using trace file + void cycle(bool delta_cycle) final { + if (!delta_cycle || m_enableDeltaCycles) cycle(); + } + // METHODS - callbacks + // Subclasses should implement this callback method + virtual void cycle() = 0; + +private: + // METHODS - Fake outs for linker + // LCOV_EXCL_START + +#ifdef NC_SYSTEMC + // Cadence Incisive has these as abstract functions so we must create them + void set_time_unit(int exponent10_seconds) override {} // deprecated +#endif + void set_time_unit(double v, sc_core::sc_time_unit tu) override {} // LCOV_EXCL_LINE + + //-------------------------------------------------- + // SystemC 2.1.v1 + + void write_comment(const std::string&) override {} + void trace(const unsigned int&, const std::string&, const char**) override {} + +#define DECL_TRACE_METHOD_A(tp) \ + void trace(const tp& object, const std::string& name) override {} +#define DECL_TRACE_METHOD_B(tp) \ + void trace(const tp& object, const std::string& name, int width) override {} + + // clang-format off + // Formatting matches that of sc_trace.h +#if SYSTEMC_VERSION >= 20171012 // SystemC >= 2.3.2 + DECL_TRACE_METHOD_A( sc_core::sc_event ) + DECL_TRACE_METHOD_A( sc_core::sc_time ) +#endif + + DECL_TRACE_METHOD_A( bool ) + DECL_TRACE_METHOD_A( sc_dt::sc_bit ) + DECL_TRACE_METHOD_A( sc_dt::sc_logic ) + + DECL_TRACE_METHOD_B( unsigned char ) + DECL_TRACE_METHOD_B( unsigned short ) + DECL_TRACE_METHOD_B( unsigned int ) + DECL_TRACE_METHOD_B( unsigned long ) + DECL_TRACE_METHOD_B( char ) + DECL_TRACE_METHOD_B( short ) + DECL_TRACE_METHOD_B( int ) + DECL_TRACE_METHOD_B( long ) + DECL_TRACE_METHOD_B( sc_dt::int64 ) + DECL_TRACE_METHOD_B( sc_dt::uint64 ) + + DECL_TRACE_METHOD_A( float ) + DECL_TRACE_METHOD_A( double ) + DECL_TRACE_METHOD_A( sc_dt::sc_int_base ) + DECL_TRACE_METHOD_A( sc_dt::sc_uint_base ) + DECL_TRACE_METHOD_A( sc_dt::sc_signed ) + DECL_TRACE_METHOD_A( sc_dt::sc_unsigned ) + + DECL_TRACE_METHOD_A( sc_dt::sc_fxval ) + DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast ) + DECL_TRACE_METHOD_A( sc_dt::sc_fxnum ) + DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast ) + + DECL_TRACE_METHOD_A( sc_dt::sc_bv_base ) + DECL_TRACE_METHOD_A( sc_dt::sc_lv_base ) + // LCOV_EXCL_STOP + // clang-format on + +#undef DECL_TRACE_METHOD_A +#undef DECL_TRACE_METHOD_B +}; + +#ifdef _VERILATOR_SYSTEMC_NO_PHASE_CALLBACK +#undef _VERILATOR_SYSTEMC_NO_PHASE_CALLBACK +#endif + +#endif // Guard diff --git a/include/verilated_std.sv b/include/verilated_std.sv index 88561db13..9eaf1ee9c 100644 --- a/include/verilated_std.sv +++ b/include/verilated_std.sv @@ -4,7 +4,7 @@ // //************************************************************************* // -// Copyright 2022-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2022-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU Lesser // General Public License Version 3 or the Perl Artistic License Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/include/verilated_sym_props.h b/include/verilated_sym_props.h index bcf9c01a5..2e7cdf805 100644 --- a/include/verilated_sym_props.h +++ b/include/verilated_sym_props.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_syms.h b/include/verilated_syms.h index 85a73b21c..1793f8b79 100644 --- a/include/verilated_syms.h +++ b/include/verilated_syms.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_threads.cpp b/include/verilated_threads.cpp index c6e327797..45318f518 100644 --- a/include/verilated_threads.cpp +++ b/include/verilated_threads.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2012-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_threads.h b/include/verilated_threads.h index 155862c9b..5c4cd5691 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2012-2023 by Wilson Snyder. This program is free software; you +// Copyright 2012-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_timing.cpp b/include/verilated_timing.cpp index c14eaf2c7..d44c7a948 100644 --- a/include/verilated_timing.cpp +++ b/include/verilated_timing.cpp @@ -53,36 +53,37 @@ void VlCoroutineHandle::dump() const { //====================================================================== // VlDelayScheduler:: Methods -#ifdef VL_DEBUG -void VlDelayScheduler::VlDelayedCoroutine::dump() const { - VL_DBG_MSGF(" Awaiting time %" PRIu64 ": ", m_timestep); - m_handle.dump(); -} -#endif - void VlDelayScheduler::resume() { #ifdef VL_DEBUG VL_DEBUG_IF(dump(); VL_DBG_MSGF(" Resuming delayed processes\n");); #endif - while (awaitingCurrentTime()) { - if (m_queue.front().m_timestep != m_context.time()) { - VL_FATAL_MT(__FILE__, __LINE__, "", - "%Error: Encountered process that should've been resumed at an " - "earlier simulation time. Missed a time slot?"); - } - // Move max element in the heap to the end - std::pop_heap(m_queue.begin(), m_queue.end()); - VlCoroutineHandle handle = std::move(m_queue.back().m_handle); - m_queue.pop_back(); + bool resumed = false; + + while (!m_queue.empty() && (m_queue.begin()->first == m_context.time())) { + VlCoroutineHandle handle = std::move(m_queue.begin()->second); + m_queue.erase(m_queue.begin()); handle.resume(); + resumed = true; + } + + if (!m_zeroDelayed.empty()) { + for (auto&& handle : m_zeroDelayed) handle.resume(); + m_zeroDelayed.clear(); + resumed = true; + } + + if (!resumed) { + VL_FATAL_MT(__FILE__, __LINE__, "", + "%Error: Encountered process that should've been resumed at an " + "earlier simulation time. Missed a time slot?\n"); } } uint64_t VlDelayScheduler::nextTimeSlot() const { - if (empty()) { + if (!m_queue.empty()) return m_queue.begin()->first; + if (m_zeroDelayed.empty()) VL_FATAL_MT(__FILE__, __LINE__, "", "%Error: There is no next time slot scheduled"); - } - return m_queue.front().m_timestep; + return m_context.time(); } #ifdef VL_DEBUG @@ -91,7 +92,16 @@ void VlDelayScheduler::dump() const { VL_DBG_MSGF(" No delayed processes:\n"); } else { VL_DBG_MSGF(" Delayed processes:\n"); - for (const auto& susp : m_queue) susp.dump(); + for (auto& susp : m_zeroDelayed) { + VL_DBG_MSGF(" Awaiting #0-delayed resumption, " + "time () %" PRIu64 ": ", + m_context.time()); + susp.dump(); + } + for (const auto& susp : m_queue) { + VL_DBG_MSGF(" Awaiting time %" PRIu64 ": ", susp.first); + susp.second.dump(); + } } } #endif diff --git a/include/verilated_timing.h b/include/verilated_timing.h index 48646de69..5d1403eb8 100644 --- a/include/verilated_timing.h +++ b/include/verilated_timing.h @@ -27,6 +27,8 @@ #include "verilated.h" +#include + // clang-format off // Some preprocessor magic to support both Clang and GCC coroutines with both libc++ and libstdc++ #if defined _LIBCPP_VERSION // libc++ @@ -36,15 +38,15 @@ # endif # include namespace std { - using namespace experimental; // Bring std::experimental into the std namespace + using namespace experimental; // Bring std::experimental into the std namespace } #else -# if defined __clang__ && defined __GLIBCXX__ +# if defined __clang__ && defined __GLIBCXX__ && !defined __cpp_impl_coroutine # define __cpp_impl_coroutine 1 // Clang doesn't define this, but it's needed for libstdc++ # endif # include # if __clang_major__ < 14 - namespace std { // Bring coroutine library into std::experimental, as Clang < 14 expects it to be there + namespace std { // Bring coroutine library into std::experimental, as Clang < 14 expects it to be there namespace experimental { using namespace std; } @@ -148,29 +150,21 @@ public: #endif }; +enum class VlDelayPhase : bool { ACTIVE, INACTIVE }; + //============================================================================= // VlDelayScheduler stores coroutines to be resumed at a certain simulation time. If the current // time is equal to a coroutine's resume time, the coroutine gets resumed. class VlDelayScheduler final { // TYPES - struct VlDelayedCoroutine { - uint64_t m_timestep; // Simulation time when the coroutine should be resumed - VlCoroutineHandle m_handle; // The suspended coroutine to be resumed - - // Comparison operator for std::push_heap(), std::pop_heap() - bool operator<(const VlDelayedCoroutine& other) const { - return m_timestep > other.m_timestep; - } -#ifdef VL_DEBUG - void dump() const; -#endif - }; - using VlDelayedCoroutineQueue = std::vector; + // Time-sorted queue of timestamps and handles + using VlDelayedCoroutineQueue = std::multimap; // MEMBERS VerilatedContext& m_context; VlDelayedCoroutineQueue m_queue; // Coroutines to be restored at a certain simulation time + std::vector m_zeroDelayed; // Coroutines waiting for #0 public: // CONSTRUCTORS @@ -183,10 +177,11 @@ public: // coroutines) uint64_t nextTimeSlot() const; // Are there no delayed coroutines awaiting? - bool empty() const { return m_queue.empty(); } + bool empty() const { return m_queue.empty() && m_zeroDelayed.empty(); } // Are there coroutines to resume at the current simulation time? bool awaitingCurrentTime() const { - return !empty() && m_queue.front().m_timestep <= m_context.time(); + return (!m_queue.empty() && (m_queue.begin()->first <= m_context.time())) + || !m_zeroDelayed.empty(); } #ifdef VL_DEBUG void dump() const; @@ -197,19 +192,34 @@ public: struct Awaitable { VlProcessRef process; // Data of the suspended process, null if not needed VlDelayedCoroutineQueue& queue; + std::vector& queueZeroDelay; uint64_t delay; + VlDelayPhase phase; VlFileLineDebug fileline; bool await_ready() const { return false; } // Always suspend void await_suspend(std::coroutine_handle<> coro) { - queue.push_back({delay, VlCoroutineHandle{coro, process, fileline}}); - // Move last element to the proper place in the max-heap - std::push_heap(queue.begin(), queue.end()); + if (phase == VlDelayPhase::ACTIVE) { + queue.emplace(delay, VlCoroutineHandle{coro, process, fileline}); + } else { + queueZeroDelay.emplace_back(VlCoroutineHandle{coro, process, fileline}); + } } void await_resume() const {} }; - return Awaitable{process, m_queue, m_context.time() + delay, - VlFileLineDebug{filename, lineno}}; + + VlDelayPhase phase = (delay == 0) ? VlDelayPhase::INACTIVE : VlDelayPhase::ACTIVE; +#ifdef VL_DEBUG + if (phase == VlDelayPhase::INACTIVE) { + VL_WARN_MT(filename, lineno, VL_UNKNOWN, + "Encountered #0 delay. #0 scheduling support is incomplete and the " + "process will be resumed before combinational logic evaluation."); + } +#endif + + return Awaitable{process, m_queue, + m_zeroDelayed, m_context.time() + delay, + phase, VlFileLineDebug{filename, lineno}}; } }; diff --git a/include/verilated_trace.h b/include/verilated_trace.h index d9af41174..b4b053b42 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_trace_imp.h b/include/verilated_trace_imp.h index 1bdef1291..794ca4363 100644 --- a/include/verilated_trace_imp.h +++ b/include/verilated_trace_imp.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -31,7 +31,7 @@ #if 0 # include -# define VL_TRACE_OFFLOAD_DEBUG(msg) std::cout << "TRACE OFFLOAD THREAD: " << msg << std::endl +# define VL_TRACE_OFFLOAD_DEBUG(msg) std::cout << "TRACE OFFLOAD THREAD: " << msg << "\n" #else # define VL_TRACE_OFFLOAD_DEBUG(msg) #endif @@ -64,9 +64,9 @@ static std::string doubleToTimescale(double value) VL_PURE { const char* suffixp = "s"; // clang-format off if (value >= 1e0) { suffixp = "s"; value *= 1e0; } - else if (value >= 1e-3 ) { suffixp = "ms"; value *= 1e3; } - else if (value >= 1e-6 ) { suffixp = "us"; value *= 1e6; } - else if (value >= 1e-9 ) { suffixp = "ns"; value *= 1e9; } + else if (value >= 1e-3) { suffixp = "ms"; value *= 1e3; } + else if (value >= 1e-6) { suffixp = "us"; value *= 1e6; } + else if (value >= 1e-9) { suffixp = "ns"; value *= 1e9; } else if (value >= 1e-12) { suffixp = "ps"; value *= 1e12; } else if (value >= 1e-15) { suffixp = "fs"; value *= 1e15; } else if (value >= 1e-18) { suffixp = "as"; value *= 1e18; } @@ -328,10 +328,7 @@ void VerilatedTrace::traceInit() VL_MT_UNSAFE { // Call all initialize callbacks, which will: // - Call decl* for each signal (these eventually call ::declCode) // - Store the base code - for (uint32_t i = 0; i < m_initCbs.size(); ++i) { - const CallbackRecord& cbr = m_initCbs[i]; - cbr.m_initCb(cbr.m_userp, self(), nextCode()); - } + for (const CallbackRecord& cbr : m_initCbs) cbr.m_initCb(cbr.m_userp, self(), nextCode()); if (expectedCodes && nextCode() != expectedCodes) { VL_FATAL_MT(__FILE__, __LINE__, "", @@ -614,10 +611,7 @@ void VerilatedTrace::dump(uint64_t timeui) VL_MT_SAFE_EXCLUD } } - for (uint32_t i = 0; i < m_cleanupCbs.size(); ++i) { - const CallbackRecord& cbr = m_cleanupCbs[i]; - cbr.m_cleanupCb(cbr.m_userp, self()); - } + for (const CallbackRecord& cbr : m_cleanupCbs) cbr.m_cleanupCb(cbr.m_userp, self()); if (offload() && VL_LIKELY(bufferp)) { // Mark end of the offload buffer we just filled diff --git a/include/verilated_types.h b/include/verilated_types.h index be2914d70..13a979faa 100644 --- a/include/verilated_types.h +++ b/include/verilated_types.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -39,6 +39,28 @@ #include #include +//========================================================================= +// Debug functions + +#ifdef VL_DEBUG +/// Evaluate statement if VL_DEBUG defined +#define VL_DEBUG_IFDEF(stmt) \ + do { stmt } while (false) +/// Evaluate statement if VL_DEBUG defined and Verilated::debug() enabled +#define VL_DEBUG_IF(stmt) \ + do { \ + if (VL_UNLIKELY(Verilated::debug())) { stmt } \ + } while (false) +#else +// We intentionally do not compile the stmt to improve compile speed +#define VL_DEBUG_IFDEF(stmt) \ + do { \ + } while (false) +#define VL_DEBUG_IF(stmt) \ + do { \ + } while (false) +#endif + //=================================================================== // String formatters (required by below containers) @@ -108,7 +130,7 @@ public: VlProcess() : m_state{RUNNING} {} // Construct child process of parent - VlProcess(VlProcessRef parentp) + explicit VlProcess(VlProcessRef parentp) : m_state{RUNNING} , m_parentp{parentp} { m_parentp->attach(this); @@ -591,6 +613,11 @@ public: m_deque.insert(m_deque.begin() + index, value); } + // inside (set membership operator) + bool inside(const T_Value& value) const { + return std::find(m_deque.begin(), m_deque.end(), value) != m_deque.end(); + } + // Return slice q[lsb:msb] VlQueue slice(int32_t lsb, int32_t msb) const { VlQueue out; @@ -1286,6 +1313,11 @@ public: bool operator==(const VlUnpacked& that) const { return !neq(that); } bool operator!=(const VlUnpacked& that) { return neq(that); } + // inside (set membership operator) + bool inside(const T_Value& value) const { + return std::find(std::begin(m_storage), std::end(m_storage), value) != std::end(m_storage); + } + void sort() { std::sort(std::begin(m_storage), std::end(m_storage)); } template void sort(Func with_func) { @@ -1499,7 +1531,7 @@ class VlDeleter final { // Queue of new objects that should be deleted std::vector m_newGarbage VL_GUARDED_BY(m_mutex); // Queue of objects currently being deleted (only for deleteAll()) - std::vector m_toDelete VL_GUARDED_BY(m_deleteMutex); + std::vector m_deleteNow VL_GUARDED_BY(m_deleteMutex); mutable VerilatedMutex m_mutex; // Mutex protecting the 'new garbage' queue mutable VerilatedMutex m_deleteMutex; // Mutex protecting the delete queue @@ -1534,12 +1566,15 @@ class VlClass VL_NOT_FINAL : public VlDeletable { friend class VlClassRef; // Needed for access to the ref counter and deleter // MEMBERS - std::atomic m_counter{0}; // Reference count for this object + std::atomic m_counter{1}; // Reference count for this object VlDeleter* m_deleterp = nullptr; // The deleter that will delete this object // METHODS // Atomically increments the reference counter - void refCountInc() VL_MT_SAFE { ++m_counter; } + void refCountInc() VL_MT_SAFE { + VL_DEBUG_IFDEF(assert(m_counter);); // If zero, we might have already deleted + ++m_counter; + } // Atomically decrements the reference counter. Assuming VlClassRef semantics are sound, it // should never get called at m_counter == 0. void refCountDec() VL_MT_SAFE { @@ -1548,8 +1583,8 @@ class VlClass VL_NOT_FINAL : public VlDeletable { public: // CONSTRUCTORS - VlClass() { refCountInc(); } - VlClass(const VlClass& copied) { refCountInc(); } + VlClass() {} + VlClass(const VlClass& copied) {} ~VlClass() override = default; }; @@ -1629,18 +1664,21 @@ public: // METHODS // Copy and move assignments VlClassRef& operator=(const VlClassRef& copied) { + if (m_objp == copied.m_objp) return *this; refCountDec(); m_objp = copied.m_objp; refCountInc(); return *this; } VlClassRef& operator=(VlClassRef&& moved) { + if (m_objp == moved.m_objp) return *this; refCountDec(); m_objp = vlstd::exchange(moved.m_objp, nullptr); return *this; } template VlClassRef& operator=(const VlClassRef& copied) { + if (m_objp == copied.m_objp) return *this; refCountDec(); m_objp = copied.m_objp; refCountInc(); @@ -1648,6 +1686,7 @@ public: } template VlClassRef& operator=(VlClassRef&& moved) { + if (m_objp == moved.m_objp) return *this; refCountDec(); m_objp = vlstd::exchange(moved.m_objp, nullptr); return *this; diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index e96840b2e..4de1aa9af 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index a81bae28a..40ea1608d 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -301,12 +301,12 @@ public: // Set time units (s/ms, defaults to ns) // Users should not need to call this, as for Verilated models, these - // propage from the Verilated default timeunit + // propagate from the Verilated default timeunit void set_time_unit(const char* unit) VL_MT_SAFE { m_sptrace.set_time_unit(unit); } void set_time_unit(const std::string& unit) VL_MT_SAFE { m_sptrace.set_time_unit(unit); } // Set time resolution (s/ms, defaults to ns) // Users should not need to call this, as for Verilated models, these - // propage from the Verilated default timeprecision + // propagate from the Verilated default timeprecision void set_time_resolution(const char* unit) VL_MT_SAFE { m_sptrace.set_time_resolution(unit); } void set_time_resolution(const std::string& unit) VL_MT_SAFE { m_sptrace.set_time_resolution(unit); diff --git a/include/verilated_vcd_sc.cpp b/include/verilated_vcd_sc.cpp index fa262cb0c..0e745e4e3 100644 --- a/include/verilated_vcd_sc.cpp +++ b/include/verilated_vcd_sc.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilated_vcd_sc.h b/include/verilated_vcd_sc.h index 53d5efe43..397a75db1 100644 --- a/include/verilated_vcd_sc.h +++ b/include/verilated_vcd_sc.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// Copyright 2001-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2001-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -12,8 +12,7 @@ /// \file /// \brief Verilated tracing in VCD format for SystemC header /// -/// User wrapper code should use this header when creating VCD SystemC -/// traces. +/// User wrapper code should use this header when creating VCD SystemC traces. /// /// This class is not threadsafe, as the SystemC kernel is not threadsafe. /// @@ -24,115 +23,35 @@ #include "verilatedos.h" -#include "verilated_sc.h" +#include "verilated_sc_trace.h" #include "verilated_vcd_c.h" -#include - //============================================================================= // VerilatedVcdSc -/// -/// Class representing a Verilator-friendly VCD trace format registered -/// with the SystemC simulation kernel, just like a SystemC-documented -/// trace format. +/// Trace file used to create VCD dump for SystemC version of Verilated models. It's very similar +/// to its C version (see the class VerilatedVcdC) -class VerilatedVcdSc final : sc_core::sc_trace_file, public VerilatedVcdC { +class VerilatedVcdSc final : VerilatedScTraceBase, public VerilatedVcdC { // CONSTRUCTORS VL_UNCOPYABLE(VerilatedVcdSc); public: - /// Construct a SC trace object, and register with the SystemC kernel VerilatedVcdSc() { - sc_core::sc_get_curr_simcontext()->add_trace_file(this); - // We want to avoid a depreciated warning, but still be back compatible. - // Turning off the message just for this still results in an - // annoying "to turn off" message. - const sc_core::sc_time t1sec{1, sc_core::SC_SEC}; - if (t1sec.to_default_time_units() != 0) { - const sc_core::sc_time tunits{1.0 / t1sec.to_default_time_units(), sc_core::SC_SEC}; - spTrace()->set_time_unit(tunits.to_string()); - } - spTrace()->set_time_resolution(sc_core::sc_get_time_resolution().to_string()); - } - /// Destruct, flush, and close the dump - ~VerilatedVcdSc() override { close(); } - - // METHODS - for SC kernel - // Called by SystemC simulate() - void cycle(bool delta_cycle) override { - if (!delta_cycle) this->dump(sc_core::sc_time_stamp().to_double()); + spTrace()->set_time_unit(VerilatedScTraceBase::getScTimeUnit()); + spTrace()->set_time_resolution(VerilatedScTraceBase::getScTimeResolution()); + VerilatedScTraceBase::enableDeltaCycles(false); } + // METHODS // Override VerilatedVcdC. Must be called after starting simulation. void open(const char* filename) override VL_MT_SAFE { - if (VL_UNLIKELY(!sc_core::sc_get_curr_simcontext()->elaboration_done())) { - Verilated::scTraceBeforeElaborationError(); - } + VerilatedScTraceBase::checkScElaborationDone(); VerilatedVcdC::open(filename); } -private: - // METHODS - Fake outs for linker - -#ifdef NC_SYSTEMC - // Cadence Incisive has these as abstract functions so we must create them - void set_time_unit(int exponent10_seconds) override {} // deprecated -#endif - void set_time_unit(double v, sc_core::sc_time_unit tu) override {} // LCOV_EXCL_LINE - - //-------------------------------------------------- - // SystemC 2.1.v1 - - void write_comment(const std::string&) override {} - void trace(const unsigned int&, const std::string&, const char**) override {} - -#define DECL_TRACE_METHOD_A(tp) \ - void trace(const tp& object, const std::string& name) override {} -#define DECL_TRACE_METHOD_B(tp) \ - void trace(const tp& object, const std::string& name, int width) override {} - - // clang-format off - // Formatting matches that of sc_trace.h - // LCOV_EXCL_START -#if (SYSTEMC_VERSION >= 20171012) - DECL_TRACE_METHOD_A( sc_core::sc_event ) - DECL_TRACE_METHOD_A( sc_core::sc_time ) -#endif - - DECL_TRACE_METHOD_A( bool ) - DECL_TRACE_METHOD_A( sc_dt::sc_bit ) - DECL_TRACE_METHOD_A( sc_dt::sc_logic ) - - DECL_TRACE_METHOD_B( unsigned char ) - DECL_TRACE_METHOD_B( unsigned short ) - DECL_TRACE_METHOD_B( unsigned int ) - DECL_TRACE_METHOD_B( unsigned long ) - DECL_TRACE_METHOD_B( char ) - DECL_TRACE_METHOD_B( short ) - DECL_TRACE_METHOD_B( int ) - DECL_TRACE_METHOD_B( long ) - DECL_TRACE_METHOD_B( sc_dt::int64 ) - DECL_TRACE_METHOD_B( sc_dt::uint64 ) - - DECL_TRACE_METHOD_A( float ) - DECL_TRACE_METHOD_A( double ) - DECL_TRACE_METHOD_A( sc_dt::sc_int_base ) - DECL_TRACE_METHOD_A( sc_dt::sc_uint_base ) - DECL_TRACE_METHOD_A( sc_dt::sc_signed ) - DECL_TRACE_METHOD_A( sc_dt::sc_unsigned ) - - DECL_TRACE_METHOD_A( sc_dt::sc_fxval ) - DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast ) - DECL_TRACE_METHOD_A( sc_dt::sc_fxnum ) - DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast ) - - DECL_TRACE_METHOD_A( sc_dt::sc_bv_base ) - DECL_TRACE_METHOD_A( sc_dt::sc_lv_base ) - // LCOV_EXCL_STOP - // clang-format on - -#undef DECL_TRACE_METHOD_A -#undef DECL_TRACE_METHOD_B + // METHODS - for SC kernel + // Called from SystemC kernel + void cycle() override { VerilatedVcdC::dump(sc_core::sc_time_stamp().to_double()); } }; #endif // Guard diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 3bab69be0..80cee6346 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -120,6 +120,7 @@ public: virtual const char* fullname() const { return ""; } virtual const char* defname() const { return ""; } virtual uint32_t type() const { return 0; } + virtual uint32_t constType() const { return vpiUndefined; } virtual uint32_t size() const { return 0; } virtual const VerilatedRange* rangep() const { return nullptr; } virtual vpiHandle dovpi_scan() { return nullptr; } @@ -158,6 +159,7 @@ public: return dynamic_cast(reinterpret_cast(h)); } uint32_t type() const override { return vpiConstant; } + uint32_t constType() const override { return vpiDecConst; } int32_t num() const { return m_num; } }; @@ -204,6 +206,18 @@ public: return dynamic_cast(reinterpret_cast(h)); } uint32_t type() const override { return vpiParameter; } + uint32_t constType() const override { + switch (m_varp->vltype()) { + case VLVT_UINT8: + case VLVT_UINT16: + case VLVT_UINT32: + case VLVT_UINT64: + case VLVT_WDATA: return vpiDecConst; + case VLVT_STRING: return vpiStringConst; + case VLVT_REAL: return vpiRealConst; + default: return vpiUndefined; + } + } void* varDatap() const { return m_varp->datap(); } }; @@ -248,10 +262,26 @@ public: class VerilatedVpioScope VL_NOT_FINAL : public VerilatedVpio { protected: const VerilatedScope* const m_scopep; + bool m_toplevel = false; public: explicit VerilatedVpioScope(const VerilatedScope* scopep) - : m_scopep{scopep} {} + : m_scopep{scopep} { + std::string scopename = m_scopep->name(); + std::string::size_type pos = std::string::npos; + // Look for '.' not inside escaped identifier + size_t i = 0; + while (i < scopename.length()) { + if (scopename[i] == '\\') { + while (i < scopename.length() && scopename[i] != ' ') ++i; + ++i; // Proc ' ', it should always be there. Then grab '.' on next cycle + } else { + while (i < scopename.length() && scopename[i] != '.') ++i; + if (i < scopename.length()) pos = i++; + } + } + if (VL_UNLIKELY(pos == std::string::npos)) m_toplevel = true; + } ~VerilatedVpioScope() override = default; static VerilatedVpioScope* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); @@ -260,6 +290,7 @@ public: const VerilatedScope* scopep() const { return m_scopep; } const char* name() const override { return m_scopep->name(); } const char* fullname() const override { return m_scopep->name(); } + bool toplevel() const { return m_toplevel; } }; class VerilatedVpioVar VL_NOT_FINAL : public VerilatedVpioVarBase { @@ -350,17 +381,28 @@ class VerilatedVpioVarIter final : public VerilatedVpio { const VerilatedScope* const m_scopep; VerilatedVarNameMap::const_iterator m_it; bool m_started = false; + const VerilatedScope* m_topscopep = nullptr; + bool m_onlyParams; public: - explicit VerilatedVpioVarIter(const VerilatedScope* scopep) - : m_scopep{scopep} {} + explicit VerilatedVpioVarIter(const VerilatedVpioScope* vop, bool onlyParams = false) + : m_scopep{vop->scopep()} + , m_onlyParams{onlyParams} { + if (VL_UNLIKELY(vop->toplevel())) + // This is a toplevel, so get TOP scope to search for ports during vpi_scan. + m_topscopep = Verilated::threadContextp()->scopeFind("TOP"); + } ~VerilatedVpioVarIter() override = default; static VerilatedVpioVarIter* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } uint32_t type() const override { return vpiIterator; } vpiHandle dovpi_scan() override { - if (VL_LIKELY(m_scopep->varsp())) { + if (VL_UNLIKELY(!m_scopep->varsp())) { + delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle + return nullptr; // End of list - only one deep + } + while (true) { const VerilatedVarNameMap* const varsp = m_scopep->varsp(); if (VL_UNLIKELY(!m_started)) { m_it = varsp->begin(); @@ -375,10 +417,13 @@ public: delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle return nullptr; } + if (m_onlyParams && !m_it->second.isParam()) continue; + if (VL_UNLIKELY(m_topscopep)) { + if (const VerilatedVar* topvarp = m_topscopep->varFind(m_it->second.name())) + return ((new VerilatedVpioVar{topvarp, m_topscopep})->castVpiHandle()); + } return ((new VerilatedVpioVar{&(m_it->second), m_scopep})->castVpiHandle()); } - delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle - return nullptr; // End of list - only one deep } }; @@ -448,12 +493,71 @@ public: } uint32_t type() const override { return vpiIterator; } vpiHandle dovpi_scan() override { - if (m_it == m_vec->end()) { - delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle - return nullptr; + while (true) { + if (m_it == m_vec->end()) { + delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle + return nullptr; + } + const VerilatedScope::Type type = (*m_it)->type(); + const VerilatedScope* const modp = *m_it++; + if (type == VerilatedScope::SCOPE_MODULE) { + return (new VerilatedVpioModule{modp})->castVpiHandle(); + } + } + } +}; + +class VerilatedVpioPackage final : public VerilatedVpioScope { + std::string m_name; + std::string m_fullname; + +public: + explicit VerilatedVpioPackage(const VerilatedScope* modulep) + : VerilatedVpioScope{modulep} { + const char* fullname = m_scopep->name(); + if (std::strncmp(fullname, "TOP.", 4) == 0) fullname += 4; + m_fullname = std::string{fullname} + "::"; + if (m_fullname == "\\$unit ::") m_fullname = "$unit::"; + m_name = std::string(m_scopep->identifier()); + if (m_name == "\\$unit ") m_name = "$unit"; + } + static VerilatedVpioPackage* castp(vpiHandle h) { + return dynamic_cast(reinterpret_cast(h)); + } + uint32_t type() const override { return vpiPackage; } + const char* name() const override { return m_name.c_str(); } + const char* fullname() const override { return m_fullname.c_str(); } +}; + +class VerilatedVpioInstanceIter final : public VerilatedVpio { + const std::vector* m_vec; + std::vector::const_iterator m_it; + +public: + explicit VerilatedVpioInstanceIter(const std::vector& vec) + : m_vec{&vec} { + m_it = m_vec->begin(); + } + ~VerilatedVpioInstanceIter() override = default; + static VerilatedVpioInstanceIter* castp(vpiHandle h) { + return dynamic_cast(reinterpret_cast(h)); + } + uint32_t type() const override { return vpiIterator; } + vpiHandle dovpi_scan() override { + while (true) { + if (m_it == m_vec->end()) { + delete this; // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle + return nullptr; + } + const VerilatedScope::Type type = (*m_it)->type(); + const VerilatedScope* const modp = *m_it++; + if (type == VerilatedScope::SCOPE_MODULE) { + return (new VerilatedVpioModule{modp})->castVpiHandle(); + } + if (type == VerilatedScope::SCOPE_PACKAGE) { + return (new VerilatedVpioPackage{modp})->castVpiHandle(); + } } - const VerilatedScope* const modp = *m_it++; - return (new VerilatedVpioModule{modp})->castVpiHandle(); } }; @@ -1640,37 +1744,61 @@ vpiHandle vpi_handle_by_name(PLI_BYTE8* namep, vpiHandle scope) { const VerilatedVpioScope* const voScopep = VerilatedVpioScope::castp(scope); std::string scopeAndName = namep; if (voScopep) { - scopeAndName = std::string{voScopep->fullname()} + "." + namep; + const bool scopeIsPackage = VerilatedVpioPackage::castp(scope) != nullptr; + scopeAndName = std::string{voScopep->fullname()} + (scopeIsPackage ? "" : ".") + namep; namep = const_cast(scopeAndName.c_str()); } { // This doesn't yet follow the hierarchy in the proper way + bool isPackage = false; scopep = Verilated::threadContextp()->scopeFind(namep); if (scopep) { // Whole thing found as a scope if (scopep->type() == VerilatedScope::SCOPE_MODULE) { return (new VerilatedVpioModule{scopep})->castVpiHandle(); + } else if (scopep->type() == VerilatedScope::SCOPE_PACKAGE) { + return (new VerilatedVpioPackage{scopep})->castVpiHandle(); } else { return (new VerilatedVpioScope{scopep})->castVpiHandle(); } } - const char* baseNamep = scopeAndName.c_str(); + std::string basename = scopeAndName; std::string scopename; - const char* const dotp = std::strrchr(namep, '.'); - if (VL_LIKELY(dotp)) { - baseNamep = dotp + 1; - const size_t len = dotp - namep; - scopename = std::string{namep, len}; + std::string::size_type prevpos = std::string::npos; + std::string::size_type pos = std::string::npos; + // Split hierarchical names at last '.' not inside escaped identifier + size_t i = 0; + while (i < scopeAndName.length()) { + if (scopeAndName[i] == '\\') { + while (i < scopeAndName.length() && scopeAndName[i] != ' ') ++i; + ++i; // Proc ' ', it should always be there. Then grab '.' on next cycle + } else { + while (i < scopeAndName.length() + && (scopeAndName[i] != '.' + && (i + 1 >= scopeAndName.length() || scopeAndName[i] != ':' + || scopeAndName[i + 1] != ':'))) + ++i; + if (i < scopeAndName.length()) { + prevpos = pos; + pos = i++; + if (scopeAndName[i - 1] == ':') isPackage = true; + } + } } - - if (scopename.find('.') == std::string::npos) { - // This is a toplevel, hence search in our TOP ports first. + // Do the split + if (VL_LIKELY(pos != std::string::npos)) { + basename.erase(0, pos + (isPackage ? 2 : 1)); + scopename = scopeAndName.substr(0, pos); + if (scopename == "$unit") scopename = "\\$unit "; + } + if (prevpos == std::string::npos) { + // scopename is a toplevel (no '.' separator), so search in our TOP ports first. scopep = Verilated::threadContextp()->scopeFind("TOP"); - if (scopep) varp = scopep->varFind(baseNamep); + if (scopep) varp = scopep->varFind(basename.c_str()); } if (!varp) { scopep = Verilated::threadContextp()->scopeFind(scopename.c_str()); if (!scopep) return nullptr; - varp = scopep->varFind(baseNamep); + varp = scopep->varFind(basename.c_str()); } } if (!varp) return nullptr; @@ -1807,7 +1935,12 @@ vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) { case vpiReg: { const VerilatedVpioScope* const vop = VerilatedVpioScope::castp(object); if (VL_UNLIKELY(!vop)) return nullptr; - return ((new VerilatedVpioVarIter{vop->scopep()})->castVpiHandle()); + return ((new VerilatedVpioVarIter{vop})->castVpiHandle()); + } + case vpiParameter: { + const VerilatedVpioScope* const vop = VerilatedVpioScope::castp(object); + if (VL_UNLIKELY(!vop)) return nullptr; + return ((new VerilatedVpioVarIter{vop, true})->castVpiHandle()); } case vpiModule: { const VerilatedVpioModule* const vop = VerilatedVpioModule::castp(object); @@ -1817,6 +1950,13 @@ vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) { if (it == map->end()) return nullptr; return ((new VerilatedVpioModuleIter{it->second})->castVpiHandle()); } + case vpiInstance: { + if (object) return nullptr; + const VerilatedHierarchyMap* const map = VerilatedImp::hierarchyMap(); + const auto it = vlstd::as_const(map)->find(nullptr); + if (it == map->end()) return nullptr; + return ((new VerilatedVpioInstanceIter{it->second})->castVpiHandle()); + } default: VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", __func__, VerilatedVpiError::strFromVpiObjType(type)); @@ -1854,6 +1994,11 @@ PLI_INT32 vpi_get(PLI_INT32 property, vpiHandle object) { if (VL_UNLIKELY(!vop)) return 0; return vop->type(); } + case vpiConstType: { + const VerilatedVpio* const vop = VerilatedVpio::castp(object); + if (VL_UNLIKELY(!vop)) return 0; + return vop->constType(); + } case vpiDirection: { // By forethought, the directions already are vpi enumerated const VerilatedVpioVarBase* const vop = VerilatedVpioVarBase::castp(object); diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h index b642d46a1..ab805fb89 100644 --- a/include/verilated_vpi.h +++ b/include/verilated_vpi.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2009-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2009-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/include/verilatedos.h b/include/verilatedos.h index a3a515518..57e7b8e9c 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -3,7 +3,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -138,7 +138,7 @@ // Defaults for unsupported compiler features #ifndef VL_ATTR_ALWINLINE -# define VL_ATTR_ALWINLINE ///< Attribute to inline, even when not optimizing +# define VL_ATTR_ALWINLINE inline ///< Attribute to inline, even when not optimizing #endif #ifndef VL_ATTR_NOINLINE # define VL_ATTR_NOINLINE ///< Attribute to never inline, even when optimizing @@ -258,11 +258,11 @@ #endif //========================================================================= -// C++-2011 +// C++-2014 -#if __cplusplus >= 201103L || defined(__GXX_EXPERIMENTAL_CXX0X__) || defined(VL_CPPCHECK) || defined(_MSC_VER) +#if __cplusplus >= 201402L || defined(__GXX_EXPERIMENTAL_CXX0X__) || defined(VL_CPPCHECK) || defined(_MSC_VER) #else -# error "Verilator requires a C++11 or newer compiler" +# error "Verilator requires a C++14 or newer compiler" #endif #ifndef VL_NO_LEGACY @@ -450,7 +450,7 @@ using ssize_t = uint32_t; ///< signed size_t; returned from read() //========================================================================= // Verilated function size macros -#define VL_MULS_MAX_WORDS 16 ///< Max size in words of MULS operation +#define VL_MULS_MAX_WORDS 128 ///< Max size in words of MULS operation #ifndef VL_VALUE_STRING_MAX_WORDS #define VL_VALUE_STRING_MAX_WORDS 64 ///< Max size in words of String conversion operation diff --git a/nodist/clang_check_attributes b/nodist/clang_check_attributes index 8fd0f8ea7..682cd7e72 100755 --- a/nodist/clang_check_attributes +++ b/nodist/clang_check_attributes @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # pylint: disable=C0114,C0115,C0116,C0209,C0302,R0902,R0911,R0912,R0914,R0915,E1101 # -# Copyright 2022-2023 by Wilson Snyder. Verilator is free software; you +# Copyright 2022-2024 by Wilson Snyder. Verilator is free software; you # can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Apache License 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Apache-2.0 @@ -1128,7 +1128,7 @@ def main(): formatter_class=argparse.RawDescriptionHelpFormatter, description="""Check function annotations for correctness""", epilog= - """Copyright 2022-2023 by Wilson Snyder. Verilator is free software; + """Copyright 2022-2024 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Apache License 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Apache-2.0""") diff --git a/nodist/code_coverage b/nodist/code_coverage index 5eb472bc3..656328b2f 100755 --- a/nodist/code_coverage +++ b/nodist/code_coverage @@ -348,7 +348,7 @@ files. Run as: cd $VERILATOR_ROOT nodist/code_coverage""", epilog= - """Copyright 2019-2023 by Wilson Snyder. This program is free software; you + """Copyright 2019-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/nodist/code_coverage.dat b/nodist/code_coverage.dat index d655d2179..0fd860a54 100644 --- a/nodist/code_coverage.dat +++ b/nodist/code_coverage.dat @@ -1,7 +1,7 @@ # -*- Python -*- # DESCRIPTION: Verilator: Internal C++ code lcov control file # -# Copyright 2019-2023 by Wilson Snyder. This program is free software; you +# Copyright 2019-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/nodist/dot_importer b/nodist/dot_importer index 970665d07..c2a8215fe 100755 --- a/nodist/dot_importer +++ b/nodist/dot_importer @@ -87,7 +87,7 @@ parser = argparse.ArgumentParser( This x.cpp file is then manually included in V3GraphTest.cpp to verify various xsub-algorithms.""", epilog= - """Copyright 2005-2023 by Wilson Snyder. This program is free software; you + """Copyright 2005-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/nodist/install_test b/nodist/install_test index 3929d825b..cfb9afebb 100755 --- a/nodist/install_test +++ b/nodist/install_test @@ -118,7 +118,7 @@ parser = argparse.ArgumentParser( Verilator kit. It isn't part of the normal "make test" due to the number of builds required.""", epilog= - """Copyright 2009-2023 by Wilson Snyder. This program is free software; you + """Copyright 2009-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/src/.gdbinit b/src/.gdbinit index b6c6c40a3..df31f80f4 100644 --- a/src/.gdbinit +++ b/src/.gdbinit @@ -1,6 +1,6 @@ # DESCRIPTION: Verilator: GDB startup file with useful defines # -# Copyright 2012-2023 by Wilson Snyder. This program is free software; you +# Copyright 2012-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index fdf215082..61c05a21d 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -4,7 +4,7 @@ # #***************************************************************************** # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -282,6 +282,7 @@ set(COMMON_SOURCES V3SchedPartition.cpp V3SchedReplicate.cpp V3SchedTiming.cpp + V3SchedVirtIface.cpp V3Scope.cpp V3Scoreboard.cpp V3Slice.cpp @@ -466,7 +467,7 @@ set_target_properties(${verilator} PROPERTIES #UNITY_BUILD $,FALSE,${CMAKE_UNITY_BUILD}> MSVC_RUNTIME_LIBRARY MultiThreaded$,,DebugDLL> #JOB_POOL_LINK one_job # Linking takes lots of resources - INTERPROCEDURAL_OPTIMIZATION_RELEASE TRUE + INTERPROCEDURAL_OPTIMIZATION_RELEASE $ ) add_dependencies(${verilator} @@ -501,13 +502,19 @@ target_include_directories(${verilator} ) if (WIN32) - target_compile_options(${verilator} PRIVATE /bigobj) + if(MINGW) + target_compile_options(${verilator} PRIVATE -Wa,-mbig-obj) + target_link_options(${verilator} PRIVATE -Wl,--stack,10000000 -mconsole -lcomctl32 -DWIN_32_LEAN_AND_MEAN) + else() + target_compile_options(${verilator} PRIVATE /bigobj) + target_link_options(${verilator} PRIVATE /STACK:10000000) + endif() + target_compile_definitions(${verilator} PRIVATE YY_NO_UNISTD_H ) target_include_directories(${verilator} PRIVATE ../platform/win32) target_link_libraries(${verilator} PRIVATE bcrypt psapi) - target_link_options(${verilator} PRIVATE /STACK:10000000) endif() install(TARGETS ${verilator}) diff --git a/src/Makefile.in b/src/Makefile.in index 9a77cfbf1..29172e1eb 100644 --- a/src/Makefile.in +++ b/src/Makefile.in @@ -7,7 +7,7 @@ # #***************************************************************************** # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index 8c79c0066..857ce1c7b 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -7,7 +7,7 @@ # #***************************************************************************** # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -274,6 +274,7 @@ RAW_OBJS_PCH_ASTNOMT = \ V3SchedPartition.o \ V3SchedReplicate.o \ V3SchedTiming.o \ + V3SchedVirtIface.o \ V3Scope.o \ V3Scoreboard.o \ V3Slice.o \ diff --git a/src/V3Active.cpp b/src/V3Active.cpp index 4930b9293..800205664 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -125,8 +125,6 @@ public: // METHODS void begin() { // Start a new if/else tracking graph - // See NODE STATE comment in ActiveLatchCheckVisitor - AstNode::user1ClearTree(); m_curVertexp = new LatchDetectGraphVertex{this, "ROOT"}; } // Clear out userp field of referenced outputs on destruction @@ -197,7 +195,6 @@ public: // Collect existing active names class ActiveNamer final : public VNVisitor { -private: // STATE AstScope* m_scopep = nullptr; // Current scope to add statement to AstActive* m_sActivep = nullptr; // For current scope, the Static active we're building @@ -308,7 +305,6 @@ AstActive*& ActiveNamer::getSpecialActive() { // Latch checking visitor class ActiveLatchCheckVisitor final : public VNVisitorConst { -private: // NODE STATE // Input: // AstVar::user1p // V2LatchGraphVertex* The vertex handling this node @@ -425,7 +421,6 @@ public: // Active class functions class ActiveVisitor final : public VNVisitor { -private: // NODE STATE // Each call to V3Const::constify // AstVarScope::user1() bool: This VarScope is referenced in the sensitivity list diff --git a/src/V3Active.h b/src/V3Active.h index 090d7b019..b1ec9db2d 100644 --- a/src/V3Active.h +++ b/src/V3Active.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ActiveTop.cpp b/src/V3ActiveTop.cpp index 4239525b9..fb59ecc0b 100644 --- a/src/V3ActiveTop.cpp +++ b/src/V3ActiveTop.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ActiveTop.h b/src/V3ActiveTop.h index ae3821112..6abd1e078 100644 --- a/src/V3ActiveTop.h +++ b/src/V3ActiveTop.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index f99a9ced8..508e33e5f 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -26,7 +26,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Assert class functions class AssertVisitor final : public VNVisitor { -private: // NODE STATE/TYPES // Cleared on netlist // AstNode::user() -> bool. True if processed diff --git a/src/V3Assert.h b/src/V3Assert.h index f345c2e27..d3362e5c6 100644 --- a/src/V3Assert.h +++ b/src/V3Assert.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index c06f3b93f..40803b5c4 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3AssertPre.h b/src/V3AssertPre.h index dc58f6054..2c87823c9 100644 --- a/src/V3AssertPre.h +++ b/src/V3AssertPre.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index 973814442..1948e60ff 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -97,18 +97,17 @@ AstNode* AstNode::abovep() const { string AstNode::encodeName(const string& namein) { // Encode signal name raw from parser, then not called again on same signal string out; - for (string::const_iterator pos = namein.begin(); pos != namein.end(); ++pos) { + out.reserve(namein.size()); + for (auto pos = namein.begin(); pos != namein.end(); ++pos) { if ((pos == namein.begin()) ? std::isalpha(pos[0]) // digits can't lead identifiers : std::isalnum(pos[0])) { out += pos[0]; } else if (pos[0] == '_') { + out += pos[0]; + if (pos + 1 == namein.end()) break; if (pos[1] == '_') { - out += "_"; - out += "__05F"; // hex(_) = 0x5F ++pos; - if (pos == namein.end()) break; - } else { - out += pos[0]; + out += "__05F"; // hex(_) = 0x5F } } else { // Need the leading 0 so this will never collide with @@ -1238,7 +1237,7 @@ void AstNode::dumpPtrs(std::ostream& os) const { // This may cause address sanitizer failures as iterpp can be stale // os << "*=" << cvtToHex(*m_iterpp); } - os << std::endl; + os << "\n"; } void AstNode::dumpTree(std::ostream& os, const string& indent, int maxDepth) const { @@ -1274,12 +1273,12 @@ void AstNode::dumpTreeAndNext(std::ostream& os, const string& indent, int maxDep } } -void AstNode::dumpTreeFile(const string& filename, bool append, bool doDump, bool doCheck) { +void AstNode::dumpTreeFile(const string& filename, bool doDump, bool doCheck) { // Not const function as calls checkTree if (doDump) { { // Write log & close UINFO(2, "Dumping " << filename << endl); - const std::unique_ptr logsp{V3File::new_ofstream(filename, append)}; + const std::unique_ptr logsp{V3File::new_ofstream(filename)}; if (logsp->fail()) v3fatal("Can't write " << filename); *logsp << "Verilator Tree Dump (format 0x3900) from to \n"; @@ -1329,10 +1328,10 @@ void AstNode::dumpTreeDot(std::ostream& os) const { drawChildren(os, this, m_op4p, "op4"); } -void AstNode::dumpTreeDotFile(const string& filename, bool append, bool doDump) { +void AstNode::dumpTreeDotFile(const string& filename, bool doDump) { if (doDump) { UINFO(2, "Dumping " << filename << endl); - const std::unique_ptr treedotp{V3File::new_ofstream(filename, append)}; + const std::unique_ptr treedotp{V3File::new_ofstream(filename)}; if (treedotp->fail()) v3fatal("Can't write " << filename); *treedotp << "digraph vTree{\n"; *treedotp << "\tgraph\t[label=\"" << filename + ".dot" @@ -1448,18 +1447,21 @@ AstNodeDType* AstNode::findBitRangeDType(const VNumRange& range, int widthMin, AstBasicDType* AstNode::findInsertSameDType(AstBasicDType* nodep) { return v3Global.rootp()->typeTablep()->findInsertSameDType(nodep); } +AstNodeDType* AstNode::findConstraintRefDType() const { + return v3Global.rootp()->typeTablep()->findConstraintRefDType(fileline()); +} AstNodeDType* AstNode::findEmptyQueueDType() const { return v3Global.rootp()->typeTablep()->findEmptyQueueDType(fileline()); } AstNodeDType* AstNode::findQueueIndexDType() const { return v3Global.rootp()->typeTablep()->findQueueIndexDType(fileline()); } -AstNodeDType* AstNode::findVoidDType() const { - return v3Global.rootp()->typeTablep()->findVoidDType(fileline()); -} AstNodeDType* AstNode::findStreamDType() const { return v3Global.rootp()->typeTablep()->findStreamDType(fileline()); } +AstNodeDType* AstNode::findVoidDType() const { + return v3Global.rootp()->typeTablep()->findVoidDType(fileline()); +} static const AstNodeDType* computeCastableBase(const AstNodeDType* nodep) { while (true) { diff --git a/src/V3Ast.h b/src/V3Ast.h index d2bb7068f..71ec84aa0 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -107,6 +107,7 @@ struct VNTypeInfo { OP_OPTIONAL, } m_opType[4]; const char* m_opNamep[4]; + size_t m_sizeof; }; class VNType final { @@ -757,11 +758,15 @@ public: bool isRef() const VL_MT_SAFE { return m_e == REF; } bool isConstRef() const VL_MT_SAFE { return m_e == CONSTREF; } }; -constexpr bool operator==(const VDirection& lhs, const VDirection& rhs) { +constexpr bool operator==(const VDirection& lhs, const VDirection& rhs) VL_MT_SAFE { return lhs.m_e == rhs.m_e; } -constexpr bool operator==(const VDirection& lhs, VDirection::en rhs) { return lhs.m_e == rhs; } -constexpr bool operator==(VDirection::en lhs, const VDirection& rhs) { return lhs == rhs.m_e; } +constexpr bool operator==(const VDirection& lhs, VDirection::en rhs) VL_MT_SAFE { + return lhs.m_e == rhs; +} +constexpr bool operator==(VDirection::en lhs, const VDirection& rhs) VL_MT_SAFE { + return lhs == rhs.m_e; +} inline std::ostream& operator<<(std::ostream& os, const VDirection& rhs) { return os << rhs.ascii(); } @@ -1456,7 +1461,6 @@ public: // string 'this', or 'vlSymsp->...' class VSelfPointerText final { -private: // STATIC MEMBERS // Keep these in shared pointers to avoid branching for special cases static const std::shared_ptr s_emptyp; // Holds "" @@ -1468,10 +1472,10 @@ private: public: // CONSTRUCTORS class Empty {}; // for creator type-overload selection - VSelfPointerText(Empty) + explicit VSelfPointerText(Empty) : m_strp{s_emptyp} {} class This {}; // for creator type-overload selection - VSelfPointerText(This) + explicit VSelfPointerText(This) : m_strp{s_thisp} {} VSelfPointerText(This, const string& field) : m_strp{std::make_shared("this->" + field)} {} @@ -1853,7 +1857,8 @@ protected: // CONSTRUCTORS AstNode(VNType t, FileLine* fl); virtual AstNode* clone() = 0; // Generally, cloneTree is what you want instead - virtual void cloneRelink() {} + virtual void cloneRelink() { cloneRelinkGen(); } + virtual void cloneRelinkGen() = 0; // Generated by 'astgen' void cloneRelinkTree(); // METHODS @@ -1949,7 +1954,7 @@ public: static constexpr int INSTR_COUNT_PLI = 20; // PLI routines // ACCESSORS - virtual string name() const { return ""; } + virtual string name() const VL_MT_STABLE { return ""; } virtual string origName() const { return ""; } virtual void name(const string& name) { this->v3fatalSrc("name() called on object without name() method"); @@ -2117,8 +2122,8 @@ public: void dtypeSetUInt32() { dtypep(findUInt32DType()); } // Twostate void dtypeSetUInt64() { dtypep(findUInt64DType()); } // Twostate void dtypeSetEmptyQueue() { dtypep(findEmptyQueueDType()); } - void dtypeSetVoid() { dtypep(findVoidDType()); } void dtypeSetStream() { dtypep(findStreamDType()); } + void dtypeSetVoid() { dtypep(findVoidDType()); } // Data type locators AstNodeDType* findBitDType() const { return findBasicDType(VBasicDTypeKwd::LOGIC); } @@ -2128,10 +2133,11 @@ public: AstNodeDType* findUInt32DType() const { return findBasicDType(VBasicDTypeKwd::UINT32); } AstNodeDType* findUInt64DType() const { return findBasicDType(VBasicDTypeKwd::UINT64); } AstNodeDType* findCHandleDType() const { return findBasicDType(VBasicDTypeKwd::CHANDLE); } + AstNodeDType* findConstraintRefDType() const; AstNodeDType* findEmptyQueueDType() const; - AstNodeDType* findVoidDType() const; - AstNodeDType* findStreamDType() const; AstNodeDType* findQueueIndexDType() const; + AstNodeDType* findStreamDType() const; + AstNodeDType* findVoidDType() const; AstNodeDType* findBitDType(int width, int widthMin, VSigning numeric) const; AstNodeDType* findLogicDType(int width, int widthMin, VSigning numeric) const; AstNodeDType* findLogicRangeDType(const VNumRange& range, int widthMin, @@ -2206,11 +2212,10 @@ public: static void dumpTreeGdb(const AstNode* nodep); // For GDB only void dumpTreeAndNext(std::ostream& os = std::cout, const string& indent = " ", int maxDepth = 0) const; - void dumpTreeFile(const string& filename, bool append = false, bool doDump = true, - bool doCheck = true); + void dumpTreeFile(const string& filename, bool doDump = true, bool doCheck = true); static void dumpTreeFileGdb(const AstNode* nodep, const char* filenamep = nullptr); void dumpTreeDot(std::ostream& os = std::cout) const; - void dumpTreeDotFile(const string& filename, bool append = false, bool doDump = true); + void dumpTreeDotFile(const string& filename, bool doDump = true); // METHODS - static advancement static AstNode* afterCommentp(AstNode* nodep) { @@ -2244,7 +2249,7 @@ public: // statement is unlikely to be taken virtual bool isUnlikely() const { return false; } virtual int instrCount() const { return 0; } - // Iff node is identical to anouther node + // Iff node is identical to another node virtual bool isSame(const AstNode* samep) const { return type() == samep->type() && same(samep); } @@ -2260,6 +2265,8 @@ public: virtual bool undead() const { return false; } // Check if node is consistent, return nullptr if ok, else reason string virtual const char* broken() const { return nullptr; } + // Generated by 'astgen'. Calls 'broken()', which can be used to add extra checks + virtual const char* brokenGen() const = 0; // Generated by 'astgen' // INVOKERS virtual void accept(VNVisitorConst& v) = 0; diff --git a/src/V3AstInlines.h b/src/V3AstInlines.h index f47aa7be8..9e61a7740 100644 --- a/src/V3AstInlines.h +++ b/src/V3AstInlines.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h index dd5efe25d..a179a011b 100644 --- a/src/V3AstNodeDType.h +++ b/src/V3AstNodeDType.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,7 +34,6 @@ class AstNodeDType VL_NOT_FINAL : public AstNode { // Ideally width() would migrate to BasicDType as that's where it makes sense, // but it's currently so prevalent in the code we leave it here. // Note the below members are included in AstTypeTable::Key lookups -private: int m_width = 0; // (also in AstTypeTable::Key) Bit width of operation int m_widthMin = 0; // (also in AstTypeTable::Key) If unsized, bitwidth of minimum implementation @@ -138,9 +137,8 @@ class AstNodeArrayDType VL_NOT_FINAL : public AstNodeDType { // Array data type, ie "some_dtype var_name [2:0]" // @astgen op1 := childDTypep : Optional[AstNodeDType] // moved to refDTypep() in V3Width // @astgen op2 := rangep : Optional[AstRange] // array bounds -private: - AstNodeDType* m_refDTypep = nullptr; // Elements of this type (after widthing) - + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Elements of this type (post-width) AstNode* rangenp() const { return reinterpret_cast(rangep()); } protected: @@ -152,13 +150,9 @@ public: void dump(std::ostream& str) const override; void dumpSmall(std::ostream& str) const override; const char* broken() const override { - BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) - || (!m_refDTypep && childDTypep()))); + BROKEN_RTN(!((m_refDTypep && !childDTypep()) || (!m_refDTypep && childDTypep()))); return nullptr; } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - } bool same(const AstNode* samep) const override { const AstNodeArrayDType* const asamep = VN_DBG_AS(samep, NodeArrayDType); return (hi() == asamep->hi() && subDTypep() == asamep->subDTypep() @@ -198,10 +192,9 @@ public: class AstNodeUOrStructDType VL_NOT_FINAL : public AstNodeDType { // A struct or union; common handling // @astgen op1 := membersp : List[AstMemberDType] -private: - // MEMBERS + // + // @astgen ptr := m_classOrPackagep : Optional[AstNodeModule] // Package emitted with string m_name; // Name from upper typedef, if any - AstNodeModule* m_classOrPackagep = nullptr; // Package it will be emitted with const int m_uniqueNum; bool m_packed; bool m_isFourstate = false; // V3Width computes @@ -218,7 +211,6 @@ protected: public: ASTGEN_MEMBERS_AstNodeUOrStructDType; int uniqueNum() const { return m_uniqueNum; } - const char* broken() const override; void dump(std::ostream& str) const override; bool isCompound() const override { return !packed(); } // For basicp() we reuse the size to indicate a "fake" basic type of same size @@ -260,7 +252,6 @@ public: class AstEnumItem final : public AstNode { // @astgen op1 := rangep : Optional[AstRange] // Range for name appending // @astgen op2 := valuep : Optional[AstNodeExpr] -private: string m_name; public: @@ -283,9 +274,9 @@ class AstAssocArrayDType final : public AstNodeDType { // Associative array data type, ie "[some_dtype]" // @astgen op1 := childDTypep : Optional[AstNodeDType] // moved to refDTypep() in V3Width // @astgen op2 := keyChildDTypep : Optional[AstNodeDType] -private: - AstNodeDType* m_refDTypep; // Elements of this type (after widthing) - AstNodeDType* m_keyDTypep; // Keys of this type (after widthing) + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Elements of this type (post-width) + // @astgen ptr := m_keyDTypep : Optional[AstNodeDType] // Keys of this type (post-width) public: AstAssocArrayDType(FileLine* fl, VFlagChildDType, AstNodeDType* dtp, AstNodeDType* keyDtp) : ASTGEN_SUPER_AssocArrayDType(fl) { @@ -303,16 +294,10 @@ public: } ASTGEN_MEMBERS_AstAssocArrayDType; const char* broken() const override { - BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) - || (!m_refDTypep && childDTypep()))); - BROKEN_RTN(!((m_keyDTypep && !childDTypep() && m_keyDTypep->brokeExists()) - || (!m_keyDTypep && childDTypep()))); + BROKEN_RTN(!((m_refDTypep && !childDTypep()) || (!m_refDTypep && childDTypep()))); + BROKEN_RTN(!((m_keyDTypep && !childDTypep()) || (!m_keyDTypep && childDTypep()))); return nullptr; } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - if (m_keyDTypep && m_keyDTypep->clonep()) m_keyDTypep = m_keyDTypep->clonep(); - } bool same(const AstNode* samep) const override { const AstAssocArrayDType* const asamep = VN_DBG_AS(samep, AssocArrayDType); if (!asamep->subDTypep()) return false; @@ -354,7 +339,6 @@ public: class AstBasicDType final : public AstNodeDType { // Builtin atomic/vectored data type // @astgen op1 := rangep : Optional[AstRange] // Range of variable -private: struct Members { VBasicDTypeKwd m_keyword; // (also in VBasicTypeKey) What keyword created basic type VNumRange m_nrange; // (also in VBasicTypeKey) Numeric msb/lsb (if non-opaque keyword) @@ -514,7 +498,6 @@ public: bool similarDType(const AstNodeDType* samep) const override { return same(samep); } string name() const override VL_MT_STABLE { return m_name; } string prettyDTypeName() const override { return m_name; } - const char* broken() const override { return nullptr; } // METHODS AstBasicDType* basicp() const override VL_MT_STABLE { return nullptr; } AstNodeDType* skipRefp() const override VL_MT_STABLE { return (AstNodeDType*)this; } @@ -533,9 +516,9 @@ public: class AstClassRefDType final : public AstNodeDType { // Reference to a class // @astgen op1 := paramsp: List[AstPin] -private: - AstClass* m_classp; // data type pointed to, BELOW the AstTypedef - AstNodeModule* m_classOrPackagep = nullptr; // Package hierarchy + // + // @astgen ptr := m_classp : Optional[AstClass] // data type pointed to, BELOW the AstTypedef + // @astgen ptr := m_classOrPackagep : Optional[AstNodeModule] // Package hierarchy public: AstClassRefDType(FileLine* fl, AstClass* classp, AstPin* paramsp) : ASTGEN_SUPER_ClassRefDType(fl) @@ -545,8 +528,6 @@ public: } ASTGEN_MEMBERS_AstClassRefDType; // METHODS - const char* broken() const override; - void cloneRelink() override; bool same(const AstNode* samep) const override { const AstClassRefDType* const asamep = VN_DBG_AS(samep, ClassRefDType); return (m_classp == asamep->m_classp && m_classOrPackagep == asamep->m_classOrPackagep); @@ -577,8 +558,8 @@ class AstConstDType final : public AstNodeDType { // ConstDType are removed in V3LinkLValue and become AstVar::isConst. // When more generic types are supported AstConstDType will be propagated further. // @astgen op1 := childDTypep : Optional[AstNodeDType] -private: - AstNodeDType* m_refDTypep = nullptr; // Inherit from this base data type + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Inherit from this base data type public: AstConstDType(FileLine* fl, VFlagChildDType, AstNodeDType* dtp) : ASTGEN_SUPER_ConstDType(fl) { @@ -589,13 +570,9 @@ public: } ASTGEN_MEMBERS_AstConstDType; const char* broken() const override { - BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) - || (!m_refDTypep && childDTypep()))); + BROKEN_RTN(!((m_refDTypep && !childDTypep()) || (!m_refDTypep && childDTypep()))); return nullptr; } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - } bool same(const AstNode* samep) const override { const AstConstDType* const sp = VN_DBG_AS(samep, ConstDType); return (m_refDTypep == sp->m_refDTypep); @@ -622,12 +599,37 @@ public: return false; } }; +class AstConstraintRefDType final : public AstNodeDType { + // For e.g. a reference to constraint for constraint_mode +public: + explicit AstConstraintRefDType(FileLine* fl) + : ASTGEN_SUPER_ConstraintRefDType(fl) { + dtypep(this); + } + ASTGEN_MEMBERS_AstConstraintRefDType; + bool hasDType() const override { return true; } + bool maybePointedTo() const override { return true; } + bool undead() const override { return true; } + AstNodeDType* subDTypep() const override VL_MT_SAFE { return nullptr; } + AstNodeDType* virtRefDTypep() const override { return nullptr; } + void virtRefDTypep(AstNodeDType* nodep) override {} + bool similarDType(const AstNodeDType* samep) const override { return this == samep; } + AstBasicDType* basicp() const override VL_MT_STABLE { return nullptr; } + // cppcheck-suppress csyleCast + AstNodeDType* skipRefp() const override VL_MT_STABLE { return (AstNodeDType*)this; } + // cppcheck-suppress csyleCast + AstNodeDType* skipRefToConstp() const override { return (AstNodeDType*)this; } + // cppcheck-suppress csyleCast + AstNodeDType* skipRefToEnump() const override { return (AstNodeDType*)this; } + int widthAlignBytes() const override { return 1; } + int widthTotalBytes() const override { return 1; } + bool isCompound() const override { return false; } +}; class AstDefImplicitDType final : public AstNodeDType { // For parsing enum/struct/unions that are declared with a variable rather than typedef // This allows "var enum {...} a,b" to share the enum definition for both variables // After link, these become typedefs // @astgen op1 := childDTypep : Optional[AstNodeDType] -private: string m_name; void* m_containerp; // In what scope is the name unique, so we can know what are duplicate // definitions (arbitrary value) @@ -673,8 +675,8 @@ public: class AstDynArrayDType final : public AstNodeDType { // Dynamic array data type, ie "[]" // @astgen op1 := childDTypep : Optional[AstNodeDType] // moved to refDTypep() in V3Width -private: - AstNodeDType* m_refDTypep = nullptr; // Elements of this type (after widthing) + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Elements of this type (post-width) public: AstDynArrayDType(FileLine* fl, VFlagChildDType, AstNodeDType* dtp) : ASTGEN_SUPER_DynArrayDType(fl) { @@ -689,13 +691,9 @@ public: } ASTGEN_MEMBERS_AstDynArrayDType; const char* broken() const override { - BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) - || (!m_refDTypep && childDTypep()))); + BROKEN_RTN(!((m_refDTypep && !childDTypep()) || (!m_refDTypep && childDTypep()))); return nullptr; } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - } bool same(const AstNode* samep) const override { const AstDynArrayDType* const asamep = VN_DBG_AS(samep, DynArrayDType); if (!asamep->subDTypep()) return false; @@ -756,12 +754,13 @@ class AstEnumDType final : public AstNodeDType { // Parents: TYPEDEF/MODULE // @astgen op1 := childDTypep : Optional[AstNodeDType] // @astgen op2 := itemsp : List[AstEnumItem] + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Elements of this type (post-width) public: using TableMap = std::map; private: string m_name; // Name from upper typedef, if any - AstNodeDType* m_refDTypep = nullptr; // Elements are of this type after V3Width const int m_uniqueNum = 0; TableMap m_tableMap; // Created table for V3Width only to remove duplicates @@ -777,16 +776,7 @@ public: } ASTGEN_MEMBERS_AstEnumDType; - const char* broken() const override { - BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) - || (!m_refDTypep && childDTypep()))); - BROKEN_RTN(std::any_of(m_tableMap.begin(), m_tableMap.end(), - [](const auto& p) { return !p.second->brokeExists(); })); - return nullptr; - } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - } + const char* broken() const override; int uniqueNum() const { return m_uniqueNum; } bool same(const AstNode* samep) const override { const AstEnumDType* const sp = VN_DBG_AS(samep, EnumDType); @@ -821,17 +811,19 @@ public: TableMap& tableMap() { return m_tableMap; } const TableMap& tableMap() const { return m_tableMap; } }; + class AstIfaceRefDType final : public AstNodeDType { // Reference to an interface, either for a port, or inside parent cell // @astgen op1 := paramsp : List[AstPin] -private: + // + // @astgen ptr := m_ifacep : Optional[AstIface] // Interface; cellp() should override + // @astgen ptr := m_cellp : Optional[AstCell] // When exact parent cell known; not a guess + // @astgen ptr := m_modportp : Optional[AstModport] // nullptr = unlinked or no modport + bool m_virtual = false; // True if virtual interface FileLine* m_modportFileline; // Where modport token was string m_cellName; // "" = no cell, such as when connects to 'input' iface string m_ifaceName; // Interface name string m_modportName; // "" = no modport - AstIface* m_ifacep = nullptr; // Pointer to interface; note cellp() should override - AstCell* m_cellp = nullptr; // When exact parent cell known; not a guess - AstModport* m_modportp = nullptr; // nullptr = unlinked or no modport public: AstIfaceRefDType(FileLine* fl, const string& cellName, const string& ifaceName) : ASTGEN_SUPER_IfaceRefDType(fl) @@ -855,11 +847,10 @@ public: addParamsp(paramsp); } ASTGEN_MEMBERS_AstIfaceRefDType; + // METHODS - const char* broken() const override; void dump(std::ostream& str = std::cout) const override; void dumpSmall(std::ostream& str) const override; - void cloneRelink() override; AstBasicDType* basicp() const override VL_MT_STABLE { return nullptr; } AstNodeDType* skipRefp() const override VL_MT_STABLE { return (AstNodeDType*)this; } AstNodeDType* skipRefToConstp() const override { return (AstNodeDType*)this; } @@ -867,6 +858,11 @@ public: bool similarDType(const AstNodeDType* samep) const override { return this == samep; } int widthAlignBytes() const override { return 1; } int widthTotalBytes() const override { return 1; } + void isVirtual(bool flag) { + m_virtual = flag; + if (flag) v3Global.setHasVirtIfaces(); + } + bool isVirtual() const { return m_virtual; } FileLine* modportFileline() const { return m_modportFileline; } string cellName() const { return m_cellName; } void cellName(const string& name) { m_cellName = name; } @@ -888,8 +884,8 @@ class AstMemberDType final : public AstNodeDType { // PARENT: AstNodeUOrStructDType // @astgen op1 := childDTypep : Optional[AstNodeDType] // @astgen op3 := valuep : Optional[AstNode] -private: - AstNodeDType* m_refDTypep = nullptr; // Elements of this type (after widthing) + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Elements of this type (post-width) string m_name; // Name of variable string m_tag; // Holds the string of the verilator tag -- used in XML output. int m_lsb = -1; // Within this level's packed struct, the LSB of the first bit of the member @@ -917,13 +913,6 @@ public: string name() const override VL_MT_STABLE { return m_name; } // * = Var name bool hasDType() const override { return true; } bool maybePointedTo() const override { return true; } - const char* broken() const override { - BROKEN_RTN(m_refDTypep && !m_refDTypep->brokeExists()); - return nullptr; - } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - } AstNodeDType* getChildDTypep() const override { return childDTypep(); } AstNodeUOrStructDType* getChildStructp() const; AstNodeDType* subDTypep() const override VL_MT_STABLE { @@ -961,7 +950,6 @@ class AstParamTypeDType final : public AstNodeDType { // Parents: MODULE // A parameter type statement; much like a var or typedef // @astgen op1 := childDTypep : Optional[AstNodeDType] -private: const VVarType m_varType; // Type of variable (for localparam vs. param) string m_name; // Name of variable public: @@ -1031,8 +1019,8 @@ class AstQueueDType final : public AstNodeDType { // Queue array data type, ie "[ $ ]" // @astgen op1 := childDTypep : Optional[AstNodeDType] // moved to refDTypep() in V3Width // @astgen op2 := boundp : Optional[AstNodeExpr] -private: - AstNodeDType* m_refDTypep = nullptr; // Elements of this type (after widthing) + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Elements of this type (post-width) public: AstQueueDType(FileLine* fl, VFlagChildDType, AstNodeDType* dtp, AstNodeExpr* boundp) : ASTGEN_SUPER_QueueDType(fl) { @@ -1049,13 +1037,9 @@ public: } ASTGEN_MEMBERS_AstQueueDType; const char* broken() const override { - BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) - || (!m_refDTypep && childDTypep()))); + BROKEN_RTN(!((m_refDTypep && !childDTypep()) || (!m_refDTypep && childDTypep()))); return nullptr; } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - } bool same(const AstNode* samep) const override { const AstQueueDType* const asamep = VN_DBG_AS(samep, QueueDType); if (!asamep->subDTypep()) return false; @@ -1093,14 +1077,14 @@ class AstRefDType final : public AstNodeDType { // @astgen op1 := typeofp : Optional[AstNode] // @astgen op2 := classOrPackageOpp : Optional[AstNodeExpr] // @astgen op3 := paramsp : List[AstPin] -private: + // // Pre-Width must reference the Typeref, not what it points to, as some child // types like AstBracketArrayType will disappear and can't lose the handle - AstTypedef* m_typedefp = nullptr; // referenced type + // @astgen ptr := m_typedefp : Optional[AstTypedef] // Referenced type // Post-width typedefs are removed and point to type directly - AstNodeDType* m_refDTypep = nullptr; // data type pointed to, BELOW the AstTypedef + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Data type references + // @astgen ptr := m_classOrPackagep : Optional[AstNodeModule] // Class/package defined in string m_name; // Name of an AstTypedef - AstNodeModule* m_classOrPackagep = nullptr; // Class/package in which it was defined public: AstRefDType(FileLine* fl, const string& name) : ASTGEN_SUPER_RefDType(fl) @@ -1119,8 +1103,6 @@ public: } ASTGEN_MEMBERS_AstRefDType; // METHODS - const char* broken() const override; - void cloneRelink() override; bool same(const AstNode* samep) const override { const AstRefDType* const asamep = VN_DBG_AS(samep, RefDType); return (m_typedefp == asamep->m_typedefp && m_refDTypep == asamep->m_refDTypep @@ -1183,7 +1165,8 @@ public: }; class AstSampleQueueDType final : public AstNodeDType { // @astgen op1 := childDTypep : Optional[AstNodeDType] // moved to refDTypep() in V3Width - AstNodeDType* m_refDTypep = nullptr; // Elements of this type (after widthing) + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Elements of this type (post-width) public: AstSampleQueueDType(FileLine* fl, AstNodeDType* dtp) : ASTGEN_SUPER_SampleQueueDType(fl) { @@ -1192,13 +1175,9 @@ public: } ASTGEN_MEMBERS_AstSampleQueueDType; const char* broken() const override { - BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) - || (!m_refDTypep && childDTypep()))); + BROKEN_RTN(!((m_refDTypep && !childDTypep()) || (!m_refDTypep && childDTypep()))); return nullptr; } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - } bool same(const AstNode* samep) const override { const AstSampleQueueDType* const asamep = VN_DBG_AS(samep, SampleQueueDType); if (!asamep->subDTypep()) return false; @@ -1259,8 +1238,8 @@ public: class AstUnsizedArrayDType final : public AstNodeDType { // Unsized/open-range Array data type, ie "some_dtype var_name []" // @astgen op1 := childDTypep : Optional[AstNodeDType] // moved to refDTypep() in V3Width -private: - AstNodeDType* m_refDTypep; // Elements of this type (after widthing) + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Elements of this type (post-width) public: AstUnsizedArrayDType(FileLine* fl, VFlagChildDType, AstNodeDType* dtp) : ASTGEN_SUPER_UnsizedArrayDType(fl) { @@ -1270,13 +1249,9 @@ public: } ASTGEN_MEMBERS_AstUnsizedArrayDType; const char* broken() const override { - BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) - || (!m_refDTypep && childDTypep()))); + BROKEN_RTN(!((m_refDTypep && !childDTypep()) || (!m_refDTypep && childDTypep()))); return nullptr; } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - } bool same(const AstNode* samep) const override; bool similarDType(const AstNodeDType* samep) const override; void dumpSmall(std::ostream& str) const override; @@ -1326,8 +1301,8 @@ public: class AstWildcardArrayDType final : public AstNodeDType { // Wildcard index type associative array data type, ie "some_dtype var_name [*]" // @astgen op1 := childDTypep : Optional[AstNodeDType] // moved to refDTypep() in V3Width -private: - AstNodeDType* m_refDTypep; // Elements of this type (after widthing) + // + // @astgen ptr := m_refDTypep : Optional[AstNodeDType] // Elements of this type (post-width) public: AstWildcardArrayDType(FileLine* fl, VFlagChildDType, AstNodeDType* dtp) : ASTGEN_SUPER_WildcardArrayDType(fl) { @@ -1337,13 +1312,9 @@ public: } ASTGEN_MEMBERS_AstWildcardArrayDType; const char* broken() const override { - BROKEN_RTN(!((m_refDTypep && !childDTypep() && m_refDTypep->brokeExists()) - || (!m_refDTypep && childDTypep()))); + BROKEN_RTN(!((m_refDTypep && !childDTypep()) || (!m_refDTypep && childDTypep()))); return nullptr; } - void cloneRelink() override { - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - } bool same(const AstNode* samep) const override; bool similarDType(const AstNodeDType* samep) const override; void dumpSmall(std::ostream& str) const override; diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index d026e5fcc..89caeed1e 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU Lesser // General Public License Version 3 or the Perl Artistic License Version 2.0. // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @@ -180,8 +180,9 @@ public: }; class AstNodeCCall VL_NOT_FINAL : public AstNodeExpr { // A call of a C++ function, perhaps a AstCFunc or perhaps globally named - // @astgen op2 := argsp : List[AstNodeExpr] // Note: op1 used by some sub-types only - AstCFunc* m_funcp; + // @astgen op2 := argsp : List[AstNodeExpr] // Note: op1 used by some sub-types only + // + // @astgen ptr := m_funcp : AstCFunc // Function being called string m_argTypes; bool m_superReference = false; // Called with super reference @@ -195,8 +196,6 @@ protected: public: ASTGEN_MEMBERS_AstNodeCCall; void dump(std::ostream& str = std::cout) const override; - void cloneRelink() override; - const char* broken() const override; int instrCount() const override { return INSTR_COUNT_CALL; } bool same(const AstNode* samep) const override { const AstNodeCCall* const asamep = VN_DBG_AS(samep, NodeCCall); @@ -223,8 +222,11 @@ class AstNodeFTaskRef VL_NOT_FINAL : public AstNodeExpr { // op2 used by some sub-types only // @astgen op3 := pinsp : List[AstNodeExpr] // @astgen op4 := scopeNamep : Optional[AstScopeName] - AstNodeFTask* m_taskp = nullptr; // [AfterLink] Pointer to task referenced - AstNodeModule* m_classOrPackagep = nullptr; // Class/package of the task + // + // @astgen ptr := m_taskp : Optional[AstNodeFTask] // [AfterLink] Pointer to task referenced + // @astgen ptr := m_classOrPackagep : Optional[AstNodeModule] // Class/package of the task + ASTGEN_MEMBERS_AstNodeFTaskRef; // Gen pointers before other members for performance +private: string m_name; // Name of variable string m_dotted; // Dotted part of scope the name()ed task/func is under or "" string m_inlinedDots; // Dotted hierarchy flattened out @@ -244,9 +246,7 @@ protected: } public: - ASTGEN_MEMBERS_AstNodeFTaskRef; const char* broken() const override; - void cloneRelink() override; void dump(std::ostream& str = std::cout) const override; string name() const override VL_MT_STABLE { return m_name; } // * = Var name bool isGateOptimizable() const override; @@ -486,10 +486,12 @@ public: }; class AstNodeVarRef VL_NOT_FINAL : public AstNodeExpr { // An AstVarRef or AstVarXRef + // @astgen ptr := m_varp : Optional[AstVar] // [AfterLink] Pointer to variable itself + // @astgen ptr := m_varScopep : Optional[AstVarScope] // Varscope for hierarchy + // @astgen ptr := m_classOrPackagep : Optional[AstNodeModule] // Class/package of the variable + ASTGEN_MEMBERS_AstNodeVarRef; // Gen pointers before other members for performance +private: VAccess m_access; // Left hand side assignment - AstVar* m_varp; // [AfterLink] Pointer to variable itself - AstVarScope* m_varScopep = nullptr; // Varscope for hierarchy - AstNodeModule* m_classOrPackagep = nullptr; // Class/package of the variable VSelfPointerText m_selfPointer = VSelfPointerText{VSelfPointerText::Empty()}; // Output code object // pointer (e.g.: 'this') @@ -507,11 +509,8 @@ protected: } public: - ASTGEN_MEMBERS_AstNodeVarRef; void dump(std::ostream& str) const override; - const char* broken() const override; int instrCount() const override { return widthInstrs(); } - void cloneRelink() override; VAccess access() const { return m_access; } void access(const VAccess& flag) { m_access = flag; } // Avoid using this; Set in constructor AstVar* varp() const { return m_varp; } // [After Link] Pointer to variable @@ -538,7 +537,7 @@ public: // === AstNodeExpr === class AstAddrOfCFunc final : public AstNodeExpr { // Get address of CFunc - AstCFunc* m_funcp; // Pointer to function itself + // @astgen ptr := m_funcp : AstCFunc // Pointer to function itself public: AstAddrOfCFunc(FileLine* fl, AstCFunc* funcp) @@ -549,8 +548,6 @@ public: public: ASTGEN_MEMBERS_AstAddrOfCFunc; - void cloneRelink() override; - const char* broken() const override; string emitVerilog() override { V3ERROR_NA_RETURN(""); } string emitC() override { V3ERROR_NA_RETURN(""); } bool cleanOut() const override { return true; } @@ -732,7 +729,6 @@ class AstCellRef final : public AstNodeExpr { // As-of-yet unlinkable reference into a cell // @astgen op1 := cellp : AstNode // @astgen op2 := exprp : AstNodeExpr -private: string m_name; // Cell name public: AstCellRef(FileLine* fl, const string& name, AstNode* cellp, AstNodeExpr* exprp) @@ -751,10 +747,9 @@ public: }; class AstClassOrPackageRef final : public AstNodeExpr { // @astgen op1 := paramsp : List[AstPin] -private: string m_name; // Node not NodeModule to appease some early parser usage - AstNode* m_classOrPackageNodep; // Pointer to class/package referenced + // @astgen ptr := m_classOrPackageNodep : Optional[AstNode] // Class/package referenced public: AstClassOrPackageRef(FileLine* fl, const string& name, AstNode* classOrPackageNodep, AstPin* paramsp) @@ -765,15 +760,6 @@ public: } ASTGEN_MEMBERS_AstClassOrPackageRef; // METHODS - const char* broken() const override { - BROKEN_RTN(m_classOrPackageNodep && !m_classOrPackageNodep->brokeExists()); - return nullptr; - } - void cloneRelink() override { - if (m_classOrPackageNodep && m_classOrPackageNodep->clonep()) { - m_classOrPackageNodep = m_classOrPackageNodep->clonep(); - } - } bool same(const AstNode* samep) const override { return (m_classOrPackageNodep == VN_DBG_AS(samep, ClassOrPackageRef)->m_classOrPackageNodep); @@ -1062,6 +1048,30 @@ public: // May return nullptr on parse failure. static AstConst* parseParamLiteral(FileLine* fl, const string& literal); }; +class AstConstraintRef final : public AstNodeExpr { + // A reference to a constraint identifier + // Not saving pointer to constraint yet, as constraint_mode is an unsupported construct + // @astgen op4 := scopeNamep : Optional[AstScopeName] + // + // @astgen ptr := m_classOrPackagep : Optional[AstNodeModule] // Class/package of constraint + string m_name; // Name of constraint + +public: + AstConstraintRef(FileLine* fl, const string& name) + : ASTGEN_SUPER_ConstraintRef(fl) + , m_name{name} { + dtypep(findConstraintRefDType()); + } + ASTGEN_MEMBERS_AstConstraintRef; + string name() const override VL_MT_STABLE { return m_name; } // * = Var name + void name(const string& name) override { m_name = name; } + AstNodeModule* classOrPackagep() const { return m_classOrPackagep; } + void classOrPackagep(AstNodeModule* nodep) { m_classOrPackagep = nodep; } + + string emitVerilog() final override { V3ERROR_NA_RETURN(""); } + string emitC() final override { V3ERROR_NA_RETURN(""); } + bool cleanOut() const final override { V3ERROR_NA_RETURN(true); } +}; class AstCvtDynArrayToPacked final : public AstNodeExpr { // Cast from dynamic queue data type to packed array // @astgen op1 := fromp : AstNodeExpr @@ -1127,8 +1137,8 @@ public: bool cleanOut() const override { return true; } }; class AstEnumItemRef final : public AstNodeExpr { - AstEnumItem* m_itemp; // [AfterLink] Pointer to item - AstNodeModule* m_classOrPackagep; // Class/package in which it was defined + // @astgen ptr := m_itemp : AstEnumItem // [AfterLink] Pointer to item + // @astgen ptr := m_classOrPackagep : Optional[AstNodeModule] // Class/package defined in public: AstEnumItemRef(FileLine* fl, AstEnumItem* itemp, AstNodeModule* classOrPackagep) : ASTGEN_SUPER_EnumItemRef(fl) @@ -1140,8 +1150,6 @@ public: void dump(std::ostream& str) const override; string name() const override VL_MT_STABLE { return itemp()->name(); } int instrCount() const override { return 0; } - const char* broken() const override; - void cloneRelink() override; bool same(const AstNode* samep) const override { const AstEnumItemRef* const sp = VN_DBG_AS(samep, EnumItemRef); return itemp() == sp->itemp(); @@ -1496,10 +1504,11 @@ public: }; class AstMemberSel final : public AstNodeExpr { // @astgen op1 := fromp : AstNodeExpr + // + // @astgen ptr := m_varp : Optional[AstVar] // Post link, variable in class that is selecting // Don't need the class we are extracting from, as the "fromp()"'s datatype can get us to it string m_name; VAccess m_access; // Read or write, as in AstNodeVarRef - AstVar* m_varp = nullptr; // Post link, variable within class that is target of selection public: AstMemberSel(FileLine* fl, AstNodeExpr* fromp, VFlagChildDType, const string& name) : ASTGEN_SUPER_MemberSel(fl) @@ -1514,8 +1523,6 @@ public: dtypep(dtp); } ASTGEN_MEMBERS_AstMemberSel; - void cloneRelink() override; - const char* broken() const override; void dump(std::ostream& str) const override; string name() const override VL_MT_STABLE { return m_name; } void name(const string& name) override { m_name = name; } @@ -1905,6 +1912,7 @@ public: string emitVerilog() override { V3ERROR_NA_RETURN(""); } string emitC() override { V3ERROR_NA_RETURN(""); } bool cleanOut() const override { V3ERROR_NA_RETURN(true); } + bool hasDType() const override { return false; } }; class AstSetAssoc final : public AstNodeExpr { // Set an assoc array element and return object, '{} @@ -1988,7 +1996,6 @@ class AstStructSel final : public AstNodeExpr { // Parents: math|stmt // Children: varref, math // @astgen op1 := fromp : AstNodeExpr -private: string m_name; // Name of the member public: AstStructSel(FileLine* fl, AstNodeExpr* fromp, const string& name) @@ -4184,11 +4191,6 @@ public: this->fromp(fromp); } ASTGEN_MEMBERS_AstCMethodCall; - const char* broken() const override { - BROKEN_BASE_RTN(AstNodeCCall::broken()); - BROKEN_RTN(!fromp()); - return nullptr; - } }; class AstCNew final : public AstNodeCCall { // C++ new() call @@ -4228,11 +4230,6 @@ public: this->fromp(fromp); } ASTGEN_MEMBERS_AstMethodCall; - const char* broken() const override { - BROKEN_BASE_RTN(AstNodeFTaskRef::broken()); - BROKEN_RTN(!fromp()); - return nullptr; - } }; class AstNew final : public AstNodeFTaskRef { // New as constructor @@ -4287,7 +4284,7 @@ class AstSelMinus final : public AstNodePreSel { // -: range extraction, perhaps with non-constant selection // Gets replaced during link with AstSel // @astgen alias op2 := bitp - // @astgen alias op3 := widtph + // @astgen alias op3 := widthp public: AstSelMinus(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp, AstNodeExpr* widthp) : ASTGEN_SUPER_SelMinus(fl, fromp, bitp, widthp) {} @@ -4297,7 +4294,7 @@ class AstSelPlus final : public AstNodePreSel { // +: range extraction, perhaps with non-constant selection // Gets replaced during link with AstSel // @astgen alias op2 := bitp - // @astgen alias op3 := widtph + // @astgen alias op3 := widthp public: AstSelPlus(FileLine* fl, AstNodeExpr* fromp, AstNodeExpr* bitp, AstNodeExpr* widthp) : ASTGEN_SUPER_SelPlus(fl, fromp, bitp, widthp) {} @@ -4714,15 +4711,14 @@ public: class AstCAwait final : public AstNodeUniop { // Emit C++'s co_await expression // @astgen alias op1 := exprp - AstSenTree* m_sensesp; // Sentree related to this await + // + // @astgen ptr := m_sensesp : Optional[AstSenTree] // Sentree related to this await public: AstCAwait(FileLine* fl, AstNodeExpr* exprp, AstSenTree* sensesp = nullptr) : ASTGEN_SUPER_CAwait(fl, exprp) , m_sensesp{sensesp} {} ASTGEN_MEMBERS_AstCAwait; bool isTimingControl() const override { return true; } - const char* broken() const override; - void cloneRelink() override; void dump(std::ostream& str) const override; AstSenTree* sensesp() const { return m_sensesp; } void clearSensesp() { m_sensesp = nullptr; } diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 23aaadb2a..48839a26e 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,7 +34,6 @@ class AstNodeBlock VL_NOT_FINAL : public AstNode { // A Begin/fork block // @astgen op2 := stmtsp : List[AstNode] // Parents: statement -private: string m_name; // Name of block bool m_unnamed; // Originally unnamed (name change does not affect this) protected: @@ -62,7 +61,6 @@ class AstNodeFTask VL_NOT_FINAL : public AstNode { // @astgen op3 := stmtsp : List[AstNode] // Scope name // @astgen op4 := scopeNamep : Optional[AstScopeName] -private: string m_name; // Name of task string m_cname; // Name of task if DPI import uint64_t m_dpiOpenParent = 0; // DPI import open array, if !=0, how many callees @@ -205,7 +203,6 @@ class AstNodeFile VL_NOT_FINAL : public AstNode { // Emitted Output file // Parents: NETLIST // @astgen op1 := tblockp : Optional[AstTextBlock] -private: string m_name; ///< Filename public: AstNodeFile(VNType t, FileLine* fl, const string& name) @@ -223,7 +220,6 @@ class AstNodeModule VL_NOT_FINAL : public AstNode { // @astgen op1 := inlinesp : List[AstNode] // @astgen op2 := stmtsp : List[AstNode] // @astgen op3 := activesp : List[AstActive] -private: string m_name; // Name of the module const string m_origName; // Name of the module, ignoring name() changes, for dot lookup string m_someInstanceName; // Hierarchical name of some arbitrary instance of this module. @@ -434,11 +430,25 @@ public: int instrCount() const override { return INSTR_COUNT_BRANCH; } bool same(const AstNode* /*samep*/) const override { return true; } }; +class AstNodeForeach VL_NOT_FINAL : public AstNodeStmt { + // @astgen op1 := arrayp : AstNode + // @astgen op2 := stmtsp : List[AstNode] +public: + AstNodeForeach(VNType t, FileLine* fl, AstNode* arrayp, AstNode* stmtsp) + : AstNodeStmt(t, fl) { + this->arrayp(arrayp); + this->addStmtsp(stmtsp); + } + ASTGEN_MEMBERS_AstNodeForeach; + bool isGateOptimizable() const override { return false; } + int instrCount() const override { return INSTR_COUNT_BRANCH; } + bool same(const AstNode* /*samep*/) const override { return true; } + bool isFirstInMyListOfStatements(AstNode* n) const override { return n == stmtsp(); } +}; class AstNodeIf VL_NOT_FINAL : public AstNodeStmt { // @astgen op1 := condp : AstNodeExpr // @astgen op2 := thensp : List[AstNode] // @astgen op3 := elsesp : List[AstNode] -private: VBranchPred m_branchPred; // Branch prediction as taken/untaken? bool m_isBoundsCheck; // True if this if node is for assertion/bounds checking protected: @@ -494,7 +504,6 @@ public: virtual const char* cFuncPrefixp() const = 0; }; class AstNodeText VL_NOT_FINAL : public AstNode { -private: string m_text; protected: @@ -514,7 +523,6 @@ public: void text(const string& value) { m_text = value; } }; class AstNodeSimpleText VL_NOT_FINAL : public AstNodeText { -private: bool m_tracking; // When emit, it's ok to parse the string to do indentation public: AstNodeSimpleText(VNType t, FileLine* fl, const string& textp, bool tracking = false) @@ -533,9 +541,9 @@ class AstActive final : public AstNode { // Parents: MODULE | CFUNC // @astgen op1 := sensesStorep : Optional[AstSenTree] // Moved into m_sensesp in V3Active // @astgen op2 := stmtsp : List[AstNode] // Logic -private: + // + // @astgen ptr := m_sensesp : Optional[AstSenTree] // Sensitivity list for this process string m_name; - AstSenTree* m_sensesp; public: AstActive(FileLine* fl, const string& name, AstSenTree* sensesp) @@ -547,8 +555,6 @@ public: ASTGEN_MEMBERS_AstActive; void dump(std::ostream& str = std::cout) const override; string name() const override VL_MT_STABLE { return m_name; } - const char* broken() const override; - void cloneRelink() override; // Statements are broken into pieces, as some must come before others. void sensesp(AstSenTree* nodep) { m_sensesp = nodep; } AstSenTree* sensesp() const { return m_sensesp; } @@ -560,7 +566,6 @@ class AstBind final : public AstNode { // Parents: MODULE // Children: CELL // @astgen op1 := cellsp : List[AstNode] -private: string m_name; // Binding to name public: AstBind(FileLine* fl, const string& name, AstNode* cellsp) @@ -582,8 +587,8 @@ class AstCFunc final : public AstNode { // @astgen op2 := initsp : List[AstNode] // @astgen op3 := stmtsp : List[AstNode] // @astgen op4 := finalsp : List[AstNode] -private: - AstScope* m_scopep; + // + // @astgen ptr := m_scopep : Optional[AstScope] // Scope that function is under string m_name; string m_cname; // C name, for dpiExports string m_rtnType; // void, bool, or other return type @@ -646,8 +651,6 @@ public: } ASTGEN_MEMBERS_AstCFunc; string name() const override VL_MT_STABLE { return m_name; } - const char* broken() const override; - void cloneRelink() override; bool maybePointedTo() const override { return true; } void dump(std::ostream& str = std::cout) const override; bool same(const AstNode* samep) const override { @@ -743,7 +746,6 @@ public: class AstCUse final : public AstNode { // C++ use of a class or #include; indicates need of forward declaration // Parents: NODEMODULE -private: const string m_name; const VUseType m_useType; // What sort of use this is @@ -778,11 +780,12 @@ class AstCell final : public AstNode { // @astgen op2 := paramsp : List[AstPin] // List of parameter assignments // @astgen op3 := rangep : Optional[AstRange] // Range for arrayed instances // @astgen op4 := intfRefsp : List[AstIntfRef] // List of interface references, for tracing + // + // @astgen ptr := m_modp : Optional[AstNodeModule] // [AfterLink] Pointer to module instanced FileLine* m_modNameFileline; // Where module the cell instances token was string m_name; // Cell name string m_origName; // Original name before dot addition string m_modName; // Module the cell instances - AstNodeModule* m_modp = nullptr; // [AfterLink] Pointer to module instanced bool m_hasIfaceVar : 1; // True if a Var has been created for this cell bool m_hasNoParens : 1; // Instantiation has no parenthesis bool m_recursive : 1; // Self-recursive module @@ -805,8 +808,8 @@ public: } ASTGEN_MEMBERS_AstCell; // No cloneRelink, we presume cloneee's want the same module linkages + void cloneRelink() override {} // TODO V3Param shouldn't require avoiding cloneRelinkGen void dump(std::ostream& str) const override; - const char* broken() const override; bool maybePointedTo() const override { return true; } // ACCESSORS string name() const override VL_MT_STABLE { return m_name; } // * = Cell name @@ -833,11 +836,9 @@ class AstCellInline final : public AstNode { // except for VPI runs where it exists until the end. // It is augmented with the scope in V3Scope for VPI. // Children: When 2 levels inlined, other CellInline under this -private: + // @astgen ptr := m_scopep : Optional[AstScope] // The scope that the cell is inlined into string m_name; // Cell name, possibly {a}__DOT__{b}... - const string - m_origModName; // Original name of the module, ignoring name() changes, for dot lookup - AstScope* m_scopep = nullptr; // The scope that the cell is inlined into + const string m_origModName; // Original name of module, ignoring name() changes, for LinkDot VTimescale m_timeunit; // Parent module time unit public: AstCellInline(FileLine* fl, const string& name, const string& origModName, @@ -848,7 +849,6 @@ public: , m_timeunit{timeunit} {} ASTGEN_MEMBERS_AstCellInline; void dump(std::ostream& str) const override; - const char* broken() const override; // ACCESSORS string name() const override VL_MT_STABLE { return m_name; } // * = Cell name string origModName() const { return m_origModName; } // * = modp()->origName() before inlining @@ -937,10 +937,11 @@ public: class AstConstPool final : public AstNode { // Container for const static data // @astgen op1 := modulep : AstModule // m_modp below TODO: fix this mess + // + // @astgen ptr := m_modp : AstModule // The Module holding the Scope below ... + // @astgen ptr := m_scopep : AstScope // Scope holding the constant variables std::unordered_multimap m_tables; // Constant tables (unpacked arrays) std::unordered_multimap m_consts; // Constant tables (scalars) - AstModule* const m_modp; // The Module holding the Scope below ... - AstScope* const m_scopep; // Scope holding the constant variables AstVarScope* createNewEntry(const string& name, AstNodeExpr* initp); @@ -948,7 +949,6 @@ public: explicit AstConstPool(FileLine* fl); ASTGEN_MEMBERS_AstConstPool; bool maybePointedTo() const override { return true; } - const char* broken() const override; void cloneRelink() override { V3ERROR_NA; } AstModule* modp() const { return m_modp; } @@ -965,6 +965,40 @@ public: // false, the returned VarScope will have _->dtypep()->sameTree(initp->dtypep()) return true. AstVarScope* findConst(AstConst* initp, bool mergeDType); }; +class AstConstraint final : public AstNode { + // Constraint + // @astgen op1 := itemsp : List[AstNode] + string m_name; // Name of constraint + bool m_isStatic = false; // static constraint +public: + AstConstraint(FileLine* fl, const string& name, AstNode* itemsp) + : ASTGEN_SUPER_Constraint(fl) + , m_name(name) { + this->addItemsp(itemsp); + } + ASTGEN_MEMBERS_AstConstraint; + string name() const override VL_MT_STABLE { return m_name; } // * = Scope name + bool isGateOptimizable() const override { return false; } + bool isPredictOptimizable() const override { return false; } + bool same(const AstNode* /*samep*/) const override { return true; } + void isStatic(bool flag) { m_isStatic = flag; } + bool isStatic() const { return m_isStatic; } +}; +class AstConstraintBefore final : public AstNode { + // Constraint solve before item + // @astgen op1 := lhssp : List[AstNodeExpr] + // @astgen op2 := rhssp : List[AstNodeExpr] +public: + AstConstraintBefore(FileLine* fl, AstNodeExpr* lhssp, AstNodeExpr* rhssp) + : ASTGEN_SUPER_ConstraintBefore(fl) { + this->addLhssp(lhssp); + this->addRhssp(rhssp); + } + ASTGEN_MEMBERS_AstConstraintBefore; + bool isGateOptimizable() const override { return false; } + bool isPredictOptimizable() const override { return false; } + bool same(const AstNode* /*samep*/) const override { return true; } +}; class AstDefParam final : public AstNode { // A defparam assignment // Parents: MODULE @@ -983,11 +1017,28 @@ public: bool same(const AstNode*) const override { return true; } string path() const { return m_path; } }; +class AstDistItem final : public AstNode { + // Constraint distribution item + // @astgen op1 := rangep : AstNodeExpr + // @astgen op2 := weightp : AstNodeExpr + bool m_isWhole = false; // True for weight ':/', false for ':=' +public: + AstDistItem(FileLine* fl, AstNodeExpr* rangep, AstNodeExpr* weightp) + : ASTGEN_SUPER_DistItem(fl) { + this->rangep(rangep); + this->weightp(weightp); + } + ASTGEN_MEMBERS_AstDistItem; + bool isGateOptimizable() const override { return false; } + bool isPredictOptimizable() const override { return false; } + bool same(const AstNode* /*samep*/) const override { return true; } + void isWhole(bool flag) { m_isWhole = flag; } + bool isWhole() const { return m_isWhole; } +}; class AstDpiExport final : public AstNode { // We could put an AstNodeFTaskRef instead of the verilog function name, // however we're not *calling* it, so that seems somehow wrong. // (Probably AstNodeFTaskRef should be renamed AstNodeFTaskCall and have-a AstNodeFTaskRef) -private: string m_name; // Name of function string m_cname; // Name of function on c side public: @@ -1004,7 +1055,6 @@ public: class AstElabDisplay final : public AstNode { // Parents: stmtlist // @astgen op1 := fmtp : List[AstSFormatF] -private: VDisplayType m_displayType; public: @@ -1089,7 +1139,6 @@ public: }; class AstIntfRef final : public AstNode { // An interface reference -private: string m_name; // Name of the reference public: AstIntfRef(FileLine* fl, const string& name) @@ -1141,9 +1190,9 @@ class AstModportFTaskRef final : public AstNode { // The storage for the function itself is inside the // interface/instantiator, thus this is a reference // PARENT: AstModport -private: + // + // @astgen ptr := m_ftaskp : Optional[AstNodeFTask] // Link to the function string m_name; // Name of the variable referenced - AstNodeFTask* m_ftaskp = nullptr; // Link to the function bool m_export; // Type of the function (import/export) public: AstModportFTaskRef(FileLine* fl, const string& name, bool isExport) @@ -1151,8 +1200,6 @@ public: , m_name{name} , m_export{isExport} {} ASTGEN_MEMBERS_AstModportFTaskRef; - const char* broken() const override; - void cloneRelink() override; void dump(std::ostream& str) const override; string name() const override VL_MT_STABLE { return m_name; } bool isImport() const { return !m_export; } @@ -1164,9 +1211,9 @@ class AstModportVarRef final : public AstNode { // A input/output/etc variable referenced under a modport // The storage for the variable itself is inside the interface, thus this is a reference // PARENT: AstModport -private: + // + // @astgen ptr := m_varp : Optional[AstVar] // Link to the actual Var string m_name; // Name of the variable referenced - AstVar* m_varp = nullptr; // Link to the actual Var VDirection m_direction; // Direction of the variable (in/out) public: AstModportVarRef(FileLine* fl, const string& name, VDirection::en direction) @@ -1174,8 +1221,6 @@ public: , m_name{name} , m_direction{direction} {} ASTGEN_MEMBERS_AstModportVarRef; - const char* broken() const override; - void cloneRelink() override; void dump(std::ostream& str) const override; string name() const override VL_MT_STABLE { return m_name; } void direction(const VDirection& flag) { m_direction = flag; } @@ -1190,18 +1235,18 @@ class AstNetlist final : public AstNode { // @astgen op1 := modulesp : List[AstNodeModule] // @astgen op2 := filesp : List[AstNodeFile] // @astgen op3 := miscsp : List[AstNode] - - AstTypeTable* const m_typeTablep; // Reference to top type table, for faster lookup - AstConstPool* const m_constPoolp; // Reference to constant pool, for faster lookup - AstPackage* m_dollarUnitPkgp = nullptr; // $unit - AstPackage* m_stdPackagep = nullptr; // SystemVerilog std package - AstCFunc* m_evalp = nullptr; // The '_eval' function - AstCFunc* m_evalNbap = nullptr; // The '_eval__nba' function - AstVarScope* m_dpiExportTriggerp = nullptr; // The DPI export trigger variable - AstVar* m_delaySchedulerp = nullptr; // The delay scheduler variable - AstVarScope* m_nbaEventp = nullptr; // The NBA event variable - AstVarScope* m_nbaEventTriggerp = nullptr; // If set to 1, the NBA event should get triggered - AstTopScope* m_topScopep = nullptr; // The singleton AstTopScope under the top module + // + // @astgen ptr := m_typeTablep : AstTypeTable // Reference to type table, for faster lookup + // @astgen ptr := m_constPoolp : AstConstPool // Reference to constant pool, for faster lookup + // @astgen ptr := m_dollarUnitPkgp : Optional[AstPackage] // $unit + // @astgen ptr := m_stdPackagep : Optional[AstPackage] // SystemVerilog std package + // @astgen ptr := m_evalp : Optional[AstCFunc] // The '_eval' function + // @astgen ptr := m_evalNbap : Optional[AstCFunc] // The '_eval__nba' function + // @astgen ptr := m_dpiExportTriggerp : Optional[AstVarScope] // DPI export trigger variable + // @astgen ptr := m_delaySchedulerp : Optional[AstVar] // Delay scheduler variable + // @astgen ptr := m_nbaEventp : Optional[AstVarScope] // NBA event variable + // @astgen ptr := m_nbaEventTriggerp : Optional[AstVarScope] // NBA event trigger + // @astgen ptr := m_topScopep : Optional[AstTopScope] // Singleton AstTopScope VTimescale m_timeunit; // Global time unit VTimescale m_timeprecision; // Global time precision bool m_timescaleSpecified = false; // Input HDL specified timescale @@ -1211,7 +1256,6 @@ class AstNetlist final : public AstNode { public: AstNetlist(); ASTGEN_MEMBERS_AstNetlist; - const char* broken() const override; void cloneRelink() override { V3ERROR_NA; } string name() const override VL_MT_STABLE { return "$root"; } void dump(std::ostream& str) const override; @@ -1253,18 +1297,17 @@ public: uint32_t usedMTaskProfilingIDs() const { return m_nextFreeMTaskProfilingID; } }; class AstPackageExport final : public AstNode { -private: // A package export declaration + // + // @astgen ptr := m_packagep : Optional[AstPackage] // Package hierarchy string m_name; - AstPackage* m_packagep; // Package hierarchy + public: AstPackageExport(FileLine* fl, AstPackage* packagep, const string& name) : ASTGEN_SUPER_PackageExport(fl) , m_name{name} , m_packagep{packagep} {} ASTGEN_MEMBERS_AstPackageExport; - const char* broken() const override; - void cloneRelink() override; void dump(std::ostream& str) const override; string name() const override VL_MT_STABLE { return m_name; } AstPackage* packagep() const { return m_packagep; } @@ -1279,18 +1322,17 @@ public: ASTGEN_MEMBERS_AstPackageExportStarStar; }; class AstPackageImport final : public AstNode { -private: // A package import declaration + // + // @astgen ptr := m_packagep : Optional[AstPackage] // Package hierarchy string m_name; - AstPackage* m_packagep; // Package hierarchy + public: AstPackageImport(FileLine* fl, AstPackage* packagep, const string& name) : ASTGEN_SUPER_PackageImport(fl) , m_name{name} , m_packagep{packagep} {} ASTGEN_MEMBERS_AstPackageImport; - const char* broken() const override; - void cloneRelink() override; void dump(std::ostream& str) const override; string name() const override VL_MT_STABLE { return m_name; } AstPackage* packagep() const { return m_packagep; } @@ -1299,11 +1341,11 @@ public: class AstPin final : public AstNode { // A port or parameter assignment on an instantiation // @astgen op1 := exprp : Optional[AstNode] // NodeExpr or NodeDType (nullptr if unconnected) -private: + // + // @astgen ptr := m_modVarp : Optional[AstVar] // Input/output connects to on submodule + // @astgen ptr := m_modPTypep : Optional[AstParamTypeDType] // Param type connects to on sub int m_pinNum; // Pin number string m_name; // Pin name, or "" for number based interconnect - AstVar* m_modVarp = nullptr; // Input/output this pin connects to on submodule. - AstParamTypeDType* m_modPTypep = nullptr; // Param type this pin connects to on submodule. bool m_param = false; // Pin connects to parameter bool m_svDotName = false; // Pin is SystemVerilog .name'ed bool m_svImplicit = false; // Pin is SystemVerilog .name'ed, allow implicit @@ -1316,8 +1358,8 @@ public: } inline AstPin(FileLine* fl, int pinNum, AstVarRef* varname, AstNode* exprp); ASTGEN_MEMBERS_AstPin; + void cloneRelink() override {} // TODO V3Param shouldn't require avoiding cloneRelinkGen void dump(std::ostream& str) const override; - const char* broken() const override; string name() const override VL_MT_STABLE { return m_name; } // * = Pin name, ""=go by number void name(const string& name) override { m_name = name; } string prettyOperatorName() const override; @@ -1406,12 +1448,14 @@ class AstScope final : public AstNode { // Children: NODEBLOCK // @astgen op1 := varsp : List[AstVarScope] // @astgen op2 := blocksp : List[AstNode] // Logic blocks/AstActive/AstCFunc + // + // Below scope and cell are nullptr if top scope + // @astgen ptr := m_aboveScopep : Optional[AstScope] // Scope above this one in the hierarchy + // @astgen ptr := m_aboveCellp : Optional[AstCell] // Cell above this in the hierarchy + // @astgen ptr := m_modp : AstNodeModule // Module scope corresponds to // An AstScope->name() is special: . indicates an uninlined scope, __DOT__ an inlined scope string m_name; // Name - AstScope* const m_aboveScopep; // Scope above this one in the hierarchy (nullptr if top) - AstCell* const m_aboveCellp; // Cell above this in the hierarchy (nullptr if top) - AstNodeModule* const m_modp; // Module scope corresponds to public: AstScope(FileLine* fl, AstNodeModule* modp, const string& name, AstScope* aboveScopep, AstCell* aboveCellp) @@ -1421,8 +1465,10 @@ public: , m_aboveCellp{aboveCellp} , m_modp{modp} {} ASTGEN_MEMBERS_AstScope; - void cloneRelink() override; - const char* broken() const override; + const char* broken() const override { + BROKEN_RTN(!m_modp); + return nullptr; + } bool maybePointedTo() const override { return true; } string name() const override VL_MT_STABLE { return m_name; } // * = Scope name void name(const string& name) override { m_name = name; } @@ -1442,6 +1488,7 @@ public: class AstSenItem final : public AstNode { // Parents: SENTREE // @astgen op1 := sensp : Optional[AstNodeExpr] // Sensitivity expression + // @astgen op2 := condp : Optional[AstNodeExpr] // Sensitivity condition VEdgeType m_edgeType; // Edge type public: class Combo {}; // for constructor type-overload selection @@ -1450,10 +1497,11 @@ public: class Initial {}; // for constructor type-overload selection class Final {}; // for constructor type-overload selection class Never {}; // for constructor type-overload selection - AstSenItem(FileLine* fl, VEdgeType edgeType, AstNodeExpr* senp) + AstSenItem(FileLine* fl, VEdgeType edgeType, AstNodeExpr* senp, AstNodeExpr* condp = nullptr) : ASTGEN_SUPER_SenItem(fl) , m_edgeType{edgeType} { this->sensp(senp); + this->condp(condp); } AstSenItem(FileLine* fl, Combo) : ASTGEN_SUPER_SenItem(fl) @@ -1524,7 +1572,6 @@ public: ASTGEN_MEMBERS_AstSplitPlaceholder; }; class AstStrengthSpec final : public AstNode { -private: VStrength m_s0; // Drive 0 strength VStrength m_s1; // Drive 1 strength @@ -1560,10 +1607,12 @@ public: class AstTypeTable final : public AstNode { // Container for hash of standard data types // @astgen op1 := typesp : List[AstNodeDType] - AstEmptyQueueDType* m_emptyQueuep = nullptr; - AstQueueDType* m_queueIndexp = nullptr; - AstVoidDType* m_voidp = nullptr; - AstStreamDType* m_streamp = nullptr; + // + // @astgen ptr := m_constraintRefp : Optional[AstConstraintRefDType] + // @astgen ptr := m_emptyQueuep : Optional[AstEmptyQueueDType] + // @astgen ptr := m_queueIndexp : Optional[AstQueueDType] + // @astgen ptr := m_streamp : Optional[AstStreamDType] + // @astgen ptr := m_voidp : Optional[AstVoidDType] AstBasicDType* m_basicps[VBasicDTypeKwd::_ENUM_MAX]{}; // using DetailedMap = std::map; @@ -1573,12 +1622,6 @@ public: explicit AstTypeTable(FileLine* fl); ASTGEN_MEMBERS_AstTypeTable; bool maybePointedTo() const override { return true; } - const char* broken() const override { - BROKEN_RTN(m_emptyQueuep && !m_emptyQueuep->brokeExists()); - BROKEN_RTN(m_queueIndexp && !m_queueIndexp->brokeExists()); - BROKEN_RTN(m_voidp && !m_voidp->brokeExists()); - return nullptr; - } void cloneRelink() override { V3ERROR_NA; } AstBasicDType* findBasicDType(FileLine* fl, VBasicDTypeKwd kwd); AstBasicDType* findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, int width, int widthMin, @@ -1586,10 +1629,11 @@ public: AstBasicDType* findLogicBitDType(FileLine* fl, VBasicDTypeKwd kwd, const VNumRange& range, int widthMin, VSigning numeric); AstBasicDType* findInsertSameDType(AstBasicDType* nodep); + AstConstraintRefDType* findConstraintRefDType(FileLine* fl); AstEmptyQueueDType* findEmptyQueueDType(FileLine* fl); AstQueueDType* findQueueIndexDType(FileLine* fl); - AstVoidDType* findVoidDType(FileLine* fl); AstStreamDType* findStreamDType(FileLine* fl); + AstVoidDType* findVoidDType(FileLine* fl); void clearCache(); void repairCache(); void dump(std::ostream& str = std::cout) const override; @@ -1629,7 +1673,6 @@ public: }; class AstTypedefFwd final : public AstNode { // Forward declaration of a type; stripped after netlist parsing is complete -private: string m_name; public: @@ -1670,6 +1713,8 @@ class AstVar final : public AstNode { // MTASKSTATE variables // @astgen op3 := valuep : Optional[AstNode] // May be a DType for type parameter defaults // @astgen op4 := attrsp : List[AstNode] // Attributes during early parse + // @astgen ptr := m_sensIfacep : Optional[AstIface] // Interface type to which reads from this + // var are sensitive string m_name; // Name of variable string m_origName; // Original name before dot addition @@ -1695,7 +1740,6 @@ class AstVar final : public AstNode { bool m_usedClock : 1; // Signal used as a clock bool m_usedParam : 1; // Parameter is referenced (on link; later signals not setup) bool m_usedLoopIdx : 1; // Variable subject of for unrolling - bool m_usedVirtIface : 1; // Signal used through a virtual interface bool m_funcLocal : 1; // Local variable for a function bool m_funcLocalSticky : 1; // As m_funcLocal but remains set if var is moved to a static bool m_funcReturn : 1; // Return variable for a function @@ -1737,7 +1781,6 @@ class AstVar final : public AstNode { m_usedClock = false; m_usedParam = false; m_usedLoopIdx = false; - m_usedVirtIface = false; m_sigPublic = false; m_sigModPublic = false; m_sigUserRdPublic = false; @@ -1866,6 +1909,7 @@ public: } void ansi(bool flag) { m_ansi = flag; } void declTyped(bool flag) { m_declTyped = flag; } + void sensIfacep(AstIface* nodep) { m_sensIfacep = nodep; } void attrClocker(VVarAttrClocker flag) { m_attrClocker = flag; } void attrFileDescr(bool flag) { m_fileDescr = flag; } void attrScClocked(bool flag) { m_scClocked = flag; } @@ -1876,7 +1920,6 @@ public: void usedClock(bool flag) { m_usedClock = flag; } void usedParam(bool flag) { m_usedParam = flag; } void usedLoopIdx(bool flag) { m_usedLoopIdx = flag; } - void usedVirtIface(bool flag) { m_usedVirtIface = flag; } void sigPublic(bool flag) { m_sigPublic = flag; } void sigModPublic(bool flag) { m_sigModPublic = flag; } void sigUserRdPublic(bool flag) { @@ -1969,7 +2012,6 @@ public: bool isUsedClock() const { return m_usedClock; } bool isUsedParam() const { return m_usedParam; } bool isUsedLoopIdx() const { return m_usedLoopIdx; } - bool isUsedVirtIface() const { return m_usedVirtIface; } bool isSc() const VL_MT_SAFE { return m_sc; } bool isScQuad() const; bool isScBv() const; @@ -1997,6 +2039,7 @@ public: bool attrSFormat() const { return m_attrSFormat; } bool attrSplitVar() const { return m_attrSplitVar; } bool attrIsolateAssign() const { return m_attrIsolateAssign; } + AstIface* sensIfacep() const { return m_sensIfacep; } VVarAttrClocker attrClocker() const { return m_attrClocker; } string verilogKwd() const override; void lifetime(const VLifetime& flag) { m_lifetime = flag; } @@ -2015,10 +2058,6 @@ public: declDirection(fromp->declDirection()); lifetime(fromp->lifetime()); } - bool gateMultiInputOptimizable() const { - // Ok to gate optimize; must return false if propagateAttrFrom would do anything - return !isUsedClock(); - } void combineType(const AstVar* typevarp) { // This is same as typevarp (for combining input & reg decls) // "this" is the input var. typevarp is the reg var. @@ -2050,9 +2089,9 @@ class AstVarScope final : public AstNode { // varscope for each var in the module // Parents: MODULE // Children: none -private: - AstScope* m_scopep; // Scope variable is underneath - AstVar* m_varp; // [AfterLink] Pointer to variable itself + // + // @astgen ptr := m_scopep : Optional[AstScope] // Scope variable is underneath + // @astgen ptr := m_varp : Optional[AstVar] // [AfterLink] Pointer to variable itself bool m_trace : 1; // Tracing is turned on for this scope public: AstVarScope(FileLine* fl, AstScope* scopep, AstVar* varp) @@ -2067,15 +2106,9 @@ public: ASTGEN_MEMBERS_AstVarScope; void cloneRelink() override { if (m_varp && m_varp->clonep()) { - m_varp = m_varp->clonep(); UASSERT(m_scopep->clonep(), "No clone cross link: " << this); - m_scopep = m_scopep->clonep(); } - } - const char* broken() const override { - BROKEN_RTN(m_varp && !m_varp->brokeExists()); - BROKEN_RTN(m_scopep && !m_scopep->brokeExists()); - return nullptr; + cloneRelinkGen(); } bool maybePointedTo() const override { return true; } string name() const override VL_MT_STABLE { return scopep()->name() + "->" + varp()->name(); } @@ -2119,7 +2152,6 @@ class AstFork final : public AstNodeBlock { // @astgen op1 := initsp : List[AstNode] // Parents: statement // Children: statements -private: VJoinType m_joinType; // Join keyword type public: // Node that puts name into the output stream @@ -2187,7 +2219,6 @@ public: class AstCFile final : public AstNodeFile { // C++ output file // Parents: NETLIST -private: bool m_slow : 1; ///< Compile w/o optimization bool m_source : 1; ///< Source file (vs header file) bool m_support : 1; ///< Support file (non systemc) @@ -2220,7 +2251,7 @@ public: class AstClass final : public AstNodeModule { // @astgen op4 := extendsp : List[AstClassExtends] // MEMBERS - AstClassPackage* m_classOrPackagep = nullptr; // Package it will be emitted with + // @astgen ptr := m_classOrPackagep : Optional[AstClassPackage] // Package to be emitted with bool m_extended = false; // Is extension or extended by other classes bool m_interfaceClass = false; // Interface class bool m_needRNG = false; // Need RNG, uses srandom/randomize @@ -2234,8 +2265,6 @@ public: string verilogKwd() const override { return "class"; } bool maybePointedTo() const override { return true; } void dump(std::ostream& str) const override; - const char* broken() const override; - void cloneRelink() override; bool timescaleMatters() const override { return false; } AstClassPackage* classOrPackagep() const VL_MT_SAFE { return m_classOrPackagep; } void classOrPackagep(AstClassPackage* classpackagep) { m_classOrPackagep = classpackagep; } @@ -2260,15 +2289,14 @@ public: }; class AstClassPackage final : public AstNodeModule { // The static information portion of a class (treated similarly to a package) - AstClass* m_classp - = nullptr; // Class package this is under (weak pointer, hard link is other way) + // + // @astgen ptr := m_classp : Optional[AstClass] // Class package this is under + // // (weak pointer, hard link is other way) public: AstClassPackage(FileLine* fl, const string& name) : ASTGEN_SUPER_ClassPackage(fl, name) {} ASTGEN_MEMBERS_AstClassPackage; string verilogKwd() const override { return "classpackage"; } - const char* broken() const override; - void cloneRelink() override; bool timescaleMatters() const override { return false; } AstClass* classp() const VL_MT_SAFE { return m_classp; } void classp(AstClass* classp) { m_classp = classp; } @@ -2286,7 +2314,6 @@ public: }; class AstModule final : public AstNodeModule { // A module declaration -private: const bool m_isProgram; // Module represents a program public: AstModule(FileLine* fl, const string& name, bool program = false) @@ -2562,6 +2589,38 @@ public: bool same(const AstNode* samep) const override { return true; } // Ignore name in comments virtual bool showAt() const { return m_showAt; } }; +class AstConstraintExpr final : public AstNodeStmt { + // Constraint expression + // @astgen op1 := exprp : AstNodeExpr + bool m_isSoft = false; // Soft constraint expression + bool m_isDisableSoft = false; // Disable soft constraint expression +public: + AstConstraintExpr(FileLine* fl, AstNodeExpr* exprp) + : ASTGEN_SUPER_ConstraintExpr(fl) { + this->exprp(exprp); + } + ASTGEN_MEMBERS_AstConstraintExpr; + bool isGateOptimizable() const override { return false; } + bool isPredictOptimizable() const override { return false; } + bool same(const AstNode* /*samep*/) const override { return true; } + void isDisableSoft(bool flag) { m_isDisableSoft = flag; } + bool isDisableSoft() const { return m_isDisableSoft; } + void isSoft(bool flag) { m_isSoft = flag; } + bool isSoft() const { return m_isSoft; } +}; +class AstConstraintUnique final : public AstNodeStmt { + // Constraint unique statement + // @astgen op1 := rangesp : List[AstNode] +public: + AstConstraintUnique(FileLine* fl, AstNode* rangesp) + : ASTGEN_SUPER_ConstraintUnique(fl) { + this->addRangesp(rangesp); + } + ASTGEN_MEMBERS_AstConstraintUnique; + bool isGateOptimizable() const override { return false; } + bool isPredictOptimizable() const override { return false; } + bool same(const AstNode* /*samep*/) const override { return true; } +}; class AstContinue final : public AstNodeStmt { public: explicit AstContinue(FileLine* fl) @@ -2574,8 +2633,9 @@ public: }; class AstCoverDecl final : public AstNodeStmt { // Coverage analysis point declaration - AstCoverDecl* m_dataDeclp = nullptr; // [After V3CoverageJoin] Pointer to duplicate - // declaration to get data from instead + // + // [After V3CoverageJoin] Duplicate declaration to get data from instead + // @astgen ptr := m_dataDeclp : Optional[AstCoverDecl] string m_page; string m_text; string m_hier; @@ -2592,15 +2652,11 @@ public: , m_offset{offset} {} ASTGEN_MEMBERS_AstCoverDecl; const char* broken() const override { - BROKEN_RTN(m_dataDeclp && !m_dataDeclp->brokeExists()); if (m_dataDeclp && m_dataDeclp->m_dataDeclp) { // Avoid O(n^2) accessing v3fatalSrc("dataDeclp should point to real data, not be a list"); } return nullptr; } - void cloneRelink() override { - if (m_dataDeclp && m_dataDeclp->clonep()) m_dataDeclp = m_dataDeclp->clonep(); - } void dump(std::ostream& str) const override; int instrCount() const override { return 1 + 2 * INSTR_COUNT_LD; } bool maybePointedTo() const override { return true; } @@ -2627,19 +2683,13 @@ public: }; class AstCoverInc final : public AstNodeStmt { // Coverage analysis point; increment coverage count - AstCoverDecl* m_declp; // [After V3Coverage] Pointer to declaration + // + // @astgen ptr := m_declp : AstCoverDecl // [After V3CoverageJoin] Declaration public: AstCoverInc(FileLine* fl, AstCoverDecl* declp) : ASTGEN_SUPER_CoverInc(fl) , m_declp{declp} {} ASTGEN_MEMBERS_AstCoverInc; - const char* broken() const override { - BROKEN_RTN(!declp()->brokeExists()); - return nullptr; - } - void cloneRelink() override { - if (m_declp->clonep()) m_declp = m_declp->clonep(); - } void dump(std::ostream& str) const override; int instrCount() const override { return 1 + 2 * INSTR_COUNT_LD; } bool same(const AstNode* samep) const override { @@ -2716,7 +2766,6 @@ class AstDisplay final : public AstNodeStmt { // Parents: stmtlist // @astgen op1 := fmtp : AstSFormatF // @astgen op2 := filep : Optional[AstNodeExpr] // file (must resolve to a VarRef) -private: VDisplayType m_displayType; public: @@ -2869,29 +2918,14 @@ public: ASTGEN_MEMBERS_AstFireEvent; bool isDelayed() const { return m_delayed; } }; -class AstForeach final : public AstNodeStmt { - // @astgen op1 := arrayp : AstNode - // @astgen op2 := stmtsp : List[AstNode] -public: - AstForeach(FileLine* fl, AstNode* arrayp, AstNode* stmtsp) - : ASTGEN_SUPER_Foreach(fl) { - this->arrayp(arrayp); - this->addStmtsp(stmtsp); - } - ASTGEN_MEMBERS_AstForeach; - bool isGateOptimizable() const override { return false; } - int instrCount() const override { return INSTR_COUNT_BRANCH; } - bool same(const AstNode* /*samep*/) const override { return true; } - bool isFirstInMyListOfStatements(AstNode* n) const override { return n == stmtsp(); } -}; class AstJumpBlock final : public AstNodeStmt { // Block of code including a single JumpLabel, and 0+ JumpGo's to that label // Parents: {statement list} // Children: {statement list, with JumpGo and JumpLabel below} // @astgen op1 := stmtsp : List[AstNode] // @astgen op2 := endStmtsp : List[AstNode] -private: - AstJumpLabel* m_labelp = nullptr; // [After V3Jump] Pointer to declaration + // + // @astgen ptr := m_labelp : AstJumpLabel // [After V3Jump] Pointer to declaration int m_labelNum = 0; // Set by V3EmitCSyms to tell final V3Emit what to increment public: // After construction must call ->labelp to associate with appropriate label @@ -2899,9 +2933,8 @@ public: : ASTGEN_SUPER_JumpBlock(fl) { this->addStmtsp(stmtsp); } - const char* broken() const override; - void cloneRelink() override; ASTGEN_MEMBERS_AstJumpBlock; + const char* broken() const override; int instrCount() const override { return 0; } bool maybePointedTo() const override { return true; } bool same(const AstNode* /*samep*/) const override { return true; } @@ -2915,15 +2948,14 @@ class AstJumpGo final : public AstNodeStmt { // No support for backward jumps at present // Parents: {statement list with JumpBlock above} // Children: none -private: - AstJumpLabel* m_labelp; // [After V3Jump] Pointer to declaration + // + // @astgen ptr := m_labelp : AstJumpLabel // [After V3Jump] Pointer to declaration public: AstJumpGo(FileLine* fl, AstJumpLabel* labelp) : ASTGEN_SUPER_JumpGo(fl) , m_labelp{labelp} {} ASTGEN_MEMBERS_AstJumpGo; const char* broken() const override; - void cloneRelink() override; void dump(std::ostream& str) const override; int instrCount() const override { return INSTR_COUNT_BRANCH; } bool same(const AstNode* samep) const override { @@ -2939,8 +2971,7 @@ class AstJumpLabel final : public AstNodeStmt { // Jump point declaration // Parents: {statement list with JumpBlock above} // Children: none -private: - AstJumpBlock* m_blockp; // [After V3Jump] Pointer to declaration + // @astgen ptr := m_blockp : AstJumpBlock // [After V3Jump] Pointer to declaration public: AstJumpLabel(FileLine* fl, AstJumpBlock* blockp) : ASTGEN_SUPER_JumpLabel(fl) @@ -2952,9 +2983,6 @@ public: BROKEN_RTN(blockp()->labelp() != this); return nullptr; } - void cloneRelink() override { - if (m_blockp->clonep()) m_blockp = m_blockp->clonep(); - } void dump(std::ostream& str) const override; int instrCount() const override { return 0; } bool same(const AstNode* samep) const override { @@ -3180,13 +3208,11 @@ class AstTraceDecl final : public AstNodeStmt { // Parents: {statement list} // Expression being traced - Moved to AstTraceInc by V3Trace // @astgen op1 := valuep : Optional[AstNodeExpr] -private: uint32_t m_code{0}; // Trace identifier code uint32_t m_fidx{0}; // Trace function index const string m_showname; // Name of variable const VNumRange m_bitRange; // Property of var the trace details const VNumRange m_arrayRange; // Property of var the trace details - const uint32_t m_codeInc; // Code increment const VVarType m_varType; // Type of variable (for localparam vs. param) const VDirection m_declDirection; // Declared direction input/output etc public: @@ -3197,9 +3223,6 @@ public: , m_showname{showname} , m_bitRange{bitRange} , m_arrayRange{arrayRange} - , m_codeInc( - ((arrayRange.ranged() ? arrayRange.elements() : 1) * valuep->dtypep()->widthWords() - * (VL_EDATASIZE / 32))) // A code is always 32-bits , m_varType{varp->varType()} , m_declDirection{varp->declDirection()} { dtypeFrom(valuep); @@ -3218,7 +3241,11 @@ public: void code(uint32_t code) { m_code = code; } uint32_t fidx() const { return m_fidx; } void fidx(uint32_t fidx) { m_fidx = fidx; } - uint32_t codeInc() const { return m_codeInc; } + uint32_t codeInc() const { + return (m_arrayRange.ranged() ? m_arrayRange.elements() : 1) + * valuep()->dtypep()->widthWords() + * (VL_EDATASIZE / 32); // A code is always 32-bits + } const VNumRange& bitRange() const { return m_bitRange; } const VNumRange& arrayRange() const { return m_arrayRange; } VVarType varType() const { return m_varType; } @@ -3226,32 +3253,24 @@ public: }; class AstTraceInc final : public AstNodeStmt { // Trace point dump - // @astgen op1 := precondsp : List[AstNode] // Statements to emit before this node - // @astgen op2 := valuep : AstNodeExpr // Expression being traced (from decl) - -private: - AstTraceDecl* m_declp; // Pointer to declaration + // @astgen op1 := valuep : AstNodeExpr // Expression being traced (from decl) + // + // @astgen ptr := m_declp : AstTraceDecl // Pointer to declaration const uint32_t m_baseCode; // Trace code base value in function containing this AstTraceInc const VTraceType m_traceType; // Is this a const/full/incremental dump public: AstTraceInc(FileLine* fl, AstTraceDecl* declp, VTraceType traceType, uint32_t baseCode = 0) : ASTGEN_SUPER_TraceInc(fl) - , m_declp{declp} , m_baseCode{baseCode} - , m_traceType{traceType} { + , m_traceType{traceType} + , m_declp{declp} { dtypeFrom(declp); - this->valuep( - declp->valuep()->cloneTree(true)); // TODO: maybe use reference to TraceDecl instead? + // Note: A clone is necessary (instead of using declp()->valuep()), + // for insertion of local temporaries in V3Premit + valuep(declp->valuep()->cloneTree(true)); } ASTGEN_MEMBERS_AstTraceInc; - const char* broken() const override { - BROKEN_RTN(!declp()->brokeExists()); - return nullptr; - } - void cloneRelink() override { - if (m_declp->clonep()) m_declp = m_declp->clonep(); - } void dump(std::ostream& str) const override; int instrCount() const override { return 10 + 2 * INSTR_COUNT_LD; } bool hasDType() const override { return true; } @@ -3268,7 +3287,7 @@ public: }; class AstTracePopPrefix final : public AstNodeStmt { public: - AstTracePopPrefix(FileLine* fl) + explicit AstTracePopPrefix(FileLine* fl) : ASTGEN_SUPER_TracePopPrefix(fl) {} ASTGEN_MEMBERS_AstTracePopPrefix; bool same(const AstNode* samep) const override { return false; } @@ -3539,7 +3558,28 @@ public: ASTGEN_MEMBERS_AstGenFor; }; +// === AstNodeForeach === +class AstConstraintForeach final : public AstNodeForeach { + // Constraint foreach statement +public: + AstConstraintForeach(FileLine* fl, AstNodeExpr* exprp, AstNode* bodysp) + : ASTGEN_SUPER_ConstraintForeach(fl, exprp, bodysp) {} + ASTGEN_MEMBERS_AstConstraintForeach; +}; +class AstForeach final : public AstNodeForeach { +public: + AstForeach(FileLine* fl, AstNode* arrayp, AstNode* stmtsp) + : ASTGEN_SUPER_Foreach(fl, arrayp, stmtsp) {} + ASTGEN_MEMBERS_AstForeach; +}; + // === AstNodeIf === +class AstConstraintIf final : public AstNodeIf { +public: + AstConstraintIf(FileLine* fl, AstNodeExpr* condp, AstNode* thensp, AstNode* elsesp) + : ASTGEN_SUPER_ConstraintIf(fl, condp, thensp, elsesp) {} + ASTGEN_MEMBERS_AstConstraintIf; +}; class AstGenIf final : public AstNodeIf { public: AstGenIf(FileLine* fl, AstNodeExpr* condp, AstNode* thensp, AstNode* elsesp) @@ -3547,7 +3587,6 @@ public: ASTGEN_MEMBERS_AstGenIf; }; class AstIf final : public AstNodeIf { -private: bool m_uniquePragma = false; // unique case bool m_unique0Pragma = false; // unique0 case bool m_priorityPragma = false; // priority case diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index d9cef86c2..77e812c64 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -23,6 +23,7 @@ #include "V3PartitionGraph.h" // Just for mtask dumping #include "V3String.h" +#include "V3Ast__gen_impl.h" // Generated by 'astgen' #include "V3Ast__gen_macros.h" // Generated by 'astgen' #include @@ -33,31 +34,15 @@ // Special methods // We need these here, because the classes they point to aren't defined when we declare the class -const char* AstIfaceRefDType::broken() const { - BROKEN_RTN(m_ifacep && !m_ifacep->brokeExists()); - BROKEN_RTN(m_cellp && !m_cellp->brokeExists()); - BROKEN_RTN(m_modportp && !m_modportp->brokeExists()); - return nullptr; -} - AstIface* AstIfaceRefDType::ifaceViaCellp() const { return ((m_cellp && m_cellp->modp()) ? VN_AS(m_cellp->modp(), Iface) : m_ifacep); } const char* AstNodeFTaskRef::broken() const { - BROKEN_RTN(m_taskp && !m_taskp->brokeExists()); - BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); BROKEN_RTN(m_purity.isCached() && m_purity.get() != getPurityRecurse()); return nullptr; } -void AstNodeFTaskRef::cloneRelink() { - if (m_taskp && m_taskp->clonep()) m_taskp = m_taskp->clonep(); - if (m_classOrPackagep && m_classOrPackagep->clonep()) { - m_classOrPackagep = m_classOrPackagep->clonep(); - } -} - bool AstNodeFTaskRef::isPure() { if (!this->taskp()) { // The task isn't linked yet, so it's assumed that it is impure, but the value shouldn't be @@ -83,40 +68,11 @@ bool AstNodeFTaskRef::getPurityRecurse() const { } bool AstNodeFTaskRef::isGateOptimizable() const { return m_taskp && m_taskp->isGateOptimizable(); } -const char* AstNodeVarRef::broken() const { - BROKEN_RTN(m_varp && !m_varp->brokeExists()); - BROKEN_RTN(m_varScopep && !m_varScopep->brokeExists()); - BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); - return nullptr; -} - -void AstNodeVarRef::cloneRelink() { - if (m_varp && m_varp->clonep()) m_varp = m_varp->clonep(); - if (m_varScopep && m_varScopep->clonep()) m_varScopep = m_varScopep->clonep(); - if (m_classOrPackagep && m_classOrPackagep->clonep()) { - m_classOrPackagep = m_classOrPackagep->clonep(); - } -} - -void AstAddrOfCFunc::cloneRelink() { - if (m_funcp && m_funcp->clonep()) m_funcp = m_funcp->clonep(); -} - -const char* AstAddrOfCFunc::broken() const { - BROKEN_RTN(m_funcp && !m_funcp->brokeExists()); - return nullptr; -} - int AstNodeSel::bitConst() const { const AstConst* const constp = VN_AS(bitp(), Const); return (constp ? constp->toSInt() : 0); } -const char* AstNodeUOrStructDType::broken() const { - BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); - return nullptr; -} - void AstNodeStmt::dump(std::ostream& str) const { this->AstNode::dump(str); } void AstNodeCCall::dump(std::ostream& str) const { @@ -128,13 +84,6 @@ void AstNodeCCall::dump(std::ostream& str) const { str << " " << name(); } } -void AstNodeCCall::cloneRelink() { - if (m_funcp && m_funcp->clonep()) m_funcp = m_funcp->clonep(); -} -const char* AstNodeCCall::broken() const { - BROKEN_RTN(m_funcp && !m_funcp->brokeExists()); - return nullptr; -} bool AstNodeCCall::isPure() { return funcp()->dpiPure(); } bool AstNodeUniop::isPure() { if (!m_purity.isCached()) m_purity.set(lhsp()->isPure()); @@ -931,7 +880,7 @@ AstNode* AstArraySel::baseFromp(AstNode* nodep, bool overMembers) { nodep = VN_AS(nodep, MemberSel)->fromp(); continue; } - // AstNodeSelPre stashes the associated variable under an ATTROF + // AstNodePreSel stashes the associated variable under an ATTROF // of VAttrType::VAR_BASE so it isn't constified else if (VN_IS(nodep, AttrOf)) { nodep = VN_AS(nodep, AttrOf)->fromp(); @@ -954,24 +903,7 @@ const char* AstJumpBlock::broken() const { BROKEN_RTN(!labelp()->brokeExistsBelow()); return nullptr; } -void AstJumpBlock::cloneRelink() { - if (m_labelp->clonep()) m_labelp = m_labelp->clonep(); -} -const char* AstScope::broken() const { - BROKEN_RTN(m_aboveScopep && !m_aboveScopep->brokeExists()); - BROKEN_RTN(m_aboveCellp && !m_aboveCellp->brokeExists()); - BROKEN_RTN(!m_modp); - BROKEN_RTN(m_modp && !m_modp->brokeExists()); - return nullptr; -} -void AstScope::cloneRelink() { - if (m_aboveScopep && m_aboveScopep->clonep()) m_aboveScopep->clonep(); - if (m_aboveCellp && m_aboveCellp->clonep()) m_aboveCellp->clonep(); - if (m_modp && static_cast(m_modp)->clonep()) { - static_cast(m_modp)->clonep(); - } -} string AstScope::nameDotless() const { string result = shortName(); string::size_type pos; @@ -1096,6 +1028,14 @@ void AstTypeTable::repairCache() { } } +AstConstraintRefDType* AstTypeTable::findConstraintRefDType(FileLine* fl) { + if (VL_UNLIKELY(!m_constraintRefp)) { + AstConstraintRefDType* const newp = new AstConstraintRefDType{fl}; + addTypesp(newp); + m_constraintRefp = newp; + } + return m_constraintRefp; +} AstEmptyQueueDType* AstTypeTable::findEmptyQueueDType(FileLine* fl) { if (VL_UNLIKELY(!m_emptyQueuep)) { AstEmptyQueueDType* const newp = new AstEmptyQueueDType{fl}; @@ -1104,16 +1044,6 @@ AstEmptyQueueDType* AstTypeTable::findEmptyQueueDType(FileLine* fl) { } return m_emptyQueuep; } - -AstVoidDType* AstTypeTable::findVoidDType(FileLine* fl) { - if (VL_UNLIKELY(!m_voidp)) { - AstVoidDType* const newp = new AstVoidDType{fl}; - addTypesp(newp); - m_voidp = newp; - } - return m_voidp; -} - AstStreamDType* AstTypeTable::findStreamDType(FileLine* fl) { if (VL_UNLIKELY(!m_streamp)) { AstStreamDType* const newp = new AstStreamDType{fl}; @@ -1122,7 +1052,6 @@ AstStreamDType* AstTypeTable::findStreamDType(FileLine* fl) { } return m_streamp; } - AstQueueDType* AstTypeTable::findQueueIndexDType(FileLine* fl) { if (VL_UNLIKELY(!m_queueIndexp)) { AstQueueDType* const newp = new AstQueueDType{fl, AstNode::findUInt32DType(), nullptr}; @@ -1131,6 +1060,14 @@ AstQueueDType* AstTypeTable::findQueueIndexDType(FileLine* fl) { } return m_queueIndexp; } +AstVoidDType* AstTypeTable::findVoidDType(FileLine* fl) { + if (VL_UNLIKELY(!m_voidp)) { + AstVoidDType* const newp = new AstVoidDType{fl}; + addTypesp(newp); + m_voidp = newp; + } + return m_voidp; +} AstBasicDType* AstTypeTable::findBasicDType(FileLine* fl, VBasicDTypeKwd kwd) { if (m_basicps[kwd]) return m_basicps[kwd]; @@ -1191,11 +1128,6 @@ AstConstPool::AstConstPool(FileLine* fl) this->modulep(m_modp); m_modp->addStmtsp(m_scopep); } -const char* AstConstPool::broken() const { - BROKEN_RTN(m_modp && !m_modp->brokeExists()); - BROKEN_RTN(m_scopep && !m_scopep->brokeExists()); - return nullptr; -} AstVarScope* AstConstPool::createNewEntry(const string& name, AstNodeExpr* initp) { FileLine* const fl = initp->fileline(); @@ -1445,29 +1377,13 @@ void AstCell::dump(std::ostream& str) const { str << " ->UNLINKED:" << modName(); } } -const char* AstCell::broken() const { - BROKEN_RTN(m_modp && !m_modp->brokeExists()); - return nullptr; -} void AstCellInline::dump(std::ostream& str) const { this->AstNode::dump(str); str << " -> " << origModName(); str << " [scopep=" << nodeAddr(scopep()) << "]"; } -const char* AstCellInline::broken() const { - BROKEN_RTN(m_scopep && !m_scopep->brokeExists()); - return nullptr; -} -const char* AstClassPackage::broken() const { - BROKEN_BASE_RTN(AstNodeModule::broken()); - BROKEN_RTN(m_classp && !m_classp->brokeExists()); - return nullptr; -} -void AstClassPackage::cloneRelink() { - if (m_classp && m_classp->clonep()) m_classp = m_classp->clonep(); -} bool AstClass::isCacheableChild(const AstNode* nodep) { - return (VN_IS(nodep, Var) || VN_IS(nodep, EnumItemRef) + return (VN_IS(nodep, Var) || VN_IS(nodep, Constraint) || VN_IS(nodep, EnumItemRef) || (VN_IS(nodep, NodeFTask) && !VN_AS(nodep, NodeFTask)->isExternProto()) || VN_IS(nodep, CFunc)); } @@ -1491,17 +1407,6 @@ void AstClass::dump(std::ostream& str) const { if (isInterfaceClass()) str << " [IFCCLS]"; if (isVirtual()) str << " [VIRT]"; } -const char* AstClass::broken() const { - BROKEN_BASE_RTN(AstNodeModule::broken()); - BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); - return nullptr; -} -void AstClass::cloneRelink() { - AstNodeModule::cloneRelink(); - if (m_classOrPackagep && m_classOrPackagep->clonep()) { - m_classOrPackagep = m_classOrPackagep->clonep(); - } -} void AstClassExtends::dump(std::ostream& str) const { this->AstNode::dump(str); if (isImplements()) str << " [IMPLEMENTS]"; @@ -1535,17 +1440,6 @@ void AstClassRefDType::dumpSmall(std::ostream& str) const { this->AstNodeDType::dumpSmall(str); str << "class:" << name(); } -const char* AstClassRefDType::broken() const { - BROKEN_RTN(m_classp && !m_classp->brokeExists()); - BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); - return nullptr; -} -void AstClassRefDType::cloneRelink() { - if (m_classp && m_classp->clonep()) m_classp = m_classp->clonep(); - if (m_classOrPackagep && m_classOrPackagep->clonep()) { - m_classOrPackagep = m_classOrPackagep->clonep(); - } -} string AstClassRefDType::name() const { return classp() ? classp()->name() : ""; } void AstNodeCoverOrAssert::dump(std::ostream& str) const { this->AstNodeStmt::dump(str); @@ -1577,17 +1471,13 @@ void AstEnumItemRef::dump(std::ostream& str) const { str << "UNLINKED"; } } -const char* AstEnumItemRef::broken() const { - BROKEN_RTN(m_itemp && !m_itemp->brokeExists()); - BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); +const char* AstEnumDType::broken() const { + BROKEN_RTN(!((m_refDTypep && !childDTypep()) || (!m_refDTypep && childDTypep()))); + BROKEN_RTN(std::any_of(m_tableMap.begin(), m_tableMap.end(), + [](const auto& p) { return !p.second->brokeExists(); })); return nullptr; } -void AstEnumItemRef::cloneRelink() { - if (m_itemp->clonep()) m_itemp = m_itemp->clonep(); - if (m_classOrPackagep && m_classOrPackagep->clonep()) { - m_classOrPackagep = m_classOrPackagep->clonep(); - } -} + void AstIfaceRefDType::dump(std::ostream& str) const { this->AstNodeDType::dump(str); if (cellName() != "") str << " cell=" << cellName(); @@ -1607,11 +1497,6 @@ void AstIfaceRefDType::dumpSmall(std::ostream& str) const { this->AstNodeDType::dumpSmall(str); str << "iface"; } -void AstIfaceRefDType::cloneRelink() { - if (m_cellp && m_cellp->clonep()) m_cellp = m_cellp->clonep(); - if (m_ifacep && m_ifacep->clonep()) m_ifacep = m_ifacep->clonep(); - if (m_modportp && m_modportp->clonep()) m_modportp = m_modportp->clonep(); -} void AstInitArray::dump(std::ostream& str) const { this->AstNode::dump(str); int n = 0; @@ -1632,6 +1517,7 @@ const char* AstInitArray::broken() const { return nullptr; } void AstInitArray::cloneRelink() { + cloneRelinkGen(); for (KeyItemMap::iterator it = m_map.begin(); it != m_map.end(); ++it) { if (it->second->clonep()) it->second = it->second->clonep(); } @@ -1673,9 +1559,7 @@ const char* AstJumpGo::broken() const { BROKEN_RTN(!labelp()->brokeExistsBelow()); return nullptr; } -void AstJumpGo::cloneRelink() { - if (m_labelp->clonep()) m_labelp = m_labelp->clonep(); -} + void AstJumpLabel::dump(std::ostream& str) const { this->AstNodeStmt::dump(str); str << " -> "; @@ -1713,13 +1597,6 @@ void AstMemberSel::dump(std::ostream& str) const { str << "%Error:UNLINKED"; } } -void AstMemberSel::cloneRelink() { - if (m_varp && m_varp->clonep()) m_varp = m_varp->clonep(); -} -const char* AstMemberSel::broken() const { - BROKEN_RTN(m_varp && !m_varp->brokeExists()); - return nullptr; -} void AstModportFTaskRef::dump(std::ostream& str) const { this->AstNode::dump(str); if (isExport()) str << " EXPORT"; @@ -1731,13 +1608,6 @@ void AstModportFTaskRef::dump(std::ostream& str) const { str << " -> UNLINKED"; } } -const char* AstModportFTaskRef::broken() const { - BROKEN_RTN(m_ftaskp && !m_ftaskp->brokeExists()); - return nullptr; -} -void AstModportFTaskRef::cloneRelink() { - if (m_ftaskp && m_ftaskp->clonep()) m_ftaskp = m_ftaskp->clonep(); -} void AstModportVarRef::dump(std::ostream& str) const { this->AstNode::dump(str); if (direction().isAny()) str << " " << direction(); @@ -1748,13 +1618,6 @@ void AstModportVarRef::dump(std::ostream& str) const { str << " -> UNLINKED"; } } -const char* AstModportVarRef::broken() const { - BROKEN_RTN(m_varp && !m_varp->brokeExists()); - return nullptr; -} -void AstModportVarRef::cloneRelink() { - if (m_varp && m_varp->clonep()) m_varp = m_varp->clonep(); -} void AstPin::dump(std::ostream& str) const { this->AstNode::dump(str); if (modVarp()) { @@ -1766,11 +1629,6 @@ void AstPin::dump(std::ostream& str) const { if (svDotName()) str << " [.n]"; if (svImplicit()) str << " [.SV]"; } -const char* AstPin::broken() const { - BROKEN_RTN(m_modVarp && !m_modVarp->brokeExists()); - BROKEN_RTN(m_modPTypep && !m_modPTypep->brokeExists()); - return nullptr; -} string AstPin::prettyOperatorName() const { return modVarp() ? ((modVarp()->direction().isAny() ? modVarp()->direction().prettyName() + " " : "") @@ -1839,19 +1697,6 @@ void AstRefDType::dumpSmall(std::ostream& str) const { this->AstNodeDType::dumpSmall(str); str << "ref"; } -const char* AstRefDType::broken() const { - BROKEN_RTN(m_typedefp && !m_typedefp->brokeExists()); - BROKEN_RTN(m_refDTypep && !m_refDTypep->brokeExists()); - BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); - return nullptr; -} -void AstRefDType::cloneRelink() { - if (m_typedefp && m_typedefp->clonep()) m_typedefp = m_typedefp->clonep(); - if (m_refDTypep && m_refDTypep->clonep()) m_refDTypep = m_refDTypep->clonep(); - if (m_classOrPackagep && m_classOrPackagep->clonep()) { - m_classOrPackagep = m_classOrPackagep->clonep(); - } -} AstNodeDType* AstRefDType::subDTypep() const VL_MT_STABLE { if (typedefp()) return typedefp()->subDTypep(); return refDTypep(); // Maybe nullptr @@ -1927,18 +1772,6 @@ void AstNetlist::dump(std::ostream& str) const { this->AstNode::dump(str); str << " [" << timeunit() << "/" << timeprecision() << "]"; } -const char* AstNetlist::broken() const { - BROKEN_RTN(m_typeTablep && !m_typeTablep->brokeExists()); - BROKEN_RTN(m_constPoolp && !m_constPoolp->brokeExists()); - BROKEN_RTN(m_dollarUnitPkgp && !m_dollarUnitPkgp->brokeExists()); - BROKEN_RTN(m_evalp && !m_evalp->brokeExists()); - BROKEN_RTN(m_dpiExportTriggerp && !m_dpiExportTriggerp->brokeExists()); - BROKEN_RTN(m_topScopep && !m_topScopep->brokeExists()); - BROKEN_RTN(m_delaySchedulerp && !m_delaySchedulerp->brokeExists()); - BROKEN_RTN(m_nbaEventp && !m_nbaEventp->brokeExists()); - BROKEN_RTN(m_nbaEventTriggerp && !m_nbaEventTriggerp->brokeExists()); - return nullptr; -} AstPackage* AstNetlist::dollarUnitPkgAddp() { if (!m_dollarUnitPkgp) { m_dollarUnitPkgp = new AstPackage{fileline(), AstPackage::dollarUnitName()}; @@ -1973,24 +1806,10 @@ void AstPackageExport::dump(std::ostream& str) const { this->AstNode::dump(str); str << " -> " << packagep(); } -const char* AstPackageExport ::broken() const { - BROKEN_RTN(!m_packagep || !m_packagep->brokeExists()); - return nullptr; -} -void AstPackageExport::cloneRelink() { - if (m_packagep && m_packagep->clonep()) m_packagep = m_packagep->clonep(); -} void AstPackageImport::dump(std::ostream& str) const { this->AstNode::dump(str); str << " -> " << packagep(); } -const char* AstPackageImport::broken() const { - BROKEN_RTN(!m_packagep || !m_packagep->brokeExists()); - return nullptr; -} -void AstPackageImport::cloneRelink() { - if (m_packagep && m_packagep->clonep()) m_packagep = m_packagep->clonep(); -} void AstPatMember::dump(std::ostream& str) const { this->AstNodeExpr::dump(str); if (isDefault()) str << " [DEFAULT]"; @@ -2144,7 +1963,7 @@ void AstVarRef::dump(std::ostream& str) const { } const char* AstVarRef::broken() const { BROKEN_RTN(!varp()); - return AstNodeVarRef::broken(); + return nullptr; } bool AstVarRef::same(const AstNode* samep) const { return same(VN_DBG_AS(samep, VarRef)); } int AstVarRef::instrCount() const { @@ -2255,13 +2074,6 @@ void AstActive::dump(std::ostream& str) const { str << "UNLINKED"; } } -const char* AstActive::broken() const { - BROKEN_RTN(m_sensesp && !m_sensesp->brokeExists()); - return nullptr; -} -void AstActive::cloneRelink() { - if (m_sensesp->clonep()) m_sensesp = m_sensesp->clonep(); -} void AstNodeFTaskRef::dump(std::ostream& str) const { this->AstNodeExpr::dump(str); if (classOrPackagep()) str << " pkg=" << nodeAddr(classOrPackagep()); @@ -2392,13 +2204,7 @@ void AstCFunc::dump(std::ostream& str) const { if (isVirtual()) str << " [VIRT]"; if (isCoroutine()) str << " [CORO]"; if (needProcess()) str << " [NPRC]"; -} -const char* AstCAwait::broken() const { - BROKEN_RTN(m_sensesp && !m_sensesp->brokeExists()); - return nullptr; -} -void AstCAwait::cloneRelink() { - if (m_sensesp && m_sensesp->clonep()) m_sensesp = m_sensesp->clonep(); + if (entryPoint()) str << " [ENTRY]"; } void AstCAwait::dump(std::ostream& str) const { this->AstNodeUniop::dump(str); @@ -2446,6 +2252,7 @@ void AstCMethodHard::setPurity() { {"first", false}, {"init", false}, {"insert", false}, + {"inside", true}, {"isFired", true}, {"isTriggered", true}, {"join", false}, @@ -2488,13 +2295,6 @@ void AstCMethodHard::setPurity() { UASSERT_OBJ(isPureIt != isPureMethod.end(), this, "Unknown purity of method " + name()); m_pure = isPureIt->second; } -const char* AstCFunc::broken() const { - BROKEN_RTN((m_scopep && !m_scopep->brokeExists())); - return nullptr; -} -void AstCFunc::cloneRelink() { - if (m_scopep && m_scopep->clonep()) m_scopep = m_scopep->clonep(); -} void AstCUse::dump(std::ostream& str) const { this->AstNode::dump(str); diff --git a/src/V3AstUserAllocator.h b/src/V3AstUserAllocator.h index a30917a71..e18aea1b1 100644 --- a/src/V3AstUserAllocator.h +++ b/src/V3AstUserAllocator.h @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp index b4fa16a24..370c3b794 100644 --- a/src/V3Begin.cpp +++ b/src/V3Begin.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -35,7 +35,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class BeginState final { -private: // NODE STATE // Entire netlist: // AstNodeFTask::user1 -> bool, 1=processed @@ -55,7 +54,6 @@ public: //###################################################################### class BeginVisitor final : public VNVisitor { -private: // STATE BeginState* const m_statep; // Current global state AstNodeModule* m_modp = nullptr; // Current module @@ -320,7 +318,7 @@ public: //###################################################################### -class BeginRelinkVisitor final : public VNVisitor { +class BeginRelinkVisitor final : public VNVisitorConst { // Replace tasks with new pointer private: // NODE STATE @@ -333,13 +331,13 @@ private: UINFO(9, " relinkFTask " << nodep << endl); nodep->name(nodep->taskp()->name()); } - iterateChildren(nodep); + iterateChildrenConst(nodep); } void visit(AstVarRef* nodep) override { if (nodep->varp()->user1()) { // It was converted UINFO(9, " relinVarRef " << nodep << endl); } - iterateChildren(nodep); + iterateChildrenConst(nodep); } void visit(AstIfaceRefDType* nodep) override { // May have changed cell names @@ -347,14 +345,14 @@ private: UINFO(8, " IFACEREFDTYPE " << nodep << endl); if (nodep->cellp()) nodep->cellName(nodep->cellp()->name()); UINFO(8, " rename to " << nodep << endl); - iterateChildren(nodep); + iterateChildrenConst(nodep); } //-------------------- - void visit(AstNode* nodep) override { iterateChildren(nodep); } + void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } public: // CONSTRUCTORS - BeginRelinkVisitor(AstNetlist* nodep, BeginState*) { iterate(nodep); } + BeginRelinkVisitor(AstNetlist* nodep, BeginState*) { iterateConst(nodep); } ~BeginRelinkVisitor() override = default; }; diff --git a/src/V3Begin.h b/src/V3Begin.h index b2cd44a01..ccb850209 100644 --- a/src/V3Begin.h +++ b/src/V3Begin.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Branch.cpp b/src/V3Branch.cpp index e297f59a9..e26b066ee 100644 --- a/src/V3Branch.cpp +++ b/src/V3Branch.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,7 +33,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Branch state, as a visitor of each AstNode class BranchVisitor final : public VNVisitorConst { -private: // NODE STATE // Entire netlist: // AstFTask::user1() -> int. Number of references diff --git a/src/V3Branch.h b/src/V3Branch.h index 79f793307..7357ef907 100644 --- a/src/V3Branch.h +++ b/src/V3Branch.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Broken.cpp b/src/V3Broken.cpp index 5daa4f5a8..94e97ce76 100644 --- a/src/V3Broken.cpp +++ b/src/V3Broken.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -60,7 +60,6 @@ static bool s_brokenAllowMidvisitorCheck = false; // Table of allocated AstNode pointers static class AllocTable final { -private: // MEMBERS std::unordered_set m_allocated; // Set of all nodes allocated but not freed @@ -122,7 +121,6 @@ void V3Broken::deleted(const AstNode* nodep) { s_allocTable.deleted(nodep); } // Table of AstNode pointers that can be linked to via member pointers static class LinkableTable final { -private: // MEMBERS std::unordered_set m_linkable; // Set of all nodes allocated but not freed @@ -166,7 +164,7 @@ private: void processEnter(AstNode* nodep) { nodep->brokenState(m_brokenCntCurrentUnder); - const char* const whyp = nodep->broken(); + const char* const whyp = nodep->brokenGen(); UASSERT_OBJ(!whyp, nodep, "Broken link in node (or something without maybePointedTo): " << whyp); if (!s_brokenAllowMidvisitorCheck) nodep->checkIter(); diff --git a/src/V3Broken.h b/src/V3Broken.h index d98add08b..7e8f7c099 100644 --- a/src/V3Broken.h +++ b/src/V3Broken.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3CCtors.cpp b/src/V3CCtors.cpp index 1f8abb5c3..5f50f4128 100644 --- a/src/V3CCtors.cpp +++ b/src/V3CCtors.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -50,7 +50,6 @@ public: }; class V3CCtorsBuilder final { -private: AstNodeModule* const m_modp; // Current module/class const string m_basename; const VCtorType m_type; // What kind of constructor are we creating @@ -130,7 +129,6 @@ private: // Link state, as a visitor of each AstNode class CCtorsVisitor final : public VNVisitor { -private: // NODE STATE // STATE diff --git a/src/V3CCtors.h b/src/V3CCtors.h index c719d65d1..b719ee466 100644 --- a/src/V3CCtors.h +++ b/src/V3CCtors.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3CUse.cpp b/src/V3CUse.cpp index 748909c2e..5ad565677 100644 --- a/src/V3CUse.cpp +++ b/src/V3CUse.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,7 +33,7 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Visit within a module all nodes and data types they reference, finding // any classes so we can make sure they are defined when Verilated code // compiles -class CUseVisitor final : public VNVisitor { +class CUseVisitor final : public VNVisitorConst { // NODE STATE // AstNode::user1() -> bool. True if already visited const VNUser1InUse m_inuser1; @@ -56,44 +56,44 @@ class CUseVisitor final : public VNVisitor { } void visit(AstCFunc* nodep) override { if (nodep->user1SetOnce()) return; - iterateAndNextNull(nodep->argsp()); - iterateAndNextNull(nodep->stmtsp()); + iterateAndNextConstNull(nodep->argsp()); + iterateAndNextConstNull(nodep->stmtsp()); } void visit(AstCCall* nodep) override { return; } void visit(AstCReturn* nodep) override { UASSERT(!nodep->user1SetOnce(), "Visited same return twice."); - iterate(nodep->lhsp()->dtypep()); + iterateConst(nodep->lhsp()->dtypep()); } void visit(AstNodeDType* nodep) override { - if (nodep->virtRefDTypep()) iterate(nodep->virtRefDTypep()); - if (nodep->virtRefDType2p()) iterate(nodep->virtRefDType2p()); + if (nodep->virtRefDTypep()) iterateConst(nodep->virtRefDTypep()); + if (nodep->virtRefDType2p()) iterateConst(nodep->virtRefDType2p()); // Add a CUse for every struct that requires a declaration AstNodeUOrStructDType* const stypep = VN_CAST(nodep->skipRefp(), NodeUOrStructDType); if (stypep && stypep->classOrPackagep()) { addNewUse(nodep, VUseType::INT_INCLUDE, stypep->classOrPackagep()->name()); - iterateChildren(stypep); + iterateChildrenConst(stypep); } else if (AstClassRefDType* const classp = VN_CAST(nodep->skipRefp(), ClassRefDType)) { addNewUse(nodep, VUseType::INT_FWD_CLASS, classp->name()); } } void visit(AstNode* nodep) override { if (nodep->user1SetOnce()) return; // Process once - if (nodep->dtypep()) iterate(nodep->dtypep()); - iterateChildren(nodep); + if (nodep->dtypep()) iterateConst(nodep->dtypep()); + iterateChildrenConst(nodep); } void visit(AstCell* nodep) override { if (nodep->user1SetOnce()) return; // Process once // Currently no IMP_INCLUDE because we include __Syms which has them all addNewUse(nodep, VUseType::INT_FWD_CLASS, nodep->modp()->name()); - iterateChildren(nodep); + iterateChildrenConst(nodep); } public: // CONSTRUCTORS explicit CUseVisitor(AstNodeModule* modp) : m_modp(modp) { - iterate(modp); + iterateConst(modp); for (auto& used : m_didUse) { AstCUse* const newp = new AstCUse{used.second.first, used.second.second, used.first}; diff --git a/src/V3CUse.h b/src/V3CUse.h index 4e475f3b8..5c864adba 100644 --- a/src/V3CUse.h +++ b/src/V3CUse.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Case.cpp b/src/V3Case.cpp index 89458cda8..fcaa828a5 100644 --- a/src/V3Case.cpp +++ b/src/V3Case.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -49,7 +49,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class CaseLintVisitor final : public VNVisitorConst { -private: const AstNodeCase* m_caseExprp = nullptr; // Under a CASE value node, if so the relevant case statement @@ -115,7 +114,6 @@ public: // Case state, as a visitor of each AstNode class CaseVisitor final : public VNVisitor { -private: // NODE STATE // Cleared each Case // AstIf::user3() -> bool. Set true to indicate clone not needed diff --git a/src/V3Case.h b/src/V3Case.h index d78984d16..7233866ed 100644 --- a/src/V3Case.h +++ b/src/V3Case.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Cast.cpp b/src/V3Cast.cpp index c8181a118..c6720efd3 100644 --- a/src/V3Cast.cpp +++ b/src/V3Cast.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -47,7 +47,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Cast state, as a visitor of each AstNode class CastVisitor final : public VNVisitor { -private: // NODE STATE // Entire netlist: // AstNode::user1() // bool. Indicates node is of known size @@ -120,7 +119,7 @@ private: // All class types are castable to each other. If they are of different types, // a compilation error will be thrown, so an explicit cast is required. Types were // already checked by V3Width and dtypep of a condition operator is a type of their - // common base class, so both classes can be safetly casted. + // common base class, so both classes can be safely casted. const AstClassRefDType* const thenClassDtypep = VN_CAST(nodep->thenp()->dtypep(), ClassRefDType); const AstClassRefDType* const elseClassDtypep diff --git a/src/V3Cast.h b/src/V3Cast.h index 23177ced6..d519b5c74 100644 --- a/src/V3Cast.h +++ b/src/V3Cast.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Class.cpp b/src/V3Class.cpp index 3ca8fedbf..545e76419 100644 --- a/src/V3Class.cpp +++ b/src/V3Class.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -31,7 +31,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class ClassVisitor final : public VNVisitor { -private: // NODE STATE // AstClass::user1() -> bool. True if iterated already // AstVar::user1p() -> AstVarScope* Scope used with this var diff --git a/src/V3Class.h b/src/V3Class.h index 8401a9504..072566cab 100644 --- a/src/V3Class.h +++ b/src/V3Class.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Clean.cpp b/src/V3Clean.cpp index 00ddad214..50dd4c576 100644 --- a/src/V3Clean.cpp +++ b/src/V3Clean.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,7 +33,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Clean state, as a visitor of each AstNode class CleanVisitor final : public VNVisitor { -private: // NODE STATE // Entire netlist: // AstNode::user() -> CleanState. For this node, 0==UNKNOWN @@ -239,10 +238,7 @@ private: if (AstNodeExpr* const exprp = VN_CAST(argp, NodeExpr)) ensureClean(exprp); } } - void visit(AstTraceDecl* nodep) override { - // No cleaning, or would loose pointer to enum - iterateChildren(nodep); - } + void visit(AstTraceDecl* nodep) override {} // Nothing to do here void visit(AstTraceInc* nodep) override { iterateChildren(nodep); ensureCleanAndNext(nodep->valuep()); diff --git a/src/V3Clean.h b/src/V3Clean.h index be37e2420..5112001fd 100644 --- a/src/V3Clean.h +++ b/src/V3Clean.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Clock.cpp b/src/V3Clock.cpp index 98596e135..d58d8c138 100644 --- a/src/V3Clock.cpp +++ b/src/V3Clock.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -39,7 +39,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Convert every WRITE AstVarRef to a READ ref class ConvertWriteRefsToRead final : public VNVisitor { -private: // MEMBERS AstNodeExpr* m_result = nullptr; @@ -67,7 +66,6 @@ public: // Clock state, as a visitor of each AstNode class ClockVisitor final : public VNVisitor { -private: // STATE AstCFunc* m_evalp = nullptr; // The '_eval' function AstScope* m_scopep = nullptr; // Current scope diff --git a/src/V3Clock.h b/src/V3Clock.h index da009685b..ab7906645 100644 --- a/src/V3Clock.h +++ b/src/V3Clock.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Combine.cpp b/src/V3Combine.cpp index 2b858de6c..0fc717789 100644 --- a/src/V3Combine.cpp +++ b/src/V3Combine.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Combine.h b/src/V3Combine.h index 466cb850c..8778f7eaa 100644 --- a/src/V3Combine.h +++ b/src/V3Combine.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Common.cpp b/src/V3Common.cpp index 6288ccea9..891ca15cf 100644 --- a/src/V3Common.cpp +++ b/src/V3Common.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Common.h b/src/V3Common.h index 854077e07..bc3e0e9dc 100644 --- a/src/V3Common.h +++ b/src/V3Common.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Config.cpp b/src/V3Config.cpp index 69a55e7fc..82af60789 100644 --- a/src/V3Config.cpp +++ b/src/V3Config.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2010-2023 by Wilson Snyder. This program is free software; you +// Copyright 2010-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -610,7 +610,7 @@ void V3Config::applyIgnores(FileLine* filelinep) { } void V3Config::applyModule(AstNodeModule* modulep) { - const string& modname = modulep->name(); + const string& modname = modulep->origName(); V3ConfigModule* modp = V3ConfigResolver::s().modules().resolve(modname); if (modp) modp->apply(modulep); } diff --git a/src/V3Config.h b/src/V3Config.h index 6b49a0997..f5e0668b0 100644 --- a/src/V3Config.h +++ b/src/V3Config.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2010-2023 by Wilson Snyder. This program is free software; you +// Copyright 2010-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Const.cpp b/src/V3Const.cpp index bb68a436b..a4a0e7fc7 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -462,7 +462,7 @@ class ConstBitOpTreeVisitor final : public VNVisitorConst { void visit(AstWordSel* nodep) override { CONST_BITOP_RETURN_IF(!m_leafp, nodep); AstConst* const constp = VN_CAST(nodep->bitp(), Const); - CONST_BITOP_RETURN_IF(!constp, nodep->rhsp()); + CONST_BITOP_RETURN_IF(!constp, nodep->bitp()); UASSERT_OBJ(m_leafp->wordIdx() == -1, nodep, "Unexpected nested WordSel"); m_leafp->wordIdx(constp->toSInt()); iterateConst(nodep->fromp()); @@ -768,16 +768,16 @@ public: if (needsCleaning) ++resultOps; if (debug() >= 9) { // LCOV_EXCL_START - cout << "- Bitop tree considered: " << endl; + cout << "- Bitop tree considered:\n"; for (AstNodeExpr* const termp : termps) termp->dumpTree("- Reduced term: "); for (const std::pair& termp : visitor.m_frozenNodes) { termp.first->dumpTree("- Frozen term with lsb " + std::to_string(termp.second.m_lsb) + " polarity " + std::to_string(termp.second.m_polarity) + ": "); } - cout << "- Needs flipping: " << needsFlip << endl; - cout << "- Needs cleaning: " << needsCleaning << endl; - cout << "- Size: " << resultOps << " input size: " << visitor.m_ops << endl; + cout << "- Needs flipping: " << needsFlip << "\n"; + cout << "- Needs cleaning: " << needsCleaning << "\n"; + cout << "- Size: " << resultOps << " input size: " << visitor.m_ops << "\n"; } // LCOV_EXCL_END // Sometimes we have no terms left after ignoring redundant terms @@ -878,7 +878,6 @@ public: // Const state, as a visitor of each AstNode class ConstVisitor final : public VNVisitor { -private: // CONSTANTS static constexpr unsigned CONCAT_MERGABLE_MAX_DEPTH = 10; // Limit alg recursion @@ -1126,7 +1125,7 @@ private: // commonly appears after V3Expand and the simplification in matchMaskedOr. Similarly, // drop redundant masking of left shift result. E.g.: 0xff000000 & ((uint32_t)a << 24). - const auto checkMask = [=](const V3Number& mask) -> bool { + const auto checkMask = [nodep, this](const V3Number& mask) -> bool { const AstConst* const constp = VN_AS(nodep->lhsp(), Const); if (constp->num().isCaseEq(mask)) { AstNode* const rhsp = nodep->rhsp(); @@ -1222,13 +1221,16 @@ private: } bool operandHugeShiftL(const AstNodeBiop* nodep) { return (VN_IS(nodep->rhsp(), Const) && !VN_AS(nodep->rhsp(), Const)->num().isFourState() - && (VN_AS(nodep->rhsp(), Const)->toUInt() >= static_cast(nodep->width())) + && (!VN_AS(nodep->rhsp(), Const)->num().fitsInUInt() // > 2^32 shift + || (VN_AS(nodep->rhsp(), Const)->toUInt() + >= static_cast(nodep->width()))) && nodep->lhsp()->isPure()); } bool operandHugeShiftR(const AstNodeBiop* nodep) { return (VN_IS(nodep->rhsp(), Const) && !VN_AS(nodep->rhsp(), Const)->num().isFourState() - && (VN_AS(nodep->rhsp(), Const)->toUInt() - >= static_cast(nodep->lhsp()->width())) + && (!VN_AS(nodep->rhsp(), Const)->num().fitsInUInt() // > 2^32 shift + || (VN_AS(nodep->rhsp(), Const)->toUInt() + >= static_cast(nodep->lhsp()->width()))) && nodep->lhsp()->isPure()); } bool operandIsTwo(const AstNode* nodep) { @@ -1269,9 +1271,9 @@ private: // V3Expand may make a arraysel that exceeds the bounds of the array // It was an expression, then got constified. In reality, the WordSel // must be wrapped in a Cond, that will be false. - return (VN_IS(nodep->rhsp(), Const) && VN_IS(nodep->fromp(), NodeVarRef) + return (VN_IS(nodep->bitp(), Const) && VN_IS(nodep->fromp(), NodeVarRef) && VN_AS(nodep->fromp(), NodeVarRef)->access().isReadOnly() - && (static_cast(VN_AS(nodep->rhsp(), Const)->toUInt()) + && (static_cast(VN_AS(nodep->bitp(), Const)->toUInt()) >= VN_AS(nodep->fromp(), NodeVarRef)->varp()->widthWords())); } bool operandSelFull(const AstSel* nodep) { @@ -2539,7 +2541,7 @@ private: // SEL(REPLICATE(from,rep),lsb,width) => SEL(from,0,width) as long // as SEL's width <= b's width AstReplicate* const repp = VN_AS(nodep->fromp(), Replicate); - AstNodeExpr* const fromp = repp->lhsp(); + AstNodeExpr* const fromp = repp->srcp(); AstConst* const lsbp = VN_CAST(nodep->lsbp(), Const); if (!lsbp) return false; AstNodeExpr* const widthp = nodep->widthp(); @@ -2562,11 +2564,11 @@ private: } bool operandRepRep(AstReplicate* nodep) { // REPLICATE(REPLICATE2(from2,cnt2),cnt1) => REPLICATE(from2,(cnt1+cnt2)) - AstReplicate* const rep2p = VN_AS(nodep->lhsp(), Replicate); - AstNodeExpr* const from2p = rep2p->lhsp(); - AstConst* const cnt1p = VN_CAST(nodep->rhsp(), Const); + AstReplicate* const rep2p = VN_AS(nodep->srcp(), Replicate); + AstNodeExpr* const from2p = rep2p->srcp(); + AstConst* const cnt1p = VN_CAST(nodep->countp(), Const); if (!cnt1p) return false; - AstConst* const cnt2p = VN_CAST(rep2p->rhsp(), Const); + AstConst* const cnt2p = VN_CAST(rep2p->countp(), Const); if (!cnt2p) return false; // from2p->unlinkFrBack(); @@ -2589,15 +2591,15 @@ private: AstNodeExpr* from2p = nodep->rhsp(); uint32_t cnt2 = 1; if (VN_IS(from1p, Replicate)) { - AstConst* const cnt1p = VN_CAST(VN_CAST(from1p, Replicate)->rhsp(), Const); + AstConst* const cnt1p = VN_CAST(VN_CAST(from1p, Replicate)->countp(), Const); if (!cnt1p) return false; - from1p = VN_AS(from1p, Replicate)->lhsp(); + from1p = VN_AS(from1p, Replicate)->srcp(); cnt1 = cnt1p->toUInt(); } if (VN_IS(from2p, Replicate)) { - AstConst* const cnt2p = VN_CAST(VN_CAST(from2p, Replicate)->rhsp(), Const); + AstConst* const cnt2p = VN_CAST(VN_CAST(from2p, Replicate)->countp(), Const); if (!cnt2p) return false; - from2p = VN_AS(from2p, Replicate)->lhsp(); + from2p = VN_AS(from2p, Replicate)->srcp(); cnt2 = cnt2p->toUInt(); } if (!operandsSame(from1p, from2p)) return false; @@ -2692,7 +2694,7 @@ private: && m_doNConst && v3Global.opt.fConst() // Default value, not a "known" constant for this usage - && !nodep->varp()->isClassMember() && !nodep->varp()->isUsedVirtIface() + && !nodep->varp()->isClassMember() && !nodep->varp()->sensIfacep() && !(nodep->varp()->isFuncLocal() && nodep->varp()->isNonOutput()) && !nodep->varp()->noSubst() && !nodep->varp()->isSigPublic()) || nodep->varp()->isParam())) { @@ -3432,10 +3434,6 @@ private: TREEOP ("AstPowSS {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule TREEOP ("AstPowSU {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule TREEOP ("AstPowUS {$rhsp.isZero}", "replaceNum(nodep, 1)"); // Overrides lhs zero rule - TREEOP ("AstPow {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)"); - TREEOP ("AstPowSU {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)"); - TREEOP ("AstPowUS {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)"); - TREEOP ("AstPowSU {$lhsp.isZero, !$rhsp.isZero}", "replaceZeroChkPure(nodep,$rhsp)"); TREEOP ("AstOr {$lhsp.isZero, $rhsp}", "replaceWRhs(nodep)"); TREEOP ("AstShiftL {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)"); TREEOP ("AstShiftLOvr {$lhsp.isZero, $rhsp}", "replaceZeroChkPure(nodep,$rhsp)"); @@ -3477,7 +3475,7 @@ private: TREEOP ("AstMul {operandIsPowTwo($lhsp), operandsSameSize($lhsp,,$rhsp)}", "replaceMulShift(nodep)"); // a*2^n -> a< a>>n TREEOP ("AstModDiv{$lhsp, operandIsPowTwo($rhsp)}", "replaceModAnd(nodep)"); // a % 2^n -> a&(2^n-1) - TREEOP ("AstPow {operandIsTwo($lhsp), $rhsp}", "replacePowShift(nodep)"); // 2**a == 1<castAdd()->lhsp(),$rhsp}, $lhsp->castAdd()->rhsp()}"); // ((a+x)-y) -> (a+(x-y)) TREEOPC("AstAnd {$lhsp.isOne, matchRedundantClean(nodep)}", "DONE") // 1 & (a == b) -> (IData)(a == b) // Trinary ops @@ -3488,8 +3486,8 @@ private: TREEOPA("AstNodeCond{$condp.isNeqZero, $thenp.castConst, $elsep.castConst}", "replaceWChild(nodep,$thenp)"); TREEOP ("AstNodeCond{$condp, operandsSame($thenp,,$elsep)}","replaceWChild(nodep,$thenp)"); // This visit function here must allow for short-circuiting. - TREEOPS("AstCond {$lhsp.isZero}", "replaceWIteratedThs(nodep)"); - TREEOPS("AstCond {$lhsp.isNeqZero}", "replaceWIteratedRhs(nodep)"); + TREEOPS("AstCond {$condp.isZero}", "replaceWIteratedThs(nodep)"); + TREEOPS("AstCond {$condp.isNeqZero}", "replaceWIteratedRhs(nodep)"); TREEOP ("AstCond{$condp.castNot, $thenp, $elsep}", "AstCond{$condp->castNot()->lhsp(), $elsep, $thenp}"); TREEOP ("AstNodeCond{$condp.width1, $thenp.width1, $thenp.isAllOnes, $elsep}", "AstLogOr {$condp, $elsep}"); // a?1:b == a||b TREEOP ("AstNodeCond{$condp.width1, $thenp.width1, $thenp, $elsep.isZero, !$elsep.isClassHandleValue}", "AstLogAnd{$condp, $thenp}"); // a?b:0 == a&&b @@ -3670,9 +3668,9 @@ private: // bits end up in the wrong places TREEOPV("AstExtend {$lhsp.castExtend}", "replaceExtend(nodep, VN_AS(nodep->lhsp(), Extend)->lhsp())"); TREEOPV("AstExtendS{$lhsp.castExtendS}", "replaceExtend(nodep, VN_AS(nodep->lhsp(), ExtendS)->lhsp())"); - TREEOPV("AstReplicate{$lhsp, $rhsp.isOne, $lhsp->width()==nodep->width()}", "replaceWLhs(nodep)"); // {1{lhs}}->lhs + TREEOPV("AstReplicate{$srcp, $countp.isOne, $srcp->width()==nodep->width()}", "replaceWLhs(nodep)"); // {1{lhs}}->lhs TREEOPV("AstReplicateN{$lhsp, $rhsp.isOne, $lhsp->width()==nodep->width()}", "replaceWLhs(nodep)"); // {1{lhs}}->lhs - TREEOPV("AstReplicate{$lhsp.castReplicate, operandRepRep(nodep)}", "DONE"); // {2{3{lhs}}}->{6{lhs}} + TREEOPV("AstReplicate{$srcp.castReplicate, operandRepRep(nodep)}", "DONE"); // {2{3{lhs}}}->{6{lhs}} TREEOPV("AstConcat{operandConcatSame(nodep)}", "DONE"); // {a,a}->{2{a}}, {a,2{a}}->{3{a}, etc // Next rule because AUTOINST puts the width of bits in // to pins, even when the widths are exactly the same across the hierarchy. @@ -3694,9 +3692,9 @@ private: // win if bit select is a constant (otherwise we may need to compute bit index several times) TREEOPV("AstSel{$fromp.castBufIf1}", "replaceSelIntoBiop(nodep)"); TREEOPV("AstSel{$fromp.castNot}", "replaceSelIntoUniop(nodep)"); - TREEOPV("AstSel{$fromp.castAnd,$lhsp.castConst}", "replaceSelIntoUniop(nodep)"); - TREEOPV("AstSel{$fromp.castOr,$lhsp.castConst}", "replaceSelIntoUniop(nodep)"); - TREEOPV("AstSel{$fromp.castXor,$lhsp.castConst}", "replaceSelIntoUniop(nodep)"); + TREEOPV("AstSel{$fromp.castAnd,$lsbp.castConst}", "replaceSelIntoBiop(nodep)"); + TREEOPV("AstSel{$fromp.castOr,$lsbp.castConst}", "replaceSelIntoBiop(nodep)"); + TREEOPV("AstSel{$fromp.castXor,$lsbp.castConst}", "replaceSelIntoBiop(nodep)"); // This visit function here must allow for short-circuiting. TREEOPS("AstLogIf{$lhsp.isZero}", "replaceNum(nodep, 1)"); TREEOPV("AstLogIf{$lhsp, $rhsp}", "AstLogOr{AstLogNot{$lhsp},$rhsp}"); diff --git a/src/V3Const.h b/src/V3Const.h index e992faca8..20e1bb95d 100644 --- a/src/V3Const.h +++ b/src/V3Const.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index c1a5bed9f..e1d188621 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -36,7 +36,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Coverage state, as a visitor of each AstNode class CoverageVisitor final : public VNVisitor { -private: // TYPES using LinenoSet = std::set; diff --git a/src/V3Coverage.h b/src/V3Coverage.h index b3a48739b..36a5558ba 100644 --- a/src/V3Coverage.h +++ b/src/V3Coverage.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3CoverageJoin.cpp b/src/V3CoverageJoin.cpp index 76f0e7bdf..7f6603f7d 100644 --- a/src/V3CoverageJoin.cpp +++ b/src/V3CoverageJoin.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,7 +32,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // CoverageJoin state, as a visitor of each AstNode class CoverageJoinVisitor final : public VNVisitor { -private: // NODE STATE // VNUser4InUse In V3Hasher via V3DupFinder diff --git a/src/V3CoverageJoin.h b/src/V3CoverageJoin.h index 9441b3742..07d83fa0b 100644 --- a/src/V3CoverageJoin.h +++ b/src/V3CoverageJoin.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Dead.cpp b/src/V3Dead.cpp index 768887b5f..66a3ced92 100644 --- a/src/V3Dead.cpp +++ b/src/V3Dead.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -45,7 +45,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Dead state, as a visitor of each AstNode class DeadVisitor final : public VNVisitor { -private: // NODE STATE // Entire Netlist: // AstNodeModule::user1() -> int. Count of number of cells referencing this module. @@ -79,6 +78,11 @@ private: // METHODS + void deleting(AstNode* nodep) { + UINFO(9, " deleting " << nodep << endl); + VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); + } + void checkAll(AstNode* nodep) { if (nodep != nodep->dtypep()) { // NodeDTypes reference themselves if (AstNode* const subnodep = nodep->dtypep()) subnodep->user1Inc(); @@ -239,7 +243,7 @@ private: iterateChildren(nodep); if (m_elimCells) { if (!nodep->varsp()) { - VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); + deleting(nodep); return; } } @@ -287,7 +291,7 @@ private: checkAll(nodep); // Has to be direct assignment without any EXTRACTing. AstVarRef* const varrefp = VN_CAST(nodep->lhsp(), VarRef); - if (varrefp && !m_sideEffect + if (varrefp && !m_sideEffect && v3Global.opt.fDeadAssigns() && varrefp->varScopep()) { // For simplicity, we only remove post-scoping m_assignMap.emplace(varrefp->varScopep(), nodep); checkAll(varrefp); // Must track reference to dtype() @@ -316,7 +320,7 @@ private: void deadCheckTypedefs() { for (AstTypedef* typedefp : m_typedefsp) { if (shouldDeleteTypedef(typedefp)) { - VL_DO_DANGLING(pushDeletep(typedefp->unlinkFrBack()), typedefp); + deleting(typedefp); continue; } checkAll(typedefp); @@ -349,7 +353,7 @@ private: cellp->modp()->user1Inc(-1); }); } - VL_DO_DANGLING(modp->unlinkFrBack()->deleteTree(), modp); + deleting(modp); retry = true; } } @@ -357,7 +361,7 @@ private: } bool mightElimVar(AstVar* nodep) const { if (nodep->isSigPublic()) return false; // Can't elim publics! - if (nodep->isIO() || nodep->isClassMember() || nodep->isUsedVirtIface()) return false; + if (nodep->isIO() || nodep->isClassMember() || nodep->sensIfacep()) return false; if (nodep->isTemp() && !nodep->isTrace()) return true; return m_elimUserVars; // Post-Trace can kill most anything } @@ -373,7 +377,7 @@ private: UINFO(4, " Dead AstScope " << scp << endl); scp->aboveScopep()->user1Inc(-1); if (scp->dtypep()) scp->dtypep()->user1Inc(-1); - VL_DO_DANGLING(scp->unlinkFrBack()->deleteTree(), scp); + deleting(scp); *it = nullptr; retry = true; } @@ -383,9 +387,9 @@ private: void deadCheckCells() { for (AstCell* cellp : m_cellsp) { - if (cellp->user1() == 0 && !cellp->modp()->stmtsp()) { + if (cellp->user1() == 0 && !cellp->modp()->stmtsp() && v3Global.opt.fDeadCells()) { cellp->modp()->user1Inc(-1); - VL_DO_DANGLING(cellp->unlinkFrBack()->deleteTree(), cellp); + deleting(cellp); } } } @@ -397,7 +401,7 @@ private: if (nodep->user1() == 0) { if (nodep->extendsp()) nodep->extendsp()->user1Inc(-1); if (nodep->classOrPackagep()) nodep->classOrPackagep()->user1Inc(-1); - VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); + deleting(nodep); itr = nullptr; retry = true; } @@ -417,11 +421,11 @@ private: AstNodeAssign* const assp = itr->second; UINFO(4, " Dead assign " << assp << endl); assp->dtypep()->user1Inc(-1); - VL_DO_DANGLING(assp->unlinkFrBack()->deleteTree(), assp); + deleting(assp); } if (vscp->scopep()) vscp->scopep()->user1Inc(-1); vscp->dtypep()->user1Inc(-1); - VL_DO_DANGLING(vscp->unlinkFrBack()->deleteTree(), vscp); + deleting(vscp); } } for (bool retry = true; retry;) { @@ -432,7 +436,7 @@ private: if (varp->user1() == 0) { UINFO(4, " Dead " << varp << endl); if (varp->dtypep()) varp->dtypep()->user1Inc(-1); - VL_DO_DANGLING(varp->unlinkFrBack()->deleteTree(), varp); + deleting(varp); *it = nullptr; retry = true; } @@ -440,11 +444,11 @@ private: } for (std::vector::iterator it = m_dtypesp.begin(); it != m_dtypesp.end(); ++it) { if ((*it)->user1() == 0) { - const AstNodeUOrStructDType* classp; // It's possible that there if a reference to each individual member, but // not to the dtype itself. Check and don't remove the parent dtype if // members are still alive. - if ((classp = VN_CAST((*it), NodeUOrStructDType))) { + if (const AstNodeUOrStructDType* const classp + = VN_CAST((*it), NodeUOrStructDType)) { bool cont = true; for (AstMemberDType* memberp = classp->membersp(); memberp; memberp = VN_AS(memberp->nextp(), MemberDType)) { @@ -455,7 +459,7 @@ private: } if (!cont) continue; } - VL_DO_DANGLING((*it)->unlinkFrBack()->deleteTree(), *it); + deleting(*it); } } } diff --git a/src/V3Dead.h b/src/V3Dead.h index 614bc7270..885a42c2a 100644 --- a/src/V3Dead.h +++ b/src/V3Dead.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index da769536e..79205f615 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -63,7 +63,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Delayed state, as a visitor of each AstNode class DelayedVisitor final : public VNVisitor { -private: // NODE STATE // Cleared each module: // AstVarScope::user1p() -> aux diff --git a/src/V3Delayed.h b/src/V3Delayed.h index c8147cb0d..a70f8fa82 100644 --- a/src/V3Delayed.h +++ b/src/V3Delayed.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp index a459a26c7..51785fc8a 100644 --- a/src/V3Depth.cpp +++ b/src/V3Depth.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,7 +34,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class DepthVisitor final : public VNVisitor { -private: // NODE STATE // STATE diff --git a/src/V3Depth.h b/src/V3Depth.h index b844330cf..8ac8b2077 100644 --- a/src/V3Depth.h +++ b/src/V3Depth.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3DepthBlock.cpp b/src/V3DepthBlock.cpp index 378f83d0c..d9fe7dd79 100644 --- a/src/V3DepthBlock.cpp +++ b/src/V3DepthBlock.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -31,7 +31,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class DepthBlockVisitor final : public VNVisitor { -private: // NODE STATE // STATE diff --git a/src/V3DepthBlock.h b/src/V3DepthBlock.h index 9f29b0ce9..ab34bbb7c 100644 --- a/src/V3DepthBlock.h +++ b/src/V3DepthBlock.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp index c603204f0..6f224ab85 100644 --- a/src/V3Descope.cpp +++ b/src/V3Descope.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,7 +33,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class DescopeVisitor final : public VNVisitor { -private: // NODE STATE // Cleared entire netlist // AstCFunc::user() // bool. Indicates processing completed diff --git a/src/V3Descope.h b/src/V3Descope.h index ff1e0a9ff..017476129 100644 --- a/src/V3Descope.h +++ b/src/V3Descope.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Dfg.cpp b/src/V3Dfg.cpp index 9cda7d02a..cc1603724 100644 --- a/src/V3Dfg.cpp +++ b/src/V3Dfg.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -80,7 +80,7 @@ static void dumpDotVertex(std::ostream& os, const DfgVertex& vtx) { } else { os << ", shape=box"; } - os << "]" << endl; + os << "]\n"; return; } @@ -104,7 +104,7 @@ static void dumpDotVertex(std::ostream& os, const DfgVertex& vtx) { } else { os << ", shape=box3d"; } - os << "]" << endl; + os << "]\n"; return; } @@ -121,7 +121,7 @@ static void dumpDotVertex(std::ostream& os, const DfgVertex& vtx) { } os << '"'; os << ", shape=plain"; - os << "]" << endl; + os << "]\n"; return; } @@ -136,7 +136,7 @@ static void dumpDotVertex(std::ostream& os, const DfgVertex& vtx) { } else { os << ", shape=circle"; } - os << "]" << endl; + os << "]\n"; return; } @@ -147,14 +147,14 @@ static void dumpDotVertex(std::ostream& os, const DfgVertex& vtx) { } else { os << ", shape=circle"; } - os << "]" << endl; + os << "]\n"; } // Dump one DfgEdge in Graphviz format static void dumpDotEdge(std::ostream& os, const DfgEdge& edge, const string& headlabel) { os << toDotId(*edge.sourcep()) << " -> " << toDotId(*edge.sinkp()); if (!headlabel.empty()) os << " [headlabel=\"" << headlabel << "\"]"; - os << endl; + os << "\n"; } // Dump one DfgVertex and all of its source DfgEdges in Graphviz format @@ -171,17 +171,17 @@ static void dumpDotVertexAndSourceEdges(std::ostream& os, const DfgVertex& vtx) void DfgGraph::dumpDot(std::ostream& os, const string& label) const { // Header - os << "digraph dfg {" << endl; + os << "digraph dfg {\n"; os << "graph [label=\"" << name(); if (!label.empty()) os << "-" << label; - os << "\", labelloc=t, labeljust=l]" << endl; - os << "graph [rankdir=LR]" << endl; + os << "\", labelloc=t, labeljust=l]\n"; + os << "graph [rankdir=LR]\n"; // Emit all vertices forEachVertex([&](const DfgVertex& vtx) { dumpDotVertexAndSourceEdges(os, vtx); }); // Footer - os << "}" << endl; + os << "}\n"; } void DfgGraph::dumpDotFile(const string& fileName, const string& label) const { @@ -242,15 +242,15 @@ void DfgGraph::dumpDotUpstreamCone(const string& fileName, const DfgVertex& vtx, if (os->fail()) v3fatal("Cannot write to file: " << fileName); // Header - *os << "digraph dfg {" << endl; - if (!name.empty()) *os << "graph [label=\"" << name << "\", labelloc=t, labeljust=l]" << endl; - *os << "graph [rankdir=LR]" << endl; + *os << "digraph dfg {\n"; + if (!name.empty()) *os << "graph [label=\"" << name << "\", labelloc=t, labeljust=l]\n"; + *os << "graph [rankdir=LR]\n"; // Dump the cone dumpDotUpstreamConeFromVertex(*os, vtx); // Footer - *os << "}" << endl; + *os << "}\n"; // Done os->close(); @@ -276,15 +276,15 @@ void DfgGraph::dumpDotAllVarConesPrefixed(const string& label) const { if (os->fail()) v3fatal("Cannot write to file: " << fileName); // Header - *os << "digraph dfg {" << endl; - *os << "graph [label=\"" << coneName << "\", labelloc=t, labeljust=l]" << endl; - *os << "graph [rankdir=LR]" << endl; + *os << "digraph dfg {\n"; + *os << "graph [label=\"" << coneName << "\", labelloc=t, labeljust=l]\n"; + *os << "graph [rankdir=LR]\n"; // Dump this cone dumpDotUpstreamConeFromVertex(*os, vtx); // Footer - *os << "}" << endl; + *os << "}\n"; // Done with this logic cone os->close(); diff --git a/src/V3Dfg.h b/src/V3Dfg.h index 3be33cf06..4e1c23a22 100644 --- a/src/V3Dfg.h +++ b/src/V3Dfg.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -752,13 +752,13 @@ class DfgVertexWithArity VL_NOT_FINAL : public DfgVertex { std::array m_srcs; // Source edges protected: - DfgVertexWithArity(DfgGraph& dfg, VDfgType type, FileLine* flp, AstNodeDType* dtypep) + DfgVertexWithArity(DfgGraph& dfg, VDfgType type, FileLine* flp, AstNodeDType* dtypep) : DfgVertex{dfg, type, flp, dtypep} { // Initialize source edges for (size_t i = 0; i < Arity; ++i) m_srcs[i].init(this); } - ~DfgVertexWithArity() override = default; + ~DfgVertexWithArity() override = default; public: std::pair sourceEdges() final override { // diff --git a/src/V3DfgAstToDfg.cpp b/src/V3DfgAstToDfg.cpp index 3b23986ff..9310e9081 100644 --- a/src/V3DfgAstToDfg.cpp +++ b/src/V3DfgAstToDfg.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -14,7 +14,7 @@ // //************************************************************************* // -// Convert and AstModule to a DfgGraph. We proceed by visiting convertable logic blocks (e.g.: +// Convert and AstModule to a DfgGraph. We proceed by visiting convertible logic blocks (e.g.: // AstAssignW of appropriate type and with no delays), recursively constructing DfgVertex instances // for the expressions that compose the subject logic block. If all expressions in the current // logic block can be converted, then we delete the logic block (now represented in the DfgGraph), diff --git a/src/V3DfgDecomposition.cpp b/src/V3DfgDecomposition.cpp index 200d12610..d7a96abff 100644 --- a/src/V3DfgDecomposition.cpp +++ b/src/V3DfgDecomposition.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -292,11 +292,11 @@ class ExtractCyclicComponents final { // Visit all neighbors. We stop at variable boundaries, // which is where we will split the graphs - vtx.forEachSource([=](DfgVertex& other) { + vtx.forEachSource([this, targetComponent](DfgVertex& other) { if (other.is()) return; visitMergeSCCs(other, targetComponent); }); - vtx.forEachSink([=](DfgVertex& other) { + vtx.forEachSink([this, targetComponent](DfgVertex& other) { if (other.is()) return; visitMergeSCCs(other, targetComponent); }); diff --git a/src/V3DfgDfgToAst.cpp b/src/V3DfgDfgToAst.cpp index a5d0a14a9..4836ca0c6 100644 --- a/src/V3DfgDfgToAst.cpp +++ b/src/V3DfgDfgToAst.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3DfgOptimizer.cpp b/src/V3DfgOptimizer.cpp index ea49de41e..98a4fc5e0 100644 --- a/src/V3DfgOptimizer.cpp +++ b/src/V3DfgOptimizer.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -95,7 +95,7 @@ class DataflowExtractVisitor final : public VNVisitor { // VISIT methods void visit(AstNetlist* nodep) override { - // Analyse the whole design + // Analyze the whole design iterateChildrenConst(nodep); // Replace candidate expressions only reading combinationally driven signals with variables diff --git a/src/V3DfgOptimizer.h b/src/V3DfgOptimizer.h index 8ec1ede6c..0cb573c0b 100644 --- a/src/V3DfgOptimizer.h +++ b/src/V3DfgOptimizer.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3DfgPasses.cpp b/src/V3DfgPasses.cpp index f65b77897..7ee4433d1 100644 --- a/src/V3DfgPasses.cpp +++ b/src/V3DfgPasses.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3DfgPasses.h b/src/V3DfgPasses.h index 6b6689503..a67b1cca0 100644 --- a/src/V3DfgPasses.h +++ b/src/V3DfgPasses.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3DfgPeephole.cpp b/src/V3DfgPeephole.cpp index f162c9ec9..e6fed4218 100644 --- a/src/V3DfgPeephole.cpp +++ b/src/V3DfgPeephole.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -66,16 +66,16 @@ struct ReductionToBitwiseImpl {}; template <> struct ReductionToBitwiseImpl { using type = DfgAnd; }; template <> struct ReductionToBitwiseImpl { using type = DfgOr; }; template <> struct ReductionToBitwiseImpl { using type = DfgXor; }; -template -using ReductionToBitwise = typename ReductionToBitwiseImpl::type; +template +using ReductionToBitwise = typename ReductionToBitwiseImpl::type; template struct BitwiseToReductionImpl {}; template <> struct BitwiseToReductionImpl { using type = DfgRedAnd; }; template <> struct BitwiseToReductionImpl { using type = DfgRedOr; }; template <> struct BitwiseToReductionImpl { using type = DfgRedXor; }; -template -using BitwiseToReduction = typename BitwiseToReductionImpl::type; +template +using BitwiseToReduction = typename BitwiseToReductionImpl::type; namespace { template void foldOp(V3Number& out, const V3Number& src); diff --git a/src/V3DfgPeephole.h b/src/V3DfgPeephole.h index c2d83042e..92a228292 100644 --- a/src/V3DfgPeephole.h +++ b/src/V3DfgPeephole.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3DfgVertices.h b/src/V3DfgVertices.h index bbcd9bdca..cdcbb34a4 100644 --- a/src/V3DfgVertices.h +++ b/src/V3DfgVertices.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -224,7 +224,7 @@ public: uint32_t driverIndex(size_t idx) const { return m_driverData[idx].second; } DfgVertex* driverAt(size_t idx) const { - const DfgEdge* const edgep = findSourceEdge([=](const DfgEdge&, size_t i) { // + const DfgEdge* const edgep = findSourceEdge([this, idx](const DfgEdge&, size_t i) { // return driverIndex(i) == idx; }); return edgep ? edgep->sourcep() : nullptr; diff --git a/src/V3DupFinder.cpp b/src/V3DupFinder.cpp index c58859b0a..9d3eec9a0 100644 --- a/src/V3DupFinder.cpp +++ b/src/V3DupFinder.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3DupFinder.h b/src/V3DupFinder.h index 102ef6a43..14c74d714 100644 --- a/src/V3DupFinder.h +++ b/src/V3DupFinder.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitC.h b/src/V3EmitC.h index bbca3be0d..6c9d90086 100644 --- a/src/V3EmitC.h +++ b/src/V3EmitC.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCBase.cpp b/src/V3EmitCBase.cpp index be8871a8a..872af5e68 100644 --- a/src/V3EmitCBase.cpp +++ b/src/V3EmitCBase.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCBase.h b/src/V3EmitCBase.h index 7067f8ed6..595d007ac 100644 --- a/src/V3EmitCBase.h +++ b/src/V3EmitCBase.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -66,7 +66,7 @@ public: static string topClassName() VL_MT_SAFE { // Return name of top wrapper module return v3Global.opt.prefix(); } - static string prefixNameProtect(const AstNode* nodep) { // C++ name with prefix + static string prefixNameProtect(const AstNode* nodep) VL_MT_STABLE { // C++ name with prefix return v3Global.opt.modPrefix() + "_" + VIdProtect::protect(nodep->name()); } static bool isAnonOk(const AstVar* varp) { diff --git a/src/V3EmitCConstInit.h b/src/V3EmitCConstInit.h index 22f8082a1..aa490e55f 100644 --- a/src/V3EmitCConstInit.h +++ b/src/V3EmitCConstInit.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCConstPool.cpp b/src/V3EmitCConstPool.cpp index 656bffcd8..04c973fac 100644 --- a/src/V3EmitCConstPool.cpp +++ b/src/V3EmitCConstPool.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCFunc.cpp b/src/V3EmitCFunc.cpp index 461d6496e..e4458b478 100644 --- a/src/V3EmitCFunc.cpp +++ b/src/V3EmitCFunc.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 6c7ef5fb0..a264bbd26 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -116,7 +116,6 @@ public: // Emit statements and expressions class EmitCFunc VL_NOT_FINAL : public EmitCConstInit { -private: VMemberMap m_memberMap; AstVarRef* m_wideTempRefp = nullptr; // Variable that _WW macros should be setting int m_labelNum = 0; // Next label number @@ -1184,25 +1183,25 @@ public: } void visit(AstSel* nodep) override { // Note ASSIGN checks for this on a LHS - emitOpName(nodep, nodep->emitC(), nodep->fromp(), nodep->lsbp(), nodep->thsp()); + emitOpName(nodep, nodep->emitC(), nodep->fromp(), nodep->lsbp(), nodep->widthp()); } void visit(AstReplicate* nodep) override { - if (nodep->lhsp()->widthMin() == 1 && !nodep->isWide()) { - UASSERT_OBJ((static_cast(VN_AS(nodep->rhsp(), Const)->toUInt()) - * nodep->lhsp()->widthMin()) + if (nodep->srcp()->widthMin() == 1 && !nodep->isWide()) { + UASSERT_OBJ((static_cast(VN_AS(nodep->countp(), Const)->toUInt()) + * nodep->srcp()->widthMin()) == nodep->widthMin(), nodep, "Replicate non-constant or width miscomputed"); puts("VL_REPLICATE_"); emitIQW(nodep); puts("OI("); - if (nodep->lhsp()) puts(cvtToStr(nodep->lhsp()->widthMin())); + if (nodep->srcp()) puts(cvtToStr(nodep->srcp()->widthMin())); puts(","); - iterateAndNextConstNull(nodep->lhsp()); + iterateAndNextConstNull(nodep->srcp()); puts(", "); - iterateAndNextConstNull(nodep->rhsp()); + iterateAndNextConstNull(nodep->countp()); puts(")"); } else { - emitOpName(nodep, nodep->emitC(), nodep->lhsp(), nodep->rhsp(), nullptr); + emitOpName(nodep, nodep->emitC(), nodep->srcp(), nodep->countp(), nullptr); } } void visit(AstStreamL* nodep) override { @@ -1229,9 +1228,9 @@ public: } void visit(AstCastDynamic* nodep) override { putbs("VL_CAST_DYNAMIC("); - iterateAndNextConstNull(nodep->lhsp()); + iterateAndNextConstNull(nodep->fromp()); puts(", "); - iterateAndNextConstNull(nodep->rhsp()); + iterateAndNextConstNull(nodep->top()); puts(")"); } void visit(AstCountBits* nodep) override { diff --git a/src/V3EmitCHeaders.cpp b/src/V3EmitCHeaders.cpp index df00d1bef..4a9bfdb06 100644 --- a/src/V3EmitCHeaders.cpp +++ b/src/V3EmitCHeaders.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index 678cef81c..bf46f0f3c 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -577,6 +577,9 @@ class EmitCTrace final : EmitCFunc { V3UniqueNames m_uniqueNames; // For generating unique file names std::unordered_map m_enumNumMap; // EnumDType to enumeration number std::deque& m_cfilesr; // cfiles generated by this emit + V3OutCFile* m_typesFp = nullptr; // File for type declarations + int m_traceTypeSubs = 0; // Number of trace type declaration sub-functions + int m_typeSplitSize = 0; // # of cfunc nodes placed into output file // METHODS void openNextOutputFile() { @@ -610,6 +613,66 @@ class EmitCTrace final : EmitCFunc { puts("\n"); } + V3OutCFile* typesFp() const VL_MT_SAFE { return m_typesFp; } + + void openNextTypesFile() { + UASSERT(!m_typesFp, "Declarations output file already open"); + + string filename + = (v3Global.opt.makeDir() + "/" + topClassName() + "_" + protect("_TraceDecls")); + filename = m_uniqueNames.get(filename); + filename += "__Slow.cpp"; + + AstCFile* const cfilep = createCFile(filename, m_slow, true /*source*/); + cfilep->support(true); + m_cfilesr.push_back(cfilep); + + if (optSystemC()) { + m_typesFp = new V3OutScFile{filename}; + } else { + m_typesFp = new V3OutCFile{filename}; + } + typesFp()->putsHeader(); + typesFp()->puts("// DESCR" + "IPTION: Verilator output: Tracing declarations\n"); + + // Includes + typesFp()->puts("#include \"" + v3Global.opt.traceSourceLang() + ".h\"\n"); + typesFp()->puts("\n"); + + typesFp()->puts("\nvoid " + prefixNameProtect(m_modp) + "__" + + protect("traceDeclTypesSub" + cvtToStr(m_traceTypeSubs++)) + "(" + + v3Global.opt.traceClassBase() + "* tracep) {\n"); + } + + void closeTypesFile() { + typesFp()->puts("}\n"); + VL_DO_CLEAR(delete m_typesFp, m_typesFp = nullptr); + } + + void callTypeSubs() { + typesFp()->puts("}\n"); + + // Forward declarations for subs in other files + for (int i = 0; i < m_traceTypeSubs - 1; ++i) { + typesFp()->puts("void " + prefixNameProtect(m_modp) + "__" + + protect("traceDeclTypesSub" + cvtToStr(i)) + "(" + + v3Global.opt.traceClassBase() + "* tracep);\n"); + } + + typesFp()->puts("\nvoid " + prefixNameProtect(m_modp) + "__" + protect("trace_decl_types") + + "(" + v3Global.opt.traceClassBase() + "* tracep) {\n"); + for (int i = 0; i < m_traceTypeSubs; ++i) { + typesFp()->puts(prefixNameProtect(m_modp) + "__" + + protect("traceDeclTypesSub" + cvtToStr(i)) + "(tracep);\n"); + } + } + + bool typesSplitNeeded() { + return v3Global.opt.outputSplitCTrace() + && m_typeSplitSize >= v3Global.opt.outputSplitCTrace(); + } + bool emitTraceIsScBv(AstTraceInc* nodep) { const AstVarRef* const varrefp = VN_CAST(nodep->declp()->valuep(), VarRef); if (!varrefp) return false; @@ -697,50 +760,60 @@ class EmitCTrace final : EmitCFunc { puts(");"); } + int getEnumMapNum(AstEnumDType* nodep) { + int enumNum = m_enumNumMap[nodep]; + if (!enumNum) { + if (typesSplitNeeded()) { + // Splitting file, so using parallel build. + v3Global.useParallelBuild(true); + closeTypesFile(); + openNextTypesFile(); + } + enumNum = ++m_enumNum; + m_enumNumMap[nodep] = enumNum; + int nvals = 0; + typesFp()->puts("{\n"); + typesFp()->puts("const char* " + protect("__VenumItemNames") + "[]\n"); + typesFp()->puts("= {"); + for (AstEnumItem* itemp = nodep->itemsp(); itemp; + itemp = VN_AS(itemp->nextp(), EnumItem)) { + if (++nvals > 1) typesFp()->puts(", "); + typesFp()->putbs("\"" + itemp->prettyName() + "\""); + } + typesFp()->puts("};\n"); + nvals = 0; + typesFp()->puts("const char* " + protect("__VenumItemValues") + "[]\n"); + typesFp()->puts("= {"); + for (AstEnumItem* itemp = nodep->itemsp(); itemp; + itemp = VN_AS(itemp->nextp(), EnumItem)) { + AstConst* const constp = VN_AS(itemp->valuep(), Const); + if (++nvals > 1) typesFp()->puts(", "); + typesFp()->putbs("\"" + constp->num().displayed(nodep, "%0b") + "\""); + } + typesFp()->puts("};\n"); + typesFp()->puts("tracep->declDTypeEnum(" + cvtToStr(enumNum) + ", \"" + + nodep->prettyName() + "\", " + cvtToStr(nvals) + ", " + + cvtToStr(nodep->widthMin()) + ", " + protect("__VenumItemNames") + + ", " + protect("__VenumItemValues") + ");\n"); + typesFp()->puts("}\n"); + m_typeSplitSize += 3; + } + return enumNum; + } + int emitTraceDeclDType(AstNodeDType* nodep) { // Return enum number or -1 for none if (v3Global.opt.traceFormat().fst()) { // Skip over refs-to-refs, but stop before final ref so can get data type name // Alternatively back in V3Width we could push enum names from upper typedefs if (AstEnumDType* const enump = VN_CAST(nodep->skipRefToEnump(), EnumDType)) { - int enumNum = m_enumNumMap[enump]; - if (!enumNum) { - enumNum = ++m_enumNum; - m_enumNumMap[enump] = enumNum; - int nvals = 0; - puts("{\n"); - puts("const char* " + protect("__VenumItemNames") + "[]\n"); - puts("= {"); - for (AstEnumItem* itemp = enump->itemsp(); itemp; - itemp = VN_AS(itemp->nextp(), EnumItem)) { - if (++nvals > 1) puts(", "); - putbs("\"" + itemp->prettyName() + "\""); - } - puts("};\n"); - nvals = 0; - puts("const char* " + protect("__VenumItemValues") + "[]\n"); - puts("= {"); - for (AstEnumItem* itemp = enump->itemsp(); itemp; - itemp = VN_AS(itemp->nextp(), EnumItem)) { - AstConst* const constp = VN_AS(itemp->valuep(), Const); - if (++nvals > 1) puts(", "); - putbs("\"" + constp->num().displayed(nodep, "%0b") + "\""); - } - puts("};\n"); - puts("tracep->declDTypeEnum(" + cvtToStr(enumNum) + ", \"" - + enump->prettyName() + "\", " + cvtToStr(nvals) + ", " - + cvtToStr(enump->widthMin()) + ", " + protect("__VenumItemNames") + ", " - + protect("__VenumItemValues") + ");\n"); - puts("}\n"); - } - return enumNum; + return getEnumMapNum(enump); } } return -1; } void emitTraceChangeOne(AstTraceInc* nodep, int arrayindex) { - iterateAndNextConstNull(nodep->precondsp()); // Note: Both VTraceType::CHANGE and VTraceType::FULL use the 'full' methods const std::string func = nodep->traceType() == VTraceType::CHANGE ? "chg" : "full"; bool emitWidth = true; @@ -870,12 +943,17 @@ class EmitCTrace final : EmitCFunc { m_modp = modp; // Open output file openNextOutputFile(); + if (m_slow) openNextTypesFile(); // Emit functions for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) { if (AstCFunc* const funcp = VN_CAST(nodep, CFunc)) { iterateConst(funcp); } } // Close output file VL_DO_CLEAR(delete m_ofp, m_ofp = nullptr); + if (m_slow) { + callTypeSubs(); + closeTypesFile(); + } } ~EmitCTrace() override = default; diff --git a/src/V3EmitCInlines.cpp b/src/V3EmitCInlines.cpp index 6425a367c..30d9f4e49 100644 --- a/src/V3EmitCInlines.cpp +++ b/src/V3EmitCInlines.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCMain.cpp b/src/V3EmitCMain.cpp index 4a9f9c496..d267cba86 100644 --- a/src/V3EmitCMain.cpp +++ b/src/V3EmitCMain.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCMain.h b/src/V3EmitCMain.h index 65877429b..f0a8e2191 100644 --- a/src/V3EmitCMain.h +++ b/src/V3EmitCMain.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp index 1cf10b01c..b833ba45f 100644 --- a/src/V3EmitCMake.cpp +++ b/src/V3EmitCMake.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCMake.h b/src/V3EmitCMake.h index ac611386c..a6ad712f5 100644 --- a/src/V3EmitCMake.h +++ b/src/V3EmitCMake.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCModel.cpp b/src/V3EmitCModel.cpp index 326aa21a9..1ecbab127 100644 --- a/src/V3EmitCModel.cpp +++ b/src/V3EmitCModel.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -498,6 +498,8 @@ class EmitCModel final : public EmitCFunc { putSectionDelimiter("Trace configuration"); // Forward declaration + puts("\nvoid " + topModNameProtected + "__" + protect("trace_decl_types") + "(" + + v3Global.opt.traceClassBase() + "* tracep);\n"); puts("\nvoid " + topModNameProtected + "__" + protect("trace_init_top") + "(" + topModNameProtected + "* vlSelf, " + v3Global.opt.traceClassBase() + "* tracep);\n"); @@ -516,6 +518,7 @@ class EmitCModel final : public EmitCFunc { puts("vlSymsp->__Vm_baseCode = code;\n"); puts("tracep->pushPrefix(std::string{vlSymsp->name()}, " "VerilatedTracePrefixType::SCOPE_MODULE);\n"); + puts(topModNameProtected + "__" + protect("trace_decl_types") + "(tracep);\n"); puts(topModNameProtected + "__" + protect("trace_init_top") + "(vlSelf, tracep);\n"); puts("tracep->popPrefix();\n"); puts("}\n"); diff --git a/src/V3EmitCPch.cpp b/src/V3EmitCPch.cpp index 1cd6ed965..0bcbcb8f7 100644 --- a/src/V3EmitCPch.cpp +++ b/src/V3EmitCPch.cpp @@ -2,7 +2,7 @@ //************************************************************************* // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index bf020e06c..8ddd82a6e 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -152,25 +152,23 @@ class EmitCSyms final : EmitCBaseVisitorConst { static string scopeDecodeIdentifier(const string& scpname) { string out = scpname; - // Remove hierarchy - string::size_type pos = out.rfind('.'); + string::size_type pos = string::npos; - // If there's more than one ident and an escape, find the true last ident - if (pos != string::npos && scpname.find('\\') != string::npos) { - size_t i = 0; - // always makes progress - while (i < scpname.length()) { - if (scpname[i] == '\\') { - while (i < scpname.length() && scpname[i] != ' ') ++i; - ++i; // Proc ' ', it should always be there. Then grab '.' on next cycle - } else { - while (i < scpname.length() && scpname[i] != '.') ++i; - if (i < scpname.length()) { pos = i++; } - } + // Remove hierarchy + size_t i = 0; + // always makes progress + while (i < scpname.length()) { + if (scpname[i] == '\\') { + while (i < scpname.length() && scpname[i] != ' ') ++i; + ++i; // Proc ' ', it should always be there. Then grab '.' on next cycle + } else { + while (i < scpname.length() && scpname[i] != '.') ++i; + if (i < scpname.length()) pos = i++; } } if (pos != std::string::npos) out.erase(0, pos + 1); + // Decode all escaped characters while ((pos = out.find("__0")) != string::npos) { unsigned int x; @@ -230,7 +228,7 @@ class EmitCSyms final : EmitCBaseVisitorConst { } // UINFO(9, "For " << scopep->name() << " - " << varp->name() << " Scp " // << scpName << "Var " << varBase << endl); - const string varBasePretty = AstNode::prettyName(VName::dehash(varBase)); + const string varBasePretty = AstNode::vpiName(VName::dehash(varBase)); const string scpPretty = AstNode::prettyName(VName::dehash(scpName)); const string scpSym = scopeSymString(VName::dehash(scpName)); // UINFO(9, " scnameins sp " << scpName << " sp " << scpPretty << " ss " @@ -320,7 +318,7 @@ class EmitCSyms final : EmitCBaseVisitorConst { m_scopes.emplace_back(nodep, m_modp); if (v3Global.opt.vpi() && !nodep->isTop()) { - const string type = VN_IS(nodep->modp(), Package) ? "SCOPE_OTHER" : "SCOPE_MODULE"; + const string type = VN_IS(nodep->modp(), Package) ? "SCOPE_PACKAGE" : "SCOPE_MODULE"; const string name_pretty = AstNode::vpiName(nodep->shortName()); const int timeunit = m_modp->timeunit().powerOfTen(); m_vpiScopeCandidates.emplace( @@ -646,7 +644,9 @@ void EmitCSyms::emitScopeHier(bool destroy) { ++it) { const string name = it->second.m_prettyName; if (it->first == "TOP") continue; - if ((name.find('.') == string::npos) && (it->second.m_type == "SCOPE_MODULE")) { + const string scopeType = it->second.m_type; + if ((name.find('.') == string::npos) + && (scopeType == "SCOPE_MODULE" || scopeType == "SCOPE_PACKAGE")) { puts("__Vhier." + method + "(0, &" + protect("__Vscope_" + it->second.m_symName) + ");\n"); } diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index 8bea8b362..6d00e3997 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -146,7 +146,7 @@ public: } else if (!v3Global.opt.libCreate().empty()) { of.puts("default: lib" + v3Global.opt.libCreate() + "\n"); } else { - of.puts("default: " + v3Global.opt.prefix() + "__ALL.a\n"); + of.puts("default: lib" + v3Global.opt.prefix() + "\n"); } of.puts("\n### Constants...\n"); of.puts("# Perl executable (from $PERL)\n"); @@ -239,13 +239,12 @@ public: if (v3Global.opt.exe()) { of.puts("\n### Link rules... (from --exe)\n"); + // let default rule depend on '{prefix}__ALL.a', for compatibility of.puts(v3Global.opt.exeName() + ": $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS)\n"); of.puts("\t$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@\n"); of.puts("\n"); - } - - if (!v3Global.opt.libCreate().empty()) { + } else if (!v3Global.opt.libCreate().empty()) { const string libCreateDeps = "$(VK_OBJS) $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) " + v3Global.opt.libCreate() + ".o $(VM_HIER_LIBS)"; of.puts("\n### Library rules from --lib-create\n"); @@ -272,6 +271,15 @@ public: of.puts("lib" + v3Global.opt.libCreate() + ": " + v3Global.opt.libCreateName(false) + " " + v3Global.opt.libCreateName(true) + "\n"); } + } else { + const string libname = "lib" + v3Global.opt.prefix() + ".a"; + of.puts("\n### Library rules (default lib mode)\n"); + // The rule to create .a is defined in verilated.mk, so just define dependency here. + of.puts(libname + ": $(VK_OBJS) $(VK_USER_OBJS) $(VM_HIER_LIBS)\n"); + of.puts("libverilated.a: $(VK_GLOBAL_OBJS)\n"); + // let default rule depend on '{prefix}__ALL.a', for compatibility + of.puts("lib" + v3Global.opt.prefix() + ": " + libname + + " libverilated.a $(VM_PREFIX)__ALL.a\n"); } of.puts("\n"); diff --git a/src/V3EmitMk.h b/src/V3EmitMk.h index 2c043890b..61118a92a 100644 --- a/src/V3EmitMk.h +++ b/src/V3EmitMk.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index d8fc2b42e..d3486d0c1 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -807,86 +807,6 @@ public: ~EmitVStreamVisitor() override = default; }; -//###################################################################### -// Emit to a stream (perhaps stringstream) - -class EmitVPrefixedFormatter final : public V3OutFormatter { - std::ostream& m_os; - const string m_prefix; // What to print at beginning of each line - const int m_flWidth; // Padding of fileline - int m_column = 0; // Rough location; need just zero or non-zero - FileLine* m_prefixFl; - // METHODS - void putcOutput(char chr) override { - if (chr == '\n') { - m_column = 0; - m_os << chr; - } else { - if (m_column == 0) { - m_column = 10; - m_os << m_prefixFl->ascii() + ":"; - m_os << V3OutFile::indentSpaces(m_flWidth - (m_prefixFl->ascii().length() + 1)); - m_os << " "; - m_os << m_prefix; - } - ++m_column; - m_os << chr; - } - } - - void putsOutput(const char* strg) override { - for (const char* cp = strg; *cp; cp++) putcOutput(*cp); - } - -public: - void prefixFl(FileLine* fl) { m_prefixFl = fl; } - FileLine* prefixFl() const { return m_prefixFl; } - int column() const { return m_column; } - EmitVPrefixedFormatter(std::ostream& os, const string& prefix, int flWidth) - : V3OutFormatter{"__STREAM", V3OutFormatter::LA_VERILOG} - , m_os(os) // Need () or GCC 4.8 false warning - , m_prefix{prefix} - , m_flWidth{flWidth} { - m_prefixFl = v3Global.rootp()->fileline(); // NETLIST's fileline instead of nullptr to - // avoid nullptr checks - } - ~EmitVPrefixedFormatter() override { - if (m_column) puts("\n"); - } -}; - -class EmitVPrefixedVisitor final : public EmitVBaseVisitorConst { - // MEMBERS - EmitVPrefixedFormatter m_formatter; // Special verilog formatter (Way down the - // inheritance is another unused V3OutFormatter) - // METHODS - void putsNoTracking(const string& str) override { m_formatter.putsNoTracking(str); } - void puts(const string& str) override { m_formatter.puts(str); } - // We don't use m_formatter's putbs because the tokens will change filelines - // and insert returns at the proper locations - void putbs(const string& str) override { m_formatter.puts(str); } - void putfs(AstNode* nodep, const string& str) override { putfsqs(nodep, str, false); } - void putqs(AstNode* nodep, const string& str) override { putfsqs(nodep, str, true); } - void putfsqs(AstNode* nodep, const string& str, bool quiet) { - if (m_formatter.prefixFl() != nodep->fileline()) { - m_formatter.prefixFl(nodep->fileline()); - if (m_formatter.column()) puts("\n"); // This in turn will print the m_prefixFl - } - if (!quiet && nodep->user3()) puts("%%"); - putbs(str); - } - -public: - EmitVPrefixedVisitor(const AstNode* nodep, std::ostream& os, const string& prefix, int flWidth, - AstSenTree* domainp, bool user3mark) - : EmitVBaseVisitorConst{false, domainp} - , m_formatter{os, prefix, flWidth} { - if (user3mark) VNUser3InUse::check(); - iterateConst(const_cast(nodep)); - } - ~EmitVPrefixedVisitor() override = default; -}; - //###################################################################### // EmitV class functions @@ -894,11 +814,6 @@ void V3EmitV::verilogForTree(const AstNode* nodep, std::ostream& os) { { EmitVStreamVisitor{nodep, os}; } } -void V3EmitV::verilogPrefixedTree(const AstNode* nodep, std::ostream& os, const string& prefix, - int flWidth, AstSenTree* domainp, bool user3mark) { - { EmitVPrefixedVisitor{nodep, os, prefix, flWidth, domainp, user3mark}; } -} - void V3EmitV::emitvFiles() { UINFO(2, __FUNCTION__ << ": " << endl); for (AstNodeFile* filep = v3Global.rootp()->filesp(); filep; diff --git a/src/V3EmitV.h b/src/V3EmitV.h index 80be5453a..c1839080f 100644 --- a/src/V3EmitV.h +++ b/src/V3EmitV.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,8 +30,6 @@ class AstSenTree; class V3EmitV final { public: static void verilogForTree(const AstNode* nodep, std::ostream& os = std::cout); - static void verilogPrefixedTree(const AstNode* nodep, std::ostream& os, const string& prefix, - int flWidth, AstSenTree* domainp, bool user3mark); static void emitvFiles(); static void debugEmitV(const string& filename); }; diff --git a/src/V3EmitXml.cpp b/src/V3EmitXml.cpp index d2cb7d621..26aa92e99 100644 --- a/src/V3EmitXml.cpp +++ b/src/V3EmitXml.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -320,7 +320,6 @@ public: // List of module files xml visitor class ModuleFilesXmlVisitor final : public VNVisitorConst { -private: // MEMBERS std::ostream& m_os; std::set m_modulesCovered; @@ -367,7 +366,6 @@ public: // Hierarchy of Cells visitor class HierCellsXmlVisitor final : public VNVisitorConst { -private: // MEMBERS std::ostream& m_os; std::string m_hier; diff --git a/src/V3EmitXml.h b/src/V3EmitXml.h index 420795b0d..5d005b83a 100644 --- a/src/V3EmitXml.h +++ b/src/V3EmitXml.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Error.cpp b/src/V3Error.cpp index 1194cd7e3..908e597f3 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Error.h b/src/V3Error.h index acebf7e6b..51de65960 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -405,7 +405,6 @@ public: // ###################################################################### class V3Error final { // Base class for any object that wants debugging and error reporting -private: // CONSTRUCTORS V3Error() { std::cerr << ("Static class"); diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp index af67ad82e..db2b53208 100644 --- a/src/V3Expand.cpp +++ b/src/V3Expand.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -37,8 +37,7 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### // Find nodes with side effects, to mark as non-expandable -class ExpandOkVisitor final : public VNVisitor { -private: +class ExpandOkVisitor final : public VNVisitorConst { // NODE STATE // AstNode::user2() -> bool. Is pure (along with all children) const VNUser2InUse m_inuser2; @@ -53,7 +52,7 @@ private: { VL_RESTORER(m_isImpure); m_isImpure = false; - iterateChildren(nodep); + iterateChildrenConst(nodep); selfImpure |= m_isImpure; nodep->user2(selfImpure); } @@ -62,7 +61,7 @@ private: public: // CONSTRUCTORS - explicit ExpandOkVisitor(AstNetlist* nodep) { iterate(nodep); } + explicit ExpandOkVisitor(AstNetlist* nodep) { iterateConst(nodep); } ~ExpandOkVisitor() = default; }; @@ -70,7 +69,6 @@ public: // Expand state, as a visitor of each AstNode class ExpandVisitor final : public VNVisitor { -private: // NODE STATE // AstNode::user1() -> bool. Processed const VNUser1InUse m_inuser1; @@ -731,7 +729,7 @@ private: } else { if (isImpure(nodep)) return; FileLine* const fl = nodep->fileline(); - AstNodeExpr* lhsp = nodep->lhsp()->unlinkFrBack(); + AstNodeExpr* lhsp = nodep->srcp()->unlinkFrBack(); AstNodeExpr* newp; const int lhswidth = lhsp->widthMin(); if (lhswidth == 1) { @@ -739,7 +737,7 @@ private: newp = new AstNegate{fl, lhsp}; } else { UINFO(8, " REPLICATE " << nodep << endl); - const AstConst* const constp = VN_AS(nodep->rhsp(), Const); + const AstConst* const constp = VN_AS(nodep->countp(), Const); UASSERT_OBJ(constp, nodep, "Replication value isn't a constant. Checked earlier!"); const uint32_t times = constp->toUInt(); @@ -765,9 +763,9 @@ private: UINFO(8, " Wordize ASSIGN(REPLICATE) " << nodep << endl); if (!doExpandWide(rhsp)) return false; FileLine* const fl = nodep->fileline(); - AstNodeExpr* const lhsp = rhsp->lhsp(); + AstNodeExpr* const lhsp = rhsp->srcp(); const int lhswidth = lhsp->widthMin(); - const AstConst* const constp = VN_AS(rhsp->rhsp(), Const); + const AstConst* const constp = VN_AS(rhsp->countp(), Const); UASSERT_OBJ(constp, rhsp, "Replication value isn't a constant. Checked earlier!"); const uint32_t times = constp->toUInt(); for (int w = 0; w < rhsp->widthWords(); ++w) { diff --git a/src/V3Expand.h b/src/V3Expand.h index e3f8fc630..249a1dfd3 100644 --- a/src/V3Expand.h +++ b/src/V3Expand.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3File.cpp b/src/V3File.cpp index a51372f8f..7e490769d 100644 --- a/src/V3File.cpp +++ b/src/V3File.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -191,7 +191,7 @@ void V3FileDependImp::writeTimes(const string& filename, const string& cmdlineIn // Read stats of files we create after we're done making them // (except for this file, of course) DependFile* const dfp = const_cast(&(*iter)); - V3Options::fileNfsFlush(dfp->filename()); + V3Os::filesystemFlush(dfp->filename()); dfp->loadStats(); off_t showSize = iter->size(); ino_t showIno = iter->ino(); @@ -256,7 +256,7 @@ bool V3FileDependImp::checkTimes(const string& filename, const string& cmdlineIn *ifp >> quote; const string chkFilename = V3Os::getline(*ifp, '"'); - V3Options::fileNfsFlush(chkFilename); + V3Os::filesystemFlush(chkFilename); // NOLINTNEXTLINE(cppcoreguidelines-pro-type-member-init) struct stat chkStat; const int err = stat(chkFilename.c_str(), &chkStat); diff --git a/src/V3File.h b/src/V3File.h index 00b9ef1aa..7cdfb0f35 100644 --- a/src/V3File.h +++ b/src/V3File.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp index 56f5090a1..0520b2e94 100644 --- a/src/V3FileLine.cpp +++ b/src/V3FileLine.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -399,7 +399,7 @@ void FileLine::v3errorEnd(std::ostringstream& sstr, const string& extra) std::ostringstream nsstr; if (lastLineno()) nsstr << this; nsstr << sstr.str(); - nsstr << endl; + nsstr << "\n"; std::ostringstream lstr; if (!extra.empty()) { lstr << std::setw(ascii().length()) << " " diff --git a/src/V3FileLine.h b/src/V3FileLine.h index cdc6ab748..f44215815 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Force.cpp b/src/V3Force.cpp index 93a3d4a08..a7217f811 100644 --- a/src/V3Force.cpp +++ b/src/V3Force.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -283,8 +283,8 @@ class ForceConvertVisitor final : public VNVisitor { // If this signal is marked externally forceable, create the public force signals if (nodep->varp()->isForceable()) { const ForceComponentsVarScope& fc = getForceComponents(nodep); - fc.m_enVscp->varp()->sigPublic(true); - fc.m_valVscp->varp()->sigPublic(true); + fc.m_enVscp->varp()->sigUserRWPublic(true); + fc.m_valVscp->varp()->sigUserRWPublic(true); } } diff --git a/src/V3Force.h b/src/V3Force.h index 647d6c813..89d678cb9 100644 --- a/src/V3Force.h +++ b/src/V3Force.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Fork.cpp b/src/V3Fork.cpp index a271874ae..2d024ea59 100644 --- a/src/V3Fork.cpp +++ b/src/V3Fork.cpp @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -25,7 +25,7 @@ // tasks to carry their own frames and as such they require their own // variable scopes. // There are two mechanisms that work together to achieve that. ForkVisitor -// moves bodies of forked prcesses into new tasks, which results in them getting their +// moves bodies of forked processes into new tasks, which results in them getting their // own scopes. The original statements get replaced with a call to the task which // passes the required variables by value. // The second mechanism, DynScopeVisitor, is designed to handle variables which can't be @@ -61,7 +61,6 @@ public: }; class ForkDynScopeFrame final { -private: // MEMBERS AstNodeModule* const m_modp; // Module to insert the scope into AstNode* const m_procp; // Procedure/block associated with that dynscope @@ -249,15 +248,15 @@ private: //###################################################################### // Dynamic scope visitor, creates classes and objects for dynamic scoping of variables and -// replaces references to varibles that need a dynamic scope with references to object's +// replaces references to variables that need a dynamic scope with references to object's // members class DynScopeVisitor final : public VNVisitor { -private: // NODE STATE // AstVar::user1() -> int, timing-control fork nesting level of that variable // AstVarRef::user2() -> bool, 1 = Node is a class handle reference. The handle gets // modified in the context of this reference. + // AstAssignDly::user2() -> bool, true if already visited const VNUser1InUse m_inuser1; const VNUser2InUse m_inuser2; @@ -270,8 +269,8 @@ private: int m_forkDepth = 0; // Number of asynchronous forks we are currently under bool m_afterTimingControl = false; // A timing control might've be executed in the current // process - size_t m_id; // Unique ID for a frame - size_t m_class_id; // Unique ID for a frame class + size_t m_id = 0; // Unique ID for a frame + size_t m_class_id = 0; // Unique ID for a frame class // METHODS @@ -313,11 +312,8 @@ private: } static bool hasAsyncFork(AstNode* nodep) { - bool afork = false; - nodep->foreach([&](AstFork* forkp) { - if (!forkp->joinType().join()) afork = true; - }); - return afork; + return nodep->exists([](AstFork* forkp) { return !forkp->joinType().join(); }) + || nodep->exists([](AstAssignDly*) { return true; }); } void bindNodeToDynScope(AstNode* nodep, ForkDynScopeFrame* frame) { @@ -388,7 +384,7 @@ private: } void visit(AstNodeFTaskRef* nodep) override { visit(static_cast(nodep)); - // We are before V3Timing, so unfortnately we need to treat any calls as suspending, + // We are before V3Timing, so unfortunately we need to treat any calls as suspending, // just to be safe. This might be improved if we could propagate suspendability // before doing all the other timing-related stuff. m_afterTimingControl = true; @@ -415,6 +411,22 @@ private: } visit(static_cast(nodep)); } + void visit(AstAssignDly* nodep) override { + if (m_procp && !nodep->user2() // Unhandled AssignDly in function/task + && nodep->lhsp()->exists( // And writes to a local variable + [](AstVarRef* refp) { + return refp->access().isWriteOrRW() && refp->varp()->isFuncLocal(); + })) { + nodep->user2(true); + // Put it in a fork to prevent lifetime issues with the local + AstFork* const forkp = new AstFork{nodep->fileline(), "", nullptr}; + forkp->joinType(VJoinType::JOIN_NONE); + nodep->replaceWith(forkp); + forkp->addStmtsp(nodep); + } else { + iterateChildren(nodep); + } + } void visit(AstNode* nodep) override { if (nodep->isTimingControl()) m_afterTimingControl = true; iterateChildren(nodep); @@ -445,14 +457,17 @@ public: if (typesAdded) v3Global.rootp()->typeTablep()->repairCache(); } - ~DynScopeVisitor() override = default; + ~DynScopeVisitor() override { + std::set frames; + for (auto node_frame : m_frames) { frames.insert(node_frame.second); } + for (auto* frame : frames) { delete frame; } + } }; //###################################################################### // Fork visitor, transforms asynchronous blocks into separate tasks class ForkVisitor final : public VNVisitor { -private: // NODE STATE // AstNode::user1() -> bool, 1 = Node was created as a call to an asynchronous task // AstVarRef::user2() -> bool, 1 = Node is a class handle reference. The handle gets diff --git a/src/V3Fork.h b/src/V3Fork.h index 53bd6c19d..02f234989 100644 --- a/src/V3Fork.h +++ b/src/V3Fork.h @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,7 +30,7 @@ class AstNetlist; class V3Fork final { public: // Move/copy variables to "anonymous" objects if their lifetime might exceed the scope of a - // procedure that declared them. Update the references apropriately. + // procedure that declared them. Update the references appropriately. static void makeDynamicScopes(AstNetlist* nodep) VL_MT_DISABLED; // Create tasks out of blocks/statments that can outlive processes in which they were forked. // Return value: number of tasks created diff --git a/src/V3FunctionTraits.h b/src/V3FunctionTraits.h index 3fa0a7305..c9d39670f 100644 --- a/src/V3FunctionTraits.h +++ b/src/V3FunctionTraits.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp index 6560dc054..61ba85be7 100644 --- a/src/V3Gate.cpp +++ b/src/V3Gate.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -37,85 +37,44 @@ VL_DEFINE_DEBUG_FUNCTIONS; -class GateDedupeVarVisitor; - -using GateVarRefList = std::list; - -constexpr int GATE_DEDUP_MAX_DEPTH = 20; +constexpr uint32_t GATE_DEDUP_MAX_DEPTH = 20; //###################################################################### - -class GateLogicVertex; -class GateVarVertex; -class GateGraphBaseVisitor VL_NOT_FINAL { -public: - V3Graph* const m_graphp; // Graph this class is visiting - explicit GateGraphBaseVisitor(V3Graph* graphp) - : m_graphp{graphp} {} - virtual ~GateGraphBaseVisitor() = default; - virtual VNUser visit(GateLogicVertex* vertexp, VNUser vu = VNUser{0}) = 0; - virtual VNUser visit(GateVarVertex* vertexp, VNUser vu = VNUser{0}) = 0; -}; - -//###################################################################### -// Support classes +// Gate graph classes class GateEitherVertex VL_NOT_FINAL : public V3GraphVertex { VL_RTTI_IMPL(GateEitherVertex, V3GraphVertex) - AstScope* const m_scopep; // Scope vertex refers to bool m_reducible = true; // True if this node should be able to be eliminated bool m_dedupable = true; // True if this node should be able to be deduped bool m_consumed = false; // Output goes to something meaningful public: - GateEitherVertex(V3Graph* graphp, AstScope* scopep) - : V3GraphVertex{graphp} - , m_scopep{scopep} {} + GateEitherVertex(V3Graph* graphp) + : V3GraphVertex{graphp} {} ~GateEitherVertex() override = default; + // ACCESSORS - string dotStyle() const override { return m_consumed ? "" : "dotted"; } - AstScope* scopep() const VL_MT_STABLE { return m_scopep; } bool reducible() const { return m_reducible; } bool dedupable() const { return m_dedupable; } - void setConsumed(const char* /*consumedReason*/) { - m_consumed = true; - // UINFO(0, "\t\tSetConsumed "<inNextp()) { - ret = static_cast(edgep->fromp())->accept(v, vu); - } - return ret; - } - // Returns only the result from the LAST vertex iterated over - // Note: This behaves differently than iterateInEdges() in that it will traverse - // all edges that exist when it is initially called, whereas - // iterateInEdges() will stop traversing edges if one is deleted - VNUser iterateCurrentOutEdges(GateGraphBaseVisitor& v, VNUser vu = VNUser{0}) { - VNUser ret{0}; - V3GraphEdge* next_edgep = nullptr; - for (V3GraphEdge* edgep = outBeginp(); edgep; edgep = next_edgep) { - // Need to find the next edge before visiting in case the edge is deleted - next_edgep = edgep->outNextp(); - ret = static_cast(edgep->top())->accept(v, vu); - } - return ret; - } + + // DOT debug + std::string dotStyle() const override { return m_consumed ? "" : "dotted"; } }; class GateVarVertex final : public GateEitherVertex { @@ -126,16 +85,13 @@ class GateVarVertex final : public GateEitherVertex { AstNode* m_rstSyncNodep = nullptr; // Used as reset and not in SenItem, in clocked always AstNode* m_rstAsyncNodep = nullptr; // Used as reset and in SenItem, in clocked always public: - GateVarVertex(V3Graph* graphp, AstScope* scopep, AstVarScope* varScp) - : GateEitherVertex{graphp, scopep} + GateVarVertex(V3Graph* graphp, AstVarScope* varScp) + : GateEitherVertex{graphp} , m_varScp{varScp} {} ~GateVarVertex() override = default; + // ACCESSORS AstVarScope* varScp() const VL_MT_STABLE { return m_varScp; } - string name() const override VL_MT_STABLE { - return (cvtToHex(m_varScp) + " " + varScp()->name()); - } - string dotColor() const override { return "blue"; } bool isTop() const { return m_isTop; } void setIsTop() { m_isTop = true; } bool isClock() const { return m_isClock; } @@ -147,6 +103,7 @@ public: void rstSyncNodep(AstNode* nodep) { m_rstSyncNodep = nodep; } AstNode* rstAsyncNodep() const { return m_rstAsyncNodep; } void rstAsyncNodep(AstNode* nodep) { m_rstAsyncNodep = nodep; } + // METHODS void propagateAttrClocksFrom(GateVarVertex* fromp) { // Propagate clock and general attribute onto this node @@ -156,9 +113,10 @@ public: setIsClock(); } } - VNUser accept(GateGraphBaseVisitor& v, VNUser vu = VNUser{0}) override { - return v.visit(this, vu); - } + + // DOT debug + std::string name() const override VL_MT_STABLE { return varScp()->name(); } + std::string dotColor() const override { return "green"; } }; class GateLogicVertex final : public GateEitherVertex { @@ -167,577 +125,217 @@ class GateLogicVertex final : public GateEitherVertex { AstActive* const m_activep; // Under what active; nullptr is ok (under cfunc or such) const bool m_slow; // In slow block public: - GateLogicVertex(V3Graph* graphp, AstScope* scopep, AstNode* nodep, AstActive* activep, - bool slow) - : GateEitherVertex{graphp, scopep} + GateLogicVertex(V3Graph* graphp, AstNode* nodep, AstActive* activep, bool slow) + : GateEitherVertex{graphp} , m_nodep{nodep} , m_activep{activep} , m_slow{slow} {} ~GateLogicVertex() override = default; + // ACCESSORS - string name() const override { return (cvtToHex(m_nodep) + "@" + scopep()->prettyName()); } - string dotColor() const override { return "purple"; } FileLine* fileline() const override { return nodep()->fileline(); } AstNode* nodep() const { return m_nodep; } AstActive* activep() const { return m_activep; } bool slow() const { return m_slow; } - VNUser accept(GateGraphBaseVisitor& v, VNUser vu = VNUser{0}) override { - return v.visit(this, vu); - } + + // DOT debug + std::string name() const override { return m_nodep->fileline()->ascii(); } + std::string dotColor() const override { return "red"; } }; -// ###################################################################### -// Is this a simple expression with a single input and single output? - -class GateOkVisitor final : public VNVisitorConst { -private: - // RETURN STATE - bool m_isSimple = true; // Set false when we know it isn't simple - GateVarRefList m_rhsVarRefs; // VarRefs on rhs of assignment - AstNode* m_substTreep = nullptr; // What to replace the variable with - // STATE - const bool - m_buffersOnly; // Set when we only allow simple buffering, no equations (for clocks) - const AstNodeVarRef* m_lhsVarRef - = nullptr; // VarRef on lhs of assignment (what we're replacing) - const bool m_dedupe; // Set when we use isGateDedupable instead of isGateOptimizable - int m_ops = 0; // Operation count - - // METHODS - void clearSimple(const char* because) { - if (m_isSimple) { - m_isSimple = false; - UINFO(9, "Clear simple " << because << endl); - } - } - // VISITORS - void visit(AstNodeVarRef* nodep) override { - ++m_ops; - iterateChildrenConst(nodep); - // We only allow a LHS ref for the var being set, and a RHS ref for - // something else being read. - if (nodep->varScopep()->varp()->isSc()) { - clearSimple("SystemC sig"); // Don't want to eliminate the VL_ASSIGN_SI's - } - if (nodep->access().isRW()) { - clearSimple("R/W"); - } else if (nodep->access().isWriteOrRW()) { - if (m_lhsVarRef) clearSimple(">1 lhs varRefs"); - m_lhsVarRef = nodep; - } else { - if (m_rhsVarRefs.size() > 1) { - const AstNodeVarRef* const lastRefp = m_rhsVarRefs.back(); - if (m_buffersOnly) clearSimple(">1 rhs varRefs"); - if (!nodep->varScopep()->varp()->gateMultiInputOptimizable() - // We didn't check multiInput on the first varref, so check it here - || !lastRefp->varScopep()->varp()->gateMultiInputOptimizable()) { - clearSimple("!gateMultiInputOptimizable"); - } - } - m_rhsVarRefs.push_back(nodep); - } - } - void visit(AstNodeAssign* nodep) override { - m_substTreep = nodep->rhsp(); - if (!VN_IS(nodep->lhsp(), NodeVarRef)) { - clearSimple("ASSIGN(non-VARREF)"); - } else if (nodep->isTimingControl()) { - clearSimple("Timing control"); - } else { - iterateChildrenConst(nodep); - } - // We don't push logic other then assignments/NOTs into SenItems - // This avoids a mess in computing what exactly a POSEDGE is - // V3Const cleans up any NOTs by flipping the edges for us - if (m_buffersOnly - && !( - VN_IS(nodep->rhsp(), VarRef) - // Avoid making non-clocked logic into clocked, - // as it slows down the verilator_sim_benchmark - || (VN_IS(nodep->rhsp(), Not) && VN_IS(VN_AS(nodep->rhsp(), Not)->lhsp(), VarRef) - && VN_AS(VN_AS(nodep->rhsp(), Not)->lhsp(), VarRef)->varp()->isUsedClock()))) { - clearSimple("Not a buffer (goes to a clock)"); - } - } - //-------------------- - void visit(AstNode* nodep) override { - // *** Special iterator - if (!m_isSimple) return; // Fastpath - if (++m_ops > v3Global.opt.gateStmts()) clearSimple("--gate-stmts exceeded"); - if (!(m_dedupe ? nodep->isGateDedupable() : nodep->isGateOptimizable()) // - || !nodep->isPure() || nodep->isBrancher()) { - UINFO(5, "Non optimizable type: " << nodep << endl); - clearSimple("Non optimizable type"); - } else { - iterateChildrenConst(nodep); - } - } +class GateEdge final : public V3GraphEdge { + std::string dotLabel() const override { return std::to_string(weight()); } public: - // CONSTRUCTORS - GateOkVisitor(AstNode* nodep, bool buffersOnly, bool dedupe) - : m_buffersOnly{buffersOnly} - , m_dedupe{dedupe} { - // Iterate - iterateConst(nodep); - // Check results - if (!m_substTreep) clearSimple("No assignment found\n"); - for (GateVarRefList::const_iterator it = m_rhsVarRefs.begin(); it != m_rhsVarRefs.end(); - ++it) { - if (m_lhsVarRef && m_lhsVarRef->varScopep() == (*it)->varScopep()) { - clearSimple("Circular logic\n"); // Oh my, we'll get an UNOPTFLAT much later - } - } - if (debug() >= 9 && !m_isSimple) nodep->dumpTree("- gate!Ok: "); - } - ~GateOkVisitor() override = default; - // PUBLIC METHODS - bool isSimple() const { return m_isSimple; } - AstNode* substTree() const { return m_substTreep; } - const GateVarRefList& rhsVarRefs() const { return m_rhsVarRefs; } + GateEdge(V3Graph* graphp, V3GraphVertex* fromp, V3GraphVertex* top, int weight) + : V3GraphEdge{graphp, fromp, top, weight} {} }; -// ###################################################################### -// Replace refs to 'varscp' with 'substp' in 'consumerp' - -static void eliminate(AstNode* logicp, - const std::unordered_map& substitutions, - GateDedupeVarVisitor* varVisp); - -// ###################################################################### -// Gate class functions - -class GateVisitor final : public VNVisitor { -private: +class GateGraph final : public V3Graph { // NODE STATE - // Entire netlist: // AstVarScope::user1p -> GateVarVertex* for usage var, 0=not set yet - // {logic}Node::user1 -> map of substitutions, via m_substitutions - // AstVarScope::user2 -> bool: Signal used in SenItem in *this* always statement - // AstVar::user2 -> bool: Warned about SYNCASYNCNET - // AstNodeVarRef::user2 -> bool: ConcatOffset visited const VNUser1InUse m_inuser1; - const VNUser2InUse m_inuser2; - // Variable substitutions to apply to a given logic block - AstUser1Allocator> m_substitutions; +public: + GateVarVertex* makeVarVertex(AstVarScope* vscp) { + GateVarVertex* vVtxp = reinterpret_cast(vscp->user1p()); + if (!vVtxp) { + UINFO(6, "New vertex " << vscp << endl); + vVtxp = new GateVarVertex{this, vscp}; + vscp->user1p(vVtxp); + if (vscp->varp()->sensIfacep()) { + // Can be used in a class method, which cannot be tracked statically + vVtxp->clearReducibleAndDedupable("VirtIface"); + vVtxp->setConsumed("VirtIface"); + } + if (vscp->varp()->isSigPublic()) { + // Public signals shouldn't be changed, pli code might be messing with them + vVtxp->clearReducibleAndDedupable("SigPublic"); + vVtxp->setConsumed("SigPublic"); + } + if (vscp->varp()->isIO() && vscp->scopep()->isTop()) { + // We may need to convert to/from sysc/reg sigs + vVtxp->setIsTop(); + vVtxp->clearReducibleAndDedupable("isTop"); + vVtxp->setConsumed("isTop"); + } + if (vscp->varp()->isUsedClock()) vVtxp->setConsumed("clock"); + } + return vVtxp; + } + void addEdge(GateVarVertex* srcp, GateLogicVertex* dstp, int weight) { + new GateEdge{this, srcp, dstp, weight}; + } + + void addEdge(GateLogicVertex* srcp, GateVarVertex* dstp, int weight) { + new GateEdge{this, srcp, dstp, weight}; + } +}; + +//###################################################################### +// GateGraph builder + +class GateBuildVisitor final : public VNVisitorConst { // STATE - V3Graph m_graph; // Scoreboard of var usages/dependencies + GateGraph* m_graphp = new GateGraph{}; // The graph being built (var usages/dependencies) GateLogicVertex* m_logicVertexp = nullptr; // Current statement being tracked, nullptr=ignored - AstScope* m_scopep = nullptr; // Current scope being processed const AstNodeModule* m_modp = nullptr; // Current module + const AstScope* m_scopep = nullptr; // Current scope being processed AstActive* m_activep = nullptr; // Current active - bool m_activeReducible = true; // Is activation block reducible? + bool m_inClockedActive = false; // Underneath clocked active bool m_inSenItem = false; // Underneath AstSenItem; any varrefs are clocks - bool m_inSlow = false; // Inside a slow structure - std::vector m_optimized; // Logic blocks optimized - - VDouble0 m_statSigs; // Statistic tracking - VDouble0 m_statRefs; // Statistic tracking - VDouble0 m_statDedupLogic; // Statistic tracking - VDouble0 m_statAssignMerged; // Statistic tracking // METHODS - void checkTimingControl(AstNode* nodep) { - if (nodep->isTimingControl() && m_logicVertexp) { + void checkNode(AstNode* nodep) { + if (nodep->isOutputter()) m_logicVertexp->setConsumed("outputter"); + if (nodep->isTimingControl()) { m_logicVertexp->clearReducibleAndDedupable("TimingControl"); m_logicVertexp->setConsumed("TimingControl"); } } - void iterateNewStmt(AstNode* nodep, const char* nonReducibleReason, - const char* consumeReason) { - if (m_scopep) { - UINFO(5, " STMT " << nodep << endl); - // m_activep is null under AstCFunc's, that's ok. - m_logicVertexp = new GateLogicVertex{&m_graph, m_scopep, nodep, m_activep, m_inSlow}; - if (nonReducibleReason) { - m_logicVertexp->clearReducibleAndDedupable(nonReducibleReason); - } else if (!m_activeReducible) { - // Sequential logic is dedupable - m_logicVertexp->clearReducible("Block Unreducible"); - } - if (consumeReason) m_logicVertexp->setConsumed(consumeReason); - if (VN_IS(nodep, SenItem)) m_logicVertexp->setConsumed("senItem"); - checkTimingControl(nodep); - iterateChildren(nodep); - m_logicVertexp = nullptr; + void iterateLogic(AstNode* nodep, bool slow = false, const char* nonReducibleReason = nullptr, + const char* consumeReason = nullptr) { + UASSERT_OBJ(m_scopep, nodep, "Logic not under Scope"); + UASSERT_OBJ(!m_logicVertexp, nodep, "Logic blocks should not nest"); + VL_RESTORER(m_logicVertexp) + + // m_activep is null under AstCFunc's, that's ok. + m_logicVertexp = new GateLogicVertex{m_graphp, nodep, m_activep, slow}; + if (nonReducibleReason) { + m_logicVertexp->clearReducibleAndDedupable(nonReducibleReason); + } else if (m_inClockedActive) { + m_logicVertexp->clearReducible("Clocked logic"); // but dedupable } + if (consumeReason) m_logicVertexp->setConsumed(consumeReason); + checkNode(nodep); + iterateChildrenConst(nodep); } - GateVarVertex* makeVarVertex(AstVarScope* varscp) { - GateVarVertex* vertexp = reinterpret_cast(varscp->user1p()); - if (!vertexp) { - UINFO(6, "New vertex " << varscp << endl); - vertexp = new GateVarVertex{&m_graph, m_scopep, varscp}; - varscp->user1p(vertexp); - if (varscp->varp()->isUsedVirtIface()) { - // Can be used in a class method, which cannot be tracked statically - vertexp->clearReducibleAndDedupable("VirtIface"); - vertexp->setConsumed("VirtIface"); - } - if (varscp->varp()->isSigPublic()) { - // Public signals shouldn't be changed, pli code might be messing with them - vertexp->clearReducibleAndDedupable("SigPublic"); - vertexp->setConsumed("SigPublic"); - } - if (varscp->varp()->isIO() && varscp->scopep()->isTop()) { - // We may need to convert to/from sysc/reg sigs - vertexp->setIsTop(); - vertexp->clearReducibleAndDedupable("isTop"); - vertexp->setConsumed("isTop"); - } - if (varscp->varp()->isUsedClock()) vertexp->setConsumed("clock"); - } - return vertexp; - } - - void optimizeElimVar(AstVarScope* varscp, AstNode* substp, AstNode* consumerp) { - if (debug() >= 5) consumerp->dumpTree("- elimUsePre: "); - if (!m_substitutions.tryGet(consumerp)) m_optimized.push_back(consumerp); - m_substitutions(consumerp).emplace(varscp, substp->cloneTreePure(false)); - } - - void commitElimVar(AstNode* logicp) { - if (auto* const substitutionsp = m_substitutions.tryGet(logicp)) { - if (!substitutionsp->empty()) { - eliminate(logicp, *substitutionsp, nullptr); - AstNode* const foldedp = V3Const::constifyEdit(logicp); - UASSERT_OBJ(foldedp == logicp, foldedp, "Should not remove whole logic"); - for (const auto& pair : *substitutionsp) pair.second->deleteTree(); - substitutionsp->clear(); - } - } - } - - void optimizeSignals(bool allowMultiIn); - bool elimLogicOkOutputs(GateLogicVertex* consumeVertexp, const GateOkVisitor& okVisitor); - void warnSignals(); - void consumedMark(); - void consumedMarkRecurse(GateEitherVertex* vertexp); - void consumedMove(); - void dedupe(); - void mergeAssigns(); - void decomposeClkVectors(); - // VISITORS - void visit(AstNetlist* nodep) override { - iterateChildren(nodep); - if (dumpGraphLevel() >= 3) m_graph.dumpDotFilePrefixed("gate_pre"); - warnSignals(); // Before loss of sync/async pointers - // Decompose clock vectors -- need to do this before removing redundant edges - decomposeClkVectors(); - m_graph.removeRedundantEdgesSum(&V3GraphEdge::followAlwaysTrue); - if (dumpGraphLevel() >= 6) m_graph.dumpDotFilePrefixed("gate_simp"); - // Find gate interconnect and optimize - m_graph.userClearVertices(); // vertex->user(): bool. Indicates we've set it as consumed - // Get rid of buffers first, - optimizeSignals(false); - // Then propagate more complicated equations - optimizeSignals(true); - // Commit substitutions on the optimized logic - for (AstNode* const logicp : m_optimized) commitElimVar(logicp); - // Remove redundant logic - if (v3Global.opt.fDedupe()) { - dedupe(); - if (dumpGraphLevel() >= 6) m_graph.dumpDotFilePrefixed("gate_dedup"); - } - if (v3Global.opt.fAssemble()) { - mergeAssigns(); - if (dumpGraphLevel() >= 6) m_graph.dumpDotFilePrefixed("gate_assm"); - } - // Consumption warnings - consumedMark(); - if (dumpGraphLevel() >= 3) m_graph.dumpDotFilePrefixed("gate_opt"); - // Rewrite assignments - consumedMove(); - } void visit(AstNodeModule* nodep) override { + UASSERT_OBJ(!m_modp, nodep, "Should not nest"); VL_RESTORER(m_modp); - VL_RESTORER(m_activeReducible); m_modp = nodep; - m_activeReducible = true; - iterateChildren(nodep); + iterateChildrenConst(nodep); } void visit(AstScope* nodep) override { - UINFO(4, " SCOPE " << nodep << endl); + UASSERT_OBJ(!m_scopep, nodep, "Should not nest"); VL_RESTORER(m_scopep); m_scopep = nodep; - m_logicVertexp = nullptr; - iterateChildren(nodep); + iterateChildrenConst(nodep); } void visit(AstActive* nodep) override { - // Create required blocks and add to module - UINFO(4, " BLOCK " << nodep << endl); + UASSERT_OBJ(!m_activep, nodep, "Should not nest"); VL_RESTORER(m_activep); - VL_RESTORER(m_activeReducible); - m_activeReducible = !(nodep->hasClocked()); // Seq logic outputs aren't reducible + VL_RESTORER(m_inClockedActive); m_activep = nodep; - AstNode::user2ClearTree(); - iterateChildren(nodep); - AstNode::user2ClearTree(); + m_inClockedActive = nodep->hasClocked(); + + // AstVarScope::user2 -> bool: Signal used in SenItem in *this* active block + const VNUser2InUse user2InUse; + iterateChildrenConst(nodep); } - void visit(AstNodeVarRef* nodep) override { - if (m_scopep) { - UASSERT_OBJ(m_logicVertexp, nodep, "Var ref not under a logic block"); - AstVarScope* const varscp = nodep->varScopep(); - UASSERT_OBJ(varscp, nodep, "Var didn't get varscoped in V3Scope.cpp"); - GateVarVertex* const vvertexp = makeVarVertex(varscp); - UINFO(5, " VARREF to " << varscp << endl); - if (m_inSenItem) { - vvertexp->setIsClock(); - // For SYNCASYNCNET - varscp->user2(true); - } else if (m_activep && m_activep->hasClocked() && nodep->access().isReadOnly()) { - if (varscp->user2()) { - if (!vvertexp->rstAsyncNodep()) vvertexp->rstAsyncNodep(nodep); - } else { - if (!vvertexp->rstSyncNodep()) vvertexp->rstSyncNodep(nodep); - } - } - // We use weight of one; if we ref the var more than once, when we simplify, - // the weight will increase - if (nodep->access().isWriteOrRW()) { - new V3GraphEdge{&m_graph, m_logicVertexp, vvertexp, 1}; - } - if (nodep->access().isReadOrRW()) { - new V3GraphEdge{&m_graph, vvertexp, m_logicVertexp, 1}; - } - } + + void visit(AstAlwaysPublic* nodep) override { iterateLogic(nodep, true, "AlwaysPublic"); } + void visit(AstCFunc* nodep) override { // + iterateLogic(nodep, nodep->slow(), "C Function", "C Function"); } - void visit(AstAlwaysPublic* nodep) override { - VL_RESTORER(m_inSlow); - m_inSlow = true; - iterateNewStmt(nodep, "AlwaysPublic", nullptr); + void visit(AstNodeProcedure* nodep) override { + const bool slow = VN_IS(nodep, Initial) || VN_IS(nodep, Final); + iterateLogic(nodep, slow, nodep->isJustOneBodyStmt() ? nullptr : "Multiple Stmts"); } - void visit(AstCFunc* nodep) override { - iterateNewStmt(nodep, "User C Function", "User C Function"); + void visit(AstAssignAlias* nodep) override { // + iterateLogic(nodep); + } + void visit(AstAssignW* nodep) override { // + iterateLogic(nodep); + } + void visit(AstCoverToggle* nodep) override { + iterateLogic(nodep, false, "CoverToggle", "CoverToggle"); } - void visit(AstClocking* nodep) override { iterateNewStmt(nodep, nullptr, nullptr); } void visit(AstSenItem* nodep) override { VL_RESTORER(m_inSenItem); m_inSenItem = true; - if (m_logicVertexp) { // Already under logic; presumably a SenGate - iterateChildren(nodep); - } else { // Standalone item, probably right under a SenTree - iterateNewStmt(nodep, nullptr, nullptr); + if (m_logicVertexp) { // Already under logic, e.g.: AstEventControl + iterateChildrenConst(nodep); + } else { // Standalone item, under a SenTree or an Active + iterateLogic(nodep, false, nullptr, "senItem"); } } - void visit(AstNodeProcedure* nodep) override { - VL_RESTORER(m_inSlow); - m_inSlow = VN_IS(nodep, Initial) || VN_IS(nodep, Final); - iterateNewStmt(nodep, (nodep->isJustOneBodyStmt() ? nullptr : "Multiple Stmts"), nullptr); - } - void visit(AstAssignAlias* nodep) override { // - iterateNewStmt(nodep, nullptr, nullptr); - } - void visit(AstAssignW* nodep) override { // - iterateNewStmt(nodep, nullptr, nullptr); - } - void visit(AstCoverToggle* nodep) override { - iterateNewStmt(nodep, "CoverToggle", "CoverToggle"); - } - void visit(AstTraceDecl* nodep) override { - VL_RESTORER(m_inSlow); - m_inSlow = true; - iterateNewStmt(nodep, "Tracing", "Tracing"); + void visit(AstNodeVarRef* nodep) override { + if (!m_logicVertexp) return; + + AstVarScope* const vscp = nodep->varScopep(); + GateVarVertex* const vVtxp = m_graphp->makeVarVertex(vscp); + + if (m_inSenItem) { + vVtxp->setIsClock(); + vscp->user2(true); + } else if (m_inClockedActive && nodep->access().isReadOnly()) { + // For SYNCASYNCNET + if (vscp->user2()) { + if (!vVtxp->rstAsyncNodep()) vVtxp->rstAsyncNodep(nodep); + } else { + if (!vVtxp->rstSyncNodep()) vVtxp->rstSyncNodep(nodep); + } + } + + // We use weight of one; if we ref the var more than once, when we simplify, + // the weight will increase + if (nodep->access().isWriteOrRW()) m_graphp->addEdge(m_logicVertexp, vVtxp, 1); + if (nodep->access().isReadOrRW()) m_graphp->addEdge(vVtxp, m_logicVertexp, 1); } void visit(AstConcat* nodep) override { UASSERT_OBJ(!(VN_IS(nodep->backp(), NodeAssign) && VN_AS(nodep->backp(), NodeAssign)->lhsp() == nodep), nodep, "Concat on LHS of assignment; V3Const should have deleted it"); - iterateChildren(nodep); + iterateChildrenConst(nodep); } //-------------------- void visit(AstNode* nodep) override { - iterateChildren(nodep); - if (nodep->isOutputter() && m_logicVertexp) m_logicVertexp->setConsumed("outputter"); - checkTimingControl(nodep); + if (m_logicVertexp) checkNode(nodep); + iterateChildrenConst(nodep); } -public: // CONSTRUCTORS - explicit GateVisitor(AstNode* nodep) { iterate(nodep); } - ~GateVisitor() override { - V3Stats::addStat("Optimizations, Gate sigs deleted", m_statSigs); - V3Stats::addStat("Optimizations, Gate inputs replaced", m_statRefs); - V3Stats::addStat("Optimizations, Gate sigs deduped", m_statDedupLogic); - V3Stats::addStat("Optimizations, Gate assign merged", m_statAssignMerged); + explicit GateBuildVisitor(AstNetlist* nodep) { iterateChildrenConst(nodep); } + +public: + static std::unique_ptr apply(AstNetlist* netlistp) { + return std::unique_ptr{GateBuildVisitor{netlistp}.m_graphp}; } }; -//---------------------------------------------------------------------- +//###################################################################### +// SYCNASYNC warning -void GateVisitor::optimizeSignals(bool allowMultiIn) { - for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { - GateVarVertex* const vvertexp = itp->cast(); - - // Consider "inlining" variables - if (!vvertexp) continue; - - if (vvertexp->inEmpty()) { // Can't deal with no sources - vvertexp->clearReducibleAndDedupable("inEmpty"); - } else if (!vvertexp->inSize1()) { // Can't deal with more than one src - vvertexp->clearReducibleAndDedupable("size!1"); - } - - // Reduce it? - if (!vvertexp->reducible()) continue; - - // Grab the driving logic - GateLogicVertex* const logicVertexp - = static_cast(vvertexp->inBeginp()->fromp()); - if (!logicVertexp->reducible()) continue; - AstNode* const logicp = logicVertexp->nodep(); - - // Commit pending optimizations to driving logic, as we will re-analyze - commitElimVar(logicp); - - // Can we eliminate? - const GateOkVisitor okVisitor{logicp, vvertexp->isClock(), false}; - - // Was it ok? - if (!okVisitor.isSimple()) continue; - - // Does it read multiple source variables? - if (okVisitor.rhsVarRefs().size() > 1) { - if (!allowMultiIn) continue; - // Do it if not used, or used only once, ignoring traces - int n = 0; - for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep; edgep = edgep->outNextp()) { - const GateLogicVertex* const consumeVertexp - = static_cast(edgep->top()); - // Ignore tracing or other slow path junk, or if the destination is not used - if (!consumeVertexp->slow() && consumeVertexp->outBeginp()) n += edgep->weight(); - if (n > 1) break; - } - - if (n > 1) continue; - } - - // Process it - AstNode* const substp = okVisitor.substTree(); - if (debug() >= 5) logicp->dumpTree("- elimVar: "); - if (debug() >= 5) substp->dumpTree("- subst: "); - ++m_statSigs; - bool removedAllUsages = true; - for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep;) { - GateLogicVertex* const consumeVertexp = static_cast(edgep->top()); - AstNode* const consumerp = consumeVertexp->nodep(); - if (!elimLogicOkOutputs(consumeVertexp, okVisitor /*ref*/)) { - // Cannot optimize this replacement - removedAllUsages = false; - edgep = edgep->outNextp(); - } else { - optimizeElimVar(vvertexp->varScp(), substp, consumerp); - // If the new replacement referred to a signal, - // Correct the graph to point to this new generating variable - const GateVarRefList& rhsVarRefs = okVisitor.rhsVarRefs(); - for (AstNodeVarRef* const refp : rhsVarRefs) { - AstVarScope* const newvarscp = refp->varScopep(); - GateVarVertex* const varvertexp = makeVarVertex(newvarscp); - new V3GraphEdge{&m_graph, varvertexp, consumeVertexp, 1}; - // Propagate clock attribute onto generating node - varvertexp->propagateAttrClocksFrom(vvertexp); - } - // Remove the edge - VL_DO_DANGLING(edgep->unlinkDelete(), edgep); - ++m_statRefs; - edgep = vvertexp->outBeginp(); - } - } - - if (removedAllUsages) { - // Remove input links - while (V3GraphEdge* const edgep = vvertexp->inBeginp()) { - VL_DO_DANGLING(edgep->unlinkDelete(), edgep); - } - // Mark the vertex so we don't mark it as being unconsumed in the next step - vvertexp->user(true); - logicVertexp->user(true); - } - } -} - -bool GateVisitor::elimLogicOkOutputs(GateLogicVertex* consumeVertexp, - const GateOkVisitor& okVisitor) { - // Return true if can optimize - // Return false if the consuming logic has an output signal that the - // replacement logic has as an input - - // Use map to find duplicates between two lists - std::unordered_set varscopes; - // Replacement logic usually has shorter input list, so faster to build list based on it - const GateVarRefList& rhsVarRefs = okVisitor.rhsVarRefs(); - for (GateVarRefList::const_iterator it = rhsVarRefs.begin(); it != rhsVarRefs.end(); ++it) { - AstVarScope* const vscp = (*it)->varScopep(); - varscopes.insert(vscp); - } - for (V3GraphEdge* edgep = consumeVertexp->outBeginp(); edgep; edgep = edgep->outNextp()) { - const GateVarVertex* const consVVertexp = static_cast(edgep->top()); - AstVarScope* const vscp = consVVertexp->varScp(); - if (varscopes.find(vscp) != varscopes.end()) { - UINFO(9, " Block-unopt, insertion generates input vscp " << vscp << endl); - return false; - } - } - return true; -} - -//---------------------------------------------------------------------- - -void GateVisitor::consumedMark() { - // Propagate consumed signals backwards to all producers into a consumed node - m_graph.userClearVertices(); - for (V3GraphVertex* vertexp = m_graph.verticesBeginp(); vertexp; - vertexp = vertexp->verticesNextp()) { - GateEitherVertex* const evertexp = static_cast(vertexp); - if (!evertexp->user() && evertexp->consumed()) consumedMarkRecurse(evertexp); - } -} - -void GateVisitor::consumedMarkRecurse(GateEitherVertex* vertexp) { - if (vertexp->user()) return; // Already marked - vertexp->user(true); - if (!vertexp->consumed()) vertexp->setConsumed("propagated"); - // Walk sources and mark them too - for (V3GraphEdge* edgep = vertexp->inBeginp(); edgep; edgep = edgep->inNextp()) { - GateEitherVertex* const eFromVertexp = static_cast(edgep->fromp()); - consumedMarkRecurse(eFromVertexp); - } -} - -void GateVisitor::consumedMove() { - // Remove unused logic (logic that doesn't hit a combo block or a display statement) - // We need the "usually" block logic to do a better job at this - for (V3GraphVertex* vertexp = m_graph.verticesBeginp(); vertexp; - vertexp = vertexp->verticesNextp()) { - if (const GateVarVertex* const vvertexp = vertexp->cast()) { - if (!vvertexp->consumed() && !vvertexp->user()) { - UINFO(8, "Unconsumed " << vvertexp->varScp() << endl); - } - } else { - const GateLogicVertex* const lvertexp = static_cast(vertexp); - AstNode* const nodep = lvertexp->nodep(); - const AstActive* const oldactp = lvertexp->activep(); // nullptr under cfunc - if (!lvertexp->consumed() && oldactp) { - // Eventually: Move the statement to a new active block - // with "tracing-on" sensitivity - UINFO(8, " Remove unconsumed " << nodep << endl); - nodep->unlinkFrBack(); - VL_DO_DANGLING(pushDeletep(nodep), nodep); - } - } - } -} - -//---------------------------------------------------------------------- - -void GateVisitor::warnSignals() { - AstNode::user2ClearTree(); - for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { +static void v3GateWarnSyncAsync(GateGraph& graph) { + // AstVar::user2 -> bool: Warned about SYNCASYNCNET + const VNUser2InUse user2InUse; + for (V3GraphVertex* itp = graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { if (const GateVarVertex* const vvertexp = itp->cast()) { const AstVarScope* const vscp = vvertexp->varScp(); const AstNode* const sp = vvertexp->rstSyncNodep(); @@ -746,7 +344,7 @@ void GateVisitor::warnSignals() { // This is somewhat wrong, as marking one flop as ok for sync // may mean a different flop now fails. However it's a pain to // then report a warning in a new place - we should report them all at once. - // Instead we'll disable if any disabled + // Instead, we will disable if any disabled if (!vscp->fileline()->warnIsOff(V3ErrorCode::SYNCASYNCNET) && !ap->fileline()->warnIsOff(V3ErrorCode::SYNCASYNCNET) && !sp->fileline()->warnIsOff(V3ErrorCode::SYNCASYNCNET)) { @@ -764,19 +362,526 @@ void GateVisitor::warnSignals() { } } +//###################################################################### +// Find a var's offset in a concatenation (only used by GateClkDecomp) + +class GateConcatVisitor final : public VNVisitorConst { + // STATE + const AstVarScope* m_vscp = nullptr; // Varscope we're trying to find + int m_offset = 0; // Current offset of varscope + int m_found_offset = 0; // Found offset of varscope + bool m_found = false; // Offset found + + // VISITORS + // TODO: This is broken, what if there is logic in between? {a, ~clk} + void visit(AstNodeVarRef* nodep) override { + if (nodep->varScopep() == m_vscp && !nodep->user2() && !m_found) { + // A concatenation may use the same var multiple times + // But the graph will initially have an edge per instance + nodep->user2(true); + m_found_offset = m_offset; + m_found = true; + UINFO(9, "CLK DECOMP Concat found var (off = " << m_offset << ") - " << nodep << endl); + } + m_offset += nodep->dtypep()->width(); + } + void visit(AstConcat* nodep) override { + iterateConst(nodep->rhsp()); + iterateConst(nodep->lhsp()); + } + //-------------------- + void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } + +public: + // PUBLIC METHODS + bool concatOffset(AstConcat* concatp, AstVarScope* vscp, int& offsetr) { + m_vscp = vscp; + m_offset = 0; + m_found = false; + // Iterate + iterateConst(concatp); + offsetr = m_found_offset; + return m_found; + } +}; + +//###################################################################### +// Recurse through the graph, looking for clock vectors to bypass + +class GateClkDecomp final { + // NODE STATE + // AstVarScope::user2p -> bool: already visited + const VNUser2InUse m_inuser2; + + GateGraph& m_graph; // The graph being processed + bool m_clkVectors = false; // A non-single-bit variable is involved in the path + GateVarVertex* m_clkVtxp = nullptr; // The canonical clock variable vertex + GateConcatVisitor m_concatVisitor; + + // Statistics + size_t m_seenClkVectors = 0; + size_t m_decomposedClkVectors = 0; + + void visit(GateVarVertex* vVtxp, int offset) { + AstVarScope* const vscp = vVtxp->varScp(); + + // Can't propagate if this variable is forceable + if (vscp->varp()->isForceable()) return; + + // Check that we haven't been here before + if (vscp->user2SetOnce()) return; + + UINFO(9, "CLK DECOMP Var - " << vVtxp << " : " << vscp << endl); + VL_RESTORER(m_clkVectors); + if (vscp->varp()->width() > 1) { + m_clkVectors = true; + ++m_seenClkVectors; + } + + for (V3GraphEdge *edgep = vVtxp->outBeginp(), *nextp; edgep; edgep = nextp) { + // Need to find the next edge before visiting in case the edge is deleted + nextp = edgep->outNextp(); + visit(edgep->top()->as(), offset, vscp); + } + + vscp->user2(false); + } + + void visit(GateLogicVertex* lVtxp, int offset, AstVarScope* lastVscp) { + int clkOffset = offset; + const AstAssignW* const assignp = VN_CAST(lVtxp->nodep(), AssignW); + if (!assignp || assignp->timingControlp()) return; + UASSERT_OBJ(lVtxp->outSize1(), assignp, "ASSIGNW Driving more than 1 LHS?"); + + AstNodeExpr* const rhsp = assignp->rhsp(); + AstNodeExpr* const lhsp = assignp->lhsp(); + + // RHS + if (const AstSel* const rselp = VN_CAST(rhsp, Sel)) { + if (VN_IS(rselp->lsbp(), Const) && VN_IS(rselp->widthp(), Const)) { + if (clkOffset < rselp->lsbConst() || clkOffset > rselp->msbConst()) return; + clkOffset -= rselp->lsbConst(); + } else { + return; + } + } else if (AstConcat* const rcatp = VN_CAST(rhsp, Concat)) { + int concat_offset; + if (!m_concatVisitor.concatOffset(rcatp, lastVscp, concat_offset /*ref*/)) return; + clkOffset += concat_offset; + } else if (!VN_IS(rhsp, VarRef)) { + return; + } + + // LHS + if (const AstSel* const lselp = VN_CAST(lhsp, Sel)) { + if (VN_IS(lselp->lsbp(), Const) && VN_IS(lselp->widthp(), Const)) { + clkOffset += lselp->lsbConst(); + } else { + return; + } + } else if (const AstVarRef* const refp = VN_CAST(lhsp, VarRef)) { + if (refp->dtypep()->width() == 1 && m_clkVectors) { + UASSERT_OBJ(clkOffset == 0, assignp, + "Should only make it here with clkOffset == 0"); + rhsp->replaceWith( + new AstVarRef{rhsp->fileline(), m_clkVtxp->varScp(), VAccess::READ}); + while (V3GraphEdge* const edgep = lVtxp->inBeginp()) { + VL_DO_DANGLING(edgep->unlinkDelete(), edgep); + } + m_graph.addEdge(m_clkVtxp, lVtxp, 1); + ++m_decomposedClkVectors; + } + } else { + return; + } + + visit(lVtxp->outBeginp()->top()->as(), clkOffset); + } + + explicit GateClkDecomp(GateGraph& graph) + : m_graph{graph} { + UINFO(9, "Starting clock decomposition" << endl); + for (V3GraphVertex* itp = graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { + GateVarVertex* const vVtxp = itp->cast(); + if (!vVtxp) continue; + + const AstVarScope* const vscp = vVtxp->varScp(); + if (vscp->varp()->attrClocker() != VVarAttrClocker::CLOCKER_YES) continue; + + if (vscp->varp()->width() == 1) { + UINFO(9, "CLK DECOMP - " << vVtxp << " : " << vscp << endl); + m_clkVtxp = vVtxp; + visit(vVtxp, 0); + } + } + } + + ~GateClkDecomp() { + V3Stats::addStat("Optimizations, Clocker seen vectors", m_seenClkVectors); + V3Stats::addStat("Optimizations, Clocker decomposed vectors", m_decomposedClkVectors); + } + +public: + static void apply(GateGraph& graph) { GateClkDecomp{graph}; } +}; + +//###################################################################### +// Is this a simple expression with a single input and single output? + +class GateOkVisitor final : public VNVisitorConst { + // RETURN STATE + bool m_isSimple = true; // Set false when we know it isn't simple + std::vector m_readVscps; // Variables read by logic + AstNodeExpr* m_substitutionp = nullptr; // What to replace the variable with + + // STATE + const bool m_dedupe; // Set when we use isGateDedupable instead of isGateOptimizable + + // Set when we only allow simple buffering, no equations (for clocks) + const bool m_buffersOnly; + // VarRef on lhs of assignment (what we're replacing) + const AstNodeVarRef* m_lhsVarRef = nullptr; + int m_ops = 0; // Operation count + + // METHODS + void clearSimple(const char* because) { + if (m_isSimple) UINFO(9, "Clear simple " << because << endl); + m_isSimple = false; + } + + static bool multiInputOptimizable(const AstVarScope* vscp) { + return !vscp->varp()->isUsedClock(); + } + + // VISITORS + void visit(AstNodeVarRef* nodep) override { + if (!m_isSimple) return; + + ++m_ops; + // Don't want to eliminate the VL_ASSIGN_S* + if (nodep->varScopep()->varp()->isSc()) clearSimple("SystemC sig"); + + if (nodep->access().isRW()) { + clearSimple("R/W"); + return; + } + + // We only allow a LHS ref for the var being set, and a RHS ref for + // something else being read. + if (nodep->access().isWriteOnly()) { + if (m_lhsVarRef) clearSimple(">1 write refs"); + m_lhsVarRef = nodep; + } else { + AstVarScope* const vscp = nodep->varScopep(); + // TODO: possible bug, should it be >= 1 as add is below? + if (m_readVscps.size() > 1) { + const AstVarScope* const lastVscp = m_readVscps.back(); + if (m_buffersOnly) { + clearSimple(">1 rhs varRefs"); + } else if (!multiInputOptimizable(vscp) || !multiInputOptimizable(lastVscp)) { + clearSimple("!multiInputOptimizable"); + } + } + m_readVscps.push_back(vscp); + } + } + void visit(AstNodeAssign* nodep) override { + if (!m_isSimple) return; + + m_substitutionp = nodep->rhsp(); + if (!VN_IS(nodep->lhsp(), NodeVarRef)) { + clearSimple("ASSIGN(non-VARREF)"); + } else if (nodep->isTimingControl()) { + clearSimple("Timing control"); + } else { + iterateChildrenConst(nodep); + } + // We don't push logic other than assignments/NOTs into SenItems + // This avoids a mess in computing what exactly a POSEDGE is + // V3Const cleans up any NOTs by flipping the edges for us + if (m_buffersOnly + && !( + VN_IS(nodep->rhsp(), VarRef) + // Avoid making non-clocked logic into clocked, + // as it slows down the verilator_sim_benchmark + || (VN_IS(nodep->rhsp(), Not) && VN_IS(VN_AS(nodep->rhsp(), Not)->lhsp(), VarRef) + && VN_AS(VN_AS(nodep->rhsp(), Not)->lhsp(), VarRef)->varp()->isUsedClock()))) { + clearSimple("Not a buffer (goes to a clock)"); + } + } + //-------------------- + void visit(AstNode* nodep) override { + if (!m_isSimple) return; // Fastpath + + if (++m_ops > v3Global.opt.gateStmts()) { + clearSimple("--gate-stmts exceeded"); + return; + } + + if (!(m_dedupe ? nodep->isGateDedupable() : nodep->isGateOptimizable()) // + || !nodep->isPure() || nodep->isBrancher()) { + UINFO(5, "Non optimizable type: " << nodep << endl); + clearSimple("Non optimizable type"); + return; + } + + iterateChildrenConst(nodep); + } + +public: + // CONSTRUCTORS + GateOkVisitor(AstNode* nodep, bool buffersOnly, bool dedupe) + : m_dedupe{dedupe} + , m_buffersOnly{buffersOnly} { + // Iterate + iterateConst(nodep); + // Check results + if (!m_substitutionp) { + clearSimple("No assignment found\n"); + return; + } + if (m_isSimple && m_lhsVarRef) { + for (const AstVarScope* const vscp : m_readVscps) { + if (m_lhsVarRef->varScopep() == vscp) { + clearSimple("Circular logic\n"); + return; + } + } + } + } + ~GateOkVisitor() override = default; + // PUBLIC METHODS + bool isSimple() const { return m_isSimple; } + AstNodeExpr* substitutionp() const { + UASSERT(m_isSimple, "Can't substitute non-simple"); + return m_substitutionp; + } + const std::vector& readVscps() const { return m_readVscps; } +}; + +//###################################################################### +// GateInline + +class GateInline final { + using Substitutions = std::unordered_map; + + // NODE STATE + // {logic}Node::user2 -> map of substitutions, via m_substitutions + const VNUser2InUse m_inuser2; + + // Variable substitutions to apply to a given logic block + AstUser2Allocator m_substitutions; + + // STATE + GateGraph& m_graph; + size_t m_ord = 0; // Counter for sorting + // Logic block with pending substitutions are stored in this map, together with their ordinal + std::unordered_map m_hasPending; + size_t m_statInlined = 0; // Statistic tracking - signals inlined + size_t m_statRefs = 0; // Statistic tracking + + // METHODS + void recordSubstitution(AstVarScope* vscp, AstNodeExpr* substp, AstNode* logicp) { + m_hasPending.emplace(logicp, ++m_ord); // It's OK if already present + m_substitutions(logicp).emplace(vscp, substp->cloneTreePure(false)); + } + + void commitSubstitutions(AstNode* logicp) { + if (!m_hasPending.erase(logicp)) return; // Had no pending substitutions + + Substitutions& substitutions = m_substitutions(logicp); + UASSERT_OBJ(!substitutions.empty(), logicp, "No pending substitutions"); + + // Recursion filter holding already replaced variables + std::unordered_set replaced(substitutions.size() * 2); + + const std::function visit = [&](AstNodeVarRef* nodep) -> void { + // See if this variable has a substitution + AstVarScope* const vscp = nodep->varScopep(); + const auto& it = substitutions.find(vscp); + if (it == substitutions.end()) return; + + // Do not substitute circular logic + if (!replaced.insert(vscp).second) return; + + // Substitute nodep with substp + AstNodeExpr* const substp = it->second; + + UASSERT_OBJ(nodep->access().isReadOnly(), nodep, "Can't replace write references"); + UASSERT_OBJ(!VN_IS(substp, NodeVarRef) || !nodep->isSame(substp), substp, + "Replacing node with itself; perhaps circular logic?"); + // The replacement + AstNodeExpr* const newp = substp->cloneTreePure(false); + // Which fileline() to use? If replacing with logic, an error/warning is likely to want + // to point to the logic IE what we're replacing with. However, a VARREF should point + // to the original as it's otherwise confusing to throw warnings that point to a PIN + // rather than where the pin us used. + if (VN_IS(newp, VarRef)) newp->fileline(nodep->fileline()); + // Make the newp an rvalue like nodep. + if (AstNodeVarRef* const varrefp = VN_CAST(newp, NodeVarRef)) { + varrefp->access(VAccess::READ); + } + // Replace the node + nodep->replaceWith(newp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + // Recursively substitute the new tree + newp->foreach(visit); + + // Remove from recursion filter + replaced.erase(vscp); + }; + + logicp->foreach(visit); + + AstNode* const simplifiedp = V3Const::constifyEdit(logicp); + UASSERT_OBJ(simplifiedp == logicp, simplifiedp, "Should not remove whole logic"); + for (const auto& pair : substitutions) pair.second->deleteTree(); + substitutions.clear(); + } + + static GateVarVertex* ffToVarVtx(V3GraphVertex* vtxp) { + while (vtxp && !vtxp->is()) vtxp = vtxp->verticesNextp(); + return static_cast(vtxp); + } + + void optimizeSignals(bool allowMultiIn) { + // Consider "inlining" variables + GateVarVertex* nextp = ffToVarVtx(m_graph.verticesBeginp()); + while (GateVarVertex* const vVtxp = nextp) { + // vVtxp and it's driving logic might be deleted, so grab next up front + nextp = ffToVarVtx(vVtxp->verticesNextp()); + + // Nothing to inline if no driver, or multiple drivers ... + if (!vVtxp->inSize1()) continue; + + // Can't inline if non-reducible, etc + if (!vVtxp->reducible()) continue; + + // Grab the driving logic + GateLogicVertex* const lVtxp = vVtxp->inBeginp()->fromp()->as(); + if (!lVtxp->reducible()) continue; + AstNode* const logicp = lVtxp->nodep(); + + // Commit pending optimizations to driving logic, as we will re-analyze + commitSubstitutions(logicp); + + // Can we eliminate? + const GateOkVisitor okVisitor{logicp, vVtxp->isClock(), false}; + + // Was it ok? + if (!okVisitor.isSimple()) continue; + + // Does it read multiple source variables? + if (okVisitor.readVscps().size() > 1) { + if (!allowMultiIn) { + continue; + } else { + // Do it if not used, or used only once, ignoring slow code + int n = 0; + for (V3GraphEdge* ep = vVtxp->outBeginp(); ep; ep = ep->outNextp()) { + const GateLogicVertex* const dstVtxp = ep->top()->as(); + // Ignore slow code, or if the destination is not used + if (!dstVtxp->slow() && dstVtxp->outBeginp()) n += ep->weight(); + if (n > 1) break; + } + if (n > 1) continue; + } + } + + // Process it + ++m_statInlined; + + AstVarScope* const vscp = vVtxp->varScp(); + AstNodeExpr* const substp = okVisitor.substitutionp(); + if (debug() >= 9) { + vscp->dumpTree("substituting: "); + substp->dumpTree(" with: "); + } + + const auto& readVscpsVec = okVisitor.readVscps(); + const std::unordered_set readVscps{readVscpsVec.begin(), + readVscpsVec.end()}; + + for (V3GraphEdge *edgep = vVtxp->outBeginp(), *nextp; edgep; edgep = nextp) { + // Edge might be deleted, so grab next + nextp = edgep->outNextp(); + + GateLogicVertex* const dstVtxp = edgep->top()->as(); + + // If the consumer logic writes one of the variables that the substitution + // is reading, then we would get a cycles, so we cannot do that. + bool canInline = true; + for (V3GraphEdge* edgep = dstVtxp->outBeginp(); edgep; edgep = edgep->outNextp()) { + const GateVarVertex* const consVVertexp = edgep->top()->as(); + if (readVscps.count(consVVertexp->varScp())) { + canInline = false; + break; + } + } + + if (!canInline) continue; // Cannot optimize this replacement + + if (debug() >= 9) dstVtxp->nodep()->dumpTree(" inside: "); + + recordSubstitution(vscp, substp, dstVtxp->nodep()); + + // If the new replacement referred to a signal, + // Correct the graph to point to this new generating variable + for (AstVarScope* const newVscp : okVisitor.readVscps()) { + GateVarVertex* const varvertexp = m_graph.makeVarVertex(newVscp); + m_graph.addEdge(varvertexp, dstVtxp, 1); + // Propagate clock attribute onto generating node + varvertexp->propagateAttrClocksFrom(vVtxp); + } + + // Remove the edge + VL_DO_DANGLING(edgep->unlinkDelete(), edgep); + ++m_statRefs; + } + + // If removed all usage + if (vVtxp->outEmpty()) { + // Remove Variable vertex + VL_DO_DANGLING(vVtxp->unlinkDelete(&m_graph), vVtxp); + // Remove driving logic and vertex + VL_DO_DANGLING(logicp->unlinkFrBack()->deleteTree(), logicp); + VL_DO_DANGLING(lVtxp->unlinkDelete(&m_graph), lVtxp); + } + } + } + + explicit GateInline(GateGraph& graph) + : m_graph{graph} { + // Find gate interconnect and optimize + graph.userClearVertices(); // vertex->user(): bool. Indicates we've set it as consumed + // Get rid of buffers first, + optimizeSignals(false); + // Then propagate more complicated equations + optimizeSignals(true); + // Commit substitutions in insertion order for stability + using Pair = std::pair; + std::vector pending{m_hasPending.begin(), m_hasPending.end()}; + std::sort(pending.begin(), pending.end(), [](const Pair& a, const Pair& b) { // + return a.second < b.second; + }); + for (const auto& pair : pending) commitSubstitutions(pair.first); + } + + ~GateInline() { + V3Stats::addStat("Optimizations, Gate sigs deleted", m_statInlined); + V3Stats::addStat("Optimizations, Gate inputs replaced", m_statRefs); + } + +public: + static void apply(GateGraph& graph) { GateInline{graph}; } +}; + //###################################################################### // Auxiliary hash class for GateDedupeVarVisitor class GateDedupeHash final : public V3DupFinderUserSame { -private: // NODE STATE - // Ast*::user2p -> parent AstNodeAssign* for this rhsp - // AstNodeExpr::user3p -> see AuxAstNodeExpr via m_aux - // VNUser1InUse m_inuser1; (Allocated for use in GateVisitor) - // VNUser2InUse m_inuser2; (Allocated for use in GateVisitor) - const VNUser3InUse m_inuser3; - // VNUser4InUse m_inuser4; (Allocated for use in V3Hasher via V3DupFinder) - + // VNUser2InUse m_inuser2; (Allocated in GateDedupe) struct AuxAstNodeExpr final { // AstActive* of assign, for isSame() in test for duplicate. Set to nullptr if this // assign's tree was later replaced @@ -784,12 +889,15 @@ private: // AstNodeExpr* of assign if condition, for isSame() in test for duplicate. Set to nullptr // if this assign's tree was later replaced AstNodeExpr* condp = nullptr; + // Parent AstNodeAssign* for this rhsp + AstNodeAssign* parentp = nullptr; }; + AstUser2Allocator m_auxNodeExpr; - AstUser3Allocator m_auxNodeExpr; + AstNodeExpr* m_currRhsp = nullptr; // Current node we are searching for duplicates of + AuxAstNodeExpr m_auxCurRhsp; // Aux of current node V3DupFinder m_dupFinder; // Duplicate finder for rhs of assigns - std::unordered_set m_nodeDeleteds; // Any node in this hash was deleted bool same(AstNode* node1p, AstNode* node2p) { // Regarding the complexity of this function 'same': @@ -809,102 +917,46 @@ private: // purposes of V3Gate, we probably only care about them either being identical instances, // or having the same sensitivities anyway, so if this becomes a problem, it can be // improved which should also speed things up), and AstNodeExpr for if conditions, which - // are hopefully small, and to be safe they should probably be only considered same when - // identical instances (otherwise if writing the condition between 2 ifs don't really - // merge). + // are hopefully small. return node1p == node2p || (node1p && node1p->sameTree(node2p)); } -public: - GateDedupeHash() = default; - ~GateDedupeHash() override { - if (v3Global.opt.debugCheck()) check(); - } - - // About to replace a node; any node we're tracking refers to oldp, change it to newp. - // This might be a variable on the lhs of the duplicate tree, - // or could be a rhs variable in a tree we're not replacing (or not yet anyways) - void hashReplace(AstNode* oldp, AstNode* newp) { - UINFO(9, "replacing " << (void*)oldp << " with " << (void*)newp << endl); - // We could update the activep and condp but the resulting node - // still has incorrect hash. We really need to remove all hash on - // the whole hash entry tree involving the replaced node and - // rehash. That's complicated and this is rare, so just remove it - // from consideration. - m_nodeDeleteds.insert(oldp); - } - bool isReplaced(AstNodeExpr* nodep) { - // Assignment may have been hashReplaced, if so consider non-match (effectively removed) - const auto& aux = m_auxNodeExpr(nodep); - AstActive* const activep = aux.activep; - AstNodeExpr* const condp = aux.condp; - return (activep && m_nodeDeleteds.count(activep)) - || (condp && m_nodeDeleteds.count(condp)); - } - // Callback from V3DupFinder::findDuplicate bool isSame(AstNode* node1p, AstNode* node2p) override { - AstNodeExpr* const expr1p = VN_AS(node1p, NodeExpr); - AstNodeExpr* const expr2p = VN_AS(node2p, NodeExpr); - - // Assignment may have been hashReplaced, if so consider non-match (effectively removed) - if (isReplaced(expr1p) || isReplaced(expr2p)) { - // UINFO(9, "isSame hit on replaced "<<(void*)node1p<<" "<<(void*)node2p<user2p()->type() == node2p->user2p()->type(); + UASSERT_OBJ(node1p == m_currRhsp, m_currRhsp, "Comparing to unexpected node"); + const auto& aux2 = m_auxNodeExpr(VN_AS(node2p, NodeExpr)); + return m_auxCurRhsp.parentp->type() == aux2.parentp->type() // + && same(m_auxCurRhsp.activep, aux2.activep) // + && same(m_auxCurRhsp.condp, aux2.condp); } - const AstNodeAssign* hashAndFindDupe(AstNodeAssign* assignp, AstActive* extra1p, - AstNodeExpr* extra2p) { - // Legal for extra1p/2p to be nullptr, we'll compare with other assigns with extras also - // nullptr - AstNodeExpr* const rhsp = assignp->rhsp(); - rhsp->user2p(assignp); - auto& aux = m_auxNodeExpr(rhsp); - aux.activep = extra1p; - aux.condp = extra2p; +public: + GateDedupeHash() = default; + ~GateDedupeHash() = default; - const auto inserted = m_dupFinder.insert(rhsp); - const auto dupit = m_dupFinder.findDuplicate(rhsp, this); - // Even though rhsp was just inserted, V3DupFinder::findDuplicate doesn't - // return anything in the hash that has the same pointer (V3DupFinder::findDuplicate) - // So dupit is either a different, duplicate rhsp, or the end of the hash. - if (dupit != m_dupFinder.end()) { - m_dupFinder.erase(inserted); - return VN_AS(dupit->second->user2p(), NodeAssign); - } - // Retain new inserted information + const AstNodeAssign* hashAndFindDupe(AstNodeAssign* assignp, AstActive* activep, + AstNodeExpr* condp) { + // Legal for activep to be nullptr, we'll compare with other assigns with also nullptr + m_currRhsp = assignp->rhsp(); + m_auxCurRhsp.activep = activep; + m_auxCurRhsp.condp = condp; + m_auxCurRhsp.parentp = assignp; + + // Check for a duplicate, if found return its assignment + const auto it = m_dupFinder.findDuplicate(m_currRhsp, this); + if (it != m_dupFinder.end()) return m_auxNodeExpr(VN_AS(it->second, NodeExpr)).parentp; + + // Insert new node + m_dupFinder.insert(m_currRhsp); + m_auxNodeExpr(m_currRhsp) = m_auxCurRhsp; return nullptr; } - - void check() { - for (const auto& itr : m_dupFinder) { - AstNodeExpr* const nodep = VN_AS(itr.second, NodeExpr); - const auto& aux = m_auxNodeExpr(nodep); - const AstActive* const activep = aux.activep; - const AstNodeExpr* const condVarp = aux.condp; - if (!isReplaced(nodep)) { - // This class won't break if activep isn't an active, or - // ifVar isn't a var, but this is checking the caller's construction. - UASSERT_OBJ(!activep || (!VN_DELETED(activep)), nodep, - "V3DupFinder check failed, lost active pointer"); - UASSERT_OBJ(!condVarp || !VN_DELETED(condVarp), nodep, - "V3DupFinder check failed, lost if pointer"); - } - } - } }; //###################################################################### // Have we seen the rhs of this assign before? -class GateDedupeVarVisitor final : public VNVisitor { +class GateDedupeVarVisitor final : public VNVisitorConst { // Given a node, it is visited to try to find the AstNodeAssign under // it that can used for dedupe. // Right now, only the following node trees are supported for dedupe. @@ -916,7 +968,7 @@ class GateDedupeVarVisitor final : public VNVisitor { // and the assign must be the only node under the if, other than the ifcond) // Any other ordering or node type, except for an AstComment, makes it not dedupable // AstExprStmt in the subtree of a node also makes the node not dedupable. -private: + // STATE GateDedupeHash m_ghash; // Hash used to find dupes of rhs of assign AstNodeAssign* m_assignp = nullptr; // Assign found for dedupe @@ -925,67 +977,70 @@ private: bool m_dedupable = true; // Determined the assign to be dedupable // VISITORS - void visit(AstNodeAssign* assignp) override { - if (m_dedupable) { - // I think we could safely dedupe an always block with multiple - // non-blocking statements, but erring on side of caution here - if (!m_assignp) { - m_assignp = assignp; - m_dedupable = !assignp->exists([&](AstExprStmt*) { return true; }); - } else { - m_dedupable = false; - } + void visit(AstNodeAssign* nodep) override { + if (!m_dedupable) return; + + // I think we could safely dedupe an always block with multiple + // non-blocking statements, but erring on side of caution here + if (!m_assignp) { + m_assignp = nodep; + m_dedupable = !nodep->exists([](AstExprStmt*) { return true; }); + return; } + + m_dedupable = false; } - void visit(AstAlways* alwaysp) override { - if (m_dedupable) { - if (!m_always) { - m_always = true; - iterateAndNextNull(alwaysp->stmtsp()); - } else { - m_dedupable = false; - } + + void visit(AstAlways* nodep) override { + if (!m_dedupable) return; + + if (!m_always) { + m_always = true; + iterateAndNextConstNull(nodep->stmtsp()); + return; } + + m_dedupable = false; } + // Ugly support for latches of the specific form - // always @(...) // if (...) // foo = ...; // or foo <= ...; - void visit(AstNodeIf* ifp) override { - if (m_dedupable) { - if (m_always && !m_ifCondp && !ifp->elsesp()) { - // we're under an always, this is the first IF, and there's no else - m_ifCondp = ifp->condp(); - m_dedupable = !m_ifCondp->exists([&](AstExprStmt*) { return true; }); - iterateAndNextNull(ifp->thensp()); - } else { - m_dedupable = false; - } + void visit(AstNodeIf* nodep) override { + if (!m_dedupable) return; + + if (m_always && !m_ifCondp && !nodep->elsesp()) { + // we're under an always, this is the first IF, and there's no else + m_ifCondp = nodep->condp(); + m_dedupable = !m_ifCondp->exists([](AstExprStmt*) { return true; }); + iterateAndNextConstNull(nodep->thensp()); + return; } + + m_dedupable = false; } void visit(AstComment*) override {} // NOP //-------------------- - void visit(AstNode*) override { // - m_dedupable = false; - } + void visit(AstNode*) override { m_dedupable = false; } public: // CONSTRUCTORS GateDedupeVarVisitor() = default; ~GateDedupeVarVisitor() override = default; // PUBLIC METHODS - AstNodeVarRef* findDupe(AstNode* nodep, AstVarScope* consumerVarScopep, AstActive* activep) { + AstNodeVarRef* findDupe(AstNode* logicp, AstVarScope* consumerVscp, AstActive* activep) { m_assignp = nullptr; m_ifCondp = nullptr; m_always = false; m_dedupable = true; - iterate(nodep); + iterateConst(logicp); if (m_dedupable && m_assignp) { const AstNode* const lhsp = m_assignp->lhsp(); // Possible todo, handle more complex lhs expressions - if (const AstNodeVarRef* const lhsVarRefp = VN_CAST(lhsp, NodeVarRef)) { - UASSERT_OBJ(lhsVarRefp->varScopep() == consumerVarScopep, consumerVarScopep, + if (const AstNodeVarRef* const lRefp = VN_CAST(lhsp, NodeVarRef)) { + UASSERT_OBJ(lRefp->varScopep() == consumerVscp, consumerVscp, "Consumer doesn't match lhs of assign"); if (const AstNodeAssign* const dup = m_ghash.hashAndFindDupe(m_assignp, activep, m_ifCondp)) { @@ -995,510 +1050,336 @@ public: } return nullptr; } - void hashReplace(AstNode* oldp, AstNode* newp) { m_ghash.hashReplace(oldp, newp); } }; -// ###################################################################### +//###################################################################### +// Recurse through the graph, looking for duplicate expressions on the rhs of an assign -static void eliminate(AstNode* logicp, - const std::unordered_map& substitutions, - GateDedupeVarVisitor* varVisp) { - - // Recursion filter holding already replaced variables - std::unordered_set replaced(substitutions.size() * 2); - - const std::function visit = [&, varVisp](AstNodeVarRef* nodep) -> void { - // See if this variable has a substitution - AstVarScope* const vscp = nodep->varScopep(); - const auto& it = substitutions.find(vscp); - if (it == substitutions.end()) return; - - // Do not substitute circular logic - if (!replaced.insert(vscp).second) return; - - AstNode* const substp = it->second; - - // Substitute in the new tree - UASSERT_OBJ(nodep->access().isReadOnly(), nodep, - "Can't replace lvalue assignments with const var"); - UASSERT_OBJ(!(VN_IS(substp, NodeVarRef) && nodep->isSame(substp)), - // Prevent an infinite loop... - substp, "Replacing node with itself; perhaps circular logic?"); - // The replacement - AstNode* const newp = substp->cloneTreePure(false); - // Which fileline() to use? If replacing with logic, an error/warning is likely to want - // to point to the logic IE what we're replacing with. However, a VARREF should point - // to the original as it's otherwise confusing to throw warnings that point to a PIN - // rather than where the pin us used. - if (VN_IS(newp, VarRef)) newp->fileline(nodep->fileline()); - // Make the newp an rvalue like nodep. This facilitates the hashing in dedupe. - if (AstNodeVarRef* const varrefp = VN_CAST(newp, NodeVarRef)) { - varrefp->access(VAccess::READ); - } - // Update hash? - if (varVisp) varVisp->hashReplace(nodep, newp); - // Replace the node - nodep->replaceWith(newp); - VL_DO_DANGLING(nodep->deleteTree(), nodep); - // Recursively substitute the new tree - newp->foreach(visit); - - // Remove from recursion filter - replaced.erase(vscp); - }; - - logicp->foreach(visit); -} - -// ###################################################################### -// Recurse through the graph, looking for duplicate expressions on the rhs of an assign - -class GateDedupeGraphVisitor final : public GateGraphBaseVisitor { -private: +class GateDedupe final { // NODE STATE // AstVarScope::user2p -> bool: already visited - // VNUser2InUse m_inuser2; (Allocated for use in GateVisitor) - VDouble0 m_numDeduped; // Statistic tracking + const VNUser2InUse m_inuser2; + + // STATE + size_t m_statDedupLogic = 0; // Statistic tracking GateDedupeVarVisitor m_varVisitor; // Looks for a dupe of the logic - int m_depth = 0; // Iteration depth + uint32_t m_depth = 0; // Iteration depth + + void visit(GateVarVertex* vVtxp) { + // Break loops; before user2 set so hit this vertex later + if (m_depth > GATE_DEDUP_MAX_DEPTH) return; - VNUser visit(GateVarVertex* vvertexp, VNUser) override { // Check that we haven't been here before - if (m_depth > GATE_DEDUP_MAX_DEPTH) - return VNUser{0}; // Break loops; before user2 set so hit this vertex later - if (vvertexp->varScp()->user2()) return VNUser{0}; - vvertexp->varScp()->user2(true); + if (vVtxp->varScp()->user2SetOnce()) return; - m_depth++; - if (vvertexp->inSize1()) { - AstNodeVarRef* const dupVarRefp = static_cast( - vvertexp->iterateInEdges(*this, VNUser{vvertexp}).toNodep()); - if (dupVarRefp) { // visit(GateLogicVertex*...) returned match - const V3GraphEdge* edgep = vvertexp->inBeginp(); - GateLogicVertex* const lvertexp = static_cast(edgep->fromp()); - UASSERT_OBJ(vvertexp->dedupable(), vvertexp->varScp(), - "GateLogicVertex* visit should have returned nullptr " - "if consumer var vertex is not dedupable."); - const GateOkVisitor okVisitor{lvertexp->nodep(), false, true}; - if (okVisitor.isSimple()) { - const AstVarScope* const dupVarScopep = dupVarRefp->varScopep(); - GateVarVertex* const dupVvertexp - = reinterpret_cast(dupVarScopep->user1p()); - UINFO(4, "replacing " << vvertexp << " with " << dupVvertexp << endl); - ++m_numDeduped; - // Replace all of this varvertex's consumers with dupVarRefp - for (V3GraphEdge* outedgep = vvertexp->outBeginp(); outedgep;) { - const GateLogicVertex* const consumeVertexp - = static_cast(outedgep->top()); - AstNode* const consumerp = consumeVertexp->nodep(); - UINFO(9, - "elim src vtx" << lvertexp << " node " << lvertexp->nodep() << endl); - UINFO(9, - "elim cons vtx" << consumeVertexp << " node " << consumerp << endl); - UINFO(9, "elim var vtx " << vvertexp << " node " << vvertexp->varScp() - << endl); - UINFO(9, "replace with " << dupVarRefp << endl); - if (lvertexp == consumeVertexp) { - UINFO(9, "skipping as self-recirculates\n"); - } else { - eliminate(consumerp, {std::make_pair(vvertexp->varScp(), dupVarRefp)}, - &m_varVisitor); - } - outedgep = outedgep->relinkFromp(dupVvertexp); - } - // Propagate attributes - dupVvertexp->propagateAttrClocksFrom(vvertexp); - // Remove inputs links - while (V3GraphEdge* const inedgep = vvertexp->inBeginp()) { - VL_DO_DANGLING(inedgep->unlinkDelete(), inedgep); - } - vvertexp->user(true); - lvertexp->user(true); - } - } + VL_RESTORER(m_depth); + ++m_depth; + if (!vVtxp->inSize1()) return; + + AstNodeVarRef* dupRefp = nullptr; + for (V3GraphEdge* edgep = vVtxp->inBeginp(); edgep; edgep = edgep->inNextp()) { + dupRefp = visit(edgep->fromp()->as(), vVtxp); } - m_depth--; - return VNUser{0}; + if (!dupRefp) return; + + UASSERT_OBJ(vVtxp->dedupable(), vVtxp->varScp(), + "GateLogicVertex* visit should have returned nullptr " + "if consumer var vertex is not dedupable."); + + GateLogicVertex* const lVtxp = vVtxp->inBeginp()->fromp()->as(); + const GateOkVisitor okVisitor{lVtxp->nodep(), false, true}; + if (!okVisitor.isSimple()) return; + + ++m_statDedupLogic; + GateVarVertex* const dupVVtxp = dupRefp->varScopep()->user1u().to(); + UINFO(4, "replacing " << vVtxp << " with " << dupVVtxp << endl); + + // Replace all of this varvertex's consumers with dupRefp + for (V3GraphEdge *edgep = vVtxp->outBeginp(), *nextp; edgep; edgep = nextp) { + nextp = edgep->outNextp(); + const GateLogicVertex* const consumerVtxp = edgep->top()->as(); + AstNode* const consumerp = consumerVtxp->nodep(); + UINFO(9, "elim src vtx" << lVtxp << " node " << lVtxp->nodep() << endl); + UINFO(9, "elim cons vtx" << consumerVtxp << " node " << consumerp << endl); + UINFO(9, "elim var vtx " << vVtxp << " node " << vVtxp->varScp() << endl); + UINFO(9, "replace with " << dupRefp << endl); + if (lVtxp == consumerVtxp) { + UINFO(9, "skipping as self-recirculates\n"); + } else { + // Substitute consumer logic + consumerp->foreach([&](AstNodeVarRef* refp) { + if (refp->varScopep() != vVtxp->varScp()) return; + + UASSERT_OBJ(refp->access().isReadOnly(), refp, "Can't replace a write ref"); + + // The replacement + AstNodeVarRef* const newp = dupRefp->cloneTreePure(false); + // A VARREF should point to the original as it's otherwise confusing to throw + // warnings that point to a PIN rather than where the pin is used. + newp->fileline(refp->fileline()); + newp->access(VAccess::READ); + + // Replace the node + refp->replaceWith(newp); + VL_DO_DANGLING(refp->deleteTree(), refp); + }); + } + edgep->relinkFromp(dupVVtxp); + } + + // Remove inputs links + while (V3GraphEdge* const edgep = vVtxp->inBeginp()) { + VL_DO_DANGLING(edgep->unlinkDelete(), edgep); + } + + // Propagate attributes + dupVVtxp->propagateAttrClocksFrom(vVtxp); } - // Given iterated logic, starting at vu which was consumer's GateVarVertex - // Returns a varref that has the same logic input; or nullptr if none - VNUser visit(GateLogicVertex* lvertexp, VNUser vu) override { - lvertexp->iterateInEdges(*this); + // Given iterated logic, starting at consumerVtxp, returns a varref that + // has the same logic input, or nullptr if none + AstNodeVarRef* visit(GateLogicVertex* lVtxp, const GateVarVertex* consumerVtxp) { + for (V3GraphEdge* edgep = lVtxp->inBeginp(); edgep; edgep = edgep->inNextp()) { + visit(edgep->fromp()->as()); + } - const GateVarVertex* const consumerVvertexpp - = static_cast(vu.toGraphVertex()); - if (lvertexp->dedupable() && consumerVvertexpp->dedupable()) { - AstNode* const nodep = lvertexp->nodep(); - AstVarScope* const consumerVarScopep = consumerVvertexpp->varScp(); + if (lVtxp->dedupable() && consumerVtxp->dedupable()) { // TODO: Doing a simple pointer comparison of activep won't work // optimally for statements under generated clocks. Statements under // different generated clocks will never compare as equal, even if the // generated clocks are deduped into one clock. - AstActive* const activep = lvertexp->activep(); - return VNUser{m_varVisitor.findDupe(nodep, consumerVarScopep, activep)}; + return m_varVisitor.findDupe(lVtxp->nodep(), consumerVtxp->varScp(), lVtxp->activep()); } - return VNUser{0}; + return nullptr; } -public: - explicit GateDedupeGraphVisitor(V3Graph* graphp) - : GateGraphBaseVisitor{graphp} {} - void dedupeTree(GateVarVertex* vvertexp) { vvertexp->accept(*this); } - VDouble0 numDeduped() { return m_numDeduped; } -}; - -//---------------------------------------------------------------------- - -void GateVisitor::dedupe() { - AstNode::user2ClearTree(); - GateDedupeGraphVisitor deduper{&m_graph}; - // Traverse starting from each of the clocks - UINFO(9, "Gate dedupe() clocks:\n"); - for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { - if (GateVarVertex* const vvertexp = itp->cast()) { - if (vvertexp->isClock()) deduper.dedupeTree(vvertexp); + explicit GateDedupe(GateGraph& graph) { + // Traverse starting from each of the clocks + UINFO(9, "Gate dedupe() clocks:\n"); + for (V3GraphVertex* itp = graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { + if (GateVarVertex* const vVtxp = itp->cast()) { + if (vVtxp->isClock()) visit(vVtxp); + } } - } - // Traverse starting from each of the outputs - UINFO(9, "Gate dedupe() outputs:\n"); - for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { - if (GateVarVertex* const vvertexp = itp->cast()) { - if (vvertexp->isTop() && vvertexp->varScp()->varp()->isWritable()) { - deduper.dedupeTree(vvertexp); + // Traverse starting from each of the outputs + UINFO(9, "Gate dedupe() outputs:\n"); + for (V3GraphVertex* itp = graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { + if (GateVarVertex* const vVtxp = itp->cast()) { + if (vVtxp->isTop() && vVtxp->varScp()->varp()->isWritable()) visit(vVtxp); } } } - m_statDedupLogic += deduper.numDeduped(); -} + + ~GateDedupe() { V3Stats::addStat("Optimizations, Gate sigs deduped", m_statDedupLogic); } + +public: + static void apply(GateGraph& graph) { GateDedupe{graph}; } +}; //###################################################################### // Recurse through the graph, try to merge assigns -class GateMergeAssignsGraphVisitor final : public GateGraphBaseVisitor { -private: - // NODE STATE - AstNodeAssign* m_assignp = nullptr; - const AstActive* m_activep = nullptr; - GateLogicVertex* m_logicvp = nullptr; - VDouble0 m_numMergedAssigns; // Statistic tracking +class GateMergeAssignments final { + GateGraph& m_graph; + size_t m_statAssignMerged = 0; // Statistic tracking // assemble two Sel into one if possible - AstSel* merge(AstSel* pre, AstSel* cur) { - const AstVarRef* const preVarRefp = VN_CAST(pre->fromp(), VarRef); - AstVarRef* const curVarRefp = VN_CAST(cur->fromp(), VarRef); - if (!preVarRefp || !curVarRefp || !curVarRefp->same(preVarRefp)) { - return nullptr; // not the same var - } - const AstConst* const pstart = VN_CAST(pre->lsbp(), Const); - const AstConst* const pwidth = VN_CAST(pre->widthp(), Const); - const AstConst* const cstart = VN_CAST(cur->lsbp(), Const); - const AstConst* const cwidth = VN_CAST(cur->widthp(), Const); + AstSel* merge(AstSel* prevSelp, AstSel* currSelp) { + const AstVarRef* const pRefp = VN_CAST(prevSelp->fromp(), VarRef); + AstVarRef* const cRefp = VN_CAST(currSelp->fromp(), VarRef); + if (!pRefp || !cRefp || !cRefp->same(pRefp)) return nullptr; // not the same var + + const AstConst* const pstart = VN_CAST(prevSelp->lsbp(), Const); + const AstConst* const pwidth = VN_CAST(prevSelp->widthp(), Const); + const AstConst* const cstart = VN_CAST(currSelp->lsbp(), Const); + const AstConst* const cwidth = VN_CAST(currSelp->widthp(), Const); if (!pstart || !pwidth || !cstart || !cwidth) return nullptr; // too complicated - if (cur->lsbConst() + cur->widthConst() == pre->lsbConst()) { - return new AstSel{curVarRefp->fileline(), curVarRefp->cloneTree(false), - cur->lsbConst(), pre->widthConst() + cur->widthConst()}; + + if (currSelp->msbConst() + 1 == prevSelp->lsbConst()) { + return new AstSel{cRefp->fileline(), cRefp->cloneTree(false), currSelp->lsbConst(), + prevSelp->widthConst() + currSelp->widthConst()}; } else { return nullptr; } } - VNUser visit(GateVarVertex* vvertexp, VNUser) override { - for (V3GraphEdge* edgep = vvertexp->inBeginp(); edgep;) { - V3GraphEdge* oldedgep = edgep; - edgep = edgep->inNextp(); // for recursive since the edge could be deleted - if (GateLogicVertex* const lvertexp = oldedgep->fromp()->cast()) { - if (AstNodeAssign* const assignp = VN_CAST(lvertexp->nodep(), NodeAssign)) { - // if (lvertexp->outSize1() && VN_IS(assignp->lhsp(), Sel)) { - if (VN_IS(assignp->lhsp(), Sel) && lvertexp->outSize1()) { - UINFO(9, "assing to the nodep[" << VN_AS(assignp->lhsp(), Sel)->lsbConst() - << "]" << endl); - // first assign with Sel-lhs - if (!m_activep) m_activep = lvertexp->activep(); - if (!m_logicvp) m_logicvp = lvertexp; - if (!m_assignp) m_assignp = assignp; + void process(GateVarVertex* vVtxp) { + GateLogicVertex* prevLVtxp = nullptr; + AstNodeAssign* prevAssignp = nullptr; - // not under the same active - if (m_activep != lvertexp->activep()) { - m_activep = lvertexp->activep(); - m_logicvp = lvertexp; - m_assignp = assignp; - continue; - } + for (V3GraphEdge *edgep = vVtxp->inBeginp(), *nextp; edgep; edgep = nextp) { + nextp = edgep->inNextp(); // fThe edge could be deleted - AstSel* const preselp = VN_CAST(m_assignp->lhsp(), Sel); - AstSel* const curselp = VN_CAST(assignp->lhsp(), Sel); - if (!preselp || !curselp) continue; + GateLogicVertex* const lVtxp = edgep->fromp()->as(); + if (!lVtxp->outSize1()) continue; - if (AstSel* const newselp = merge(preselp, curselp)) { - UINFO(5, "assemble to new sel: " << newselp << endl); - // replace preSel with newSel - preselp->replaceWith(newselp); - VL_DO_DANGLING(preselp->deleteTree(), preselp); - // create new rhs for pre assignment - AstNode* const newrhsp - = new AstConcat{m_assignp->rhsp()->fileline(), - m_assignp->rhsp()->cloneTreePure(false), - assignp->rhsp()->cloneTreePure(false)}; - AstNode* const oldrhsp = m_assignp->rhsp(); - oldrhsp->replaceWith(newrhsp); - VL_DO_DANGLING(oldrhsp->deleteTree(), oldrhsp); - m_assignp->dtypeChgWidthSigned(m_assignp->width() + assignp->width(), - m_assignp->width() + assignp->width(), - VSigning::SIGNED); - // don't need to delete, will be handled - // assignp->unlinkFrBack(); VL_DO_DANGLING(assignp->deleteTree(), - // assignp); + AstNodeAssign* const assignp = VN_CAST(lVtxp->nodep(), NodeAssign); + if (!assignp) continue; - // update the graph - { - // delete all inedges to lvertexp - if (!lvertexp->inEmpty()) { - for (V3GraphEdge* ledgep = lvertexp->inBeginp(); ledgep;) { - V3GraphEdge* oedgep = ledgep; - ledgep = ledgep->inNextp(); - GateEitherVertex* const fromvp - = static_cast(oedgep->fromp()); - new V3GraphEdge{m_graphp, fromvp, m_logicvp, 1}; - VL_DO_DANGLING(oedgep->unlinkDelete(), oedgep); - } - } - // delete all outedges to lvertexp, only one - VL_DO_DANGLING(oldedgep->unlinkDelete(), oldedgep); - } - ++m_numMergedAssigns; - } else { - m_assignp = assignp; - m_logicvp = lvertexp; - } - } + if (!VN_IS(assignp->lhsp(), Sel)) continue; + + // First assign with Sel-lhs, or not under the same active + if (!prevLVtxp || prevLVtxp->activep() != lVtxp->activep()) { + prevLVtxp = lVtxp; + prevAssignp = assignp; + continue; + } + + UASSERT_OBJ(prevAssignp->type() == assignp->type(), assignp, "Mismatched types"); + + AstSel* const prevSelp = VN_AS(prevAssignp->lhsp(), Sel); + AstSel* const currSelp = VN_AS(assignp->lhsp(), Sel); + + if (AstSel* const newSelp = merge(prevSelp, currSelp)) { + UINFO(5, "assemble to new sel: " << newSelp << endl); + // replace preSel with newSel + prevSelp->replaceWith(newSelp); + VL_DO_DANGLING(prevSelp->deleteTree(), prevSelp); + // create new rhs for pre assignment + AstNode* const newRhsp = new AstConcat{prevAssignp->rhsp()->fileline(), + prevAssignp->rhsp()->cloneTreePure(false), + assignp->rhsp()->cloneTreePure(false)}; + AstNode* const prevRhsp = prevAssignp->rhsp(); + prevRhsp->replaceWith(newRhsp); + VL_DO_DANGLING(prevRhsp->deleteTree(), prevRhsp); + // Why do we care about the type of an assignment? + prevAssignp->dtypeChgWidthSigned(prevAssignp->width() + assignp->width(), + prevAssignp->width() + assignp->width(), + VSigning::SIGNED); + // Don't need to delete assignp, will be handled + + // Update the graph + while (V3GraphEdge* const iedgep = lVtxp->inBeginp()) { + GateVarVertex* const fromVtxp = iedgep->fromp()->as(); + m_graph.addEdge(fromVtxp, prevLVtxp, 1); + VL_DO_DANGLING(iedgep->unlinkDelete(), iedgep); } + + // Delete the out-edges of lVtxp (there is only one, we checked earlier) + VL_DO_DANGLING(edgep->unlinkDelete(), edgep); + + ++m_statAssignMerged; + } else { + prevLVtxp = lVtxp; + prevAssignp = assignp; } } - return VNUser{0}; } - VNUser visit(GateLogicVertex*, VNUser) override { // - return VNUser{0}; + + explicit GateMergeAssignments(GateGraph& graph) + : m_graph{graph} { + UINFO(6, "mergeAssigns\n"); + for (V3GraphVertex* itp = graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { + if (GateVarVertex* const vVtxp = itp->cast()) process(vVtxp); + } + } + + ~GateMergeAssignments() { + V3Stats::addStat("Optimizations, Gate assign merged", m_statAssignMerged); } public: - explicit GateMergeAssignsGraphVisitor(V3Graph* graphp) - : GateGraphBaseVisitor{graphp} {} - void mergeAssignsTree(GateVarVertex* vvertexp) { vvertexp->accept(*this); } - VDouble0 numMergedAssigns() { return m_numMergedAssigns; } + static void apply(GateGraph& graph) { GateMergeAssignments{graph}; } }; -//---------------------------------------------------------------------- - -void GateVisitor::mergeAssigns() { - UINFO(6, "mergeAssigns\n"); - GateMergeAssignsGraphVisitor merger{&m_graph}; - for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { - if (GateVarVertex* const vvertexp = itp->cast()) { - merger.mergeAssignsTree(vvertexp); - } - } - m_statAssignMerged += merger.numMergedAssigns(); -} - //###################################################################### -// Find a var's offset in a concatenation +// GateUnused -class GateConcatVisitor final : public VNVisitorConst { -private: +class GateUnused final { // STATE - const AstVarScope* m_vscp = nullptr; // Varscope we're trying to find - int m_offset = 0; // Current offset of varscope - int m_found_offset = 0; // Found offset of varscope - bool m_found = false; // Offset found + GateGraph& m_graph; - // VISITORS - void visit(AstNodeVarRef* nodep) override { - UINFO(9, "CLK DECOMP Concat search var (off = " << m_offset << ") - " << nodep << endl); - if (nodep->varScopep() == m_vscp && !nodep->user2() && !m_found) { - // A concatenation may use the same var multiple times - // But the graph will initially have an edge per instance - nodep->user2(true); - m_found_offset = m_offset; - m_found = true; - UINFO(9, "CLK DECOMP Concat found var (off = " << m_offset << ") - " << nodep << endl); + // METHODS + + void markRecurse(GateEitherVertex* vtxp) { + if (vtxp->user()) return; // Already marked + vtxp->user(true); + vtxp->setConsumed("propagated"); + // Walk sources and mark them too + for (V3GraphEdge* edgep = vtxp->inBeginp(); edgep; edgep = edgep->inNextp()) { + GateEitherVertex* const fromVtxp = static_cast(edgep->fromp()); + markRecurse(fromVtxp); } - m_offset += nodep->dtypep()->width(); } - void visit(AstConcat* nodep) override { - UINFO(9, "CLK DECOMP Concat search (off = " << m_offset << ") - " << nodep << endl); - iterateConst(nodep->rhsp()); - iterateConst(nodep->lhsp()); + + // Mark all vertices that feed a consumed vertex + void mark() { + m_graph.userClearVertices(); + for (V3GraphVertex* vtxp = m_graph.verticesBeginp(); vtxp; vtxp = vtxp->verticesNextp()) { + GateEitherVertex* const eVtxp = static_cast(vtxp); + if (eVtxp->consumed()) markRecurse(eVtxp); + } + } + + // Remove unused logic + void remove() { + for (V3GraphVertex *vtxp = m_graph.verticesBeginp(), *nextp; vtxp; vtxp = nextp) { + nextp = vtxp->verticesNextp(); + if (GateLogicVertex* const lVtxp = vtxp->cast()) { + if (!lVtxp->consumed() && lVtxp->activep()) { // activep is nullptr under cfunc + AstNode* const nodep = lVtxp->nodep(); + UINFO(8, " Remove unconsumed " << nodep << endl); + nodep->unlinkFrBack(); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + lVtxp->unlinkDelete(&m_graph); + } + } + } + } + + GateUnused(GateGraph& graph) + : m_graph{graph} { + mark(); // Mark all used vertices + remove(); // Remove unused vertices } - //-------------------- - void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } public: - // CONSTRUCTORS - GateConcatVisitor() = default; - ~GateConcatVisitor() override = default; - // PUBLIC METHODS - bool concatOffset(AstConcat* concatp, AstVarScope* vscp, int& offsetr) { - m_vscp = vscp; - m_offset = 0; - m_found = false; - // Iterate - iterateConst(concatp); - UINFO(9, "CLK DECOMP Concat Offset (found = " << m_found << ") (" << m_found_offset - << ") - " << concatp << " : " << vscp - << endl); - offsetr = m_found_offset; - return m_found; - } + static void apply(GateGraph& graph) { GateUnused{graph}; } }; //###################################################################### -// Recurse through the graph, looking for clock vectors to bypass +// Pass entry point -class GateClkDecompState final { -public: - const int m_offset; - AstVarScope* const m_last_vsp; - GateClkDecompState(int offset, AstVarScope* vsp) - : m_offset{offset} - , m_last_vsp{vsp} {} - virtual ~GateClkDecompState() = default; -}; - -class GateClkDecompGraphVisitor final : public GateGraphBaseVisitor { -private: - // NODE STATE - // AstVarScope::user2p -> bool: already visited - int m_seen_clk_vectors = 0; - AstVarScope* m_clk_vsp = nullptr; - GateVarVertex* m_clk_vvertexp = nullptr; - GateConcatVisitor m_concat_visitor; - int m_total_seen_clk_vectors = 0; - int m_total_decomposed_clk_vectors = 0; - - VNUser visit(GateVarVertex* vvertexp, VNUser vu) override { - // Check that we haven't been here before - AstVarScope* const vsp = vvertexp->varScp(); - if (vsp->user2SetOnce()) return VNUser{0}; - UINFO(9, "CLK DECOMP Var - " << vvertexp << " : " << vsp << endl); - if (vsp->varp()->width() > 1) { - ++m_seen_clk_vectors; - ++m_total_seen_clk_vectors; - } - const GateClkDecompState* const currState = reinterpret_cast(vu.c()); - GateClkDecompState nextState{currState->m_offset, vsp}; - vvertexp->iterateCurrentOutEdges(*this, VNUser{&nextState}); - if (vsp->varp()->width() > 1) --m_seen_clk_vectors; - vsp->user2(false); - return VNUser{0}; // Unused - } - - VNUser visit(GateLogicVertex* lvertexp, VNUser vu) override { - const GateClkDecompState* const currState = reinterpret_cast(vu.c()); - int clk_offset = currState->m_offset; - if (const AstAssignW* const assignp = VN_CAST(lvertexp->nodep(), AssignW)) { - UINFO(9, "CLK DECOMP Logic (off = " << clk_offset << ") - " << lvertexp << " : " - << m_clk_vsp << endl); - // RHS - if (const AstSel* const rselp = VN_CAST(assignp->rhsp(), Sel)) { - if (VN_IS(rselp->lsbp(), Const) && VN_IS(rselp->widthp(), Const)) { - if (clk_offset < rselp->lsbConst() || clk_offset > rselp->msbConst()) { - UINFO(9, "CLK DECOMP Sel [ " << rselp->msbConst() << " : " - << rselp->lsbConst() << " ] dropped clock (" - << clk_offset << ")" << endl); - return VNUser{0}; - } - clk_offset -= rselp->lsbConst(); - } else { - return VNUser{0}; - } - } else if (AstConcat* const catp = VN_CAST(assignp->rhsp(), Concat)) { - UINFO(9, "CLK DECOMP Concat searching - " << assignp->lhsp() << endl); - int concat_offset; - if (!m_concat_visitor.concatOffset(catp, currState->m_last_vsp, - concat_offset /*ref*/)) { - return VNUser{0}; - } - clk_offset += concat_offset; - } else if (VN_IS(assignp->rhsp(), VarRef)) { - UINFO(9, "CLK DECOMP VarRef searching - " << assignp->lhsp() << endl); - } else { - return VNUser{0}; - } - // LHS - if (const AstSel* const lselp = VN_CAST(assignp->lhsp(), Sel)) { - if (VN_IS(lselp->lsbp(), Const) && VN_IS(lselp->widthp(), Const)) { - clk_offset += lselp->lsbConst(); - } else { - return VNUser{0}; - } - } else if (const AstVarRef* const vrp = VN_CAST(assignp->lhsp(), VarRef)) { - if (vrp->dtypep()->width() == 1 && m_seen_clk_vectors) { - if (clk_offset != 0) { - UINFO(9, "Should only make it here with clk_offset = 0" << endl); - return VNUser{0}; - } - UINFO(9, "CLK DECOMP Connecting - " << assignp->lhsp() << endl); - UINFO(9, " to - " << m_clk_vsp << endl); - AstNode* const rhsp = assignp->rhsp(); - rhsp->replaceWith(new AstVarRef{rhsp->fileline(), m_clk_vsp, VAccess::READ}); - while (V3GraphEdge* const edgep = lvertexp->inBeginp()) { - VL_DO_DANGLING(edgep->unlinkDelete(), edgep); - } - new V3GraphEdge{m_graphp, m_clk_vvertexp, lvertexp, 1}; - m_total_decomposed_clk_vectors++; - } - } else { - return VNUser{0}; - } - GateClkDecompState nextState{clk_offset, currState->m_last_vsp}; - return lvertexp->iterateCurrentOutEdges(*this, VNUser{&nextState}); - } - return VNUser{0}; - } - -public: - explicit GateClkDecompGraphVisitor(V3Graph* graphp) - : GateGraphBaseVisitor{graphp} {} - ~GateClkDecompGraphVisitor() override { - V3Stats::addStat("Optimizations, Clocker seen vectors", m_total_seen_clk_vectors); - V3Stats::addStat("Optimizations, Clocker decomposed vectors", - m_total_decomposed_clk_vectors); - } - void clkDecomp(GateVarVertex* vvertexp) { - UINFO(9, "CLK DECOMP Starting Var - " << vvertexp << endl); - m_seen_clk_vectors = 0; - m_clk_vsp = vvertexp->varScp(); - m_clk_vvertexp = vvertexp; - GateClkDecompState nextState{0, m_clk_vsp}; - vvertexp->accept(*this, VNUser{&nextState}); - } -}; - -void GateVisitor::decomposeClkVectors() { - UINFO(9, "Starting clock decomposition" << endl); - AstNode::user2ClearTree(); - GateClkDecompGraphVisitor decomposer{&m_graph}; - for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { - if (GateVarVertex* const vertp = itp->cast()) { - const AstVarScope* const vsp = vertp->varScp(); - if (vsp->varp()->attrClocker() == VVarAttrClocker::CLOCKER_YES) { - if (vsp->varp()->width() > 1) { - UINFO(9, "Clocker > 1 bit, not decomposing: " << vsp << endl); - } else { - UINFO(9, "CLK DECOMP - " << vertp << " : " << vsp << endl); - decomposer.clkDecomp(vertp); - } - } - } - } -} - -//###################################################################### -// Gate class functions - -void V3Gate::gateAll(AstNetlist* nodep) { +void V3Gate::gateAll(AstNetlist* netlistp) { UINFO(2, __FUNCTION__ << ": " << endl); - { const GateVisitor visitor{nodep}; } // Destruct before checking + + { + // Build the graph + std::unique_ptr graphp = GateBuildVisitor::apply(netlistp); + if (dumpGraphLevel() >= 3) graphp->dumpDotFilePrefixed("gate_graph"); + + // Warn, before loss of sync/async pointers + v3GateWarnSyncAsync(*graphp); + + // Decompose clock vectors -- need to do this before removing redundant edges + GateClkDecomp::apply(*graphp); + if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_decomp"); + + // Remove redundant edges. Edge weighs are added, so a variable read twice by + // the same logic block will have and edge to the logic block with weight 2 + graphp->removeRedundantEdgesSum(&V3GraphEdge::followAlwaysTrue); + if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_simp"); + + // Inline variables + GateInline::apply(*graphp); + if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_inline"); + + // Remove redundant logic + if (v3Global.opt.fDedupe()) { + GateDedupe::apply(*graphp); + if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_dedup"); + } + + // Merge assignments + if (v3Global.opt.fAssemble()) { + GateMergeAssignments::apply(*graphp); + if (dumpGraphLevel() >= 6) graphp->dumpDotFilePrefixed("gate_merge"); + } + + // Remove unused logic + GateUnused::apply(*graphp); + if (dumpGraphLevel() >= 3) graphp->dumpDotFilePrefixed("gate_final"); + } + V3Global::dumpCheckGlobalTree("gate", 0, dumpTreeLevel() >= 3); } diff --git a/src/V3Gate.h b/src/V3Gate.h index f30c6f9a4..9314c3cb7 100644 --- a/src/V3Gate.h +++ b/src/V3Gate.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Global.cpp b/src/V3Global.cpp index 454787fe9..5e6d767b9 100644 --- a/src/V3Global.cpp +++ b/src/V3Global.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -54,7 +54,7 @@ void V3Global::readFiles() { if (v3Global.opt.std()) { parser.parseFile(new FileLine{V3Options::getStdPackagePath()}, V3Options::getStdPackagePath(), false, - "Cannot find verilated_std.sv containing built-in std:: definitions:"); + "Cannot find verilated_std.sv containing built-in std:: definitions: "); } // Read top module @@ -106,9 +106,9 @@ string V3Global::digitsFilename(int number) { void V3Global::dumpCheckGlobalTree(const string& stagename, int newNumber, bool doDump) { const string treeFilename = v3Global.debugFilename(stagename + ".tree", newNumber); - v3Global.rootp()->dumpTreeFile(treeFilename, false, doDump); + v3Global.rootp()->dumpTreeFile(treeFilename, doDump); if (v3Global.opt.dumpTreeDot()) { - v3Global.rootp()->dumpTreeDotFile(treeFilename + ".dot", false, doDump); + v3Global.rootp()->dumpTreeDotFile(treeFilename + ".dot", doDump); } if (v3Global.opt.stats()) V3Stats::statsStage(stagename); } diff --git a/src/V3Global.h b/src/V3Global.h index 036a5515e..5bbe63519 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -112,6 +112,7 @@ class V3Global final { bool m_dpi = false; // Need __Dpi include files bool m_hasEvents = false; // Design uses SystemVerilog named events bool m_hasClasses = false; // Design uses SystemVerilog classes + bool m_hasVirtIfaces = false; // Design uses virtual interfaces bool m_usesProbDist = false; // Uses $dist_* bool m_usesStdPackage = false; // Design uses the std package bool m_usesTiming = false; // Design uses timing constructs @@ -162,6 +163,8 @@ public: void setHasEvents() { m_hasEvents = true; } bool hasClasses() const { return m_hasClasses; } void setHasClasses() { m_hasClasses = true; } + bool hasVirtIfaces() const { return m_hasVirtIfaces; } + void setHasVirtIfaces() { m_hasVirtIfaces = true; } bool usesProbDist() const { return m_usesProbDist; } void setUsesProbDist() { m_usesProbDist = true; } bool usesStdPackage() const { return m_usesStdPackage; } diff --git a/src/V3Graph.cpp b/src/V3Graph.cpp index f77f1d056..8b7c9cf08 100644 --- a/src/V3Graph.cpp +++ b/src/V3Graph.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -294,6 +294,12 @@ void V3Graph::dumpEdge(std::ostream& os, const V3GraphVertex* vertexp, os << '\n'; } } +void V3Graph::dumpEdges(std::ostream& os, const V3GraphVertex* vertexp) const { + for (const V3GraphEdge* edgep = vertexp->inBeginp(); edgep; edgep = edgep->inNextp()) + dumpEdge(os, vertexp, edgep); + for (const V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep = edgep->outNextp()) + dumpEdge(os, vertexp, edgep); +} void V3Graph::dumpDotFilePrefixed(const string& nameComment, bool colorAsSubgraph) const { dumpDotFile(v3Global.debugFilename(nameComment) + ".dot", colorAsSubgraph); @@ -410,5 +416,5 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) const { *logp << "}\n"; logp->close(); - cout << "dot -Tpdf -o ~/a.pdf " << filename << endl; + cout << "dot -Tpdf -o ~/a.pdf " << filename << "\n"; } diff --git a/src/V3Graph.h b/src/V3Graph.h index c2973cae7..af0c965fe 100644 --- a/src/V3Graph.h +++ b/src/V3Graph.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -80,7 +80,6 @@ constexpr bool operator==(GraphWay::en lhs, const GraphWay& rhs) { return lhs == //============================================================================ class V3Graph VL_NOT_FINAL { -private: // MEMBERS V3List m_vertices; // All vertices @@ -180,6 +179,7 @@ public: bool colorAsSubgraph = false) const VL_MT_DISABLED; void dumpDotFilePrefixedAlways(const string& nameComment, bool colorAsSubgraph = false) const VL_MT_DISABLED; + void dumpEdges(std::ostream& os, const V3GraphVertex* vertexp) const VL_MT_DISABLED; static void selfTest() VL_MT_DISABLED; // CALLBACKS diff --git a/src/V3GraphAcyc.cpp b/src/V3GraphAcyc.cpp index 4bf46a495..302b109ae 100644 --- a/src/V3GraphAcyc.cpp +++ b/src/V3GraphAcyc.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -92,7 +92,6 @@ struct GraphAcycEdgeCmp { // CLASSES class GraphAcyc final { -private: using OrigEdgeList = std::list; // List of orig edges, see also GraphAcycEdge's decl // GRAPH USERS diff --git a/src/V3GraphAlg.cpp b/src/V3GraphAlg.cpp index 43edcb9e0..c64751d9d 100644 --- a/src/V3GraphAlg.cpp +++ b/src/V3GraphAlg.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -136,7 +136,6 @@ void V3Graph::removeTransitiveEdges() { GraphAlgRemoveTransitiveEdges{this}.go() // Changes color() class GraphAlgWeakly final : GraphAlg<> { -private: void main() { // Initialize state m_graphp->clearColors(); @@ -178,7 +177,6 @@ void V3Graph::weaklyConnected(V3EdgeFuncP edgeFuncp) { GraphAlgWeakly{this, edge // Changes user() and color() class GraphAlgStrongly final : GraphAlg<> { -private: uint32_t m_currentDfs = 0; // DFS count std::vector m_callTrace; // List of everything we hit processing so far @@ -269,7 +267,6 @@ void V3Graph::stronglyConnected(V3EdgeFuncP edgeFuncp) { GraphAlgStrongly{this, // Changes user() and rank() class GraphAlgRank final : GraphAlg<> { -private: void main() { // Rank each vertex, ignoring cutable edges // Vertex::m_user begin: 1 indicates processing, 2 indicates completed @@ -325,7 +322,6 @@ void V3Graph::rank(V3EdgeFuncP edgeFuncp) { GraphAlgRank{this, edgeFuncp}; } // Changes user() class GraphAlgRLoops final : GraphAlg<> { -private: std::vector m_callTrace; // List of everything we hit processing so far bool m_done = false; // Exit algorithm @@ -379,7 +375,6 @@ void V3Graph::reportLoops(V3EdgeFuncP edgeFuncp, V3GraphVertex* vertexp) { // Changes user() class GraphAlgSubtrees final : GraphAlg<> { -private: V3Graph* const m_loopGraphp; //! Iterate through all connected nodes of a graph with a loop or loops. diff --git a/src/V3GraphAlg.h b/src/V3GraphAlg.h index e93f37949..63fec5691 100644 --- a/src/V3GraphAlg.h +++ b/src/V3GraphAlg.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3GraphPathChecker.cpp b/src/V3GraphPathChecker.cpp index 21cd1493c..b9157c647 100644 --- a/src/V3GraphPathChecker.cpp +++ b/src/V3GraphPathChecker.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3GraphPathChecker.h b/src/V3GraphPathChecker.h index c4326d129..124feedc8 100644 --- a/src/V3GraphPathChecker.h +++ b/src/V3GraphPathChecker.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3GraphStream.h b/src/V3GraphStream.h index a2cdbd888..0e6391216 100644 --- a/src/V3GraphStream.h +++ b/src/V3GraphStream.h @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -42,7 +42,6 @@ template class GraphStream final { -private: // TYPES class VxHolder final { public: diff --git a/src/V3GraphTest.cpp b/src/V3GraphTest.cpp index 1635bfc6a..293de138e 100644 --- a/src/V3GraphTest.cpp +++ b/src/V3GraphTest.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -149,22 +149,22 @@ class V3GraphTestVars final : public V3GraphTest { public: string name() override { return "vars"; } void runTest() override { - V3Graph* gp = &m_graph; + V3Graph* const gp = &m_graph; - V3GraphTestVertex* clk = new V3GraphTestVarVertex{gp, "$clk"}; + V3GraphTestVertex* const clk = new V3GraphTestVarVertex{gp, "$clk"}; - V3GraphTestVertex* a = new V3GraphTestVarVertex{gp, "$a"}; - V3GraphTestVertex* a_dly = new V3GraphTestVarVertex{gp, "$a_dly"}; - V3GraphTestVertex* a_dlyblk = new V3GraphTestVarVertex{gp, "$a_dlyblk"}; - V3GraphTestVertex* b = new V3GraphTestVarVertex{gp, "$b"}; - V3GraphTestVertex* b_dly = new V3GraphTestVarVertex{gp, "$b_dly"}; - V3GraphTestVertex* b_dlyblk = new V3GraphTestVarVertex{gp, "$b_dlyblk"}; - V3GraphTestVertex* c = new V3GraphTestVarVertex{gp, "$c"}; - V3GraphTestVertex* i = new V3GraphTestVarVertex{gp, "$i"}; + V3GraphTestVertex* const a = new V3GraphTestVarVertex{gp, "$a"}; + V3GraphTestVertex* const a_dly = new V3GraphTestVarVertex{gp, "$a_dly"}; + V3GraphTestVertex* const a_dlyblk = new V3GraphTestVarVertex{gp, "$a_dlyblk"}; + V3GraphTestVertex* const b = new V3GraphTestVarVertex{gp, "$b"}; + V3GraphTestVertex* const b_dly = new V3GraphTestVarVertex{gp, "$b_dly"}; + V3GraphTestVertex* const b_dlyblk = new V3GraphTestVarVertex{gp, "$b_dlyblk"}; + V3GraphTestVertex* const c = new V3GraphTestVarVertex{gp, "$c"}; + V3GraphTestVertex* const i = new V3GraphTestVarVertex{gp, "$i"}; - V3GraphTestVertex* ap = new V3GraphTestVarVertex{gp, "$a_pre"}; - V3GraphTestVertex* bp = new V3GraphTestVarVertex{gp, "$b_pre"}; - V3GraphTestVertex* cp = new V3GraphTestVarVertex{gp, "$c_pre"}; + V3GraphTestVertex* const ap = new V3GraphTestVarVertex{gp, "$a_pre"}; + V3GraphTestVertex* const bp = new V3GraphTestVarVertex{gp, "$b_pre"}; + V3GraphTestVertex* const cp = new V3GraphTestVarVertex{gp, "$c_pre"}; V3GraphTestVertex* n; @@ -185,7 +185,7 @@ public: new V3GraphEdge{gp, n, i, 2}; } - V3GraphTestVertex* posedge = n = new V3GraphTestVertex{gp, "*posedge clk*"}; + V3GraphTestVertex* const posedge = n = new V3GraphTestVertex{gp, "*posedge clk*"}; { new V3GraphEdge{gp, clk, n, 2}; } // AssignPre's VarRefs on LHS: generate special BLK @@ -258,6 +258,9 @@ public: gp->acyclic(&V3GraphEdge::followAlwaysTrue); gp->order(); + // Test debug function + gp->dumpEdges(std::cout, ap); + dumpSelf(); } }; diff --git a/src/V3Hash.cpp b/src/V3Hash.cpp index bff44cdf1..cb3d5468f 100644 --- a/src/V3Hash.cpp +++ b/src/V3Hash.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Hash.h b/src/V3Hash.h index 7e75045ef..1aa39b292 100644 --- a/src/V3Hash.h +++ b/src/V3Hash.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Hasher.cpp b/src/V3Hasher.cpp index e58dce546..382b4f0d5 100644 --- a/src/V3Hasher.cpp +++ b/src/V3Hasher.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -26,7 +26,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Visitor that computes node hashes class HasherVisitor final : public VNVisitorConst { -private: // NODE STATE // AstNode::user4() -> V3Hash. Hash value of this node (hash of 0 is illegal) // VNUser4InUse in V3Hasher.h @@ -91,56 +90,56 @@ private: //------------------------------------------------------------ // AstNodeDType void visit(AstNodeArrayDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { iterateConstNull(nodep->virtRefDTypep()); m_hash += nodep->left(); m_hash += nodep->right(); }); } void visit(AstNodeUOrStructDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, false, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, false, [this, nodep]() { // m_hash += nodep->uniqueNum(); }); } void visit(AstParamTypeDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->name(); m_hash += nodep->varType(); }); } void visit(AstMemberDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstDefImplicitDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->uniqueNum(); }); } void visit(AstAssocArrayDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { iterateConstNull(nodep->virtRefDTypep()); iterateConstNull(nodep->virtRefDType2p()); }); } void visit(AstDynArrayDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->virtRefDTypep()); }); } void visit(AstUnsizedArrayDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->virtRefDTypep()); }); } void visit(AstWildcardArrayDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->virtRefDTypep()); }); } void visit(AstBasicDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->keyword(); m_hash += nodep->numeric(); m_hash += nodep->nrange().left(); @@ -148,45 +147,45 @@ private: }); } void visit(AstCDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstConstDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->virtRefDTypep()); }); } void visit(AstClassRefDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->classp()); }); } void visit(AstIfaceRefDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->cellp()); }); } void visit(AstQueueDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->virtRefDTypep()); }); } void visit(AstRefDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->name(); iterateConstNull(nodep->typedefp()); iterateConstNull(nodep->refDTypep()); }); } void visit(AstStreamDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, []() {}); } void visit(AstVoidDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, []() {}); } void visit(AstEnumDType* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, false, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, false, [this, nodep]() { // m_hash += nodep->uniqueNum(); }); } @@ -194,23 +193,23 @@ private: //------------------------------------------------------------ // AstNodeExpr void visit(AstNodeExpr* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstConst* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->num().toHash(); }); } void visit(AstNullCheck* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstCCast* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->size(); }); } void visit(AstVarRef* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { if (nodep->varScopep()) { iterateConstNull(nodep->varScopep()); } else { @@ -220,28 +219,28 @@ private: }); } void visit(AstVarXRef* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { iterateConstNull(nodep->varp()); m_hash += nodep->dotted(); }); } void visit(AstMemberSel* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstFScanF* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->text(); }); } void visit(AstSScanF* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->text(); }); } void visit(AstAddrOfCFunc* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->funcp()); }); } @@ -249,64 +248,64 @@ private: //------------------------------------------------------------ // AstNodeStmt void visit(AstNodeStmt* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, []() {}); } void visit(AstNodeText* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->text(); }); } void visit(AstNodeCCall* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->funcp()); }); } void visit(AstNodeFTaskRef* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { iterateConstNull(nodep->taskp()); iterateConstNull(nodep->classOrPackagep()); }); } void visit(AstCMethodHard* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstCAwait* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->sensesp()); }); } void visit(AstCLocalScope* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstCoverInc* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->declp()); }); } void visit(AstDisplay* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->displayType(); }); } void visit(AstMonitorOff* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->off(); }); } void visit(AstJumpGo* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->labelp()); }); } void visit(AstTraceInc* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->declp()); }); } void visit(AstNodeCoverOrAssert* nodep) override { - m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, false, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } @@ -314,103 +313,104 @@ private: //------------------------------------------------------------ // AstNode direct descendants void visit(AstNodeRange* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstNodeModule* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, false, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, false, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstNodePreSel* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstClassExtends* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstSelLoopVars* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstDefParam* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstArg* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstParseRef* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->expect(); m_hash += nodep->name(); }); } void visit(AstClassOrPackageRef* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->classOrPackageNodep()); }); } void visit(AstSenItem* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->edgeType(); }); } void visit(AstSenTree* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstSFormatF* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->text(); }); } void visit(AstElabDisplay* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->displayType(); }); } void visit(AstInitItem* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstInitArray* nodep) override { if (const AstAssocArrayDType* const dtypep = VN_CAST(nodep->dtypep(), AssocArrayDType)) { if (nodep->defaultp()) { m_hash - += hashNodeAndIterate(nodep->defaultp(), HASH_DTYPE, HASH_CHILDREN, [=]() {}); + += hashNodeAndIterate(nodep->defaultp(), HASH_DTYPE, HASH_CHILDREN, []() {}); } const auto& mapr = nodep->map(); for (const auto& itr : mapr) { // mapr is sorted, so hash should get stable results m_hash += itr.first; - m_hash += hashNodeAndIterate(itr.second, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(itr.second, HASH_DTYPE, HASH_CHILDREN, []() {}); } } else if (const AstUnpackArrayDType* const dtypep = VN_CAST(nodep->dtypep(), UnpackArrayDType)) { // Hash unpacked array initializers by value, as the order of initializer nodes does // not matter, and we want semantically equivalent initializers to map to the same // hash. - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, /* hashChildren: */ !dtypep, [=]() { - if (dtypep) { - const uint32_t size = dtypep->elementsConst(); - for (uint32_t n = 0; n < size; ++n) { // - iterateConstNull(nodep->getIndexDefaultedValuep(n)); + m_hash += hashNodeAndIterate( + nodep, HASH_DTYPE, /* hashChildren: */ !dtypep, [this, nodep, dtypep]() { + if (dtypep) { + const uint32_t size = dtypep->elementsConst(); + for (uint32_t n = 0; n < size; ++n) { // + iterateConstNull(nodep->getIndexDefaultedValuep(n)); + } } - } - }); + }); } } void visit(AstPragma* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->pragType(); }); } void visit(AstAttrOf* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->attrType(); }); } void visit(AstNodeFile* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstCFunc* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // // We might be in a recursive function, if so on *second* call // here we need to break what would be an infinite loop. nodep->user4(V3Hash{1}.value()); // Set this "first" call @@ -421,90 +421,90 @@ private: }); } void visit(AstVar* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->name(); m_hash += nodep->varType(); }); } void visit(AstScope* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, false, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, false, [this, nodep]() { m_hash += nodep->name(); iterateConstNull(nodep->aboveScopep()); }); } void visit(AstVarScope* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { iterateConstNull(nodep->varp()); iterateConstNull(nodep->scopep()); }); } void visit(AstEnumItem* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstTypedef* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstTypedefFwd* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstActive* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // iterateConstNull(nodep->sensesp()); }); } void visit(AstCell* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->name(); iterateConstNull(nodep->modp()); }); } void visit(AstCellInline* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->name(); iterateConstNull(nodep->scopep()); }); } void visit(AstNodeFTask* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstModport* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstModportVarRef* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->name(); iterateConstNull(nodep->varp()); }); } void visit(AstModportFTaskRef* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->name(); iterateConstNull(nodep->ftaskp()); }); } void visit(AstMTaskBody* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstNodeProcedure* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {}); + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, []() {}); } void visit(AstNodeBlock* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { // + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { // m_hash += nodep->name(); }); } void visit(AstPin* nodep) override { - m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() { + m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [this, nodep]() { m_hash += nodep->name(); m_hash += nodep->pinNum(); }); diff --git a/src/V3Hasher.h b/src/V3Hasher.h index 6c24cfe0d..221740b04 100644 --- a/src/V3Hasher.h +++ b/src/V3Hasher.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3HierBlock.cpp b/src/V3HierBlock.cpp index 294613e18..cffa77359 100644 --- a/src/V3HierBlock.cpp +++ b/src/V3HierBlock.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -90,7 +90,7 @@ VL_DEFINE_DEBUG_FUNCTIONS; static string V3HierCommandArgsFileName(const string& prefix, bool forCMake) { return v3Global.opt.makeDir() + "/" + prefix - + (forCMake ? "_hierCMakeArgs.f" : "_hierMkArgs.f"); + + (forCMake ? "__hierCMakeArgs.f" : "__hierMkArgs.f"); } static void V3HierWriteCommonInputs(const V3HierBlock* hblockp, std::ostream* of, bool forCMake) { @@ -236,7 +236,7 @@ string V3HierBlock::commandArgsFileName(bool forCMake) const { //###################################################################### // Collect how hierarchical blocks are used -class HierBlockUsageCollectVisitor final : public VNVisitor { +class HierBlockUsageCollectVisitor final : public VNVisitorConst { // NODE STATE // AstNode::user1() -> bool. Processed const VNUser1InUse m_inuser1; @@ -266,7 +266,7 @@ class HierBlockUsageCollectVisitor final : public VNVisitor { } prevGParams.swap(m_gparams); - iterateChildren(nodep); + iterateChildrenConst(nodep); if (nodep->hierBlock()) { m_planp->add(nodep, m_gparams); @@ -280,7 +280,7 @@ class HierBlockUsageCollectVisitor final : public VNVisitor { // Visit used module here to know that the module is hier_block or not. // This visitor behaves almost depth first search if (AstModule* const modp = VN_CAST(nodep->modp(), Module)) { - iterate(modp); + iterateConst(modp); m_referred.insert(modp); } // Nothing to do for interface because hierarchical block does not exist @@ -294,12 +294,12 @@ class HierBlockUsageCollectVisitor final : public VNVisitor { } void visit(AstNodeExpr*) override {} // Accelerate - void visit(AstNode* nodep) override { iterateChildren(nodep); } + void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } public: HierBlockUsageCollectVisitor(V3HierBlockPlan* planp, AstNetlist* netlist) : m_planp{planp} { - iterateChildren(netlist); + iterateChildrenConst(netlist); } }; diff --git a/src/V3HierBlock.h b/src/V3HierBlock.h index 33310209f..00d2652a6 100644 --- a/src/V3HierBlock.h +++ b/src/V3HierBlock.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index ec3b52149..90d6bd304 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -59,7 +59,6 @@ using ModuleStateUser1Allocator = AstUser1Allocator; // Visitor that determines which modules will be inlined class InlineMarkVisitor final : public VNVisitor { -private: // NODE STATE // Output // AstNodeModule::user1() // OUTPUT: ModuleState instance (via m_moduleState) @@ -245,7 +244,6 @@ public: // After cell is cloned, relink the new module's contents class InlineRelinkVisitor final : public VNVisitor { -private: // NODE STATE // Input: // See InlineVisitor @@ -285,7 +283,7 @@ private: // user2p is either a const or a var. FileLine* const flp = nodep->fileline(); AstConst* const exprconstp = VN_CAST(nodep->user2p(), Const); - const AstVarRef* const exprvarrefp = VN_CAST(nodep->user2p(), VarRef); + AstVarRef* exprvarrefp = VN_CAST(nodep->user2p(), VarRef); UINFO(8, "connectto: " << nodep->user2p() << endl); UASSERT_OBJ(exprconstp || exprvarrefp, nodep, "Unknown interconnect type; pinReconnectSimple should have cleared up"); @@ -298,30 +296,32 @@ private: // remove the change detection on the output variable. UINFO(9, "public pin assign: " << exprvarrefp << endl); UASSERT_OBJ(!nodep->isNonOutput(), nodep, "Outputs only - inputs use AssignAlias"); - m_modp->addStmtsp( - new AstAssignW{flp, new AstVarRef{flp, exprvarrefp->varp(), VAccess::WRITE}, - new AstVarRef{flp, nodep, VAccess::READ}}); + m_modp->addStmtsp(new AstAssignW{flp, exprvarrefp->cloneTree(false), + new AstVarRef{flp, nodep, VAccess::READ}}); } else if (nodep->isSigPublic() && VN_IS(nodep->dtypep(), UnpackArrayDType)) { // Public variable at this end and it is an unpacked array. We need to assign // instead of aliased, because otherwise it will pass V3Slice and invalid // code will be emitted. UINFO(9, "assign to public and unpacked: " << nodep << endl); + exprvarrefp = exprvarrefp->cloneTree(false); + exprvarrefp->access(VAccess::READ); m_modp->addStmtsp( - new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE}, - new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}}); + new AstAssignW{flp, new AstVarRef{flp, nodep, VAccess::WRITE}, exprvarrefp}); } else if (nodep->isIfaceRef()) { - m_modp->addStmtsp( - new AstAssignVarScope{flp, new AstVarRef{flp, nodep, VAccess::WRITE}, - new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}}); + exprvarrefp = exprvarrefp->cloneTree(false); + exprvarrefp->access(VAccess::READ); + m_modp->addStmtsp(new AstAssignVarScope{ + flp, new AstVarRef{flp, nodep, VAccess::WRITE}, exprvarrefp}); FileLine* const flbp = exprvarrefp->varp()->fileline(); flp->modifyStateInherit(flbp); flbp->modifyStateInherit(flp); } else { // Do to inlining child's variable now within the same // module, so a AstVarRef not AstVarXRef below - m_modp->addStmtsp( - new AstAssignAlias{flp, new AstVarRef{flp, nodep, VAccess::WRITE}, - new AstVarRef{flp, exprvarrefp->varp(), VAccess::READ}}); + exprvarrefp = exprvarrefp->cloneTree(false); + exprvarrefp->access(VAccess::READ); + m_modp->addStmtsp(new AstAssignAlias{ + flp, new AstVarRef{flp, nodep, VAccess::WRITE}, exprvarrefp}); FileLine* const flbp = exprvarrefp->varp()->fileline(); flp->modifyStateInherit(flbp); flbp->modifyStateInherit(flp); @@ -378,6 +378,7 @@ private: return; } else if (const AstVarRef* const vrefp = VN_CAST(varp->user2p(), VarRef)) { nodep->varp(vrefp->varp()); + nodep->classOrPackagep(vrefp->classOrPackagep()); } else { nodep->v3fatalSrc("Null connection?"); } @@ -451,7 +452,6 @@ public: // Inline state, as a visitor of each AstNode class InlineVisitor final : public VNVisitor { -private: // NODE STATE // Cleared entire netlist // AstIfaceRefDType::user1() // Whether the cell pointed to by this diff --git a/src/V3Inline.h b/src/V3Inline.h index 1f347b139..be83e68f8 100644 --- a/src/V3Inline.h +++ b/src/V3Inline.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index fa5b2da3c..16a6461df 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,7 +33,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Inst state, as a visitor of each AstNode class InstVisitor final : public VNVisitor { -private: // NODE STATE // Cleared each Cell: // AstPin::user1p() -> bool. True if created assignment already @@ -362,11 +361,11 @@ private: } // end expanding ranged cell else if (AstArraySel* const arrselp = VN_CAST(nodep->exprp(), ArraySel)) { if (const AstUnpackArrayDType* const arrp - = VN_CAST(arrselp->lhsp()->dtypep(), UnpackArrayDType)) { + = VN_CAST(arrselp->fromp()->dtypep(), UnpackArrayDType)) { if (!VN_IS(arrp->subDTypep(), IfaceRefDType)) return; // Interface pin attaches to one element of arrayed interface - V3Const::constifyParamsEdit(arrselp->rhsp()); - const AstConst* const constp = VN_CAST(arrselp->rhsp(), Const); + V3Const::constifyParamsEdit(arrselp->bitp()); + const AstConst* const constp = VN_CAST(arrselp->bitp(), Const); if (!constp) { nodep->v3warn( E_UNSUPPORTED, @@ -374,9 +373,9 @@ private: return; } const string index = AstNode::encodeNumber(constp->toSInt()); - if (VN_IS(arrselp->lhsp(), SliceSel)) - arrselp->lhsp()->v3error("Unsupported: interface slices"); - const AstVarRef* const varrefp = VN_CAST(arrselp->lhsp(), VarRef); + if (VN_IS(arrselp->fromp(), SliceSel)) + arrselp->fromp()->v3error("Unsupported: interface slices"); + const AstVarRef* const varrefp = VN_CAST(arrselp->fromp(), VarRef); UASSERT_OBJ(varrefp, arrselp, "No interface varref under array"); AstVarXRef* const newp = new AstVarXRef{ nodep->fileline(), varrefp->name() + "__BRA__" + index + "__KET__", "", @@ -482,7 +481,6 @@ public: // Inst static function class InstStatic final { -private: InstStatic() = default; // Static class static AstNodeExpr* extendOrSel(FileLine* fl, AstNodeExpr* rhsp, AstNode* cmpWidthp) { diff --git a/src/V3Inst.h b/src/V3Inst.h index 8baccb465..dc97bfde3 100644 --- a/src/V3Inst.h +++ b/src/V3Inst.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3InstrCount.cpp b/src/V3InstrCount.cpp index 1881d2fff..704df1abc 100644 --- a/src/V3InstrCount.cpp +++ b/src/V3InstrCount.cpp @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,7 +30,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; /// whichever is larger. We know we won't run both. class InstrCountVisitor final : public VNVisitorConst { -private: // NODE STATE // AstNode::user1() -> bool. Processed if assertNoDups // AstNode::user2() -> int. Path cost + 1, 0 means don't dump @@ -48,7 +47,6 @@ private: // TYPES // Little class to cleanly call startVisitBase/endVisitBase class VisitBase final { - private: // MEMBERS uint32_t m_savedCount; AstNode* const m_nodep; @@ -287,7 +285,6 @@ private: // Iterate the graph printing the critical path marked by previous visitation class InstrCountDumpVisitor final : public VNVisitorConst { -private: // NODE STATE // AstNode::user2() -> int. Path cost, 0 means don't dump diff --git a/src/V3InstrCount.h b/src/V3InstrCount.h index d50da1708..614f54e88 100644 --- a/src/V3InstrCount.h +++ b/src/V3InstrCount.h @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Interface.cpp b/src/V3Interface.cpp index 005fdc57b..4f5cfcc9c 100644 --- a/src/V3Interface.cpp +++ b/src/V3Interface.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,7 +33,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Track interface references under the Cell they reference class InlineIntfRefVisitor final : public VNVisitor { -private: // NODE STATE // AstVar::user1p() // AstCell which this Var points to const VNUser1InUse m_inuser1; diff --git a/src/V3Interface.h b/src/V3Interface.h index 08bea3574..05ed4678b 100644 --- a/src/V3Interface.h +++ b/src/V3Interface.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LangCode.h b/src/V3LangCode.h index 3835825d9..6403bec25 100644 --- a/src/V3LangCode.h +++ b/src/V3LangCode.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LanguageWords.h b/src/V3LanguageWords.h index 2717b90d6..3da1019cb 100644 --- a/src/V3LanguageWords.h +++ b/src/V3LanguageWords.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Life.cpp b/src/V3Life.cpp index 821365623..48d4f107e 100644 --- a/src/V3Life.cpp +++ b/src/V3Life.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -137,7 +137,7 @@ public: void checkRemoveAssign(const LifeMap::iterator& it) { const AstVar* const varp = it->first->varp(); LifeVarEntry* const entp = &(it->second); - if (!varp->isSigPublic() && !varp->isUsedVirtIface()) { + if (!varp->isSigPublic() && !varp->sensIfacep()) { // Rather than track what sigs AstUCFunc/AstUCStmt may change, // we just don't optimize any public sigs // Check the var entry, and remove if appropriate @@ -178,7 +178,7 @@ public: const auto pair = m_map.emplace(nodep, LifeVarEntry::CONSUMED{}); if (!pair.second) { if (AstConst* const constp = pair.first->second.constNodep()) { - if (!varrefp->varp()->isSigPublic() && !varrefp->varp()->isUsedVirtIface()) { + if (!varrefp->varp()->isSigPublic() && !varrefp->varp()->sensIfacep()) { // Aha, variable is constant; substitute in. // We'll later constant propagate UINFO(4, " replaceconst: " << varrefp << endl); @@ -258,7 +258,6 @@ public: // Life state, as a visitor of each AstNode class LifeVisitor final : public VNVisitor { -private: // STATE LifeState* const m_statep; // Current state bool m_sideEffect = false; // Side effects discovered in assign RHS @@ -301,6 +300,7 @@ private: } // Collect any used variables first, as lhs may also be on rhs // Similar code in V3Dead + VL_RESTORER(m_sideEffect); m_sideEffect = false; m_lifep->clearReplaced(); iterateAndNextNull(nodep->rhsp()); @@ -407,7 +407,9 @@ private: iterateChildren(nodep); // Enter the function and trace it // else is non-inline or public function we optimize separately - if (!nodep->funcp()->entryPoint()) { + if (nodep->funcp()->entryPoint()) { + setNoopt(); + } else { m_tracingCall = true; iterate(nodep->funcp()); } @@ -416,6 +418,7 @@ private: // UINFO(4, " CFUNC " << nodep << endl); if (!m_tracingCall && !nodep->entryPoint()) return; m_tracingCall = false; + if (nodep->recursive()) setNoopt(); if (nodep->dpiImportPrototype() && !nodep->dpiPure()) { m_sideEffect = true; // If appears on assign RHS, don't ever delete the assignment } diff --git a/src/V3Life.h b/src/V3Life.h index 024f4e7c8..a80859a6b 100644 --- a/src/V3Life.h +++ b/src/V3Life.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LifePost.cpp b/src/V3LifePost.cpp index 6692a3ebf..07f6d0eeb 100644 --- a/src/V3LifePost.cpp +++ b/src/V3LifePost.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -41,7 +41,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // LifePost class functions class LifePostElimVisitor final : public VNVisitor { -private: bool m_tracingCall = false; // Iterating into a CCall to a CFunc // NODE STATE @@ -127,7 +126,6 @@ struct LifePostLocation { // LifePost delay elimination class LifePostDlyVisitor final : public VNVisitor { -private: // NODE STATE // AstVarScope::user1() -> bool: referenced outside _eval__nba // AstVarScope::user4() -> AstVarScope*: Passed to LifePostElim to substitute this var @@ -252,8 +250,6 @@ private: // VISITORS void visit(AstTopScope* nodep) override { - AstNode::user4ClearTree(); // user4p() used on entire tree - // First, build maps of every location (mtask and sequence // within the mtask) where each varscope is read, and written. iterateChildren(nodep); diff --git a/src/V3LifePost.h b/src/V3LifePost.h index 01042ce38..cf48e2e02 100644 --- a/src/V3LifePost.h +++ b/src/V3LifePost.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp index 60647c7d2..7c259806c 100644 --- a/src/V3LinkCells.cpp +++ b/src/V3LinkCells.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -92,7 +92,6 @@ void LinkCellsGraph::loopsMessageCb(V3GraphVertex* vertexp) { // Link state, as a visitor of each AstNode class LinkCellsVisitor final : public VNVisitor { -private: // NODE STATE // Entire netlist: // AstNodeModule::user1p() // V3GraphVertex* Vertex describing this module @@ -160,7 +159,6 @@ private: // VISITs void visit(AstNetlist* nodep) override { - AstNode::user1ClearTree(); readModNames(); iterateChildren(nodep); // Find levels in graph @@ -241,6 +239,11 @@ private: nodep->v3error("Non-interface used as an interface: " << nodep->prettyNameQ()); } } + iterateChildren(nodep); + for (AstPin* pinp = nodep->paramsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { + pinp->param(true); + if (pinp->name() == "") pinp->name("__paramNumber" + cvtToStr(pinp->pinNum())); + } // Note cannot do modport resolution here; modports are allowed underneath generates } diff --git a/src/V3LinkCells.h b/src/V3LinkCells.h index dbaecd2be..639a71eff 100644 --- a/src/V3LinkCells.h +++ b/src/V3LinkCells.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index b7c04c4b5..ce262adc9 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -116,7 +116,6 @@ public: // LinkDot state, as a visitor of each AstNode class LinkDotState final { -private: // NODE STATE // Cleared on Netlist // AstNodeModule::user1p() // VSymEnt*. Last symbol created for this node @@ -235,6 +234,8 @@ public: } } else if (VN_IS(nodep, Cell)) { return "instance"; + } else if (VN_IS(nodep, Constraint)) { + return "constraint"; } else if (VN_IS(nodep, Task)) { return "task"; } else if (VN_IS(nodep, Func)) { @@ -918,6 +919,7 @@ class LinkDotFindVisitor final : public VNVisitor { UINFO(5, "Module not under any CELL or top - dead module: " << nodep << endl); } } + void visit(AstClass* nodep) override { UASSERT_OBJ(m_curSymp, nodep, "Class not under module/package/$unit"); UINFO(8, " " << nodep << endl); @@ -1188,6 +1190,11 @@ class LinkDotFindVisitor final : public VNVisitor { nodep->varp(newvarp); iterate(nodep->exprp()); } + void visit(AstConstraint* nodep) override { + VL_RESTORER(m_curSymp); + m_curSymp = m_statep->insertBlock(m_curSymp, nodep->name(), nodep, m_classOrPackagep); + iterateChildren(nodep); + } void visit(AstVar* nodep) override { // Var: Remember its name for later resolution UASSERT_OBJ(m_curSymp && m_modSymp, nodep, "Var not under module?"); @@ -1429,7 +1436,7 @@ class LinkDotFindVisitor final : public VNVisitor { // No longer needed, but can't delete until any multi-instantiated modules are expanded } - void visit(AstForeach* nodep) override { + void visit(AstNodeForeach* nodep) override { // Symbol table needs nodep->name() as the index variable's name VL_RESTORER(m_curSymp); { @@ -1540,7 +1547,6 @@ public: //====================================================================== class LinkDotParamVisitor final : public VNVisitor { -private: // NODE STATE // Cleared on global // *::user1p() -> See LinkDotState @@ -1587,11 +1593,11 @@ private: // region. V3Dead should cleanup. // Downstream visitors up until V3Dead need to check for nodep->dead. nodep->dead(true); - } else { - m_modp = nodep; - iterateChildren(nodep); - m_modp = nullptr; + return; } + VL_RESTORER(m_modp); + m_modp = nodep; + iterateChildren(nodep); } void visit(AstPin* nodep) override { // Pin: Link to submodule's port @@ -1761,11 +1767,11 @@ class LinkDotScopeVisitor final : public VNVisitor { "Scopes should only exist right after V3Scope"); // Using the CELL names, we created all hierarchy. We now need to match this Scope // up with the hierarchy created by the CELL names. + VL_RESTORER(m_modSymp); + VL_RESTORER(m_scopep); m_modSymp = m_statep->getScopeSym(nodep); m_scopep = nodep; iterateChildren(nodep); - m_modSymp = nullptr; - m_scopep = nullptr; } void visit(AstVarScope* nodep) override { if (!nodep->varp()->isFuncLocal() && !nodep->varp()->isClassMember()) { @@ -1810,7 +1816,7 @@ class LinkDotScopeVisitor final : public VNVisitor { symp->fallbackp(m_modSymp); iterateChildren(nodep); } - void visit(AstForeach* nodep) override { + void visit(AstNodeForeach* nodep) override { VSymEnt* const symp = m_statep->insertBlock(m_modSymp, nodep->name(), nodep, nullptr); symp->fallbackp(m_modSymp); // No recursion, we don't want to pick up variables @@ -1997,7 +2003,6 @@ void LinkDotState::computeIfaceModSyms() { //====================================================================== class LinkDotResolveVisitor final : public VNVisitor { -private: // NODE STATE // Cleared on global // *::user1p() -> See LinkDotState @@ -2537,7 +2542,7 @@ private: // m_curSymp is symbol table of outer expression // m_ds.m_dotSymp is symbol table relative to "."'s above now UASSERT_OBJ(m_ds.m_dotSymp, nodep, "nullptr lookup symbol table"); - // Generally resolved during Primay, but might be at param time under AstUnlinkedRef + // Generally resolved during Primary, but might be at param time under AstUnlinkedRef UASSERT_OBJ(m_statep->forPrimary() || m_statep->forPrearray(), nodep, "ParseRefs should no longer exist"); const DotStates lastStates = m_ds; @@ -2803,6 +2808,13 @@ private: nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } + } else if (AstConstraint* const consp = VN_CAST(foundp->nodep(), Constraint)) { + AstNode* const newp = new AstConstraintRef{nodep->fileline(), consp->name()}; + nodep->replaceWith(newp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + ok = true; + m_ds.m_dotPos = DP_MEMBER; + m_ds.m_dotText = ""; } else if (AstEnumItem* const valuep = VN_CAST(foundp->nodep(), EnumItem)) { if (allowVar) { AstNode* const newp @@ -2936,6 +2948,12 @@ private: << nodep->classOrPackageNodep()->prettyName() << "#()'"); } } + void visit(AstConstraintRef* nodep) override { + if (nodep->user3SetOnce()) return; + UINFO(8, " " << nodep << endl); + UINFO(8, " " << m_ds.ascii() << endl); + // No children defined + } void visit(AstVarRef* nodep) override { // VarRef: Resolve its reference // ParseRefs are used the first pass (forPrimary) so we shouldn't get can't find @@ -3326,7 +3344,19 @@ private: m_ds.init(m_curSymp); iterateAndNextNull(nodep->rhsp()); iterateAndNextNull(nodep->thsp()); - iterateAndNextNull(nodep->attrp()); + } + + if (nodep->attrp()) { + AstNode* const attrp = nodep->attrp()->unlinkFrBack(); + VL_DO_DANGLING(attrp->deleteTree(), attrp); + } + AstNode* const basefromp = AstArraySel::baseFromp(nodep, false); + if (VN_IS(basefromp, Replicate)) { + // From {...}[...] syntax in IEEE 2017 + if (basefromp) UINFO(1, " Related node: " << basefromp << endl); + } else { + nodep->attrp(new AstAttrOf{nodep->fileline(), VAttrType::VAR_BASE, + basefromp->cloneTree(false)}); } } void visit(AstMemberSel* nodep) override { @@ -3371,6 +3401,7 @@ private: } } VL_RESTORER(m_curSymp); + VL_RESTORER(m_ftaskp); { m_ftaskp = nodep; m_ds.m_dotSymp = m_curSymp = m_statep->getNodeSym(nodep); @@ -3386,9 +3417,8 @@ private: } } m_ds.m_dotSymp = VL_RESTORER_PREV(m_curSymp); - m_ftaskp = nullptr; } - void visit(AstForeach* nodep) override { + void visit(AstNodeForeach* nodep) override { UINFO(5, " " << nodep << endl); checkNoDot(nodep); VL_RESTORER(m_curSymp); @@ -3725,6 +3755,22 @@ private: iterateChildren(nodep); } + void visit(AstIfaceRefDType* nodep) override { + if (nodep->paramsp()) { + // If there is no parameters, there is no need to visit this node. + AstIface* const ifacep = nodep->ifacep(); + UASSERT_OBJ(ifacep, nodep, "Port parameters of AstIfaceRefDType without ifacep()"); + if (ifacep->dead()) return; + checkNoDot(nodep); + m_usedPins.clear(); + VL_RESTORER(m_pinSymp); + m_pinSymp = m_statep->getNodeSym(ifacep); + iterateAndNextNull(nodep->paramsp()); + } + } + + void visit(AstAttrOf* nodep) override { iterateChildren(nodep); } + void visit(AstNode* nodep) override { checkNoDot(nodep); iterateChildren(nodep); diff --git a/src/V3LinkDot.h b/src/V3LinkDot.h index 5e3667210..351993913 100644 --- a/src/V3LinkDot.h +++ b/src/V3LinkDot.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkInc.cpp b/src/V3LinkInc.cpp index d4a00861c..6f87710ca 100644 --- a/src/V3LinkInc.cpp +++ b/src/V3LinkInc.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -47,7 +47,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class LinkIncVisitor final : public VNVisitor { -private: // TYPES enum InsertMode : uint8_t { IM_BEFORE, // Pointing at statement ref is in, insert before this @@ -129,7 +128,7 @@ private: // Done the loop m_insStmtp = nullptr; // Next thing should be new statement } - void visit(AstForeach* nodep) override { + void visit(AstNodeForeach* nodep) override { // Special, as statements need to be put in different places // Body insert just before themselves m_insStmtp = nullptr; // First thing should be new statement diff --git a/src/V3LinkInc.h b/src/V3LinkInc.h index b41807437..9a3051da4 100644 --- a/src/V3LinkInc.h +++ b/src/V3LinkInc.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp index e777ac164..267439768 100644 --- a/src/V3LinkJump.cpp +++ b/src/V3LinkJump.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -42,7 +42,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class LinkJumpVisitor final : public VNVisitor { -private: // NODE STATE // AstNode::user1() -> AstJumpLabel*, for this block if endOfIter // AstNode::user2() -> AstJumpLabel*, for this block if !endOfIter @@ -143,18 +142,18 @@ private: return labelp; } } - void addPrefixToBlocksRecurse(AstNode* nodep) { - // Add do_while_ prefix to blocks + void addPrefixToBlocksRecurse(const std::string& prefix, AstNode* const nodep) { + // Add a prefix to blocks // Used to not have blocks with duplicated names if (AstBegin* const beginp = VN_CAST(nodep, Begin)) { - if (beginp->name() != "") beginp->name("__Vdo_while_" + beginp->name()); + if (beginp->name() != "") beginp->name(prefix + beginp->name()); } - if (nodep->op1p()) addPrefixToBlocksRecurse(nodep->op1p()); - if (nodep->op2p()) addPrefixToBlocksRecurse(nodep->op2p()); - if (nodep->op3p()) addPrefixToBlocksRecurse(nodep->op3p()); - if (nodep->op4p()) addPrefixToBlocksRecurse(nodep->op4p()); - if (nodep->nextp()) addPrefixToBlocksRecurse(nodep->nextp()); + if (nodep->op1p()) addPrefixToBlocksRecurse(prefix, nodep->op1p()); + if (nodep->op2p()) addPrefixToBlocksRecurse(prefix, nodep->op2p()); + if (nodep->op3p()) addPrefixToBlocksRecurse(prefix, nodep->op3p()); + if (nodep->op4p()) addPrefixToBlocksRecurse(prefix, nodep->op4p()); + if (nodep->nextp()) addPrefixToBlocksRecurse(prefix, nodep->nextp()); } // VISITORS @@ -241,11 +240,12 @@ private: VL_DO_DANGLING(nodep->deleteTree(), nodep); if (bodyp) { AstNode* const copiedBodyp = bodyp->cloneTree(false); - addPrefixToBlocksRecurse(copiedBodyp); + addPrefixToBlocksRecurse("__Vdo_while1_", copiedBodyp); + addPrefixToBlocksRecurse("__Vdo_while2_", bodyp); whilep->addHereThisAsNext(copiedBodyp); } } - void visit(AstForeach* nodep) override { + void visit(AstNodeForeach* nodep) override { VL_RESTORER(m_loopp); { m_loopp = nodep; diff --git a/src/V3LinkJump.h b/src/V3LinkJump.h index 48b919f8a..da6b0751d 100644 --- a/src/V3LinkJump.h +++ b/src/V3LinkJump.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkLValue.cpp b/src/V3LinkLValue.cpp index 11a1e4499..88b34da37 100644 --- a/src/V3LinkLValue.cpp +++ b/src/V3LinkLValue.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -28,7 +28,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Link state, as a visitor of each AstNode class LinkLValueVisitor final : public VNVisitor { -private: // NODE STATE // STATE @@ -238,19 +237,19 @@ private: void visit(AstSel* nodep) override { VL_RESTORER(m_setRefLvalue); { - iterateAndNextNull(nodep->lhsp()); + iterateAndNextNull(nodep->fromp()); // Only set lvalues on the from m_setRefLvalue = VAccess::NOCHANGE; - iterateAndNextNull(nodep->rhsp()); - iterateAndNextNull(nodep->thsp()); + iterateAndNextNull(nodep->lsbp()); + iterateAndNextNull(nodep->widthp()); } } void visit(AstNodeSel* nodep) override { VL_RESTORER(m_setRefLvalue); { // Only set lvalues on the from - iterateAndNextNull(nodep->lhsp()); + iterateAndNextNull(nodep->fromp()); m_setRefLvalue = VAccess::NOCHANGE; - iterateAndNextNull(nodep->rhsp()); + iterateAndNextNull(nodep->bitp()); } } void visit(AstCellArrayRef* nodep) override { diff --git a/src/V3LinkLValue.h b/src/V3LinkLValue.h index 26cbaa4e3..0d0139890 100644 --- a/src/V3LinkLValue.h +++ b/src/V3LinkLValue.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index f784f0707..f6d19543a 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkLevel.h b/src/V3LinkLevel.h index aa86a2b82..02e661d9b 100644 --- a/src/V3LinkLevel.h +++ b/src/V3LinkLevel.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -29,7 +29,6 @@ //============================================================================ class V3LinkLevel final { -private: using ModVec = std::vector; static void timescaling(const ModVec& mods) VL_MT_DISABLED; diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index baf66d3f7..728539c2a 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -33,7 +33,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Link state, as a visitor of each AstNode class LinkParseVisitor final : public VNVisitor { -private: // NODE STATE // Cleared on netlist // AstNode::user1() -> bool. True if processed @@ -242,6 +241,10 @@ private: } } void visit(AstNodeDType* nodep) override { visitIterateNodeDType(nodep); } + void visit(AstConstraint* nodep) override { + v3Global.useRandomizeMethods(true); + iterateChildren(nodep); + } void visit(AstEnumDType* nodep) override { if (nodep->name() == "") { nodep->name(nameFromTypedef(nodep)); // Might still remain "" @@ -533,7 +536,7 @@ private: VL_DO_DANGLING(nodep->deleteTree(), nodep); } - void visit(AstForeach* nodep) override { + void visit(AstNodeForeach* nodep) override { // FOREACH(array, loopvars, body) UINFO(9, "FOREACH " << nodep << endl); cleanFileline(nodep); @@ -557,7 +560,7 @@ private: // Convert to AstSelLoopVars so V3LinkDot knows what's being defined AstNode* const newp = new AstSelLoopVars{selp->fileline(), selp->fromp()->unlinkFrBack(), - selp->rhsp()->unlinkFrBackWithNext()}; + selp->bitp()->unlinkFrBackWithNext()}; selp->replaceWith(newp); VL_DO_DANGLING(selp->deleteTree(), selp); } else if (VN_IS(bracketp, SelLoopVars)) { diff --git a/src/V3LinkParse.h b/src/V3LinkParse.h index 5694c4396..fc56900ba 100644 --- a/src/V3LinkParse.h +++ b/src/V3LinkParse.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index b0636a298..0507decdf 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -37,7 +37,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Link state, as a visitor of each AstNode class LinkResolveVisitor final : public VNVisitor { -private: // NODE STATE // Entire netlist: // AstCaseItem::user2() // bool Moved default caseitems @@ -182,19 +181,6 @@ private: nodep->scopeNamep(new AstScopeName{nodep->fileline(), false}); } } - void visit(AstNodePreSel* nodep) override { - if (!nodep->attrp()) { - iterateChildren(nodep); - AstNode* const basefromp = AstArraySel::baseFromp(nodep, false); - if (VN_IS(basefromp, Replicate)) { - // From {...}[...] syntax in IEEE 2017 - if (basefromp) UINFO(1, " Related node: " << basefromp << endl); - } else { - nodep->attrp(new AstAttrOf{nodep->fileline(), VAttrType::VAR_BASE, - basefromp->cloneTree(false)}); - } - } - } void visit(AstCaseItem* nodep) override { // Move default caseItems to the bottom of the list @@ -493,7 +479,6 @@ public: // from child cells up to the top module. class LinkBotupVisitor final : public VNVisitorConst { -private: // STATE AstNodeModule* m_modp = nullptr; // Current module diff --git a/src/V3LinkResolve.h b/src/V3LinkResolve.h index 0588f8e7a..e1eb1f879 100644 --- a/src/V3LinkResolve.h +++ b/src/V3LinkResolve.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3List.h b/src/V3List.h index 6b4472008..6b6305929 100644 --- a/src/V3List.h +++ b/src/V3List.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Localize.cpp b/src/V3Localize.cpp index d26a86175..b92751c89 100644 --- a/src/V3Localize.cpp +++ b/src/V3Localize.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -37,7 +37,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // LocalizeVisitor class LocalizeVisitor final : public VNVisitor { -private: // NODE STATE // AstVarScope::user1() -> Bool indicating VarScope is not optimizable. // AstCFunc::user1() -> Bool indicating CFunc is not a leaf function. @@ -167,7 +166,7 @@ private: && !nodep->varp()->isFuncLocal() // Not already a function local (e.g.: argument) && !nodep->varp()->isStatic() // Not a static variable && !nodep->varp()->isClassMember() // Statically exists in design hierarchy - && !nodep->varp()->isUsedVirtIface() // Not used through a virtual interface + && !nodep->varp()->sensIfacep() // Not sensitive to an interface && !nodep->varp()->valuep() // Does not have an initializer ) { UINFO(4, "Consider for localization: " << nodep << endl); diff --git a/src/V3Localize.h b/src/V3Localize.h index ee4e62e6d..e9041b63f 100644 --- a/src/V3Localize.h +++ b/src/V3Localize.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3MemberMap.h b/src/V3MemberMap.h index 8601214ca..9b9035133 100644 --- a/src/V3MemberMap.h +++ b/src/V3MemberMap.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -74,6 +74,16 @@ private: if (AstClass::isCacheableChild(itemp)) memberInsert(mmapr, itemp); } } + } else if (const AstIface* const anodep = VN_CAST(nodep, Iface)) { + for (AstNode* itemp = anodep->stmtsp(); itemp; itemp = itemp->nextp()) { + if (const AstScope* const scopep = VN_CAST(itemp, Scope)) { + for (AstNode* blockp = scopep->blocksp(); blockp; blockp = blockp->nextp()) { + memberInsert(mmapr, blockp); + } + } else { + memberInsert(mmapr, itemp); + } + } } else if (const AstNodeUOrStructDType* const anodep = VN_CAST(nodep, NodeUOrStructDType)) { for (AstNode* itemp = anodep->membersp(); itemp; itemp = itemp->nextp()) { diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp index e5b078daa..55e674808 100644 --- a/src/V3MergeCond.cpp +++ b/src/V3MergeCond.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -223,7 +223,7 @@ class CodeMotionAnalysisVisitor final : public VNVisitorConst { } } - // Analyse this statement + // Analyze this statement analyzeNode(nodep); // If there is an enclosing statement, propagate properties upwards @@ -261,7 +261,7 @@ class CodeMotionAnalysisVisitor final : public VNVisitorConst { if (!singletonListStart) m_stack.emplace_back(m_hasher); } - // Analyse node + // Analyze node if (AstNodeStmt* const stmtp = VN_CAST(nodep, NodeStmt)) { analyzeStmt(stmtp, /*tryCondMatch:*/ !singletonListStart); } else if (AstVarRef* const vrefp = VN_CAST(nodep, VarRef)) { @@ -281,7 +281,7 @@ class CodeMotionAnalysisVisitor final : public VNVisitorConst { } public: - // Analyse the statement list starting at nodep, filling in stmtProperties. + // Analyze the statement list starting at nodep, filling in stmtProperties. static void analyze(AstNode* nodep, StmtPropertiesAllocator& stmtProperties) { CodeMotionAnalysisVisitor{nodep, stmtProperties}; } @@ -425,7 +425,6 @@ public: // Conditional merging class MergeCondVisitor final : public VNVisitor { -private: // NODE STATE // AstVar::user1 -> bool: Set for variables referenced by m_mgCondp // (Only below MergeCondVisitor::process). @@ -475,7 +474,7 @@ private: AstNode* currp = m_workQueuep->front(); m_workQueuep->pop(); - // Analyse sub-tree list for code motion and conditional merging + // Analyze sub-tree list for code motion and conditional merging CodeMotionAnalysisVisitor::analyze(currp, stmtProperties); // Perform the code motion within the whole sub-tree list if (v3Global.opt.fMergeCondMotion()) { diff --git a/src/V3MergeCond.h b/src/V3MergeCond.h index 4510e4572..6e798e8ac 100644 --- a/src/V3MergeCond.h +++ b/src/V3MergeCond.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Mutex.h b/src/V3Mutex.h index e08fed7c6..cbf78b10a 100644 --- a/src/V3Mutex.h +++ b/src/V3Mutex.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -39,11 +39,10 @@ #define VL_LOCK_SPINS 50000 /// Number of times to spin for a mutex before yielding -// MutexConfig class that allows to configure how mutex and lockgurads behave +// MutexConfig class that allows to configure how mutex and lockguards behave // once configured and locked, it cannot be changed. Configuration and lock needs to be // done before starting any additional threads. class V3MutexConfig final { -private: // Allows to disable mutexes and lockguards. // Use carefully as it can cause undefined behavior when used inappropriately. // All mutexes needs to be unlocked. @@ -78,7 +77,6 @@ public: /// Mutex, wrapped to allow -fthread_safety checks template class VL_CAPABILITY("mutex") V3MutexImp final { -private: T m_mutex; // Mutex public: diff --git a/src/V3Name.cpp b/src/V3Name.cpp index 9825a3bac..481539e64 100644 --- a/src/V3Name.cpp +++ b/src/V3Name.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,8 +30,7 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### // Name state, as a visitor of each AstNode -class NameVisitor final : public VNVisitor { -private: +class NameVisitor final : public VNVisitorConst { // NODE STATE // Cleared on Netlist // AstCell::user1() -> bool. Set true if already processed @@ -69,7 +68,7 @@ private: VL_RESTORER(m_modp); { m_modp = nodep; - iterateChildren(nodep); + iterateChildrenConst(nodep); } } // Add __PVT__ to names of local signals @@ -82,39 +81,39 @@ private: } void visit(AstCFunc* nodep) override { if (!nodep->user1()) { - iterateChildren(nodep); + iterateChildrenConst(nodep); rename(nodep, false); } } - void visit(AstVarRef* nodep) override { iterate(nodep->varp()); } + void visit(AstVarRef* nodep) override { iterateConst(nodep->varp()); } void visit(AstCell* nodep) override { if (!nodep->user1()) { rename(nodep, (!nodep->modp()->modPublic() && !VN_IS(nodep->modp(), ClassPackage))); - iterateChildren(nodep); + iterateChildrenConst(nodep); } } void visit(AstMemberDType* nodep) override { if (!nodep->user1()) { rename(nodep, true); - iterateChildren(nodep); + iterateChildrenConst(nodep); } } void visit(AstMemberSel* nodep) override { if (!nodep->user1()) { rename(nodep, true); - iterateChildren(nodep); + iterateChildrenConst(nodep); } } void visit(AstStructSel* nodep) override { if (!nodep->user1()) { rename(nodep, true); - iterateChildren(nodep); + iterateChildrenConst(nodep); } } void visit(AstScope* nodep) override { if (!nodep->user1SetOnce()) { - if (nodep->aboveScopep()) iterate(nodep->aboveScopep()); - if (nodep->aboveCellp()) iterate(nodep->aboveCellp()); + if (nodep->aboveScopep()) iterateConst(nodep->aboveScopep()); + if (nodep->aboveCellp()) iterateConst(nodep->aboveCellp()); // Always recompute name (as many levels above scope may have changed) // Same formula as V3Scope nodep->name(nodep->isTop() ? "TOP" @@ -123,16 +122,16 @@ private: ? ("TOP." + m_modp->name()) : (nodep->aboveScopep()->name() + "." + nodep->aboveCellp()->name())); nodep->editCountInc(); - iterateChildren(nodep); + iterateChildrenConst(nodep); } } //-------------------- - void visit(AstNode* nodep) override { iterateChildren(nodep); } + void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } public: // CONSTRUCTORS - explicit NameVisitor(AstNetlist* nodep) { iterate(nodep); } + explicit NameVisitor(AstNetlist* nodep) { iterateConst(nodep); } ~NameVisitor() override = default; }; diff --git a/src/V3Name.h b/src/V3Name.h index cb2781378..df0f9d083 100644 --- a/src/V3Name.h +++ b/src/V3Name.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Number.cpp b/src/V3Number.cpp index 91403a532..e6263c18e 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -482,6 +482,11 @@ V3Number& V3Number::setAllBitsXRemoved() { } } } +V3Number& V3Number::setValue1() { + m_data.num()[0] = {1, 0}; + for (int i = 1; i < words(); i++) m_data.num()[i] = {0, 0}; + return *this; +} V3Number& V3Number::setMask(int nbits) { setZero(); @@ -896,14 +901,20 @@ string V3Number::toDecimalU() const VL_MT_STABLE { //====================================================================== // ACCESSORS - as numbers +bool V3Number::fitsInUInt() const VL_MT_SAFE { + if (isFourState()) return false; + // We allow wide numbers that represent values <= 32 bits + for (int i = 1; i < words(); ++i) { + if (m_data.num()[i].m_value) return false; + } + return true; +} uint32_t V3Number::toUInt() const VL_MT_SAFE { UASSERT(!isFourState(), "toUInt with 4-state " << *this); // We allow wide numbers that represent values <= 32 bits - for (int i = 1; i < words(); ++i) { - if (m_data.num()[i].m_value) { - v3error("Value too wide for 32-bits expected in this context " << *this); - break; - } + if (VL_UNCOVERABLE(!fitsInUInt())) { + v3error("Value too wide for 32-bits expected in this context " // LCOV_EXCL_LINE + << *this); } return m_data.num()[0].m_value; } @@ -2133,18 +2144,18 @@ V3Number& V3Number::opPow(const V3Number& lhs, const V3Number& rhs, bool lsign, NUM_ASSERT_OP_ARGS2(lhs, rhs); NUM_ASSERT_LOGIC_ARGS2(lhs, rhs); if (lhs.isFourState() || rhs.isFourState()) return setAllBitsX(); - if (rhs.isEqZero()) return setQuad(1); // Overrides lhs 0 -> return 0 + if (rhs.isEqZero()) return setValue1(); // Overrides lhs 0 -> return 1 // We may want to special case when the lhs is 2, so we can get larger outputs if (rsign && rhs.isNegative()) { if (lhs.isEqZero()) { return setAllBitsXRemoved(); } else if (lhs.isEqOne()) { - return setQuad(1); + return setValue1(); } else if (lsign && lhs.isEqAllOnes()) { if (rhs.bitIs1(0)) { return setAllBits1(); // -1^odd=-1 } else { - return setQuad(1); // -1^even=1 + return setValue1(); // -1^even=1 } } return setZero(); diff --git a/src/V3Number.h b/src/V3Number.h index acab8420e..70c63b019 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -581,6 +581,7 @@ public: V3Number& setAllBitsZ(); V3Number& setAllBits0(); V3Number& setAllBits1(); + V3Number& setValue1(); V3Number& setMask(int nbits); // IE if nbits=1, then 0b1, if 2->0b11, if 3->0b111 etc // ACCESSORS @@ -638,6 +639,7 @@ public: bool isAnyXZ() const; bool isAnyZ() const VL_MT_SAFE; bool isMsbXZ() const { return bitIsXZ(m_data.width() - 1); } + bool fitsInUInt() const VL_MT_SAFE; uint32_t toUInt() const VL_MT_SAFE; int32_t toSInt() const VL_MT_SAFE; uint64_t toUQuad() const VL_MT_SAFE; diff --git a/src/V3Number_test.cpp b/src/V3Number_test.cpp index 1d7898013..45bbc1d82 100644 --- a/src/V3Number_test.cpp +++ b/src/V3Number_test.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3OptionParser.cpp b/src/V3OptionParser.cpp index ea245400e..be65611be 100644 --- a/src/V3OptionParser.cpp +++ b/src/V3OptionParser.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3OptionParser.h b/src/V3OptionParser.h index 6975bd844..77250b1c7 100644 --- a/src/V3OptionParser.h +++ b/src/V3OptionParser.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 983e8243b..7a72a8dc5 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -456,23 +456,6 @@ bool V3Options::fileStatNormal(const string& filename) { return true; } -void V3Options::fileNfsFlush(const string& filename) { - // NFS caches stat() calls so to get up-to-date information must - // do a open or opendir on the filename. - // Faster to just try both rather than check if a file is a dir. -#ifdef _MSC_VER - if (int fd = ::open(filename.c_str(), O_RDONLY)) { // LCOV_EXCL_BR_LINE - if (fd > 0) ::close(fd); - } -#else - if (DIR* const dirp = opendir(filename.c_str())) { // LCOV_EXCL_BR_LINE - closedir(dirp); // LCOV_EXCL_LINE - } else if (int fd = ::open(filename.c_str(), O_RDONLY)) { // LCOV_EXCL_BR_LINE - if (fd > 0) ::close(fd); - } -#endif -} - string V3Options::fileExists(const string& filename) { // Surprisingly, for VCS and other simulators, this process // is quite slow; presumably because of re-reading each directory @@ -967,7 +950,7 @@ string V3Options::argString(int argc, char** argv) { string opts; for (int i = 0; i < argc; ++i) { if (i != 0) opts += " "; - opts += string(argv[i]); + opts += string{argv[i]}; } return opts; } @@ -1232,6 +1215,8 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, }); DECL_OPTION("-fdfg-pre-inline", FOnOff, &m_fDfgPreInline); DECL_OPTION("-fdfg-post-inline", FOnOff, &m_fDfgPostInline); + DECL_OPTION("-fdead-assigns", FOnOff, &m_fDeadAssigns); + DECL_OPTION("-fdead-cells", FOnOff, &m_fDeadCells); DECL_OPTION("-fexpand", FOnOff, &m_fExpand); DECL_OPTION("-fgate", FOnOff, &m_fGate); DECL_OPTION("-finline", FOnOff, &m_fInline); @@ -1330,47 +1315,6 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, DECL_OPTION("-O2", CbCall, [this]() { optimize(2); }); DECL_OPTION("-O3", CbCall, [this]() { optimize(3); }); - DECL_OPTION("-O", CbPartialMatch, [this, fl](const char* optp) { - // Optimization, e.g. -O1rX - // LCOV_EXCL_START - fl->v3warn(DEPRECATED, "Option -O is deprecated. " - "Use -f or -fno- instead."); - for (const char* cp = optp; *cp; ++cp) { - const bool flag = std::isupper(*cp); - switch (std::tolower(*cp)) { - case '0': optimize(0); break; - case '1': optimize(1); break; - case '2': optimize(2); break; - case '3': optimize(3); break; - case 'a': m_fTable = flag; break; // == -fno-table - case 'b': m_fCombine = flag; break; // == -fno-combine - case 'c': m_fConst = flag; break; // == -fno-const - case 'd': m_fDedupe = flag; break; // == -fno-dedup - case 'e': m_fCase = flag; break; // == -fno-case - case 'g': m_fGate = flag; break; // == -fno-gate - case 'i': m_fInline = flag; break; // == -fno-inline - case 'k': m_fSubstConst = flag; break; // == -fno-subst-const - case 'l': m_fLife = flag; break; // == -fno-life - case 'm': m_fAssemble = flag; break; // == -fno-assemble - case 'o': m_fConstBitOpTree = flag; break; // == -fno-const-bit-op-tree - case 'p': - m_public = !flag; - break; // With -Op so flag=0, we want public on so few optimizations done - case 'r': m_fReorder = flag; break; // == -fno-reorder - case 's': m_fSplit = flag; break; // == -fno-split - case 't': m_fLifePost = flag; break; // == -fno-life-post - case 'u': m_fSubst = flag; break; // == -fno-subst - case 'v': m_fReloop = flag; break; // == -fno-reloop - case 'w': m_fMergeCond = flag; break; // == -fno-merge-cond - case 'x': m_fExpand = flag; break; // == -fno-expand - case 'y': m_fAcycSimp = flag; break; // == -fno-acyc-simp - case 'z': m_fLocalize = flag; break; // == -fno-localize - default: - break; // No error, just ignore - // LCOV_EXCL_STOP - } - } - }); DECL_OPTION("-o", Set, &m_exeName); DECL_OPTION("-order-clock-delay", CbOnOff, [fl](bool /*flag*/) { fl->v3warn(DEPRECATED, "Option order-clock-delay is deprecated and has no effect."); @@ -1417,11 +1361,6 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, [this]() { m_profC = m_profCFuncs = true; }); // Renamed DECL_OPTION("-prof-exec", OnOff, &m_profExec); DECL_OPTION("-prof-pgo", OnOff, &m_profPgo); - DECL_OPTION("-prof-threads", CbOnOff, [this, fl](bool flag) { - fl->v3warn(DEPRECATED, "Option --prof-threads is deprecated. " - "Use --prof-exec and --prof-pgo instead."); - m_profExec = m_profPgo = flag; - }); DECL_OPTION("-protect-ids", OnOff, &m_protectIds); DECL_OPTION("-protect-key", Set, &m_protectKey); DECL_OPTION("-protect-lib", CbVal, [this](const char* valp) { @@ -1687,7 +1626,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, }); DECL_OPTION("-y", CbVal, [this, &optdir](const char* valp) { - addIncDirUser(parseFileArg(optdir, string(valp))); + addIncDirUser(parseFileArg(optdir, string{valp})); }); parser.finalize(); @@ -1896,46 +1835,46 @@ string V3Options::parseFileArg(const string& optdir, const string& relfilename) void V3Options::showVersion(bool verbose) { cout << version(); - cout << endl; + cout << "\n"; if (!verbose) return; - cout << endl; - cout << "Copyright 2003-2023 by Wilson Snyder. Verilator is free software; you can\n"; + cout << "\n"; + cout << "Copyright 2003-2024 by Wilson Snyder. Verilator is free software; you can\n"; cout << "redistribute it and/or modify the Verilator internals under the terms of\n"; cout << "either the GNU Lesser General Public License Version 3 or the Perl Artistic\n"; cout << "License Version 2.0.\n"; - cout << endl; + cout << "\n"; cout << "See https://verilator.org for documentation\n"; - cout << endl; + cout << "\n"; cout << "Summary of configuration:\n"; cout << " Compiled in defaults if not in environment:\n"; - cout << " SYSTEMC = " << DEFENV_SYSTEMC << endl; - cout << " SYSTEMC_ARCH = " << DEFENV_SYSTEMC_ARCH << endl; - cout << " SYSTEMC_INCLUDE = " << DEFENV_SYSTEMC_INCLUDE << endl; - cout << " SYSTEMC_LIBDIR = " << DEFENV_SYSTEMC_LIBDIR << endl; - cout << " VERILATOR_ROOT = " << DEFENV_VERILATOR_ROOT << endl; - cout << " SystemC system-wide = " << cvtToStr(systemCSystemWide()) << endl; + cout << " SYSTEMC = " << DEFENV_SYSTEMC << "\n"; + cout << " SYSTEMC_ARCH = " << DEFENV_SYSTEMC_ARCH << "\n"; + cout << " SYSTEMC_INCLUDE = " << DEFENV_SYSTEMC_INCLUDE << "\n"; + cout << " SYSTEMC_LIBDIR = " << DEFENV_SYSTEMC_LIBDIR << "\n"; + cout << " VERILATOR_ROOT = " << DEFENV_VERILATOR_ROOT << "\n"; + cout << " SystemC system-wide = " << cvtToStr(systemCSystemWide()) << "\n"; // If update below, also update V3Options::getenvBuiltins() - cout << endl; + cout << "\n"; cout << "Environment:\n"; - cout << " MAKE = " << V3Os::getenvStr("MAKE", "") << endl; - cout << " PERL = " << V3Os::getenvStr("PERL", "") << endl; - cout << " SYSTEMC = " << V3Os::getenvStr("SYSTEMC", "") << endl; - cout << " SYSTEMC_ARCH = " << V3Os::getenvStr("SYSTEMC_ARCH", "") << endl; - cout << " SYSTEMC_INCLUDE = " << V3Os::getenvStr("SYSTEMC_INCLUDE", "") << endl; - cout << " SYSTEMC_LIBDIR = " << V3Os::getenvStr("SYSTEMC_LIBDIR", "") << endl; + cout << " MAKE = " << V3Os::getenvStr("MAKE", "") << "\n"; + cout << " PERL = " << V3Os::getenvStr("PERL", "") << "\n"; + cout << " SYSTEMC = " << V3Os::getenvStr("SYSTEMC", "") << "\n"; + cout << " SYSTEMC_ARCH = " << V3Os::getenvStr("SYSTEMC_ARCH", "") << "\n"; + cout << " SYSTEMC_INCLUDE = " << V3Os::getenvStr("SYSTEMC_INCLUDE", "") << "\n"; + cout << " SYSTEMC_LIBDIR = " << V3Os::getenvStr("SYSTEMC_LIBDIR", "") << "\n"; // wrapper uses VERILATOR_BIN - cout << " VERILATOR_BIN = " << V3Os::getenvStr("VERILATOR_BIN", "") << endl; - cout << " VERILATOR_ROOT = " << V3Os::getenvStr("VERILATOR_ROOT", "") << endl; + cout << " VERILATOR_BIN = " << V3Os::getenvStr("VERILATOR_BIN", "") << "\n"; + cout << " VERILATOR_ROOT = " << V3Os::getenvStr("VERILATOR_ROOT", "") << "\n"; // If update below, also update V3Options::getSupported() - cout << endl; + cout << "\n"; cout << "Supported features (compiled-in or forced by environment):\n"; - cout << " COROUTINES = " << getSupported("COROUTINES") << endl; - cout << " SYSTEMC = " << getSupported("SYSTEMC") << endl; + cout << " COROUTINES = " << getSupported("COROUTINES") << "\n"; + cout << " SYSTEMC = " << getSupported("SYSTEMC") << "\n"; } //====================================================================== @@ -1969,7 +1908,7 @@ void V3Options::setDebugMode(int level) { if (!m_dumpLevel.count("tree")) m_dumpLevel["tree"] = 3; // Don't override if already set. m_stats = true; m_debugCheck = true; - cout << "Starting " << version() << endl; + cout << "Starting " << version() << "\n"; } unsigned V3Options::debugLevel(const string& tag) const VL_MT_SAFE { @@ -2016,6 +1955,8 @@ void V3Options::optimize(int level) { m_fDedupe = flag; m_fDfgPreInline = flag; m_fDfgPostInline = flag; + m_fDeadAssigns = flag; + m_fDeadCells = flag; m_fExpand = flag; m_fGate = flag; m_fInline = flag; diff --git a/src/V3Options.h b/src/V3Options.h index 259462fe8..bed53babe 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -143,7 +143,7 @@ public: constexpr operator en() const { return m_e; } bool fst() const { return m_e == FST; } bool vcd() const { return m_e == VCD; } - string classBase() const { + string classBase() const VL_MT_SAFE { static const char* const names[] = {"VerilatedVcd", "VerilatedFst"}; return names[m_e]; } @@ -363,6 +363,8 @@ private: bool m_fDfgPeephole = true; // main switch: -fno-dfg-peephole bool m_fDfgPreInline; // main switch: -fno-dfg-pre-inline and -fno-dfg bool m_fDfgPostInline; // main switch: -fno-dfg-post-inline and -fno-dfg + bool m_fDeadAssigns; // main switch: -fno-dead-assigns: remove dead assigns + bool m_fDeadCells; // main switch: -fno-dead-cells: remove dead cells bool m_fExpand; // main switch: -fno-expand: expansion of C macros bool m_fGate; // main switch: -fno-gate: gate wire elimination bool m_fInline; // main switch: -fno-inline: module inlining @@ -626,6 +628,8 @@ public: bool fDfgPeepholeEnabled(const std::string& name) const { return !m_fDfgPeepholeDisabled.count(name); } + bool fDeadAssigns() const { return m_fDeadAssigns; } + bool fDeadCells() const { return m_fDeadCells; } bool fExpand() const { return m_fExpand; } bool fGate() const { return m_fGate; } bool fInline() const { return m_fInline; } @@ -643,7 +647,7 @@ public: bool fTable() const { return m_fTable; } bool fTaskifyAll() const { return m_fTaskifyAll; } - string traceClassBase() const { return m_traceFormat.classBase(); } + string traceClassBase() const VL_MT_SAFE { return m_traceFormat.classBase(); } string traceClassLang() const { return m_traceFormat.classBase() + (systemC() ? "Sc" : "C"); } string traceSourceBase() const { return m_traceFormat.sourceName(); } string traceSourceLang() const VL_MT_SAFE { @@ -697,7 +701,6 @@ public: void filePathLookedMsg(FileLine* fl, const string& modname); V3LangCode fileLanguage(const string& filename); static bool fileStatNormal(const string& filename); - static void fileNfsFlush(const string& filename); // METHODS (other OS) static void throwSigsegv(); diff --git a/src/V3Order.cpp b/src/V3Order.cpp index 7b59511fc..cb5266bf9 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -1414,7 +1414,7 @@ void OrderProcess::process(bool multiThreaded) { // edges) will have its own color, and corresponds to a loop in the // original graph. However the new graph will be acyclic (the removed // edges are actually still there, just with weight 0). - UINFO(2, " Acyclic & Order...\n"); + UINFO(2, " Acyclic and Order...\n"); m_graph.acyclic(&V3GraphEdge::followAlwaysTrue); if (dumpGraphLevel()) m_graph.dumpDotFilePrefixed(m_tag + "_orderg_acyc"); diff --git a/src/V3Order.h b/src/V3Order.h index 3262e0ed8..dd7c42255 100644 --- a/src/V3Order.h +++ b/src/V3Order.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3OrderGraph.h b/src/V3OrderGraph.h index fef667f5b..7b08f4c62 100644 --- a/src/V3OrderGraph.h +++ b/src/V3OrderGraph.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3OrderMoveGraph.h b/src/V3OrderMoveGraph.h index 2404e9730..961053219 100644 --- a/src/V3OrderMoveGraph.h +++ b/src/V3OrderMoveGraph.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Os.cpp b/src/V3Os.cpp index 8763725c1..b6d2be2a0 100644 --- a/src/V3Os.cpp +++ b/src/V3Os.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -45,7 +45,9 @@ VL_DEFINE_DEBUG_FUNCTIONS; #define PATH_MAX MAX_PATH #else #include +#include #endif +#include #include #include @@ -58,6 +60,7 @@ VL_DEFINE_DEBUG_FUNCTIONS; # include // BCryptGenRandom # include # include // mkdir +# include // open, read, write, close # include // GetProcessMemoryInfo # include // These macros taken from gdbsupport/gdb_wait.h in binutils-gdb @@ -294,6 +297,36 @@ void V3Os::createDir(const string& dirname) { #endif } +void V3Os::filesystemFlush(const string& dirname) { + // NFS caches stat() calls so to get up-to-date information must + // do a open or opendir on the filename. +#if defined(_MSC_VER) || defined(__MINGW32__) + if (int fd = ::open(dirname.c_str(), O_RDONLY)) { // LCOV_EXCL_BR_LINE + if (fd > 0) ::close(fd); + } +#else + // Faster to just try both rather than check if a file is a dir. + if (DIR* const dirp = opendir(dirname.c_str())) { // LCOV_EXCL_BR_LINE + closedir(dirp); // LCOV_EXCL_LINE + } else if (int fd = ::open(dirname.c_str(), O_RDONLY)) { // LCOV_EXCL_BR_LINE + if (fd > 0) ::close(fd); + } +#endif +} + +void V3Os::filesystemFlushBuildDir(const string& dirname) { + // Attempt to force out written directory, for NFS like file systems. +#if !defined(_MSC_VER) && !defined(__MINGW32__) + // Linux kernel may not reread from NFS unless timestamp modified + struct timeval tv; + gettimeofday(&tv, NULL); + const int err = utimes(dirname.c_str(), &tv); + // Not an error + if (err != 0) UINFO(1, "-Info: File not utimed: " << dirname << endl); +#endif + filesystemFlush(dirname); +} + void V3Os::unlinkRegexp(const string& dir, const string& regexp) { #ifdef _MSC_VER try { diff --git a/src/V3Os.h b/src/V3Os.h index 3bf69ca17..d9858c878 100644 --- a/src/V3Os.h +++ b/src/V3Os.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -63,6 +63,8 @@ public: // METHODS (directory utilities) static void createDir(const string& dirname); + static void filesystemFlush(const string& dirname); + static void filesystemFlushBuildDir(const string& dirname); static void unlinkRegexp(const string& dir, const string& regexp); // METHODS (random) diff --git a/src/V3PairingHeap.h b/src/V3PairingHeap.h index 9e6bc041a..6b70b7ed6 100644 --- a/src/V3PairingHeap.h +++ b/src/V3PairingHeap.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Param.cpp b/src/V3Param.cpp index ffe79fa1f..028be731b 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -74,6 +74,7 @@ class ParameterizedHierBlocks final { using GParamsMap = std::map; // key:parameter name value:parameter // MEMBERS + const bool m_hierSubRun; // Is in sub-run for hierarchical verilation // key:Original module name, value:HiearchyBlockOption* // If a module is parameterized, the module is uniquified to overridden parameters. // This is why HierBlockOptsByOrigName is multimap. @@ -88,7 +89,8 @@ class ParameterizedHierBlocks final { // METHODS public: - ParameterizedHierBlocks(const V3HierBlockOptSet& hierOpts, AstNetlist* nodep) { + ParameterizedHierBlocks(const V3HierBlockOptSet& hierOpts, AstNetlist* nodep) + : m_hierSubRun(!v3Global.opt.hierBlocks().empty() || v3Global.opt.hierChild()) { for (const auto& hierOpt : hierOpts) { m_hierBlockOptsByOrigName.emplace(hierOpt.second.origName(), &hierOpt.second); const V3HierarchicalBlockOption::ParamStrMap& params = hierOpt.second.params(); @@ -109,7 +111,11 @@ public: if (hierOpts.find(modp->prettyName()) != hierOpts.end()) { m_hierBlockMod.emplace(modp->name(), modp); } - const auto defParamIt = m_modParams.find(modp->name()); + // Recursive hierarchical module may change its name, so we have to match its origName. + // Collect values from recursive cloned module as parameters in the top module could be + // overridden. + const string actualModName = modp->recursiveClone() ? modp->origName() : modp->name(); + const auto defParamIt = m_modParams.find(actualModName); if (defParamIt != m_modParams.end()) { // modp is the original of parameterized hierarchical block for (AstNode* stmtp = modp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { @@ -120,11 +126,13 @@ public: } } } + bool hierSubRun() const { return m_hierSubRun; } + bool isHierBlock(const string& origName) const { + return m_hierBlockOptsByOrigName.find(origName) != m_hierBlockOptsByOrigName.end(); + } AstNodeModule* findByParams(const string& origName, AstPin* firstPinp, const AstNodeModule* modp) { - if (m_hierBlockOptsByOrigName.find(origName) == m_hierBlockOptsByOrigName.end()) { - return nullptr; - } + UASSERT(isHierBlock(origName), origName << " is not hierarchical block\n"); // This module is a hierarchical block. Need to replace it by the --lib-create wrapper. const std::pair candidates = m_hierBlockOptsByOrigName.equal_range(origName); @@ -510,9 +518,9 @@ class ParamProcessor final { pair.first->second = std::move(params); } const auto paramsIt = pair.first; - if (paramsIt->second.empty()) return modp->name(); // modp has no parameter + if (paramsIt->second.empty()) return modp->origName(); // modp has no parameter - string longname = modp->name(); + string longname = modp->origName(); for (auto&& defaultValue : paramsIt->second) { const auto pinIt = pins.find(defaultValue.first); const AstConst* const constp @@ -536,7 +544,7 @@ class ParamProcessor final { // Hex string must be a safe suffix for any symbol const string hashStr = hashStrGen.digestHex(); for (string::size_type i = 1; i < hashStr.size(); ++i) { - string newName = modp->name(); + string newName = modp->origName(); // Don't use '__' not to be encoded when this module is loaded later by Verilator if (newName.at(newName.size() - 1) != '_') newName += '_'; newName += hashStr.substr(0, i); @@ -586,8 +594,6 @@ class ParamProcessor final { newmodp->user2(false); // We need to re-recurse this module once changed newmodp->recursive(false); newmodp->recursiveClone(false); - // Only the first generation of clone holds this property - newmodp->hierBlock(srcModp->hierBlock() && !srcModp->recursiveClone()); // Recursion may need level cleanups if (newmodp->level() <= m_modp->level()) newmodp->level(m_modp->level() + 1); if ((newmodp->level() - srcModp->level()) >= (v3Global.opt.moduleRecursionDepth() - 2)) { @@ -851,7 +857,16 @@ class ParamProcessor final { cellInterfaceCleanup(pinsp, srcModpr, longname /*ref*/, any_overrides /*ref*/, ifaceRefRefs /*ref*/); - if (!any_overrides) { + if (m_hierBlocks.hierSubRun() && m_hierBlocks.isHierBlock(srcModpr->origName())) { + AstNodeModule* const paramedModp + = m_hierBlocks.findByParams(srcModpr->origName(), paramsp, m_modp); + UASSERT_OBJ(paramedModp, nodep, "Failed to find sub-module for hierarchical block"); + paramedModp->dead(false); + // We need to relink the pins to the new module + relinkPinsByName(pinsp, paramedModp); + srcModpr = paramedModp; + any_overrides = true; + } else if (!any_overrides) { UINFO(8, "Cell parameters all match original values, skipping expansion.\n"); // If it's the first use of the default instance, create a copy and store it in user3p. // user3p will also be used to check if the default instance is used. @@ -863,12 +878,6 @@ class ParamProcessor final { srcModpr->user3p(classCopyp); storeOriginalParams(classCopyp); } - } else if (AstNodeModule* const paramedModp - = m_hierBlocks.findByParams(srcModpr->name(), paramsp, m_modp)) { - paramedModp->dead(false); - // We need to relink the pins to the new module - relinkPinsByName(pinsp, paramedModp); - srcModpr = paramedModp; } else { const string newname = srcModpr->hierBlock() ? longname : moduleCalcName(srcModpr, longname); @@ -910,6 +919,11 @@ class ParamProcessor final { nodep->recursive(false); } + void ifaceRefDeparam(AstIfaceRefDType* const nodep, AstNodeModule*& srcModpr) { + nodeDeparamCommon(nodep, srcModpr, nodep->paramsp(), nullptr, false); + nodep->ifacep(VN_AS(srcModpr, Iface)); + } + void classRefDeparam(AstClassOrPackageRef* nodep, AstNodeModule*& srcModpr) { if (nodeDeparamCommon(nodep, srcModpr, nodep->paramsp(), nullptr, false)) nodep->classOrPackagep(srcModpr); @@ -939,6 +953,8 @@ public: if (auto* cellp = VN_CAST(nodep, Cell)) { cellDeparam(cellp, srcModpr); + } else if (auto* ifaceRefDTypep = VN_CAST(nodep, IfaceRefDType)) { + ifaceRefDeparam(ifaceRefDTypep, srcModpr); } else if (auto* classRefp = VN_CAST(nodep, ClassRefDType)) { classRefDeparam(classRefp, srcModpr); } else if (auto* classRefp = VN_CAST(nodep, ClassOrPackageRef)) { @@ -1033,6 +1049,8 @@ class ParamVisitor final : public VNVisitor { if (VN_IS(classRefp->classOrPackageNodep(), ParamTypeDType)) continue; } else if (const auto* classRefp = VN_CAST(cellp, ClassRefDType)) { srcModp = classRefp->classp(); + } else if (const auto* ifaceRefp = VN_CAST(cellp, IfaceRefDType)) { + srcModp = ifaceRefp->ifacep(); } else { cellp->v3fatalSrc("Expected module parameterization"); } @@ -1128,8 +1146,16 @@ class ParamVisitor final : public VNVisitor { void visit(AstCell* nodep) override { visitCellOrClassRef(nodep, VN_IS(nodep->modp(), Iface)); } + void visit(AstIfaceRefDType* nodep) override { + if (nodep->ifacep()) visitCellOrClassRef(nodep, true); + } void visit(AstClassRefDType* nodep) override { visitCellOrClassRef(nodep, false); } - void visit(AstClassOrPackageRef* nodep) override { visitCellOrClassRef(nodep, false); } + void visit(AstClassOrPackageRef* nodep) override { + // If it points to a typedef it is not really a class reference. That typedef will be + // visited anyway (from its parent node), so even if it points to a parameterized class + // type, the instance will be created. + if (!VN_IS(nodep->classOrPackageNodep(), Typedef)) visitCellOrClassRef(nodep, false); + } // Make sure all parameters are constantified void visit(AstVar* nodep) override { @@ -1304,6 +1330,10 @@ class ParamVisitor final : public VNVisitor { // so process here rather than at the generate to avoid iteration problems UINFO(9, " BEGIN " << nodep << endl); UINFO(9, " GENFOR " << forp << endl); + // Visit child nodes before unrolling + iterateAndNextNull(forp->initsp()); + iterateAndNextNull(forp->condp()); + iterateAndNextNull(forp->incsp()); V3Width::widthParamsEdit(forp); // Param typed widthing will NOT recurse the body // Outer wrapper around generate used to hold genvar, and to ensure genvar // doesn't conflict in V3LinkDot resolution with other genvars diff --git a/src/V3Param.h b/src/V3Param.h index d09a4314c..f042f788d 100644 --- a/src/V3Param.h +++ b/src/V3Param.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Parse.h b/src/V3Parse.h index 70e7b4896..852af5328 100644 --- a/src/V3Parse.h +++ b/src/V3Parse.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,7 +32,6 @@ class V3ParseSym; //============================================================================ class V3Parse final { -private: V3ParseImp* m_impp; // CONSTRUCTORS diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp index 384ec1ffa..12f44fd33 100644 --- a/src/V3ParseGrammar.cpp +++ b/src/V3ParseGrammar.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp index 1a058be02..0a630777c 100644 --- a/src/V3ParseImp.cpp +++ b/src/V3ParseImp.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index 345c118e1..6142e5326 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2009-2023 by Wilson Snyder. This program is free software; you +// Copyright 2009-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ParseLex.cpp b/src/V3ParseLex.cpp index bb39e3a59..552d3b652 100644 --- a/src/V3ParseLex.cpp +++ b/src/V3ParseLex.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ParseSym.h b/src/V3ParseSym.h index 32b817e19..a0a31ee60 100644 --- a/src/V3ParseSym.h +++ b/src/V3ParseSym.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2009-2023 by Wilson Snyder. This program is free software; you +// Copyright 2009-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index a1a502a06..d73b45e46 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -418,7 +418,6 @@ using MergeCandidateScoreboard = V3Scoreboard // Information associated with scoreboarding a merge candidate class MergeCandidate VL_NOT_FINAL : public MergeCandidateScoreboard::Node { -private: // Only the known subclasses can create or delete one of these friend class SiblingMC; friend class MTaskEdge; @@ -1056,7 +1055,6 @@ private: }; class PartPropagateCpSelfTest final { -private: // MEMBERS V3Graph m_graph; // A graph std::array m_vx; // All vertices within the graph @@ -1236,7 +1234,6 @@ static void partRedirectEdgesFrom(V3Graph* graphp, LogicMTask* recipientp, Logic // Perform edge or sibling contraction on the partition graph class PartContraction final { -private: // TYPES // New CP information for mtaskp reflecting an upcoming merge struct NewCp { @@ -1846,7 +1843,6 @@ private: // Scan node, indicate whether it contains a call to a DPI imported // routine. class DpiImportCallVisitor final : public VNVisitor { -private: bool m_hasDpiHazard = false; // Found a DPI import call. bool m_tracingCall = false; // Iterating into a CCall to a CFunc // METHODS @@ -1964,7 +1960,6 @@ private: // parallel mode. // class PartFixDataHazards final { -private: // TYPES using TasksByRank = std::map>; diff --git a/src/V3Partition.h b/src/V3Partition.h index 72d4e5b92..08574b6ba 100644 --- a/src/V3Partition.h +++ b/src/V3Partition.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -82,7 +82,6 @@ private: // Map a pointer into a id, for e.g. nodep to mtask mappings class PartPtrIdMap final { -private: // TYPES // MEMBERS mutable uint64_t m_nextId = 0; diff --git a/src/V3PartitionGraph.h b/src/V3PartitionGraph.h index cdfab1be1..2f55cc10e 100644 --- a/src/V3PartitionGraph.h +++ b/src/V3PartitionGraph.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3PchAstMT.h b/src/V3PchAstMT.h index af0c3b25a..c49e2a546 100644 --- a/src/V3PchAstMT.h +++ b/src/V3PchAstMT.h @@ -2,7 +2,7 @@ //************************************************************************* // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3PchAstNoMT.h b/src/V3PchAstNoMT.h index 2ecde3fd5..5d158864d 100644 --- a/src/V3PchAstNoMT.h +++ b/src/V3PchAstNoMT.h @@ -2,7 +2,7 @@ //************************************************************************* // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3PreLex.h b/src/V3PreLex.h index b6718d264..95ae573f0 100644 --- a/src/V3PreLex.h +++ b/src/V3PreLex.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2000-2023 by Wilson Snyder. This program is free software; you +// Copyright 2000-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3PreLex.l b/src/V3PreLex.l index 3209aa8bf..e8d882da4 100644 --- a/src/V3PreLex.l +++ b/src/V3PreLex.l @@ -5,7 +5,7 @@ * ************************************************************************** * - * Copyright 2003-2023 by Wilson Snyder. This program is free software; you + * Copyright 2003-2024 by Wilson Snyder. This program is free software; you * can redistribute it and/or modify it under the terms of either the * GNU Lesser General Public License Version 3 or the Perl Artistic License * Version 2.0. diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index 7769dd41a..26bbba4bd 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2000-2023 by Wilson Snyder. This program is free software; you +// Copyright 2000-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -455,7 +455,7 @@ void V3PreProcImp::comment(const string& text) { if (!vlcomment && !synth) return; // Short-circuit while (std::isspace(*cp)) ++cp; - string cmd = commentCleanup(string(cp)); + string cmd = commentCleanup(string{cp}); // cmd now is comment without extra spaces and "verilator" prefix if (synth) { @@ -952,17 +952,17 @@ int V3PreProcImp::getRawToken() { void V3PreProcImp::debugToken(int tok, const char* cmtp) { static int s_debugFileline = v3Global.opt.debugSrcLevel("fileline"); // --debugi-fileline 9 if (debug() >= 5) { - string buf = string(yyourtext(), yyourleng()); + string buf{yyourtext(), yyourleng()}; string::size_type pos; - while ((pos = buf.find('\n')) != string::npos) { buf.replace(pos, 1, "\\n"); } - while ((pos = buf.find('\r')) != string::npos) { buf.replace(pos, 1, "\\r"); } + while ((pos = buf.find('\n')) != string::npos) buf.replace(pos, 1, "\\n"); + while ((pos = buf.find('\r')) != string::npos) buf.replace(pos, 1, "\\r"); const string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); - fprintf(stderr, "%s: %s %s %s(%d) dr%d: <%d>%-10s: %s\n", flcol.c_str(), cmtp, - (m_off ? "of" : "on"), procStateName(state()), static_cast(m_states.size()), - static_cast(m_defRefs.size()), m_lexp->currentStartState(), tokenName(tok), - buf.c_str()); + UINFO(0, flcol << ": " << cmtp << " " << (m_off ? "of" : "on") << " " + << procStateName(state()) << "(" << static_cast(m_states.size()) + << ") dr" << m_defRefs.size() << ": <" << m_lexp->currentStartState() + << ">" << tokenName(tok) << ": " << buf << endl); if (s_debugFileline >= 9) { - std::cerr << m_lexp->m_tokFilelinep->warnContextSecondary() << endl; + std::cout << m_lexp->m_tokFilelinep->warnContextSecondary() << endl; } } } @@ -1533,15 +1533,14 @@ int V3PreProcImp::getFinalToken(string& buf) { if (!m_finAhead) { m_finAhead = true; m_finToken = getStateToken(); - m_finBuf = string(yyourtext(), yyourleng()); + m_finBuf = string{yyourtext(), yyourleng()}; } const int tok = m_finToken; buf = m_finBuf; if (false && debug() >= 5) { const string bufcln = V3PreLex::cleanDbgStrg(buf); const string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); - fprintf(stderr, "%s: FIN: %-10s: %s\n", flcol.c_str(), tokenName(tok), - bufcln.c_str()); + UINFO(0, flcol << ": FIN: " << tokenName(tok) << ": " << bufcln << endl); } // Track `line const char* bufp = buf.c_str(); @@ -1555,8 +1554,9 @@ int V3PreProcImp::getFinalToken(string& buf) { = (m_lexp->m_tokFilelinep->lastLineno() - m_finFilelinep->lastLineno())) { if (debug() >= 5) { const string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); - fprintf(stderr, "%s: FIN: readjust, fin at %d request at %d\n", flcol.c_str(), - m_finFilelinep->lastLineno(), m_lexp->m_tokFilelinep->lastLineno()); + UINFO(0, flcol << ": FIN: readjust, fin at " << m_finFilelinep->lastLineno() + << " request at " << m_lexp->m_tokFilelinep->lastLineno() + << endl); } m_finFilelinep->filename(m_lexp->m_tokFilelinep->filename()); m_finFilelinep->lineno(m_lexp->m_tokFilelinep->lastLineno()); @@ -1565,7 +1565,7 @@ int V3PreProcImp::getFinalToken(string& buf) { // Output stream is behind, send newlines to get back in sync // (Most likely because we're completing a disabled `endif) if (m_preprocp->keepWhitespace()) { - buf = string(outBehind, '\n'); + buf = std::string(outBehind, '\n'); // () for char repeat return VP_TEXT; } } else { @@ -1600,8 +1600,7 @@ string V3PreProcImp::getline() { if (debug() >= 5) { const string bufcln = V3PreLex::cleanDbgStrg(buf); const string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); - fprintf(stderr, "%s: GETFETC: %-10s: %s\n", flcol.c_str(), tokenName(tok), - bufcln.c_str()); + UINFO(0, flcol << ": GETFETC: " << tokenName(tok) << ": " << bufcln << endl); } if (tok == VP_EOF) { // Add a final newline, if the user forgot the final \n. @@ -1621,7 +1620,7 @@ string V3PreProcImp::getline() { if (debug() >= 4) { const string lncln = V3PreLex::cleanDbgStrg(theLine); const string flcol = m_lexp->m_tokFilelinep->asciiLineCol(); - fprintf(stderr, "%s: GETLINE: %s\n", flcol.c_str(), lncln.c_str()); + UINFO(0, flcol << ": GETLINE: " << lncln << endl); } return theLine; } diff --git a/src/V3PreProc.h b/src/V3PreProc.h index 13d4aefad..e57be8787 100644 --- a/src/V3PreProc.h +++ b/src/V3PreProc.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2000-2023 by Wilson Snyder. This program is free software; you +// Copyright 2000-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3PreShell.cpp b/src/V3PreShell.cpp index fc48e1f62..44d6a8ff8 100644 --- a/src/V3PreShell.cpp +++ b/src/V3PreShell.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3PreShell.h b/src/V3PreShell.h index 6972d5a67..4ebb97077 100644 --- a/src/V3PreShell.h +++ b/src/V3PreShell.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp index c6ebaacee..08ab03e69 100644 --- a/src/V3Premit.cpp +++ b/src/V3Premit.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -39,7 +39,6 @@ constexpr int STATIC_CONST_MIN_WIDTH = 256; // Minimum size to extract to stati // Premit state, as a visitor of each AstNode class PremitVisitor final : public VNVisitor { -private: // NODE STATE // AstNodeExpr::user() -> bool. True if iterated already // *::user3() -> Used when visiting AstNodeAssign @@ -50,78 +49,39 @@ private: // STATE - for current visit position (use VL_RESTORER) AstCFunc* m_cfuncp = nullptr; // Current block - int m_tmpVarCnt = 0; // Number of temporary variables created inside a function + size_t m_tmpVarCnt = 0; // Number of temporary variables created inside a function AstNode* m_stmtp = nullptr; // Current statement - AstCCall* m_callp = nullptr; // Current AstCCall - AstWhile* m_inWhilep = nullptr; // Inside while loop, special statement additions - AstTraceInc* m_inTracep = nullptr; // Inside while loop, special statement additions + AstWhile* m_inWhileCondp = nullptr; // Inside condition of this while loop bool m_assignLhs = false; // Inside assignment lhs, don't breakup extracts // METHODS - bool assignNoTemp(AstNodeAssign* nodep) { - return (VN_IS(nodep->lhsp(), VarRef) && !AstVar::scVarRecurse(nodep->lhsp()) - && VN_IS(nodep->rhsp(), Const)); - } void checkNode(AstNodeExpr* nodep) { // Consider adding a temp for this expression. - // We need to avoid adding temps to the following: - // ASSIGN(x, *here*) - // ASSIGN(CONST*here*, VARREF(!sc)) - // ARRAYSEL(*here*, ...) (No wides can be in any argument but first, - // so we don't check which arg is wide) - // ASSIGN(x, SEL*HERE*(ARRAYSEL()...) (m_assignLhs==true handles this.) - // UINFO(9, " Check: " << nodep << endl); - // UINFO(9, " Detail stmtp=" << (m_stmtp?"Y":"N") << " U=" << (nodep->user1()?"Y":"N") - // << " IW=" << (nodep->isWide()?"Y":"N") << endl); - if (m_stmtp && !nodep->user1()) { // Not already done - if (nodep->isWide()) { - if (m_assignLhs) { - } else if (nodep->firstAbovep() && VN_IS(nodep->firstAbovep(), NodeAssign) - && assignNoTemp(VN_AS(nodep->firstAbovep(), NodeAssign))) { - // Not much point if it's just a direct assignment to a constant - } else if (VN_IS(nodep->backp(), Sel) - && VN_AS(nodep->backp(), Sel)->widthp() == nodep) { - // AstSel::width must remain a constant - } else if ((nodep->firstAbovep() && VN_IS(nodep->firstAbovep(), ArraySel)) - || ((m_callp || VN_IS(m_stmtp, CStmt)) && VN_IS(nodep, ArraySel))) { - // ArraySel's are pointer refs, ignore - } else { - UINFO(4, "Cre Temp: " << nodep << endl); - createDeepTemp(nodep, false); - } - } - } + if (!m_stmtp) return; // Not under a statement + if (nodep->user1SetOnce()) return; // Already processed + if (!nodep->isWide()) return; // Not wide + if (m_assignLhs) return; // This is an lvalue! + UASSERT_OBJ(!VN_IS(nodep->firstAbovep(), ArraySel), nodep, "Should have been ignored"); + createWideTemp(nodep); } - void insertBeforeStmt(AstNode* newp) { - // Insert newp before m_stmtp - if (m_inWhilep) { - // Statements that are needed for the 'condition' in a while - // actually have to be put before & after the loop, since we - // can't do any statements in a while's (cond). - m_inWhilep->addPrecondsp(newp); - } else if (m_inTracep) { - m_inTracep->addPrecondsp(newp); - } else if (m_stmtp) { - m_stmtp->addHereThisAsNext(newp); - } else { - newp->v3fatalSrc("No statement insertion point."); - } - } - - void createDeepTemp(AstNodeExpr* nodep, bool noSubst) { - if (nodep->user1SetOnce()) return; // Only add another assignment for this node + AstVar* createWideTemp(AstNodeExpr* nodep) { + UASSERT_OBJ(m_stmtp, nodep, "Attempting to create temporary with no insertion point"); + UINFO(4, "createWideTemp: " << nodep << endl); VNRelinker relinker; nodep->unlinkFrBack(&relinker); - FileLine* const fl = nodep->fileline(); - AstVar* varp = nullptr; + FileLine* const flp = nodep->fileline(); AstConst* const constp = VN_CAST(nodep, Const); const bool useConstPool = constp // Is a constant && (constp->width() >= STATIC_CONST_MIN_WIDTH) // Large enough && !constp->num().isFourState() // Not four state && !constp->num().isString(); // Not a string + + AstVar* varp = nullptr; + AstAssign* assignp = nullptr; + if (useConstPool) { // Extract into constant pool. const bool merge = v3Global.opt.fMergeConstPool(); @@ -129,101 +89,33 @@ private: nodep->deleteTree(); ++m_extractedToConstPool; } else { - // Keep as local temporary. Name based on hash of node for output stability. - varp = new AstVar{fl, VVarType::STMTTEMP, "__Vtemp_" + cvtToStr(++m_tmpVarCnt), - nodep->dtypep()}; + // Keep as local temporary. + const std::string name = "__Vtemp_" + std::to_string(++m_tmpVarCnt); + varp = new AstVar{flp, VVarType::STMTTEMP, name, nodep->dtypep()}; m_cfuncp->addInitsp(varp); - // Put assignment before the referencing statement - insertBeforeStmt(new AstAssign{fl, new AstVarRef{fl, varp, VAccess::WRITE}, nodep}); - } - // Do not remove VarRefs to this in V3Const - if (noSubst) varp->noSubst(true); + // Put assignment before the referencing statement + assignp = new AstAssign{flp, new AstVarRef{flp, varp, VAccess::WRITE}, nodep}; + if (m_inWhileCondp) { + // Statements that are needed for the 'condition' in a while + // actually have to be put before & after the loop, since we + // can't do any statements in a while's (cond). + m_inWhileCondp->addPrecondsp(assignp); + } else { + m_stmtp->addHereThisAsNext(assignp); + } + } // Replace node with VarRef to new Var - relinker.relink(new AstVarRef{fl, varp, VAccess::READ}); + relinker.relink(new AstVarRef{flp, varp, VAccess::READ}); + + // Handle wide expressions inside the expression recursively + if (assignp) iterate(assignp); + + // Return the temporary variable + return varp; } - // VISITORS - void visit(AstNodeModule* nodep) override { - UINFO(4, " MOD " << nodep << endl); - iterateChildren(nodep); - } - void visit(AstCFunc* nodep) override { - VL_RESTORER(m_cfuncp); - VL_RESTORER(m_tmpVarCnt); - m_cfuncp = nodep; - m_tmpVarCnt = 0; - iterateChildren(nodep); - } - -#define RESTORER_START_STATEMENT() \ - VL_RESTORER(m_assignLhs); \ - VL_RESTORER(m_stmtp); - - // Must use RESTORER_START_STATEMENT() in visitors using this - void startStatement(AstNode* nodep) { - m_assignLhs = false; - if (m_cfuncp) m_stmtp = nodep; - } - - void visit(AstWhile* nodep) override { - UINFO(4, " WHILE " << nodep << endl); - RESTORER_START_STATEMENT(); - startStatement(nodep); - iterateAndNextNull(nodep->precondsp()); - startStatement(nodep); - { - VL_RESTORER(m_inWhilep); - m_inWhilep = nodep; - iterateAndNextNull(nodep->condp()); - } - startStatement(nodep); - iterateAndNextNull(nodep->stmtsp()); - iterateAndNextNull(nodep->incsp()); - } - void visit(AstNodeAssign* nodep) override { - RESTORER_START_STATEMENT(); - startStatement(nodep); - { - bool noopt = false; - { - const VNUser3InUse user3InUse; - nodep->lhsp()->foreach([](const AstVarRef* refp) { - if (refp->access().isWriteOrRW()) refp->varp()->user3(true); - }); - nodep->rhsp()->foreach([&noopt](const AstVarRef* refp) { - if (refp->access().isReadOnly() && refp->varp()->user3()) noopt = true; - }); - } - - if (noopt && !nodep->user1()) { - nodep->user1(true); - // Need to do this even if not wide, as e.g. a select may be on a wide operator - UINFO(4, "Deep temp for LHS/RHS\n"); - createDeepTemp(nodep->rhsp(), false); - } - } - iterateAndNextNull(nodep->rhsp()); - { - // VL_RESTORER(m_assignLhs); // Not needed; part of RESTORER_START_STATEMENT() - m_assignLhs = true; - iterateAndNextNull(nodep->lhsp()); - } - } - void visit(AstNodeStmt* nodep) override { - UINFO(4, " STMT " << nodep << endl); - RESTORER_START_STATEMENT(); - startStatement(nodep); - iterateChildren(nodep); - } - void visit(AstTraceInc* nodep) override { - RESTORER_START_STATEMENT(); - startStatement(nodep); - VL_RESTORER(m_inTracep); - m_inTracep = nodep; - iterateChildren(nodep); - } void visitShift(AstNodeBiop* nodep) { // Shifts of > 32/64 bits in C++ will wrap-around and generate non-0s UINFO(4, " ShiftFix " << nodep << endl); @@ -257,14 +149,107 @@ private: iterateChildren(nodep); checkNode(nodep); } + + static bool rhsReadsLhs(AstNodeAssign* nodep) { + const VNUser3InUse user3InUse; + nodep->lhsp()->foreach([](const AstVarRef* refp) { + if (refp->access().isWriteOrRW()) refp->varp()->user3(true); + }); + return nodep->rhsp()->exists([](const AstVarRef* refp) { + return refp->access().isReadOnly() && refp->varp()->user3(); + }); + } + + // VISITORS + void visit(AstCFunc* nodep) override { + UASSERT_OBJ(!m_cfuncp, nodep, "Should not nest"); + VL_RESTORER(m_cfuncp); + VL_RESTORER(m_tmpVarCnt); + m_cfuncp = nodep; + m_tmpVarCnt = 0; + iterateChildren(nodep); + } + + // VISITORS - Statements +#define START_STATEMENT_OR_RETURN(stmtp) \ + if (!m_cfuncp) return; \ + if (stmtp->user1SetOnce()) return; \ + VL_RESTORER(m_assignLhs); \ + VL_RESTORER(m_stmtp); \ + m_assignLhs = false; \ + m_stmtp = stmtp + + void visit(AstWhile* nodep) override { + UINFO(4, " WHILE " << nodep << endl); + START_STATEMENT_OR_RETURN(nodep); + iterateAndNextNull(nodep->precondsp()); + { + VL_RESTORER(m_inWhileCondp); + m_inWhileCondp = nodep; + iterateAndNextNull(nodep->condp()); + } + iterateAndNextNull(nodep->stmtsp()); + iterateAndNextNull(nodep->incsp()); + } + void visit(AstNodeAssign* nodep) override { + START_STATEMENT_OR_RETURN(nodep); + + // Direct assignment to a simple variable + if (VN_IS(nodep->lhsp(), VarRef) && !AstVar::scVarRecurse(nodep->lhsp())) { + AstNode* const rhsp = nodep->rhsp(); + // Rhs is already a var ref, so nothing to so + if (VN_IS(rhsp, VarRef) && !AstVar::scVarRecurse(rhsp)) return; + if (!VN_IS(rhsp, Const)) { + // Don't replace the rhs, it's already a simple assignment + rhsp->user1(true); + } else if (rhsp->width() < STATIC_CONST_MIN_WIDTH) { + // It's a small constant, so nothing to do, otherwise will be put to const pool + return; + } + } + + if (rhsReadsLhs(nodep)) { + // Need to do this even if not wide, as e.g. a select may be on a wide operator + createWideTemp(nodep->rhsp()); + } else { + iterateAndNextNull(nodep->rhsp()); + } + + m_assignLhs = true; // Restored by VL_RESTORER in START_STATEMENT_OR_RETURN + iterateAndNextNull(nodep->lhsp()); + } + void visit(AstDisplay* nodep) override { + START_STATEMENT_OR_RETURN(nodep); + iterateChildren(nodep); + if (v3Global.opt.autoflush()) { + const AstNode* searchp = nodep->nextp(); + while (searchp && VN_IS(searchp, Comment)) searchp = searchp->nextp(); + if (searchp && VN_IS(searchp, Display) + && nodep->filep()->sameGateTree(VN_AS(searchp, Display)->filep())) { + // There's another display next; we can just wait to flush + } else { + UINFO(4, "Autoflush " << nodep << endl); + nodep->addNextHere( + new AstFFlush{nodep->fileline(), + nodep->filep() ? nodep->filep()->cloneTreePure(true) : nullptr}); + } + } + } + void visit(AstNodeStmt* nodep) override { + START_STATEMENT_OR_RETURN(nodep); + iterateChildren(nodep); + } + +#undef START_STATEMENT_OR_RETURN + + // VISITORS - Expressions void visit(AstShiftL* nodep) override { visitShift(nodep); } void visit(AstShiftR* nodep) override { visitShift(nodep); } void visit(AstShiftRS* nodep) override { visitShift(nodep); } + + void visit(AstConst* nodep) override { checkNode(nodep); } // Operators - void visit(AstNodeTermop* nodep) override { - iterateChildren(nodep); - checkNode(nodep); - } + void visit(AstNodeTermop* nodep) override { checkNode(nodep); } void visit(AstNodeUniop* nodep) override { iterateChildren(nodep); checkNode(nodep); @@ -291,18 +276,20 @@ private: VL_RESTORER(m_assignLhs); m_assignLhs = false; iterateAndNextNull(nodep->lsbp()); - iterateAndNextNull(nodep->widthp()); + // AstSel::widthp() must remain a constant, so not iterating } checkNode(nodep); } void visit(AstArraySel* nodep) override { - iterateAndNextNull(nodep->fromp()); + // Skip straight to children. Don't replace the array + iterateChildren(nodep->fromp()); { // Only the 'from' is part of the assignment LHS VL_RESTORER(m_assignLhs); m_assignLhs = false; - iterateAndNextNull(nodep->bitp()); + // Index is never wide, so skip straight to children + iterateChildren(nodep->bitp()); } - checkNode(nodep); + // ArraySel are just pointer arithmetic and should never be replaced } void visit(AstAssocSel* nodep) override { iterateAndNextNull(nodep->fromp()); @@ -313,54 +300,27 @@ private: } checkNode(nodep); } - void visit(AstConst* nodep) override { - iterateChildren(nodep); - checkNode(nodep); - } void visit(AstNodeCond* nodep) override { iterateChildren(nodep); if (nodep->thenp()->isWide() && !VN_IS(nodep->condp(), Const) && !VN_IS(nodep->condp(), VarRef)) { // We're going to need the expression several times in the expanded code, // so might as well make it a common expression - createDeepTemp(nodep->condp(), false); + createWideTemp(nodep->condp()); VIsCached::clearCacheTree(); } checkNode(nodep); } - void visit(AstCCall* nodep) override { - VL_RESTORER(m_callp); - m_callp = nodep; - iterateChildren(nodep); - } - - // Autoflush - void visit(AstDisplay* nodep) override { - RESTORER_START_STATEMENT(); - startStatement(nodep); - iterateChildren(nodep); - if (v3Global.opt.autoflush()) { - const AstNode* searchp = nodep->nextp(); - while (searchp && VN_IS(searchp, Comment)) searchp = searchp->nextp(); - if (searchp && VN_IS(searchp, Display) - && nodep->filep()->sameGateTree(VN_AS(searchp, Display)->filep())) { - // There's another display next; we can just wait to flush - } else { - UINFO(4, "Autoflush " << nodep << endl); - nodep->addNextHere( - new AstFFlush{nodep->fileline(), - nodep->filep() ? nodep->filep()->cloneTreePure(true) : nullptr}); - } - } - } void visit(AstSFormatF* nodep) override { iterateChildren(nodep); // Any strings sent to a display must be var of string data type, // to avoid passing a pointer to a temporary. - for (AstNodeExpr* expp = nodep->exprsp(); expp; expp = VN_AS(expp->nextp(), NodeExpr)) { - if (expp->dtypep()->basicp() && expp->dtypep()->basicp()->isString() - && !VN_IS(expp, VarRef)) { - createDeepTemp(expp, true); + for (AstNodeExpr *expp = nodep->exprsp(), *nextp; expp; expp = nextp) { + nextp = VN_AS(expp->nextp(), NodeExpr); + if (expp->isString() && !VN_IS(expp, VarRef)) { + AstVar* const varp = createWideTemp(expp); + // Do not remove VarRefs to this in V3Const + varp->noSubst(true); } } } diff --git a/src/V3Premit.h b/src/V3Premit.h index e625392f0..ac4c19ac0 100644 --- a/src/V3Premit.h +++ b/src/V3Premit.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp index 0fa0c4c2a..9d1efe086 100644 --- a/src/V3ProtectLib.cpp +++ b/src/V3ProtectLib.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,7 +30,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // ProtectLib top-level visitor class ProtectVisitor final : public VNVisitor { -private: AstVFile* m_vfilep = nullptr; // DPI-enabled Verilog wrapper AstCFile* m_cfilep = nullptr; // C implementation of DPI functions // Verilog text blocks diff --git a/src/V3ProtectLib.h b/src/V3ProtectLib.h index 7c1361573..5fe6e4b3c 100644 --- a/src/V3ProtectLib.h +++ b/src/V3ProtectLib.h @@ -1,12 +1,12 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* -// DESCRIPTION: Verilator: Buitd DPI protected C++ and SV +// DESCRIPTION: Verilator: Build DPI protected C++ and SV // // Code available from: https://verilator.org // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 755e13fb4..ecdd7824e 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -36,7 +36,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Visitor that marks classes needing a randomize() method class RandomizeMarkVisitor final : public VNVisitorConst { -private: // NODE STATE // Cleared on Netlist // AstClass::user1() -> bool. Set true to indicate needs randomize processing @@ -128,7 +127,6 @@ public: // Visitor that defines a randomize method where needed class RandomizeVisitor final : public VNVisitor { -private: // NODE STATE // Cleared on Netlist // AstClass::user1() -> bool. Set true to indicate needs randomize processing @@ -198,7 +196,7 @@ private: AstBasicDType* const basicp = varp->dtypep()->skipRefp()->basicp(); UASSERT_OBJ(basicp, varp, "Unexpected randc variable dtype"); if (basicp->width() > 32) { - varp->v3error("Maxiumum implemented width for randc is 32 bits, " + varp->v3error("Maximum implemented width for randc is 32 bits, " << varp->prettyNameQ() << " is " << basicp->width() << " bits"); varp->isRandC(false); varp->isRand(true); @@ -358,6 +356,10 @@ private: addPrePostCall(nodep, funcp, "post_randomize"); nodep->user1(false); } + void visit(AstConstraint* nodep) override { + nodep->v3warn(CONSTRAINTIGN, "Constraint ignored (unsupported)"); + if (!v3Global.opt.xmlOnly()) VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep); + } void visit(AstRandCase* nodep) override { // RANDCASE // CASEITEM expr1 : stmt1 diff --git a/src/V3Randomize.h b/src/V3Randomize.h index 5de300667..24e0fb994 100644 --- a/src/V3Randomize.h +++ b/src/V3Randomize.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp index 9700bce27..3149ac55d 100644 --- a/src/V3Reloop.cpp +++ b/src/V3Reloop.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -40,7 +40,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class ReloopVisitor final : public VNVisitor { -private: // NODE STATE // AstCFunc::user1p -> Var* for temp var, 0=not set yet const VNUser1InUse m_inuser1; diff --git a/src/V3Reloop.h b/src/V3Reloop.h index 4408bcb8d..61fbaafcb 100644 --- a/src/V3Reloop.h +++ b/src/V3Reloop.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Rtti.h b/src/V3Rtti.h index f787ef8c7..87f2b2e2e 100644 --- a/src/V3Rtti.h +++ b/src/V3Rtti.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp index 926379d97..59014e149 100644 --- a/src/V3Sched.cpp +++ b/src/V3Sched.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -170,22 +170,25 @@ AstNodeStmt* profExecSectionPop(FileLine* flp) { struct EvalLoop { // Flag set to true during the first iteration of the loop AstVarScope* firstIterp; - // The loop continuation flag (set to true to loop again) - AstVarScope* continuep = nullptr; // The loop itself and statements around it AstNodeStmt* stmtsp = nullptr; }; // Create an eval loop with all the trimmings. -EvalLoop createEvalLoop(AstNetlist* netlistp, // - const std::string& tag, // Tag for current phase - const string& name, // Name of current phase - bool slow, // Should create slow functions - AstVarScope* trigp, // The trigger vector - AstCFunc* dumpFuncp, // Trigger dump function for debugging only - AstNodeStmt* innerp, // The inner loop, if any - AstNodeStmt* phasePrepp, // Prep statements run before checking triggers - AstNodeStmt* phaseWorkp // The work to do if anything triggered +EvalLoop createEvalLoop( + AstNetlist* netlistp, // + const std::string& tag, // Tag for current phase + const string& name, // Name of current phase + bool slow, // Should create slow functions + AstVarScope* trigp, // The trigger vector + AstCFunc* dumpFuncp, // Trigger dump function for debugging only + AstNodeStmt* innerp, // The inner loop, if any + AstNodeStmt* phasePrepp, // Prep statements run before checking triggers + AstNodeStmt* phaseWorkp, // The work to do if anything triggered + // Extra statements to run after the work, even if no triggers fired. This function is + // passed a variable, which must be set to true if we must continue and loop again, + // and must be unmodified otherwise. + std::function phaseExtra = [](AstVarScope*) { return nullptr; } // ) { const std::string varPrefix = "__V" + tag; AstScope* const scopeTopp = netlistp->topScopep()->scopep(); @@ -213,6 +216,9 @@ EvalLoop createEvalLoop(AstNetlist* netlistp, // ifp->addThensp(phaseWorkp); phaseFuncp->addStmtsp(ifp); + // Construct the extra statements + if (AstNodeStmt* const extrap = phaseExtra(executeFlagp)) phaseFuncp->addStmtsp(extrap); + // The function returns ture iff it did run the work phaseFuncp->rtnType("bool"); phaseFuncp->addStmtsp( @@ -272,7 +278,7 @@ EvalLoop createEvalLoop(AstNetlist* netlistp, // // Prof-exec section pop if (v3Global.opt.profExec()) stmtps->addNext(profExecSectionPop(flp)); - return {firstIterFlagp, continueFlagp, stmtps}; + return {firstIterFlagp, stmtps}; } //============================================================================ @@ -429,7 +435,8 @@ void orderSequentially(AstCFunc* funcp, const LogicByScope& lbs) { if (procp->isSuspendable()) { funcp->slow(false); subFuncp = createNewSubFuncp(scopep); - subFuncp->name(subFuncp->name() + "__" + cvtToStr(scopep->user2Inc())); + subFuncp->name(subFuncp->name() + "__Vtiming__" + + cvtToStr(scopep->user2Inc())); subFuncp->rtnType("VlCoroutine"); if (VN_IS(procp, Always)) { subFuncp->slow(false); @@ -507,16 +514,16 @@ struct TriggerKit { m_funcp->stmtsp()->addHereThisAsNext(callp->makeStmt()); } - // Utility to set then clear the dpiExportTrigger trigger - void addDpiExportTriggerAssignment(AstVarScope* dpiExportTriggerVscp, uint32_t index) const { - FileLine* const flp = dpiExportTriggerVscp->fileline(); + // Utility to set then clear an extra trigger + void addExtraTriggerAssignment(AstVarScope* extraTriggerVscp, uint32_t index) const { + FileLine* const flp = extraTriggerVscp->fileline(); AstVarRef* const vrefp = new AstVarRef{flp, m_vscp, VAccess::WRITE}; AstCMethodHard* const callp = new AstCMethodHard{flp, vrefp, "set"}; callp->addPinsp(new AstConst{flp, index}); - callp->addPinsp(new AstVarRef{flp, dpiExportTriggerVscp, VAccess::READ}); + callp->addPinsp(new AstVarRef{flp, extraTriggerVscp, VAccess::READ}); callp->dtypeSetVoid(); AstNode* const stmtp = callp->makeStmt(); - stmtp->addNext(new AstAssign{flp, new AstVarRef{flp, dpiExportTriggerVscp, VAccess::WRITE}, + stmtp->addNext(new AstAssign{flp, new AstVarRef{flp, extraTriggerVscp, VAccess::WRITE}, new AstConst{flp, AstConst::BitFalse{}}}); m_funcp->stmtsp()->addHereThisAsNext(stmtp); } @@ -575,6 +582,17 @@ public: const string& description(size_t index) const { return m_descriptions[index]; } }; +//============================================================================ +// Helper that creates virtual interface trigger resets + +void addVirtIfaceTriggerAssignments(const VirtIfaceTriggers& virtIfaceTriggers, + size_t vifTriggerIndex, const TriggerKit& actTrig) { + for (const auto& p : virtIfaceTriggers) { + actTrig.addExtraTriggerAssignment(p.second, vifTriggerIndex); + ++vifTriggerIndex; + } +} + //============================================================================ // Create a TRIGGERVEC and the related TriggerKit for the given AstSenTree vector @@ -807,7 +825,8 @@ void createSettle(AstNetlist* netlistp, AstCFunc* const initFuncp, SenExprBuilde // Order the replicated combinational logic to create the 'ico' region AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, - SenExprBuilder& senExprBuilder, LogicByScope& logic) { + SenExprBuilder& senExprBuilder, LogicByScope& logic, + const VirtIfaceTriggers& virtIfaceTriggers) { // Nothing to do if no combinational logic is sensitive to top level inputs if (logic.empty()) return nullptr; @@ -833,6 +852,10 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, const size_t dpiExportTriggerIndex = dpiExportTriggerVscp ? extraTriggers.allocate("DPI export trigger") : std::numeric_limits::max(); + const size_t firstVifTriggerIndex = extraTriggers.size(); + for (const auto& p : virtIfaceTriggers) { + extraTriggers.allocate("virtual interface: " + p.first->name()); + } // Gather the relevant sensitivity expressions and create the trigger kit const auto& senTreeps = getSenTreesUsedBy({&logic}); @@ -840,8 +863,9 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, = createTriggers(netlistp, initFuncp, senExprBuilder, senTreeps, "ico", extraTriggers); if (dpiExportTriggerVscp) { - trig.addDpiExportTriggerAssignment(dpiExportTriggerVscp, dpiExportTriggerIndex); + trig.addExtraTriggerAssignment(dpiExportTriggerVscp, dpiExportTriggerIndex); } + addVirtIfaceTriggerAssignments(virtIfaceTriggers, firstVifTriggerIndex, trig); // Remap sensitivities remapSensitivities(logic, trig.m_map); @@ -858,6 +882,8 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, AstSenTree* const dpiExportTriggered = dpiExportTriggerVscp ? createTriggerSenTree(netlistp, trig.m_vscp, dpiExportTriggerIndex) : nullptr; + const auto& vifTriggered + = virtIfaceTriggers.makeIfaceToSensMap(netlistp, firstVifTriggerIndex, trig.m_vscp); // Create and Order the body function AstCFunc* const icoFuncp @@ -868,6 +894,10 @@ AstNode* createInputCombLoop(AstNetlist* netlistp, AstCFunc* const initFuncp, out.push_back(inputChanged); } if (varp->isWrittenByDpi()) out.push_back(dpiExportTriggered); + if (vscp->varp()->sensIfacep()) { + const auto it = vifTriggered.find(vscp->varp()->sensIfacep()); + if (it != vifTriggered.end()) out.push_back(it->second); + } }); splitCheck(icoFuncp); @@ -987,25 +1017,27 @@ void createEval(AstNetlist* netlistp, // workp->addNext(createTriggerClearCall(flp, nbaKit.m_vscp)); // return workp; - }()); + }(), + // Extra work (not conditional on having had a fired trigger) + [&](AstVarScope* continuep) -> AstNodeStmt* { + // Check if any dynamic NBAs are pending, if there are any in the design + if (!netlistp->nbaEventp()) return nullptr; + AstVarScope* const nbaEventp = netlistp->nbaEventp(); + AstVarScope* const nbaEventTriggerp = netlistp->nbaEventTriggerp(); + UASSERT(nbaEventTriggerp, "NBA event trigger var should exist"); + netlistp->nbaEventp(nullptr); + netlistp->nbaEventTriggerp(nullptr); - // If the NBA event exists, trigger it in 'nba' - if (AstVarScope* const nbaEventp = netlistp->nbaEventp()) { - AstVarScope* const nbaEventTriggerp = netlistp->nbaEventTriggerp(); - UASSERT(nbaEventTriggerp, "NBA event trigger var should exist"); - netlistp->nbaEventp(nullptr); - netlistp->nbaEventTriggerp(nullptr); - - AstIf* const ifp = new AstIf{flp, new AstVarRef{flp, nbaEventTriggerp, VAccess::READ}}; - ifp->addThensp(setVar(topLoop.continuep, 1)); - ifp->addThensp(setVar(nbaEventTriggerp, 0)); - AstCMethodHard* const firep - = new AstCMethodHard{flp, new AstVarRef{flp, nbaEventp, VAccess::WRITE}, "fire"}; - firep->dtypeSetVoid(); - ifp->addThensp(firep->makeStmt()); - // actLoop.stmtsp happens to be the head of the loop body inside the NBA loop... - actLoop.stmtsp->addNext(ifp); - } + // If a dynamic NBA is pending, clear the pending flag and fire the commit event + AstIf* const ifp = new AstIf{flp, new AstVarRef{flp, nbaEventTriggerp, VAccess::READ}}; + ifp->addThensp(setVar(continuep, 1)); + ifp->addThensp(setVar(nbaEventTriggerp, 0)); + AstCMethodHard* const firep + = new AstCMethodHard{flp, new AstVarRef{flp, nbaEventp, VAccess::WRITE}, "fire"}; + firep->dtypeSetVoid(); + ifp->addThensp(firep->makeStmt()); + return ifp; + }); if (!obsKit.empty()) { // Create the Observed eval loop, which becomes the top level loop. @@ -1069,6 +1101,21 @@ void createEval(AstNetlist* netlistp, // } // namespace +//============================================================================ +// Helper that builds virtual interface trigger sentrees + +VirtIfaceTriggers::IfaceSensMap +VirtIfaceTriggers::makeIfaceToSensMap(AstNetlist* const netlistp, size_t vifTriggerIndex, + AstVarScope* trigVscp) const { + std::map ifaceToSensMap; + for (const auto& p : *this) { + ifaceToSensMap.emplace( + std::make_pair(p.first, createTriggerSenTree(netlistp, trigVscp, vifTriggerIndex))); + ++vifTriggerIndex; + } + return ifaceToSensMap; +} + //============================================================================ // Top level entry-point to scheduling @@ -1079,7 +1126,10 @@ void schedule(AstNetlist* netlistp) { V3Stats::addStat("Scheduling, " + name, size); }; - // Step 0. Prepare timing-related logic and external domains + // Step 0. Prepare external domains for timing and virtual interfaces + // Create extra triggers for virtual interfaces + const auto& virtIfaceTriggers = makeVirtIfaceTriggers(netlistp); + // Prepare timing-related logic and external domains TimingKit timingKit = prepareTiming(netlistp); // Step 1. Gather and classify all logic in the design @@ -1144,8 +1194,8 @@ void schedule(AstNetlist* netlistp) { } // Step 7: Create input combinational logic loop - AstNode* const icoLoopp - = createInputCombLoop(netlistp, initp, senExprBuilder, logicReplicas.m_ico); + AstNode* const icoLoopp = createInputCombLoop(netlistp, initp, senExprBuilder, + logicReplicas.m_ico, virtIfaceTriggers); if (v3Global.opt.stats()) V3Stats::statsStage("sched-create-ico"); // Step 8: Create the pre/act/nba triggers @@ -1156,6 +1206,10 @@ void schedule(AstNetlist* netlistp) { const size_t dpiExportTriggerIndex = dpiExportTriggerVscp ? extraTriggers.allocate("DPI export trigger") : std::numeric_limits::max(); + const size_t firstVifTriggerIndex = extraTriggers.size(); + for (const auto& p : virtIfaceTriggers) { + extraTriggers.allocate("virtual interface: " + p.first->name()); + } const auto& senTreeps = getSenTreesUsedBy({&logicRegions.m_pre, // &logicRegions.m_act, // @@ -1170,8 +1224,9 @@ void schedule(AstNetlist* netlistp) { if (timingKit.m_postUpdates) actTrig.m_funcp->addStmtsp(timingKit.m_postUpdates); if (dpiExportTriggerVscp) { - actTrig.addDpiExportTriggerAssignment(dpiExportTriggerVscp, dpiExportTriggerIndex); + actTrig.addExtraTriggerAssignment(dpiExportTriggerVscp, dpiExportTriggerIndex); } + addVirtIfaceTriggerAssignments(virtIfaceTriggers, firstVifTriggerIndex, actTrig); AstVarScope* const actTrigVscp = actTrig.m_vscp; AstVarScope* const preTrigVscp = scopeTopp->createTempLike("__VpreTriggered", actTrigVscp); @@ -1223,12 +1278,19 @@ void schedule(AstNetlist* netlistp) { ? createTriggerSenTree(netlistp, actTrig.m_vscp, dpiExportTriggerIndex) : nullptr; + const auto& vifTriggeredAct + = virtIfaceTriggers.makeIfaceToSensMap(netlistp, firstVifTriggerIndex, actTrig.m_vscp); + AstCFunc* const actFuncp = V3Order::order( netlistp, {&logicRegions.m_pre, &logicRegions.m_act, &logicReplicas.m_act}, trigToSenAct, "act", false, false, [&](const AstVarScope* vscp, std::vector& out) { auto it = actTimingDomains.find(vscp); if (it != actTimingDomains.end()) out = it->second; if (vscp->varp()->isWrittenByDpi()) out.push_back(dpiExportTriggeredAct); + if (vscp->varp()->sensIfacep()) { + const auto sit = vifTriggeredAct.find(vscp->varp()->sensIfacep()); + if (sit != vifTriggeredAct.end()) out.push_back(sit->second); + } }); splitCheck(actFuncp); if (v3Global.opt.stats()) V3Stats::statsStage("sched-create-act"); @@ -1252,6 +1314,8 @@ void schedule(AstNetlist* netlistp) { = dpiExportTriggerVscp ? createTriggerSenTree(netlistp, trigVscp, dpiExportTriggerIndex) : nullptr; + const auto& vifTriggered + = virtIfaceTriggers.makeIfaceToSensMap(netlistp, firstVifTriggerIndex, trigVscp); const auto& timingDomains = timingKit.remapDomains(trigMap); AstCFunc* const funcp = V3Order::order( @@ -1260,6 +1324,10 @@ void schedule(AstNetlist* netlistp) { auto it = timingDomains.find(vscp); if (it != timingDomains.end()) out = it->second; if (vscp->varp()->isWrittenByDpi()) out.push_back(dpiExportTriggered); + if (vscp->varp()->sensIfacep()) { + const auto sit = vifTriggered.find(vscp->varp()->sensIfacep()); + if (sit != vifTriggered.end()) out.push_back(sit->second); + } }); // Create the trigger dumping function, which is the same as act trigger diff --git a/src/V3Sched.h b/src/V3Sched.h index fca742de4..27a4264d5 100644 --- a/src/V3Sched.h +++ b/src/V3Sched.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -149,6 +149,27 @@ public: TimingKit& operator=(TimingKit&&) = default; }; +class VirtIfaceTriggers final { + using IfaceTrigger = std::pair; + using IfaceTriggerVec = std::vector; + using IfaceSensMap = std::map; + IfaceTriggerVec m_triggers; + +public: + void emplace_back(IfaceTrigger&& p) { m_triggers.emplace_back(std::move(p)); } + IfaceTriggerVec::const_iterator begin() const { return m_triggers.begin(); } + IfaceTriggerVec::const_iterator end() const { return m_triggers.end(); } + IfaceSensMap makeIfaceToSensMap(AstNetlist* netlistp, size_t vifTriggerIndex, + AstVarScope* trigVscp) const; + VL_UNCOPYABLE(VirtIfaceTriggers); + VirtIfaceTriggers() = default; + VirtIfaceTriggers(VirtIfaceTriggers&&) = default; + VirtIfaceTriggers& operator=(VirtIfaceTriggers&&) = default; +}; + +// Creates trigger vars for signals driven via virtual interfaces +VirtIfaceTriggers makeVirtIfaceTriggers(AstNetlist* nodep) VL_MT_DISABLED; + // Creates the timing kit and marks variables written by suspendables TimingKit prepareTiming(AstNetlist* const netlistp) VL_MT_DISABLED; diff --git a/src/V3SchedAcyclic.cpp b/src/V3SchedAcyclic.cpp index f70022350..b968d5b91 100644 --- a/src/V3SchedAcyclic.cpp +++ b/src/V3SchedAcyclic.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3SchedPartition.cpp b/src/V3SchedPartition.cpp index e381b2727..1b07fbb06 100644 --- a/src/V3SchedPartition.cpp +++ b/src/V3SchedPartition.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -184,7 +184,7 @@ class SchedGraphBuilder final : public VNVisitor { // Clocked or hybrid logic has explicit sensitivity, so add edge from sensitivity vertex if (!m_senTreep->hasCombo()) { - m_senTreep->foreach([=](AstSenItem* senItemp) { + m_senTreep->foreach([this, nodep, logicVtxp](AstSenItem* senItemp) { if (senItemp->isIllegal()) return; UASSERT_OBJ(senItemp->isClocked() || senItemp->isHybrid(), nodep, "Non-clocked SenItem under clocked SenTree"); @@ -194,7 +194,7 @@ class SchedGraphBuilder final : public VNVisitor { } // Add edges based on references - nodep->foreach([=](const AstVarRef* vrefp) { + nodep->foreach([this, logicVtxp](const AstVarRef* vrefp) { AstVarScope* const vscp = vrefp->varScopep(); if (vrefp->access().isReadOrRW() && m_readTriggersThisLogic(vscp)) { new V3GraphEdge{m_graphp, getVarVertex(vscp), logicVtxp, 10}; @@ -206,7 +206,7 @@ class SchedGraphBuilder final : public VNVisitor { // If the logic calls a 'context' DPI import, it might fire the DPI Export trigger if (m_dpiExportTriggerp) { - nodep->foreach([=](const AstCCall* callp) { + nodep->foreach([this, logicVtxp](const AstCCall* callp) { if (!callp->funcp()->dpiImportWrapper()) return; if (!callp->funcp()->dpiContext()) return; new V3GraphEdge{m_graphp, logicVtxp, getVarVertex(m_dpiExportTriggerp), 10}; diff --git a/src/V3SchedReplicate.cpp b/src/V3SchedReplicate.cpp index 9ef1fcdb0..5b0256210 100644 --- a/src/V3SchedReplicate.cpp +++ b/src/V3SchedReplicate.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -121,7 +121,8 @@ public: : SchedReplicateVertex{graphp} , m_vscp{vscp} { // Top level inputs are - if (varp()->isPrimaryInish() || varp()->isSigUserRWPublic() || varp()->isWrittenByDpi()) { + if (varp()->isPrimaryInish() || varp()->isSigUserRWPublic() || varp()->isWrittenByDpi() + || varp()->sensIfacep()) { addDrivingRegions(INPUT); } // Currently we always execute suspendable processes at the beginning of diff --git a/src/V3SchedTiming.cpp b/src/V3SchedTiming.cpp index 368201f05..d83d82e61 100644 --- a/src/V3SchedTiming.cpp +++ b/src/V3SchedTiming.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -67,11 +67,22 @@ AstCCall* TimingKit::createResume(AstNetlist* const netlistp) { m_resumeFuncp->isConst(false); m_resumeFuncp->declPrivate(true); scopeTopp->addBlocksp(m_resumeFuncp); + + // Put all the timing actives in the resume function + AstActive* dlyShedActivep = nullptr; for (auto& p : m_lbs) { - // Put all the timing actives in the resume function AstActive* const activep = p.second; + // Hack to ensure that #0 delays will be executed after any other `act` events. + // Just handle delayed coroutines last. + AstVarRef* const schedrefp = VN_AS( + VN_AS(VN_AS(activep->stmtsp(), StmtExpr)->exprp(), CMethodHard)->fromp(), VarRef); + if (schedrefp->varScopep()->dtypep()->basicp()->isDelayScheduler()) { + dlyShedActivep = activep; + continue; + } m_resumeFuncp->addStmtsp(activep); } + if (dlyShedActivep) m_resumeFuncp->addStmtsp(dlyShedActivep); } AstCCall* const callp = new AstCCall{m_resumeFuncp->fileline(), m_resumeFuncp}; callp->dtypeSetVoid(); @@ -135,7 +146,6 @@ AstCCall* TimingKit::createCommit(AstNetlist* const netlistp) { TimingKit prepareTiming(AstNetlist* const netlistp) { if (!v3Global.usesTiming()) return {}; class AwaitVisitor final : public VNVisitor { - private: // NODE STATE // AstSenTree::user1() -> bool. Set true if the sentree has been visited. const VNUser1InUse m_inuser1; @@ -266,7 +276,6 @@ void transformForks(AstNetlist* const netlistp) { if (!v3Global.usesTiming()) return; // Transform all forked processes into functions class ForkVisitor final : public VNVisitor { - private: // NODE STATE // AstVar::user1() -> bool. Set true if the variable was declared before the current // fork. @@ -288,7 +297,8 @@ void transformForks(AstNetlist* const netlistp) { funcp->foreach([&](AstNodeVarRef* refp) { AstVar* const varp = refp->varp(); AstBasicDType* const dtypep = varp->dtypep()->basicp(); - bool passByValue = false; + // If not a fork..join, copy. All write refs should've been handled by V3Fork + bool passByValue = !m_forkp->joinType().join(); if (!varp->isFuncLocal()) { if (VString::startsWith(varp->name(), "__Vintra")) { // Pass it by value to the new function, as otherwise there are issues with diff --git a/src/V3SchedVirtIface.cpp b/src/V3SchedVirtIface.cpp new file mode 100644 index 000000000..270c62aae --- /dev/null +++ b/src/V3SchedVirtIface.cpp @@ -0,0 +1,234 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Create triggers necessary for scheduling across +// virtual interfaces +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* +// V3SchedVirtIface's Transformations: +// +// Each interface type written to via virtual interface, or written to normally but read via +// virtual interface: +// Create a trigger var for it +// Each AssignW, AssignPost: +// If it writes to a virtual interface, or to a variable read via virtual interface: +// Convert to an always +// Each statement: +// If it writes to a virtual interface, or to a variable read via virtual interface: +// Set the corresponding trigger to 1 +// If the write is done by an AssignDly, the trigger is also set by AssignDly +// +//************************************************************************* + +#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT + +#include "V3AstNodeExpr.h" +#include "V3Sched.h" +#include "V3UniqueNames.h" + +VL_DEFINE_DEBUG_FUNCTIONS; + +namespace V3Sched { + +namespace { + +class VirtIfaceVisitor final : public VNVisitor { +private: + // NODE STATE + // AstIface::user1() -> AstVarScope*. Trigger var for this interface + const VNUser1InUse m_user1InUse; + + // TYPES + using OnWriteToVirtIface = std::function; + + // STATE + AstNetlist* const m_netlistp; // Root node + AstAssign* m_trigAssignp = nullptr; // Previous/current trigger assignment + AstIface* m_trigAssignIfacep = nullptr; // Interface type whose trigger is assigned + // by m_trigAssignp + V3UniqueNames m_vifTriggerNames{"__VvifTrigger"}; // Unique names for virt iface + // triggers + VirtIfaceTriggers m_triggers; // Interfaces and corresponding trigger vars + + // METHODS + // For each write across a virtual interface boundary + static void foreachWrittenVirtIface(AstNode* const nodep, const OnWriteToVirtIface& onWrite) { + nodep->foreach([&](AstVarRef* const refp) { + if (refp->access().isReadOnly()) return; + if (AstIfaceRefDType* const dtypep = VN_CAST(refp->varp()->dtypep(), IfaceRefDType)) { + if (dtypep->isVirtual() && VN_IS(refp->firstAbovep(), MemberSel)) { + onWrite(refp, dtypep->ifacep()); + } + } else if (AstIface* const ifacep = refp->varp()->sensIfacep()) { + onWrite(refp, ifacep); + } + }); + } + // Returns true if there is a write across a virtual interface boundary + static bool writesToVirtIface(const AstNode* const nodep) { + return nodep->exists([](const AstVarRef* const refp) { + if (!refp->access().isWriteOrRW()) return false; + AstIfaceRefDType* const dtypep = VN_CAST(refp->varp()->dtypep(), IfaceRefDType); + const bool writesToVirtIfaceMember + = (dtypep && dtypep->isVirtual() && VN_IS(refp->firstAbovep(), MemberSel)); + const bool writesToIfaceSensVar = refp->varp()->sensIfacep(); + return writesToVirtIfaceMember || writesToIfaceSensVar; + }); + } + // Error on write across a virtual interface boundary + static void unsupportedWriteToVirtIface(AstNode* nodep, const char* locationp) { + if (!nodep) return; + foreachWrittenVirtIface(nodep, [locationp](AstVarRef* const selp, AstIface*) { + selp->v3warn(E_UNSUPPORTED, + "Unsupported: write to virtual interface in " << locationp); + }); + } + // Create trigger var for the given interface if it doesn't exist; return a write ref to it + AstVarRef* createVirtIfaceTriggerRefp(FileLine* const flp, AstIface* ifacep) { + if (!ifacep->user1()) { + AstScope* const scopeTopp = m_netlistp->topScopep()->scopep(); + AstVarScope* const vscp = scopeTopp->createTemp(m_vifTriggerNames.get(ifacep), 1); + ifacep->user1p(vscp); + m_triggers.emplace_back(std::make_pair(ifacep, vscp)); + } + return new AstVarRef{flp, VN_AS(ifacep->user1p(), VarScope), VAccess::WRITE}; + } + + // VISITORS + void visit(AstNodeProcedure* nodep) override { + VL_RESTORER(m_trigAssignp); + m_trigAssignp = nullptr; + VL_RESTORER(m_trigAssignIfacep); + m_trigAssignIfacep = nullptr; + iterateChildren(nodep); + } + void visit(AstCFunc* nodep) override { + VL_RESTORER(m_trigAssignp); + m_trigAssignp = nullptr; + VL_RESTORER(m_trigAssignIfacep); + m_trigAssignIfacep = nullptr; + iterateChildren(nodep); + } + void visit(AstAssignW* nodep) override { + if (writesToVirtIface(nodep)) { + // Convert to always, as we have to assign the trigger var + nodep->convertToAlways(); + } + } + void visit(AstAssignPost* nodep) override { + if (writesToVirtIface(nodep)) { + // Convert to always, as we have to assign the trigger var + FileLine* const flp = nodep->fileline(); + AstAlwaysPost* const postp = new AstAlwaysPost{flp, nullptr, nullptr}; + nodep->replaceWith(postp); + postp->addStmtsp( + new AstAssign{flp, nodep->lhsp()->unlinkFrBack(), nodep->rhsp()->unlinkFrBack()}); + nodep->deleteTree(); + } + } + void visit(AstNodeIf* nodep) override { + unsupportedWriteToVirtIface(nodep->condp(), "if condition"); + { + VL_RESTORER(m_trigAssignp); + VL_RESTORER(m_trigAssignIfacep); + iterateAndNextNull(nodep->thensp()); + } + { + VL_RESTORER(m_trigAssignp); + VL_RESTORER(m_trigAssignIfacep); + iterateAndNextNull(nodep->elsesp()); + } + if (v3Global.usesTiming()) { + // Clear the trigger assignment, as there could have been timing controls in either + // branch + m_trigAssignp = nullptr; + m_trigAssignIfacep = nullptr; + } + } + void visit(AstWhile* nodep) override { + unsupportedWriteToVirtIface(nodep->precondsp(), "loop condition"); + unsupportedWriteToVirtIface(nodep->condp(), "loop condition"); + unsupportedWriteToVirtIface(nodep->incsp(), "loop increment statement"); + { + VL_RESTORER(m_trigAssignp); + VL_RESTORER(m_trigAssignIfacep); + iterateAndNextNull(nodep->stmtsp()); + } + if (v3Global.usesTiming()) { + // Clear the trigger assignment, as there could have been timing controls in the loop + m_trigAssignp = nullptr; + m_trigAssignIfacep = nullptr; + } + } + void visit(AstJumpBlock* nodep) override { + { + VL_RESTORER(m_trigAssignp); + VL_RESTORER(m_trigAssignIfacep); + iterateChildren(nodep); + } + if (v3Global.usesTiming()) { + // Clear the trigger assignment, as there could have been timing controls in the jump + // block + m_trigAssignp = nullptr; + m_trigAssignIfacep = nullptr; + } + } + void visit(AstNodeStmt* nodep) override { + if (v3Global.usesTiming() + && nodep->exists([](AstNode* nodep) { return nodep->isTimingControl(); })) { + m_trigAssignp = nullptr; // Could be after a delay - need new trigger assignment + m_trigAssignIfacep = nullptr; + // No restorer, as following statements should not reuse the old assignment + } + FileLine* const flp = nodep->fileline(); + foreachWrittenVirtIface(nodep, [&](AstVarRef*, AstIface* ifacep) { + if (ifacep != m_trigAssignIfacep) { + // Write to different interface type than before - need new trigger assignment + // No restorer, as following statements should not reuse the old assignment + m_trigAssignIfacep = ifacep; + m_trigAssignp = nullptr; + } + if (!m_trigAssignp) { + m_trigAssignp = new AstAssign{flp, createVirtIfaceTriggerRefp(flp, ifacep), + new AstConst{flp, AstConst::BitTrue{}}}; + nodep->addNextHere(m_trigAssignp); + } + }); + } + void visit(AstNodeExpr*) override {} // Accelerate + void visit(AstNode* nodep) override { iterateChildren(nodep); } + +public: + // CONSTRUCTORS + explicit VirtIfaceVisitor(AstNetlist* nodep) + : m_netlistp{nodep} { + iterate(nodep); + } + ~VirtIfaceVisitor() override = default; + + // METHODS + VirtIfaceTriggers take_triggers() { return std::move(m_triggers); } +}; + +} //namespace + +VirtIfaceTriggers makeVirtIfaceTriggers(AstNetlist* nodep) { + UINFO(2, __FUNCTION__ << ": " << endl); + if (v3Global.hasVirtIfaces()) { + VirtIfaceVisitor visitor{nodep}; + V3Global::dumpCheckGlobalTree("sched_vif", 0, dumpTreeLevel() >= 6); + return visitor.take_triggers(); + } + return {}; +} + +} //namespace V3Sched diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp index 4f6efb93e..c8eb247d2 100644 --- a/src/V3Scope.cpp +++ b/src/V3Scope.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -34,7 +34,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Scope class functions class ScopeVisitor final : public VNVisitor { -private: // NODE STATE // AstVar::user1p -> AstVarScope replacement for this variable // AstCell::user2p -> AstScope*. The scope created inside the cell @@ -335,7 +334,6 @@ public: // Scope cleanup -- remove unused activates class ScopeCleanupVisitor final : public VNVisitor { -private: // STATE AstScope* m_scopep = nullptr; // Current scope we are building diff --git a/src/V3Scope.h b/src/V3Scope.h index 5e5760554..8c9cd8d27 100644 --- a/src/V3Scope.h +++ b/src/V3Scope.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Scoreboard.cpp b/src/V3Scoreboard.cpp index 1a26dbc2f..517d59917 100644 --- a/src/V3Scoreboard.cpp +++ b/src/V3Scoreboard.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Scoreboard.h b/src/V3Scoreboard.h index 27573b8d2..2cc727a8b 100644 --- a/src/V3Scoreboard.h +++ b/src/V3Scoreboard.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h index 70a981696..203f446fb 100644 --- a/src/V3SenExprBuilder.h +++ b/src/V3SenExprBuilder.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -91,7 +91,7 @@ class SenExprBuilder final { } AstVarScope* getPrev(AstNodeExpr* exprp) { FileLine* const flp = exprp->fileline(); - const auto rdCurr = [=]() { return getCurr(exprp); }; + const auto rdCurr = [this, exprp]() { return getCurr(exprp); }; AstNode* scopeExprp = exprp; if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) scopeExprp = refp->varScopep(); @@ -155,8 +155,10 @@ class SenExprBuilder final { FileLine* const flp = senItemp->fileline(); AstNodeExpr* const senp = senItemp->sensp(); - const auto currp = [=]() { return getCurr(senp); }; - const auto prevp = [=]() { return new AstVarRef{flp, getPrev(senp), VAccess::READ}; }; + const auto currp = [this, senp]() { return getCurr(senp); }; + const auto prevp = [this, flp, senp]() { + return new AstVarRef{flp, getPrev(senp), VAccess::READ}; + }; const auto lsb = [=](AstNodeExpr* opp) { return new AstSel{flp, opp, 0, 1}; }; // All event signals should be 1-bit at this point @@ -223,7 +225,9 @@ public: for (AstSenItem* senItemp = senTreep->sensesp(); senItemp; senItemp = VN_AS(senItemp->nextp(), SenItem)) { const auto& pair = createTerm(senItemp); - if (AstNodeExpr* const termp = pair.first) { + if (AstNodeExpr* termp = pair.first) { + AstNodeExpr* const condp = senItemp->condp(); + if (condp) termp = new AstAnd{flp, condp->cloneTreePure(false), termp}; resultp = resultp ? new AstOr{flp, resultp, termp} : termp; firedAtInitialization |= pair.second; } diff --git a/src/V3SenTree.h b/src/V3SenTree.h index 81b5e6ef5..f78370e00 100644 --- a/src/V3SenTree.h +++ b/src/V3SenTree.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,7 +32,6 @@ // And provide functions to find/add a new one class SenTreeFinder final { -private: // STATE AstTopScope* const m_topScopep; // Top scope to add global SenTrees to std::unordered_set> m_trees; // Set of global SenTrees diff --git a/src/V3Simulate.h b/src/V3Simulate.h index 5343af244..b9c4c80ab 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -559,7 +559,8 @@ private: AstNode* const valuep = nodep->itemp()->valuep(); if (valuep) { iterateAndNextConstNull(valuep); - if (optimizable()) newValue(nodep, fetchValue(valuep)); + if (!optimizable()) return; + newValue(nodep, fetchValue(valuep)); } else { clearOptimizable(nodep, "No value found for enum item"); // LCOV_EXCL_LINE } @@ -611,13 +612,13 @@ private: iterateChildrenConst(nodep); } else { iterateConst(nodep->lhsp()); - if (optimizable()) { - if (fetchConst(nodep->lhsp())->num().isNeqZero()) { - iterateConst(nodep->rhsp()); - newValue(nodep, fetchValue(nodep->rhsp())); - } else { - newValue(nodep, fetchValue(nodep->lhsp())); // a zero - } + if (!optimizable()) return; + if (fetchConst(nodep->lhsp())->num().isNeqZero()) { + iterateConst(nodep->rhsp()); + if (!optimizable()) return; + newValue(nodep, fetchValue(nodep->rhsp())); + } else { + newValue(nodep, fetchValue(nodep->lhsp())); // a zero } } } @@ -629,13 +630,13 @@ private: iterateChildrenConst(nodep); } else { iterateConst(nodep->lhsp()); - if (optimizable()) { - if (fetchConst(nodep->lhsp())->num().isNeqZero()) { - newValue(nodep, fetchValue(nodep->lhsp())); // a one - } else { - iterateConst(nodep->rhsp()); - newValue(nodep, fetchValue(nodep->rhsp())); - } + if (!optimizable()) return; + if (fetchConst(nodep->lhsp())->num().isNeqZero()) { + newValue(nodep, fetchValue(nodep->lhsp())); // a one + } else { + iterateConst(nodep->rhsp()); + if (!optimizable()) return; + newValue(nodep, fetchValue(nodep->rhsp())); } } } @@ -647,15 +648,14 @@ private: iterateChildrenConst(nodep); } else { iterateConst(nodep->lhsp()); - if (optimizable()) { - if (fetchConst(nodep->lhsp())->num().isEqZero()) { - const AstConst cnst{nodep->fileline(), AstConst::WidthedValue{}, 1, - 1}; // a one - newValue(nodep, &cnst); // a one - } else { - iterateConst(nodep->rhsp()); - newValue(nodep, fetchValue(nodep->rhsp())); - } + if (!optimizable()) return; + if (fetchConst(nodep->lhsp())->num().isEqZero()) { + const AstConst cnst{nodep->fileline(), AstConst::WidthedValue{}, 1, 1}; // a one + newValue(nodep, &cnst); // a one + } else { + iterateConst(nodep->rhsp()); + if (!optimizable()) return; + newValue(nodep, fetchValue(nodep->rhsp())); } } } @@ -669,14 +669,15 @@ private: iterateChildrenConst(nodep); } else { iterateConst(nodep->condp()); - if (optimizable()) { - if (fetchConst(nodep->condp())->num().isNeqZero()) { - iterateConst(nodep->thenp()); - newValue(nodep, fetchValue(nodep->thenp())); - } else { - iterateConst(nodep->elsep()); - newValue(nodep, fetchValue(nodep->elsep())); - } + if (!optimizable()) return; + if (fetchConst(nodep->condp())->num().isNeqZero()) { + iterateConst(nodep->thenp()); + if (!optimizable()) return; + newValue(nodep, fetchValue(nodep->thenp())); + } else { + iterateConst(nodep->elsep()); + if (!optimizable()) return; + newValue(nodep, fetchValue(nodep->elsep())); } } } @@ -767,7 +768,7 @@ private: outVarrefpRef = varrefp; lsbRef = fetchConst(selp->lsbp())->num(); return; // And presumably still optimizable() - } else if (AstSel* const subselp = VN_CAST(selp->lhsp(), Sel)) { + } else if (AstSel* const subselp = VN_CAST(selp->fromp(), Sel)) { V3Number sublsb{nodep}; handleAssignSelRecurse(nodep, subselp, outVarrefpRef, sublsb /*ref*/, depth + 1); if (optimizable()) { @@ -815,10 +816,9 @@ private: iterateChildrenConst(nodep); } else if (optimizable()) { iterateAndNextConstNull(nodep->rhsp()); - if (optimizable()) { - AstNode* const vscp = varOrScope(VN_CAST(nodep->lhsp(), VarRef)); - assignOutValue(nodep, vscp, fetchValue(nodep->rhsp())); - } + if (!optimizable()) return; + AstNode* const vscp = varOrScope(VN_CAST(nodep->lhsp(), VarRef)); + assignOutValue(nodep, vscp, fetchValue(nodep->rhsp())); } } void visit(AstArraySel* nodep) override { diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp index cc479b95c..69ecca56f 100644 --- a/src/V3Slice.cpp +++ b/src/V3Slice.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -148,7 +148,7 @@ class SliceVisitor final : public VNVisitor { if (AstSliceSel* const slicep = VN_CAST(itemp, SliceSel)) { offset += slicep->declRange().lo(); newp = new AstArraySel{nodep->fileline(), - slicep->lhsp()->cloneTreePure(false), offset}; + slicep->fromp()->cloneTreePure(false), offset}; } else { newp = new AstArraySel{nodep->fileline(), itemp->cloneTreePure(false), offset}; diff --git a/src/V3Slice.h b/src/V3Slice.h index 5eefd784c..c96c482ab 100644 --- a/src/V3Slice.h +++ b/src/V3Slice.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Split.cpp b/src/V3Split.cpp index 08d39bc18..75735761b 100644 --- a/src/V3Split.cpp +++ b/src/V3Split.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -241,7 +241,6 @@ public: // Split class functions class SplitReorderBaseVisitor VL_NOT_FINAL : public VNVisitor { -private: // NODE STATE // AstVarScope::user1p -> Var SplitNodeVertex* for usage var, 0=not set yet // AstVarScope::user2p -> Var SplitNodeVertex* for delayed assignment var, 0=not set yet @@ -845,7 +844,6 @@ public: }; class SplitVisitor final : public SplitReorderBaseVisitor { -private: // Keys are original always blocks pending delete, // values are newly split always blocks pending insertion // at the same position as the originals: diff --git a/src/V3Split.h b/src/V3Split.h index e3eff188f..d14013df3 100644 --- a/src/V3Split.h +++ b/src/V3Split.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3SplitAs.cpp b/src/V3SplitAs.cpp index 26898c676..b048692e5 100644 --- a/src/V3SplitAs.cpp +++ b/src/V3SplitAs.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,8 +32,7 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### // Find all split variables in a block -class SplitAsFindVisitor final : public VNVisitor { -private: +class SplitAsFindVisitor final : public VNVisitorConst { // STATE - across all visitors AstVarScope* m_splitVscp = nullptr; // Variable we want to split @@ -49,11 +48,11 @@ private: // This will break if the m_splitVscp is a "ref" argument to the function, // but little we can do. } - void visit(AstNode* nodep) override { iterateChildren(nodep); } + void visit(AstNode* nodep) override { iterateChildrenConst(nodep); } public: // CONSTRUCTORS - explicit SplitAsFindVisitor(AstAlways* nodep) { iterate(nodep); } + explicit SplitAsFindVisitor(AstAlways* nodep) { iterateConst(nodep); } ~SplitAsFindVisitor() override = default; // METHODS AstVarScope* splitVscp() const { return m_splitVscp; } @@ -63,7 +62,6 @@ public: // Remove nodes not containing proper references class SplitAsCleanVisitor final : public VNVisitor { -private: // STATE - across all visitors const AstVarScope* const m_splitVscp; // Variable we want to split const bool m_modeMatch; // Remove matching Vscp, else non-matching @@ -125,7 +123,6 @@ public: // SplitAs class functions class SplitAsVisitor final : public VNVisitor { -private: // NODE STATE // AstAlways::user() -> bool. True if already processed const VNUser1InUse m_inuser1; diff --git a/src/V3SplitAs.h b/src/V3SplitAs.h index 528695564..b45b263ac 100644 --- a/src/V3SplitAs.h +++ b/src/V3SplitAs.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp index adfc8e8c6..9bb0b1ea5 100644 --- a/src/V3SplitVar.cpp +++ b/src/V3SplitVar.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3SplitVar.h b/src/V3SplitVar.h index d3f47afb6..e5ac9e12b 100644 --- a/src/V3SplitVar.h +++ b/src/V3SplitVar.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Stats.cpp b/src/V3Stats.cpp index 03d823d8b..f133f6776 100644 --- a/src/V3Stats.cpp +++ b/src/V3Stats.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -104,8 +104,8 @@ public: iterateConst(nodep); // Shorthand - const auto addStat = [&](const std::string& name, double count) { // - V3Stats::addStat(stage, name, count); + const auto addStat = [&](const std::string& name, double count, unsigned precision = 0) { + V3Stats::addStat(stage, name, count, precision); }; // Variable widths @@ -124,13 +124,25 @@ public: } } - // Node types + // Node types (also total memory usage) const auto typeName = [](int type) { return std::string{VNType{type}.ascii()}; }; + const auto typeSize = [](int type) { return VNType{type}.typeInfo()->m_sizeof; }; + size_t totalNodeMemoryUsage = 0; for (int t = 0; t < VNType::_ENUM_END; ++t) { if (const uint64_t count = m_counters.m_statTypeCount[t]) { + totalNodeMemoryUsage += count * typeSize(t); addStat("Node count, " + typeName(t), count); } } + addStat("Node memory TOTAL (MiB)", totalNodeMemoryUsage >> 20); + + // Node Memory usage + for (int t = 0; t < VNType::_ENUM_END; ++t) { + if (const uint64_t count = m_counters.m_statTypeCount[t]) { + const double share = 100.0 * count * typeSize(t) / totalNodeMemoryUsage; + addStat("Node memory share (%), " + typeName(t), share, 2); + } + } // Expression combinations for (int t1 = 0; t1 < VNType::_ENUM_END; ++t1) { diff --git a/src/V3Stats.h b/src/V3Stats.h index 8fd207d28..1347dcfd3 100644 --- a/src/V3Stats.h +++ b/src/V3Stats.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -68,7 +68,8 @@ public: class V3Statistic final { // A statistical entry we want published into the database const string m_name; ///< Name of this statistic - double m_count; ///< Count of occurrences/ value + double m_value; ///< Value of statistic (count, ratio, etc.) + unsigned m_precision; ///< Precision to print with (number of fractional digits) const string m_stage; ///< Runtime stage const bool m_sumit; ///< Do summation of similar stats const bool m_perf; ///< Performance section @@ -77,20 +78,22 @@ public: // METHODS string stage() const VL_MT_SAFE { return m_stage; } string name() const VL_MT_SAFE { return m_name; } - double count() const VL_MT_SAFE { return m_count; } + double value() const VL_MT_SAFE { return m_value; } + unsigned precision() const VL_MT_SAFE { return m_precision; } bool sumit() const VL_MT_SAFE { return m_sumit; } bool perf() const VL_MT_SAFE { return m_perf; } bool printit() const VL_MT_SAFE { return m_printit; } virtual void dump(std::ofstream& os) const VL_MT_SAFE; void combineWith(V3Statistic* otherp) { - m_count += otherp->count(); + m_value += otherp->value(); otherp->m_printit = false; } // CONSTRUCTORS - V3Statistic(const string& stage, const string& name, double count, bool sumit = false, - bool perf = false) + V3Statistic(const string& stage, const string& name, double value, unsigned precision, + bool sumit = false, bool perf = false) : m_name{name} - , m_count{count} + , m_value{value} + , m_precision{precision} , m_stage{stage} , m_sumit{sumit} , m_perf{perf} {} @@ -102,17 +105,18 @@ public: class V3Stats final { public: static void addStat(const V3Statistic&); - static void addStat(const string& stage, const string& name, double count) { - addStat(V3Statistic{stage, name, count}); + static void addStat(const string& stage, const string& name, double value, + unsigned precision = 0) { + addStat(V3Statistic{stage, name, value, precision}); } - static void addStat(const string& name, double count) { - addStat(V3Statistic{"*", name, count}); + static void addStat(const string& name, double value, unsigned precision = 0) { + addStat(V3Statistic{"*", name, value, precision}); } static void addStatSum(const string& name, double count) { - addStat(V3Statistic{"*", name, count, true}); + addStat(V3Statistic{"*", name, count, 0, true}); } - static void addStatPerf(const string& name, double count) { - addStat(V3Statistic{"*", name, count, true, true}); + static void addStatPerf(const string& name, double value) { + addStat(V3Statistic{"*", name, value, 6, true, true}); } /// Called each stage static void statsStage(const string& name); diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp index a41f116d6..c4bc2b7bc 100644 --- a/src/V3StatsReport.cpp +++ b/src/V3StatsReport.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -181,11 +181,8 @@ StatsReport::StatColl StatsReport::s_allStats; // V3Statstic class void V3Statistic::dump(std::ofstream& os) const { - if (perf()) { - os << " " << std::right << std::fixed << std::setprecision(6) << std::setw(9) << count(); - } else { - os << " " << std::right << std::fixed << std::setprecision(0) << std::setw(9) << count(); - } + os << " " << std::right << std::fixed << std::setprecision(precision()) << std::setw(9) + << value(); } //###################################################################### diff --git a/src/V3StdFuture.h b/src/V3StdFuture.h index 09f21dbd4..2e4d2f31b 100644 --- a/src/V3StdFuture.h +++ b/src/V3StdFuture.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3String.cpp b/src/V3String.cpp index e42bee71d..45e7da277 100644 --- a/src/V3String.cpp +++ b/src/V3String.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3String.h b/src/V3String.h index 149ce2d43..0fc795399 100644 --- a/src/V3String.h +++ b/src/V3String.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -174,7 +174,7 @@ public: uint64_t digestUInt64(); // Return 64-bits of digest static void selfTest(); // Test this class - // Inerting hash data + // Inserting hash data void insert(const void* datap, size_t length); // Process data into the digest void insert(const string& data) { insert(data.data(), data.length()); diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp index 7c2465dad..643a051f1 100644 --- a/src/V3Subst.cpp +++ b/src/V3Subst.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -165,8 +165,7 @@ public: // See if any variables have changed value since we determined subst value, // as a visitor of each AstNode -class SubstUseVisitor final : public VNVisitor { -private: +class SubstUseVisitor final : public VNVisitorConst { // NODE STATE // See SubstVisitor // @@ -197,7 +196,7 @@ private: void visit(AstConst*) override {} // Accelerate void visit(AstNode* nodep) override { if (!nodep->isPure()) m_ok = false; - iterateChildren(nodep); + iterateChildrenConst(nodep); } public: @@ -205,7 +204,7 @@ public: SubstUseVisitor(AstNode* nodep, int origStep) : m_origStep{origStep} { UINFO(9, " SubstUseVisitor " << origStep << " " << nodep << endl); - iterate(nodep); + iterateConst(nodep); } ~SubstUseVisitor() override = default; // METHODS @@ -216,18 +215,17 @@ public: // Subst state, as a visitor of each AstNode class SubstVisitor final : public VNVisitor { -private: // NODE STATE // Passed to SubstUseVisitor - // AstVar::user1p -> SubstVar* for usage var, 0=not set yet + // AstVar::user1p -> SubstVar* for usage var, 0=not set yet. Only under CFunc. // AstVar::user2 -> int step number for last assignment, 0=not set yet - const VNUser1InUse m_inuser1; const VNUser2InUse m_inuser2; // STATE - std::vector m_entryps; // Nodes to delete when we are finished + std::deque m_entries; // Nodes to delete when we are finished int m_ops = 0; // Number of operators on assign rhs int m_assignStep = 0; // Assignment number to determine var lifetime + const AstCFunc* m_funcp = nullptr; // Current function we are under VDouble0 m_statSubsts; // Statistic tracking enum { @@ -237,21 +235,18 @@ private: // METHODS SubstVarEntry* getEntryp(AstVarRef* nodep) { - if (!nodep->varp()->user1p()) { - SubstVarEntry* const entryp = new SubstVarEntry{nodep->varp()}; - m_entryps.push_back(entryp); - nodep->varp()->user1p(entryp); - return entryp; - } else { - SubstVarEntry* const entryp - = reinterpret_cast(nodep->varp()->user1p()); - return entryp; + AstVar* const varp = nodep->varp(); + if (!varp->user1p()) { + m_entries.emplace_back(varp); + varp->user1p(&m_entries.back()); } + return varp->user1u().to(); } bool isSubstVar(AstVar* nodep) { return nodep->isStatementTemp() && !nodep->noSubst(); } // VISITORS void visit(AstNodeAssign* nodep) override { + if (!m_funcp) return; VL_RESTORER(m_ops); m_ops = 0; m_assignStep++; @@ -270,9 +265,9 @@ private: } } } else if (const AstWordSel* const wordp = VN_CAST(nodep->lhsp(), WordSel)) { - if (AstVarRef* const varrefp = VN_CAST(wordp->lhsp(), VarRef)) { - if (VN_IS(wordp->rhsp(), Const) && isSubstVar(varrefp->varp())) { - const int word = VN_AS(wordp->rhsp(), Const)->toUInt(); + if (AstVarRef* const varrefp = VN_CAST(wordp->fromp(), VarRef)) { + if (VN_IS(wordp->bitp(), Const) && isSubstVar(varrefp->varp())) { + const int word = VN_AS(wordp->bitp(), Const)->toUInt(); SubstVarEntry* const entryp = getEntryp(varrefp); hit = true; if (m_ops > SUBST_MAX_OPS_SUBST) { @@ -295,13 +290,14 @@ private: } if (debug() > 5) newp->dumpTree("- w_new: "); nodep->replaceWith(newp); - VL_DO_DANGLING(pushDeletep(nodep), nodep); + VL_DO_DANGLING(nodep->deleteTree(), nodep); ++m_statSubsts; } void visit(AstWordSel* nodep) override { - iterate(nodep->rhsp()); - AstVarRef* const varrefp = VN_CAST(nodep->lhsp(), VarRef); - const AstConst* const constp = VN_CAST(nodep->rhsp(), Const); + if (!m_funcp) return; + iterate(nodep->bitp()); + AstVarRef* const varrefp = VN_CAST(nodep->fromp(), VarRef); + const AstConst* const constp = VN_CAST(nodep->bitp(), Const); if (varrefp && isSubstVar(varrefp->varp()) && varrefp->access().isReadOnly() && constp) { // Nicely formed lvalues handled in NodeAssign // Other lvalues handled as unknown mess in AstVarRef @@ -320,10 +316,11 @@ private: entryp->consumeWord(word); } } else { - iterate(nodep->lhsp()); + iterate(nodep->fromp()); } } void visit(AstVarRef* nodep) override { + if (!m_funcp) return; // Any variable if (nodep->access().isWriteOrRW()) { m_assignStep++; @@ -353,13 +350,19 @@ private: } void visit(AstVar*) override {} void visit(AstConst*) override {} - void visit(AstModule* nodep) override { - ++m_ops; - if (!nodep->isSubstOptimizable()) m_ops = SUBST_MAX_OPS_NA; + + void visit(AstCFunc* nodep) override { + UASSERT_OBJ(!m_funcp, nodep, "Should not nest"); + UASSERT_OBJ(m_entries.empty(), nodep, "References outside functions"); + VL_RESTORER(m_funcp); + m_funcp = nodep; + + const VNUser1InUse m_inuser1; iterateChildren(nodep); - // Reduce peak memory usage by reclaiming the edited AstNodes - doDeletes(); + for (SubstVarEntry& ip : m_entries) ip.deleteUnusedAssign(); + m_entries.clear(); } + void visit(AstNode* nodep) override { ++m_ops; if (!nodep->isSubstOptimizable()) m_ops = SUBST_MAX_OPS_NA; @@ -371,10 +374,7 @@ public: explicit SubstVisitor(AstNode* nodep) { iterate(nodep); } ~SubstVisitor() override { V3Stats::addStat("Optimizations, Substituted temps", m_statSubsts); - for (SubstVarEntry* ip : m_entryps) { - ip->deleteUnusedAssign(); - delete ip; - } + UASSERT(m_entries.empty(), "References outside functions"); } }; diff --git a/src/V3Subst.h b/src/V3Subst.h index 5320e4c3c..2d29df8e4 100644 --- a/src/V3Subst.h +++ b/src/V3Subst.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3SymTable.h b/src/V3SymTable.h index 3fcdabb90..836ee8e55 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index 916e95d0d..c94784db2 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -11,7 +11,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3TSP.h b/src/V3TSP.h index 91a31d7ed..1288945af 100644 --- a/src/V3TSP.h +++ b/src/V3TSP.h @@ -7,7 +7,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Table.cpp b/src/V3Table.cpp index cfdc10717..06ffe06b8 100644 --- a/src/V3Table.cpp +++ b/src/V3Table.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -145,7 +145,6 @@ public: // Table class functions class TableVisitor final : public VNVisitor { -private: // NODE STATE // Cleared on each always/assignw diff --git a/src/V3Table.h b/src/V3Table.h index 40c43657b..9f7db3fec 100644 --- a/src/V3Table.h +++ b/src/V3Table.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Task.cpp b/src/V3Task.cpp index f0b3d5fba..21c494a6d 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,7 +30,6 @@ #include "V3Const.h" #include "V3EmitCBase.h" #include "V3Graph.h" -#include "V3LinkLValue.h" #include @@ -92,7 +91,6 @@ public: //###################################################################### class TaskStateVisitor final : public VNVisitor { -private: // NODE STATE // Output: // AstNodeFTask::user3p // AstScope* this FTask is under @@ -273,8 +271,6 @@ public: // CONSTRUCTORS explicit TaskStateVisitor(AstNetlist* nodep) { m_curVxp = new TaskCodeVertex{&m_callGraph}; - AstNode::user3ClearTree(); - AstNode::user4ClearTree(); // iterate(nodep); // @@ -333,7 +329,6 @@ struct TaskDpiUtils { // Task state, as a visitor of each AstNode class TaskVisitor final : public VNVisitor { -private: // NODE STATE // Each module: // AstNodeFTask::user1 // True if its been expanded @@ -507,7 +502,6 @@ private: } } else if (portp->isInoutish()) { // if (debug() >= 9) pinp->dumpTree("-pinrsize- "); - V3LinkLValue::linkLValueSet(pinp); AstVarScope* const newvscp = createVarScope(portp, namePrefix + "__" + portp->shortName()); @@ -528,12 +522,6 @@ private: beginp->addNext(postassp); // if (debug() >= 9) beginp->dumpTreeAndNext(cout, "-pinrsize-out- "); } else if (portp->isWritable()) { - // Make output variables - // Correct lvalue; we didn't know when we linked - // This is slightly scary; are we sure no decisions were made - // before here based on this not being a lvalue? - // Doesn't seem so; V3Unknown uses it earlier, but works ok. - V3LinkLValue::linkLValueSet(pinp); // Even if it's referencing a varref, we still make a temporary // Else task(x,x,x) might produce incorrect results AstVarScope* const newvscp @@ -1863,9 +1851,9 @@ AstNodeFTask* V3Task::taskConnectWrapNew(AstNodeFTask* taskp, const string& newn newTaskp->addStmtsp(newAssignp); } oldNewVars.emplace(portp, newPortp); - AstArg* const newArgp - = new AstArg{portp->fileline(), portp->name(), - new AstVarRef{portp->fileline(), newPortp, VAccess::READ}}; + const VAccess pinAccess = portp->isWritable() ? VAccess::WRITE : VAccess::READ; + AstArg* const newArgp = new AstArg{portp->fileline(), portp->name(), + new AstVarRef{portp->fileline(), newPortp, pinAccess}}; newCallp->addPinsp(newArgp); } // Create wrapper call to original, passing arguments, adding setting of return value diff --git a/src/V3Task.h b/src/V3Task.h index feea7e17e..f3f7cfacd 100644 --- a/src/V3Task.h +++ b/src/V3Task.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ThreadPool.cpp b/src/V3ThreadPool.cpp index c2173eae9..9753b59e5 100644 --- a/src/V3ThreadPool.cpp +++ b/src/V3ThreadPool.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3ThreadPool.h b/src/V3ThreadPool.h index ccfa2f88c..2b28619b7 100644 --- a/src/V3ThreadPool.h +++ b/src/V3ThreadPool.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -109,22 +110,59 @@ class V3ThreadPool final { // Indicates whether multithreading has been suspended. // Used for error detection in resumeMultithreading only. You probably should use // m_exclusiveAccess for information whether something should be run in current thread. - bool m_multithreadingSuspended VL_GUARDED_BY(m_mutex) = false; + std::atomic_bool m_multithreadingSuspended{false}; // CONSTRUCTORS V3ThreadPool() = default; ~V3ThreadPool() { - if (!m_mutex.try_lock()) { - if (m_jobsInProgress != 0) { + if (m_multithreadingSuspended) { + // Ideally we shouldn't deal with this and just call the std::abort. However, + // std::exit(0) (which invokes this destructor) is called in multiple places with + // multithreading being suspended. Aborting would change the exit code, what would not + // be acceptable. + resumeMultithreading(); + } + // Unexpected states. Aborting to subtly signal to the outside world that something is + // wrong. This won't make things worse to an user - the program is already terminating at + // this point anyway, most likely as a result of an error. Using if/abort instead of assert + // because assert can be disabled. + if (VL_UNCOVERABLE(m_exclusiveAccess)) { + std::cerr << "%Error: Internal Error: attempted to destroy Thread Pool with active " + "exclusive access mode" + << std::endl; + std::abort(); + } + if (VL_UNCOVERABLE(m_stopRequested)) { + std::cerr << "%Error: Internal Error: attempted to destroy Thread Pool with active " + "stop request" + << std::endl; + std::abort(); + } + + if (VL_UNCOVERABLE(!m_mutex.try_lock())) { + if (VL_UNCOVERABLE(m_jobsInProgress != 0)) { // ThreadPool shouldn't be destroyed when jobs are running and mutex is locked, - // something is wrong. Most likely Verilator is exitting as a result of failed - // assert in critical section. Do nothing, let it exit. - return; + // something is wrong. Most likely Verilator is exiting as a result of failed + // assert in critical section. Just returning is dangerous, as threads and this + // class' members might keep the program hanging endlessly. + std::cerr << "%Error: Internal Error: attempted to destroy Thread Pool with " + "running jobs" + << std::endl; + std::abort(); } + // Probably an error happened in a call to some V3ThreadPool's method. We can't just + // unlock m_mutex and be sure that resize(0) handle this well. + std::cerr << "%Error: Internal Error: attempted to destroy locked Thread Pool" + << std::endl; + std::abort(); } else { V3LockGuard lock{m_mutex, std::adopt_lock_t{}}; m_queue = {}; // make sure queue is empty } + + // This locks mutexes and wakes up threads, so it would be nice to move this to a separate + // method that would be called just before controlled exit. Such method would need to be + // called in quite a few places that call std::exit(0), so leaving it here for now. resize(0); } @@ -169,7 +207,7 @@ public: bool waitIfStopRequested() VL_MT_SAFE VL_EXCLUDES(m_stoppedJobsMutex); // Waits for future. - // This function can be interupted by exclusive access request. + // This function can be interrupted by exclusive access request. // When other thread requested exclusive access to processing, // current thread is stopped and waits until it is resumed. // Returns future result @@ -177,7 +215,7 @@ public: static T waitForFuture(std::future& future) VL_MT_SAFE_EXCLUDES(m_mutex); // Waits for list of futures - // This function can be interupted by exclusive access request. + // This function can be interrupted by exclusive access request. // When other thread requested exclusive access to processing, // current thread is stopped and waits until it is resumed. // This function uses function overload instead of template @@ -232,6 +270,7 @@ private: // True when any thread requested exclusive access bool stopRequested() const VL_MT_SAFE { + if (m_exclusiveAccess) return false; // don't wait if shutdown already requested if (m_shutdown) return false; return m_stopRequested; diff --git a/src/V3ThreadSafety.h b/src/V3ThreadSafety.h index 61b75aa95..0b62ce9a3 100644 --- a/src/V3ThreadSafety.h +++ b/src/V3ThreadSafety.h @@ -1,12 +1,12 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* -// DESCRIPTION: Verilator: Definitions for thread safety checing +// DESCRIPTION: Verilator: Definitions for thread safety checking // // Code available from: https://verilator.org // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp index 6484a7247..3ed545153 100644 --- a/src/V3Timing.cpp +++ b/src/V3Timing.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -108,7 +108,6 @@ static bool hasFlags(AstNode* const nodep, uint8_t flags) { return !(~nodep->use // Detect nodes affected by timing and/or requiring a process class TimingSuspendableVisitor final : public VNVisitor { -private: // TYPES // Vertex of a dependency graph of suspendable nodes, e.g. if a node (process or task) is // suspendable, all its dependents should also be suspendable @@ -279,6 +278,28 @@ private: visit(static_cast(nodep)); addFlags(m_procp, T_FORCES_PROC | T_NEEDS_PROC); } + void visit(AstWait* nodep) override { + AstNodeExpr* const condp = V3Const::constifyEdit(nodep->condp()); + if (AstConst* const constp = VN_CAST(condp, Const)) { + if (!nodep->fileline()->warnIsOff(V3ErrorCode::WAITCONST)) { + condp->v3warn(WAITCONST, "Wait statement condition is constant"); + } + if (!constp->isZero()) { + // Remove AstWait before we track process as T_SUSPENDER + if (AstNode* const stmtsp = nodep->stmtsp()) { + stmtsp->unlinkFrBackWithNext(); + nodep->replaceWith(stmtsp); + } else { + nodep->unlinkFrBack(); + } + VL_DO_DANGLING(pushDeletep(nodep), nodep); + return; + } + } + v3Global.setUsesTiming(); + if (m_procp) addFlags(m_procp, T_SUSPENDEE | T_SUSPENDER | T_NEEDS_PROC); + iterateChildren(nodep); + } void visit(AstCFunc* nodep) override { VL_RESTORER(m_procp); m_procp = nodep; @@ -428,7 +449,6 @@ public: // Transform nodes affected by timing class TimingControlVisitor final : public VNVisitor { -private: // NODE STATE // Ast{Always,NodeCCall,Fork,NodeAssign}::user1() -> bool. Set true if the node has // been processed. @@ -876,10 +896,7 @@ private: FileLine* const flp = nodep->fileline(); AstNodeExpr* valuep = V3Const::constifyEdit(nodep->lhsp()->unlinkFrBack()); auto* const constp = VN_CAST(valuep, Const); - if (constp && constp->isZero()) { - nodep->v3warn(ZERODLY, "Unsupported: #0 delays do not schedule process resumption in " - "the Inactive region"); - } else { + if (!constp || !constp->isZero()) { // Scale the delay if (valuep->dtypep()->isDouble()) { valuep = new AstRToIRoundS{ @@ -1029,8 +1046,12 @@ private: // Special case for NBA if (inAssignDly) { // Put it in a fork so it doesn't block - auto* const forkp = new AstFork{flp, "", nullptr}; - forkp->joinType(VJoinType::JOIN_NONE); + // Could already be the only thing directly under a fork, reuse that if possible + AstFork* forkp = !nodep->nextp() ? VN_CAST(nodep->firstAbovep(), Fork) : nullptr; + if (!forkp) { + forkp = new AstFork{flp, "", nullptr}; + forkp->joinType(VJoinType::JOIN_NONE); + } if (!m_underProcedure) { // If it's in a function, it won't be handled by V3Delayed // Put it behind an additional named event that gets triggered in the NBA region @@ -1123,9 +1144,6 @@ private: AstNodeExpr* const condp = V3Const::constifyEdit(nodep->condp()->unlinkFrBack()); auto* const constp = VN_CAST(condp, Const); if (constp) { - if (!nodep->fileline()->warnIsOff(V3ErrorCode::WAITCONST)) { - condp->v3warn(WAITCONST, "Wait statement condition is constant"); - } if (constp->isZero()) { // We have to await forever instead of simply returning in case we're deep in a // callstack @@ -1136,11 +1154,9 @@ private: nodep->replaceWith(awaitp->makeStmt()); if (stmtsp) VL_DO_DANGLING(stmtsp->deleteTree(), stmtsp); VL_DO_DANGLING(condp->deleteTree(), condp); - } else if (stmtsp) { - // Just put the statements there - nodep->replaceWith(stmtsp); } else { - nodep->unlinkFrBack(); + nodep->v3fatalSrc("constant wait should have been removed in " + "TimingSuspendableVisitor::visit(AstWait)"); } } else if (needDynamicTrigger(condp)) { // No point in making a sentree, just use the expression as sensitivity diff --git a/src/V3Timing.h b/src/V3Timing.h index 271583793..7d53d456b 100644 --- a/src/V3Timing.h +++ b/src/V3Timing.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp index 070092cd9..5c64abda0 100644 --- a/src/V3Trace.cpp +++ b/src/V3Trace.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -156,7 +156,6 @@ public: // Trace state, as a visitor of each AstNode class TraceVisitor final : public VNVisitor { -private: // NODE STATE // V3Hasher in V3DupFinder // Ast*::user4() // V3Hasher calculation @@ -202,40 +201,24 @@ private: UINFO(9, "Finding duplicates\n"); // Note uses user4 V3DupFinder dupFinder; // Duplicate code detection - // Hash all of the values the traceIncs need - for (const V3GraphVertex* itp = m_graph.verticesBeginp(); itp; - itp = itp->verticesNextp()) { - if (const TraceTraceVertex* const vvertexp = itp->cast()) { - const AstTraceDecl* const nodep = vvertexp->nodep(); - if (nodep->valuep()) { - UASSERT_OBJ(nodep->valuep()->backp() == nodep, nodep, - "Trace duplicate back needs consistency," - " so we can map duplicates back to TRACEINCs"); - // Just keep one node in the map and point all duplicates to this node - if (dupFinder.findDuplicate(nodep->valuep()) == dupFinder.end()) { - dupFinder.insert(nodep->valuep()); - } - } - } - } - // Find if there are any duplicates + // Hash all of the traced values and find if there are any duplicates for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp = itp->verticesNextp()) { if (TraceTraceVertex* const vvertexp = itp->cast()) { const AstTraceDecl* const nodep = vvertexp->nodep(); - if (nodep->valuep() && !vvertexp->duplicatep()) { - const auto dupit = dupFinder.findDuplicate(nodep->valuep()); - if (dupit != dupFinder.end()) { - const AstTraceDecl* const dupDeclp - = VN_AS(dupit->second->backp(), TraceDecl); - UASSERT_OBJ(dupDeclp, nodep, "Trace duplicate of wrong type"); - TraceTraceVertex* const dupvertexp - = dupDeclp->user1u().toGraphVertex()->cast(); - UINFO(8, " Orig " << nodep << endl); - UINFO(8, " dup " << dupDeclp << endl); - // Mark the hashed node as the original and our - // iterating node as duplicated - vvertexp->duplicatep(dupvertexp); - } + UASSERT_OBJ(!vvertexp->duplicatep(), nodep, "Should not be a duplicate"); + const auto dupit = dupFinder.findDuplicate(nodep->valuep()); + if (dupit == dupFinder.end()) { + dupFinder.insert(nodep->valuep()); + } else { + const AstTraceDecl* const dupDeclp = VN_AS(dupit->second->backp(), TraceDecl); + UASSERT_OBJ(dupDeclp, nodep, "Trace duplicate of wrong type"); + TraceTraceVertex* const dupvertexp + = dupDeclp->user1u().toGraphVertex()->cast(); + UINFO(8, " Orig " << nodep << endl); + UINFO(8, " dup " << dupDeclp << endl); + // Mark the hashed node as the original and our + // iterating node as duplicated + vvertexp->duplicatep(dupvertexp); } } } @@ -595,8 +578,9 @@ private: UASSERT_OBJ(declp->code() == 0, declp, "Canonical node should not have code assigned yet"); declp->code(m_code); - m_code += declp->codeInc(); - m_statUniqCodes += declp->codeInc(); + const uint32_t codeInc = declp->codeInc(); + m_code += codeInc; + m_statUniqCodes += codeInc; ++m_statUniqSigs; // If this is a const signal, add the AstTraceInc diff --git a/src/V3Trace.h b/src/V3Trace.h index 214f71a33..bcb884d97 100644 --- a/src/V3Trace.h +++ b/src/V3Trace.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index 17aa40860..47986dbd6 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -90,7 +90,6 @@ public: // TraceDecl state, as a visitor of each AstNode class TraceDeclVisitor final : public VNVisitor { -private: // NODE STATE // STATE @@ -259,7 +258,7 @@ private: const size_t pos = path.rfind('.'); const std::string name = path.substr(pos == string::npos ? 0 : pos + 1); - // Compute the type of the scope beign fixed up + // Compute the type of the scope being fixed up AstNodeModule* const modp = scopep->aboveCellp()->modp(); const VTracePrefixType scopeType = VN_IS(modp, Iface) ? VTracePrefixType::SCOPE_INTERFACE @@ -427,7 +426,7 @@ private: // Assume only references under the same parent scope reference // the same interface. - // TODO: This is not actually correct. An inteface can propagate + // TODO: This is not actually correct. An interface can propagate // upwards and sideways when passed to a port via a downward // hierarchical reference, which we will miss here. if (!VString::startsWith(refName, parentPath)) continue; diff --git a/src/V3TraceDecl.h b/src/V3TraceDecl.h index 91ca6cad7..ff9dacc98 100644 --- a/src/V3TraceDecl.h +++ b/src/V3TraceDecl.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp index 4807365af..48f1e8d46 100644 --- a/src/V3Tristate.cpp +++ b/src/V3Tristate.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Tristate.h b/src/V3Tristate.h index 0fff67827..98a498bbb 100644 --- a/src/V3Tristate.h +++ b/src/V3Tristate.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Undriven.cpp b/src/V3Undriven.cpp index 09d6e5043..faae3ec1a 100644 --- a/src/V3Undriven.cpp +++ b/src/V3Undriven.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2004-2023 by Wilson Snyder. This program is free software; you +// Copyright 2004-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -265,7 +265,6 @@ public: // Undriven state, as a visitor of each AstNode class UndrivenVisitor final : public VNVisitorConst { -private: // NODE STATE // Netlist: // AstVar::user1p -> UndrivenVar* for usage var, 0=not set yet diff --git a/src/V3Undriven.h b/src/V3Undriven.h index 30c107598..1a9c2de65 100644 --- a/src/V3Undriven.h +++ b/src/V3Undriven.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3UniqueNames.h b/src/V3UniqueNames.h index 30d4cd2fa..ec8a0e4ee 100644 --- a/src/V3UniqueNames.h +++ b/src/V3UniqueNames.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2005-2023 by Wilson Snyder. This program is free software; you +// Copyright 2005-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index 625055393..cb34c7ed3 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -41,7 +41,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; //###################################################################### class UnknownVisitor final : public VNVisitor { -private: // NODE STATE // Cleared on Netlist // AstSel::user() -> bool. Set true if already processed diff --git a/src/V3Unknown.h b/src/V3Unknown.h index 912152836..49d2c9ebe 100644 --- a/src/V3Unknown.h +++ b/src/V3Unknown.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp index f2a7af31b..ae92a5230 100644 --- a/src/V3Unroll.cpp +++ b/src/V3Unroll.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -38,7 +38,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Unroll state, as a visitor of each AstNode class UnrollVisitor final : public VNVisitor { -private: // STATE AstVar* m_forVarp; // Iterator variable const AstVarScope* m_forVscp; // Iterator variable scope (nullptr for generate pass) diff --git a/src/V3Unroll.h b/src/V3Unroll.h index c13e99a58..88cb4e7fb 100644 --- a/src/V3Unroll.h +++ b/src/V3Unroll.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3VariableOrder.cpp b/src/V3VariableOrder.cpp index 2fbea7c75..7bddc69a6 100644 --- a/src/V3VariableOrder.cpp +++ b/src/V3VariableOrder.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -36,7 +36,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Establish mtask variable sort order in mtasks mode class VarTspSorter final : public V3TSP::TspStateBase { -private: // MEMBERS const MTaskIdSet& m_mtaskIds; // Mtask we're ordering static unsigned s_serialNext; // Unique ID to establish serial order diff --git a/src/V3VariableOrder.h b/src/V3VariableOrder.h index 33cc55cec..4e556ebf6 100644 --- a/src/V3VariableOrder.h +++ b/src/V3VariableOrder.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Waiver.cpp b/src/V3Waiver.cpp index deb9ec6f7..bd4ad0883 100644 --- a/src/V3Waiver.cpp +++ b/src/V3Waiver.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2020-2023 by Wilson Snyder. This program is free software; you +// Copyright 2020-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Waiver.h b/src/V3Waiver.h index 8ad1e62dc..8ccc1f8e9 100644 --- a/src/V3Waiver.h +++ b/src/V3Waiver.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3Width.cpp b/src/V3Width.cpp index a9922e57c..93ce607c1 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -70,6 +70,7 @@ #include "V3Const.h" #include "V3Error.h" #include "V3Global.h" +#include "V3LinkLValue.h" #include "V3MemberMap.h" #include "V3Number.h" #include "V3Randomize.h" @@ -201,7 +202,6 @@ public: //###################################################################### class WidthVisitor final : public VNVisitor { -private: // TYPES using TableMap = std::map, AstVar*>; using PatVecMap = std::map; @@ -730,12 +730,12 @@ private: // LHS, RHS is self-determined // width: value(LHS) * width(RHS) if (m_vup->prelim()) { - iterateCheckSizedSelf(nodep, "RHS", nodep->rhsp(), SELF, BOTH); - V3Const::constifyParamsNoWarnEdit(nodep->rhsp()); // rhsp may change + iterateCheckSizedSelf(nodep, "RHS", nodep->countp(), SELF, BOTH); + V3Const::constifyParamsNoWarnEdit(nodep->countp()); // rhsp may change uint32_t times = 1; - const AstConst* const constp = VN_CAST(nodep->rhsp(), Const); + const AstConst* const constp = VN_CAST(nodep->countp(), Const); if (constp) times = constp->toUInt(); AstNodeDType* const vdtypep = m_vup->dtypeNullSkipRefp(); @@ -746,18 +746,18 @@ private: << vdtypep->prettyDTypeNameQ() << " data type"); } - if (VN_IS(nodep->lhsp(), Concat)) { + if (VN_IS(nodep->srcp(), Concat)) { // Convert to concat directly, and visit(AstConst) will convert. // Don't iterate lhsp as SELF, the potential Concat below needs // the adtypep passed down to recognize the QueueDType - userIterateAndNext(nodep->lhsp(), WidthVP{vdtypep, BOTH}.p()); - nodep->replaceWith(nodep->lhsp()->unlinkFrBack()); + userIterateAndNext(nodep->srcp(), WidthVP{vdtypep, BOTH}.p()); + nodep->replaceWith(nodep->srcp()->unlinkFrBack()); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; } else { // int a[] = {lhs} -> same as '{lhs} auto* const newp = new AstPattern{ nodep->fileline(), - new AstPatMember{nodep->lhsp()->fileline(), nodep->lhsp()->unlinkFrBack(), + new AstPatMember{nodep->srcp()->fileline(), nodep->srcp()->unlinkFrBack(), nullptr, nullptr}}; nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); @@ -769,11 +769,11 @@ private: nodep->v3warn(E_UNSUPPORTED, "Unsupported: Replication to form " << vdtypep->prettyDTypeNameQ() << " data type"); } - iterateCheckSizedSelf(nodep, "LHS", nodep->lhsp(), SELF, BOTH); - if ((vdtypep && vdtypep->isString()) || nodep->lhsp()->isString()) { + iterateCheckSizedSelf(nodep, "LHS", nodep->srcp(), SELF, BOTH); + if ((vdtypep && vdtypep->isString()) || nodep->srcp()->isString()) { AstNode* const newp - = new AstReplicateN{nodep->fileline(), nodep->lhsp()->unlinkFrBack(), - nodep->rhsp()->unlinkFrBack()}; + = new AstReplicateN{nodep->fileline(), nodep->srcp()->unlinkFrBack(), + nodep->countp()->unlinkFrBack()}; nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; @@ -785,8 +785,8 @@ private: " (IEEE 1800-2017 11.4.12.1)"); times = 1; // Set to 1, so we can continue looking for errors } - nodep->dtypeSetLogicUnsized((nodep->lhsp()->width() * times), - (nodep->lhsp()->widthMin() * times), + nodep->dtypeSetLogicUnsized((nodep->srcp()->width() * times), + (nodep->srcp()->widthMin() * times), VSigning::UNSIGNED); } } @@ -898,7 +898,7 @@ private: userIterateAndNext(nodep->lsbp(), WidthVP{SELF, PRELIM}.p()); checkCvtUS(nodep->fromp()); iterateCheckSizedSelf(nodep, "Select Width", nodep->widthp(), SELF, BOTH); - iterateCheckSizedSelf(nodep, "Select LHS", nodep->lhsp(), SELF, BOTH); + iterateCheckSizedSelf(nodep, "Select LHS", nodep->fromp(), SELF, BOTH); V3Const::constifyParamsEdit(nodep->widthp()); // widthp may change const AstConst* const widthConstp = VN_CAST(nodep->widthp(), Const); if (!widthConstp) { @@ -1141,7 +1141,7 @@ private: void visit(AstSelBit* nodep) override { // Just a quick check as after V3Param these nodes instead are AstSel's userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel - userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel + userIterateAndNext(nodep->bitp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel userIterateAndNext(nodep->thsp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel userIterateAndNext(nodep->attrp(), WidthVP{SELF, BOTH}.p()); AstNode* const selp = V3Width::widthSelNoIterEdit(nodep); @@ -1155,8 +1155,8 @@ private: void visit(AstSelExtract* nodep) override { // Just a quick check as after V3Param these nodes instead are AstSel's userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel - userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel - userIterateAndNext(nodep->thsp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel + userIterateAndNext(nodep->leftp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel + userIterateAndNext(nodep->rightp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel userIterateAndNext(nodep->attrp(), WidthVP{SELF, BOTH}.p()); AstNode* const selp = V3Width::widthSelNoIterEdit(nodep); if (selp != nodep) { @@ -1168,8 +1168,8 @@ private: } void visit(AstSelPlus* nodep) override { userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel - userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel - userIterateAndNext(nodep->thsp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel + userIterateAndNext(nodep->bitp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel + userIterateAndNext(nodep->widthp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel userIterateAndNext(nodep->attrp(), WidthVP{SELF, BOTH}.p()); AstNode* const selp = V3Width::widthSelNoIterEdit(nodep); if (selp != nodep) { @@ -1181,8 +1181,8 @@ private: } void visit(AstSelMinus* nodep) override { userIterateAndNext(nodep->fromp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel - userIterateAndNext(nodep->rhsp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel - userIterateAndNext(nodep->thsp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel + userIterateAndNext(nodep->bitp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel + userIterateAndNext(nodep->widthp(), WidthVP{CONTEXT_DET, PRELIM}.p()); // FINAL in AstSel userIterateAndNext(nodep->attrp(), WidthVP{SELF, BOTH}.p()); AstNode* const selp = V3Width::widthSelNoIterEdit(nodep); if (selp != nodep) { @@ -1693,6 +1693,10 @@ private: // visit VL_DO_DANGLING(userIterate(newp, nullptr), newp); } + void visit(AstConstraintRefDType* nodep) override { + if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed + nodep->dtypep(nodep); + } void visit(AstDynArrayDType* nodep) override { if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed // Iterate into subDTypep() to resolve that type and update pointer. @@ -2090,6 +2094,20 @@ private: VL_DANGLING(underp); } } + void visit(AstConstraintBefore* nodep) override { + userIterateAndNext(nodep->lhssp(), WidthVP{SELF, BOTH}.p()); + userIterateAndNext(nodep->rhssp(), WidthVP{SELF, BOTH}.p()); + } + void visit(AstConstraintExpr* nodep) override { + userIterateAndNext(nodep->exprp(), WidthVP{SELF, BOTH}.p()); + } + void visit(AstConstraintUnique* nodep) override { + userIterateAndNext(nodep->rangesp(), WidthVP{SELF, BOTH}.p()); + } + void visit(AstDistItem* nodep) override { + userIterate(nodep->rangep(), WidthVP{SELF, BOTH}.p()); + userIterate(nodep->weightp(), WidthVP{SELF, BOTH}.p()); + } void visit(AstVar* nodep) override { // if (debug()) nodep->dumpTree("- InitPre: "); // Must have deterministic constant width @@ -2537,16 +2555,16 @@ private: // Similar logic in V3Case inewp = irangep->newAndFromInside(nodep->exprp(), irangep->lhsp()->unlinkFrBack(), irangep->rhsp()->unlinkFrBack()); - } else if (VN_IS(itemDtp, UnpackArrayDType)) { - nodep->v3error("Unsupported: inside (set membership operator) on unpacked array"); - // Need the AstInside type to persist, then - // for parameters, need V3Simulate support. - // For non-parameters, need runtime support. - continue; - } else if (VN_IS(itemDtp, AssocArrayDType) || VN_IS(itemDtp, DynArrayDType) + } else if (VN_IS(itemDtp, UnpackArrayDType) || VN_IS(itemDtp, DynArrayDType) || VN_IS(itemDtp, QueueDType)) { - nodep->v3error( - "Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13)"); + // Unsupported in parameters + inewp = new AstCMethodHard{itemp->fileline(), itemp->unlinkFrBack(), "inside", + nodep->exprp()->cloneTreePure(true)}; + inewp->dtypeSetBit(); + inewp->didWidth(true); + } else if (VN_IS(itemDtp, AssocArrayDType)) { + nodep->v3error("Inside operator not specified on associative arrays (IEEE " + "1800-2017 11.4.13)"); continue; } else { inewp = AstEqWild::newTyped(itemp->fileline(), nodep->exprp()->cloneTreePure(true), @@ -2723,7 +2741,10 @@ private: if (AstVar* const varp = VN_CAST(foundp, Var)) { nodep->dtypep(foundp->dtypep()); nodep->varp(varp); - varp->usedVirtIface(true); + AstIface* const ifacep = adtypep->ifacep(); + varp->sensIfacep(ifacep); + nodep->fromp()->foreach( + [ifacep](AstVarRef* const refp) { refp->varp()->sensIfacep(ifacep); }); return; } UINFO(1, "found object " << foundp << endl); @@ -2791,6 +2812,13 @@ private: VL_DO_DANGLING(pushDeletep(nodep), nodep); return true; } + if (VN_IS(foundp, Constraint)) { + // We don't support constraints yet, so just keep as unlinked for now + // Presumably we'll next see a constraint_mode AstMethodCall + nodep->dtypep(nodep->findConstraintRefDType()); + UINFO(9, "Unsupported constraint select " << nodep << endl); + return true; + } UINFO(1, "found object " << foundp << endl); nodep->v3fatalSrc("MemberSel of non-variable\n" << nodep->warnContextPrimary() << '\n' @@ -2803,7 +2831,7 @@ private: VSpellCheck speller; for (AstClass* classp = first_classp; classp;) { for (AstNode* itemp = classp->membersp(); itemp; itemp = itemp->nextp()) { - if (VN_IS(itemp, Var) || VN_IS(itemp, EnumItemRef)) { + if (VN_IS(itemp, Constraint) || VN_IS(itemp, EnumItemRef) || VN_IS(itemp, Var)) { speller.pushCandidate(itemp->prettyName()); } } @@ -2913,10 +2941,12 @@ private: methodCallQueue(nodep, adtypep); } else if (AstClassRefDType* const adtypep = VN_CAST(fromDtp, ClassRefDType)) { methodCallClass(nodep, adtypep); + } else if (AstIfaceRefDType* const adtypep = VN_CAST(fromDtp, IfaceRefDType)) { + methodCallIfaceRef(nodep, adtypep); } else if (AstUnpackArrayDType* const adtypep = VN_CAST(fromDtp, UnpackArrayDType)) { methodCallUnpack(nodep, adtypep); - } else if (basicp && nodep->name() == "constraint_mode") { - methodCallConstraint(nodep, basicp); + } else if (AstConstraintRefDType* const adtypep = VN_CAST(fromDtp, ConstraintRefDType)) { + methodCallConstraint(nodep, adtypep); } else if (basicp && basicp->isEvent()) { methodCallEvent(nodep, basicp); } else if (basicp && basicp->isString()) { @@ -3496,6 +3526,38 @@ private: << "() should be handled"); } } + void methodCallIfaceRef(AstMethodCall* nodep, AstIfaceRefDType* adtypep) { + AstIface* const ifacep = adtypep->ifacep(); + UINFO(1, __FUNCTION__ << ":" << nodep << endl); + if (AstNodeFTask* const ftaskp + = VN_CAST(m_memberMap.findMember(ifacep, nodep->name()), NodeFTask)) { + UINFO(1, __FUNCTION__ << "AstNodeFTask" << nodep << endl); + userIterate(ftaskp, nullptr); + if (ftaskp->isStatic()) { + AstNodeExpr* argsp = nullptr; + if (nodep->pinsp()) argsp = nodep->pinsp()->unlinkFrBackWithNext(); + AstNodeFTaskRef* newp = nullptr; + if (VN_IS(ftaskp, Task)) { + newp = new AstTaskRef{nodep->fileline(), ftaskp->name(), argsp}; + } else { + newp = new AstFuncRef{nodep->fileline(), ftaskp->name(), argsp}; + } + newp->taskp(ftaskp); + newp->classOrPackagep(ifacep); + nodep->replaceWith(newp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + } else { + nodep->taskp(ftaskp); + nodep->dtypeFrom(ftaskp); + nodep->classOrPackagep(ifacep); + if (VN_IS(ftaskp, Task)) nodep->dtypeSetVoid(); + processFTaskRefArgs(nodep); + } + return; + } + nodep->v3error("Member reference from interface to " + << nodep->prettyNameQ() << " is not referencing a valid task or function "); + } void methodCallClass(AstMethodCall* nodep, AstClassRefDType* adtypep) { // No need to width-resolve the class, as it was done when we did the child AstClass* const first_classp = adtypep->classp(); @@ -3557,6 +3619,11 @@ private: nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitTrue{}}); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; + } else if (nodep->name() == "constraint_mode") { + nodep->v3warn(CONSTRAINTIGN, "Unsupported: 'constraint_mode' called on object"); + nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitTrue{}}); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + return; } classp = classp->extendsp() ? classp->extendsp()->classp() : nullptr; } @@ -3576,8 +3643,8 @@ private: } nodep->dtypeSetSigned32(); // Guess on error } - void methodCallConstraint(AstMethodCall* nodep, AstBasicDType*) { - // Method call on constraint (currently hacked as just a var) + void methodCallConstraint(AstMethodCall* nodep, AstConstraintRefDType*) { + // Method call on constraint if (nodep->name() == "constraint_mode") { methodOkArguments(nodep, 0, 1); nodep->v3warn(CONSTRAINTIGN, "constraint_mode ignored (unsupported)"); @@ -3585,7 +3652,9 @@ private: nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}}); VL_DO_DANGLING(pushDeletep(nodep), nodep); } else { - nodep->v3fatalSrc("Unknown built-in constraint method " << nodep->prettyNameQ()); + nodep->v3error("No such constraint method " << nodep->prettyNameQ()); + nodep->replaceWith(new AstConst{nodep->fileline(), AstConst::BitFalse{}}); + VL_DO_DANGLING(pushDeletep(nodep), nodep); } } void methodCallRandMode(AstMethodCall* nodep) { @@ -3805,8 +3874,9 @@ private: classp->v3fatalSrc("Can't find class's new"); } if (classp->isVirtual() || classp->isInterfaceClass()) { - nodep->v3error( - "Illegal to call 'new' using an abstract virtual class (IEEE 1800-2017 8.21)"); + nodep->v3error("Illegal to call 'new' using an abstract virtual class " + + AstNode::prettyNameQ(classp->origName()) + + " (IEEE 1800-2017 8.21)"); } } else { // super.new case // in this case class and taskp() should be properly linked in V3LinkDot.cpp during @@ -4318,14 +4388,14 @@ private: return valuep; } - static void checkEventAssignement(const AstNodeAssign* const asgnp) { + static void checkEventAssignment(const AstNodeAssign* const asgnp) { string unsupEvtAsgn; if (!usesDynamicScheduler(asgnp->lhsp())) unsupEvtAsgn = "to"; if (asgnp->rhsp()->dtypep()->isEvent() && !usesDynamicScheduler(asgnp->rhsp())) { unsupEvtAsgn += (unsupEvtAsgn.empty() ? "from" : " and from"); } if (!unsupEvtAsgn.empty()) { - asgnp->v3warn(E_UNSUPPORTED, "Assignement " + asgnp->v3warn(E_UNSUPPORTED, "Assignment " << unsupEvtAsgn << " event in statically scheduled context.\n" << asgnp->warnMore() @@ -4549,7 +4619,9 @@ private: userIterateAndNext(nodep->resultp(), m_vup); nodep->dtypeFrom(nodep->resultp()); } - void visit(AstForeach* nodep) override { + void visit(AstNodeForeach* nodep) override { + if (nodep->didWidth()) return; + nodep->didWidth(true); const AstSelLoopVars* const loopsp = VN_CAST(nodep->arrayp(), SelLoopVars); UASSERT_OBJ(loopsp, nodep, "No loop variables under foreach"); // if (debug()) nodep->dumpTree("- foreach-old: "); @@ -4558,20 +4630,16 @@ private: UASSERT_OBJ(fromp->dtypep(), fromp, "Missing data type"); AstNodeDType* fromDtp = fromp->dtypep()->skipRefp(); // Split into for loop - AstNode* bodyp = nodep->stmtsp(); // Might be null - if (bodyp) bodyp->unlinkFrBackWithNext(); // We record where the body needs to eventually go with bodyPointp - // (Can't use bodyp as might be null) AstNode* lastBodyPointp = nullptr; AstNode* newp = nullptr; // Major dimension first - while (AstNode* argsp - = loopsp->elementsp()) { // Loop advances due to below varp->unlinkFrBack() + for (AstNode *argsp = loopsp->elementsp(), *next_argsp; argsp; argsp = next_argsp) { + next_argsp = argsp->nextp(); const bool empty = VN_IS(argsp, Empty); AstVar* const varp = VN_CAST(argsp, Var); UASSERT_OBJ(varp || empty, argsp, "Missing foreach loop variable"); if (varp) varp->usedLoopIdx(true); - argsp->unlinkFrBack(); if (!fromDtp) { argsp->v3error("foreach loop variables exceed number of indices of array"); VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); @@ -4582,121 +4650,138 @@ private: UINFO(9, "- from on " << fromp << endl); UINFO(9, "- from dtp " << fromDtp << endl); - FileLine* const fl = argsp->fileline(); - AstNode* bodyPointp = new AstBegin{fl, "[EditWrapper]", nullptr}; - AstNode* loopp = nullptr; - if (const AstNodeArrayDType* const adtypep = VN_CAST(fromDtp, NodeArrayDType)) { - if (varp) { - loopp = createForeachLoopRanged(nodep, bodyPointp, varp, adtypep->declRange()); - } + if (VN_IS(nodep, ConstraintForeach)) { + // For now unsupported + userIterate(varp, nullptr); // Prep for next - fromDtp = fromDtp->subDTypep(); - } else if (AstBasicDType* const adtypep = VN_CAST(fromDtp, BasicDType)) { - if (adtypep->isString()) { - if (varp) { - AstConst* const leftp = new AstConst{fl, AstConst::Signed32{}, 0}; - AstLt* const condp - = new AstLt{fl, new AstVarRef{fl, varp, VAccess::READ}, - new AstLenN{fl, fromp->cloneTreePure(false)}}; - AstAdd* const incp - = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1}, - new AstVarRef{fl, varp, VAccess::READ}}; - loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, condp, incp); - } - } else if (!adtypep->isRanged()) { - argsp->v3error("Illegal to foreach loop on basic '" + fromDtp->prettyTypeName() - + "'"); - VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - VL_DO_DANGLING(bodyPointp->deleteTree(), bodyPointp); - return; - } else { + fromDtp = nullptr; + } else { + argsp->unlinkFrBack(); + + FileLine* const fl = argsp->fileline(); + AstNode* bodyPointp = new AstBegin{fl, "[EditWrapper]", nullptr}; + AstNode* loopp = nullptr; + if (const AstNodeArrayDType* const adtypep = VN_CAST(fromDtp, NodeArrayDType)) { if (varp) { loopp = createForeachLoopRanged(nodep, bodyPointp, varp, adtypep->declRange()); } - } - // Prep for next - fromDtp = nullptr; - } else if (VN_IS(fromDtp, DynArrayDType) || VN_IS(fromDtp, QueueDType)) { - if (varp) { - auto* const leftp = new AstConst{fl, AstConst::Signed32{}, 0}; - auto* const sizep - = new AstCMethodHard{fl, fromp->cloneTreePure(false), "size"}; - sizep->dtypeSetSigned32(); - sizep->didWidth(true); - sizep->protect(false); - AstNodeExpr* const condp - = new AstLt{fl, new AstVarRef{fl, varp, VAccess::READ}, sizep}; - AstNodeExpr* const incp - = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1}, - new AstVarRef{fl, varp, VAccess::READ}}; - loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, condp, incp); - } - // Prep for next - fromDtp = fromDtp->subDTypep(); - } else if (const AstAssocArrayDType* const adtypep - = VN_CAST(fromDtp, AssocArrayDType)) { - // Make this: var KEY_TYPE index; - // bit index__Vfirst; - // index__Vfirst = 0; - // if (0 != array.first(index)) - // do body while (index__Vfirst || 0 != array.next(index)) - varp->dtypeFrom(adtypep->keyDTypep()); - AstVar* const first_varp = new AstVar{ - fl, VVarType::BLOCKTEMP, varp->name() + "__Vfirst", VFlagBitPacked{}, 1}; - first_varp->usedLoopIdx(true); - AstNodeExpr* const firstp = new AstMethodCall{ - fl, fromp->cloneTreePure(false), "first", - new AstArg{fl, "", new AstVarRef{fl, varp, VAccess::READWRITE}}}; - AstNodeExpr* const nextp = new AstMethodCall{ - fl, fromp->cloneTreePure(false), "next", - new AstArg{fl, "", new AstVarRef{fl, varp, VAccess::READWRITE}}}; - AstNode* const first_clearp - = new AstAssign{fl, new AstVarRef{fl, first_varp, VAccess::WRITE}, - new AstConst{fl, AstConst::BitFalse{}}}; - auto* const orp = new AstLogOr{fl, new AstVarRef{fl, first_varp, VAccess::READ}, - new AstNeq{fl, new AstConst{fl, 0}, nextp}}; - AstNode* const whilep = new AstWhile{fl, orp, first_clearp}; - first_clearp->addNext(bodyPointp); - AstNode* const ifbodyp - = new AstAssign{fl, new AstVarRef{fl, first_varp, VAccess::WRITE}, - new AstConst{fl, AstConst::BitTrue{}}}; - ifbodyp->addNext(whilep); - AstNode* const stmtsp = varp; // New statements for under new Begin - stmtsp->addNext(first_varp); - stmtsp->addNext( - new AstIf{fl, new AstNeq{fl, new AstConst{fl, 0}, firstp}, ifbodyp}); - loopp = new AstBegin{nodep->fileline(), "", stmtsp, false, true}; - // Prep for next - fromDtp = fromDtp->subDTypep(); - } else { - argsp->v3error("Illegal to foreach loop on '" + fromDtp->prettyTypeName() + "'"); - VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - return; - } - // New loop goes UNDER previous loop - if (varp) { - if (!newp) { - newp = loopp; + // Prep for next + fromDtp = fromDtp->subDTypep(); + } else if (AstBasicDType* const adtypep = VN_CAST(fromDtp, BasicDType)) { + if (adtypep->isString()) { + if (varp) { + AstConst* const leftp = new AstConst{fl, AstConst::Signed32{}, 0}; + AstLt* const condp + = new AstLt{fl, new AstVarRef{fl, varp, VAccess::READ}, + new AstLenN{fl, fromp->cloneTreePure(false)}}; + AstAdd* const incp + = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1}, + new AstVarRef{fl, varp, VAccess::READ}}; + loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, condp, incp); + } + } else if (!adtypep->isRanged()) { + argsp->v3error("Illegal to foreach loop on basic '" + + fromDtp->prettyTypeName() + "'"); + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + VL_DO_DANGLING(bodyPointp->deleteTree(), bodyPointp); + return; + } else { + if (varp) { + loopp = createForeachLoopRanged(nodep, bodyPointp, varp, + adtypep->declRange()); + } + } + // Prep for next + fromDtp = nullptr; + } else if (VN_IS(fromDtp, DynArrayDType) || VN_IS(fromDtp, QueueDType)) { + if (varp) { + auto* const leftp = new AstConst{fl, AstConst::Signed32{}, 0}; + auto* const sizep + = new AstCMethodHard{fl, fromp->cloneTreePure(false), "size"}; + sizep->dtypeSetSigned32(); + sizep->didWidth(true); + sizep->protect(false); + AstNodeExpr* const condp + = new AstLt{fl, new AstVarRef{fl, varp, VAccess::READ}, sizep}; + AstNodeExpr* const incp + = new AstAdd{fl, new AstConst{fl, AstConst::Signed32{}, 1}, + new AstVarRef{fl, varp, VAccess::READ}}; + loopp = createForeachLoop(nodep, bodyPointp, varp, leftp, condp, incp); + } + // Prep for next + fromDtp = fromDtp->subDTypep(); + } else if (const AstAssocArrayDType* const adtypep + = VN_CAST(fromDtp, AssocArrayDType)) { + // Make this: var KEY_TYPE index; + // bit index__Vfirst; + // index__Vfirst = 0; + // if (0 != array.first(index)) + // do body while (index__Vfirst || 0 != array.next(index)) + varp->dtypeFrom(adtypep->keyDTypep()); + AstVar* const first_varp = new AstVar{ + fl, VVarType::BLOCKTEMP, varp->name() + "__Vfirst", VFlagBitPacked{}, 1}; + first_varp->usedLoopIdx(true); + AstNodeExpr* const firstp = new AstMethodCall{ + fl, fromp->cloneTreePure(false), "first", + new AstArg{fl, "", new AstVarRef{fl, varp, VAccess::READWRITE}}}; + AstNodeExpr* const nextp = new AstMethodCall{ + fl, fromp->cloneTreePure(false), "next", + new AstArg{fl, "", new AstVarRef{fl, varp, VAccess::READWRITE}}}; + AstNode* const first_clearp + = new AstAssign{fl, new AstVarRef{fl, first_varp, VAccess::WRITE}, + new AstConst{fl, AstConst::BitFalse{}}}; + auto* const orp + = new AstLogOr{fl, new AstVarRef{fl, first_varp, VAccess::READ}, + new AstNeq{fl, new AstConst{fl, 0}, nextp}}; + AstNode* const whilep = new AstWhile{fl, orp, first_clearp}; + first_clearp->addNext(bodyPointp); + AstNode* const ifbodyp + = new AstAssign{fl, new AstVarRef{fl, first_varp, VAccess::WRITE}, + new AstConst{fl, AstConst::BitTrue{}}}; + ifbodyp->addNext(whilep); + AstNode* const stmtsp = varp; // New statements for under new Begin + stmtsp->addNext(first_varp); + stmtsp->addNext( + new AstIf{fl, new AstNeq{fl, new AstConst{fl, 0}, firstp}, ifbodyp}); + loopp = new AstBegin{nodep->fileline(), "", stmtsp, false, true}; + // Prep for next + fromDtp = fromDtp->subDTypep(); } else { - lastBodyPointp->replaceWith(loopp); + argsp->v3error("Illegal to foreach loop on '" + fromDtp->prettyTypeName() + + "'"); + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); + return; + } + // New loop goes UNDER previous loop + if (varp) { + if (!newp) { + newp = loopp; + } else { + lastBodyPointp->replaceWith(loopp); + } + lastBodyPointp = bodyPointp; } - lastBodyPointp = bodyPointp; } } // The parser validates we don't have "foreach (array[,,,])" - UASSERT_OBJ(newp, nodep, "foreach has no non-empty loop variable"); - if (bodyp) { - lastBodyPointp->replaceWith(bodyp); + AstNode* const bodyp = nodep->stmtsp(); + if (VN_IS(nodep, ConstraintForeach)) { + userIterateAndNext(bodyp, nullptr); } else { - lastBodyPointp->unlinkFrBack(); + UASSERT_OBJ(newp, nodep, "foreach has no non-empty loop variable"); + if (bodyp) { + lastBodyPointp->replaceWith(bodyp->unlinkFrBackWithNext()); + } else { + lastBodyPointp->unlinkFrBack(); + } + // if (debug()) newp->dumpTreeAndNext(cout, "- foreach-new: "); + nodep->replaceWith(newp); + if (lastBodyPointp) VL_DO_DANGLING(lastBodyPointp->deleteTree(), lastBodyPointp); + VL_DO_DANGLING(nodep->deleteTree(), nodep); } - // if (debug()) newp->dumpTreeAndNext(cout, "- foreach-new: "); - nodep->replaceWith(newp); - VL_DO_DANGLING(lastBodyPointp->deleteTree(), lastBodyPointp); - VL_DO_DANGLING(nodep->deleteTree(), nodep); } - AstNode* createForeachLoopRanged(AstForeach* nodep, AstNode* bodysp, AstVar* varp, + AstNode* createForeachLoopRanged(AstNodeForeach* nodep, AstNode* bodysp, AstVar* varp, const VNumRange& declRange) { FileLine* const fl = varp->fileline(); AstNodeExpr* const leftp = new AstConst{fl, AstConst::Signed32{}, declRange.left()}; @@ -4714,7 +4799,7 @@ private: } return createForeachLoop(nodep, bodysp, varp, leftp, condp, incp); } - AstNode* createForeachLoop(AstForeach* nodep, AstNode* bodysp, AstVar* varp, + AstNode* createForeachLoop(AstNodeForeach* nodep, AstNode* bodysp, AstVar* varp, AstNodeExpr* leftp, AstNodeExpr* condp, AstNodeExpr* incp) { FileLine* const fl = varp->fileline(); auto* const whilep = new AstWhile{ @@ -4811,7 +4896,7 @@ private: } if (nodep->hasDType() && nodep->dtypep()->isEvent()) { - checkEventAssignement(nodep); + checkEventAssignment(nodep); v3Global.setAssignsEvents(); } } @@ -4843,6 +4928,21 @@ private: } else if (inPct) { inPct = false; bool added = false; + const AstNodeDType* const dtypep = argp ? argp->dtypep()->skipRefp() : nullptr; + const AstBasicDType* const basicp = dtypep ? dtypep->basicp() : nullptr; + if (ch == '?') { // Unspecified by user, guess + if (argp && argp->isDouble()) { + ch = 'g'; + } else if (argp && argp->isString()) { + ch = '@'; + } else if (nodep->missingArgChar() == 'd' && argp->isSigned()) { + ch = '~'; + } else if (basicp) { + ch = nodep->missingArgChar(); + } else { + ch = 'p'; + } + } switch (std::tolower(ch)) { case '%': break; // %% - just output a % case 'm': break; // %m - auto insert "name" @@ -4871,8 +4971,6 @@ private: break; } case 'p': { // Pattern - const AstNodeDType* const dtypep = argp ? argp->dtypep()->skipRefp() : nullptr; - const AstBasicDType* const basicp = dtypep ? dtypep->basicp() : nullptr; if (basicp && basicp->isString()) { added = true; newFormat += "\"%@\""; @@ -4944,19 +5042,6 @@ private: } break; } - case '?': { // Unspecified by user, guess - if (argp && argp->isDouble()) { - ch = 'g'; - } else if (argp && argp->isString()) { - ch = '@'; - } else if (nodep->missingArgChar() == 'd' && argp->isSigned()) { - ch = '~'; - } else { - ch = nodep->missingArgChar(); - } - if (argp) argp = VN_AS(argp->nextp(), NodeExpr); - break; - } default: { // Most operators, just move to next argument if (argp) argp = VN_AS(argp->nextp(), NodeExpr); break; @@ -4973,6 +5058,7 @@ private: nodep->text(newFormat); UINFO(9, " Display out " << nodep->text() << endl); } + void visit(AstConstraintRef* nodep) override { userIterateChildren(nodep, nullptr); } void visit(AstDisplay* nodep) override { assertAtStatement(nodep); if (nodep->filep()) iterateCheckFileDesc(nodep, nodep->filep(), BOTH); @@ -5640,6 +5726,7 @@ private: AstNodeExpr* const newp = new AstResizeLValue{pinp->fileline(), pinp}; relinkHandle.relink(newp); } + if (portp->isWritable()) V3LinkLValue::linkLValueSet(pinp); if (!portp->basicp() || portp->basicp()->isOpaque()) { checkClassAssign(nodep, "Function Argument", pinp, portDTypep); userIterate(pinp, WidthVP{portDTypep, FINAL}.p()); diff --git a/src/V3Width.h b/src/V3Width.h index 0ac3a6b25..6d3da85cd 100644 --- a/src/V3Width.h +++ b/src/V3Width.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3WidthCommit.cpp b/src/V3WidthCommit.cpp index abfb20bab..c3ac9bc95 100644 --- a/src/V3WidthCommit.cpp +++ b/src/V3WidthCommit.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -99,9 +99,9 @@ private: nodep->v3warn(ENCAPSULATED, nodep->prettyNameQ() << " is hidden as " << how << " within this context (IEEE 1800-2017 8.18)\n" - << nodep->warnContextPrimary() << endl + << nodep->warnContextPrimary() << "\n" << nodep->warnOther() - << "... Location of definition" << endl + << "... Location of definition\n" << defp->warnContextSecondary()); } } diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h index 4c61e0da8..b8c963d13 100644 --- a/src/V3WidthCommit.h +++ b/src/V3WidthCommit.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3WidthRemove.h b/src/V3WidthRemove.h index 23469299e..7c9a6a8a9 100644 --- a/src/V3WidthRemove.h +++ b/src/V3WidthRemove.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp index 8c8aa4bb4..3935d083b 100644 --- a/src/V3WidthSel.cpp +++ b/src/V3WidthSel.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -37,7 +37,6 @@ VL_DEFINE_DEBUG_FUNCTIONS; // Width state, as a visitor of each AstNode class WidthSelVisitor final : public VNVisitor { -private: // IMPORTANT //**** This is not a normal visitor, in that all iteration is instead // done by the caller (V3Width). This avoids duplicating much of the @@ -216,7 +215,7 @@ private: if (debug() >= 9) nodep->backp()->dumpTree("- SELBT0: "); // lhsp/rhsp do not need to be constant AstNodeExpr* const fromp = nodep->fromp()->unlinkFrBack(); - AstNodeExpr* const rhsp = nodep->rhsp()->unlinkFrBack(); // bit we're extracting + AstNodeExpr* const rhsp = nodep->bitp()->unlinkFrBack(); // bit we're extracting if (debug() >= 9) nodep->dumpTree("- SELBT2: "); const FromData fromdata = fromDataForArray(nodep, fromp); AstNodeDType* const ddtypep = fromdata.m_dtypep; @@ -354,8 +353,8 @@ private: AstNodeDType* const ddtypep = fromdata.m_dtypep; const VNumRange fromRange = fromdata.m_fromRange; if (VN_IS(ddtypep, QueueDType)) { - AstNodeExpr* const qleftp = nodep->rhsp()->unlinkFrBack(); - AstNodeExpr* const qrightp = nodep->thsp()->unlinkFrBack(); + AstNodeExpr* const qleftp = nodep->leftp()->unlinkFrBack(); + AstNodeExpr* const qrightp = nodep->rightp()->unlinkFrBack(); AstNodeExpr* const qleftBacknessp = selQueueBackness(qleftp); AstNodeExpr* const qrightBacknessp = selQueueBackness(qrightp); // Use special methods to refer to back rather than math using @@ -381,8 +380,8 @@ private: "First value of [a:b] isn't a constant, maybe you want +: or -:"); checkConstantOrReplace(nodep->rightp(), "Second value of [a:b] isn't a constant, maybe you want +: or -:"); - AstNodeExpr* const msbp = nodep->rhsp()->unlinkFrBack(); - AstNodeExpr* const lsbp = nodep->thsp()->unlinkFrBack(); + AstNodeExpr* const msbp = nodep->leftp()->unlinkFrBack(); + AstNodeExpr* const lsbp = nodep->rightp()->unlinkFrBack(); int32_t msb = VN_AS(msbp, Const)->toSInt(); int32_t lsb = VN_AS(lsbp, Const)->toSInt(); const int32_t elem = (msb > lsb) ? (msb - lsb + 1) : (lsb - msb + 1); diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 2d23c0d5d..cee743a50 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -234,10 +234,12 @@ static void process() { V3Inst::dearrayAll(v3Global.rootp()); V3LinkDot::linkDotArrayed(v3Global.rootp()); - // Generate classes and tasks required to maintain proper lifetimes for references in - // forks - V3Fork::makeDynamicScopes(v3Global.rootp()); - V3Fork::makeTasks(v3Global.rootp()); + if (v3Global.opt.timing().isSetTrue()) { + // Generate classes and tasks required to maintain proper lifetimes for references + // in forks + V3Fork::makeDynamicScopes(v3Global.rootp()); + V3Fork::makeTasks(v3Global.rootp()); + } // Task inlining & pushing BEGINs names to variables/cells // Begin processing must be after Param, before module inlining @@ -636,8 +638,10 @@ static void verilate(const string& argString) { // --FRONTEND------------------ // Cleanup - V3Os::unlinkRegexp(v3Global.opt.hierTopDataDir(), v3Global.opt.prefix() + "_*.tree"); + // Ideally we'd do prefix + "_*.*", and prefix + ".*", but this seems + // potentially disruptive to old behavior, and --skip-identical V3Os::unlinkRegexp(v3Global.opt.hierTopDataDir(), v3Global.opt.prefix() + "_*.dot"); + V3Os::unlinkRegexp(v3Global.opt.hierTopDataDir(), v3Global.opt.prefix() + "_*.tree"); V3Os::unlinkRegexp(v3Global.opt.hierTopDataDir(), v3Global.opt.prefix() + "_*.txt"); // Internal tests (after option parsing as need debug() setting, @@ -690,7 +694,7 @@ static void verilate(const string& argString) { const V3MtDisabledLockGuard mtDisabler{v3MtDisabledLock()}; UASSERT(v3Global.opt.hierarchical(), "hierarchical must be set"); - UASSERT(!v3Global.opt.hierChild(), "This must not be a hierarhcical-child run"); + UASSERT(!v3Global.opt.hierChild(), "This must not be a hierarchical-child run"); UASSERT(v3Global.opt.hierBlocks().empty(), "hierarchical-block must not be set"); if (v3Global.opt.gmake()) { v3Global.hierPlanp()->writeCommandArgsFiles(false); @@ -717,6 +721,9 @@ static void verilate(const string& argString) { argString); } + V3Os::filesystemFlushBuildDir(v3Global.opt.makeDir()); + if (v3Global.opt.hierTop()) V3Os::filesystemFlushBuildDir(v3Global.opt.hierTopDataDir()); + // Final writing shouldn't throw warnings, but... V3Error::abortIfWarnings(); } @@ -747,6 +754,7 @@ static void execBuildJob() { UINFO(1, "Start Build\n"); const string cmdStr = buildMakeCmd(v3Global.opt.prefix() + ".mk", ""); + V3Os::filesystemFlushBuildDir(v3Global.opt.hierTopDataDir()); const int exit_code = V3Os::system(cmdStr); if (exit_code != 0) { v3error(cmdStr << " exited with " << exit_code << std::endl); @@ -759,6 +767,7 @@ static void execHierVerilation() { const string makefile = v3Global.opt.prefix() + "_hier.mk "; const string target = v3Global.opt.build() ? " hier_build" : " hier_verilation"; const string cmdStr = buildMakeCmd(makefile, target); + V3Os::filesystemFlushBuildDir(v3Global.opt.hierTopDataDir()); const int exit_code = V3Os::system(cmdStr); if (exit_code != 0) { v3error(cmdStr << " exited with " << exit_code << std::endl); diff --git a/src/VlcBucket.h b/src/VlcBucket.h index 3d46bd4c7..0f2697db0 100644 --- a/src/VlcBucket.h +++ b/src/VlcBucket.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -31,7 +31,6 @@ // has hit that point with sufficient coverage. class VlcBuckets final { -private: // MEMBERS uint64_t* m_datap = nullptr; ///< Pointer to first bucket (dynamically allocated) uint64_t m_dataSize = 0; ///< Current entries in m_datap @@ -121,7 +120,7 @@ public: for (uint64_t i = 0; i < m_dataSize; ++i) { if (hits(i)) std::cout << "," << i; } - std::cout << std::endl; + std::cout << "\n"; } }; diff --git a/src/VlcMain.cpp b/src/VlcMain.cpp index 34e314d6d..00baa18c2 100644 --- a/src/VlcMain.cpp +++ b/src/VlcMain.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -103,16 +103,16 @@ void VlcOptions::parseOptsList(int argc, char** argv) { void VlcOptions::showVersion(bool verbose) { std::cout << version(); - std::cout << endl; + std::cout << "\n"; if (!verbose) return; - std::cout << endl; - std::cout << "Copyright 2003-2023 by Wilson Snyder. Verilator is free software; you can\n"; + std::cout << "\n"; + std::cout << "Copyright 2003-2024 by Wilson Snyder. Verilator is free software; you can\n"; std::cout << "redistribute it and/or modify the Verilator internals under the terms of\n"; std::cout << "either the GNU Lesser General Public License Version 3 or the Perl Artistic\n"; std::cout << "License Version 2.0.\n"; - std::cout << endl; + std::cout << "\n"; std::cout << "See https://verilator.org for documentation\n"; } diff --git a/src/VlcOptions.h b/src/VlcOptions.h index a81737b4f..2784dde03 100644 --- a/src/VlcOptions.h +++ b/src/VlcOptions.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/VlcPoint.h b/src/VlcPoint.h index a4618daea..aeb326fca 100644 --- a/src/VlcPoint.h +++ b/src/VlcPoint.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -36,7 +36,6 @@ // VlcPoint - A coverage point (across all tests) class VlcPoint final { -private: // MEMBERS string m_name; //< Name of the point uint64_t m_pointNum; //< Point number @@ -108,7 +107,6 @@ public: // VlcPoints - Container of all points class VlcPoints final { -private: // MEMBERS using NameMap = std::map; // Sorted by name (ordered) NameMap m_nameMap; //< Name to point-number diff --git a/src/VlcSource.h b/src/VlcSource.h index 74584be63..bcd51166d 100644 --- a/src/VlcSource.h +++ b/src/VlcSource.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -31,7 +31,6 @@ class VlcPoint; // VlcColumnCount - count at specific source file, line and column class VlcSourceCount final { -private: // TYPES using PointsSet = std::set; diff --git a/src/VlcTest.h b/src/VlcTest.h index 0a60758ba..4d3024c7a 100644 --- a/src/VlcTest.h +++ b/src/VlcTest.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -30,7 +30,6 @@ // VlcTest - a single testrun i.e. a file containing coverage data class VlcTest final { -private: // MEMBERS string m_name; //< Name of the test double m_computrons; //< Runtime for the test diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp index 5ca8d968e..60ea127ac 100644 --- a/src/VlcTop.cpp +++ b/src/VlcTop.cpp @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/VlcTop.h b/src/VlcTop.h index 3f05bf343..d48568bd5 100644 --- a/src/VlcTop.h +++ b/src/VlcTop.h @@ -6,7 +6,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/astgen b/src/astgen index 0ace3f347..1be8dff1c 100755 --- a/src/astgen +++ b/src/astgen @@ -1,5 +1,5 @@ #!/usr/bin/env python3 -# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0209,C0301,C0302,R0902,R0913,R0914,R0912,R0915,W0621 +# pylint: disable=C0103,C0114,C0115,C0116,C0123,C0209,C0301,C0302,R0902,R0904,R0913,R0914,R0912,R0915,W0511,W0621 ###################################################################### import argparse @@ -29,6 +29,7 @@ class Node: self._ordIdx = None # Ordering index of this class self._arity = -1 # Arity of node self._ops = {} # Operands of node + self._ptrs = [] # Pointer members of node (name, types) @property def name(self): @@ -54,6 +55,11 @@ class Node: def lineno(self): return self._lineno + @property + def ptrs(self): + assert self.isCompleted + return self._ptrs + # Pre completion methods def addSubClass(self, subClass): assert not self.isCompleted @@ -73,6 +79,10 @@ class Node: return self.superClass.getOp(n) return None + def addPtr(self, name, monad, kind): + name = re.sub(r'^m_', '', name) + self._ptrs.append({'name': name, 'monad': monad, 'kind': kind}) + # Computes derived properties over entire class hierarchy. # No more changes to the hierarchy are allowed once this was called def complete(self, typeId=0, ordIdx=0): @@ -503,13 +513,16 @@ class Cpt: " // Generated by astgen with short-circuiting\n" + " void visit(Ast" + node.name + "* nodep) override {\n" + - " iterateAndNextNull(nodep->lhsp());\n" + - "".join(out_for_type_sc)) + " iterateAndNextNull(nodep->{op1}());\n".format( + op1=node.getOp(1)[0]) + "".join(out_for_type_sc)) if out_for_type[0]: - self.print(" iterateAndNextNull(nodep->rhsp());\n") + self.print( + " iterateAndNextNull(nodep->{op2}());\n".format( + op2=node.getOp(2)[0])) if node.isSubClassOf(AstNodes["NodeTriop"]): self.print( - " iterateAndNextNull(nodep->thsp());\n") + " iterateAndNextNull(nodep->{op3}());\n". + format(op3=node.getOp(3)[0])) self.print("".join(out_for_type) + " }\n") elif len(out_for_type) > 0: # Other types with something to print skip = node.name in self.tree_skip_visit @@ -647,15 +660,41 @@ def read_types(filename, Nodes, prefix): op = node.getOp(n) if op is None: error(lineno, - "Alaised op" + str(n) + " is not defined") + "Aliased op" + str(n) + " is not defined") else: node.addOp(n, ident, *op[1:]) + elif what == "ptr": + ident, sep, kind = partitionAndStrip(rest, ":") + ident = ident.strip() + kind = parseOpType(kind) + if not kind: + error( + lineno, "Bad type for '@astgen " + what + + "' (expecting Ast*, Optional[Ast*], or List[Ast*]):" + + decl) + if not re.match(r'^m_(\w+)$', ident): + error( + lineno, "Malformed '@astgen ptr'" + " identifier (expecting m_ in '" + ident + "')") + else: + node.addPtr(ident, *kind) + else: + error( + lineno, + "Malformed @astgen what (expecting 'op1'..'op4'," + + " 'alias op1'.., 'ptr'): " + what) else: line = re.sub(r'//.*$', '', line) if re.match(r'.*[Oo]p[1-9].*', line): error(lineno, "Use generated accessors to access op operands") + if re.match( + r'^\s*Ast[A-Z][A-Za-z0-9_]+\s*\*(\s*const)?\s+m_[A-Za-z0-9_]+\s*;', + line): + error(lineno, + "Use '@astgen ptr' for Ast pointer members: " + line) + checkFinishedNode(node) if hasErrors: sys.exit("%Error: Stopping due to errors reported above") @@ -700,7 +739,7 @@ def check_types(sortedTypes, prefix, abstractPrefix): hasOrderingError = True pred = expect[node] print( - "{file}:{lineno}: %Error: Definition of '{p}{n}' is out of order. Shold be {where}." + "{file}:{lineno}: %Error: Definition of '{p}{n}' is out of order. Should be {where}." .format(file=file, lineno=node.lineno, p=prefix, @@ -806,7 +845,7 @@ def write_report(filename): ################################################################################ -# Common code genaration +# Common code generation ################################################################################ @@ -904,7 +943,7 @@ def write_type_tests(prefix, nodeList): ################################################################################ -# Ast code genaration +# Ast code generation ################################################################################ @@ -933,14 +972,55 @@ def write_ast_type_info(filename): ['VNTypeInfo::{0}'.format(s) for s in opTypeList]) opNameStr = ', '.join(['"{0}"'.format(s) for s in opNameList]) fh.write( - ' {{ "Ast{name}", {{{opTypeStr}}}, {{{opNameStr}}} }},\n'. - format( + ' {{ "Ast{name}", {{{opTypeStr}}}, {{{opNameStr}}}, sizeof(Ast{name}) }},\n' + .format( name=node.name, opTypeStr=opTypeStr, opNameStr=opNameStr, )) +def write_ast_impl(filename): + with open_file(filename) as fh: + + def emitBlock(pattern, **fmt): + fh.write( + textwrap.indent(textwrap.dedent(pattern), + " ").format(**fmt)) + + for node in AstNodeList: + if node.name == "Node": + continue + emitBlock("const char* Ast{t}::brokenGen() const {{\n", + t=node.name) + if node.superClass.name != 'Node': + emitBlock(" BROKEN_BASE_RTN(Ast{base}::brokenGen());\n", + base=node.superClass.name) + for ptr in node.ptrs: + if ptr['monad'] == 'Optional': + emitBlock( + " BROKEN_RTN(m_{name} && !m_{name}->brokeExists());\n", + name=ptr['name']) + else: + emitBlock(" BROKEN_RTN(!m_{name});\n" + + " BROKEN_RTN(!m_{name}->brokeExists());\n", + name=ptr['name']) + # Node's broken rules can be specialized by declaring broken() + emitBlock(" return Ast{t}::broken(); }}\n", t=node.name) + + emitBlock("void Ast{t}::cloneRelinkGen() {{\n", t=node.name) + if node.superClass.name != 'Node': + emitBlock(" Ast{base}::cloneRelinkGen();\n", + base=node.superClass.name) + for ptr in node.ptrs: + emitBlock( + " if (m_{name} && m_{name}->clonep()) m_{name} = m_{name}->clonep();\n", + name=ptr['name'], + kind=ptr['kind']) + + emitBlock("}}\n") + + def write_ast_macros(filename): with open_file(filename) as fh: @@ -951,6 +1031,24 @@ def write_ast_macros(filename): for node in AstNodeList: fh.write("#define ASTGEN_MEMBERS_Ast{t} \\\n".format(t=node.name)) + any_ptr = False + for ptr in node.ptrs: + if not any_ptr: + fh.write("private: \\\n") + any_ptr = True + emitBlock("Ast{kind}* m_{name} = nullptr;", + name=ptr['name'], + kind=ptr['kind']) + if any_ptr: + fh.write("public: \\\n") + # TODO pointer accessors + # for ptr in node.ptrs: + # emitBlock( + # ("{kind}* {name}() const {{ return m_{name}; }}\n" + + # "void {name}({kind}* nodep) {{ m_{name} = nodep; }}"), + # name=ptr['name'], + # kind=ptr['kind']) + emitBlock('''\ Ast{t}* unlinkFrBack(VNRelinker* linkerp = nullptr) {{ return static_cast(AstNode::unlinkFrBack(linkerp)); @@ -966,6 +1064,8 @@ def write_ast_macros(filename): }} Ast{t}* clonep() const {{ return static_cast(AstNode::clonep()); }} Ast{t}* addNext(Ast{t}* nodep) {{ return static_cast(AstNode::addNext(this, nodep)); }} + const char* brokenGen() const override; + void cloneRelinkGen() override; ''', t=node.name) @@ -976,6 +1076,8 @@ def write_ast_macros(filename): ''', t=node.name) + hiddenMethods = [] + for n in range(1, 5): op = node.getOp(n) if not op: @@ -983,6 +1085,11 @@ def write_ast_macros(filename): name, monad, kind = op retrieve = ("VN_DBG_AS(op{n}p(), {kind})" if kind != "Node" else "op{n}p()").format(n=n, kind=kind) + superOp = node.superClass.getOp(n) + superName = None + if superOp: + superName = superOp[0] + hiddenMethods.append(superName) if monad == "List": emitBlock('''\ Ast{kind}* {name}() const VL_MT_STABLE {{ return {retrieve}; }} @@ -993,6 +1100,9 @@ def write_ast_macros(filename): Name=name[0].upper() + name[1:], n=n, retrieve=retrieve) + if superOp: + hiddenMethods.append("add" + superName[0].upper() + + superName[1:]) elif monad == "Optional": emitBlock('''\ Ast{kind}* {name}() const VL_MT_STABLE {{ return {retrieve}; }} @@ -1012,6 +1122,13 @@ def write_ast_macros(filename): n=n, retrieve=retrieve) + if hiddenMethods: + fh.write("private: \\\n") + for method in hiddenMethods: + fh.write(" using Ast{sup}::{method}; \\\n".format( + sup=node.superClass.name, method=method)) + fh.write("public: \\\n") + fh.write( " static_assert(true, \"\")\n") # Swallowing the semicolon @@ -1032,7 +1149,7 @@ def write_ast_yystype(filename): ################################################################################ -# DFG code genaration +# DFG code generation ################################################################################ @@ -1086,7 +1203,7 @@ def write_dfg_auto_classes(filename): fh.write(textwrap.dedent(pattern).format(**fmt)) for node in DfgVertexList: - # Only generate code for automatically derieved leaf nodes + # Only generate code for automatically derived leaf nodes if (node.file is not None) or not node.isLeaf: continue @@ -1106,7 +1223,7 @@ def write_dfg_auto_classes(filename): def write_dfg_ast_to_dfg(filename): with open_file(filename) as fh: for node in DfgVertexList: - # Only generate code for automatically derieved leaf nodes + # Only generate code for automatically derived leaf nodes if (node.file is not None) or (not node.isLeaf): continue @@ -1144,7 +1261,7 @@ def write_dfg_ast_to_dfg(filename): def write_dfg_dfg_to_ast(filename): with open_file(filename) as fh: for node in DfgVertexList: - # Only generate code for automatically derieved leaf nodes + # Only generate code for automatically derived leaf nodes if (node.file is not None) or (not node.isLeaf): continue @@ -1170,7 +1287,7 @@ parser = argparse.ArgumentParser( formatter_class=argparse.RawDescriptionHelpFormatter, description="""Generate V3Ast headers to reduce C++ code duplication.""", epilog= - """Copyright 2002-2023 by Wilson Snyder. This program is free software; you + """Copyright 2002-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. @@ -1259,7 +1376,7 @@ for node in AstNodeList: op = node.getOp(n) if op is not None: name, monad, kind = op - assert monad == "", "Cannot represnt AstNode as DfgVertex" + assert monad == "", "Cannot represent AstNode as DfgVertex" vertex.addOp(n, name, "", "") # Compute derived properties over the whole DfgVertex hierarchy @@ -1295,6 +1412,7 @@ if Args.classes: write_type_enum("Ast", AstNodeList) write_type_tests("Ast", AstNodeList) write_ast_type_info("V3Ast__gen_type_info.h") + write_ast_impl("V3Ast__gen_impl.h") write_ast_macros("V3Ast__gen_macros.h") write_ast_yystype("V3Ast__gen_yystype.h") # Write Dfg code @@ -1317,5 +1435,5 @@ for cpt in Args.infiles: ###################################################################### # Local Variables: -# compile-command: "cd obj_dbg && ../astgen -I.. V3Const.cpp" +# compile-command: "touch src/V3AstNodeExpr.h ; v4make" # End: diff --git a/src/bisonpre b/src/bisonpre index 507ca1668..3f97f0f2c 100755 --- a/src/bisonpre +++ b/src/bisonpre @@ -508,7 +508,7 @@ BISON GRAMMAR EXTENSIONS If the bison version is >= the specified version, include the given command. -Copyright 2002-2023 by Wilson Snyder. This program is free software; you +Copyright 2002-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/src/config_build.h b/src/config_build.h index f4204016c..ca5c9bd7e 100644 --- a/src/config_build.h +++ b/src/config_build.h @@ -8,7 +8,7 @@ // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/src/config_package.h.in b/src/config_package.h.in index 4588746aa..663244ce3 100644 --- a/src/config_package.h.in +++ b/src/config_package.h.in @@ -6,7 +6,7 @@ // // Code available from: https://verilator.org // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; +// Copyright 2003-2024 by Wilson Snyder. This program is free software; // you can redistribute it and/or modify it under the terms of either // the GNU Lesser General Public License Version 3 or // the Perl Artistic License Version 2.0. diff --git a/src/config_rev b/src/config_rev index 420140ec7..0640d85b1 100755 --- a/src/config_rev +++ b/src/config_rev @@ -2,7 +2,7 @@ # pylint: disable=C0103,C0114 ###################################################################### # -# Copyright 2005-2023 by Wilson Snyder. This program is free software; you +# Copyright 2005-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/src/cppcheck_filtered b/src/cppcheck_filtered index d023910ce..b158f724e 100755 --- a/src/cppcheck_filtered +++ b/src/cppcheck_filtered @@ -183,7 +183,7 @@ filters out unnecessary warnings related to Verilator. Run as: cd $VERILATOR_ROOT make -k cppcheck""", epilog= - """Copyright 2014-2023 by Wilson Snyder. This program is free software; you + """Copyright 2014-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/src/flexfix b/src/flexfix index ee017dc43..64f95a385 100755 --- a/src/flexfix +++ b/src/flexfix @@ -2,7 +2,7 @@ # pylint: disable=C0114,C0301 ###################################################################### # -# Copyright 2002-2023 by Wilson Snyder. This program is free software; you +# Copyright 2002-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/src/verilog.l b/src/verilog.l index 7d43128b0..8f6a09897 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -6,7 +6,7 @@ * ************************************************************************** * - * Copyright 2003-2023 by Wilson Snyder. Verilator is free software; you + * Copyright 2003-2024 by Wilson Snyder. Verilator is free software; you * can redistribute it and/or modify it under the terms of either the * GNU Lesser General Public License Version 3 or the Perl Artistic License * Version 2.0. diff --git a/src/verilog.y b/src/verilog.y index 3a274eba3..b83b953bc 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1,12 +1,12 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* -// DESCRIPTION: Verilator: Bison grammer file +// DESCRIPTION: Verilator: Bison grammar file // // Code available from: https://verilator.org // //************************************************************************* // -// Copyright 2003-2023 by Wilson Snyder. This program is free software; you +// Copyright 2003-2024 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -1054,7 +1054,7 @@ BISONPRE_VERSION(3.7,%define api.header.include {"V3ParseBison.h"}) %token yP_SSRIGHTEQ ">>>=" // [* is not an operator, as "[ * ]" is legal -// [= and [-> could be repitition operators, but to match [* we don't add them. +// [= and [-> could be repetition operators, but to match [* we don't add them. // '( is not an operator, as "' (" is legal //******************** @@ -2134,12 +2134,22 @@ data_typeNoRef: // ==IEEE: data_type, excluding class_ty data_typeVirtual: // ==IEEE: data_type after yVIRTUAL [ yINTERFACE ] // // Parameters here are SV2009 - id/*interface*/ { $$ = new AstIfaceRefDType{$1, "", *$1}; } - | id/*interface*/ '.' id/*modport*/ { $$ = new AstIfaceRefDType{$1, $3, "", *$1, *$3}; } + id/*interface*/ + { AstIfaceRefDType* const ifrefp = new AstIfaceRefDType{$1, "", *$1}; + ifrefp->isVirtual(true); + $$ = ifrefp; } + | id/*interface*/ '.' id/*modport*/ + { AstIfaceRefDType* const ifrefp = new AstIfaceRefDType{$1, $3, "", *$1, *$3}; + ifrefp->isVirtual(true); + $$ = ifrefp; } | id/*interface*/ parameter_value_assignmentClass - { $$ = new AstIfaceRefDType{$1, nullptr, "", *$1, "", $2}; } + { AstIfaceRefDType* const ifrefp = new AstIfaceRefDType{$1, nullptr, "", *$1, "", $2}; + ifrefp->isVirtual(true); + $$ = ifrefp; } | id/*interface*/ parameter_value_assignmentClass '.' id/*modport*/ - { $$ = new AstIfaceRefDType{$1, $4, "", *$1, *$4, $2}; } + { AstIfaceRefDType* const ifrefp = new AstIfaceRefDType{$1, $4, "", *$1, *$4, $2}; + ifrefp->isVirtual(true); + $$ = ifrefp; } ; data_type_or_void: // ==IEEE: data_type_or_void @@ -2189,7 +2199,7 @@ struct_union_memberList: // IEEE: { struct_union_member } ; struct_union_member: // ==IEEE: struct_union_member - // // UNSUP random_qualifer not propagagted until have randomize support + // // UNSUP random_qualifer not propagated until have randomize support random_qualifierE data_type_or_void /*mid*/ { GRAMMARP->m_memDTypep = $2; } // As a list follows, need to attach this dtype to each member. /*cont*/ list_of_member_decl_assignments ';' @@ -3348,8 +3358,7 @@ senitem: // IEEE: part of event_expression, non-'OR' ',' | expr { $$ = new AstSenItem{$1, VEdgeType::ET_CHANGED, $1}; } | expr yIFF expr - { $$ = new AstSenItem{$1, VEdgeType::ET_CHANGED, $1}; - if ($2) BBUNSUP($2, "Unsupported: event expression 'iff'"); } + { $$ = new AstSenItem{$1, VEdgeType::ET_CHANGED, $1, $3}; } ; senitemVar: @@ -3364,14 +3373,11 @@ senitemEdge: // IEEE: part of event_expression | yEDGE expr { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2}; } | yPOSEDGE expr yIFF expr - { $$ = new AstSenItem{$1, VEdgeType::ET_POSEDGE, $2}; - BBUNSUP($3, "Unsupported: event expression 'iff'"); } + { $$ = new AstSenItem{$1, VEdgeType::ET_POSEDGE, $2, $4}; } | yNEGEDGE expr yIFF expr - { $$ = new AstSenItem{$1, VEdgeType::ET_NEGEDGE, $2}; - BBUNSUP($3, "Unsupported: event expression 'iff'"); } + { $$ = new AstSenItem{$1, VEdgeType::ET_NEGEDGE, $2, $4}; } | yEDGE expr yIFF expr - { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2}; - BBUNSUP($3, "Unsupported: event expression 'iff'"); } + { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2, $4}; } ; //************************************************ @@ -4907,7 +4913,7 @@ expr: // IEEE: part of expression/constant_expression/ // // // IEEE: expression_or_dist - here to avoid reduce problems // // "expr yDIST '{' dist_list '}'" - | ~l~expr yDIST '{' dist_list '}' { $$ = $1; BBUNSUP($2, "Unsupported: dist"); } + | ~l~expr yDIST '{' dist_list '}' { $$ = $1; } ; fexpr: // For use as first part of statement (disambiguates <=) @@ -5988,7 +5994,7 @@ property_port_itemDirE: property_declarationBody: // IEEE: part of property_declaration //UNSUP assertion_variable_declarationList property_statement_spec {} - // // IEEE-2012: Incorectly hasyCOVER ySEQUENCE then property_spec here. + // // IEEE-2012: Incorrectly has yCOVER ySEQUENCE then property_spec here. // // Fixed in IEEE 1800-2017 property_spec { $$ = $1; } | property_spec ';' { $$ = $1; } @@ -6301,7 +6307,7 @@ cycle_delay_range: // IEEE: ==cycle_delay_range BBUNSUP($1, "Unsupported: ## () cycle delay range expression"); } // // In 1800-2009 ONLY: // // IEEE: yP_POUNDPOUND constant_primary - // // UNSUP: This causes a big grammer ambiguity + // // UNSUP: This causes a big grammar ambiguity // // as ()'s mismatch between primary and the following statement // // the sv-ac committee has been asked to clarify (Mantis 1901) | yP_POUNDPOUND anyrange @@ -6493,7 +6499,7 @@ trans_list: // ==IEEE: trans_list trans_set: // ==IEEE: trans_set trans_range_list { $$ = $1; } - // // Note the { => } in the grammer, this is really a list + // // Note the { => } in the grammar, this is really a list | trans_set yP_EQGT trans_range_list { $$ = $1; BBUNSUP($2, "Unsupported: cover trans set '=>'"); } ; @@ -6843,7 +6849,7 @@ checker_generate_item: // ==IEEE: checker_generate_item class_declaration: // ==IEEE: part of class_declaration // // IEEE-2012: using this also for interface_class_declaration - // // The classExtendsE rule relys on classFront having the + // // The classExtendsE rule relies on classFront having the // // new class scope correct via classFront classFront parameter_port_listE classExtendsE classImplementsE ';' /*mid*/ { // Allow resolving types declared in base extends class @@ -6881,7 +6887,7 @@ classVirtualE: ; classExtendsE: // IEEE: part of class_declaration - // // The classExtendsE rule relys on classFront having the + // // The classExtendsE rule relies on classFront having the // // new class scope correct via classFront /* empty */ { $$ = nullptr; $$ = nullptr; } | yEXTENDS classExtendsList { $$ = $2; $$ = $2; } @@ -7107,21 +7113,29 @@ memberQualOne: // IEEE: property_qualifier + me //********************************************************************** // Constraints -class_constraint: // ==IEEE: class_constraint +class_constraint: // ==IEEE: class_constraint // // IEEE: constraint_declaration // // UNSUP: We have the unsupported warning on the randomize() call, so don't bother on // // constraint blocks. When we support randomize we need to make AST nodes for below rules - constraintStaticE yCONSTRAINT idAny constraint_block - { // Variable so we can link and later ignore constraint_mode() methods - $$ = new AstVar{$3, VVarType::MEMBER, *$3, VFlagBitPacked{}, 1}; - $2->v3warn(CONSTRAINTIGN, "Constraint ignored (unsupported)"); } + constraintStaticE yCONSTRAINT constraintIdNew constraint_block + { $$ = $3; $$->isStatic($1); $$->addItemsp($4); SYMP->popScope($$); } + | constraintStaticE yCONSTRAINT constraintIdNew '{' '}' + { $$ = $3; $$->isStatic($1); SYMP->popScope($$); } // // IEEE: constraint_prototype + constraint_prototype_qualifier - | constraintStaticE yCONSTRAINT idAny ';' - { $$ = nullptr; } - | yEXTERN constraintStaticE yCONSTRAINT idAny ';' - { $$ = nullptr; BBUNSUP($1, "Unsupported: extern constraint"); } - | yPURE constraintStaticE yCONSTRAINT idAny ';' - { $$ = nullptr; BBUNSUP($1, "Unsupported: pure constraint"); } + | constraintStaticE yCONSTRAINT constraintIdNew ';' + { $$ = $3; $$->isStatic($1); SYMP->popScope($$); } + | yEXTERN constraintStaticE yCONSTRAINT constraintIdNew ';' + { $$ = $4; $$->isStatic($1); SYMP->popScope($4); + BBUNSUP($1, "Unsupported: extern constraint"); } + | yPURE constraintStaticE yCONSTRAINT constraintIdNew ';' + { $$ = $4; $$->isStatic($1); SYMP->popScope($4); + BBUNSUP($1, "Unsupported: pure constraint"); } + ; + +constraintIdNew: // IEEE: id part of class_constraint + idAny/*constraint_identifier*/ + { $$ = new AstConstraint{$1, *$1, nullptr}; + SYMP->pushNewUnderNodeOrCurrent($$, nullptr); } ; constraint_block: // ==IEEE: constraint_block @@ -7136,15 +7150,15 @@ constraint_block_itemList: // IEEE: { constraint_block_item } constraint_block_item: // ==IEEE: constraint_block_item constraint_expression { $$ = $1; } | ySOLVE solve_before_list yBEFORE solve_before_list ';' - { $$ = nullptr; BBUNSUP($2, "Unsupported: solve before"); } + { $$ = new AstConstraintBefore{$1, $2, $4}; } ; -solve_before_list: // ==IEEE: solve_before_list +solve_before_list: // ==IEEE: solve_before_list constraint_primary { $$ = $1; } | solve_before_list ',' constraint_primary { $$ = addNextNull($1, $3); } ; -constraint_primary: // ==IEEE: constraint_primary +constraint_primary: // ==IEEE: constraint_primary // // exprScope more general than: // // [ implicit_class_handle '.' | class_scope ] hierarchical_identifier select exprScope { $$ = $1; } @@ -7156,21 +7170,32 @@ constraint_expressionList: // ==IEEE: { constraint_expression } ; constraint_expression: // ==IEEE: constraint_expression - expr/*expression_or_dist*/ ';' { $$ = $1; } + expr/*expression_or_dist*/ ';' + { $$ = new AstConstraintExpr{$1->fileline(), $1}; } // // 1800-2012: - | ySOFT expr/*expression_or_dist*/ ';' { $$ = nullptr; /*UNSUP-no-UVM*/ } + | ySOFT expr/*expression_or_dist*/ ';' + { AstConstraintExpr* const newp = new AstConstraintExpr{$1, $2}; + newp->isSoft(true); + $$ = newp; } // // 1800-2012: // // IEEE: uniqueness_constraint ';' - | yUNIQUE '{' range_list '}' { $$ = nullptr; /*UNSUP-no-UVM*/ } + | yUNIQUE '{' range_list '}' + { $$ = new AstConstraintUnique{$1, $3}; } // // IEEE: expr yP_MINUSGT constraint_set // // Conflicts with expr:"expr yP_MINUSGT expr"; rule moved there // - | yIF '(' expr ')' constraint_set %prec prLOWER_THAN_ELSE { $$ = nullptr; /*UNSUP-UVM*/ } - | yIF '(' expr ')' constraint_set yELSE constraint_set { $$ = nullptr; /*UNSUP-UVM*/ } + | yIF '(' expr ')' constraint_set %prec prLOWER_THAN_ELSE + { $$ = new AstConstraintIf{$1, $3, $5, nullptr}; } + | yIF '(' expr ')' constraint_set yELSE constraint_set + { $$ = new AstConstraintIf{$1, $3, $5, $7}; } // // IEEE says array_identifier here, but dotted accepted in VMM + 1800-2009 - | yFOREACH '(' idClassSelForeach ')' constraint_set { $$ = nullptr; /*UNSUP-UVM*/ } + | yFOREACH '(' idClassSelForeach ')' constraint_set + { $$ = new AstConstraintForeach{$1, $3, $5}; } // // soft is 1800-2012 - | yDISABLE ySOFT expr/*constraint_primary*/ ';' { $$ = nullptr; /*UNSUP-no-UVM*/ } + | yDISABLE ySOFT expr/*constraint_primary*/ ';' + { AstConstraintExpr* const newp = new AstConstraintExpr{$1, $3}; + newp->isDisableSoft(true); + $$ = newp; } ; constraint_set: // ==IEEE: constraint_set @@ -7183,14 +7208,17 @@ dist_list: // ==IEEE: dist_list | dist_list ',' dist_item { $$ = addNextNull($1, $3); } ; -dist_item: // ==IEEE: dist_item + dist_weight - value_range { $$ = $1; /* Same as := 1 */ } - | value_range yP_COLONEQ expr { $$ = $1; /*UNSUP-no-UVM*/ } - | value_range yP_COLONDIV expr { $$ = $1; /*UNSUP-no-UVM*/ } +dist_item: // ==IEEE: dist_item + dist_weight + value_range + { $$ = new AstDistItem{$1->fileline(), $1, new AstConst{$1->fileline(), 1}}; } + | value_range yP_COLONEQ expr + { $$ = new AstDistItem{$2, $1, $3}; } + | value_range yP_COLONDIV expr + { $$ = new AstDistItem{$2, $1, $3}; $$->isWhole(true); } ; extern_constraint_declaration: // ==IEEE: extern_constraint_declaration - constraintStaticE yCONSTRAINT packageClassScopeE idAny + constraintStaticE yCONSTRAINT packageClassScopeE idAny constraint_block { $$ = nullptr; BBUNSUP($2, "Unsupported: extern constraint"); } ; diff --git a/src/vlcovgen b/src/vlcovgen index 9465d6929..960b9c691 100755 --- a/src/vlcovgen +++ b/src/vlcovgen @@ -83,7 +83,7 @@ parser = argparse.ArgumentParser( description= """Generate verilated_cov headers to reduce C++ code duplication.""", epilog= - """Copyright 2002-2023 by Wilson Snyder. This program is free software; you + """Copyright 2002-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/test_regress/CMakeLists.txt b/test_regress/CMakeLists.txt index 91e5eab28..ad09a1282 100644 --- a/test_regress/CMakeLists.txt +++ b/test_regress/CMakeLists.txt @@ -4,7 +4,7 @@ # # This CMake file is meant to be consumed by regression tests. # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/test_regress/Makefile b/test_regress/Makefile index 57b804818..420fbbc4d 100644 --- a/test_regress/Makefile +++ b/test_regress/Makefile @@ -5,7 +5,7 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/test_regress/Makefile_obj b/test_regress/Makefile_obj index 297f3d560..5e1fa1424 100644 --- a/test_regress/Makefile_obj +++ b/test_regress/Makefile_obj @@ -5,7 +5,7 @@ # # This is executed in the object directory, and called by ../Makefile # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 3e53a89d3..07db695c2 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -333,22 +333,23 @@ use strict; sub new { my $class = shift; my $self = { - # Parameters + # Arguments driver_log_filename => undef, quiet => 0, # Counts all_cnt => 0, left_cnt => 0, - ok_cnt => 0, - fail1_cnt => 0, + ok_cnt => 0, # Argument passed when rerunning + fail1_cnt => 0, # Argument passed when rerunning fail_cnt => 0, - skip_cnt => 0, + skip_cnt => 0, # Argument passed when rerunning skip_msgs => [], fail_msgs => [], fail_tests => [], # Per-task identifiers running_ids => {}, - @_}; + @_ # All legal arguments shown immediately above + }; bless $self, $class; return $self; } @@ -357,7 +358,11 @@ sub fail_count { return $_[0]->{fail_cnt}; } sub one_test { my $self = shift; - my @params = @_; + my @params = (# Parameters: + # pl_filename => + # rerun_skipping => + # {scenario_name} => 1 + @_); # All legal arguments shown immediately above my %params = (@params); $self->{all_cnt}++; $self->{left_cnt}++; @@ -484,7 +489,7 @@ sub print_summary { my $self = shift; my %params = (force => 0, # Force printing show_running => 0, # Show running processes - @_); + @_); # All legal arguments shown immediately above if (!$self->{quiet} || $params{force} || ($self->{left_cnt} < 5) || (time() - ($self->{_last_summary_time} || 0) >= 15)) { # Don't show for interactive gdb etc @@ -564,7 +569,7 @@ sub defineOpt { sub new { my $class = shift; - my $self = {@_}; + my $self = {@_}; # Supports arbitrary arguments $self->{name} ||= $2 if $self->{pl_filename} =~ m!^(.*/)?([^/]*)\.pl$!; @@ -787,8 +792,7 @@ sub skip { sub scenarios { my $self = (ref $_[0] ? shift : $Self); - my %params = (@_); - # Called from tests as: scenarios(...); + my %params = (@_); # Called from tests as: scenarios(...); # to specify which scenarios this test runs under. # Where ... is one cases listed in All_Scenarios if ((scalar keys %params) < 1) { @@ -903,7 +907,8 @@ sub clean_objs { sub compile_vlt_cmd { my $self = (ref $_[0] ? shift : $Self); - my %param = (%{$self}, @_); # Default arguments are from $self + my %param = (%{$self}, # Default arguments are from $self + @_); # Supports arbitrary arguments return 1 if $self->errors || $self->skips; my @vlt_cmd = ( @@ -918,7 +923,8 @@ sub compile_vlt_cmd { sub compile_vlt_flags { my $self = (ref $_[0] ? shift : $Self); - my %param = (%{$self}, @_); # Default arguments are from $self + my %param = (%{$self}, # Default arguments are from $self + @_); # Supports arbitrary arguments return 1 if $self->errors || $self->skips; my $checkflags = (' '.join(' ', @@ -951,7 +957,7 @@ sub compile_vlt_flags { unshift @verilator_flags, "--threads $param{threads}" if $param{threads} >= 0; unshift @verilator_flags, "--trace-threads 2" if $param{vltmt} && $checkflags =~ /-trace-fst /; unshift @verilator_flags, "--debug-partition" if $param{vltmt}; - unshift @verilator_flags, "-CFLAGS -ggdb -LDFLAGS -ggdb" if $opt_gdbsim; + unshift @verilator_flags, "-CFLAGS -ggdb -LDFLAGS -ggdb" if $opt_gdbsim || $opt_rrsim; unshift @verilator_flags, "-CFLAGS -fsanitize=address,undefined -LDFLAGS -fsanitize=address,undefined" if $param{sanitize}; unshift @verilator_flags, "--make gmake" if $param{verilator_make_gmake}; unshift @verilator_flags, "--make cmake" if $param{verilator_make_cmake}; @@ -988,14 +994,15 @@ sub lint { make_top_shell => 0, verilator_flags2 => ["--lint-only"], verilator_make_gmake => 0, - @_); + @_); # Supports arbitrary arguments $self->compile(%param); } sub compile { my $self = (ref $_[0] ? shift : $Self); my %param = (tee => 1, - %{$self}, @_); # Default arguments are from $self + %{$self}, # Default arguments are from $self + @_); # Supports arbitrary arguments return 1 if $self->errors || $self->skips; $self->oprint("Compile\n") if $self->{verbose}; @@ -1254,7 +1261,8 @@ sub compile { sub execute { my $self = (ref $_[0] ? shift : $Self); return 1 if $self->errors || $self->skips; - my %param = (%{$self}, @_); # Default arguments are from $self + my %param = (%{$self}, # Default arguments are from $self + @_); # Supports arbitrary arguments # params may be expect or {tool}_expect $self->oprint("Run\n") if $self->{verbose}; @@ -1403,8 +1411,6 @@ sub inline_checks { return 1 if $self->errors || $self->skips; return 1 if !$self->{vlt_all}; - my %param = (%{$self}, @_); # Default arguments are from $self - my $covfn = $Self->{coverage_filename}; my $contents = $self->file_contents($covfn); @@ -1592,15 +1598,21 @@ sub vm_prefix { sub run { my $self = (ref $_[0] ? shift : $Self); - $self->_run(@_); + $self->_run(@_); # See _run() for arguments } sub _run { my $self = (ref $_[0] ? shift : $Self); my %param = (tee => 1, - #entering => # Print entering directory information - #verilator_run => # Move gcov data to parallel area - @_); + # cmd => [...] + # check_finished => 0 # Check for All Finished + # entering => # Print entering directory information + # expect => # Regexp to expect in output + # expect_filename => # Filename that should match logfile + # fails => 0 # Command should fail + # logfile => # Filename to write putput to + # verilator_run => # Move gcov data to parallel area + @_); # All legal arguments shown immediately above my $command = join(' ', @{$param{cmd}}); $command = "time $command" if $opt_benchmark && $command !~ /^cd /; @@ -1760,7 +1772,8 @@ sub _try_regex { # 1 if $text ~= /$regex/ms # 0 if no match # -1 if $regex is invalid, doesn't compile - my ($text, $regex) = @_; + my $text = shift; + my $regex = shift; my $result; { local $@; @@ -2492,6 +2505,20 @@ sub file_grep { } } +sub file_grep_count { + my $self = (ref $_[0] ? shift : $Self); + my $filename = shift; + my $regexp = shift; + my $expcount = shift; + return if $self->errors || $self->skips; + + my $contents = $self->file_contents($filename); + my $count = () = $contents =~ /$regexp/g; + if ($count != $expcount) { + $self->error("file_grep_count: $filename: Got='$count' Expected='$expcount' for regexp: $regexp\n"); + } +} + sub file_grep_any { my $self = $Self; my @filenames = @{$_[0]}; shift; @@ -2564,12 +2591,12 @@ sub file_sed { sub extract { my $self = (ref $_[0] ? shift : $Self); - my %param = ( #in =>, - #out => - regexp => qr/.*/, - lineno_adjust => -9999, - lines => undef, #'#, #-#', - @_); + my %param = (#in =>, + #out => + regexp => qr/.*/, + lineno_adjust => -9999, + lines => undef, #'#, #-#', + @_); # All legal arguments shown immediately above my $temp_fn = $param{out}; $temp_fn =~ s!.*/!!g; @@ -2700,7 +2727,7 @@ See docs/internals.rst in the distribution for more information. The latest version is available from L. -Copyright 2003-2023 by Wilson Snyder. This program is free software; you +Copyright 2003-2024 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. diff --git a/test_regress/t/TestCheck.h b/test_regress/t/TestCheck.h index 17a25accb..0551634ac 100644 --- a/test_regress/t/TestCheck.h +++ b/test_regress/t/TestCheck.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2013-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2013-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -12,6 +12,8 @@ #ifndef TEST_CHECK_H_ #define TEST_CHECK_H_ +#include + extern int errors; #ifdef TEST_VERBOSE diff --git a/test_regress/t/TestSimulator.h b/test_regress/t/TestSimulator.h index b7c1acb14..9576bfe01 100644 --- a/test_regress/t/TestSimulator.h +++ b/test_regress/t/TestSimulator.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2013-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2013-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/test_regress/t/TestVpi.h b/test_regress/t/TestVpi.h index 01db39ced..d5b746b1b 100644 --- a/test_regress/t/TestVpi.h +++ b/test_regress/t/TestVpi.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2013-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2013-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. @@ -32,6 +32,7 @@ public: TestVpiHandle& operator=(vpiHandle h) { release(); m_handle = h; + m_freeit = true; return *this; } void release() { diff --git a/test_regress/t/bootstrap.pl b/test_regress/t/bootstrap.pl index dd290d26e..564203d1e 100755 --- a/test_regress/t/bootstrap.pl +++ b/test_regress/t/bootstrap.pl @@ -1,7 +1,7 @@ #!/usr/bin/env perl # DESCRIPTION: Verilator: Verilog Test driver bootstrapper # -# Copyright 2008-2023 by Wilson Snyder. This program is free software; you +# Copyright 2008-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/test_regress/t/t_EXAMPLE.pl b/test_regress/t/t_EXAMPLE.pl index 859050d63..e64ab41be 100755 --- a/test_regress/t/t_EXAMPLE.pl +++ b/test_regress/t/t_EXAMPLE.pl @@ -2,7 +2,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2023 by Wilson Snyder. This program is free software; you +# Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v index ad11f43cd..9693c0bee 100644 --- a/test_regress/t/t_EXAMPLE.v +++ b/test_regress/t/t_EXAMPLE.v @@ -13,7 +13,7 @@ // please note it here, otherwise:** // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2023 by Wilson Snyder. +// any use, without warranty, 2024 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ diff --git a/test_regress/t/t_assert_iff.pl b/test_regress/t/t_assert_iff.pl new file mode 100755 index 000000000..63d2a42a6 --- /dev/null +++ b/test_regress/t/t_assert_iff.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['--assert --cc --coverage-user'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_assert_iff.v b/test_regress/t/t_assert_iff.v new file mode 100644 index 000000000..380f8831d --- /dev/null +++ b/test_regress/t/t_assert_iff.v @@ -0,0 +1,57 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + logic[3:0] enable; + int cyc = 0; + + Test test(.*); + + always @ (posedge clk) begin + cyc <= cyc + 1; + `ifdef FAIL1 enable[0] <= 1; `endif + enable[1] <= 1; + `ifdef FAIL2 enable[2] <= 1; `endif + enable[3] <= 1; + if (cyc != 0) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end +endmodule + +module Test( + input clk, + input[3:0] enable + ); + + assert property ( + @(posedge clk iff enable[0]) + 0 + ) else $stop; + + assert property ( + @(posedge clk iff enable[1]) + 1 + ); + + cover property ( + @(posedge clk iff enable[2]) + 1 + ) $stop; + + cover property ( + @(posedge clk iff enable[3]) + 0 + ) $stop; + +endmodule diff --git a/test_regress/t/t_assert_iff_bad1.pl b/test_regress/t/t_assert_iff_bad1.pl new file mode 100755 index 000000000..3959b8306 --- /dev/null +++ b/test_regress/t/t_assert_iff_bad1.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename('t_assert_iff.v'); + +compile( + verilator_flags2 => ['--assert --cc --coverage-user -DFAIL1'], + ); + +execute( + fails => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_assert_iff_bad2.pl b/test_regress/t/t_assert_iff_bad2.pl new file mode 100755 index 000000000..f71edd058 --- /dev/null +++ b/test_regress/t/t_assert_iff_bad2.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename('t_assert_iff.v'); + +compile( + verilator_flags2 => ['--assert --cc --coverage-user -DFAIL2'], + ); + +execute( + fails => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_assert_procedural_clk.out b/test_regress/t/t_assert_procedural_clk.out deleted file mode 100644 index 365914727..000000000 --- a/test_regress/t/t_assert_procedural_clk.out +++ /dev/null @@ -1,9 +0,0 @@ -%Error: t/t_assert_procedural_clk.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2017 16.14.6) - : ... note: In instance 't' - 21 | assume property (@(posedge clk) cyc == 9); - | ^~~~~~ -%Error: t/t_assert_procedural_clk.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2017 16.14.6) - : ... note: In instance 't' - 22 | assume property (@(negedge clk) cyc == 9); - | ^~~~~~ -%Error: Exiting due to diff --git a/test_regress/t/t_assert_procedural_clk_bad.out b/test_regress/t/t_assert_procedural_clk_bad.out new file mode 100644 index 000000000..e1e26adee --- /dev/null +++ b/test_regress/t/t_assert_procedural_clk_bad.out @@ -0,0 +1,9 @@ +%Error: t/t_assert_procedural_clk_bad.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2017 16.14.6) + : ... note: In instance 't' + 21 | assume property (@(posedge clk) cyc == 9); + | ^~~~~~ +%Error: t/t_assert_procedural_clk_bad.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2017 16.14.6) + : ... note: In instance 't' + 22 | assume property (@(negedge clk) cyc == 9); + | ^~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_assert_procedural_clk.pl b/test_regress/t/t_assert_procedural_clk_bad.pl similarity index 100% rename from test_regress/t/t_assert_procedural_clk.pl rename to test_regress/t/t_assert_procedural_clk_bad.pl diff --git a/test_regress/t/t_assert_procedural_clk.v b/test_regress/t/t_assert_procedural_clk_bad.v similarity index 100% rename from test_regress/t/t_assert_procedural_clk.v rename to test_regress/t/t_assert_procedural_clk_bad.v diff --git a/test_regress/t/t_assert_property_pexpr_unsup.pl b/test_regress/t/t_assert_property_pexpr_unsup.pl index c9ca914d8..fa4fb8b52 100755 --- a/test_regress/t/t_assert_property_pexpr_unsup.pl +++ b/test_regress/t/t_assert_property_pexpr_unsup.pl @@ -13,7 +13,7 @@ scenarios(vlt => 1); compile( expect_filename => $Self->{golden_filename}, verilator_flags2 => ['--assert --error-limit 1000'], - fails => 1, + fails => $Self->{vlt_all}, ); ok(1); diff --git a/test_regress/t/t_assigndly_dynamic.v b/test_regress/t/t_assigndly_dynamic.v index 9183eb767..7a403fa9b 100644 --- a/test_regress/t/t_assigndly_dynamic.v +++ b/test_regress/t/t_assigndly_dynamic.v @@ -25,8 +25,26 @@ class nba_waiter; endtask endclass +class Foo; + task bar(logic a, logic b); + int x; + int y; + // bar's local vars and intravals could be overwritten by other locals + if (a) x <= `DELAY 'hDEAD; + if (b) y <= `DELAY 'hBEEF; + #2 + if (x != 'hDEAD) $stop; + endtask + + task qux(); + int x[] = new[1]; + x[0] <= `DELAY 'hBEEF; // Segfault check + endtask +endclass + module t; nba_waiter waiter = new; + Foo foo = new; event e; int cnt = 0; @@ -42,6 +60,9 @@ module t; waiter.wait_for_nba_region; if (cnt != 4) $stop; if ($time != `TIME_AFTER_SECOND_WAIT) $stop; + foo.bar(1, 1); + foo.qux(); + #2 $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_assigndly_dynamic_nofork.pl b/test_regress/t/t_assigndly_dynamic_nofork.pl new file mode 100755 index 000000000..b4872e54c --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic_nofork.pl @@ -0,0 +1,27 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_assigndly_task.v"); + +compile( + verilator_flags2 => ["--timing"], + ); + +foreach my $file ( + glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.h"), + glob_all("$Self->{obj_dir}/$Self->{vm_prefix}*.cpp") + ) { + file_grep_not($file, qr/__Vfork_/i); +} + +ok(1); +1; diff --git a/test_regress/t/t_assigndly_dynamic_notiming.out b/test_regress/t/t_assigndly_dynamic_notiming.out deleted file mode 100644 index 7fe77946a..000000000 --- a/test_regress/t/t_assigndly_dynamic_notiming.out +++ /dev/null @@ -1,6 +0,0 @@ -%Error-NOTIMING: t/t_assigndly_dynamic_notiming.v:10:13: Delayed assignment in a non-inlined function/task requires --timing - : ... note: In instance '$unit::foo' - 10 | qux <= '1; - | ^~ - ... For error description see https://verilator.org/warn/NOTIMING?v=latest -%Error: Exiting due to diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.out b/test_regress/t/t_assigndly_dynamic_notiming_bad.out new file mode 100644 index 000000000..687d05541 --- /dev/null +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.out @@ -0,0 +1,6 @@ +%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:11: Delayed assignment in a non-inlined function/task requires --timing + : ... note: In instance '$unit::Cls' + 10 | qux <= '1; + | ^~ + ... For error description see https://verilator.org/warn/NOTIMING?v=latest +%Error: Exiting due to diff --git a/test_regress/t/t_assigndly_dynamic_notiming.pl b/test_regress/t/t_assigndly_dynamic_notiming_bad.pl similarity index 100% rename from test_regress/t/t_assigndly_dynamic_notiming.pl rename to test_regress/t/t_assigndly_dynamic_notiming_bad.pl diff --git a/test_regress/t/t_assigndly_dynamic_notiming.v b/test_regress/t/t_assigndly_dynamic_notiming_bad.v similarity index 51% rename from test_regress/t/t_assigndly_dynamic_notiming.v rename to test_regress/t/t_assigndly_dynamic_notiming_bad.v index f4b96c4de..b2f77420a 100644 --- a/test_regress/t/t_assigndly_dynamic_notiming.v +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.v @@ -4,9 +4,18 @@ // without warranty, 2023 by Antmicro Ltd. // SPDX-License-Identifier: CC0-1.0 -class foo; - task bar; - int qux; - qux <= '1; - endtask +class Cls; + task bar; + int qux; + qux <= '1; + endtask endclass + +module t; + initial begin + Cls c; + c.bar(); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_assigndly_task.pl b/test_regress/t/t_assigndly_task.pl new file mode 100755 index 000000000..da2e37bda --- /dev/null +++ b/test_regress/t/t_assigndly_task.pl @@ -0,0 +1,17 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +ok(1); +1; diff --git a/test_regress/t/t_assigndly_task.v b/test_regress/t/t_assigndly_task.v new file mode 100644 index 000000000..3d51a7ad6 --- /dev/null +++ b/test_regress/t/t_assigndly_task.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +module t ( + input clk, + input [7:0] d, + input [2:0] a, + output [7:0] q +); + always_ff @(posedge clk) tick(a); + + logic [7:0] d_ = d; + logic [7:0] q_; + assign q = q_; + + task automatic tick(logic [2:0] a); + q_[a] <= d_[a]; + endtask +endmodule diff --git a/test_regress/t/t_checker.pl b/test_regress/t/t_checker.pl index 1ce0595d2..657040447 100755 --- a/test_regress/t/t_checker.pl +++ b/test_regress/t/t_checker.pl @@ -13,7 +13,7 @@ scenarios(vlt => 1); compile( verilator_flags2 => ['--assert'], expect_filename => $Self->{golden_filename}, - fails => 1, + fails => $Self->{vlt_all}, ); #execute( diff --git a/test_regress/t/t_class_param_typedef2.pl b/test_regress/t/t_class_param_typedef2.pl new file mode 100755 index 000000000..1aa73f80a --- /dev/null +++ b/test_regress/t/t_class_param_typedef2.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_class_param_typedef2.v b/test_regress/t/t_class_param_typedef2.v new file mode 100644 index 000000000..ea2e74a1a --- /dev/null +++ b/test_regress/t/t_class_param_typedef2.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +virtual class Virt; +endclass + +class MyInt; + int x; +endclass + +class uvm_object_registry #( + type T = Virt +); + static function T create_object(); + T obj = new(); + obj.x = 1; + return obj; + endfunction +endclass + +typedef uvm_object_registry#(MyInt) type_id; + +module t; + initial begin + MyInt mi = type_id::create_object(); + if (mi.x != 1) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_class_param_virtual_bad.out b/test_regress/t/t_class_param_virtual_bad.out new file mode 100644 index 000000000..6d05be5df --- /dev/null +++ b/test_regress/t/t_class_param_virtual_bad.out @@ -0,0 +1,9 @@ +%Error: t/t_class_param_virtual_bad.v:13:11: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2017 8.21) + : ... note: In instance 't' + 13 | t = new; + | ^~~ +%Error: t/t_class_param_virtual_bad.v:23:28: Illegal to call 'new' using an abstract virtual class 'ClsVirt' (IEEE 1800-2017 8.21) + : ... note: In instance 't' + 23 | ClsVirt#(VBase) cv = new; + | ^~~ +%Error: Exiting due to diff --git a/test_regress/t/t_class_param_virtual_bad.pl b/test_regress/t/t_class_param_virtual_bad.pl new file mode 100755 index 000000000..009248fc5 --- /dev/null +++ b/test_regress/t/t_class_param_virtual_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_class_param_virtual_bad.v b/test_regress/t/t_class_param_virtual_bad.v new file mode 100644 index 000000000..e9f3c9c85 --- /dev/null +++ b/test_regress/t/t_class_param_virtual_bad.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +virtual class VBase; +endclass + +class Cls#(parameter type T = VBase); + T t; + function new; + t = new; + endfunction +endclass + +virtual class ClsVirt#(parameter type T); +endclass + +module t; + initial begin + Cls c = new; // Error + ClsVirt#(VBase) cv = new; // Error + $stop; + end +endmodule diff --git a/test_regress/t/t_class_virtual_bad.out b/test_regress/t/t_class_virtual_bad.out index 946c04299..3a0cb92f1 100644 --- a/test_regress/t/t_class_virtual_bad.out +++ b/test_regress/t/t_class_virtual_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_class_virtual_bad.v:12:17: Illegal to call 'new' using an abstract virtual class (IEEE 1800-2017 8.21) +%Error: t/t_class_virtual_bad.v:12:17: Illegal to call 'new' using an abstract virtual class 'VBase' (IEEE 1800-2017 8.21) : ... note: In instance 't' 12 | VBase b = new; | ^~~ diff --git a/test_regress/t/t_clk_inp_init.cpp b/test_regress/t/t_clk_inp_init.cpp index 6afcc98ce..f6f91d8d6 100644 --- a/test_regress/t/t_clk_inp_init.cpp +++ b/test_regress/t/t_clk_inp_init.cpp @@ -2,11 +2,7 @@ // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -// Test defines -// Generated header -#include "Vt_clk_inp_init.h" -// General headers -#include "verilated.h" +#include VM_PREFIX_INCLUDE void oneTest(int argc, char** argv, int seed) { uint64_t sim_time = 1000; diff --git a/test_regress/t/t_const_bitoptree_bug3096.cpp b/test_regress/t/t_const_bitoptree_bug3096.cpp index 8c3dc8625..e8fec7a42 100644 --- a/test_regress/t/t_const_bitoptree_bug3096.cpp +++ b/test_regress/t/t_const_bitoptree_bug3096.cpp @@ -9,7 +9,7 @@ // //************************************************************************* -#include +#include VM_PREFIX_INCLUDE #include #include diff --git a/test_regress/t/t_constraint_method_bad.out b/test_regress/t/t_constraint_method_bad.out new file mode 100644 index 000000000..9c27c3b0a --- /dev/null +++ b/test_regress/t/t_constraint_method_bad.out @@ -0,0 +1,5 @@ +%Error: t/t_constraint_method_bad.v:13:12: No such constraint method 'bad_method' + : ... note: In instance 't' + 13 | cons.bad_method(1); + | ^~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_constraint_method_bad.pl b/test_regress/t/t_constraint_method_bad.pl new file mode 100755 index 000000000..66fa61649 --- /dev/null +++ b/test_regress/t/t_constraint_method_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_constraint_method_bad.v b/test_regress/t/t_constraint_method_bad.v new file mode 100644 index 000000000..05f833a5e --- /dev/null +++ b/test_regress/t/t_constraint_method_bad.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Packet; + rand int m_one; + + constraint cons { m_one > 0 && m_one < 2; } + + task test1; + cons.bad_method(1); // BAD + endtask + +endclass + +module t (/*AUTOARG*/); +endmodule diff --git a/test_regress/t/t_constraint_mode.v b/test_regress/t/t_constraint_mode.v index 6d18156bc..cdf87c283 100644 --- a/test_regress/t/t_constraint_mode.v +++ b/test_regress/t/t_constraint_mode.v @@ -5,20 +5,17 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int one; + rand int m_one; - constraint a { one > 0 && one < 2; } + constraint cons { m_one > 0 && m_one < 2; } + + Packet other; task test1; - // TODO Verilator ignores this setting currently, always returning 1 (rand on) - one.rand_mode(0); - one.rand_mode(1); - if (one.rand_mode() != 1) $stop; - // TODO Verilator ignores this setting currently, always returning 0 (constraint off) - a.constraint_mode(1); - a.constraint_mode(0); - if (a.constraint_mode() != 0) $stop; + cons.constraint_mode(1); + cons.constraint_mode(0); + if (cons.constraint_mode() != 0) $stop; endtask endclass @@ -34,24 +31,34 @@ module t (/*AUTOARG*/); v = p.randomize(); if (v != 1) $stop; `ifndef VERILATOR - if (p.one != 1) $stop; + if (p.m_one != 1) $stop; `endif + // IEEE: function void object[.constraint_identifier].constraint_mode(bit on_off); + // IEEE: function int object.constraint_identifier.constraint_mode(); + // TODO Verilator ignores this setting currently, always returning 1 (rand on) - p.one.rand_mode(0); - p.one.rand_mode(1); - if (p.one.rand_mode() != 1) $stop; + // TODO test that these control constraints as specified + p.constraint_mode(0); + p.constraint_mode(1); + // Not legal to get current constraint_mode() value on a class-only call // TODO Verilator ignores this setting currently, always returning 0 (constraint off) - p.a.constraint_mode(1); - p.a.constraint_mode(0); - if (p.a.constraint_mode() != 0) $stop; + // TODO test that these control constraints as specified + p.cons.constraint_mode(1); + p.cons.constraint_mode(0); + if (p.cons.constraint_mode() != 0) $stop; + + // TODO Verilator ignores this setting currently, always returning 0 (constraint off) + // TODO test that these control constraints as specified + p.other = new; + p.other.cons.constraint_mode(1); + p.other.cons.constraint_mode(0); + if (p.other.cons.constraint_mode() != 0) $stop; p.test1(); - // TODO test can't redefine constraint_mode - // TODO test can't redefine rand_mode - // TODO test can't call constraint_mode on non-constraint + // TODO for example way to test this, see t_randomize_rand_mode.v $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_constraint_mode_warn_bad.out b/test_regress/t/t_constraint_mode_warn_bad.out index 7bcae1c14..261aaab42 100644 --- a/test_regress/t/t_constraint_mode_warn_bad.out +++ b/test_regress/t/t_constraint_mode_warn_bad.out @@ -1,54 +1,51 @@ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:10:4: Constraint ignored (unsupported) - 10 | constraint a { one > 0 && one < 2; } - | ^~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:16:12: constraint_mode ignored (unsupported) + : ... note: In instance 't' + 16 | cons.constraint_mode(1); + | ^~~~~~~~~~~~~~~ ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:14:11: rand_mode ignored (unsupported) +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:17:12: constraint_mode ignored (unsupported) : ... note: In instance 't' - 14 | one.rand_mode(0); - | ^~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:15:11: rand_mode ignored (unsupported) + 17 | cons.constraint_mode(0); + | ^~~~~~~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:18:16: constraint_mode ignored (unsupported) : ... note: In instance 't' - 15 | one.rand_mode(1); - | ^~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:16:15: rand_mode ignored (unsupported) - : ... note: In instance 't' - 16 | if (one.rand_mode() != 1) $stop; - | ^~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:19:9: constraint_mode ignored (unsupported) + 18 | if (cons.constraint_mode() != 0) $stop; + | ^~~~~~~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:42:9: Unsupported: 'constraint_mode' called on object : ... note: In instance 't' - 19 | a.constraint_mode(1); + 42 | p.constraint_mode(0); | ^~~~~~~~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:20:9: constraint_mode ignored (unsupported) +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:43:9: Unsupported: 'constraint_mode' called on object : ... note: In instance 't' - 20 | a.constraint_mode(0); + 43 | p.constraint_mode(1); | ^~~~~~~~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:21:13: constraint_mode ignored (unsupported) +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:48:14: constraint_mode ignored (unsupported) : ... note: In instance 't' - 21 | if (a.constraint_mode() != 0) $stop; - | ^~~~~~~~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:41:13: rand_mode ignored (unsupported) + 48 | p.cons.constraint_mode(1); + | ^~~~~~~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:49:14: constraint_mode ignored (unsupported) : ... note: In instance 't' - 41 | p.one.rand_mode(0); - | ^~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:42:13: rand_mode ignored (unsupported) + 49 | p.cons.constraint_mode(0); + | ^~~~~~~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:50:18: constraint_mode ignored (unsupported) : ... note: In instance 't' - 42 | p.one.rand_mode(1); - | ^~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:43:17: rand_mode ignored (unsupported) + 50 | if (p.cons.constraint_mode() != 0) $stop; + | ^~~~~~~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:55:20: constraint_mode ignored (unsupported) : ... note: In instance 't' - 43 | if (p.one.rand_mode() != 1) $stop; - | ^~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:46:11: constraint_mode ignored (unsupported) + 55 | p.other.cons.constraint_mode(1); + | ^~~~~~~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:56:20: constraint_mode ignored (unsupported) : ... note: In instance 't' - 46 | p.a.constraint_mode(1); - | ^~~~~~~~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:47:11: constraint_mode ignored (unsupported) + 56 | p.other.cons.constraint_mode(0); + | ^~~~~~~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:57:24: constraint_mode ignored (unsupported) : ... note: In instance 't' - 47 | p.a.constraint_mode(0); - | ^~~~~~~~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:48:15: constraint_mode ignored (unsupported) + 57 | if (p.other.cons.constraint_mode() != 0) $stop; + | ^~~~~~~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_constraint_mode.v:10:15: Constraint ignored (unsupported) : ... note: In instance 't' - 48 | if (p.a.constraint_mode() != 0) $stop; - | ^~~~~~~~~~~~~~~ + 10 | constraint cons { m_one > 0 && m_one < 2; } + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_constraint_xml.out b/test_regress/t/t_constraint_xml.out new file mode 100644 index 000000000..fd9e5c556 --- /dev/null +++ b/test_regress/t/t_constraint_xml.out @@ -0,0 +1,202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/test_regress/t/t_constraint_xml.pl b/test_regress/t/t_constraint_xml.pl new file mode 100755 index 000000000..4cb7c4c79 --- /dev/null +++ b/test_regress/t/t_constraint_xml.pl @@ -0,0 +1,25 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; + +compile( + verilator_flags2 => ['--no-std', '--xml-only', '-Wno-CONSTRAINTIGN'], + verilator_make_gmake => 0, + make_top_shell => 0, + make_main => 0, + ); + +files_identical($out_filename, $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_constraint_xml.v b/test_regress/t/t_constraint_xml.v new file mode 100644 index 000000000..6386361d2 --- /dev/null +++ b/test_regress/t/t_constraint_xml.v @@ -0,0 +1,62 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Packet; + rand int header; // 0..7 + rand int length; // 0..15 + rand int sublength; // 0..15 + rand bit if_4; + rand bit iff_5_6; + + rand int array[2]; // 2,4,6 + + constraint empty {} + + constraint size { + header > 0 && header <= 7; + length <= 15; + length >= header; + length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; + } + + constraint ifs { + if (header > 4) { + if_4 == '1; + } + if (header == 5 || header == 6) { + iff_5_6 == '1; + } else { + iff_5_6 == '0; + } + } + + constraint arr_uniq { + foreach (array[i]) { + array[i] inside {2, 4, 6}; + } + unique { array[0], array[1] } + } + + constraint order { solve length before header; } + + constraint dis { + soft sublength; + disable soft sublength; + sublength <= length; + } + +endclass + +module t (/*AUTOARG*/); + + Packet p; + + initial begin + // Not testing use of constraints + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_delay_var.out b/test_regress/t/t_delay_var.out deleted file mode 100644 index 1ee2ef517..000000000 --- a/test_regress/t/t_delay_var.out +++ /dev/null @@ -1,6 +0,0 @@ -%Warning-ZERODLY: t/t_delay_var.v:20:7: Unsupported: #0 delays do not schedule process resumption in the Inactive region - 20 | #0 in = 1'b1; - | ^ - ... For warning description see https://verilator.org/warn/ZERODLY?v=latest - ... Use "/* verilator lint_off ZERODLY */" and lint_on around source to disable this message. -%Error: Exiting due to diff --git a/test_regress/t/t_delay_var.pl b/test_regress/t/t_delay_var.pl index 68a8b13cd..0b10f155d 100755 --- a/test_regress/t/t_delay_var.pl +++ b/test_regress/t/t_delay_var.pl @@ -13,8 +13,6 @@ scenarios(vlt => 1); compile( verilator_flags2 => ["--exe --main --timing"], make_main => 0, - fails => $Self->{vlt}, - expect_filename => $Self->{golden_filename}, ); execute( diff --git a/test_regress/t/t_delay_var.v b/test_regress/t/t_delay_var.v index b303a45f0..6c0137758 100644 --- a/test_regress/t/t_delay_var.v +++ b/test_regress/t/t_delay_var.v @@ -17,7 +17,6 @@ module t; wire #PDLY d_param = in; initial begin - #0 in = 1'b1; #2 in = 1'b0; #100; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_disable_iff_multi_bad.out b/test_regress/t/t_disable_iff_multi_bad.out new file mode 100644 index 000000000..24b6b78a6 --- /dev/null +++ b/test_regress/t/t_disable_iff_multi_bad.out @@ -0,0 +1,8 @@ +%Error-UNSUPPORTED: t/t_disable_iff_multi_bad.v:13:4: Unsupported: default disable iff + 13 | default disable iff (!rstn); + | ^~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_disable_iff_multi_bad.v:14:4: Unsupported: default disable iff + 14 | default disable iff (!rstn); + | ^~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_disable_iff_multi_bad.pl b/test_regress/t/t_disable_iff_multi_bad.pl new file mode 100755 index 000000000..7fdfc93e0 --- /dev/null +++ b/test_regress/t/t_disable_iff_multi_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + verilator_flags2 => ["--timing"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_disable_iff_multi_bad.v b/test_regress/t/t_disable_iff_multi_bad.v new file mode 100644 index 000000000..624ab3268 --- /dev/null +++ b/test_regress/t/t_disable_iff_multi_bad.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2022 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + rstn + ); + input rstn; + + default disable iff (!rstn); + default disable iff (!rstn); + +endmodule diff --git a/test_regress/t/t_display.out b/test_regress/t/t_display.out index 00db3a06d..259cffc0f 100644 --- a/test_regress/t/t_display.out +++ b/test_regress/t/t_display.out @@ -61,6 +61,7 @@ b: 000001100 000001100 4294967294 2863311530 2863311530 +assoc_c='{} [0] hello, from a very long string. Percent %s are literally substituted in. hello, from a concatenated string. hello, from a concatenated format string [0]. diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v index ca2b59b21..9e23bd3b6 100644 --- a/test_regress/t/t_display.v +++ b/test_regress/t/t_display.v @@ -19,6 +19,8 @@ module t; string svs = "sv-str"; reg [31:0] regstr = "meep"; + reg [5:0] assoc_c[int]; + sub sub (); sub2 sub2 (); sub3 sub3 (); @@ -156,6 +158,7 @@ module t; $display($unsigned(-2)); // 4294967294 $display("%d", 32'haaaaaaaa); // 2863311530 $display(32'haaaaaaaa); // 2863311530 + $display("assoc_c=", assoc_c); // Default to %p $display("[%0t] %s%s%s", $time, "hel", "lo, fr", "om a very long string. Percent %s are literally substituted in."); diff --git a/test_regress/t/t_dist_attributes/mt_disabled.cpp b/test_regress/t/t_dist_attributes/mt_disabled.cpp index f292d422a..5211d804f 100644 --- a/test_regress/t/t_dist_attributes/mt_disabled.cpp +++ b/test_regress/t/t_dist_attributes/mt_disabled.cpp @@ -4,7 +4,7 @@ // // Code available from: https://verilator.org // -// Copyright 2022-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2022-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/test_regress/t/t_dist_attributes/mt_disabled.h b/test_regress/t/t_dist_attributes/mt_disabled.h index 5e085526d..e47a7be8a 100644 --- a/test_regress/t/t_dist_attributes/mt_disabled.h +++ b/test_regress/t/t_dist_attributes/mt_disabled.h @@ -4,7 +4,7 @@ // // Code available from: https://verilator.org // -// Copyright 2022-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2022-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/test_regress/t/t_dist_attributes/mt_enabled.cpp b/test_regress/t/t_dist_attributes/mt_enabled.cpp index 20bc2eb5d..569ed08d8 100644 --- a/test_regress/t/t_dist_attributes/mt_enabled.cpp +++ b/test_regress/t/t_dist_attributes/mt_enabled.cpp @@ -4,7 +4,7 @@ // // Code available from: https://verilator.org // -// Copyright 2022-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2022-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/test_regress/t/t_dist_attributes/mt_enabled.h b/test_regress/t/t_dist_attributes/mt_enabled.h index 3a71f1ad7..b13f0f9e8 100644 --- a/test_regress/t/t_dist_attributes/mt_enabled.h +++ b/test_regress/t/t_dist_attributes/mt_enabled.h @@ -4,7 +4,7 @@ // // Code available from: https://verilator.org // -// Copyright 2022-2023 by Wilson Snyder. This program is free software; you can +// Copyright 2022-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/test_regress/t/t_dist_copyright.pl b/test_regress/t/t_dist_copyright.pl index 18338c290..be727f19d 100755 --- a/test_regress/t/t_dist_copyright.pl +++ b/test_regress/t/t_dist_copyright.pl @@ -28,6 +28,7 @@ our @Exempt_Files_List = qw( ci/coverage-upload.sh docs/CONTRIBUTING.rst docs/CONTRIBUTORS + docs/README.rst docs/_static docs/gen docs/spelling.txt diff --git a/test_regress/t/t_dist_warn_coverage.pl b/test_regress/t/t_dist_warn_coverage.pl index 558a35b3d..f21e1e798 100755 --- a/test_regress/t/t_dist_warn_coverage.pl +++ b/test_regress/t/t_dist_warn_coverage.pl @@ -31,7 +31,6 @@ foreach my $s ( 'Unsupported: Ranges ignored in port-lists', # Hard to hit 'dynamic new() not expected in this context (expected under an assign)', # Instead get syntax error # Not yet analyzed - ' is not an in/out/inout/param/interface: ', ' loading non-variable', '--pipe-filter protocol error, unexpected: ', '/*verilator sformat*/ can only be applied to last argument of ', diff --git a/test_regress/t/t_do_while.v b/test_regress/t/t_do_while.v index 9423853f4..cf52f432d 100644 --- a/test_regress/t/t_do_while.v +++ b/test_regress/t/t_do_while.v @@ -52,6 +52,15 @@ module t (/*AUTOARG*/); end while (a < 0); if (a != 5) $stop; + a = 1; + do begin + do begin + int x = 1; + a += x; + end while (a < 3); + end while (a < 5); + if (a != 5) $stop; + $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_dotfiles.pl b/test_regress/t/t_dotfiles.pl index c60055256..9189fda39 100755 --- a/test_regress/t/t_dotfiles.pl +++ b/test_regress/t/t_dotfiles.pl @@ -18,7 +18,7 @@ compile( threads => 2 ); -foreach my $dotname ("linkcells", "task_call", "gate_simp", "gate_opt", +foreach my $dotname ("linkcells", "task_call", "gate_graph", "gate_final", "acyc_simp", "orderg_pre", "orderg_acyc", "orderg_order", "orderg_domain", "ordermv_initial", "ordermv_hazards", "ordermv_contraction", "ordermv_transitive1", "orderg_done", "ordermv_transitive2", "schedule") { diff --git a/test_regress/t/t_dpi_vams.cpp b/test_regress/t/t_dpi_vams.cpp index 3eed4f0ed..33fac09c8 100644 --- a/test_regress/t/t_dpi_vams.cpp +++ b/test_regress/t/t_dpi_vams.cpp @@ -8,7 +8,7 @@ #include -#include "Vt_dpi_vams.h" +#include VM_PREFIX_INCLUDE //====================================================================== diff --git a/test_regress/t/t_event_copy.out b/test_regress/t/t_event_copy.out index 8784c2883..81bba8753 100644 --- a/test_regress/t/t_event_copy.out +++ b/test_regress/t/t_event_copy.out @@ -1,17 +1,17 @@ -%Error-UNSUPPORTED: t/t_event_copy.v:100:13: Assignement to and from event in statically scheduled context. +%Error-UNSUPPORTED: t/t_event_copy.v:100:13: Assignment to and from event in statically scheduled context. : ... note: In instance 't' : Static event scheduling won't be able to handle this. : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. 100 | e4 = e3; | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_event_copy.v:101:13: Assignement to and from event in statically scheduled context. +%Error-UNSUPPORTED: t/t_event_copy.v:101:13: Assignment to and from event in statically scheduled context. : ... note: In instance 't' : Static event scheduling won't be able to handle this. : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. 101 | e3 = e2; | ^ -%Error-UNSUPPORTED: t/t_event_copy.v:128:13: Assignement to event in statically scheduled context. +%Error-UNSUPPORTED: t/t_event_copy.v:128:13: Assignment to event in statically scheduled context. : ... note: In instance 't' : Static event scheduling won't be able to handle this. : ... Suggest move the event into a completely dynamic context, eg. a class, and reference it only from such context. diff --git a/test_regress/t/t_flag_deprecated_bad.out b/test_regress/t/t_flag_deprecated_bad.out index e13b7628f..18d8e3d6f 100644 --- a/test_regress/t/t_flag_deprecated_bad.out +++ b/test_regress/t/t_flag_deprecated_bad.out @@ -1,7 +1,5 @@ -%Warning-DEPRECATED: Option -O is deprecated. Use -f or -fno- instead. +%Warning-DEPRECATED: Option --trace-fst-thread is deprecated. Use --trace-fst with --trace-threads > 0. ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. -%Warning-DEPRECATED: Option --prof-threads is deprecated. Use --prof-exec and --prof-pgo instead. -%Warning-DEPRECATED: Option --trace-fst-thread is deprecated. Use --trace-fst with --trace-threads > 0. %Warning-DEPRECATED: Option order-clock-delay is deprecated and has no effect. %Error: Exiting due to diff --git a/test_regress/t/t_flag_deprecated_bad.pl b/test_regress/t/t_flag_deprecated_bad.pl index 5edf03bb9..ba2b1d388 100755 --- a/test_regress/t/t_flag_deprecated_bad.pl +++ b/test_regress/t/t_flag_deprecated_bad.pl @@ -11,7 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(vlt => 1); lint( - verilator_flags2 => ["-Ox --prof-threads --trace-fst-thread --order-clock-delay"], + verilator_flags2 => ["--trace-fst-thread --order-clock-delay"], fails => 1, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_flag_expand_limit.pl b/test_regress/t/t_flag_expand_limit.pl index 60ff7ed44..4bbbb8f4e 100755 --- a/test_regress/t/t_flag_expand_limit.pl +++ b/test_regress/t/t_flag_expand_limit.pl @@ -14,7 +14,7 @@ compile( verilator_flags2 => ['--expand-limit 1 --stats -fno-dfg'], ); -file_grep($Self->{stats}, qr/Optimizations, expand limited\s+(\d+)/i, 4); +file_grep($Self->{stats}, qr/Optimizations, expand limited\s+(\d+)/i, 3); ok(1); 1; diff --git a/test_regress/t/t_flag_fi.cpp b/test_regress/t/t_flag_fi.cpp index e510f4cee..8ff1ba655 100644 --- a/test_regress/t/t_flag_fi.cpp +++ b/test_regress/t/t_flag_fi.cpp @@ -8,7 +8,7 @@ #include -#include "Vt_flag_fi.h" +#include VM_PREFIX_INCLUDE //====================================================================== diff --git a/test_regress/t/t_flag_fi_h.h b/test_regress/t/t_flag_fi_h.h index c92f7df3f..b104399bd 100644 --- a/test_regress/t/t_flag_fi_h.h +++ b/test_regress/t/t_flag_fi_h.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2010-2017 by Wilson Snyder. This program is free software; you can +// Copyright 2010-2024 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. diff --git a/test_regress/t/t_flag_lib_dpi.cpp b/test_regress/t/t_flag_lib_dpi.cpp new file mode 100644 index 000000000..60a3f7eb6 --- /dev/null +++ b/test_regress/t/t_flag_lib_dpi.cpp @@ -0,0 +1,14 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Shupei Fan. +// SPDX-License-Identifier: CC0-1.0 +// +//************************************************************************* + +#include "Vt_flag_lib_dpi__Dpi.h" +#include "svdpi.h" + +#include +void write_all_finished() { std::cout << "*-* All Finished *-*" << std::endl; } diff --git a/test_regress/t/t_flag_lib_dpi.mk b/test_regress/t/t_flag_lib_dpi.mk new file mode 100644 index 000000000..d51f28ed7 --- /dev/null +++ b/test_regress/t/t_flag_lib_dpi.mk @@ -0,0 +1,10 @@ +# DESCRIPTION: Verilator: Makefile for Verilog Test module +# +# This file ONLY is placed under the Creative Commons Public Domain, for +# any use, without warranty, 2023 by Shupei Fan. +# SPDX-License-Identifier: CC0-1.0 + +include Vt_flag_lib_dpi.mk + +t_flag_lib_dpi_test: libVt_flag_lib_dpi.a libverilated.a + $(LINK) $(LDFLAGS) $^ $(LDLIBS) -o $@ diff --git a/test_regress/t/t_flag_lib_dpi.pl b/test_regress/t/t_flag_lib_dpi.pl new file mode 100755 index 000000000..9cb3e8bfb --- /dev/null +++ b/test_regress/t/t_flag_lib_dpi.pl @@ -0,0 +1,34 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This file ONLY is placed under the Creative Commons Public Domain, for +# any use, without warranty, 2023 by Shupei Fan. +# SPDX-License-Identifier: CC0-1.0 + +scenarios(vlt => 1); + +run(logfile => "$Self->{obj_dir}/vlt_compile.log", + cmd => ["perl", + "$ENV{VERILATOR_ROOT}/bin/verilator", + "-cc", + "--build", + '--no-timing', + "-Mdir", + "$Self->{obj_dir}", + "t/t_flag_lib_dpi.v", + "$Self->{t_dir}/t_flag_lib_dpi.cpp", + "$Self->{t_dir}/t_flag_lib_dpi_main.cpp"], + verilator_run => 1, + ); + +run(logfile => "$Self->{obj_dir}/cxx_compile.log", + cmd => ["cd $Self->{obj_dir}" + . " && cp $Self->{t_dir}/t_flag_lib_dpi.mk t_flag_lib_dpi.mk" + . " && $ENV{MAKE} -f t_flag_lib_dpi.mk t_flag_lib_dpi_test" + . " && ./t_flag_lib_dpi_test"], + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_flag_lib_dpi.v b/test_regress/t/t_flag_lib_dpi.v new file mode 100644 index 000000000..2b16948bc --- /dev/null +++ b/test_regress/t/t_flag_lib_dpi.v @@ -0,0 +1,16 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Shupei Fan. +// SPDX-License-Identifier: CC0-1.0 + +import "DPI-C" function void write_all_finished(); + +module t (/*AUTOARG*/); + + initial begin + write_all_finished; + $finish; + end + +endmodule diff --git a/test_regress/t/t_flag_lib_dpi_main.cpp b/test_regress/t/t_flag_lib_dpi_main.cpp new file mode 100644 index 000000000..3fcfd8179 --- /dev/null +++ b/test_regress/t/t_flag_lib_dpi_main.cpp @@ -0,0 +1,42 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Shupei Fan. +// SPDX-License-Identifier: CC0-1.0 +// +//************************************************************************* +// +// DESCRIPTION: main() calling loop, created with Verilator --main + +#include "verilated.h" + +#include "Vt_flag_lib_dpi.h" + +//====================== + +int main(int argc, char** argv, char**) { + // Setup context, defaults, and parse command line + Verilated::debug(0); + const std::unique_ptr contextp{new VerilatedContext}; + contextp->commandArgs(argc, argv); + + // Construct the Verilated model, from Vtop.h generated from Verilating + const std::unique_ptr topp{new Vt_flag_lib_dpi{contextp.get()}}; + + // Simulate until $finish + while (!contextp->gotFinish()) { + // Evaluate model + topp->eval(); + // Advance time + contextp->timeInc(1); + } + + if (!contextp->gotFinish()) { + VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n");); + } + + // Final model cleanup + topp->final(); + return 0; +} diff --git a/test_regress/t/t_foreach_nindex_bad.out b/test_regress/t/t_foreach_nindex_bad.out index 1433bce46..4e28c541f 100644 --- a/test_regress/t/t_foreach_nindex_bad.out +++ b/test_regress/t/t_foreach_nindex_bad.out @@ -1,4 +1,5 @@ %Error: t/t_foreach_nindex_bad.v:12:34: foreach loop variables exceed number of indices of array + : ... note: In instance 't' 12 | foreach (array[i, j, badk, badl]); | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_fork_output_arg.pl b/test_regress/t/t_fork_output_arg.pl new file mode 100755 index 000000000..b8493bd06 --- /dev/null +++ b/test_regress/t/t_fork_output_arg.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["--exe --main --timing"], + make_main => 0, + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_fork_output_arg.v b/test_regress/t/t_fork_output_arg.v new file mode 100644 index 000000000..e5c5169e5 --- /dev/null +++ b/test_regress/t/t_fork_output_arg.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +class Cls; + int x = 100; + task get_x(output int arg); + arg = x; + endtask +endclass + +task automatic test; + int o; + Cls c = new; + fork + c.get_x(o); + join_any + if (o != 100) $stop; +endtask + +module t(); + initial begin + test(); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_func_rand.cpp b/test_regress/t/t_func_rand.cpp index 772dd9fee..c11d28602 100644 --- a/test_regress/t/t_func_rand.cpp +++ b/test_regress/t/t_func_rand.cpp @@ -8,7 +8,7 @@ #include -#include "Vt_func_rand.h" +#include VM_PREFIX_INCLUDE double sc_time_stamp() { return 0; } diff --git a/test_regress/t/t_gantt_two.cpp b/test_regress/t/t_gantt_two.cpp index 9bea82889..50a30b88b 100644 --- a/test_regress/t/t_gantt_two.cpp +++ b/test_regress/t/t_gantt_two.cpp @@ -8,7 +8,7 @@ #include "verilated.h" -#include "Vt_gantt_two.h" +#include VM_PREFIX_INCLUDE #include diff --git a/test_regress/t/t_hier_block.pl b/test_regress/t/t_hier_block.pl index 620a1c458..4253963ee 100755 --- a/test_regress/t/t_hier_block.pl +++ b/test_regress/t/t_hier_block.pl @@ -35,7 +35,7 @@ file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", qr/^\s+\/\/\s+timeprecision\s+(\d file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 13); +file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); ok(1); diff --git a/test_regress/t/t_hier_block_cmake.pl b/test_regress/t/t_hier_block_cmake.pl index 8ccd098fa..c815fb6c9 100755 --- a/test_regress/t/t_hier_block_cmake.pl +++ b/test_regress/t/t_hier_block_cmake.pl @@ -36,7 +36,7 @@ if (!$Self->have_cmake) { file_grep($target_dir . 'Vsub0/sub0.sv', /^module\s+(\S+)\s+/, "sub0"); file_grep($target_dir . 'Vsub1/sub1.sv', /^module\s+(\S+)\s+/, "sub1"); file_grep($target_dir . 'Vsub2/sub2.sv', /^module\s+(\S+)\s+/, "sub2"); - file_grep($target_dir . 'Vt_hier_block__stats.txt', qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 13); + file_grep($target_dir . 'Vt_hier_block__stats.txt', qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); file_grep($Self->{obj_dir} . '/run.log', qr/MACRO:(\S+) is defined/i, "cplusplus"); } diff --git a/test_regress/t/t_hier_block_cmake/CMakeLists.txt b/test_regress/t/t_hier_block_cmake/CMakeLists.txt index 87d396b8b..f39db2c11 100644 --- a/test_regress/t/t_hier_block_cmake/CMakeLists.txt +++ b/test_regress/t/t_hier_block_cmake/CMakeLists.txt @@ -2,7 +2,7 @@ # # DESCRIPTION: CMake script for t_hier_block_cmake # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/test_regress/t/t_hier_block_sc.pl b/test_regress/t/t_hier_block_sc.pl index 4a14b17d5..8fa8cc912 100755 --- a/test_regress/t/t_hier_block_sc.pl +++ b/test_regress/t/t_hier_block_sc.pl @@ -35,7 +35,7 @@ execute( file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 13); +file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); ok(1); diff --git a/test_regress/t/t_hier_block_sc_trace_fst.out b/test_regress/t/t_hier_block_sc_trace_fst.out index d483bed92..e96290518 100644 --- a/test_regress/t/t_hier_block_sc_trace_fst.out +++ b/test_regress/t/t_hier_block_sc_trace_fst.out @@ -1,5 +1,5 @@ $date - Mon Oct 23 12:15:09 2023 + Tue Oct 31 12:42:16 2023 $end $version @@ -74,1444 +74,1558 @@ $var wire 8 , out [7:0] $end $var logic 8 / tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end -$var parameter 32 0 N [31:0] $end -$var parameter 32 . WIDTH [31:0] $end $var wire 1 * clk $end $var wire 8 / in [7:0] $end $var wire 8 , out [7:0] $end -$var logic 8 1 tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_delay0.delay_2.genblk1.i_delay $end +$var wire 1 0 clk $end +$var wire 8 1 in [7:0] $end +$var wire 8 2 out [7:0] $end +$scope module delay_4 $end +$var parameter 32 3 N [31:0] $end +$var parameter 32 4 WIDTH [31:0] $end +$var wire 1 0 clk $end +$var wire 8 1 in [7:0] $end +$var wire 8 2 out [7:0] $end +$var logic 8 5 tmp [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_delay1 $end -$var wire 1 2 clk $end -$var wire 8 3 in [7:0] $end -$var wire 8 4 out [7:0] $end -$scope module delay_9 $end -$var parameter 32 5 N [31:0] $end -$var parameter 32 6 WIDTH [31:0] $end -$var wire 1 2 clk $end -$var wire 8 3 in [7:0] $end -$var wire 8 4 out [7:0] $end -$var logic 8 7 tmp [7:0] $end -$scope module genblk1 $end -$scope module i_delay $end -$var parameter 32 8 N [31:0] $end -$var parameter 32 6 WIDTH [31:0] $end -$var wire 1 2 clk $end +$var wire 1 6 clk $end $var wire 8 7 in [7:0] $end -$var wire 8 4 out [7:0] $end -$var logic 8 9 tmp [7:0] $end +$var wire 8 8 out [7:0] $end +$scope module delay_9 $end +$var parameter 32 9 N [31:0] $end +$var parameter 32 : WIDTH [31:0] $end +$var wire 1 6 clk $end +$var wire 8 7 in [7:0] $end +$var wire 8 8 out [7:0] $end +$var logic 8 ; tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end -$var parameter 32 : N [31:0] $end -$var parameter 32 6 WIDTH [31:0] $end -$var wire 1 2 clk $end -$var wire 8 9 in [7:0] $end -$var wire 8 4 out [7:0] $end -$var logic 8 ; tmp [7:0] $end +$var wire 1 6 clk $end +$var wire 8 ; in [7:0] $end +$var wire 8 8 out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_delay1.delay_9.genblk1.i_delay $end +$var wire 1 < clk $end +$var wire 8 = in [7:0] $end +$var wire 8 > out [7:0] $end +$scope module delay_2 $end +$var parameter 32 ? N [31:0] $end +$var parameter 32 @ WIDTH [31:0] $end +$var wire 1 < clk $end +$var wire 8 = in [7:0] $end +$var wire 8 > out [7:0] $end +$var logic 8 A tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var wire 1 < clk $end +$var wire 8 A in [7:0] $end +$var wire 8 > out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_delay1.delay_9.genblk1.i_delay.delay_2.genblk1.i_delay $end +$var wire 1 B clk $end +$var wire 8 C in [7:0] $end +$var wire 8 D out [7:0] $end +$scope module delay_4 $end +$var parameter 32 E N [31:0] $end +$var parameter 32 F WIDTH [31:0] $end +$var wire 1 B clk $end +$var wire 8 C in [7:0] $end +$var wire 8 D out [7:0] $end +$var logic 8 G tmp [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub0.i_sub0 $end -$var wire 1 < clk $end -$var wire 8 = in [7:0] $end -$var wire 8 > out [7:0] $end +$var wire 1 H clk $end +$var wire 8 I in [7:0] $end +$var wire 8 J out [7:0] $end $scope module sub0 $end -$var wire 1 < clk $end -$var wire 8 = in [7:0] $end -$var wire 8 > out [7:0] $end -$var logic 8 ? ff [7:0] $end +$var wire 1 H clk $end +$var wire 8 I in [7:0] $end +$var wire 8 J out [7:0] $end +$var logic 8 K ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub1 $end -$var wire 1 @ clk $end -$var wire 8 A in [11:4] $end -$var wire 8 B out [7:0] $end +$var wire 1 L clk $end +$var wire 8 M in [11:4] $end +$var wire 8 N out [7:0] $end $scope module sub1 $end -$var wire 1 @ clk $end -$var wire 8 A in [11:4] $end -$var wire 8 B out [7:0] $end -$var logic 8 C ff [7:0] $end +$var wire 1 L clk $end +$var wire 8 M in [11:4] $end +$var wire 8 N out [7:0] $end +$var logic 8 O ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2 $end -$var wire 1 D clk $end -$var wire 8 E in [7:0] $end -$var wire 8 F out [7:0] $end +$var wire 1 P clk $end +$var wire 8 Q in [7:0] $end +$var wire 8 R out [7:0] $end $scope module sub2 $end -$var wire 1 D clk $end -$var wire 8 E in [7:0] $end -$var wire 8 F out [7:0] $end -$var logic 8 G ff [7:0] $end +$var wire 1 P clk $end +$var wire 8 Q in [7:0] $end +$var wire 8 R out [7:0] $end +$var logic 8 S ff [7:0] $end $scope interface in_ifs $end -$var wire 1 D clk $end -$var logic 8 G data [7:0] $end +$var wire 1 P clk $end +$var logic 8 S data [7:0] $end $upscope $end $scope interface out_ifs $end -$var wire 1 D clk $end -$var logic 8 H data [7:0] $end +$var wire 1 P clk $end +$var logic 8 T data [7:0] $end $upscope $end $scope module i_sub3 $end $scope interface in $end -$var wire 1 D clk $end -$var logic 8 G data [7:0] $end +$var wire 1 P clk $end +$var logic 8 S data [7:0] $end $upscope $end $scope interface out $end -$var wire 1 D clk $end -$var logic 8 H data [7:0] $end +$var wire 1 P clk $end +$var logic 8 T data [7:0] $end $upscope $end -$var wire 8 G in_wire [7:0] $end -$var wire 8 H out_1 [7:0] $end -$var wire 8 I out_2 [7:0] $end +$var wire 8 S in_wire [7:0] $end +$var wire 8 T out_1 [7:0] $end +$var wire 8 U out_2 [7:0] $end $scope module i_sub3 $end -$var wire 1 D clk $end -$var wire 8 G in [7:0] $end -$var wire 8 H out [7:0] $end +$var wire 1 P clk $end +$var wire 8 S in [7:0] $end +$var wire 8 T out [7:0] $end $upscope $end $scope module i_sub3_2 $end -$var wire 1 D clk $end -$var wire 8 G in [7:0] $end -$var wire 8 I out [7:0] $end +$var wire 1 P clk $end +$var wire 8 S in [7:0] $end +$var wire 8 U out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end -$var wire 1 J clk $end -$var wire 8 K in [7:0] $end -$var wire 8 L out [7:0] $end +$var wire 1 V clk $end +$var wire 8 W in [7:0] $end +$var wire 8 X out [7:0] $end $scope module sub3_c $end -$var parameter 8 M P0 [7:0] $end -$var parameter 32 N UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 O UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 P UNUSED [15:0] $end -$var wire 1 J clk $end -$var wire 8 K in [7:0] $end -$var wire 8 L out [7:0] $end -$var logic 8 Q ff [7:0] $end -$var wire 8 L out4 [7:0] $end -$var wire 8 R out4_2 [7:0] $end +$var parameter 8 Y P0 [7:0] $end +$var parameter 32 Z UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 [ UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 \ UNUSED [15:0] $end +$var wire 1 V clk $end +$var wire 8 W in [7:0] $end +$var wire 8 X out [7:0] $end +$var logic 8 ] ff [7:0] $end +$var wire 8 X out4 [7:0] $end +$var wire 8 ^ out4_2 [7:0] $end $scope module i_sub4_0 $end -$var wire 1 J clk $end -$var wire 8 Q in [7:0] $end -$var wire 8 L out [7:0] $end +$var wire 1 V clk $end +$var wire 8 ] in [7:0] $end +$var wire 8 X out [7:0] $end $upscope $end $scope module i_sub4_1 $end -$var wire 1 J clk $end -$var wire 8 Q in [7:0] $end -$var wire 8 R out [7:0] $end +$var wire 1 V clk $end +$var wire 8 ] in [7:0] $end +$var wire 8 ^ out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end -$var wire 1 S clk $end -$var wire 8 T in [7:0] $end -$var wire 8 U out [7:0] $end +$var wire 1 _ clk $end +$var wire 8 ` in [7:0] $end +$var wire 8 a out [7:0] $end $scope module sub4_2 $end -$var parameter 32 V P0 [31:0] $end -$var real_parameter 64 W P1 $end -$var real_parameter 64 X P3 $end -$var wire 1 S clk $end -$var wire 8 T in [7:0] $end -$var wire 8 U out [7:0] $end -$var logic 8 Y ff [7:0] $end -$var logic 128 Z sub5_in[0][0] [127:0] $end -$var logic 128 [ sub5_in[0][1] [127:0] $end -$var logic 128 \ sub5_in[0][2] [127:0] $end -$var logic 128 ] sub5_in[1][0] [127:0] $end -$var logic 128 ^ sub5_in[1][1] [127:0] $end -$var logic 128 _ sub5_in[1][2] [127:0] $end -$var wire 8 ` sub5_out[0][0] [7:0] $end -$var wire 8 a sub5_out[0][1] [7:0] $end -$var wire 8 b sub5_out[0][2] [7:0] $end -$var wire 8 c sub5_out[1][0] [7:0] $end -$var wire 8 d sub5_out[1][1] [7:0] $end -$var wire 8 e sub5_out[1][2] [7:0] $end -$var int 32 f count [31:0] $end +$var parameter 32 b P0 [31:0] $end +$var real_parameter 64 c P1 $end +$var real_parameter 64 d P3 $end +$var wire 1 _ clk $end +$var wire 8 ` in [7:0] $end +$var wire 8 a out [7:0] $end +$var logic 8 e ff [7:0] $end +$var logic 128 f sub5_in[0][0] [127:0] $end +$var logic 128 g sub5_in[0][1] [127:0] $end +$var logic 128 h sub5_in[0][2] [127:0] $end +$var logic 128 i sub5_in[1][0] [127:0] $end +$var logic 128 j sub5_in[1][1] [127:0] $end +$var logic 128 k sub5_in[1][2] [127:0] $end +$var wire 8 l sub5_out[0][0] [7:0] $end +$var wire 8 m sub5_out[0][1] [7:0] $end +$var wire 8 n sub5_out[0][2] [7:0] $end +$var wire 8 o sub5_out[1][0] [7:0] $end +$var wire 8 p sub5_out[1][1] [7:0] $end +$var wire 8 q sub5_out[1][2] [7:0] $end +$var int 32 r count [31:0] $end $scope module i_sub5 $end -$var wire 1 S clk $end -$var wire 128 g in[0][0] [127:0] $end -$var wire 128 h in[0][1] [127:0] $end -$var wire 128 i in[0][2] [127:0] $end -$var wire 128 j in[1][0] [127:0] $end -$var wire 128 k in[1][1] [127:0] $end -$var wire 128 l in[1][2] [127:0] $end -$var wire 8 m out[0][0] [7:0] $end -$var wire 8 n out[0][1] [7:0] $end -$var wire 8 o out[0][2] [7:0] $end -$var wire 8 p out[1][0] [7:0] $end -$var wire 8 q out[1][1] [7:0] $end -$var wire 8 r out[1][2] [7:0] $end +$var wire 1 _ clk $end +$var wire 128 s in[0][0] [127:0] $end +$var wire 128 t in[0][1] [127:0] $end +$var wire 128 u in[0][2] [127:0] $end +$var wire 128 v in[1][0] [127:0] $end +$var wire 128 w in[1][1] [127:0] $end +$var wire 128 x in[1][2] [127:0] $end +$var wire 8 y out[0][0] [7:0] $end +$var wire 8 z out[0][1] [7:0] $end +$var wire 8 { out[0][2] [7:0] $end +$var wire 8 | out[1][0] [7:0] $end +$var wire 8 } out[1][1] [7:0] $end +$var wire 8 ~ out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 s i [31:0] $end +$var int 32 !! i [31:0] $end $scope module unnamedblk2 $end -$var int 32 t j [31:0] $end +$var int 32 "! j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 u exp [7:0] $end +$var byte 8 #! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end -$var wire 1 v clk $end -$var wire 128 w in[0][0] [127:0] $end -$var wire 128 x in[0][1] [127:0] $end -$var wire 128 y in[0][2] [127:0] $end -$var wire 128 z in[1][0] [127:0] $end -$var wire 128 { in[1][1] [127:0] $end -$var wire 128 | in[1][2] [127:0] $end -$var wire 8 } out[0][0] [7:0] $end -$var wire 8 ~ out[0][1] [7:0] $end -$var wire 8 !! out[0][2] [7:0] $end -$var wire 8 "! out[1][0] [7:0] $end -$var wire 8 #! out[1][1] [7:0] $end -$var wire 8 $! out[1][2] [7:0] $end +$var wire 1 $! clk $end +$var wire 128 %! in[0][0] [127:0] $end +$var wire 128 &! in[0][1] [127:0] $end +$var wire 128 '! in[0][2] [127:0] $end +$var wire 128 (! in[1][0] [127:0] $end +$var wire 128 )! in[1][1] [127:0] $end +$var wire 128 *! in[1][2] [127:0] $end +$var wire 8 +! out[0][0] [7:0] $end +$var wire 8 ,! out[0][1] [7:0] $end +$var wire 8 -! out[0][2] [7:0] $end +$var wire 8 .! out[1][0] [7:0] $end +$var wire 8 /! out[1][1] [7:0] $end +$var wire 8 0! out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 v clk $end -$var wire 128 w in[0][0] [127:0] $end -$var wire 128 x in[0][1] [127:0] $end -$var wire 128 y in[0][2] [127:0] $end -$var wire 128 z in[1][0] [127:0] $end -$var wire 128 { in[1][1] [127:0] $end -$var wire 128 | in[1][2] [127:0] $end -$var wire 8 } out[0][0] [7:0] $end -$var wire 8 ~ out[0][1] [7:0] $end -$var wire 8 !! out[0][2] [7:0] $end -$var wire 8 "! out[1][0] [7:0] $end -$var wire 8 #! out[1][1] [7:0] $end -$var wire 8 $! out[1][2] [7:0] $end -$var int 32 %! count [31:0] $end -$var wire 8 &! val0[0] [7:0] $end -$var wire 8 '! val0[1] [7:0] $end -$var wire 8 (! val1[0] [7:0] $end -$var wire 8 )! val1[1] [7:0] $end -$var wire 8 *! val2[0] [7:0] $end -$var wire 8 +! val2[1] [7:0] $end -$var wire 8 ,! val3[0] [7:0] $end -$var wire 8 -! val3[1] [7:0] $end +$var wire 1 $! clk $end +$var wire 128 %! in[0][0] [127:0] $end +$var wire 128 &! in[0][1] [127:0] $end +$var wire 128 '! in[0][2] [127:0] $end +$var wire 128 (! in[1][0] [127:0] $end +$var wire 128 )! in[1][1] [127:0] $end +$var wire 128 *! in[1][2] [127:0] $end +$var wire 8 +! out[0][0] [7:0] $end +$var wire 8 ,! out[0][1] [7:0] $end +$var wire 8 -! out[0][2] [7:0] $end +$var wire 8 .! out[1][0] [7:0] $end +$var wire 8 /! out[1][1] [7:0] $end +$var wire 8 0! out[1][2] [7:0] $end +$var int 32 1! count [31:0] $end +$var wire 8 2! val0[0] [7:0] $end +$var wire 8 3! val0[1] [7:0] $end +$var wire 8 4! val1[0] [7:0] $end +$var wire 8 5! val1[1] [7:0] $end +$var wire 8 6! val2[0] [7:0] $end +$var wire 8 7! val2[1] [7:0] $end +$var wire 8 8! val3[0] [7:0] $end +$var wire 8 9! val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 .! P0 [31:0] $end -$var parameter 32 /! P1 [31:0] $end -$var wire 8 &! out[0] [7:0] $end -$var wire 8 '! out[1] [7:0] $end +$var wire 8 :! out[0] [7:0] $end +$var wire 8 ;! out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 .! P0 [31:0] $end -$var parameter 32 /! P1 [31:0] $end -$var wire 8 (! out[0] [7:0] $end -$var wire 8 )! out[1] [7:0] $end +$var wire 8 ! out[0] [7:0] $end +$var wire 8 ?! out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 0! out[0] [7:0] $end -$var wire 8 1! out[1] [7:0] $end +$var wire 8 @! out[0] [7:0] $end +$var wire 8 A! out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 2! i [31:0] $end +$var int 32 B! i [31:0] $end $scope module unnamedblk2 $end -$var int 32 3! j [31:0] $end +$var int 32 C! j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 4! exp [127:0] $end +$var bit 128 D! exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end +$var wire 8 E! out[0] [7:0] $end +$var wire 8 F! out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 G! P0 [31:0] $end +$var parameter 32 H! P1 [31:0] $end +$var wire 8 E! out[0] [7:0] $end +$var wire 8 F! out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end -$var wire 8 5! out[0] [7:0] $end -$var wire 8 6! out[1] [7:0] $end +$var wire 8 I! out[0] [7:0] $end +$var wire 8 J! out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 7! P0 [31:0] $end -$var parameter 32 8! P1 [31:0] $end -$var wire 8 5! out[0] [7:0] $end -$var wire 8 6! out[1] [7:0] $end +$var parameter 32 K! P0 [31:0] $end +$var parameter 32 L! P1 [31:0] $end +$var wire 8 I! out[0] [7:0] $end +$var wire 8 J! out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end -$var wire 1 9! clk $end -$var wire 8 :! in [7:0] $end -$var wire 8 ;! out [7:0] $end +$var wire 1 M! clk $end +$var wire 8 N! in [7:0] $end +$var wire 8 O! out [7:0] $end $scope module sub4_b $end -$var parameter 32 ! P3 $end -$var wire 1 9! clk $end -$var wire 8 :! in [7:0] $end -$var wire 8 ;! out [7:0] $end -$var logic 8 ?! ff [7:0] $end -$var logic 128 @! sub5_in[0][0] [127:0] $end -$var logic 128 A! sub5_in[0][1] [127:0] $end -$var logic 128 B! sub5_in[0][2] [127:0] $end -$var logic 128 C! sub5_in[1][0] [127:0] $end -$var logic 128 D! sub5_in[1][1] [127:0] $end -$var logic 128 E! sub5_in[1][2] [127:0] $end -$var wire 8 F! sub5_out[0][0] [7:0] $end -$var wire 8 G! sub5_out[0][1] [7:0] $end -$var wire 8 H! sub5_out[0][2] [7:0] $end -$var wire 8 I! sub5_out[1][0] [7:0] $end -$var wire 8 J! sub5_out[1][1] [7:0] $end -$var wire 8 K! sub5_out[1][2] [7:0] $end -$var int 32 L! count [31:0] $end +$var parameter 32 P! P0 [31:0] $end +$var real_parameter 64 Q! P1 $end +$var real_parameter 64 R! P3 $end +$var wire 1 M! clk $end +$var wire 8 N! in [7:0] $end +$var wire 8 O! out [7:0] $end +$var logic 8 S! ff [7:0] $end +$var logic 128 T! sub5_in[0][0] [127:0] $end +$var logic 128 U! sub5_in[0][1] [127:0] $end +$var logic 128 V! sub5_in[0][2] [127:0] $end +$var logic 128 W! sub5_in[1][0] [127:0] $end +$var logic 128 X! sub5_in[1][1] [127:0] $end +$var logic 128 Y! sub5_in[1][2] [127:0] $end +$var wire 8 Z! sub5_out[0][0] [7:0] $end +$var wire 8 [! sub5_out[0][1] [7:0] $end +$var wire 8 \! sub5_out[0][2] [7:0] $end +$var wire 8 ]! sub5_out[1][0] [7:0] $end +$var wire 8 ^! sub5_out[1][1] [7:0] $end +$var wire 8 _! sub5_out[1][2] [7:0] $end +$var int 32 `! count [31:0] $end $scope module i_sub5 $end -$var wire 1 9! clk $end -$var wire 128 M! in[0][0] [127:0] $end -$var wire 128 N! in[0][1] [127:0] $end -$var wire 128 O! in[0][2] [127:0] $end -$var wire 128 P! in[1][0] [127:0] $end -$var wire 128 Q! in[1][1] [127:0] $end -$var wire 128 R! in[1][2] [127:0] $end -$var wire 8 S! out[0][0] [7:0] $end -$var wire 8 T! out[0][1] [7:0] $end -$var wire 8 U! out[0][2] [7:0] $end -$var wire 8 V! out[1][0] [7:0] $end -$var wire 8 W! out[1][1] [7:0] $end -$var wire 8 X! out[1][2] [7:0] $end +$var wire 1 M! clk $end +$var wire 128 a! in[0][0] [127:0] $end +$var wire 128 b! in[0][1] [127:0] $end +$var wire 128 c! in[0][2] [127:0] $end +$var wire 128 d! in[1][0] [127:0] $end +$var wire 128 e! in[1][1] [127:0] $end +$var wire 128 f! in[1][2] [127:0] $end +$var wire 8 g! out[0][0] [7:0] $end +$var wire 8 h! out[0][1] [7:0] $end +$var wire 8 i! out[0][2] [7:0] $end +$var wire 8 j! out[1][0] [7:0] $end +$var wire 8 k! out[1][1] [7:0] $end +$var wire 8 l! out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 Y! i [31:0] $end +$var int 32 m! i [31:0] $end $scope module unnamedblk2 $end -$var int 32 Z! j [31:0] $end +$var int 32 n! j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 [! exp [7:0] $end +$var byte 8 o! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end -$var wire 1 \! clk $end -$var wire 128 ]! in[0][0] [127:0] $end -$var wire 128 ^! in[0][1] [127:0] $end -$var wire 128 _! in[0][2] [127:0] $end -$var wire 128 `! in[1][0] [127:0] $end -$var wire 128 a! in[1][1] [127:0] $end -$var wire 128 b! in[1][2] [127:0] $end -$var wire 8 c! out[0][0] [7:0] $end -$var wire 8 d! out[0][1] [7:0] $end -$var wire 8 e! out[0][2] [7:0] $end -$var wire 8 f! out[1][0] [7:0] $end -$var wire 8 g! out[1][1] [7:0] $end -$var wire 8 h! out[1][2] [7:0] $end +$var wire 1 p! clk $end +$var wire 128 q! in[0][0] [127:0] $end +$var wire 128 r! in[0][1] [127:0] $end +$var wire 128 s! in[0][2] [127:0] $end +$var wire 128 t! in[1][0] [127:0] $end +$var wire 128 u! in[1][1] [127:0] $end +$var wire 128 v! in[1][2] [127:0] $end +$var wire 8 w! out[0][0] [7:0] $end +$var wire 8 x! out[0][1] [7:0] $end +$var wire 8 y! out[0][2] [7:0] $end +$var wire 8 z! out[1][0] [7:0] $end +$var wire 8 {! out[1][1] [7:0] $end +$var wire 8 |! out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 \! clk $end -$var wire 128 ]! in[0][0] [127:0] $end -$var wire 128 ^! in[0][1] [127:0] $end -$var wire 128 _! in[0][2] [127:0] $end -$var wire 128 `! in[1][0] [127:0] $end -$var wire 128 a! in[1][1] [127:0] $end -$var wire 128 b! in[1][2] [127:0] $end -$var wire 8 c! out[0][0] [7:0] $end -$var wire 8 d! out[0][1] [7:0] $end -$var wire 8 e! out[0][2] [7:0] $end -$var wire 8 f! out[1][0] [7:0] $end -$var wire 8 g! out[1][1] [7:0] $end -$var wire 8 h! out[1][2] [7:0] $end -$var int 32 i! count [31:0] $end -$var wire 8 j! val0[0] [7:0] $end -$var wire 8 k! val0[1] [7:0] $end -$var wire 8 l! val1[0] [7:0] $end -$var wire 8 m! val1[1] [7:0] $end -$var wire 8 n! val2[0] [7:0] $end -$var wire 8 o! val2[1] [7:0] $end -$var wire 8 p! val3[0] [7:0] $end -$var wire 8 q! val3[1] [7:0] $end +$var wire 1 p! clk $end +$var wire 128 q! in[0][0] [127:0] $end +$var wire 128 r! in[0][1] [127:0] $end +$var wire 128 s! in[0][2] [127:0] $end +$var wire 128 t! in[1][0] [127:0] $end +$var wire 128 u! in[1][1] [127:0] $end +$var wire 128 v! in[1][2] [127:0] $end +$var wire 8 w! out[0][0] [7:0] $end +$var wire 8 x! out[0][1] [7:0] $end +$var wire 8 y! out[0][2] [7:0] $end +$var wire 8 z! out[1][0] [7:0] $end +$var wire 8 {! out[1][1] [7:0] $end +$var wire 8 |! out[1][2] [7:0] $end +$var int 32 }! count [31:0] $end +$var wire 8 ~! val0[0] [7:0] $end +$var wire 8 !" val0[1] [7:0] $end +$var wire 8 "" val1[0] [7:0] $end +$var wire 8 #" val1[1] [7:0] $end +$var wire 8 $" val2[0] [7:0] $end +$var wire 8 %" val2[1] [7:0] $end +$var wire 8 &" val3[0] [7:0] $end +$var wire 8 '" val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 r! P0 [31:0] $end -$var parameter 32 s! P1 [31:0] $end -$var wire 8 j! out[0] [7:0] $end -$var wire 8 k! out[1] [7:0] $end +$var wire 8 (" out[0] [7:0] $end +$var wire 8 )" out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 r! P0 [31:0] $end -$var parameter 32 s! P1 [31:0] $end -$var wire 8 l! out[0] [7:0] $end -$var wire 8 m! out[1] [7:0] $end +$var wire 8 *" out[0] [7:0] $end +$var wire 8 +" out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 r! P0 [31:0] $end -$var parameter 32 s! P1 [31:0] $end -$var wire 8 n! out[0] [7:0] $end -$var wire 8 o! out[1] [7:0] $end +$var wire 8 ," out[0] [7:0] $end +$var wire 8 -" out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 t! out[0] [7:0] $end -$var wire 8 u! out[1] [7:0] $end +$var wire 8 ." out[0] [7:0] $end +$var wire 8 /" out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 v! i [31:0] $end +$var int 32 0" i [31:0] $end $scope module unnamedblk2 $end -$var int 32 w! j [31:0] $end +$var int 32 1" j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 x! exp [127:0] $end +$var bit 128 2" exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end +$var wire 8 3" out[0] [7:0] $end +$var wire 8 4" out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 5" P0 [31:0] $end +$var parameter 32 6" P1 [31:0] $end +$var wire 8 3" out[0] [7:0] $end +$var wire 8 4" out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end -$var wire 8 y! out[0] [7:0] $end -$var wire 8 z! out[1] [7:0] $end +$var wire 8 7" out[0] [7:0] $end +$var wire 8 8" out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 {! P0 [31:0] $end -$var parameter 32 |! P1 [31:0] $end -$var wire 8 y! out[0] [7:0] $end -$var wire 8 z! out[1] [7:0] $end +$var parameter 32 9" P0 [31:0] $end +$var parameter 32 :" P1 [31:0] $end +$var wire 8 7" out[0] [7:0] $end +$var wire 8 8" out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3_2 $end -$var wire 1 }! clk $end -$var wire 8 ~! in [7:0] $end -$var wire 8 !" out [7:0] $end +$var wire 1 ;" clk $end +$var wire 8 <" in [7:0] $end +$var wire 8 =" out [7:0] $end $scope module sub3_2 $end -$var parameter 8 "" P0 [7:0] $end -$var parameter 32 #" UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 $" UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 %" UNUSED [15:0] $end -$var wire 1 }! clk $end -$var wire 8 ~! in [7:0] $end -$var wire 8 !" out [7:0] $end -$var logic 8 &" ff [7:0] $end -$var wire 8 !" out4 [7:0] $end -$var wire 8 '" out4_2 [7:0] $end +$var parameter 8 >" P0 [7:0] $end +$var parameter 32 ?" UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 @" UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 A" UNUSED [15:0] $end +$var wire 1 ;" clk $end +$var wire 8 <" in [7:0] $end +$var wire 8 =" out [7:0] $end +$var logic 8 B" ff [7:0] $end +$var wire 8 =" out4 [7:0] $end +$var wire 8 C" out4_2 [7:0] $end $scope module i_sub4_0 $end -$var wire 1 }! clk $end -$var wire 8 &" in [7:0] $end -$var wire 8 !" out [7:0] $end +$var wire 1 ;" clk $end +$var wire 8 B" in [7:0] $end +$var wire 8 =" out [7:0] $end $upscope $end $scope module i_sub4_1 $end -$var wire 1 }! clk $end -$var wire 8 &" in [7:0] $end -$var wire 8 '" out [7:0] $end +$var wire 1 ;" clk $end +$var wire 8 B" in [7:0] $end +$var wire 8 C" out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end -$var wire 1 (" clk $end -$var wire 8 )" in [7:0] $end -$var wire 8 *" out [7:0] $end +$var wire 1 D" clk $end +$var wire 8 E" in [7:0] $end +$var wire 8 F" out [7:0] $end $scope module sub4_2 $end -$var parameter 32 +" P0 [31:0] $end -$var real_parameter 64 ," P1 $end -$var real_parameter 64 -" P3 $end -$var wire 1 (" clk $end -$var wire 8 )" in [7:0] $end -$var wire 8 *" out [7:0] $end -$var logic 8 ." ff [7:0] $end -$var logic 128 /" sub5_in[0][0] [127:0] $end -$var logic 128 0" sub5_in[0][1] [127:0] $end -$var logic 128 1" sub5_in[0][2] [127:0] $end -$var logic 128 2" sub5_in[1][0] [127:0] $end -$var logic 128 3" sub5_in[1][1] [127:0] $end -$var logic 128 4" sub5_in[1][2] [127:0] $end -$var wire 8 5" sub5_out[0][0] [7:0] $end -$var wire 8 6" sub5_out[0][1] [7:0] $end -$var wire 8 7" sub5_out[0][2] [7:0] $end -$var wire 8 8" sub5_out[1][0] [7:0] $end -$var wire 8 9" sub5_out[1][1] [7:0] $end -$var wire 8 :" sub5_out[1][2] [7:0] $end -$var int 32 ;" count [31:0] $end +$var parameter 32 G" P0 [31:0] $end +$var real_parameter 64 H" P1 $end +$var real_parameter 64 I" P3 $end +$var wire 1 D" clk $end +$var wire 8 E" in [7:0] $end +$var wire 8 F" out [7:0] $end +$var logic 8 J" ff [7:0] $end +$var logic 128 K" sub5_in[0][0] [127:0] $end +$var logic 128 L" sub5_in[0][1] [127:0] $end +$var logic 128 M" sub5_in[0][2] [127:0] $end +$var logic 128 N" sub5_in[1][0] [127:0] $end +$var logic 128 O" sub5_in[1][1] [127:0] $end +$var logic 128 P" sub5_in[1][2] [127:0] $end +$var wire 8 Q" sub5_out[0][0] [7:0] $end +$var wire 8 R" sub5_out[0][1] [7:0] $end +$var wire 8 S" sub5_out[0][2] [7:0] $end +$var wire 8 T" sub5_out[1][0] [7:0] $end +$var wire 8 U" sub5_out[1][1] [7:0] $end +$var wire 8 V" sub5_out[1][2] [7:0] $end +$var int 32 W" count [31:0] $end $scope module i_sub5 $end -$var wire 1 (" clk $end -$var wire 128 <" in[0][0] [127:0] $end -$var wire 128 =" in[0][1] [127:0] $end -$var wire 128 >" in[0][2] [127:0] $end -$var wire 128 ?" in[1][0] [127:0] $end -$var wire 128 @" in[1][1] [127:0] $end -$var wire 128 A" in[1][2] [127:0] $end -$var wire 8 B" out[0][0] [7:0] $end -$var wire 8 C" out[0][1] [7:0] $end -$var wire 8 D" out[0][2] [7:0] $end -$var wire 8 E" out[1][0] [7:0] $end -$var wire 8 F" out[1][1] [7:0] $end -$var wire 8 G" out[1][2] [7:0] $end +$var wire 1 D" clk $end +$var wire 128 X" in[0][0] [127:0] $end +$var wire 128 Y" in[0][1] [127:0] $end +$var wire 128 Z" in[0][2] [127:0] $end +$var wire 128 [" in[1][0] [127:0] $end +$var wire 128 \" in[1][1] [127:0] $end +$var wire 128 ]" in[1][2] [127:0] $end +$var wire 8 ^" out[0][0] [7:0] $end +$var wire 8 _" out[0][1] [7:0] $end +$var wire 8 `" out[0][2] [7:0] $end +$var wire 8 a" out[1][0] [7:0] $end +$var wire 8 b" out[1][1] [7:0] $end +$var wire 8 c" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 H" i [31:0] $end +$var int 32 d" i [31:0] $end $scope module unnamedblk2 $end -$var int 32 I" j [31:0] $end +$var int 32 e" j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 J" exp [7:0] $end +$var byte 8 f" exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end -$var wire 1 K" clk $end -$var wire 128 L" in[0][0] [127:0] $end -$var wire 128 M" in[0][1] [127:0] $end -$var wire 128 N" in[0][2] [127:0] $end -$var wire 128 O" in[1][0] [127:0] $end -$var wire 128 P" in[1][1] [127:0] $end -$var wire 128 Q" in[1][2] [127:0] $end -$var wire 8 R" out[0][0] [7:0] $end -$var wire 8 S" out[0][1] [7:0] $end -$var wire 8 T" out[0][2] [7:0] $end -$var wire 8 U" out[1][0] [7:0] $end -$var wire 8 V" out[1][1] [7:0] $end -$var wire 8 W" out[1][2] [7:0] $end +$var wire 1 g" clk $end +$var wire 128 h" in[0][0] [127:0] $end +$var wire 128 i" in[0][1] [127:0] $end +$var wire 128 j" in[0][2] [127:0] $end +$var wire 128 k" in[1][0] [127:0] $end +$var wire 128 l" in[1][1] [127:0] $end +$var wire 128 m" in[1][2] [127:0] $end +$var wire 8 n" out[0][0] [7:0] $end +$var wire 8 o" out[0][1] [7:0] $end +$var wire 8 p" out[0][2] [7:0] $end +$var wire 8 q" out[1][0] [7:0] $end +$var wire 8 r" out[1][1] [7:0] $end +$var wire 8 s" out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 K" clk $end -$var wire 128 L" in[0][0] [127:0] $end -$var wire 128 M" in[0][1] [127:0] $end -$var wire 128 N" in[0][2] [127:0] $end -$var wire 128 O" in[1][0] [127:0] $end -$var wire 128 P" in[1][1] [127:0] $end -$var wire 128 Q" in[1][2] [127:0] $end -$var wire 8 R" out[0][0] [7:0] $end -$var wire 8 S" out[0][1] [7:0] $end -$var wire 8 T" out[0][2] [7:0] $end -$var wire 8 U" out[1][0] [7:0] $end -$var wire 8 V" out[1][1] [7:0] $end -$var wire 8 W" out[1][2] [7:0] $end -$var int 32 X" count [31:0] $end -$var wire 8 Y" val0[0] [7:0] $end -$var wire 8 Z" val0[1] [7:0] $end -$var wire 8 [" val1[0] [7:0] $end -$var wire 8 \" val1[1] [7:0] $end -$var wire 8 ]" val2[0] [7:0] $end -$var wire 8 ^" val2[1] [7:0] $end -$var wire 8 _" val3[0] [7:0] $end -$var wire 8 `" val3[1] [7:0] $end +$var wire 1 g" clk $end +$var wire 128 h" in[0][0] [127:0] $end +$var wire 128 i" in[0][1] [127:0] $end +$var wire 128 j" in[0][2] [127:0] $end +$var wire 128 k" in[1][0] [127:0] $end +$var wire 128 l" in[1][1] [127:0] $end +$var wire 128 m" in[1][2] [127:0] $end +$var wire 8 n" out[0][0] [7:0] $end +$var wire 8 o" out[0][1] [7:0] $end +$var wire 8 p" out[0][2] [7:0] $end +$var wire 8 q" out[1][0] [7:0] $end +$var wire 8 r" out[1][1] [7:0] $end +$var wire 8 s" out[1][2] [7:0] $end +$var int 32 t" count [31:0] $end +$var wire 8 u" val0[0] [7:0] $end +$var wire 8 v" val0[1] [7:0] $end +$var wire 8 w" val1[0] [7:0] $end +$var wire 8 x" val1[1] [7:0] $end +$var wire 8 y" val2[0] [7:0] $end +$var wire 8 z" val2[1] [7:0] $end +$var wire 8 {" val3[0] [7:0] $end +$var wire 8 |" val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 a" P0 [31:0] $end -$var parameter 32 b" P1 [31:0] $end -$var wire 8 Y" out[0] [7:0] $end -$var wire 8 Z" out[1] [7:0] $end +$var wire 8 }" out[0] [7:0] $end +$var wire 8 ~" out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 a" P0 [31:0] $end -$var parameter 32 b" P1 [31:0] $end -$var wire 8 [" out[0] [7:0] $end -$var wire 8 \" out[1] [7:0] $end +$var wire 8 !# out[0] [7:0] $end +$var wire 8 "# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 a" P0 [31:0] $end -$var parameter 32 b" P1 [31:0] $end -$var wire 8 ]" out[0] [7:0] $end -$var wire 8 ^" out[1] [7:0] $end +$var wire 8 ## out[0] [7:0] $end +$var wire 8 $# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 c" out[0] [7:0] $end -$var wire 8 d" out[1] [7:0] $end +$var wire 8 %# out[0] [7:0] $end +$var wire 8 &# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 e" i [31:0] $end +$var int 32 '# i [31:0] $end $scope module unnamedblk2 $end -$var int 32 f" j [31:0] $end +$var int 32 (# j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 g" exp [127:0] $end +$var bit 128 )# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end +$var wire 8 *# out[0] [7:0] $end +$var wire 8 +# out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 ,# P0 [31:0] $end +$var parameter 32 -# P1 [31:0] $end +$var wire 8 *# out[0] [7:0] $end +$var wire 8 +# out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end -$var wire 8 h" out[0] [7:0] $end -$var wire 8 i" out[1] [7:0] $end +$var wire 8 .# out[0] [7:0] $end +$var wire 8 /# out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 j" P0 [31:0] $end -$var parameter 32 k" P1 [31:0] $end -$var wire 8 h" out[0] [7:0] $end -$var wire 8 i" out[1] [7:0] $end +$var parameter 32 0# P0 [31:0] $end +$var parameter 32 1# P1 [31:0] $end +$var wire 8 .# out[0] [7:0] $end +$var wire 8 /# out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end -$var wire 1 l" clk $end -$var wire 8 m" in [7:0] $end -$var wire 8 n" out [7:0] $end +$var wire 1 2# clk $end +$var wire 8 3# in [7:0] $end +$var wire 8 4# out [7:0] $end $scope module sub4_b $end -$var parameter 32 o" P0 [31:0] $end -$var real_parameter 64 p" P1 $end -$var real_parameter 64 q" P3 $end -$var wire 1 l" clk $end -$var wire 8 m" in [7:0] $end -$var wire 8 n" out [7:0] $end -$var logic 8 r" ff [7:0] $end -$var logic 128 s" sub5_in[0][0] [127:0] $end -$var logic 128 t" sub5_in[0][1] [127:0] $end -$var logic 128 u" sub5_in[0][2] [127:0] $end -$var logic 128 v" sub5_in[1][0] [127:0] $end -$var logic 128 w" sub5_in[1][1] [127:0] $end -$var logic 128 x" sub5_in[1][2] [127:0] $end -$var wire 8 y" sub5_out[0][0] [7:0] $end -$var wire 8 z" sub5_out[0][1] [7:0] $end -$var wire 8 {" sub5_out[0][2] [7:0] $end -$var wire 8 |" sub5_out[1][0] [7:0] $end -$var wire 8 }" sub5_out[1][1] [7:0] $end -$var wire 8 ~" sub5_out[1][2] [7:0] $end -$var int 32 !# count [31:0] $end +$var parameter 32 5# P0 [31:0] $end +$var real_parameter 64 6# P1 $end +$var real_parameter 64 7# P3 $end +$var wire 1 2# clk $end +$var wire 8 3# in [7:0] $end +$var wire 8 4# out [7:0] $end +$var logic 8 8# ff [7:0] $end +$var logic 128 9# sub5_in[0][0] [127:0] $end +$var logic 128 :# sub5_in[0][1] [127:0] $end +$var logic 128 ;# sub5_in[0][2] [127:0] $end +$var logic 128 <# sub5_in[1][0] [127:0] $end +$var logic 128 =# sub5_in[1][1] [127:0] $end +$var logic 128 ># sub5_in[1][2] [127:0] $end +$var wire 8 ?# sub5_out[0][0] [7:0] $end +$var wire 8 @# sub5_out[0][1] [7:0] $end +$var wire 8 A# sub5_out[0][2] [7:0] $end +$var wire 8 B# sub5_out[1][0] [7:0] $end +$var wire 8 C# sub5_out[1][1] [7:0] $end +$var wire 8 D# sub5_out[1][2] [7:0] $end +$var int 32 E# count [31:0] $end $scope module i_sub5 $end -$var wire 1 l" clk $end -$var wire 128 "# in[0][0] [127:0] $end -$var wire 128 ## in[0][1] [127:0] $end -$var wire 128 $# in[0][2] [127:0] $end -$var wire 128 %# in[1][0] [127:0] $end -$var wire 128 &# in[1][1] [127:0] $end -$var wire 128 '# in[1][2] [127:0] $end -$var wire 8 (# out[0][0] [7:0] $end -$var wire 8 )# out[0][1] [7:0] $end -$var wire 8 *# out[0][2] [7:0] $end -$var wire 8 +# out[1][0] [7:0] $end -$var wire 8 ,# out[1][1] [7:0] $end -$var wire 8 -# out[1][2] [7:0] $end +$var wire 1 2# clk $end +$var wire 128 F# in[0][0] [127:0] $end +$var wire 128 G# in[0][1] [127:0] $end +$var wire 128 H# in[0][2] [127:0] $end +$var wire 128 I# in[1][0] [127:0] $end +$var wire 128 J# in[1][1] [127:0] $end +$var wire 128 K# in[1][2] [127:0] $end +$var wire 8 L# out[0][0] [7:0] $end +$var wire 8 M# out[0][1] [7:0] $end +$var wire 8 N# out[0][2] [7:0] $end +$var wire 8 O# out[1][0] [7:0] $end +$var wire 8 P# out[1][1] [7:0] $end +$var wire 8 Q# out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 .# i [31:0] $end +$var int 32 R# i [31:0] $end $scope module unnamedblk2 $end -$var int 32 /# j [31:0] $end +$var int 32 S# j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 0# exp [7:0] $end +$var byte 8 T# exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end -$var wire 1 1# clk $end -$var wire 128 2# in[0][0] [127:0] $end -$var wire 128 3# in[0][1] [127:0] $end -$var wire 128 4# in[0][2] [127:0] $end -$var wire 128 5# in[1][0] [127:0] $end -$var wire 128 6# in[1][1] [127:0] $end -$var wire 128 7# in[1][2] [127:0] $end -$var wire 8 8# out[0][0] [7:0] $end -$var wire 8 9# out[0][1] [7:0] $end -$var wire 8 :# out[0][2] [7:0] $end -$var wire 8 ;# out[1][0] [7:0] $end -$var wire 8 <# out[1][1] [7:0] $end -$var wire 8 =# out[1][2] [7:0] $end +$var wire 1 U# clk $end +$var wire 128 V# in[0][0] [127:0] $end +$var wire 128 W# in[0][1] [127:0] $end +$var wire 128 X# in[0][2] [127:0] $end +$var wire 128 Y# in[1][0] [127:0] $end +$var wire 128 Z# in[1][1] [127:0] $end +$var wire 128 [# in[1][2] [127:0] $end +$var wire 8 \# out[0][0] [7:0] $end +$var wire 8 ]# out[0][1] [7:0] $end +$var wire 8 ^# out[0][2] [7:0] $end +$var wire 8 _# out[1][0] [7:0] $end +$var wire 8 `# out[1][1] [7:0] $end +$var wire 8 a# out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 1# clk $end -$var wire 128 2# in[0][0] [127:0] $end -$var wire 128 3# in[0][1] [127:0] $end -$var wire 128 4# in[0][2] [127:0] $end -$var wire 128 5# in[1][0] [127:0] $end -$var wire 128 6# in[1][1] [127:0] $end -$var wire 128 7# in[1][2] [127:0] $end -$var wire 8 8# out[0][0] [7:0] $end -$var wire 8 9# out[0][1] [7:0] $end -$var wire 8 :# out[0][2] [7:0] $end -$var wire 8 ;# out[1][0] [7:0] $end -$var wire 8 <# out[1][1] [7:0] $end -$var wire 8 =# out[1][2] [7:0] $end -$var int 32 ># count [31:0] $end -$var wire 8 ?# val0[0] [7:0] $end -$var wire 8 @# val0[1] [7:0] $end -$var wire 8 A# val1[0] [7:0] $end -$var wire 8 B# val1[1] [7:0] $end -$var wire 8 C# val2[0] [7:0] $end -$var wire 8 D# val2[1] [7:0] $end -$var wire 8 E# val3[0] [7:0] $end -$var wire 8 F# val3[1] [7:0] $end +$var wire 1 U# clk $end +$var wire 128 V# in[0][0] [127:0] $end +$var wire 128 W# in[0][1] [127:0] $end +$var wire 128 X# in[0][2] [127:0] $end +$var wire 128 Y# in[1][0] [127:0] $end +$var wire 128 Z# in[1][1] [127:0] $end +$var wire 128 [# in[1][2] [127:0] $end +$var wire 8 \# out[0][0] [7:0] $end +$var wire 8 ]# out[0][1] [7:0] $end +$var wire 8 ^# out[0][2] [7:0] $end +$var wire 8 _# out[1][0] [7:0] $end +$var wire 8 `# out[1][1] [7:0] $end +$var wire 8 a# out[1][2] [7:0] $end +$var int 32 b# count [31:0] $end +$var wire 8 c# val0[0] [7:0] $end +$var wire 8 d# val0[1] [7:0] $end +$var wire 8 e# val1[0] [7:0] $end +$var wire 8 f# val1[1] [7:0] $end +$var wire 8 g# val2[0] [7:0] $end +$var wire 8 h# val2[1] [7:0] $end +$var wire 8 i# val3[0] [7:0] $end +$var wire 8 j# val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 G# P0 [31:0] $end -$var parameter 32 H# P1 [31:0] $end -$var wire 8 ?# out[0] [7:0] $end -$var wire 8 @# out[1] [7:0] $end +$var wire 8 k# out[0] [7:0] $end +$var wire 8 l# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 G# P0 [31:0] $end -$var parameter 32 H# P1 [31:0] $end -$var wire 8 A# out[0] [7:0] $end -$var wire 8 B# out[1] [7:0] $end +$var wire 8 m# out[0] [7:0] $end +$var wire 8 n# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 G# P0 [31:0] $end -$var parameter 32 H# P1 [31:0] $end -$var wire 8 C# out[0] [7:0] $end -$var wire 8 D# out[1] [7:0] $end +$var wire 8 o# out[0] [7:0] $end +$var wire 8 p# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 I# out[0] [7:0] $end -$var wire 8 J# out[1] [7:0] $end +$var wire 8 q# out[0] [7:0] $end +$var wire 8 r# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 K# i [31:0] $end +$var int 32 s# i [31:0] $end $scope module unnamedblk2 $end -$var int 32 L# j [31:0] $end +$var int 32 t# j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 M# exp [127:0] $end +$var bit 128 u# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end +$var wire 8 v# out[0] [7:0] $end +$var wire 8 w# out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 x# P0 [31:0] $end +$var parameter 32 y# P1 [31:0] $end +$var wire 8 v# out[0] [7:0] $end +$var wire 8 w# out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end -$var wire 8 N# out[0] [7:0] $end -$var wire 8 O# out[1] [7:0] $end +$var wire 8 z# out[0] [7:0] $end +$var wire 8 {# out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 P# P0 [31:0] $end -$var parameter 32 Q# P1 [31:0] $end -$var wire 8 N# out[0] [7:0] $end -$var wire 8 O# out[1] [7:0] $end +$var parameter 32 |# P0 [31:0] $end +$var parameter 32 }# P1 [31:0] $end +$var wire 8 z# out[0] [7:0] $end +$var wire 8 {# out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3 $end -$var wire 1 R# clk $end -$var wire 8 S# in [7:0] $end -$var wire 8 T# out [7:0] $end +$var wire 1 ~# clk $end +$var wire 8 !$ in [7:0] $end +$var wire 8 "$ out [7:0] $end $scope module sub3_d $end -$var parameter 8 U# P0 [7:0] $end -$var parameter 32 V# UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 W# UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 X# UNUSED [15:0] $end -$var wire 1 R# clk $end -$var wire 8 S# in [7:0] $end -$var wire 8 T# out [7:0] $end -$var logic 8 Y# ff [7:0] $end -$var wire 8 T# out4 [7:0] $end -$var wire 8 Z# out4_2 [7:0] $end +$var parameter 8 #$ P0 [7:0] $end +$var parameter 32 $$ UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 %$ UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 &$ UNUSED [15:0] $end +$var wire 1 ~# clk $end +$var wire 8 !$ in [7:0] $end +$var wire 8 "$ out [7:0] $end +$var logic 8 '$ ff [7:0] $end +$var wire 8 "$ out4 [7:0] $end +$var wire 8 ($ out4_2 [7:0] $end $scope module i_sub4_0 $end -$var wire 1 R# clk $end -$var wire 8 Y# in [7:0] $end -$var wire 8 T# out [7:0] $end +$var wire 1 ~# clk $end +$var wire 8 '$ in [7:0] $end +$var wire 8 "$ out [7:0] $end $upscope $end $scope module i_sub4_1 $end -$var wire 1 R# clk $end -$var wire 8 Y# in [7:0] $end -$var wire 8 Z# out [7:0] $end +$var wire 1 ~# clk $end +$var wire 8 '$ in [7:0] $end +$var wire 8 ($ out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0 $end -$var wire 1 [# clk $end -$var wire 8 \# in [7:0] $end -$var wire 8 ]# out [7:0] $end +$var wire 1 )$ clk $end +$var wire 8 *$ in [7:0] $end +$var wire 8 +$ out [7:0] $end $scope module sub4_2 $end -$var parameter 32 ^# P0 [31:0] $end -$var real_parameter 64 _# P1 $end -$var real_parameter 64 `# P3 $end -$var wire 1 [# clk $end -$var wire 8 \# in [7:0] $end -$var wire 8 ]# out [7:0] $end -$var logic 8 a# ff [7:0] $end -$var logic 128 b# sub5_in[0][0] [127:0] $end -$var logic 128 c# sub5_in[0][1] [127:0] $end -$var logic 128 d# sub5_in[0][2] [127:0] $end -$var logic 128 e# sub5_in[1][0] [127:0] $end -$var logic 128 f# sub5_in[1][1] [127:0] $end -$var logic 128 g# sub5_in[1][2] [127:0] $end -$var wire 8 h# sub5_out[0][0] [7:0] $end -$var wire 8 i# sub5_out[0][1] [7:0] $end -$var wire 8 j# sub5_out[0][2] [7:0] $end -$var wire 8 k# sub5_out[1][0] [7:0] $end -$var wire 8 l# sub5_out[1][1] [7:0] $end -$var wire 8 m# sub5_out[1][2] [7:0] $end -$var int 32 n# count [31:0] $end +$var parameter 32 ,$ P0 [31:0] $end +$var real_parameter 64 -$ P1 $end +$var real_parameter 64 .$ P3 $end +$var wire 1 )$ clk $end +$var wire 8 *$ in [7:0] $end +$var wire 8 +$ out [7:0] $end +$var logic 8 /$ ff [7:0] $end +$var logic 128 0$ sub5_in[0][0] [127:0] $end +$var logic 128 1$ sub5_in[0][1] [127:0] $end +$var logic 128 2$ sub5_in[0][2] [127:0] $end +$var logic 128 3$ sub5_in[1][0] [127:0] $end +$var logic 128 4$ sub5_in[1][1] [127:0] $end +$var logic 128 5$ sub5_in[1][2] [127:0] $end +$var wire 8 6$ sub5_out[0][0] [7:0] $end +$var wire 8 7$ sub5_out[0][1] [7:0] $end +$var wire 8 8$ sub5_out[0][2] [7:0] $end +$var wire 8 9$ sub5_out[1][0] [7:0] $end +$var wire 8 :$ sub5_out[1][1] [7:0] $end +$var wire 8 ;$ sub5_out[1][2] [7:0] $end +$var int 32 <$ count [31:0] $end $scope module i_sub5 $end -$var wire 1 [# clk $end -$var wire 128 o# in[0][0] [127:0] $end -$var wire 128 p# in[0][1] [127:0] $end -$var wire 128 q# in[0][2] [127:0] $end -$var wire 128 r# in[1][0] [127:0] $end -$var wire 128 s# in[1][1] [127:0] $end -$var wire 128 t# in[1][2] [127:0] $end -$var wire 8 u# out[0][0] [7:0] $end -$var wire 8 v# out[0][1] [7:0] $end -$var wire 8 w# out[0][2] [7:0] $end -$var wire 8 x# out[1][0] [7:0] $end -$var wire 8 y# out[1][1] [7:0] $end -$var wire 8 z# out[1][2] [7:0] $end +$var wire 1 )$ clk $end +$var wire 128 =$ in[0][0] [127:0] $end +$var wire 128 >$ in[0][1] [127:0] $end +$var wire 128 ?$ in[0][2] [127:0] $end +$var wire 128 @$ in[1][0] [127:0] $end +$var wire 128 A$ in[1][1] [127:0] $end +$var wire 128 B$ in[1][2] [127:0] $end +$var wire 8 C$ out[0][0] [7:0] $end +$var wire 8 D$ out[0][1] [7:0] $end +$var wire 8 E$ out[0][2] [7:0] $end +$var wire 8 F$ out[1][0] [7:0] $end +$var wire 8 G$ out[1][1] [7:0] $end +$var wire 8 H$ out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 {# i [31:0] $end +$var int 32 I$ i [31:0] $end $scope module unnamedblk2 $end -$var int 32 |# j [31:0] $end +$var int 32 J$ j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 }# exp [7:0] $end +$var byte 8 K$ exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end -$var wire 1 ~# clk $end -$var wire 128 !$ in[0][0] [127:0] $end -$var wire 128 "$ in[0][1] [127:0] $end -$var wire 128 #$ in[0][2] [127:0] $end -$var wire 128 $$ in[1][0] [127:0] $end -$var wire 128 %$ in[1][1] [127:0] $end -$var wire 128 &$ in[1][2] [127:0] $end -$var wire 8 '$ out[0][0] [7:0] $end -$var wire 8 ($ out[0][1] [7:0] $end -$var wire 8 )$ out[0][2] [7:0] $end -$var wire 8 *$ out[1][0] [7:0] $end -$var wire 8 +$ out[1][1] [7:0] $end -$var wire 8 ,$ out[1][2] [7:0] $end +$var wire 1 L$ clk $end +$var wire 128 M$ in[0][0] [127:0] $end +$var wire 128 N$ in[0][1] [127:0] $end +$var wire 128 O$ in[0][2] [127:0] $end +$var wire 128 P$ in[1][0] [127:0] $end +$var wire 128 Q$ in[1][1] [127:0] $end +$var wire 128 R$ in[1][2] [127:0] $end +$var wire 8 S$ out[0][0] [7:0] $end +$var wire 8 T$ out[0][1] [7:0] $end +$var wire 8 U$ out[0][2] [7:0] $end +$var wire 8 V$ out[1][0] [7:0] $end +$var wire 8 W$ out[1][1] [7:0] $end +$var wire 8 X$ out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 ~# clk $end -$var wire 128 !$ in[0][0] [127:0] $end -$var wire 128 "$ in[0][1] [127:0] $end -$var wire 128 #$ in[0][2] [127:0] $end -$var wire 128 $$ in[1][0] [127:0] $end -$var wire 128 %$ in[1][1] [127:0] $end -$var wire 128 &$ in[1][2] [127:0] $end -$var wire 8 '$ out[0][0] [7:0] $end -$var wire 8 ($ out[0][1] [7:0] $end -$var wire 8 )$ out[0][2] [7:0] $end -$var wire 8 *$ out[1][0] [7:0] $end -$var wire 8 +$ out[1][1] [7:0] $end -$var wire 8 ,$ out[1][2] [7:0] $end -$var int 32 -$ count [31:0] $end -$var wire 8 .$ val0[0] [7:0] $end -$var wire 8 /$ val0[1] [7:0] $end -$var wire 8 0$ val1[0] [7:0] $end -$var wire 8 1$ val1[1] [7:0] $end -$var wire 8 2$ val2[0] [7:0] $end -$var wire 8 3$ val2[1] [7:0] $end -$var wire 8 4$ val3[0] [7:0] $end -$var wire 8 5$ val3[1] [7:0] $end +$var wire 1 L$ clk $end +$var wire 128 M$ in[0][0] [127:0] $end +$var wire 128 N$ in[0][1] [127:0] $end +$var wire 128 O$ in[0][2] [127:0] $end +$var wire 128 P$ in[1][0] [127:0] $end +$var wire 128 Q$ in[1][1] [127:0] $end +$var wire 128 R$ in[1][2] [127:0] $end +$var wire 8 S$ out[0][0] [7:0] $end +$var wire 8 T$ out[0][1] [7:0] $end +$var wire 8 U$ out[0][2] [7:0] $end +$var wire 8 V$ out[1][0] [7:0] $end +$var wire 8 W$ out[1][1] [7:0] $end +$var wire 8 X$ out[1][2] [7:0] $end +$var int 32 Y$ count [31:0] $end +$var wire 8 Z$ val0[0] [7:0] $end +$var wire 8 [$ val0[1] [7:0] $end +$var wire 8 \$ val1[0] [7:0] $end +$var wire 8 ]$ val1[1] [7:0] $end +$var wire 8 ^$ val2[0] [7:0] $end +$var wire 8 _$ val2[1] [7:0] $end +$var wire 8 `$ val3[0] [7:0] $end +$var wire 8 a$ val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 6$ P0 [31:0] $end -$var parameter 32 7$ P1 [31:0] $end -$var wire 8 .$ out[0] [7:0] $end -$var wire 8 /$ out[1] [7:0] $end +$var wire 8 b$ out[0] [7:0] $end +$var wire 8 c$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 6$ P0 [31:0] $end -$var parameter 32 7$ P1 [31:0] $end -$var wire 8 0$ out[0] [7:0] $end -$var wire 8 1$ out[1] [7:0] $end +$var wire 8 d$ out[0] [7:0] $end +$var wire 8 e$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 6$ P0 [31:0] $end -$var parameter 32 7$ P1 [31:0] $end -$var wire 8 2$ out[0] [7:0] $end -$var wire 8 3$ out[1] [7:0] $end +$var wire 8 f$ out[0] [7:0] $end +$var wire 8 g$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 8$ out[0] [7:0] $end -$var wire 8 9$ out[1] [7:0] $end +$var wire 8 h$ out[0] [7:0] $end +$var wire 8 i$ out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 :$ i [31:0] $end +$var int 32 j$ i [31:0] $end $scope module unnamedblk2 $end -$var int 32 ;$ j [31:0] $end +$var int 32 k$ j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 <$ exp [127:0] $end +$var bit 128 l$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end +$var wire 8 m$ out[0] [7:0] $end +$var wire 8 n$ out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 o$ P0 [31:0] $end +$var parameter 32 p$ P1 [31:0] $end +$var wire 8 m$ out[0] [7:0] $end +$var wire 8 n$ out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end -$var wire 8 =$ out[0] [7:0] $end -$var wire 8 >$ out[1] [7:0] $end +$var wire 8 q$ out[0] [7:0] $end +$var wire 8 r$ out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 ?$ P0 [31:0] $end -$var parameter 32 @$ P1 [31:0] $end -$var wire 8 =$ out[0] [7:0] $end -$var wire 8 >$ out[1] [7:0] $end +$var parameter 32 s$ P0 [31:0] $end +$var parameter 32 t$ P1 [31:0] $end +$var wire 8 q$ out[0] [7:0] $end +$var wire 8 r$ out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1 $end -$var wire 1 A$ clk $end -$var wire 8 B$ in [7:0] $end -$var wire 8 C$ out [7:0] $end +$var wire 1 u$ clk $end +$var wire 8 v$ in [7:0] $end +$var wire 8 w$ out [7:0] $end $scope module sub4_b $end -$var parameter 32 D$ P0 [31:0] $end -$var real_parameter 64 E$ P1 $end -$var real_parameter 64 F$ P3 $end -$var wire 1 A$ clk $end -$var wire 8 B$ in [7:0] $end -$var wire 8 C$ out [7:0] $end -$var logic 8 G$ ff [7:0] $end -$var logic 128 H$ sub5_in[0][0] [127:0] $end -$var logic 128 I$ sub5_in[0][1] [127:0] $end -$var logic 128 J$ sub5_in[0][2] [127:0] $end -$var logic 128 K$ sub5_in[1][0] [127:0] $end -$var logic 128 L$ sub5_in[1][1] [127:0] $end -$var logic 128 M$ sub5_in[1][2] [127:0] $end -$var wire 8 N$ sub5_out[0][0] [7:0] $end -$var wire 8 O$ sub5_out[0][1] [7:0] $end -$var wire 8 P$ sub5_out[0][2] [7:0] $end -$var wire 8 Q$ sub5_out[1][0] [7:0] $end -$var wire 8 R$ sub5_out[1][1] [7:0] $end -$var wire 8 S$ sub5_out[1][2] [7:0] $end -$var int 32 T$ count [31:0] $end +$var parameter 32 x$ P0 [31:0] $end +$var real_parameter 64 y$ P1 $end +$var real_parameter 64 z$ P3 $end +$var wire 1 u$ clk $end +$var wire 8 v$ in [7:0] $end +$var wire 8 w$ out [7:0] $end +$var logic 8 {$ ff [7:0] $end +$var logic 128 |$ sub5_in[0][0] [127:0] $end +$var logic 128 }$ sub5_in[0][1] [127:0] $end +$var logic 128 ~$ sub5_in[0][2] [127:0] $end +$var logic 128 !% sub5_in[1][0] [127:0] $end +$var logic 128 "% sub5_in[1][1] [127:0] $end +$var logic 128 #% sub5_in[1][2] [127:0] $end +$var wire 8 $% sub5_out[0][0] [7:0] $end +$var wire 8 %% sub5_out[0][1] [7:0] $end +$var wire 8 &% sub5_out[0][2] [7:0] $end +$var wire 8 '% sub5_out[1][0] [7:0] $end +$var wire 8 (% sub5_out[1][1] [7:0] $end +$var wire 8 )% sub5_out[1][2] [7:0] $end +$var int 32 *% count [31:0] $end $scope module i_sub5 $end -$var wire 1 A$ clk $end -$var wire 128 U$ in[0][0] [127:0] $end -$var wire 128 V$ in[0][1] [127:0] $end -$var wire 128 W$ in[0][2] [127:0] $end -$var wire 128 X$ in[1][0] [127:0] $end -$var wire 128 Y$ in[1][1] [127:0] $end -$var wire 128 Z$ in[1][2] [127:0] $end -$var wire 8 [$ out[0][0] [7:0] $end -$var wire 8 \$ out[0][1] [7:0] $end -$var wire 8 ]$ out[0][2] [7:0] $end -$var wire 8 ^$ out[1][0] [7:0] $end -$var wire 8 _$ out[1][1] [7:0] $end -$var wire 8 `$ out[1][2] [7:0] $end +$var wire 1 u$ clk $end +$var wire 128 +% in[0][0] [127:0] $end +$var wire 128 ,% in[0][1] [127:0] $end +$var wire 128 -% in[0][2] [127:0] $end +$var wire 128 .% in[1][0] [127:0] $end +$var wire 128 /% in[1][1] [127:0] $end +$var wire 128 0% in[1][2] [127:0] $end +$var wire 8 1% out[0][0] [7:0] $end +$var wire 8 2% out[0][1] [7:0] $end +$var wire 8 3% out[0][2] [7:0] $end +$var wire 8 4% out[1][0] [7:0] $end +$var wire 8 5% out[1][1] [7:0] $end +$var wire 8 6% out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 a$ i [31:0] $end +$var int 32 7% i [31:0] $end $scope module unnamedblk2 $end -$var int 32 b$ j [31:0] $end +$var int 32 8% j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 c$ exp [7:0] $end +$var byte 8 9% exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end -$var wire 1 d$ clk $end -$var wire 128 e$ in[0][0] [127:0] $end -$var wire 128 f$ in[0][1] [127:0] $end -$var wire 128 g$ in[0][2] [127:0] $end -$var wire 128 h$ in[1][0] [127:0] $end -$var wire 128 i$ in[1][1] [127:0] $end -$var wire 128 j$ in[1][2] [127:0] $end -$var wire 8 k$ out[0][0] [7:0] $end -$var wire 8 l$ out[0][1] [7:0] $end -$var wire 8 m$ out[0][2] [7:0] $end -$var wire 8 n$ out[1][0] [7:0] $end -$var wire 8 o$ out[1][1] [7:0] $end -$var wire 8 p$ out[1][2] [7:0] $end +$var wire 1 :% clk $end +$var wire 128 ;% in[0][0] [127:0] $end +$var wire 128 <% in[0][1] [127:0] $end +$var wire 128 =% in[0][2] [127:0] $end +$var wire 128 >% in[1][0] [127:0] $end +$var wire 128 ?% in[1][1] [127:0] $end +$var wire 128 @% in[1][2] [127:0] $end +$var wire 8 A% out[0][0] [7:0] $end +$var wire 8 B% out[0][1] [7:0] $end +$var wire 8 C% out[0][2] [7:0] $end +$var wire 8 D% out[1][0] [7:0] $end +$var wire 8 E% out[1][1] [7:0] $end +$var wire 8 F% out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 d$ clk $end -$var wire 128 e$ in[0][0] [127:0] $end -$var wire 128 f$ in[0][1] [127:0] $end -$var wire 128 g$ in[0][2] [127:0] $end -$var wire 128 h$ in[1][0] [127:0] $end -$var wire 128 i$ in[1][1] [127:0] $end -$var wire 128 j$ in[1][2] [127:0] $end -$var wire 8 k$ out[0][0] [7:0] $end -$var wire 8 l$ out[0][1] [7:0] $end -$var wire 8 m$ out[0][2] [7:0] $end -$var wire 8 n$ out[1][0] [7:0] $end -$var wire 8 o$ out[1][1] [7:0] $end -$var wire 8 p$ out[1][2] [7:0] $end -$var int 32 q$ count [31:0] $end -$var wire 8 r$ val0[0] [7:0] $end -$var wire 8 s$ val0[1] [7:0] $end -$var wire 8 t$ val1[0] [7:0] $end -$var wire 8 u$ val1[1] [7:0] $end -$var wire 8 v$ val2[0] [7:0] $end -$var wire 8 w$ val2[1] [7:0] $end -$var wire 8 x$ val3[0] [7:0] $end -$var wire 8 y$ val3[1] [7:0] $end +$var wire 1 :% clk $end +$var wire 128 ;% in[0][0] [127:0] $end +$var wire 128 <% in[0][1] [127:0] $end +$var wire 128 =% in[0][2] [127:0] $end +$var wire 128 >% in[1][0] [127:0] $end +$var wire 128 ?% in[1][1] [127:0] $end +$var wire 128 @% in[1][2] [127:0] $end +$var wire 8 A% out[0][0] [7:0] $end +$var wire 8 B% out[0][1] [7:0] $end +$var wire 8 C% out[0][2] [7:0] $end +$var wire 8 D% out[1][0] [7:0] $end +$var wire 8 E% out[1][1] [7:0] $end +$var wire 8 F% out[1][2] [7:0] $end +$var int 32 G% count [31:0] $end +$var wire 8 H% val0[0] [7:0] $end +$var wire 8 I% val0[1] [7:0] $end +$var wire 8 J% val1[0] [7:0] $end +$var wire 8 K% val1[1] [7:0] $end +$var wire 8 L% val2[0] [7:0] $end +$var wire 8 M% val2[1] [7:0] $end +$var wire 8 N% val3[0] [7:0] $end +$var wire 8 O% val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 z$ P0 [31:0] $end -$var parameter 32 {$ P1 [31:0] $end -$var wire 8 r$ out[0] [7:0] $end -$var wire 8 s$ out[1] [7:0] $end +$var wire 8 P% out[0] [7:0] $end +$var wire 8 Q% out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 z$ P0 [31:0] $end -$var parameter 32 {$ P1 [31:0] $end -$var wire 8 t$ out[0] [7:0] $end -$var wire 8 u$ out[1] [7:0] $end +$var wire 8 R% out[0] [7:0] $end +$var wire 8 S% out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 z$ P0 [31:0] $end -$var parameter 32 {$ P1 [31:0] $end -$var wire 8 v$ out[0] [7:0] $end -$var wire 8 w$ out[1] [7:0] $end +$var wire 8 T% out[0] [7:0] $end +$var wire 8 U% out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 |$ out[0] [7:0] $end -$var wire 8 }$ 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+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 @% +b00000000000000000000000000010001 G% +b00000001 #! +b00000001 o! +b00000001 f" +b00000001 T# +b00000001 K$ +b00000001 9% b00011101 $ -b00011101 F -b00011101 H -b00011101 I -b00011101 L b00011101 R +b00011101 T b00011101 U -b00011101 Y -b00011101 ;! -b00011101 ?! -b00011101 ~! -b00011101 S# +b00011101 X +b00011101 ^ +b00011101 a +b00011101 e +b00011101 O! +b00011101 S! +b00011101 <" +b00011101 !$ b00010101 ( -b00010101 4 -b00010101 ; +b00010101 8 +b00010101 > +b00010101 D +b00010101 G b00011011 % b00011011 & b00011011 + -b00011011 = -b00011011 !" -b00011011 '" -b00011011 *" -b00011011 ." -b00011011 n" -b00011011 r" -b00011011 T# -b00011011 Z# -b00011011 ]# -b00011011 a# -b00011011 C$ -b00011011 G$ -b00011001 E -b00011001 C -b00011001 B +b00011011 I +b00011011 =" +b00011011 C" +b00011011 F" +b00011011 J" +b00011011 4# +b00011011 8# +b00011011 "$ +b00011011 ($ +b00011011 +$ +b00011011 /$ +b00011011 w$ +b00011011 {$ +b00011001 Q +b00011001 O +b00011001 N b00011001 # b00011000 ' b00011000 , -b00011000 1 -b00011000 3 +b00011000 2 +b00011000 5 +b00011000 7 #171 #172 #173 diff --git a/test_regress/t/t_hier_block_sc_trace_fst.pl b/test_regress/t/t_hier_block_sc_trace_fst.pl index 8eb7a21c9..f95c37ec9 100755 --- a/test_regress/t/t_hier_block_sc_trace_fst.pl +++ b/test_regress/t/t_hier_block_sc_trace_fst.pl @@ -37,7 +37,7 @@ execute( file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 13); +file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); fst_identical($Self->trace_filename, $Self->{golden_filename}); diff --git a/test_regress/t/t_hier_block_sc_trace_vcd.out b/test_regress/t/t_hier_block_sc_trace_vcd.out index 92595318b..6b75f6fe8 100644 --- a/test_regress/t/t_hier_block_sc_trace_vcd.out +++ b/test_regress/t/t_hier_block_sc_trace_vcd.out @@ -1,6 +1,5 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module top $end $scope module t $end $var wire 1 * clk $end @@ -59,986 +58,1040 @@ $timescale 1ps $end $var wire 8 . in [7:0] $end $var wire 8 / out [7:0] $end $scope module delay_2 $end - $var wire 32 2 N [31:0] $end - $var wire 32 3 WIDTH [31:0] $end + $var wire 32 1 N [31:0] $end + $var wire 32 2 WIDTH [31:0] $end $var wire 1 - clk $end $var wire 8 . in [7:0] $end $var wire 8 / out [7:0] $end $var wire 8 0 tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 4 N [31:0] $end - $var wire 32 3 WIDTH [31:0] $end $var wire 1 - clk $end $var wire 8 0 in [7:0] $end $var wire 8 / out [7:0] $end - $var wire 8 1 tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_delay0.delay_2.genblk1.i_delay $end + $var wire 1 4 clk $end + $var wire 8 5 in [7:0] $end + $var wire 8 6 out [7:0] $end + $scope module delay_4 $end + $var wire 32 8 N [31:0] $end + $var wire 32 9 WIDTH [31:0] $end + $var wire 1 4 clk $end + $var wire 8 5 in [7:0] $end + $var wire 8 6 out [7:0] $end + $var wire 8 7 tmp [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_delay1 $end - $var wire 1 9 clk $end - $var wire 8 : in [7:0] $end - $var wire 8 ; out [7:0] $end + $var wire 1 ; clk $end + $var wire 8 < in [7:0] $end + $var wire 8 = out [7:0] $end $scope module delay_9 $end - $var wire 32 < N [31:0] $end - $var wire 32 = WIDTH [31:0] $end - $var wire 1 9 clk $end - $var wire 8 : in [7:0] $end - $var wire 8 ; out [7:0] $end - $var wire 8 6 tmp [7:0] $end + $var wire 32 ? N [31:0] $end + $var wire 32 @ WIDTH [31:0] $end + $var wire 1 ; clk $end + $var wire 8 < in [7:0] $end + $var wire 8 = out [7:0] $end + $var wire 8 > tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 > N [31:0] $end - $var wire 32 = WIDTH [31:0] $end - $var wire 1 9 clk $end - $var wire 8 6 in [7:0] $end - $var wire 8 ; out [7:0] $end - $var wire 8 7 tmp [7:0] $end - $scope module genblk1 $end - $scope module i_delay $end - $var wire 32 ? N [31:0] $end - $var wire 32 = WIDTH [31:0] $end - $var wire 1 9 clk $end - $var wire 8 7 in [7:0] $end - $var wire 8 ; out [7:0] $end - $var wire 8 8 tmp [7:0] $end - $upscope $end - $upscope $end + $var wire 1 ; clk $end + $var wire 8 > in [7:0] $end + $var wire 8 = out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_delay1.delay_9.genblk1.i_delay $end + $var wire 1 B clk $end + $var wire 8 C in [7:0] $end + $var wire 8 D out [7:0] $end + $scope module delay_2 $end + $var wire 32 F N [31:0] $end + $var wire 32 G WIDTH [31:0] $end + $var wire 1 B clk $end + $var wire 8 C in [7:0] $end + $var wire 8 D out [7:0] $end + $var wire 8 E tmp [7:0] $end + $scope module genblk1 $end + $scope module i_delay $end + $var wire 1 B clk $end + $var wire 8 E in [7:0] $end + $var wire 8 D out [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_delay1.delay_9.genblk1.i_delay.delay_2.genblk1.i_delay $end + $var wire 1 I clk $end + $var wire 8 J in [7:0] $end + $var wire 8 K out [7:0] $end + $scope module delay_4 $end + $var wire 32 M N [31:0] $end + $var wire 32 N WIDTH [31:0] $end + $var wire 1 I clk $end + $var wire 8 J in [7:0] $end + $var wire 8 K out [7:0] $end + $var wire 8 L tmp [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub0.i_sub0 $end - $var wire 1 A clk $end - $var wire 8 B in [7:0] $end - $var wire 8 C out [7:0] $end + $var wire 1 P clk $end + $var wire 8 Q in [7:0] $end + $var wire 8 R out [7:0] $end $scope module sub0 $end - $var wire 1 A clk $end - $var wire 8 B in [7:0] $end - $var wire 8 C out [7:0] $end - $var wire 8 D ff [7:0] $end + $var wire 1 P clk $end + $var wire 8 Q in [7:0] $end + $var wire 8 R out [7:0] $end + $var wire 8 S ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub1 $end - $var wire 1 F clk $end - $var wire 8 G in [11:4] $end - $var wire 8 H out [7:0] $end + $var wire 1 U clk $end + $var wire 8 V in [11:4] $end + $var wire 8 W out [7:0] $end $scope module sub1 $end - $var wire 1 F clk $end - $var wire 8 G in [11:4] $end - $var wire 8 H out [7:0] $end - $var wire 8 I ff [7:0] $end + $var wire 1 U clk $end + $var wire 8 V in [11:4] $end + $var wire 8 W out [7:0] $end + $var wire 8 X ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2 $end - $var wire 1 K clk $end - $var wire 8 L in [7:0] $end - $var wire 8 M out [7:0] $end + $var wire 1 Z clk $end + $var wire 8 [ in [7:0] $end + $var wire 8 \ out [7:0] $end $scope module sub2 $end - $var wire 1 K clk $end - $var wire 8 L in [7:0] $end - $var wire 8 M out [7:0] $end - $var wire 8 N ff [7:0] $end + $var wire 1 Z clk $end + $var wire 8 [ in [7:0] $end + $var wire 8 \ out [7:0] $end + $var wire 8 ] ff [7:0] $end $scope module in_ifs $end - $var wire 1 K clk $end - $var wire 8 N data [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ] data [7:0] $end $upscope $end $scope module out_ifs $end - $var wire 1 K clk $end - $var wire 8 O data [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ^ data [7:0] $end $upscope $end $scope module i_sub3 $end $scope module in $end - $var wire 1 K clk $end - $var wire 8 N data [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ] data [7:0] $end $upscope $end $scope module out $end - $var wire 1 K clk $end - $var wire 8 O data [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ^ data [7:0] $end $upscope $end - $var wire 8 N in_wire [7:0] $end - $var wire 8 O out_1 [7:0] $end - $var wire 8 P out_2 [7:0] $end + $var wire 8 ] in_wire [7:0] $end + $var wire 8 ^ out_1 [7:0] $end + $var wire 8 _ out_2 [7:0] $end $scope module i_sub3 $end - $var wire 1 K clk $end - $var wire 8 N in [7:0] $end - $var wire 8 O out [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ] in [7:0] $end + $var wire 8 ^ out [7:0] $end $upscope $end $scope module i_sub3_2 $end - $var wire 1 K clk $end - $var wire 8 N in [7:0] $end - $var wire 8 P out [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ] in [7:0] $end + $var wire 8 _ out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end - $var wire 1 R clk $end - $var wire 8 S in [7:0] $end - $var wire 8 T out [7:0] $end + $var wire 1 a clk $end + $var wire 8 b in [7:0] $end + $var wire 8 c out [7:0] $end $scope module sub3_c $end - $var wire 8 W P0 [7:0] $end - $var wire 32 X UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 Y UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 Z UNUSED [15:0] $end - $var wire 1 R clk $end - $var wire 8 S in [7:0] $end - $var wire 8 T out [7:0] $end - $var wire 8 U ff [7:0] $end - $var wire 8 T out4 [7:0] $end - $var wire 8 V out4_2 [7:0] $end + $var wire 8 f P0 [7:0] $end + $var wire 32 g UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 h UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 i UNUSED [15:0] $end + $var wire 1 a clk $end + $var wire 8 b in [7:0] $end + $var wire 8 c out [7:0] $end + $var wire 8 d ff [7:0] $end + $var wire 8 c out4 [7:0] $end + $var wire 8 e out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 1 R clk $end - $var wire 8 U in [7:0] $end - $var wire 8 T out [7:0] $end + $var wire 1 a clk $end + $var wire 8 d in [7:0] $end + $var wire 8 c out [7:0] $end $upscope $end $scope module i_sub4_1 $end - $var wire 1 R clk $end - $var wire 8 U in [7:0] $end - $var wire 8 V out [7:0] $end + $var wire 1 a clk $end + $var wire 8 d in [7:0] $end + $var wire 8 e out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end - $var wire 1 ?! clk $end - $var wire 8 @! in [7:0] $end - $var wire 8 A! out [7:0] $end + $var wire 1 N! clk $end + $var wire 8 O! in [7:0] $end + $var wire 8 P! out [7:0] $end $scope module sub4_2 $end - $var wire 32 B! P0 [31:0] $end - $var real 64 C! P1 $end - $var real 64 E! P3 $end - $var wire 1 ?! clk $end - $var wire 8 @! in [7:0] $end - $var wire 8 A! out [7:0] $end - $var wire 8 \ ff [7:0] $end - $var wire 128 ] sub5_in[0][0] [127:0] $end - $var wire 128 a sub5_in[0][1] [127:0] $end - $var wire 128 e sub5_in[0][2] [127:0] $end - $var wire 128 i sub5_in[1][0] [127:0] $end - $var wire 128 m sub5_in[1][1] [127:0] $end - $var wire 128 q sub5_in[1][2] [127:0] $end - $var wire 8 3! sub5_out[0][0] [7:0] $end - $var wire 8 4! sub5_out[0][1] [7:0] $end - $var wire 8 5! sub5_out[0][2] [7:0] $end - $var wire 8 6! sub5_out[1][0] [7:0] $end - $var wire 8 7! sub5_out[1][1] [7:0] $end - $var wire 8 8! sub5_out[1][2] [7:0] $end - $var wire 32 u count [31:0] $end + $var wire 32 Q! P0 [31:0] $end + $var real 64 R! P1 $end + $var real 64 T! P3 $end + $var wire 1 N! clk $end + $var wire 8 O! in [7:0] $end + $var wire 8 P! out [7:0] $end + $var wire 8 k ff [7:0] $end + $var wire 128 l sub5_in[0][0] [127:0] $end + $var wire 128 p sub5_in[0][1] [127:0] $end + $var wire 128 t sub5_in[0][2] [127:0] $end + $var wire 128 x sub5_in[1][0] [127:0] $end + $var wire 128 | sub5_in[1][1] [127:0] $end + $var wire 128 "! sub5_in[1][2] [127:0] $end + $var wire 8 B! sub5_out[0][0] [7:0] $end + $var wire 8 C! sub5_out[0][1] [7:0] $end + $var wire 8 D! sub5_out[0][2] [7:0] $end + $var wire 8 E! sub5_out[1][0] [7:0] $end + $var wire 8 F! sub5_out[1][1] [7:0] $end + $var wire 8 G! sub5_out[1][2] [7:0] $end + $var wire 32 &! count [31:0] $end $scope module i_sub5 $end - $var wire 1 ?! clk $end - $var wire 128 y in[0][0] [127:0] $end - $var wire 128 } in[0][1] [127:0] $end - $var wire 128 #! in[0][2] [127:0] $end - $var wire 128 '! in[1][0] [127:0] $end - $var wire 128 +! in[1][1] [127:0] $end - $var wire 128 /! in[1][2] [127:0] $end - $var wire 8 9! out[0][0] [7:0] $end - $var wire 8 :! out[0][1] [7:0] $end - $var wire 8 ;! out[0][2] [7:0] $end - $var wire 8 ! out[1][2] [7:0] $end + $var wire 1 N! clk $end + $var wire 128 *! in[0][0] [127:0] $end + $var wire 128 .! in[0][1] [127:0] $end + $var wire 128 2! in[0][2] [127:0] $end + $var wire 128 6! in[1][0] [127:0] $end + $var wire 128 :! in[1][1] [127:0] $end + $var wire 128 >! in[1][2] [127:0] $end + $var wire 8 H! out[0][0] [7:0] $end + $var wire 8 I! out[0][1] [7:0] $end + $var wire 8 J! out[0][2] [7:0] $end + $var wire 8 K! out[1][0] [7:0] $end + $var wire 8 L! out[1][1] [7:0] $end + $var wire 8 M! out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 v i [31:0] $end + $var wire 32 '! i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 w j [31:0] $end + $var wire 32 (! j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 x exp [7:0] $end + $var wire 8 )! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end - $var wire 1 Y! clk $end - $var wire 128 Z! in[0][0] [127:0] $end - $var wire 128 ^! in[0][1] [127:0] $end - $var wire 128 b! in[0][2] [127:0] $end - $var wire 128 f! in[1][0] [127:0] $end - $var wire 128 j! in[1][1] [127:0] $end - $var wire 128 n! in[1][2] [127:0] $end - $var wire 8 r! out[0][0] [7:0] $end - $var wire 8 s! out[0][1] [7:0] $end - $var wire 8 t! out[0][2] [7:0] $end - $var wire 8 u! out[1][0] [7:0] $end - $var wire 8 v! out[1][1] [7:0] $end - $var wire 8 w! out[1][2] [7:0] $end + $var wire 1 n! clk $end + $var wire 128 o! in[0][0] [127:0] $end + $var wire 128 s! in[0][1] [127:0] $end + $var wire 128 w! in[0][2] [127:0] $end + $var wire 128 {! in[1][0] [127:0] $end + $var wire 128 !" in[1][1] [127:0] $end + $var wire 128 %" in[1][2] [127:0] $end + $var wire 8 )" out[0][0] [7:0] $end + $var wire 8 *" out[0][1] [7:0] $end + $var wire 8 +" out[0][2] [7:0] $end + $var wire 8 ," out[1][0] [7:0] $end + $var wire 8 -" out[1][1] [7:0] $end + $var wire 8 ." out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 Y! clk $end - $var wire 128 Z! in[0][0] [127:0] $end - $var wire 128 ^! in[0][1] [127:0] $end - $var wire 128 b! in[0][2] [127:0] $end - $var wire 128 f! in[1][0] [127:0] $end - $var wire 128 j! in[1][1] [127:0] $end - $var wire 128 n! in[1][2] [127:0] $end - $var wire 8 r! out[0][0] [7:0] $end - $var wire 8 s! out[0][1] [7:0] $end - $var wire 8 t! out[0][2] [7:0] $end - $var wire 8 u! out[1][0] [7:0] $end - $var wire 8 v! out[1][1] [7:0] $end - $var wire 8 w! out[1][2] [7:0] $end - $var wire 32 R! count [31:0] $end - $var wire 8 H! val0[0] [7:0] $end - $var wire 8 I! val0[1] [7:0] $end - $var wire 8 J! val1[0] [7:0] $end - $var wire 8 K! val1[1] [7:0] $end - $var wire 8 L! val2[0] [7:0] $end - $var wire 8 M! val2[1] [7:0] $end - $var wire 8 N! val3[0] [7:0] $end - $var wire 8 O! val3[1] [7:0] $end + $var wire 1 n! clk $end + $var wire 128 o! in[0][0] [127:0] $end + $var wire 128 s! in[0][1] [127:0] $end + $var wire 128 w! in[0][2] [127:0] $end + $var wire 128 {! in[1][0] [127:0] $end + $var wire 128 !" in[1][1] [127:0] $end + $var wire 128 %" in[1][2] [127:0] $end + $var wire 8 )" out[0][0] [7:0] $end + $var wire 8 *" out[0][1] [7:0] $end + $var wire 8 +" out[0][2] [7:0] $end + $var wire 8 ," out[1][0] [7:0] $end + $var wire 8 -" out[1][1] [7:0] $end + $var wire 8 ." out[1][2] [7:0] $end + $var wire 32 g! count [31:0] $end + $var wire 8 W! val0[0] [7:0] $end + $var wire 8 X! val0[1] [7:0] $end + $var wire 8 Y! val1[0] [7:0] $end + $var wire 8 Z! val1[1] [7:0] $end + $var wire 8 [! val2[0] [7:0] $end + $var wire 8 \! val2[1] [7:0] $end + $var wire 8 ]! val3[0] [7:0] $end + $var wire 8 ^! val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 x! P0 [31:0] $end - $var wire 32 y! P1 [31:0] $end - $var wire 8 H! out[0] [7:0] $end - $var wire 8 I! out[1] [7:0] $end + $var wire 8 _! out[0] [7:0] $end + $var wire 8 `! out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 x! P0 [31:0] $end - $var wire 32 y! P1 [31:0] $end - $var wire 8 J! out[0] [7:0] $end - $var wire 8 K! out[1] [7:0] $end + $var wire 8 a! out[0] [7:0] $end + $var wire 8 b! out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 x! P0 [31:0] $end - $var wire 32 y! P1 [31:0] $end - $var wire 8 L! out[0] [7:0] $end - $var wire 8 M! out[1] [7:0] $end + $var wire 8 c! out[0] [7:0] $end + $var wire 8 d! out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 P! out[0] [7:0] $end - $var wire 8 Q! out[1] [7:0] $end + $var wire 8 e! out[0] [7:0] $end + $var wire 8 f! out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 S! i [31:0] $end + $var wire 32 h! i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 T! j [31:0] $end + $var wire 32 i! j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 U! exp [127:0] $end + $var wire 128 j! exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end + $var wire 8 0" out[0] [7:0] $end + $var wire 8 1" out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 2" P0 [31:0] $end + $var wire 32 3" P1 [31:0] $end + $var wire 8 0" out[0] [7:0] $end + $var wire 8 1" out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end - $var wire 8 {! out[0] [7:0] $end - $var wire 8 |! out[1] [7:0] $end + $var wire 8 5" out[0] [7:0] $end + $var wire 8 6" out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 }! P0 [31:0] $end - $var wire 32 ~! P1 [31:0] $end - $var wire 8 {! out[0] [7:0] $end - $var wire 8 |! out[1] [7:0] $end + $var wire 32 7" P0 [31:0] $end + $var wire 32 8" P1 [31:0] $end + $var wire 8 5" out[0] [7:0] $end + $var wire 8 6" out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end - $var wire 1 c" clk $end - $var wire 8 d" in [7:0] $end - $var wire 8 e" out [7:0] $end + $var wire 1 {" clk $end + $var wire 8 |" in [7:0] $end + $var wire 8 }" out [7:0] $end $scope module sub4_b $end - $var wire 32 f" P0 [31:0] $end - $var real 64 g" P1 $end - $var real 64 i" P3 $end - $var wire 1 c" clk $end - $var wire 8 d" in [7:0] $end - $var wire 8 e" out [7:0] $end - $var wire 8 "" ff [7:0] $end - $var wire 128 #" sub5_in[0][0] [127:0] $end - $var wire 128 '" sub5_in[0][1] [127:0] $end - $var wire 128 +" sub5_in[0][2] [127:0] $end - $var wire 128 /" sub5_in[1][0] [127:0] $end - $var wire 128 3" sub5_in[1][1] [127:0] $end - $var wire 128 7" sub5_in[1][2] [127:0] $end - $var wire 8 W" sub5_out[0][0] [7:0] $end - $var wire 8 X" sub5_out[0][1] [7:0] $end - $var wire 8 Y" sub5_out[0][2] [7:0] $end - $var wire 8 Z" sub5_out[1][0] [7:0] $end - $var wire 8 [" sub5_out[1][1] [7:0] $end - $var wire 8 \" sub5_out[1][2] [7:0] $end - $var wire 32 ;" count [31:0] $end + $var wire 32 ~" P0 [31:0] $end + $var real 64 !# P1 $end + $var real 64 ## P3 $end + $var wire 1 {" clk $end + $var wire 8 |" in [7:0] $end + $var wire 8 }" out [7:0] $end + $var wire 8 :" ff [7:0] $end + $var wire 128 ;" sub5_in[0][0] [127:0] $end + $var wire 128 ?" sub5_in[0][1] [127:0] $end + $var wire 128 C" sub5_in[0][2] [127:0] $end + $var wire 128 G" sub5_in[1][0] [127:0] $end + $var wire 128 K" sub5_in[1][1] [127:0] $end + $var wire 128 O" sub5_in[1][2] [127:0] $end + $var wire 8 o" sub5_out[0][0] [7:0] $end + $var wire 8 p" sub5_out[0][1] [7:0] $end + $var wire 8 q" sub5_out[0][2] [7:0] $end + $var wire 8 r" sub5_out[1][0] [7:0] $end + $var wire 8 s" sub5_out[1][1] [7:0] $end + $var wire 8 t" sub5_out[1][2] [7:0] $end + $var wire 32 S" count [31:0] $end $scope module i_sub5 $end - $var wire 1 c" clk $end - $var wire 128 ?" in[0][0] [127:0] $end - $var wire 128 C" in[0][1] [127:0] $end - $var wire 128 G" in[0][2] [127:0] $end - $var wire 128 K" in[1][0] [127:0] $end - $var wire 128 O" in[1][1] [127:0] $end - $var wire 128 S" in[1][2] [127:0] $end - $var wire 8 ]" out[0][0] [7:0] $end - $var wire 8 ^" out[0][1] [7:0] $end - $var wire 8 _" out[0][2] [7:0] $end - $var wire 8 `" out[1][0] [7:0] $end - $var wire 8 a" out[1][1] [7:0] $end - $var wire 8 b" out[1][2] [7:0] $end + $var wire 1 {" clk $end + $var wire 128 W" in[0][0] [127:0] $end + $var wire 128 [" in[0][1] [127:0] $end + $var wire 128 _" in[0][2] [127:0] $end + $var wire 128 c" in[1][0] [127:0] $end + $var wire 128 g" in[1][1] [127:0] $end + $var wire 128 k" in[1][2] [127:0] $end + $var wire 8 u" out[0][0] [7:0] $end + $var wire 8 v" out[0][1] [7:0] $end + $var wire 8 w" out[0][2] [7:0] $end + $var wire 8 x" out[1][0] [7:0] $end + $var wire 8 y" out[1][1] [7:0] $end + $var wire 8 z" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 <" i [31:0] $end + $var wire 32 T" i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 =" j [31:0] $end + $var wire 32 U" j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 >" exp [7:0] $end + $var wire 8 V" exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end - $var wire 1 }" clk $end - $var wire 128 ~" in[0][0] [127:0] $end - $var wire 128 $# in[0][1] [127:0] $end - $var wire 128 (# in[0][2] [127:0] $end - $var wire 128 ,# in[1][0] [127:0] $end - $var wire 128 0# in[1][1] [127:0] $end - $var wire 128 4# in[1][2] [127:0] $end - $var wire 8 8# out[0][0] [7:0] $end - $var wire 8 9# out[0][1] [7:0] $end - $var wire 8 :# out[0][2] [7:0] $end - $var wire 8 ;# out[1][0] [7:0] $end - $var wire 8 <# out[1][1] [7:0] $end - $var wire 8 =# out[1][2] [7:0] $end + $var wire 1 =# clk $end + $var wire 128 ># in[0][0] [127:0] $end + $var wire 128 B# in[0][1] [127:0] $end + $var wire 128 F# in[0][2] [127:0] $end + $var wire 128 J# in[1][0] [127:0] $end + $var wire 128 N# in[1][1] [127:0] $end + $var wire 128 R# in[1][2] [127:0] $end + $var wire 8 V# out[0][0] [7:0] $end + $var wire 8 W# out[0][1] [7:0] $end + $var wire 8 X# out[0][2] [7:0] $end + $var wire 8 Y# out[1][0] [7:0] $end + $var wire 8 Z# out[1][1] [7:0] $end + $var wire 8 [# out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 }" clk $end - $var wire 128 ~" in[0][0] [127:0] $end - $var wire 128 $# in[0][1] [127:0] $end - $var wire 128 (# in[0][2] [127:0] $end - $var wire 128 ,# in[1][0] [127:0] $end - $var wire 128 0# in[1][1] [127:0] $end - $var wire 128 4# in[1][2] [127:0] $end - $var wire 8 8# out[0][0] [7:0] $end - $var wire 8 9# out[0][1] [7:0] $end - $var wire 8 :# out[0][2] [7:0] $end - $var wire 8 ;# out[1][0] [7:0] $end - $var wire 8 <# out[1][1] [7:0] $end - $var wire 8 =# out[1][2] [7:0] $end - $var wire 32 v" count [31:0] $end - $var wire 8 l" val0[0] [7:0] $end - $var wire 8 m" val0[1] [7:0] $end - $var wire 8 n" val1[0] [7:0] $end - $var wire 8 o" val1[1] [7:0] $end - $var wire 8 p" val2[0] [7:0] $end - $var wire 8 q" val2[1] [7:0] $end - $var wire 8 r" val3[0] [7:0] $end - $var wire 8 s" val3[1] [7:0] $end + $var wire 1 =# clk $end + $var wire 128 ># in[0][0] [127:0] $end + $var wire 128 B# in[0][1] [127:0] $end + $var wire 128 F# in[0][2] [127:0] $end + $var wire 128 J# in[1][0] [127:0] $end + $var wire 128 N# in[1][1] [127:0] $end + $var wire 128 R# in[1][2] [127:0] $end + $var wire 8 V# out[0][0] [7:0] $end + $var wire 8 W# out[0][1] [7:0] $end + $var wire 8 X# out[0][2] [7:0] $end + $var wire 8 Y# out[1][0] [7:0] $end + $var wire 8 Z# out[1][1] [7:0] $end + $var wire 8 [# out[1][2] [7:0] $end + $var wire 32 6# count [31:0] $end + $var wire 8 &# val0[0] [7:0] $end + $var wire 8 '# val0[1] [7:0] $end + $var wire 8 (# val1[0] [7:0] $end + $var wire 8 )# val1[1] [7:0] $end + $var wire 8 *# val2[0] [7:0] $end + $var wire 8 +# val2[1] [7:0] $end + $var wire 8 ,# val3[0] [7:0] $end + $var wire 8 -# val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 ># P0 [31:0] $end - $var wire 32 ?# P1 [31:0] $end - $var wire 8 l" out[0] [7:0] $end - $var wire 8 m" out[1] [7:0] $end + $var wire 8 .# out[0] [7:0] $end + $var wire 8 /# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 ># P0 [31:0] $end - $var wire 32 ?# P1 [31:0] $end - $var wire 8 n" out[0] [7:0] $end - $var wire 8 o" out[1] [7:0] $end + $var wire 8 0# out[0] [7:0] $end + $var wire 8 1# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 ># P0 [31:0] $end - $var wire 32 ?# P1 [31:0] $end - $var wire 8 p" out[0] [7:0] $end - $var wire 8 q" out[1] [7:0] $end + $var wire 8 2# out[0] [7:0] $end + $var wire 8 3# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 t" out[0] [7:0] $end - $var wire 8 u" out[1] [7:0] $end + $var wire 8 4# out[0] [7:0] $end + $var wire 8 5# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 w" i [31:0] $end + $var wire 32 7# i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 x" j [31:0] $end + $var wire 32 8# j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 y" exp [127:0] $end + $var wire 128 9# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end + $var wire 8 ]# out[0] [7:0] $end + $var wire 8 ^# out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 _# P0 [31:0] $end + $var wire 32 `# P1 [31:0] $end + $var wire 8 ]# out[0] [7:0] $end + $var wire 8 ^# out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end - $var wire 8 A# out[0] [7:0] $end - $var wire 8 B# out[1] [7:0] $end + $var wire 8 b# out[0] [7:0] $end + $var wire 8 c# out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 C# P0 [31:0] $end - $var wire 32 D# P1 [31:0] $end - $var wire 8 A# out[0] [7:0] $end - $var wire 8 B# out[1] [7:0] $end + $var wire 32 d# P0 [31:0] $end + $var wire 32 e# P1 [31:0] $end + $var wire 8 b# out[0] [7:0] $end + $var wire 8 c# out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3_2 $end - $var wire 1 F# clk $end - $var wire 8 G# in [7:0] $end - $var wire 8 H# out [7:0] $end + $var wire 1 g# clk $end + $var wire 8 h# in [7:0] $end + $var wire 8 i# out [7:0] $end $scope module sub3_2 $end - $var wire 8 K# P0 [7:0] $end - $var wire 32 L# UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 M# UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 N# UNUSED [15:0] $end - $var wire 1 F# clk $end - $var wire 8 G# in [7:0] $end - $var wire 8 H# out [7:0] $end - $var wire 8 I# ff [7:0] $end - $var wire 8 H# out4 [7:0] $end - $var wire 8 J# out4_2 [7:0] $end + $var wire 8 l# P0 [7:0] $end + $var wire 32 m# UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 n# UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 o# UNUSED [15:0] $end + $var wire 1 g# clk $end + $var wire 8 h# in [7:0] $end + $var wire 8 i# out [7:0] $end + $var wire 8 j# ff [7:0] $end + $var wire 8 i# out4 [7:0] $end + $var wire 8 k# out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 1 F# clk $end - $var wire 8 I# in [7:0] $end - $var wire 8 H# out [7:0] $end + $var wire 1 g# clk $end + $var wire 8 j# in [7:0] $end + $var wire 8 i# out [7:0] $end $upscope $end $scope module i_sub4_1 $end - $var wire 1 F# clk $end - $var wire 8 I# in [7:0] $end - $var wire 8 J# out [7:0] $end + $var wire 1 g# clk $end + $var wire 8 j# in [7:0] $end + $var wire 8 k# out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end - $var wire 1 3$ clk $end - $var wire 8 4$ in [7:0] $end - $var wire 8 5$ out [7:0] $end + $var wire 1 T$ clk $end + $var wire 8 U$ in [7:0] $end + $var wire 8 V$ out [7:0] $end $scope module sub4_2 $end - $var wire 32 6$ P0 [31:0] $end - $var real 64 7$ P1 $end - $var real 64 9$ P3 $end - $var wire 1 3$ clk $end - $var wire 8 4$ in [7:0] $end - $var wire 8 5$ out [7:0] $end - $var wire 8 P# ff [7:0] $end - $var wire 128 Q# sub5_in[0][0] [127:0] $end - $var wire 128 U# sub5_in[0][1] [127:0] $end - $var wire 128 Y# sub5_in[0][2] [127:0] $end - $var wire 128 ]# sub5_in[1][0] [127:0] $end - $var wire 128 a# sub5_in[1][1] [127:0] $end - $var wire 128 e# sub5_in[1][2] [127:0] $end - $var wire 8 '$ sub5_out[0][0] [7:0] $end - $var wire 8 ($ sub5_out[0][1] [7:0] $end - $var wire 8 )$ sub5_out[0][2] [7:0] $end - $var wire 8 *$ sub5_out[1][0] [7:0] $end - $var wire 8 +$ sub5_out[1][1] [7:0] $end - $var wire 8 ,$ sub5_out[1][2] [7:0] $end - $var wire 32 i# count [31:0] $end + $var wire 32 W$ P0 [31:0] $end + $var real 64 X$ P1 $end + $var real 64 Z$ P3 $end + $var wire 1 T$ clk $end + $var wire 8 U$ in [7:0] $end + $var wire 8 V$ out [7:0] $end + $var wire 8 q# ff [7:0] $end + $var wire 128 r# sub5_in[0][0] [127:0] $end + $var wire 128 v# sub5_in[0][1] [127:0] $end + $var wire 128 z# sub5_in[0][2] [127:0] $end + $var wire 128 ~# sub5_in[1][0] [127:0] $end + $var wire 128 $$ sub5_in[1][1] [127:0] $end + $var wire 128 ($ sub5_in[1][2] [127:0] $end + $var wire 8 H$ sub5_out[0][0] [7:0] $end + $var wire 8 I$ sub5_out[0][1] [7:0] $end + $var wire 8 J$ sub5_out[0][2] [7:0] $end + $var wire 8 K$ sub5_out[1][0] [7:0] $end + $var wire 8 L$ sub5_out[1][1] [7:0] $end + $var wire 8 M$ sub5_out[1][2] [7:0] $end + $var wire 32 ,$ count [31:0] $end $scope module i_sub5 $end - $var wire 1 3$ clk $end - $var wire 128 m# in[0][0] [127:0] $end - $var wire 128 q# in[0][1] [127:0] $end - $var wire 128 u# in[0][2] [127:0] $end - $var wire 128 y# in[1][0] [127:0] $end - $var wire 128 }# in[1][1] [127:0] $end - $var wire 128 #$ in[1][2] [127:0] $end - $var wire 8 -$ out[0][0] [7:0] $end - $var wire 8 .$ out[0][1] [7:0] $end - $var wire 8 /$ out[0][2] [7:0] $end - $var wire 8 0$ out[1][0] [7:0] $end - $var wire 8 1$ out[1][1] [7:0] $end - $var wire 8 2$ out[1][2] [7:0] $end + $var wire 1 T$ clk $end + $var wire 128 0$ in[0][0] [127:0] $end + $var wire 128 4$ in[0][1] [127:0] $end + $var wire 128 8$ in[0][2] [127:0] $end + $var wire 128 <$ in[1][0] [127:0] $end + $var wire 128 @$ in[1][1] [127:0] $end + $var wire 128 D$ in[1][2] [127:0] $end + $var wire 8 N$ out[0][0] [7:0] $end + $var wire 8 O$ out[0][1] [7:0] $end + $var wire 8 P$ out[0][2] [7:0] $end + $var wire 8 Q$ out[1][0] [7:0] $end + $var wire 8 R$ out[1][1] [7:0] $end + $var wire 8 S$ out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 j# i [31:0] $end + $var wire 32 -$ i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 k# j [31:0] $end + $var wire 32 .$ j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 l# exp [7:0] $end + $var wire 8 /$ exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end - $var wire 1 M$ clk $end - $var wire 128 N$ in[0][0] [127:0] $end - $var wire 128 R$ in[0][1] [127:0] $end - $var wire 128 V$ in[0][2] [127:0] $end - $var wire 128 Z$ in[1][0] [127:0] $end - $var wire 128 ^$ in[1][1] [127:0] $end - $var wire 128 b$ in[1][2] [127:0] $end - $var wire 8 f$ out[0][0] [7:0] $end - $var wire 8 g$ out[0][1] [7:0] $end - $var wire 8 h$ out[0][2] [7:0] $end - $var wire 8 i$ out[1][0] [7:0] $end - $var wire 8 j$ out[1][1] [7:0] $end - $var wire 8 k$ out[1][2] [7:0] $end + $var wire 1 t$ clk $end + $var wire 128 u$ in[0][0] [127:0] $end + $var wire 128 y$ in[0][1] [127:0] $end + $var wire 128 }$ in[0][2] [127:0] $end + $var wire 128 #% in[1][0] [127:0] $end + $var wire 128 '% in[1][1] [127:0] $end + $var wire 128 +% in[1][2] [127:0] $end + $var wire 8 /% out[0][0] [7:0] $end + $var wire 8 0% out[0][1] [7:0] $end + $var wire 8 1% out[0][2] [7:0] $end + $var wire 8 2% out[1][0] [7:0] $end + $var wire 8 3% out[1][1] [7:0] $end + $var wire 8 4% out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 M$ clk $end - $var wire 128 N$ in[0][0] [127:0] $end - $var wire 128 R$ in[0][1] [127:0] $end - $var wire 128 V$ in[0][2] [127:0] $end - $var wire 128 Z$ in[1][0] [127:0] $end - $var wire 128 ^$ in[1][1] [127:0] $end - $var wire 128 b$ in[1][2] [127:0] $end - $var wire 8 f$ out[0][0] [7:0] $end - $var wire 8 g$ out[0][1] [7:0] $end - $var wire 8 h$ out[0][2] [7:0] $end - $var wire 8 i$ out[1][0] [7:0] $end - $var wire 8 j$ out[1][1] [7:0] $end - $var wire 8 k$ out[1][2] [7:0] $end - $var wire 32 F$ count [31:0] $end - $var wire 8 <$ val0[0] [7:0] $end - $var wire 8 =$ val0[1] [7:0] $end - $var wire 8 >$ val1[0] [7:0] $end - $var wire 8 ?$ val1[1] [7:0] $end - $var wire 8 @$ val2[0] [7:0] $end - $var wire 8 A$ val2[1] [7:0] $end - $var wire 8 B$ val3[0] [7:0] $end - $var wire 8 C$ val3[1] [7:0] $end + $var wire 1 t$ clk $end + $var wire 128 u$ in[0][0] [127:0] $end + $var wire 128 y$ in[0][1] [127:0] $end + $var wire 128 }$ in[0][2] [127:0] $end + $var wire 128 #% in[1][0] [127:0] $end + $var wire 128 '% in[1][1] [127:0] $end + $var wire 128 +% in[1][2] [127:0] $end + $var wire 8 /% out[0][0] [7:0] $end + $var wire 8 0% out[0][1] [7:0] $end + $var wire 8 1% out[0][2] [7:0] $end + $var wire 8 2% out[1][0] [7:0] $end + $var wire 8 3% out[1][1] [7:0] $end + $var wire 8 4% out[1][2] [7:0] $end + $var wire 32 m$ count [31:0] $end + $var wire 8 ]$ val0[0] [7:0] $end + $var wire 8 ^$ val0[1] [7:0] $end + $var wire 8 _$ val1[0] [7:0] $end + $var wire 8 `$ val1[1] [7:0] $end + $var wire 8 a$ val2[0] [7:0] $end + $var wire 8 b$ val2[1] [7:0] $end + $var wire 8 c$ val3[0] [7:0] $end + $var wire 8 d$ val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 l$ P0 [31:0] $end - $var wire 32 m$ P1 [31:0] $end - $var wire 8 <$ out[0] [7:0] $end - $var wire 8 =$ out[1] [7:0] $end + $var wire 8 e$ out[0] [7:0] $end + $var wire 8 f$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 l$ P0 [31:0] $end - $var wire 32 m$ P1 [31:0] $end - $var wire 8 >$ out[0] [7:0] $end - $var wire 8 ?$ out[1] [7:0] $end + $var wire 8 g$ out[0] [7:0] $end + $var wire 8 h$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 l$ P0 [31:0] $end - $var wire 32 m$ P1 [31:0] $end - $var wire 8 @$ out[0] [7:0] $end - $var wire 8 A$ out[1] [7:0] $end + $var wire 8 i$ out[0] [7:0] $end + $var wire 8 j$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 D$ out[0] [7:0] $end - $var wire 8 E$ out[1] [7:0] $end + $var wire 8 k$ out[0] [7:0] $end + $var wire 8 l$ out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 G$ i [31:0] $end + $var wire 32 n$ i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 H$ j [31:0] $end + $var wire 32 o$ j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 I$ exp [127:0] $end + $var wire 128 p$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end + $var wire 8 6% out[0] [7:0] $end + $var wire 8 7% out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 8% P0 [31:0] $end + $var wire 32 9% P1 [31:0] $end + $var wire 8 6% out[0] [7:0] $end + $var wire 8 7% out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end - $var wire 8 o$ out[0] [7:0] $end - $var wire 8 p$ out[1] [7:0] $end + $var wire 8 ;% out[0] [7:0] $end + $var wire 8 <% out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 q$ P0 [31:0] $end - $var wire 32 r$ P1 [31:0] $end - $var wire 8 o$ out[0] [7:0] $end - $var wire 8 p$ out[1] [7:0] $end + $var wire 32 =% P0 [31:0] $end + $var wire 32 >% P1 [31:0] $end + $var wire 8 ;% out[0] [7:0] $end + $var wire 8 <% out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end - $var wire 1 W% clk $end - $var wire 8 X% in [7:0] $end - $var wire 8 Y% out [7:0] $end + $var wire 1 #& clk $end + $var wire 8 $& in [7:0] $end + $var wire 8 %& out [7:0] $end $scope module sub4_b $end - $var wire 32 Z% P0 [31:0] $end - $var real 64 [% P1 $end - $var real 64 ]% P3 $end - $var wire 1 W% clk $end - $var wire 8 X% in [7:0] $end - $var wire 8 Y% out [7:0] $end - $var wire 8 t$ ff [7:0] $end - $var wire 128 u$ sub5_in[0][0] [127:0] $end - $var wire 128 y$ sub5_in[0][1] [127:0] $end - $var wire 128 }$ sub5_in[0][2] [127:0] $end - $var wire 128 #% sub5_in[1][0] [127:0] $end - $var wire 128 '% sub5_in[1][1] [127:0] $end - $var wire 128 +% sub5_in[1][2] [127:0] $end - $var wire 8 K% sub5_out[0][0] [7:0] $end - $var wire 8 L% sub5_out[0][1] [7:0] $end - $var wire 8 M% sub5_out[0][2] [7:0] $end - $var wire 8 N% sub5_out[1][0] [7:0] $end - $var wire 8 O% sub5_out[1][1] [7:0] $end - $var wire 8 P% sub5_out[1][2] [7:0] $end - $var wire 32 /% count [31:0] $end + $var wire 32 && P0 [31:0] $end + $var real 64 '& P1 $end + $var real 64 )& P3 $end + $var wire 1 #& clk $end + $var wire 8 $& in [7:0] $end + $var wire 8 %& out [7:0] $end + $var wire 8 @% ff [7:0] $end + $var wire 128 A% sub5_in[0][0] [127:0] $end + $var wire 128 E% sub5_in[0][1] [127:0] $end + $var wire 128 I% sub5_in[0][2] [127:0] $end + $var wire 128 M% sub5_in[1][0] [127:0] $end + $var wire 128 Q% sub5_in[1][1] [127:0] $end + $var wire 128 U% sub5_in[1][2] [127:0] $end + $var wire 8 u% sub5_out[0][0] [7:0] $end + $var wire 8 v% sub5_out[0][1] [7:0] $end + $var wire 8 w% sub5_out[0][2] [7:0] $end + $var wire 8 x% sub5_out[1][0] [7:0] $end + $var wire 8 y% sub5_out[1][1] [7:0] $end + $var wire 8 z% sub5_out[1][2] [7:0] $end + $var wire 32 Y% count [31:0] $end $scope module i_sub5 $end - $var wire 1 W% clk $end - $var wire 128 3% in[0][0] [127:0] $end - $var wire 128 7% in[0][1] [127:0] $end - $var wire 128 ;% in[0][2] [127:0] $end - $var wire 128 ?% in[1][0] [127:0] $end - $var wire 128 C% in[1][1] [127:0] $end - $var wire 128 G% in[1][2] [127:0] $end - $var wire 8 Q% out[0][0] [7:0] $end - $var wire 8 R% out[0][1] [7:0] $end - $var wire 8 S% out[0][2] [7:0] $end - $var wire 8 T% out[1][0] [7:0] $end - $var wire 8 U% out[1][1] [7:0] $end - $var wire 8 V% out[1][2] [7:0] $end + $var wire 1 #& clk $end + $var wire 128 ]% in[0][0] [127:0] $end + $var wire 128 a% in[0][1] [127:0] $end + $var wire 128 e% in[0][2] [127:0] $end + $var wire 128 i% in[1][0] [127:0] $end + $var wire 128 m% in[1][1] [127:0] $end + $var wire 128 q% in[1][2] [127:0] $end + $var wire 8 {% out[0][0] [7:0] $end + $var wire 8 |% out[0][1] [7:0] $end + $var wire 8 }% out[0][2] [7:0] $end + $var wire 8 ~% out[1][0] [7:0] $end + $var wire 8 !& out[1][1] [7:0] $end + $var wire 8 "& out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 0% i [31:0] $end + $var wire 32 Z% i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 1% j [31:0] $end + $var wire 32 [% j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 2% exp [7:0] $end + $var wire 8 \% exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end - $var wire 1 q% clk $end - $var wire 128 r% in[0][0] [127:0] $end - $var wire 128 v% in[0][1] [127:0] $end - $var wire 128 z% in[0][2] [127:0] $end - $var wire 128 ~% in[1][0] [127:0] $end - $var wire 128 $& in[1][1] [127:0] $end - $var wire 128 (& in[1][2] [127:0] $end - $var wire 8 ,& out[0][0] [7:0] $end - $var wire 8 -& out[0][1] [7:0] $end - $var wire 8 .& out[0][2] [7:0] $end - $var wire 8 /& out[1][0] [7:0] $end - $var wire 8 0& out[1][1] [7:0] $end - $var wire 8 1& out[1][2] [7:0] $end + $var wire 1 C& clk $end + $var wire 128 D& in[0][0] [127:0] $end + $var wire 128 H& in[0][1] [127:0] $end + $var wire 128 L& in[0][2] [127:0] $end + $var wire 128 P& in[1][0] [127:0] $end + $var wire 128 T& in[1][1] [127:0] $end + $var wire 128 X& in[1][2] [127:0] $end + $var wire 8 \& out[0][0] [7:0] $end + $var wire 8 ]& out[0][1] [7:0] $end + $var wire 8 ^& out[0][2] [7:0] $end + $var wire 8 _& out[1][0] [7:0] $end + $var wire 8 `& out[1][1] [7:0] $end + $var wire 8 a& out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 q% clk $end - $var wire 128 r% in[0][0] [127:0] $end - $var wire 128 v% in[0][1] [127:0] $end - $var wire 128 z% in[0][2] [127:0] $end - $var wire 128 ~% in[1][0] [127:0] $end - $var wire 128 $& in[1][1] [127:0] $end - $var wire 128 (& in[1][2] [127:0] $end - $var wire 8 ,& out[0][0] [7:0] $end - $var wire 8 -& out[0][1] [7:0] $end - $var wire 8 .& out[0][2] [7:0] $end - $var wire 8 /& out[1][0] [7:0] $end - $var wire 8 0& out[1][1] [7:0] $end - $var wire 8 1& out[1][2] [7:0] $end - $var wire 32 j% count [31:0] $end - $var wire 8 `% val0[0] [7:0] $end - $var wire 8 a% val0[1] [7:0] $end - $var wire 8 b% val1[0] [7:0] $end - $var wire 8 c% val1[1] [7:0] $end - $var wire 8 d% val2[0] [7:0] $end - $var wire 8 e% val2[1] [7:0] $end - $var wire 8 f% val3[0] [7:0] $end - $var wire 8 g% val3[1] [7:0] $end + $var wire 1 C& clk $end + $var wire 128 D& in[0][0] [127:0] $end + $var wire 128 H& in[0][1] [127:0] $end + $var wire 128 L& in[0][2] [127:0] $end + $var wire 128 P& in[1][0] [127:0] $end + $var wire 128 T& in[1][1] [127:0] $end + $var wire 128 X& in[1][2] [127:0] $end + $var wire 8 \& out[0][0] [7:0] $end + $var wire 8 ]& out[0][1] [7:0] $end + $var wire 8 ^& out[0][2] [7:0] $end + $var wire 8 _& out[1][0] [7:0] $end + $var wire 8 `& out[1][1] [7:0] $end + $var wire 8 a& out[1][2] [7:0] $end + $var wire 32 <& count [31:0] $end + $var wire 8 ,& val0[0] [7:0] $end + $var wire 8 -& val0[1] [7:0] $end + $var wire 8 .& val1[0] [7:0] $end + $var wire 8 /& val1[1] [7:0] $end + $var wire 8 0& val2[0] [7:0] $end + $var wire 8 1& val2[1] [7:0] $end + $var wire 8 2& val3[0] [7:0] $end + $var wire 8 3& val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 2& P0 [31:0] $end - $var wire 32 3& P1 [31:0] $end - $var wire 8 `% out[0] [7:0] $end - $var wire 8 a% out[1] [7:0] $end + $var wire 8 4& out[0] [7:0] $end + $var wire 8 5& out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 2& P0 [31:0] $end - $var wire 32 3& P1 [31:0] $end - $var wire 8 b% out[0] [7:0] $end - $var wire 8 c% out[1] [7:0] $end + $var wire 8 6& out[0] [7:0] $end + $var wire 8 7& out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 2& P0 [31:0] $end - $var wire 32 3& P1 [31:0] $end - $var wire 8 d% out[0] [7:0] $end - $var wire 8 e% out[1] [7:0] $end + $var wire 8 8& out[0] [7:0] $end + $var wire 8 9& out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 h% out[0] [7:0] $end - $var wire 8 i% out[1] [7:0] $end + $var wire 8 :& out[0] [7:0] $end + $var wire 8 ;& out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 k% i [31:0] $end + $var wire 32 =& i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 l% j [31:0] $end + $var wire 32 >& j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 m% exp [127:0] $end + $var wire 128 ?& exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end + $var wire 8 c& out[0] [7:0] $end + $var wire 8 d& out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 e& P0 [31:0] $end + $var wire 32 f& P1 [31:0] $end + $var wire 8 c& out[0] [7:0] $end + $var wire 8 d& out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end - $var wire 8 5& out[0] [7:0] $end - $var wire 8 6& out[1] [7:0] $end + $var wire 8 h& out[0] [7:0] $end + $var wire 8 i& out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 7& P0 [31:0] $end - $var wire 32 8& P1 [31:0] $end - $var wire 8 5& out[0] [7:0] $end - $var wire 8 6& out[1] [7:0] $end + $var wire 32 j& P0 [31:0] $end + $var wire 32 k& P1 [31:0] $end + $var wire 8 h& out[0] [7:0] $end + $var wire 8 i& out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3 $end - $var wire 1 :& clk $end - $var wire 8 ;& in [7:0] $end - $var wire 8 <& out [7:0] $end + $var wire 1 m& clk $end + $var wire 8 n& in [7:0] $end + $var wire 8 o& out [7:0] $end $scope module sub3_d $end - $var wire 8 ?& P0 [7:0] $end - $var wire 32 @& UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 A& UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 B& UNUSED [15:0] $end - $var wire 1 :& clk $end - $var wire 8 ;& in [7:0] $end - $var wire 8 <& out [7:0] $end - $var wire 8 =& ff [7:0] $end - $var wire 8 <& out4 [7:0] $end - $var wire 8 >& out4_2 [7:0] $end + $var wire 8 r& P0 [7:0] $end + $var wire 32 s& UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 t& UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 u& UNUSED [15:0] $end + $var wire 1 m& clk $end + $var wire 8 n& in [7:0] $end + $var wire 8 o& out [7:0] $end + $var wire 8 p& ff [7:0] $end + $var wire 8 o& out4 [7:0] $end + $var wire 8 q& out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 1 :& clk $end - $var wire 8 =& in [7:0] $end - $var wire 8 <& out [7:0] $end + $var wire 1 m& clk $end + $var wire 8 p& in [7:0] $end + $var wire 8 o& out [7:0] $end $upscope $end $scope module i_sub4_1 $end - $var wire 1 :& clk $end - $var wire 8 =& in [7:0] $end - $var wire 8 >& out [7:0] $end + $var wire 1 m& clk $end + $var wire 8 p& in [7:0] $end + $var wire 8 q& out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0 $end - $var wire 1 '' clk $end - $var wire 8 (' in [7:0] $end - $var wire 8 )' out [7:0] $end + $var wire 1 Z' clk $end + $var wire 8 [' in [7:0] $end + $var wire 8 \' out [7:0] $end $scope module sub4_2 $end - $var wire 32 *' P0 [31:0] $end - $var real 64 +' P1 $end - $var real 64 -' P3 $end - $var wire 1 '' clk $end - $var wire 8 (' in [7:0] $end - $var wire 8 )' out [7:0] $end - $var wire 8 D& ff [7:0] $end - $var wire 128 E& sub5_in[0][0] [127:0] $end - $var wire 128 I& sub5_in[0][1] [127:0] $end - $var wire 128 M& sub5_in[0][2] [127:0] $end - $var wire 128 Q& sub5_in[1][0] [127:0] $end - $var wire 128 U& sub5_in[1][1] [127:0] $end - $var wire 128 Y& sub5_in[1][2] [127:0] $end - $var wire 8 y& sub5_out[0][0] [7:0] $end - $var wire 8 z& sub5_out[0][1] [7:0] $end - $var wire 8 {& sub5_out[0][2] [7:0] $end - $var wire 8 |& sub5_out[1][0] [7:0] $end - $var wire 8 }& sub5_out[1][1] [7:0] $end - $var wire 8 ~& sub5_out[1][2] [7:0] $end - $var wire 32 ]& count [31:0] $end + $var wire 32 ]' P0 [31:0] $end + $var real 64 ^' P1 $end + $var real 64 `' P3 $end + $var wire 1 Z' clk $end + $var wire 8 [' in [7:0] $end + $var wire 8 \' out [7:0] $end + $var wire 8 w& ff [7:0] $end + $var wire 128 x& sub5_in[0][0] [127:0] $end + $var wire 128 |& sub5_in[0][1] [127:0] $end + $var wire 128 "' sub5_in[0][2] [127:0] $end + $var wire 128 &' sub5_in[1][0] [127:0] $end + $var wire 128 *' sub5_in[1][1] [127:0] $end + $var wire 128 .' sub5_in[1][2] [127:0] $end + $var wire 8 N' sub5_out[0][0] [7:0] $end + $var wire 8 O' sub5_out[0][1] [7:0] $end + $var wire 8 P' sub5_out[0][2] [7:0] $end + $var wire 8 Q' sub5_out[1][0] [7:0] $end + $var wire 8 R' sub5_out[1][1] [7:0] $end + $var wire 8 S' sub5_out[1][2] [7:0] $end + $var wire 32 2' count [31:0] $end $scope module i_sub5 $end - $var wire 1 '' clk $end - $var wire 128 a& in[0][0] [127:0] $end - $var wire 128 e& in[0][1] [127:0] $end - $var wire 128 i& in[0][2] [127:0] $end - $var wire 128 m& in[1][0] [127:0] $end - $var wire 128 q& in[1][1] [127:0] $end - $var wire 128 u& in[1][2] [127:0] $end - $var wire 8 !' out[0][0] [7:0] $end - $var wire 8 "' out[0][1] [7:0] $end - $var wire 8 #' out[0][2] [7:0] $end - $var wire 8 $' out[1][0] [7:0] $end - $var wire 8 %' out[1][1] [7:0] $end - $var wire 8 &' out[1][2] [7:0] $end + $var wire 1 Z' clk $end + $var wire 128 6' in[0][0] [127:0] $end + $var wire 128 :' in[0][1] [127:0] $end + $var wire 128 >' in[0][2] [127:0] $end + $var wire 128 B' in[1][0] [127:0] $end + $var wire 128 F' in[1][1] [127:0] $end + $var wire 128 J' in[1][2] [127:0] $end + $var wire 8 T' out[0][0] [7:0] $end + $var wire 8 U' out[0][1] [7:0] $end + $var wire 8 V' out[0][2] [7:0] $end + $var wire 8 W' out[1][0] [7:0] $end + $var wire 8 X' out[1][1] [7:0] $end + $var wire 8 Y' out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 ^& i [31:0] $end + $var wire 32 3' i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 _& j [31:0] $end + $var wire 32 4' j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 `& exp [7:0] $end + $var wire 8 5' exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end - $var wire 1 A' clk $end - $var wire 128 B' in[0][0] [127:0] $end - $var wire 128 F' in[0][1] [127:0] $end - $var wire 128 J' in[0][2] [127:0] $end - $var wire 128 N' in[1][0] [127:0] $end - $var wire 128 R' in[1][1] [127:0] $end - $var wire 128 V' in[1][2] [127:0] $end - $var wire 8 Z' out[0][0] [7:0] $end - $var wire 8 [' out[0][1] [7:0] $end - $var wire 8 \' out[0][2] [7:0] $end - $var wire 8 ]' out[1][0] [7:0] $end - $var wire 8 ^' out[1][1] [7:0] $end - $var wire 8 _' out[1][2] [7:0] $end + $var wire 1 z' clk $end + $var wire 128 {' in[0][0] [127:0] $end + $var wire 128 !( in[0][1] [127:0] $end + $var wire 128 %( in[0][2] [127:0] $end + $var wire 128 )( in[1][0] [127:0] $end + $var wire 128 -( in[1][1] [127:0] $end + $var wire 128 1( in[1][2] [127:0] $end + $var wire 8 5( out[0][0] [7:0] $end + $var wire 8 6( out[0][1] [7:0] $end + $var wire 8 7( out[0][2] [7:0] $end + $var wire 8 8( out[1][0] [7:0] $end + $var wire 8 9( out[1][1] [7:0] $end + $var wire 8 :( out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 A' clk $end - $var wire 128 B' in[0][0] [127:0] $end - $var wire 128 F' in[0][1] [127:0] $end - $var wire 128 J' in[0][2] [127:0] $end - $var wire 128 N' in[1][0] [127:0] $end - $var wire 128 R' in[1][1] [127:0] $end - $var wire 128 V' in[1][2] [127:0] $end - $var wire 8 Z' out[0][0] [7:0] $end - $var wire 8 [' out[0][1] [7:0] $end - $var wire 8 \' out[0][2] [7:0] $end - $var wire 8 ]' out[1][0] [7:0] $end - $var wire 8 ^' out[1][1] [7:0] $end - $var wire 8 _' out[1][2] [7:0] $end - $var wire 32 :' count [31:0] $end - $var wire 8 0' val0[0] [7:0] $end - $var wire 8 1' val0[1] [7:0] $end - $var wire 8 2' val1[0] [7:0] $end - $var wire 8 3' val1[1] [7:0] $end - $var wire 8 4' val2[0] [7:0] $end - $var wire 8 5' val2[1] [7:0] $end - $var wire 8 6' val3[0] [7:0] $end - $var wire 8 7' val3[1] [7:0] $end + $var wire 1 z' clk $end + $var wire 128 {' in[0][0] [127:0] $end + $var wire 128 !( in[0][1] [127:0] $end + $var wire 128 %( in[0][2] [127:0] $end + $var wire 128 )( in[1][0] [127:0] $end + $var wire 128 -( in[1][1] [127:0] $end + $var wire 128 1( in[1][2] [127:0] $end + $var wire 8 5( out[0][0] [7:0] $end + $var wire 8 6( out[0][1] [7:0] $end + $var wire 8 7( out[0][2] [7:0] $end + $var wire 8 8( out[1][0] [7:0] $end + $var wire 8 9( out[1][1] [7:0] $end + $var wire 8 :( out[1][2] [7:0] $end + $var wire 32 s' count [31:0] $end + $var wire 8 c' val0[0] [7:0] $end + $var wire 8 d' val0[1] [7:0] $end + $var wire 8 e' val1[0] [7:0] $end + $var wire 8 f' val1[1] [7:0] $end + $var wire 8 g' val2[0] [7:0] $end + $var wire 8 h' val2[1] [7:0] $end + $var wire 8 i' val3[0] [7:0] $end + $var wire 8 j' val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 `' P0 [31:0] $end - $var wire 32 a' P1 [31:0] $end - $var wire 8 0' out[0] [7:0] $end - $var wire 8 1' out[1] [7:0] $end + $var wire 8 k' out[0] [7:0] $end + $var wire 8 l' out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 `' P0 [31:0] $end - $var wire 32 a' P1 [31:0] $end - $var wire 8 2' out[0] [7:0] $end - $var wire 8 3' out[1] [7:0] $end + $var wire 8 m' out[0] [7:0] $end + $var wire 8 n' out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 `' P0 [31:0] $end - $var wire 32 a' P1 [31:0] $end - $var wire 8 4' out[0] [7:0] $end - $var wire 8 5' out[1] [7:0] $end + $var wire 8 o' out[0] [7:0] $end + $var wire 8 p' out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 8' out[0] [7:0] $end - $var wire 8 9' out[1] [7:0] $end + $var wire 8 q' out[0] [7:0] $end + $var wire 8 r' out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 ;' i [31:0] $end + $var wire 32 t' i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 <' j [31:0] $end + $var wire 32 u' j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 =' exp [127:0] $end + $var wire 128 v' exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end + $var wire 8 <( out[0] [7:0] $end + $var wire 8 =( out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 >( P0 [31:0] $end + $var wire 32 ?( P1 [31:0] $end + $var wire 8 <( out[0] [7:0] $end + $var wire 8 =( out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end - $var wire 8 c' out[0] [7:0] $end - $var wire 8 d' out[1] [7:0] $end + $var wire 8 A( out[0] [7:0] $end + $var wire 8 B( out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 e' P0 [31:0] $end - $var wire 32 f' P1 [31:0] $end - $var wire 8 c' out[0] [7:0] $end - $var wire 8 d' out[1] [7:0] $end + $var wire 32 C( P0 [31:0] $end + $var wire 32 D( P1 [31:0] $end + $var wire 8 A( out[0] [7:0] $end + $var wire 8 B( out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1 $end - $var wire 1 K( clk $end - $var wire 8 L( in [7:0] $end - $var wire 8 M( out [7:0] $end + $var wire 1 )) clk $end + $var wire 8 *) in [7:0] $end + $var wire 8 +) out [7:0] $end $scope module sub4_b $end - $var wire 32 N( P0 [31:0] $end - $var real 64 O( P1 $end - $var real 64 Q( P3 $end - $var wire 1 K( clk $end - $var wire 8 L( in [7:0] $end - $var wire 8 M( out [7:0] $end - $var wire 8 h' ff [7:0] $end - $var wire 128 i' sub5_in[0][0] [127:0] $end - $var wire 128 m' sub5_in[0][1] [127:0] $end - $var wire 128 q' sub5_in[0][2] [127:0] $end - $var wire 128 u' sub5_in[1][0] [127:0] $end - $var wire 128 y' sub5_in[1][1] [127:0] $end - $var wire 128 }' sub5_in[1][2] [127:0] $end - $var wire 8 ?( sub5_out[0][0] [7:0] $end - $var wire 8 @( sub5_out[0][1] [7:0] $end - $var wire 8 A( sub5_out[0][2] [7:0] $end - $var wire 8 B( sub5_out[1][0] [7:0] $end - $var wire 8 C( sub5_out[1][1] [7:0] $end - $var wire 8 D( sub5_out[1][2] [7:0] $end - $var wire 32 #( count [31:0] $end + $var wire 32 ,) P0 [31:0] $end + $var real 64 -) P1 $end + $var real 64 /) P3 $end + $var wire 1 )) clk $end + $var wire 8 *) in [7:0] $end + $var wire 8 +) out [7:0] $end + $var wire 8 F( ff [7:0] $end + $var wire 128 G( sub5_in[0][0] [127:0] $end + $var wire 128 K( sub5_in[0][1] [127:0] $end + $var wire 128 O( sub5_in[0][2] [127:0] $end + $var wire 128 S( sub5_in[1][0] [127:0] $end + $var wire 128 W( sub5_in[1][1] [127:0] $end + $var wire 128 [( sub5_in[1][2] [127:0] $end + $var wire 8 {( sub5_out[0][0] [7:0] $end + $var wire 8 |( sub5_out[0][1] [7:0] $end + $var wire 8 }( sub5_out[0][2] [7:0] $end + $var wire 8 ~( sub5_out[1][0] [7:0] $end + $var wire 8 !) sub5_out[1][1] [7:0] $end + $var wire 8 ") sub5_out[1][2] [7:0] $end + $var wire 32 _( count [31:0] $end $scope module i_sub5 $end - $var wire 1 K( clk $end - $var wire 128 '( in[0][0] [127:0] $end - $var wire 128 +( in[0][1] [127:0] $end - $var wire 128 /( in[0][2] [127:0] $end - $var wire 128 3( in[1][0] [127:0] $end - $var wire 128 7( in[1][1] [127:0] $end - $var wire 128 ;( in[1][2] [127:0] $end - $var wire 8 E( out[0][0] [7:0] $end - $var wire 8 F( out[0][1] [7:0] $end - $var wire 8 G( out[0][2] [7:0] $end - $var wire 8 H( out[1][0] [7:0] $end - $var wire 8 I( out[1][1] [7:0] $end - $var wire 8 J( out[1][2] [7:0] $end + $var wire 1 )) clk $end + $var wire 128 c( in[0][0] [127:0] $end + $var wire 128 g( in[0][1] [127:0] $end + $var wire 128 k( in[0][2] [127:0] $end + $var wire 128 o( in[1][0] [127:0] $end + $var wire 128 s( in[1][1] [127:0] $end + $var wire 128 w( in[1][2] [127:0] $end + $var wire 8 #) out[0][0] [7:0] $end + $var wire 8 $) out[0][1] [7:0] $end + $var wire 8 %) out[0][2] [7:0] $end + $var wire 8 &) out[1][0] [7:0] $end + $var wire 8 ') out[1][1] [7:0] $end + $var wire 8 () out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 $( i [31:0] $end + $var wire 32 `( i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 %( j [31:0] $end + $var wire 32 a( j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 &( exp [7:0] $end + $var wire 8 b( exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end - $var wire 1 e( clk $end - $var wire 128 f( in[0][0] [127:0] $end - $var wire 128 j( in[0][1] [127:0] $end - $var wire 128 n( in[0][2] [127:0] $end - $var wire 128 r( in[1][0] [127:0] $end - $var wire 128 v( in[1][1] [127:0] $end - $var wire 128 z( in[1][2] [127:0] $end - $var wire 8 ~( out[0][0] [7:0] $end - $var wire 8 !) out[0][1] [7:0] $end - $var wire 8 ") out[0][2] [7:0] $end - $var wire 8 #) out[1][0] [7:0] $end - $var wire 8 $) out[1][1] [7:0] $end - $var wire 8 %) out[1][2] [7:0] $end + $var wire 1 I) clk $end + $var wire 128 J) in[0][0] [127:0] $end + $var wire 128 N) in[0][1] [127:0] $end + $var wire 128 R) in[0][2] [127:0] $end + $var wire 128 V) in[1][0] [127:0] $end + $var wire 128 Z) in[1][1] [127:0] $end + $var wire 128 ^) in[1][2] [127:0] $end + $var wire 8 b) out[0][0] [7:0] $end + $var wire 8 c) out[0][1] [7:0] $end + $var wire 8 d) out[0][2] [7:0] $end + $var wire 8 e) out[1][0] [7:0] $end + $var wire 8 f) out[1][1] [7:0] $end + $var wire 8 g) out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 e( clk $end - $var wire 128 f( in[0][0] [127:0] $end - $var wire 128 j( in[0][1] [127:0] $end - $var wire 128 n( in[0][2] [127:0] $end - $var wire 128 r( in[1][0] [127:0] $end - $var wire 128 v( in[1][1] [127:0] $end - $var wire 128 z( in[1][2] [127:0] $end - $var wire 8 ~( out[0][0] [7:0] $end - $var wire 8 !) out[0][1] [7:0] $end - $var wire 8 ") out[0][2] [7:0] $end - $var wire 8 #) out[1][0] [7:0] $end - $var wire 8 $) out[1][1] [7:0] $end - $var wire 8 %) out[1][2] [7:0] $end - $var wire 32 ^( count [31:0] $end - $var wire 8 T( val0[0] [7:0] $end - $var wire 8 U( val0[1] [7:0] $end - $var wire 8 V( val1[0] [7:0] $end - $var wire 8 W( val1[1] [7:0] $end - $var wire 8 X( val2[0] [7:0] $end - $var wire 8 Y( val2[1] [7:0] $end - $var wire 8 Z( val3[0] [7:0] $end - $var wire 8 [( val3[1] [7:0] $end + $var wire 1 I) clk $end + $var wire 128 J) in[0][0] [127:0] $end + $var wire 128 N) in[0][1] [127:0] $end + $var wire 128 R) in[0][2] [127:0] $end + $var wire 128 V) in[1][0] [127:0] $end + $var wire 128 Z) in[1][1] [127:0] $end + $var wire 128 ^) in[1][2] [127:0] $end + $var wire 8 b) out[0][0] [7:0] $end + $var wire 8 c) out[0][1] [7:0] $end + $var wire 8 d) out[0][2] [7:0] $end + $var wire 8 e) out[1][0] [7:0] $end + $var wire 8 f) out[1][1] [7:0] $end + $var wire 8 g) out[1][2] [7:0] $end + $var wire 32 B) count [31:0] $end + $var wire 8 2) val0[0] [7:0] $end + $var wire 8 3) val0[1] [7:0] $end + $var wire 8 4) val1[0] [7:0] $end + $var wire 8 5) val1[1] [7:0] $end + $var wire 8 6) val2[0] [7:0] $end + $var wire 8 7) val2[1] [7:0] $end + $var wire 8 8) val3[0] [7:0] $end + $var wire 8 9) val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 &) P0 [31:0] $end - $var wire 32 ') P1 [31:0] $end - $var wire 8 T( out[0] [7:0] $end - $var wire 8 U( out[1] [7:0] $end + $var wire 8 :) out[0] [7:0] $end + $var wire 8 ;) out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 &) P0 [31:0] $end - $var wire 32 ') P1 [31:0] $end - $var wire 8 V( out[0] [7:0] $end - $var wire 8 W( out[1] [7:0] $end + $var wire 8 <) out[0] [7:0] $end + $var wire 8 =) out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 &) P0 [31:0] $end - $var wire 32 ') P1 [31:0] $end - $var wire 8 X( out[0] [7:0] $end - $var wire 8 Y( out[1] [7:0] $end + $var wire 8 >) out[0] [7:0] $end + $var wire 8 ?) out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 \( out[0] [7:0] $end - $var wire 8 ]( out[1] [7:0] $end + $var wire 8 @) out[0] [7:0] $end + $var wire 8 A) out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 _( i [31:0] $end + $var wire 32 C) i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 `( j [31:0] $end + $var wire 32 D) j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 a( exp [127:0] $end + $var wire 128 E) exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end + $var wire 8 i) out[0] [7:0] $end + $var wire 8 j) out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 k) P0 [31:0] $end + $var wire 32 l) P1 [31:0] $end + $var wire 8 i) out[0] [7:0] $end + $var wire 8 j) out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end - $var wire 8 )) out[0] [7:0] $end - $var wire 8 *) out[1] [7:0] $end + $var wire 8 n) out[0] [7:0] $end + $var wire 8 o) out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 +) P0 [31:0] $end - $var wire 32 ,) P1 [31:0] $end - $var wire 8 )) out[0] [7:0] $end - $var wire 8 *) out[1] [7:0] $end + $var wire 32 p) P0 [31:0] $end + $var wire 32 q) P1 [31:0] $end + $var wire 8 n) out[0] [7:0] $end + $var wire 8 o) out[1] [7:0] $end $upscope $end $upscope $end $enddefinitions $end @@ -1058,469 +1111,529 @@ b00000000000000000000000000000000 + b00000000 . b00000000 / b00000000 0 -b00000000 1 +04 +b00000000 5 b00000000 6 b00000000 7 -b00000000 8 -09 -b00000000 : -b00000000 ; -0A -b00000000 B +0; +b00000000 < +b00000000 = +b00000000 > +0B b00000000 C b00000000 D -0F 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--git a/test_regress/t/t_hier_block_sc_trace_vcd.pl b/test_regress/t/t_hier_block_sc_trace_vcd.pl index 52b2816a1..57b99c8dc 100755 --- a/test_regress/t/t_hier_block_sc_trace_vcd.pl +++ b/test_regress/t/t_hier_block_sc_trace_vcd.pl @@ -37,7 +37,7 @@ execute( file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 13); +file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); vcd_identical($Self->trace_filename, $Self->{golden_filename}); diff --git a/test_regress/t/t_hier_block_trace_fst.out b/test_regress/t/t_hier_block_trace_fst.out index 743c3853a..ed4dc4f56 100644 --- a/test_regress/t/t_hier_block_trace_fst.out +++ b/test_regress/t/t_hier_block_trace_fst.out @@ -1,5 +1,5 @@ $date - Mon Oct 23 12:13:57 2023 + Tue Oct 31 12:38:36 2023 $end $version @@ -75,1444 +75,1558 @@ $var wire 8 , out [7:0] $end $var logic 8 / tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end -$var parameter 32 0 N [31:0] $end -$var parameter 32 . WIDTH [31:0] $end $var wire 1 * clk $end $var wire 8 / in [7:0] $end $var wire 8 , out [7:0] $end -$var logic 8 1 tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_delay0.delay_2.genblk1.i_delay $end +$var wire 1 0 clk $end +$var wire 8 1 in [7:0] $end +$var wire 8 2 out [7:0] $end +$scope module delay_4 $end +$var parameter 32 3 N [31:0] $end +$var parameter 32 4 WIDTH [31:0] $end +$var wire 1 0 clk $end +$var wire 8 1 in [7:0] $end +$var wire 8 2 out [7:0] $end +$var logic 8 5 tmp [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_delay1 $end -$var wire 1 2 clk $end -$var wire 8 3 in [7:0] $end -$var wire 8 4 out [7:0] $end -$scope module delay_9 $end -$var parameter 32 5 N [31:0] $end -$var parameter 32 6 WIDTH [31:0] $end -$var wire 1 2 clk $end -$var wire 8 3 in [7:0] $end -$var wire 8 4 out [7:0] $end -$var logic 8 7 tmp [7:0] $end -$scope module genblk1 $end -$scope module i_delay $end -$var parameter 32 8 N [31:0] $end -$var parameter 32 6 WIDTH [31:0] $end -$var wire 1 2 clk $end +$var wire 1 6 clk $end $var wire 8 7 in [7:0] $end -$var wire 8 4 out [7:0] $end -$var logic 8 9 tmp [7:0] $end +$var wire 8 8 out [7:0] $end +$scope module delay_9 $end +$var parameter 32 9 N [31:0] $end +$var parameter 32 : WIDTH [31:0] $end +$var wire 1 6 clk $end +$var wire 8 7 in [7:0] $end +$var wire 8 8 out [7:0] $end +$var logic 8 ; tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end -$var parameter 32 : N [31:0] $end -$var parameter 32 6 WIDTH [31:0] $end -$var wire 1 2 clk $end -$var wire 8 9 in [7:0] $end -$var wire 8 4 out [7:0] $end -$var logic 8 ; tmp [7:0] $end +$var wire 1 6 clk $end +$var wire 8 ; in [7:0] $end +$var wire 8 8 out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_delay1.delay_9.genblk1.i_delay $end +$var wire 1 < clk $end +$var wire 8 = in [7:0] $end +$var wire 8 > out [7:0] $end +$scope module delay_2 $end +$var parameter 32 ? N [31:0] $end +$var parameter 32 @ WIDTH [31:0] $end +$var wire 1 < clk $end +$var wire 8 = in [7:0] $end +$var wire 8 > out [7:0] $end +$var logic 8 A tmp [7:0] $end +$scope module genblk1 $end +$scope module i_delay $end +$var wire 1 < clk $end +$var wire 8 A in [7:0] $end +$var wire 8 > out [7:0] $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module top.t.i_delay1.delay_9.genblk1.i_delay.delay_2.genblk1.i_delay $end +$var wire 1 B clk $end +$var wire 8 C in [7:0] $end +$var wire 8 D out [7:0] $end +$scope module delay_4 $end +$var parameter 32 E N [31:0] $end +$var parameter 32 F WIDTH [31:0] $end +$var wire 1 B clk $end +$var wire 8 C in [7:0] $end +$var wire 8 D out [7:0] $end +$var logic 8 G tmp [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub0.i_sub0 $end -$var wire 1 < clk $end -$var wire 8 = in [7:0] $end -$var wire 8 > out [7:0] $end +$var wire 1 H clk $end +$var wire 8 I in [7:0] $end +$var wire 8 J out [7:0] $end $scope module sub0 $end -$var wire 1 < clk $end -$var wire 8 = in [7:0] $end -$var wire 8 > out [7:0] $end -$var logic 8 ? ff [7:0] $end +$var wire 1 H clk $end +$var wire 8 I in [7:0] $end +$var wire 8 J out [7:0] $end +$var logic 8 K ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub1 $end -$var wire 1 @ clk $end -$var wire 8 A in [11:4] $end -$var wire 8 B out [7:0] $end +$var wire 1 L clk $end +$var wire 8 M in [11:4] $end +$var wire 8 N out [7:0] $end $scope module sub1 $end -$var wire 1 @ clk $end -$var wire 8 A in [11:4] $end -$var wire 8 B out [7:0] $end -$var logic 8 C ff [7:0] $end +$var wire 1 L clk $end +$var wire 8 M in [11:4] $end +$var wire 8 N out [7:0] $end +$var logic 8 O ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2 $end -$var wire 1 D clk $end -$var wire 8 E in [7:0] $end -$var wire 8 F out [7:0] $end +$var wire 1 P clk $end +$var wire 8 Q in [7:0] $end +$var wire 8 R out [7:0] $end $scope module sub2 $end -$var wire 1 D clk $end -$var wire 8 E in [7:0] $end -$var wire 8 F out [7:0] $end -$var logic 8 G ff [7:0] $end +$var wire 1 P clk $end +$var wire 8 Q in [7:0] $end +$var wire 8 R out [7:0] $end +$var logic 8 S ff [7:0] $end $scope interface in_ifs $end -$var wire 1 D clk $end -$var logic 8 G data [7:0] $end +$var wire 1 P clk $end +$var logic 8 S data [7:0] $end $upscope $end $scope interface out_ifs $end -$var wire 1 D clk $end -$var logic 8 H data [7:0] $end +$var wire 1 P clk $end +$var logic 8 T data [7:0] $end $upscope $end $scope module i_sub3 $end $scope interface in $end -$var wire 1 D clk $end -$var logic 8 G data [7:0] $end +$var wire 1 P clk $end +$var logic 8 S data [7:0] $end $upscope $end $scope interface out $end -$var wire 1 D clk $end -$var logic 8 H data [7:0] $end +$var wire 1 P clk $end +$var logic 8 T data [7:0] $end $upscope $end -$var wire 8 G in_wire [7:0] $end -$var wire 8 H out_1 [7:0] $end -$var wire 8 I out_2 [7:0] $end +$var wire 8 S in_wire [7:0] $end +$var wire 8 T out_1 [7:0] $end +$var wire 8 U out_2 [7:0] $end $scope module i_sub3 $end -$var wire 1 D clk $end -$var wire 8 G in [7:0] $end -$var wire 8 H out [7:0] $end +$var wire 1 P clk $end +$var wire 8 S in [7:0] $end +$var wire 8 T out [7:0] $end $upscope $end $scope module i_sub3_2 $end -$var wire 1 D clk $end -$var wire 8 G in [7:0] $end -$var wire 8 I out [7:0] $end +$var wire 1 P clk $end +$var wire 8 S in [7:0] $end +$var wire 8 U out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end -$var wire 1 J clk $end -$var wire 8 K in [7:0] $end -$var wire 8 L out [7:0] $end +$var wire 1 V clk $end +$var wire 8 W in [7:0] $end +$var wire 8 X out [7:0] $end $scope module sub3_c $end -$var parameter 8 M P0 [7:0] $end -$var parameter 32 N UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 O UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 P UNUSED [15:0] $end -$var wire 1 J clk $end -$var wire 8 K in [7:0] $end -$var wire 8 L out [7:0] $end -$var logic 8 Q ff [7:0] $end -$var wire 8 L out4 [7:0] $end -$var wire 8 R out4_2 [7:0] $end +$var parameter 8 Y P0 [7:0] $end +$var parameter 32 Z UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 [ UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 \ UNUSED [15:0] $end +$var wire 1 V clk $end +$var wire 8 W in [7:0] $end +$var wire 8 X out [7:0] $end +$var logic 8 ] ff [7:0] $end +$var wire 8 X out4 [7:0] $end +$var wire 8 ^ out4_2 [7:0] $end $scope module i_sub4_0 $end -$var wire 1 J clk $end -$var wire 8 Q in [7:0] $end -$var wire 8 L out [7:0] $end +$var wire 1 V clk $end +$var wire 8 ] in [7:0] $end +$var wire 8 X out [7:0] $end $upscope $end $scope module i_sub4_1 $end -$var wire 1 J clk $end -$var wire 8 Q in [7:0] $end -$var wire 8 R out [7:0] $end +$var wire 1 V clk $end +$var wire 8 ] in [7:0] $end +$var wire 8 ^ out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end -$var wire 1 S clk $end -$var wire 8 T in [7:0] $end -$var wire 8 U out [7:0] $end +$var wire 1 _ clk $end +$var wire 8 ` in [7:0] $end +$var wire 8 a out [7:0] $end $scope module sub4_2 $end -$var parameter 32 V P0 [31:0] $end -$var real_parameter 64 W P1 $end -$var real_parameter 64 X P3 $end -$var wire 1 S clk $end -$var wire 8 T in [7:0] $end -$var wire 8 U out [7:0] $end -$var logic 8 Y ff [7:0] $end -$var logic 128 Z sub5_in[0][0] [127:0] $end -$var logic 128 [ sub5_in[0][1] [127:0] $end -$var logic 128 \ sub5_in[0][2] [127:0] $end -$var logic 128 ] sub5_in[1][0] [127:0] $end -$var logic 128 ^ sub5_in[1][1] [127:0] $end -$var logic 128 _ sub5_in[1][2] [127:0] $end -$var wire 8 ` sub5_out[0][0] [7:0] $end -$var wire 8 a sub5_out[0][1] [7:0] $end -$var wire 8 b sub5_out[0][2] [7:0] $end -$var wire 8 c sub5_out[1][0] [7:0] $end -$var wire 8 d sub5_out[1][1] [7:0] $end -$var wire 8 e sub5_out[1][2] [7:0] $end -$var int 32 f count [31:0] $end +$var parameter 32 b P0 [31:0] $end +$var real_parameter 64 c P1 $end +$var real_parameter 64 d P3 $end +$var wire 1 _ clk $end +$var wire 8 ` in [7:0] $end +$var wire 8 a out [7:0] $end +$var logic 8 e ff [7:0] $end +$var logic 128 f sub5_in[0][0] [127:0] $end +$var logic 128 g sub5_in[0][1] [127:0] $end +$var logic 128 h sub5_in[0][2] [127:0] $end +$var logic 128 i sub5_in[1][0] [127:0] $end +$var logic 128 j sub5_in[1][1] [127:0] $end +$var logic 128 k sub5_in[1][2] [127:0] $end +$var wire 8 l sub5_out[0][0] [7:0] $end +$var wire 8 m sub5_out[0][1] [7:0] $end +$var wire 8 n sub5_out[0][2] [7:0] $end +$var wire 8 o sub5_out[1][0] [7:0] $end +$var wire 8 p sub5_out[1][1] [7:0] $end +$var wire 8 q sub5_out[1][2] [7:0] $end +$var int 32 r count [31:0] $end $scope module i_sub5 $end -$var wire 1 S clk $end -$var wire 128 g in[0][0] [127:0] $end -$var wire 128 h in[0][1] [127:0] $end -$var wire 128 i in[0][2] [127:0] $end -$var wire 128 j in[1][0] [127:0] $end -$var wire 128 k in[1][1] [127:0] $end -$var wire 128 l in[1][2] [127:0] $end -$var wire 8 m out[0][0] [7:0] $end -$var wire 8 n out[0][1] [7:0] $end -$var wire 8 o out[0][2] [7:0] $end -$var wire 8 p out[1][0] [7:0] $end -$var wire 8 q out[1][1] [7:0] $end -$var wire 8 r out[1][2] [7:0] $end +$var wire 1 _ clk $end +$var wire 128 s in[0][0] [127:0] $end +$var wire 128 t in[0][1] [127:0] $end +$var wire 128 u in[0][2] [127:0] $end +$var wire 128 v in[1][0] [127:0] $end +$var wire 128 w in[1][1] [127:0] $end +$var wire 128 x in[1][2] [127:0] $end +$var wire 8 y out[0][0] [7:0] $end +$var wire 8 z out[0][1] [7:0] $end +$var wire 8 { out[0][2] [7:0] $end +$var wire 8 | out[1][0] [7:0] $end +$var wire 8 } out[1][1] [7:0] $end +$var wire 8 ~ out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 s i [31:0] $end +$var int 32 !! i [31:0] $end $scope module unnamedblk2 $end -$var int 32 t j [31:0] $end +$var int 32 "! j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 u exp [7:0] $end +$var byte 8 #! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end -$var wire 1 v clk $end -$var wire 128 w in[0][0] [127:0] $end -$var wire 128 x in[0][1] [127:0] $end -$var wire 128 y in[0][2] [127:0] $end -$var wire 128 z in[1][0] [127:0] $end -$var wire 128 { in[1][1] [127:0] $end -$var wire 128 | in[1][2] [127:0] $end -$var wire 8 } out[0][0] [7:0] $end -$var wire 8 ~ out[0][1] [7:0] $end -$var wire 8 !! out[0][2] [7:0] $end -$var wire 8 "! out[1][0] [7:0] $end -$var wire 8 #! out[1][1] [7:0] $end -$var wire 8 $! out[1][2] [7:0] $end +$var wire 1 $! clk $end +$var wire 128 %! in[0][0] [127:0] $end +$var wire 128 &! in[0][1] [127:0] $end +$var wire 128 '! in[0][2] [127:0] $end +$var wire 128 (! in[1][0] [127:0] $end +$var wire 128 )! in[1][1] [127:0] $end +$var wire 128 *! in[1][2] [127:0] $end +$var wire 8 +! out[0][0] [7:0] $end +$var wire 8 ,! out[0][1] [7:0] $end +$var wire 8 -! out[0][2] [7:0] $end +$var wire 8 .! out[1][0] [7:0] $end +$var wire 8 /! out[1][1] [7:0] $end +$var wire 8 0! out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 v clk $end -$var wire 128 w in[0][0] [127:0] $end -$var wire 128 x in[0][1] [127:0] $end -$var wire 128 y in[0][2] [127:0] $end -$var wire 128 z in[1][0] [127:0] $end -$var wire 128 { in[1][1] [127:0] $end -$var wire 128 | in[1][2] [127:0] $end -$var wire 8 } out[0][0] [7:0] $end -$var wire 8 ~ out[0][1] [7:0] $end -$var wire 8 !! out[0][2] [7:0] $end -$var wire 8 "! out[1][0] [7:0] $end -$var wire 8 #! out[1][1] [7:0] $end -$var wire 8 $! out[1][2] [7:0] $end -$var int 32 %! count [31:0] $end -$var wire 8 &! val0[0] [7:0] $end -$var wire 8 '! val0[1] [7:0] $end -$var wire 8 (! val1[0] [7:0] $end -$var wire 8 )! val1[1] [7:0] $end -$var wire 8 *! val2[0] [7:0] $end -$var wire 8 +! val2[1] [7:0] $end -$var wire 8 ,! val3[0] [7:0] $end -$var wire 8 -! val3[1] [7:0] $end +$var wire 1 $! clk $end +$var wire 128 %! in[0][0] [127:0] $end +$var wire 128 &! in[0][1] [127:0] $end +$var wire 128 '! in[0][2] [127:0] $end +$var wire 128 (! in[1][0] [127:0] $end +$var wire 128 )! in[1][1] [127:0] $end +$var wire 128 *! in[1][2] [127:0] $end +$var wire 8 +! out[0][0] [7:0] $end +$var wire 8 ,! out[0][1] [7:0] $end +$var wire 8 -! out[0][2] [7:0] $end +$var wire 8 .! out[1][0] [7:0] $end +$var wire 8 /! out[1][1] [7:0] $end +$var wire 8 0! out[1][2] [7:0] $end +$var int 32 1! count [31:0] $end +$var wire 8 2! val0[0] [7:0] $end +$var wire 8 3! val0[1] [7:0] $end +$var wire 8 4! val1[0] [7:0] $end +$var wire 8 5! val1[1] [7:0] $end +$var wire 8 6! val2[0] [7:0] $end +$var wire 8 7! val2[1] [7:0] $end +$var wire 8 8! val3[0] [7:0] $end +$var wire 8 9! val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 .! P0 [31:0] $end -$var parameter 32 /! P1 [31:0] $end -$var wire 8 &! out[0] [7:0] $end -$var wire 8 '! out[1] [7:0] $end +$var wire 8 :! out[0] [7:0] $end +$var wire 8 ;! out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 .! P0 [31:0] $end -$var parameter 32 /! P1 [31:0] $end -$var wire 8 (! out[0] [7:0] $end -$var wire 8 )! out[1] [7:0] $end +$var wire 8 ! out[0] [7:0] $end +$var wire 8 ?! out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 0! out[0] [7:0] $end -$var wire 8 1! out[1] [7:0] $end +$var wire 8 @! out[0] [7:0] $end +$var wire 8 A! out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 2! i [31:0] $end +$var int 32 B! i [31:0] $end $scope module unnamedblk2 $end -$var int 32 3! j [31:0] $end +$var int 32 C! j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 4! exp [127:0] $end +$var bit 128 D! exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end +$var wire 8 E! out[0] [7:0] $end +$var wire 8 F! out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 G! P0 [31:0] $end +$var parameter 32 H! P1 [31:0] $end +$var wire 8 E! out[0] [7:0] $end +$var wire 8 F! out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end -$var wire 8 5! out[0] [7:0] $end -$var wire 8 6! out[1] [7:0] $end +$var wire 8 I! out[0] [7:0] $end +$var wire 8 J! out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 7! P0 [31:0] $end -$var parameter 32 8! P1 [31:0] $end -$var wire 8 5! out[0] [7:0] $end -$var wire 8 6! out[1] [7:0] $end +$var parameter 32 K! P0 [31:0] $end +$var parameter 32 L! P1 [31:0] $end +$var wire 8 I! out[0] [7:0] $end +$var wire 8 J! out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end -$var wire 1 9! clk $end -$var wire 8 :! in [7:0] $end -$var wire 8 ;! out [7:0] $end +$var wire 1 M! clk $end +$var wire 8 N! in [7:0] $end +$var wire 8 O! out [7:0] $end $scope module sub4_b $end -$var parameter 32 ! P3 $end -$var wire 1 9! clk $end -$var wire 8 :! in [7:0] $end -$var wire 8 ;! out [7:0] $end -$var logic 8 ?! ff [7:0] $end -$var logic 128 @! sub5_in[0][0] [127:0] $end -$var logic 128 A! sub5_in[0][1] [127:0] $end -$var logic 128 B! sub5_in[0][2] [127:0] $end -$var logic 128 C! sub5_in[1][0] [127:0] $end -$var logic 128 D! sub5_in[1][1] [127:0] $end -$var logic 128 E! sub5_in[1][2] [127:0] $end -$var wire 8 F! sub5_out[0][0] [7:0] $end -$var wire 8 G! sub5_out[0][1] [7:0] $end -$var wire 8 H! sub5_out[0][2] [7:0] $end -$var wire 8 I! sub5_out[1][0] [7:0] $end -$var wire 8 J! sub5_out[1][1] [7:0] $end -$var wire 8 K! sub5_out[1][2] [7:0] $end -$var int 32 L! count [31:0] $end +$var parameter 32 P! P0 [31:0] $end +$var real_parameter 64 Q! P1 $end +$var real_parameter 64 R! P3 $end +$var wire 1 M! clk $end +$var wire 8 N! in [7:0] $end +$var wire 8 O! out [7:0] $end +$var logic 8 S! ff [7:0] $end +$var logic 128 T! sub5_in[0][0] [127:0] $end +$var logic 128 U! sub5_in[0][1] [127:0] $end +$var logic 128 V! sub5_in[0][2] [127:0] $end +$var logic 128 W! sub5_in[1][0] [127:0] $end +$var logic 128 X! sub5_in[1][1] [127:0] $end +$var logic 128 Y! sub5_in[1][2] [127:0] $end +$var wire 8 Z! sub5_out[0][0] [7:0] $end +$var wire 8 [! sub5_out[0][1] [7:0] $end +$var wire 8 \! sub5_out[0][2] [7:0] $end +$var wire 8 ]! sub5_out[1][0] [7:0] $end +$var wire 8 ^! sub5_out[1][1] [7:0] $end +$var wire 8 _! sub5_out[1][2] [7:0] $end +$var int 32 `! count [31:0] $end $scope module i_sub5 $end -$var wire 1 9! clk $end -$var wire 128 M! in[0][0] [127:0] $end -$var wire 128 N! in[0][1] [127:0] $end -$var wire 128 O! in[0][2] [127:0] $end -$var wire 128 P! in[1][0] [127:0] $end -$var wire 128 Q! in[1][1] [127:0] $end -$var wire 128 R! in[1][2] [127:0] $end -$var wire 8 S! out[0][0] [7:0] $end -$var wire 8 T! out[0][1] [7:0] $end -$var wire 8 U! out[0][2] [7:0] $end -$var wire 8 V! out[1][0] [7:0] $end -$var wire 8 W! out[1][1] [7:0] $end -$var wire 8 X! out[1][2] [7:0] $end +$var wire 1 M! clk $end +$var wire 128 a! in[0][0] [127:0] $end +$var wire 128 b! in[0][1] [127:0] $end +$var wire 128 c! in[0][2] [127:0] $end +$var wire 128 d! in[1][0] [127:0] $end +$var wire 128 e! in[1][1] [127:0] $end +$var wire 128 f! in[1][2] [127:0] $end +$var wire 8 g! out[0][0] [7:0] $end +$var wire 8 h! out[0][1] [7:0] $end +$var wire 8 i! out[0][2] [7:0] $end +$var wire 8 j! out[1][0] [7:0] $end +$var wire 8 k! out[1][1] [7:0] $end +$var wire 8 l! out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 Y! i [31:0] $end +$var int 32 m! i [31:0] $end $scope module unnamedblk2 $end -$var int 32 Z! j [31:0] $end +$var int 32 n! j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 [! exp [7:0] $end +$var byte 8 o! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end -$var wire 1 \! clk $end -$var wire 128 ]! in[0][0] [127:0] $end -$var wire 128 ^! in[0][1] [127:0] $end -$var wire 128 _! in[0][2] [127:0] $end -$var wire 128 `! in[1][0] [127:0] $end -$var wire 128 a! in[1][1] [127:0] $end -$var wire 128 b! in[1][2] [127:0] $end -$var wire 8 c! out[0][0] [7:0] $end -$var wire 8 d! out[0][1] [7:0] $end -$var wire 8 e! out[0][2] [7:0] $end -$var wire 8 f! out[1][0] [7:0] $end -$var wire 8 g! out[1][1] [7:0] $end -$var wire 8 h! out[1][2] [7:0] $end +$var wire 1 p! clk $end +$var wire 128 q! in[0][0] [127:0] $end +$var wire 128 r! in[0][1] [127:0] $end +$var wire 128 s! in[0][2] [127:0] $end +$var wire 128 t! in[1][0] [127:0] $end +$var wire 128 u! in[1][1] [127:0] $end +$var wire 128 v! in[1][2] [127:0] $end +$var wire 8 w! out[0][0] [7:0] $end +$var wire 8 x! out[0][1] [7:0] $end +$var wire 8 y! out[0][2] [7:0] $end +$var wire 8 z! out[1][0] [7:0] $end +$var wire 8 {! out[1][1] [7:0] $end +$var wire 8 |! out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 \! clk $end -$var wire 128 ]! in[0][0] [127:0] $end -$var wire 128 ^! in[0][1] [127:0] $end -$var wire 128 _! in[0][2] [127:0] $end -$var wire 128 `! in[1][0] [127:0] $end -$var wire 128 a! in[1][1] [127:0] $end -$var wire 128 b! in[1][2] [127:0] $end -$var wire 8 c! out[0][0] [7:0] $end -$var wire 8 d! out[0][1] [7:0] $end -$var wire 8 e! out[0][2] [7:0] $end -$var wire 8 f! out[1][0] [7:0] $end -$var wire 8 g! out[1][1] [7:0] $end -$var wire 8 h! out[1][2] [7:0] $end -$var int 32 i! count [31:0] $end -$var wire 8 j! val0[0] [7:0] $end -$var wire 8 k! val0[1] [7:0] $end -$var wire 8 l! val1[0] [7:0] $end -$var wire 8 m! val1[1] [7:0] $end -$var wire 8 n! val2[0] [7:0] $end -$var wire 8 o! val2[1] [7:0] $end -$var wire 8 p! val3[0] [7:0] $end -$var wire 8 q! val3[1] [7:0] $end +$var wire 1 p! clk $end +$var wire 128 q! in[0][0] [127:0] $end +$var wire 128 r! in[0][1] [127:0] $end +$var wire 128 s! in[0][2] [127:0] $end +$var wire 128 t! in[1][0] [127:0] $end +$var wire 128 u! in[1][1] [127:0] $end +$var wire 128 v! in[1][2] [127:0] $end +$var wire 8 w! out[0][0] [7:0] $end +$var wire 8 x! out[0][1] [7:0] $end +$var wire 8 y! out[0][2] [7:0] $end +$var wire 8 z! out[1][0] [7:0] $end +$var wire 8 {! out[1][1] [7:0] $end +$var wire 8 |! out[1][2] [7:0] $end +$var int 32 }! count [31:0] $end +$var wire 8 ~! val0[0] [7:0] $end +$var wire 8 !" val0[1] [7:0] $end +$var wire 8 "" val1[0] [7:0] $end +$var wire 8 #" val1[1] [7:0] $end +$var wire 8 $" val2[0] [7:0] $end +$var wire 8 %" val2[1] [7:0] $end +$var wire 8 &" val3[0] [7:0] $end +$var wire 8 '" val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 r! P0 [31:0] $end -$var parameter 32 s! P1 [31:0] $end -$var wire 8 j! out[0] [7:0] $end -$var wire 8 k! out[1] [7:0] $end +$var wire 8 (" out[0] [7:0] $end +$var wire 8 )" out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 r! P0 [31:0] $end -$var parameter 32 s! P1 [31:0] $end -$var wire 8 l! out[0] [7:0] $end -$var wire 8 m! out[1] [7:0] $end +$var wire 8 *" out[0] [7:0] $end +$var wire 8 +" out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 r! P0 [31:0] $end -$var parameter 32 s! P1 [31:0] $end -$var wire 8 n! out[0] [7:0] $end -$var wire 8 o! out[1] [7:0] $end +$var wire 8 ," out[0] [7:0] $end +$var wire 8 -" out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 t! out[0] [7:0] $end -$var wire 8 u! out[1] [7:0] $end +$var wire 8 ." out[0] [7:0] $end +$var wire 8 /" out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 v! i [31:0] $end +$var int 32 0" i [31:0] $end $scope module unnamedblk2 $end -$var int 32 w! j [31:0] $end +$var int 32 1" j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 x! exp [127:0] $end +$var bit 128 2" exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end +$var wire 8 3" out[0] [7:0] $end +$var wire 8 4" out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 5" P0 [31:0] $end +$var parameter 32 6" P1 [31:0] $end +$var wire 8 3" out[0] [7:0] $end +$var wire 8 4" out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end -$var wire 8 y! out[0] [7:0] $end -$var wire 8 z! out[1] [7:0] $end +$var wire 8 7" out[0] [7:0] $end +$var wire 8 8" out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 {! P0 [31:0] $end -$var parameter 32 |! P1 [31:0] $end -$var wire 8 y! out[0] [7:0] $end -$var wire 8 z! out[1] [7:0] $end +$var parameter 32 9" P0 [31:0] $end +$var parameter 32 :" P1 [31:0] $end +$var wire 8 7" out[0] [7:0] $end +$var wire 8 8" out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3_2 $end -$var wire 1 }! clk $end -$var wire 8 ~! in [7:0] $end -$var wire 8 !" out [7:0] $end +$var wire 1 ;" clk $end +$var wire 8 <" in [7:0] $end +$var wire 8 =" out [7:0] $end $scope module sub3_2 $end -$var parameter 8 "" P0 [7:0] $end -$var parameter 32 #" UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 $" UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 %" UNUSED [15:0] $end -$var wire 1 }! clk $end -$var wire 8 ~! in [7:0] $end -$var wire 8 !" out [7:0] $end -$var logic 8 &" ff [7:0] $end -$var wire 8 !" out4 [7:0] $end -$var wire 8 '" out4_2 [7:0] $end +$var parameter 8 >" P0 [7:0] $end +$var parameter 32 ?" UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 @" UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 A" UNUSED [15:0] $end +$var wire 1 ;" clk $end +$var wire 8 <" in [7:0] $end +$var wire 8 =" out [7:0] $end +$var logic 8 B" ff [7:0] $end +$var wire 8 =" out4 [7:0] $end +$var wire 8 C" out4_2 [7:0] $end $scope module i_sub4_0 $end -$var wire 1 }! clk $end -$var wire 8 &" in [7:0] $end -$var wire 8 !" out [7:0] $end +$var wire 1 ;" clk $end +$var wire 8 B" in [7:0] $end +$var wire 8 =" out [7:0] $end $upscope $end $scope module i_sub4_1 $end -$var wire 1 }! clk $end -$var wire 8 &" in [7:0] $end -$var wire 8 '" out [7:0] $end +$var wire 1 ;" clk $end +$var wire 8 B" in [7:0] $end +$var wire 8 C" out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end -$var wire 1 (" clk $end -$var wire 8 )" in [7:0] $end -$var wire 8 *" out [7:0] $end +$var wire 1 D" clk $end +$var wire 8 E" in [7:0] $end +$var wire 8 F" out [7:0] $end $scope module sub4_2 $end -$var parameter 32 +" P0 [31:0] $end -$var real_parameter 64 ," P1 $end -$var real_parameter 64 -" P3 $end -$var wire 1 (" clk $end -$var wire 8 )" in [7:0] $end -$var wire 8 *" out [7:0] $end -$var logic 8 ." ff [7:0] $end -$var logic 128 /" sub5_in[0][0] [127:0] $end -$var logic 128 0" sub5_in[0][1] [127:0] $end -$var logic 128 1" sub5_in[0][2] [127:0] $end -$var logic 128 2" sub5_in[1][0] [127:0] $end -$var logic 128 3" sub5_in[1][1] [127:0] $end -$var logic 128 4" sub5_in[1][2] [127:0] $end -$var wire 8 5" sub5_out[0][0] [7:0] $end -$var wire 8 6" sub5_out[0][1] [7:0] $end -$var wire 8 7" sub5_out[0][2] [7:0] $end -$var wire 8 8" sub5_out[1][0] [7:0] $end -$var wire 8 9" sub5_out[1][1] [7:0] $end -$var wire 8 :" sub5_out[1][2] [7:0] $end -$var int 32 ;" count [31:0] $end +$var parameter 32 G" P0 [31:0] $end +$var real_parameter 64 H" P1 $end +$var real_parameter 64 I" P3 $end +$var wire 1 D" clk $end +$var wire 8 E" in [7:0] $end +$var wire 8 F" out [7:0] $end +$var logic 8 J" ff [7:0] $end +$var logic 128 K" sub5_in[0][0] [127:0] $end +$var logic 128 L" sub5_in[0][1] [127:0] $end +$var logic 128 M" sub5_in[0][2] [127:0] $end +$var logic 128 N" sub5_in[1][0] [127:0] $end +$var logic 128 O" sub5_in[1][1] [127:0] $end +$var logic 128 P" sub5_in[1][2] [127:0] $end +$var wire 8 Q" sub5_out[0][0] [7:0] $end +$var wire 8 R" sub5_out[0][1] [7:0] $end +$var wire 8 S" sub5_out[0][2] [7:0] $end +$var wire 8 T" sub5_out[1][0] [7:0] $end +$var wire 8 U" sub5_out[1][1] [7:0] $end +$var wire 8 V" sub5_out[1][2] [7:0] $end +$var int 32 W" count [31:0] $end $scope module i_sub5 $end -$var wire 1 (" clk $end -$var wire 128 <" in[0][0] [127:0] $end -$var wire 128 =" in[0][1] [127:0] $end -$var wire 128 >" in[0][2] [127:0] $end -$var wire 128 ?" in[1][0] [127:0] $end -$var wire 128 @" in[1][1] [127:0] $end -$var wire 128 A" in[1][2] [127:0] $end -$var wire 8 B" out[0][0] [7:0] $end -$var wire 8 C" out[0][1] [7:0] $end -$var wire 8 D" out[0][2] [7:0] $end -$var wire 8 E" out[1][0] [7:0] $end -$var wire 8 F" out[1][1] [7:0] $end -$var wire 8 G" out[1][2] [7:0] $end +$var wire 1 D" clk $end +$var wire 128 X" in[0][0] [127:0] $end +$var wire 128 Y" in[0][1] [127:0] $end +$var wire 128 Z" in[0][2] [127:0] $end +$var wire 128 [" in[1][0] [127:0] $end +$var wire 128 \" in[1][1] [127:0] $end +$var wire 128 ]" in[1][2] [127:0] $end +$var wire 8 ^" out[0][0] [7:0] $end +$var wire 8 _" out[0][1] [7:0] $end +$var wire 8 `" out[0][2] [7:0] $end +$var wire 8 a" out[1][0] [7:0] $end +$var wire 8 b" out[1][1] [7:0] $end +$var wire 8 c" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 H" i [31:0] $end +$var int 32 d" i [31:0] $end $scope module unnamedblk2 $end -$var int 32 I" j [31:0] $end +$var int 32 e" j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 J" exp [7:0] $end +$var byte 8 f" exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end -$var wire 1 K" clk $end -$var wire 128 L" in[0][0] [127:0] $end -$var wire 128 M" in[0][1] [127:0] $end -$var wire 128 N" in[0][2] [127:0] $end -$var wire 128 O" in[1][0] [127:0] $end -$var wire 128 P" in[1][1] [127:0] $end -$var wire 128 Q" in[1][2] [127:0] $end -$var wire 8 R" out[0][0] [7:0] $end -$var wire 8 S" out[0][1] [7:0] $end -$var wire 8 T" out[0][2] [7:0] $end -$var wire 8 U" out[1][0] [7:0] $end -$var wire 8 V" out[1][1] [7:0] $end -$var wire 8 W" out[1][2] [7:0] $end +$var wire 1 g" clk $end +$var wire 128 h" in[0][0] [127:0] $end +$var wire 128 i" in[0][1] [127:0] $end +$var wire 128 j" in[0][2] [127:0] $end +$var wire 128 k" in[1][0] [127:0] $end +$var wire 128 l" in[1][1] [127:0] $end +$var wire 128 m" in[1][2] [127:0] $end +$var wire 8 n" out[0][0] [7:0] $end +$var wire 8 o" out[0][1] [7:0] $end +$var wire 8 p" out[0][2] [7:0] $end +$var wire 8 q" out[1][0] [7:0] $end +$var wire 8 r" out[1][1] [7:0] $end +$var wire 8 s" out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 K" clk $end -$var wire 128 L" in[0][0] [127:0] $end -$var wire 128 M" in[0][1] [127:0] $end -$var wire 128 N" in[0][2] [127:0] $end -$var wire 128 O" in[1][0] [127:0] $end -$var wire 128 P" in[1][1] [127:0] $end -$var wire 128 Q" in[1][2] [127:0] $end -$var wire 8 R" out[0][0] [7:0] $end -$var wire 8 S" out[0][1] [7:0] $end -$var wire 8 T" out[0][2] [7:0] $end -$var wire 8 U" out[1][0] [7:0] $end -$var wire 8 V" out[1][1] [7:0] $end -$var wire 8 W" out[1][2] [7:0] $end -$var int 32 X" count [31:0] $end -$var wire 8 Y" val0[0] [7:0] $end -$var wire 8 Z" val0[1] [7:0] $end -$var wire 8 [" val1[0] [7:0] $end -$var wire 8 \" val1[1] [7:0] $end -$var wire 8 ]" val2[0] [7:0] $end -$var wire 8 ^" val2[1] [7:0] $end -$var wire 8 _" val3[0] [7:0] $end -$var wire 8 `" val3[1] [7:0] $end +$var wire 1 g" clk $end +$var wire 128 h" in[0][0] [127:0] $end +$var wire 128 i" in[0][1] [127:0] $end +$var wire 128 j" in[0][2] [127:0] $end +$var wire 128 k" in[1][0] [127:0] $end +$var wire 128 l" in[1][1] [127:0] $end +$var wire 128 m" in[1][2] [127:0] $end +$var wire 8 n" out[0][0] [7:0] $end +$var wire 8 o" out[0][1] [7:0] $end +$var wire 8 p" out[0][2] [7:0] $end +$var wire 8 q" out[1][0] [7:0] $end +$var wire 8 r" out[1][1] [7:0] $end +$var wire 8 s" out[1][2] [7:0] $end +$var int 32 t" count [31:0] $end +$var wire 8 u" val0[0] [7:0] $end +$var wire 8 v" val0[1] [7:0] $end +$var wire 8 w" val1[0] [7:0] $end +$var wire 8 x" val1[1] [7:0] $end +$var wire 8 y" val2[0] [7:0] $end +$var wire 8 z" val2[1] [7:0] $end +$var wire 8 {" val3[0] [7:0] $end +$var wire 8 |" val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 a" P0 [31:0] $end -$var parameter 32 b" P1 [31:0] $end -$var wire 8 Y" out[0] [7:0] $end -$var wire 8 Z" out[1] [7:0] $end +$var wire 8 }" out[0] [7:0] $end +$var wire 8 ~" out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 a" P0 [31:0] $end -$var parameter 32 b" P1 [31:0] $end -$var wire 8 [" out[0] [7:0] $end -$var wire 8 \" out[1] [7:0] $end +$var wire 8 !# out[0] [7:0] $end +$var wire 8 "# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 a" P0 [31:0] $end -$var parameter 32 b" P1 [31:0] $end -$var wire 8 ]" out[0] [7:0] $end -$var wire 8 ^" out[1] [7:0] $end +$var wire 8 ## out[0] [7:0] $end +$var wire 8 $# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 c" out[0] [7:0] $end -$var wire 8 d" out[1] [7:0] $end +$var wire 8 %# out[0] [7:0] $end +$var wire 8 &# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 e" i [31:0] $end +$var int 32 '# i [31:0] $end $scope module unnamedblk2 $end -$var int 32 f" j [31:0] $end +$var int 32 (# j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 g" exp [127:0] $end +$var bit 128 )# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end +$var wire 8 *# out[0] [7:0] $end +$var wire 8 +# out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 ,# P0 [31:0] $end +$var parameter 32 -# P1 [31:0] $end +$var wire 8 *# out[0] [7:0] $end +$var wire 8 +# out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end -$var wire 8 h" out[0] [7:0] $end -$var wire 8 i" out[1] [7:0] $end +$var wire 8 .# out[0] [7:0] $end +$var wire 8 /# out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 j" P0 [31:0] $end -$var parameter 32 k" P1 [31:0] $end -$var wire 8 h" out[0] [7:0] $end -$var wire 8 i" out[1] [7:0] $end +$var parameter 32 0# P0 [31:0] $end +$var parameter 32 1# P1 [31:0] $end +$var wire 8 .# out[0] [7:0] $end +$var wire 8 /# out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end -$var wire 1 l" clk $end -$var wire 8 m" in [7:0] $end -$var wire 8 n" out [7:0] $end +$var wire 1 2# clk $end +$var wire 8 3# in [7:0] $end +$var wire 8 4# out [7:0] $end $scope module sub4_b $end -$var parameter 32 o" P0 [31:0] $end -$var real_parameter 64 p" P1 $end -$var real_parameter 64 q" P3 $end -$var wire 1 l" clk $end -$var wire 8 m" in [7:0] $end -$var wire 8 n" out [7:0] $end -$var logic 8 r" ff [7:0] $end -$var logic 128 s" sub5_in[0][0] [127:0] $end -$var logic 128 t" sub5_in[0][1] [127:0] $end -$var logic 128 u" sub5_in[0][2] [127:0] $end -$var logic 128 v" sub5_in[1][0] [127:0] $end -$var logic 128 w" sub5_in[1][1] [127:0] $end -$var logic 128 x" sub5_in[1][2] [127:0] $end -$var wire 8 y" sub5_out[0][0] [7:0] $end -$var wire 8 z" sub5_out[0][1] [7:0] $end -$var wire 8 {" sub5_out[0][2] [7:0] $end -$var wire 8 |" sub5_out[1][0] [7:0] $end -$var wire 8 }" sub5_out[1][1] [7:0] $end -$var wire 8 ~" sub5_out[1][2] [7:0] $end -$var int 32 !# count [31:0] $end +$var parameter 32 5# P0 [31:0] $end +$var real_parameter 64 6# P1 $end +$var real_parameter 64 7# P3 $end +$var wire 1 2# clk $end +$var wire 8 3# in [7:0] $end +$var wire 8 4# out [7:0] $end +$var logic 8 8# ff [7:0] $end +$var logic 128 9# sub5_in[0][0] [127:0] $end +$var logic 128 :# sub5_in[0][1] [127:0] $end +$var logic 128 ;# sub5_in[0][2] [127:0] $end +$var logic 128 <# sub5_in[1][0] [127:0] $end +$var logic 128 =# sub5_in[1][1] [127:0] $end +$var logic 128 ># sub5_in[1][2] [127:0] $end +$var wire 8 ?# sub5_out[0][0] [7:0] $end +$var wire 8 @# sub5_out[0][1] [7:0] $end +$var wire 8 A# sub5_out[0][2] [7:0] $end +$var wire 8 B# sub5_out[1][0] [7:0] $end +$var wire 8 C# sub5_out[1][1] [7:0] $end +$var wire 8 D# sub5_out[1][2] [7:0] $end +$var int 32 E# count [31:0] $end $scope module i_sub5 $end -$var wire 1 l" clk $end -$var wire 128 "# in[0][0] [127:0] $end -$var wire 128 ## in[0][1] [127:0] $end -$var wire 128 $# in[0][2] [127:0] $end -$var wire 128 %# in[1][0] [127:0] $end -$var wire 128 &# in[1][1] [127:0] $end -$var wire 128 '# in[1][2] [127:0] $end -$var wire 8 (# out[0][0] [7:0] $end -$var wire 8 )# out[0][1] [7:0] $end -$var wire 8 *# out[0][2] [7:0] $end -$var wire 8 +# out[1][0] [7:0] $end -$var wire 8 ,# out[1][1] [7:0] $end -$var wire 8 -# out[1][2] [7:0] $end +$var wire 1 2# clk $end +$var wire 128 F# in[0][0] [127:0] $end +$var wire 128 G# in[0][1] [127:0] $end +$var wire 128 H# in[0][2] [127:0] $end +$var wire 128 I# in[1][0] [127:0] $end +$var wire 128 J# in[1][1] [127:0] $end +$var wire 128 K# in[1][2] [127:0] $end +$var wire 8 L# out[0][0] [7:0] $end +$var wire 8 M# out[0][1] [7:0] $end +$var wire 8 N# out[0][2] [7:0] $end +$var wire 8 O# out[1][0] [7:0] $end +$var wire 8 P# out[1][1] [7:0] $end +$var wire 8 Q# out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 .# i [31:0] $end +$var int 32 R# i [31:0] $end $scope module unnamedblk2 $end -$var int 32 /# j [31:0] $end +$var int 32 S# j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 0# exp [7:0] $end +$var byte 8 T# exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end -$var wire 1 1# clk $end -$var wire 128 2# in[0][0] [127:0] $end -$var wire 128 3# in[0][1] [127:0] $end -$var wire 128 4# in[0][2] [127:0] $end -$var wire 128 5# in[1][0] [127:0] $end -$var wire 128 6# in[1][1] [127:0] $end -$var wire 128 7# in[1][2] [127:0] $end -$var wire 8 8# out[0][0] [7:0] $end -$var wire 8 9# out[0][1] [7:0] $end -$var wire 8 :# out[0][2] [7:0] $end -$var wire 8 ;# out[1][0] [7:0] $end -$var wire 8 <# out[1][1] [7:0] $end -$var wire 8 =# out[1][2] [7:0] $end +$var wire 1 U# clk $end +$var wire 128 V# in[0][0] [127:0] $end +$var wire 128 W# in[0][1] [127:0] $end +$var wire 128 X# in[0][2] [127:0] $end +$var wire 128 Y# in[1][0] [127:0] $end +$var wire 128 Z# in[1][1] [127:0] $end +$var wire 128 [# in[1][2] [127:0] $end +$var wire 8 \# out[0][0] [7:0] $end +$var wire 8 ]# out[0][1] [7:0] $end +$var wire 8 ^# out[0][2] [7:0] $end +$var wire 8 _# out[1][0] [7:0] $end +$var wire 8 `# out[1][1] [7:0] $end +$var wire 8 a# out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 1# clk $end -$var wire 128 2# in[0][0] [127:0] $end -$var wire 128 3# in[0][1] [127:0] $end -$var wire 128 4# in[0][2] [127:0] $end -$var wire 128 5# in[1][0] [127:0] $end -$var wire 128 6# in[1][1] [127:0] $end -$var wire 128 7# in[1][2] [127:0] $end -$var wire 8 8# out[0][0] [7:0] $end -$var wire 8 9# out[0][1] [7:0] $end -$var wire 8 :# out[0][2] [7:0] $end -$var wire 8 ;# out[1][0] [7:0] $end -$var wire 8 <# out[1][1] [7:0] $end -$var wire 8 =# out[1][2] [7:0] $end -$var int 32 ># count [31:0] $end -$var wire 8 ?# val0[0] [7:0] $end -$var wire 8 @# val0[1] [7:0] $end -$var wire 8 A# val1[0] [7:0] $end -$var wire 8 B# val1[1] [7:0] $end -$var wire 8 C# val2[0] [7:0] $end -$var wire 8 D# val2[1] [7:0] $end -$var wire 8 E# val3[0] [7:0] $end -$var wire 8 F# val3[1] [7:0] $end +$var wire 1 U# clk $end +$var wire 128 V# in[0][0] [127:0] $end +$var wire 128 W# in[0][1] [127:0] $end +$var wire 128 X# in[0][2] [127:0] $end +$var wire 128 Y# in[1][0] [127:0] $end +$var wire 128 Z# in[1][1] [127:0] $end +$var wire 128 [# in[1][2] [127:0] $end +$var wire 8 \# out[0][0] [7:0] $end +$var wire 8 ]# out[0][1] [7:0] $end +$var wire 8 ^# out[0][2] [7:0] $end +$var wire 8 _# out[1][0] [7:0] $end +$var wire 8 `# out[1][1] [7:0] $end +$var wire 8 a# out[1][2] [7:0] $end +$var int 32 b# count [31:0] $end +$var wire 8 c# val0[0] [7:0] $end +$var wire 8 d# val0[1] [7:0] $end +$var wire 8 e# val1[0] [7:0] $end +$var wire 8 f# val1[1] [7:0] $end +$var wire 8 g# val2[0] [7:0] $end +$var wire 8 h# val2[1] [7:0] $end +$var wire 8 i# val3[0] [7:0] $end +$var wire 8 j# val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 G# P0 [31:0] $end -$var parameter 32 H# P1 [31:0] $end -$var wire 8 ?# out[0] [7:0] $end -$var wire 8 @# out[1] [7:0] $end +$var wire 8 k# out[0] [7:0] $end +$var wire 8 l# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 G# P0 [31:0] $end -$var parameter 32 H# P1 [31:0] $end -$var wire 8 A# out[0] [7:0] $end -$var wire 8 B# out[1] [7:0] $end +$var wire 8 m# out[0] [7:0] $end +$var wire 8 n# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 G# P0 [31:0] $end -$var parameter 32 H# P1 [31:0] $end -$var wire 8 C# out[0] [7:0] $end -$var wire 8 D# out[1] [7:0] $end +$var wire 8 o# out[0] [7:0] $end +$var wire 8 p# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 I# out[0] [7:0] $end -$var wire 8 J# out[1] [7:0] $end +$var wire 8 q# out[0] [7:0] $end +$var wire 8 r# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 K# i [31:0] $end +$var int 32 s# i [31:0] $end $scope module unnamedblk2 $end -$var int 32 L# j [31:0] $end +$var int 32 t# j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 M# exp [127:0] $end +$var bit 128 u# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end +$var wire 8 v# out[0] [7:0] $end +$var wire 8 w# out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 x# P0 [31:0] $end +$var parameter 32 y# P1 [31:0] $end +$var wire 8 v# out[0] [7:0] $end +$var wire 8 w# out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end -$var wire 8 N# out[0] [7:0] $end -$var wire 8 O# out[1] [7:0] $end +$var wire 8 z# out[0] [7:0] $end +$var wire 8 {# out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 P# P0 [31:0] $end -$var parameter 32 Q# P1 [31:0] $end -$var wire 8 N# out[0] [7:0] $end -$var wire 8 O# out[1] [7:0] $end +$var parameter 32 |# P0 [31:0] $end +$var parameter 32 }# P1 [31:0] $end +$var wire 8 z# out[0] [7:0] $end +$var wire 8 {# out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3 $end -$var wire 1 R# clk $end -$var wire 8 S# in [7:0] $end -$var wire 8 T# out [7:0] $end +$var wire 1 ~# clk $end +$var wire 8 !$ in [7:0] $end +$var wire 8 "$ out [7:0] $end $scope module sub3_d $end -$var parameter 8 U# P0 [7:0] $end -$var parameter 32 V# UNPACKED_ARRAY[0] [31:0] $end -$var parameter 32 W# UNPACKED_ARRAY[1] [31:0] $end -$var parameter 16 X# UNUSED [15:0] $end -$var wire 1 R# clk $end -$var wire 8 S# in [7:0] $end -$var wire 8 T# out [7:0] $end -$var logic 8 Y# ff [7:0] $end -$var wire 8 T# out4 [7:0] $end -$var wire 8 Z# out4_2 [7:0] $end +$var parameter 8 #$ P0 [7:0] $end +$var parameter 32 $$ UNPACKED_ARRAY[0] [31:0] $end +$var parameter 32 %$ UNPACKED_ARRAY[1] [31:0] $end +$var parameter 16 &$ UNUSED [15:0] $end +$var wire 1 ~# clk $end +$var wire 8 !$ in [7:0] $end +$var wire 8 "$ out [7:0] $end +$var logic 8 '$ ff [7:0] $end +$var wire 8 "$ out4 [7:0] $end +$var wire 8 ($ out4_2 [7:0] $end $scope module i_sub4_0 $end -$var wire 1 R# clk $end -$var wire 8 Y# in [7:0] $end -$var wire 8 T# out [7:0] $end +$var wire 1 ~# clk $end +$var wire 8 '$ in [7:0] $end +$var wire 8 "$ out [7:0] $end $upscope $end $scope module i_sub4_1 $end -$var wire 1 R# clk $end -$var wire 8 Y# in [7:0] $end -$var wire 8 Z# out [7:0] $end +$var wire 1 ~# clk $end +$var wire 8 '$ in [7:0] $end +$var wire 8 ($ out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0 $end -$var wire 1 [# clk $end -$var wire 8 \# in [7:0] $end -$var wire 8 ]# out [7:0] $end +$var wire 1 )$ clk $end +$var wire 8 *$ in [7:0] $end +$var wire 8 +$ out [7:0] $end $scope module sub4_2 $end -$var parameter 32 ^# P0 [31:0] $end -$var real_parameter 64 _# P1 $end -$var real_parameter 64 `# P3 $end -$var wire 1 [# clk $end -$var wire 8 \# in [7:0] $end -$var wire 8 ]# out [7:0] $end -$var logic 8 a# ff [7:0] $end -$var logic 128 b# sub5_in[0][0] [127:0] $end -$var logic 128 c# sub5_in[0][1] [127:0] $end -$var logic 128 d# sub5_in[0][2] [127:0] $end -$var logic 128 e# sub5_in[1][0] [127:0] $end -$var logic 128 f# sub5_in[1][1] [127:0] $end -$var logic 128 g# sub5_in[1][2] [127:0] $end -$var wire 8 h# sub5_out[0][0] [7:0] $end -$var wire 8 i# sub5_out[0][1] [7:0] $end -$var wire 8 j# sub5_out[0][2] [7:0] $end -$var wire 8 k# sub5_out[1][0] [7:0] $end -$var wire 8 l# sub5_out[1][1] [7:0] $end -$var wire 8 m# sub5_out[1][2] [7:0] $end -$var int 32 n# count [31:0] $end +$var parameter 32 ,$ P0 [31:0] $end +$var real_parameter 64 -$ P1 $end +$var real_parameter 64 .$ P3 $end +$var wire 1 )$ clk $end +$var wire 8 *$ in [7:0] $end +$var wire 8 +$ out [7:0] $end +$var logic 8 /$ ff [7:0] $end +$var logic 128 0$ sub5_in[0][0] [127:0] $end +$var logic 128 1$ sub5_in[0][1] [127:0] $end +$var logic 128 2$ sub5_in[0][2] [127:0] $end +$var logic 128 3$ sub5_in[1][0] [127:0] $end +$var logic 128 4$ sub5_in[1][1] [127:0] $end +$var logic 128 5$ sub5_in[1][2] [127:0] $end +$var wire 8 6$ sub5_out[0][0] [7:0] $end +$var wire 8 7$ sub5_out[0][1] [7:0] $end +$var wire 8 8$ sub5_out[0][2] [7:0] $end +$var wire 8 9$ sub5_out[1][0] [7:0] $end +$var wire 8 :$ sub5_out[1][1] [7:0] $end +$var wire 8 ;$ sub5_out[1][2] [7:0] $end +$var int 32 <$ count [31:0] $end $scope module i_sub5 $end -$var wire 1 [# clk $end -$var wire 128 o# in[0][0] [127:0] $end -$var wire 128 p# in[0][1] [127:0] $end -$var wire 128 q# in[0][2] [127:0] $end -$var wire 128 r# in[1][0] [127:0] $end -$var wire 128 s# in[1][1] [127:0] $end -$var wire 128 t# in[1][2] [127:0] $end -$var wire 8 u# out[0][0] [7:0] $end -$var wire 8 v# out[0][1] [7:0] $end -$var wire 8 w# out[0][2] [7:0] $end -$var wire 8 x# out[1][0] [7:0] $end -$var wire 8 y# out[1][1] [7:0] $end -$var wire 8 z# out[1][2] [7:0] $end +$var wire 1 )$ clk $end +$var wire 128 =$ in[0][0] [127:0] $end +$var wire 128 >$ in[0][1] [127:0] $end +$var wire 128 ?$ in[0][2] [127:0] $end +$var wire 128 @$ in[1][0] [127:0] $end +$var wire 128 A$ in[1][1] [127:0] $end +$var wire 128 B$ in[1][2] [127:0] $end +$var wire 8 C$ out[0][0] [7:0] $end +$var wire 8 D$ out[0][1] [7:0] $end +$var wire 8 E$ out[0][2] [7:0] $end +$var wire 8 F$ out[1][0] [7:0] $end +$var wire 8 G$ out[1][1] [7:0] $end +$var wire 8 H$ out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 {# i [31:0] $end +$var int 32 I$ i [31:0] $end $scope module unnamedblk2 $end -$var int 32 |# j [31:0] $end +$var int 32 J$ j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 }# exp [7:0] $end +$var byte 8 K$ exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end -$var wire 1 ~# clk $end -$var wire 128 !$ in[0][0] [127:0] $end -$var wire 128 "$ in[0][1] [127:0] $end -$var wire 128 #$ in[0][2] [127:0] $end -$var wire 128 $$ in[1][0] [127:0] $end -$var wire 128 %$ in[1][1] [127:0] $end -$var wire 128 &$ in[1][2] [127:0] $end -$var wire 8 '$ out[0][0] [7:0] $end -$var wire 8 ($ out[0][1] [7:0] $end -$var wire 8 )$ out[0][2] [7:0] $end -$var wire 8 *$ out[1][0] [7:0] $end -$var wire 8 +$ out[1][1] [7:0] $end -$var wire 8 ,$ out[1][2] [7:0] $end +$var wire 1 L$ clk $end +$var wire 128 M$ in[0][0] [127:0] $end +$var wire 128 N$ in[0][1] [127:0] $end +$var wire 128 O$ in[0][2] [127:0] $end +$var wire 128 P$ in[1][0] [127:0] $end +$var wire 128 Q$ in[1][1] [127:0] $end +$var wire 128 R$ in[1][2] [127:0] $end +$var wire 8 S$ out[0][0] [7:0] $end +$var wire 8 T$ out[0][1] [7:0] $end +$var wire 8 U$ out[0][2] [7:0] $end +$var wire 8 V$ out[1][0] [7:0] $end +$var wire 8 W$ out[1][1] [7:0] $end +$var wire 8 X$ out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 ~# clk $end -$var wire 128 !$ in[0][0] [127:0] $end -$var wire 128 "$ in[0][1] [127:0] $end -$var wire 128 #$ in[0][2] [127:0] $end -$var wire 128 $$ in[1][0] [127:0] $end -$var wire 128 %$ in[1][1] [127:0] $end -$var wire 128 &$ in[1][2] [127:0] $end -$var wire 8 '$ out[0][0] [7:0] $end -$var wire 8 ($ out[0][1] [7:0] $end -$var wire 8 )$ out[0][2] [7:0] $end -$var wire 8 *$ out[1][0] [7:0] $end -$var wire 8 +$ out[1][1] [7:0] $end -$var wire 8 ,$ out[1][2] [7:0] $end -$var int 32 -$ count [31:0] $end -$var wire 8 .$ val0[0] [7:0] $end -$var wire 8 /$ val0[1] [7:0] $end -$var wire 8 0$ val1[0] [7:0] $end -$var wire 8 1$ val1[1] [7:0] $end -$var wire 8 2$ val2[0] [7:0] $end -$var wire 8 3$ val2[1] [7:0] $end -$var wire 8 4$ val3[0] [7:0] $end -$var wire 8 5$ val3[1] [7:0] $end +$var wire 1 L$ clk $end +$var wire 128 M$ in[0][0] [127:0] $end +$var wire 128 N$ in[0][1] [127:0] $end +$var wire 128 O$ in[0][2] [127:0] $end +$var wire 128 P$ in[1][0] [127:0] $end +$var wire 128 Q$ in[1][1] [127:0] $end +$var wire 128 R$ in[1][2] [127:0] $end +$var wire 8 S$ out[0][0] [7:0] $end +$var wire 8 T$ out[0][1] [7:0] $end +$var wire 8 U$ out[0][2] [7:0] $end +$var wire 8 V$ out[1][0] [7:0] $end +$var wire 8 W$ out[1][1] [7:0] $end +$var wire 8 X$ out[1][2] [7:0] $end +$var int 32 Y$ count [31:0] $end +$var wire 8 Z$ val0[0] [7:0] $end +$var wire 8 [$ val0[1] [7:0] $end +$var wire 8 \$ val1[0] [7:0] $end +$var wire 8 ]$ val1[1] [7:0] $end +$var wire 8 ^$ val2[0] [7:0] $end +$var wire 8 _$ val2[1] [7:0] $end +$var wire 8 `$ val3[0] [7:0] $end +$var wire 8 a$ val3[1] [7:0] $end $scope module i_sub0 $end -$var parameter 32 6$ P0 [31:0] $end -$var parameter 32 7$ P1 [31:0] $end -$var wire 8 .$ out[0] [7:0] $end -$var wire 8 /$ out[1] [7:0] $end +$var wire 8 b$ out[0] [7:0] $end +$var wire 8 c$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end -$var parameter 32 6$ P0 [31:0] $end -$var parameter 32 7$ P1 [31:0] $end -$var wire 8 0$ out[0] [7:0] $end -$var wire 8 1$ out[1] [7:0] $end +$var wire 8 d$ out[0] [7:0] $end +$var wire 8 e$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end -$var parameter 32 6$ P0 [31:0] $end -$var parameter 32 7$ P1 [31:0] $end -$var wire 8 2$ out[0] [7:0] $end -$var wire 8 3$ out[1] [7:0] $end +$var wire 8 f$ out[0] [7:0] $end +$var wire 8 g$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end -$var wire 8 8$ out[0] [7:0] $end -$var wire 8 9$ out[1] [7:0] $end +$var wire 8 h$ out[0] [7:0] $end +$var wire 8 i$ out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 :$ i [31:0] $end +$var int 32 j$ i [31:0] $end $scope module unnamedblk2 $end -$var int 32 ;$ j [31:0] $end +$var int 32 k$ j [31:0] $end $scope module unnamedblk3 $end -$var bit 128 <$ exp [127:0] $end +$var bit 128 l$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end +$scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end +$var wire 8 m$ out[0] [7:0] $end +$var wire 8 n$ out[1] [7:0] $end +$scope module sub6_f $end +$var parameter 32 o$ P0 [31:0] $end +$var parameter 32 p$ P1 [31:0] $end +$var wire 8 m$ out[0] [7:0] $end +$var wire 8 n$ out[1] [7:0] $end +$upscope $end +$upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end -$var wire 8 =$ out[0] [7:0] $end -$var wire 8 >$ out[1] [7:0] $end +$var wire 8 q$ out[0] [7:0] $end +$var wire 8 r$ out[1] [7:0] $end $scope module sub6_9 $end -$var parameter 32 ?$ P0 [31:0] $end -$var parameter 32 @$ P1 [31:0] $end -$var wire 8 =$ out[0] [7:0] $end -$var wire 8 >$ out[1] [7:0] $end +$var parameter 32 s$ P0 [31:0] $end +$var parameter 32 t$ P1 [31:0] $end +$var wire 8 q$ out[0] [7:0] $end +$var wire 8 r$ out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1 $end -$var wire 1 A$ clk $end -$var wire 8 B$ in [7:0] $end -$var wire 8 C$ out [7:0] $end +$var wire 1 u$ clk $end +$var wire 8 v$ in [7:0] $end +$var wire 8 w$ out [7:0] $end $scope module sub4_b $end -$var parameter 32 D$ P0 [31:0] $end -$var real_parameter 64 E$ P1 $end -$var real_parameter 64 F$ P3 $end -$var wire 1 A$ clk $end -$var wire 8 B$ in [7:0] $end -$var wire 8 C$ out [7:0] $end -$var logic 8 G$ ff [7:0] $end -$var logic 128 H$ sub5_in[0][0] [127:0] $end -$var logic 128 I$ sub5_in[0][1] [127:0] $end -$var logic 128 J$ sub5_in[0][2] [127:0] $end -$var logic 128 K$ sub5_in[1][0] [127:0] $end -$var logic 128 L$ sub5_in[1][1] [127:0] $end -$var logic 128 M$ sub5_in[1][2] [127:0] $end -$var wire 8 N$ sub5_out[0][0] [7:0] $end -$var wire 8 O$ sub5_out[0][1] [7:0] $end -$var wire 8 P$ sub5_out[0][2] [7:0] $end -$var wire 8 Q$ sub5_out[1][0] [7:0] $end -$var wire 8 R$ sub5_out[1][1] [7:0] $end -$var wire 8 S$ sub5_out[1][2] [7:0] $end -$var int 32 T$ count [31:0] $end +$var parameter 32 x$ P0 [31:0] $end +$var real_parameter 64 y$ P1 $end +$var real_parameter 64 z$ P3 $end +$var wire 1 u$ clk $end +$var wire 8 v$ in [7:0] $end +$var wire 8 w$ out [7:0] $end +$var logic 8 {$ ff [7:0] $end +$var logic 128 |$ sub5_in[0][0] [127:0] $end +$var logic 128 }$ sub5_in[0][1] [127:0] $end +$var logic 128 ~$ sub5_in[0][2] [127:0] $end +$var logic 128 !% sub5_in[1][0] [127:0] $end +$var logic 128 "% sub5_in[1][1] [127:0] $end +$var logic 128 #% sub5_in[1][2] [127:0] $end +$var wire 8 $% sub5_out[0][0] [7:0] $end +$var wire 8 %% sub5_out[0][1] [7:0] $end +$var wire 8 &% sub5_out[0][2] [7:0] $end +$var wire 8 '% sub5_out[1][0] [7:0] $end +$var wire 8 (% sub5_out[1][1] [7:0] $end +$var wire 8 )% sub5_out[1][2] [7:0] $end +$var int 32 *% count [31:0] $end $scope module i_sub5 $end -$var wire 1 A$ clk $end -$var wire 128 U$ in[0][0] [127:0] $end -$var wire 128 V$ in[0][1] [127:0] $end -$var wire 128 W$ in[0][2] [127:0] $end -$var wire 128 X$ in[1][0] [127:0] $end -$var wire 128 Y$ in[1][1] [127:0] $end -$var wire 128 Z$ in[1][2] [127:0] $end -$var wire 8 [$ out[0][0] [7:0] $end -$var wire 8 \$ out[0][1] [7:0] $end -$var wire 8 ]$ out[0][2] [7:0] $end -$var wire 8 ^$ out[1][0] [7:0] $end -$var wire 8 _$ out[1][1] [7:0] $end -$var wire 8 `$ out[1][2] [7:0] $end +$var wire 1 u$ clk $end +$var wire 128 +% in[0][0] [127:0] $end +$var wire 128 ,% in[0][1] [127:0] $end +$var wire 128 -% in[0][2] [127:0] $end +$var wire 128 .% in[1][0] [127:0] $end +$var wire 128 /% in[1][1] [127:0] $end +$var wire 128 0% in[1][2] [127:0] $end +$var wire 8 1% out[0][0] [7:0] $end +$var wire 8 2% out[0][1] [7:0] $end +$var wire 8 3% out[0][2] [7:0] $end +$var wire 8 4% out[1][0] [7:0] $end +$var wire 8 5% out[1][1] [7:0] $end +$var wire 8 6% out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end -$var int 32 a$ i [31:0] $end +$var int 32 7% i [31:0] $end $scope module unnamedblk2 $end -$var int 32 b$ j [31:0] $end +$var int 32 8% j [31:0] $end $scope module unnamedblk3 $end -$var byte 8 c$ exp [7:0] $end +$var byte 8 9% exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end -$var wire 1 d$ clk $end -$var wire 128 e$ in[0][0] [127:0] $end -$var wire 128 f$ in[0][1] [127:0] $end -$var wire 128 g$ in[0][2] [127:0] $end -$var wire 128 h$ in[1][0] [127:0] $end -$var wire 128 i$ in[1][1] [127:0] $end -$var wire 128 j$ in[1][2] [127:0] $end -$var wire 8 k$ out[0][0] [7:0] $end -$var wire 8 l$ out[0][1] [7:0] $end -$var wire 8 m$ out[0][2] [7:0] $end -$var wire 8 n$ out[1][0] [7:0] $end -$var wire 8 o$ out[1][1] [7:0] $end -$var wire 8 p$ out[1][2] [7:0] $end +$var wire 1 :% clk $end +$var wire 128 ;% in[0][0] [127:0] $end +$var wire 128 <% in[0][1] [127:0] $end +$var wire 128 =% in[0][2] [127:0] $end +$var wire 128 >% in[1][0] [127:0] $end +$var wire 128 ?% in[1][1] [127:0] $end +$var wire 128 @% in[1][2] [127:0] $end +$var wire 8 A% out[0][0] [7:0] $end +$var wire 8 B% out[0][1] [7:0] $end +$var wire 8 C% out[0][2] [7:0] $end +$var wire 8 D% out[1][0] [7:0] $end +$var wire 8 E% out[1][1] [7:0] $end +$var wire 8 F% out[1][2] [7:0] $end $scope module sub5 $end -$var wire 1 d$ clk $end -$var wire 128 e$ in[0][0] [127:0] $end -$var wire 128 f$ in[0][1] [127:0] $end -$var wire 128 g$ in[0][2] [127:0] $end -$var wire 128 h$ in[1][0] [127:0] $end -$var wire 128 i$ in[1][1] [127:0] $end -$var wire 128 j$ in[1][2] [127:0] $end -$var wire 8 k$ out[0][0] [7:0] $end -$var wire 8 l$ out[0][1] [7:0] $end -$var wire 8 m$ out[0][2] [7:0] $end -$var wire 8 n$ out[1][0] [7:0] $end -$var wire 8 o$ out[1][1] [7:0] $end -$var wire 8 p$ out[1][2] [7:0] $end -$var int 32 q$ count [31:0] $end -$var wire 8 r$ val0[0] [7:0] $end -$var wire 8 s$ val0[1] [7:0] $end -$var wire 8 t$ val1[0] [7:0] $end -$var wire 8 u$ val1[1] [7:0] $end -$var wire 8 v$ val2[0] [7:0] $end -$var wire 8 w$ val2[1] [7:0] $end -$var wire 8 x$ val3[0] [7:0] $end -$var wire 8 y$ val3[1] [7:0] $end +$var wire 1 :% clk $end +$var wire 128 ;% in[0][0] [127:0] $end +$var wire 128 <% in[0][1] [127:0] $end +$var wire 128 =% in[0][2] [127:0] $end +$var wire 128 >% in[1][0] [127:0] $end +$var wire 128 ?% in[1][1] [127:0] $end +$var wire 128 @% in[1][2] [127:0] $end +$var wire 8 A% out[0][0] [7:0] $end +$var wire 8 B% out[0][1] [7:0] $end +$var wire 8 C% out[0][2] [7:0] $end +$var wire 8 D% out[1][0] [7:0] $end +$var wire 8 E% out[1][1] [7:0] $end +$var wire 8 F% out[1][2] [7:0] $end +$var int 32 G% count [31:0] $end +$var wire 8 H% val0[0] [7:0] $end +$var wire 8 I% val0[1] [7:0] $end +$var wire 8 J% val1[0] [7:0] $end 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o! +b00000001 f" +b00000001 T# +b00000001 K$ +b00000001 9% b00011101 $ -b00011101 F -b00011101 H -b00011101 I -b00011101 L b00011101 R +b00011101 T b00011101 U -b00011101 Y -b00011101 ;! -b00011101 ?! -b00011101 ~! -b00011101 S# +b00011101 X +b00011101 ^ +b00011101 a +b00011101 e +b00011101 O! +b00011101 S! +b00011101 <" +b00011101 !$ b00010101 ( -b00010101 4 -b00010101 ; +b00010101 8 +b00010101 > +b00010101 D +b00010101 G b00011011 % b00011011 & b00011011 + -b00011011 = -b00011011 !" -b00011011 '" -b00011011 *" -b00011011 ." -b00011011 n" -b00011011 r" -b00011011 T# -b00011011 Z# -b00011011 ]# -b00011011 a# -b00011011 C$ -b00011011 G$ -b00011001 E -b00011001 C -b00011001 B +b00011011 I +b00011011 =" +b00011011 C" +b00011011 F" +b00011011 J" +b00011011 4# +b00011011 8# +b00011011 "$ +b00011011 ($ +b00011011 +$ +b00011011 /$ +b00011011 w$ +b00011011 {$ +b00011001 Q +b00011001 O +b00011001 N b00011001 # b00011000 ' b00011000 , -b00011000 1 -b00011000 3 +b00011000 2 +b00011000 5 +b00011000 7 diff --git a/test_regress/t/t_hier_block_trace_vcd.out b/test_regress/t/t_hier_block_trace_vcd.out index a3c3edfbb..8faed889f 100644 --- a/test_regress/t/t_hier_block_trace_vcd.out +++ b/test_regress/t/t_hier_block_trace_vcd.out @@ -1,6 +1,5 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module top $end $var wire 1 * clk $end $scope module t $end @@ -60,986 +59,1040 @@ $timescale 1ps $end $var wire 8 . in [7:0] $end $var wire 8 / out [7:0] $end $scope module delay_2 $end - $var wire 32 2 N [31:0] $end - $var wire 32 3 WIDTH [31:0] $end + $var wire 32 1 N [31:0] $end + $var wire 32 2 WIDTH [31:0] $end $var wire 1 - clk $end $var wire 8 . in [7:0] $end $var wire 8 / out [7:0] $end $var wire 8 0 tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 4 N [31:0] $end - $var wire 32 3 WIDTH [31:0] $end $var wire 1 - clk $end $var wire 8 0 in [7:0] $end $var wire 8 / out [7:0] $end - $var wire 8 1 tmp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_delay0.delay_2.genblk1.i_delay $end + $var wire 1 4 clk $end + $var wire 8 5 in [7:0] $end + $var wire 8 6 out [7:0] $end + $scope module delay_4 $end + $var wire 32 8 N [31:0] $end + $var wire 32 9 WIDTH [31:0] $end + $var wire 1 4 clk $end + $var wire 8 5 in [7:0] $end + $var wire 8 6 out [7:0] $end + $var wire 8 7 tmp [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_delay1 $end - $var wire 1 9 clk $end - $var wire 8 : in [7:0] $end - $var wire 8 ; out [7:0] $end + $var wire 1 ; clk $end + $var wire 8 < in [7:0] $end + $var wire 8 = out [7:0] $end $scope module delay_9 $end - $var wire 32 < N [31:0] $end - $var wire 32 = WIDTH [31:0] $end - $var wire 1 9 clk $end - $var wire 8 : in [7:0] $end - $var wire 8 ; out [7:0] $end - $var wire 8 6 tmp [7:0] $end + $var wire 32 ? N [31:0] $end + $var wire 32 @ WIDTH [31:0] $end + $var wire 1 ; clk $end + $var wire 8 < in [7:0] $end + $var wire 8 = out [7:0] $end + $var wire 8 > tmp [7:0] $end $scope module genblk1 $end $scope module i_delay $end - $var wire 32 > N [31:0] $end - $var wire 32 = WIDTH [31:0] $end - $var wire 1 9 clk $end - $var wire 8 6 in [7:0] $end - $var wire 8 ; out [7:0] $end - $var wire 8 7 tmp [7:0] $end - $scope module genblk1 $end - $scope module i_delay $end - $var wire 32 ? N [31:0] $end - $var wire 32 = WIDTH [31:0] $end - $var wire 1 9 clk $end - $var wire 8 7 in [7:0] $end - $var wire 8 ; out [7:0] $end - $var wire 8 8 tmp [7:0] $end - $upscope $end - $upscope $end + $var wire 1 ; clk $end + $var wire 8 > in [7:0] $end + $var wire 8 = out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_delay1.delay_9.genblk1.i_delay $end + $var wire 1 B clk $end + $var wire 8 C in [7:0] $end + $var wire 8 D out [7:0] $end + $scope module delay_2 $end + $var wire 32 F N [31:0] $end + $var wire 32 G WIDTH [31:0] $end + $var wire 1 B clk $end + $var wire 8 C in [7:0] $end + $var wire 8 D out [7:0] $end + $var wire 8 E tmp [7:0] $end + $scope module genblk1 $end + $scope module i_delay $end + $var wire 1 B clk $end + $var wire 8 E in [7:0] $end + $var wire 8 D out [7:0] $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module top.t.i_delay1.delay_9.genblk1.i_delay.delay_2.genblk1.i_delay $end + $var wire 1 I clk $end + $var wire 8 J in [7:0] $end + $var wire 8 K out [7:0] $end + $scope module delay_4 $end + $var wire 32 M N [31:0] $end + $var wire 32 N WIDTH [31:0] $end + $var wire 1 I clk $end + $var wire 8 J in [7:0] $end + $var wire 8 K out [7:0] $end + $var wire 8 L tmp [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub0.i_sub0 $end - $var wire 1 A clk $end - $var wire 8 B in [7:0] $end - $var wire 8 C out [7:0] $end + $var wire 1 P clk $end + $var wire 8 Q in [7:0] $end + $var wire 8 R out [7:0] $end $scope module sub0 $end - $var wire 1 A clk $end - $var wire 8 B in [7:0] $end - $var wire 8 C out [7:0] $end - $var wire 8 D ff [7:0] $end + $var wire 1 P clk $end + $var wire 8 Q in [7:0] $end + $var wire 8 R out [7:0] $end + $var wire 8 S ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub1 $end - $var wire 1 F clk $end - $var wire 8 G in [11:4] $end - $var wire 8 H out [7:0] $end + $var wire 1 U clk $end + $var wire 8 V in [11:4] $end + $var wire 8 W out [7:0] $end $scope module sub1 $end - $var wire 1 F clk $end - $var wire 8 G in [11:4] $end - $var wire 8 H out [7:0] $end - $var wire 8 I ff [7:0] $end + $var wire 1 U clk $end + $var wire 8 V in [11:4] $end + $var wire 8 W out [7:0] $end + $var wire 8 X ff [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2 $end - $var wire 1 K clk $end - $var wire 8 L in [7:0] $end - $var wire 8 M out [7:0] $end + $var wire 1 Z clk $end + $var wire 8 [ in [7:0] $end + $var wire 8 \ out [7:0] $end $scope module sub2 $end - $var wire 1 K clk $end - $var wire 8 L in [7:0] $end - $var wire 8 M out [7:0] $end - $var wire 8 N ff [7:0] $end + $var wire 1 Z clk $end + $var wire 8 [ in [7:0] $end + $var wire 8 \ out [7:0] $end + $var wire 8 ] ff [7:0] $end $scope module in_ifs $end - $var wire 1 K clk $end - $var wire 8 N data [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ] data [7:0] $end $upscope $end $scope module out_ifs $end - $var wire 1 K clk $end - $var wire 8 O data [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ^ data [7:0] $end $upscope $end $scope module i_sub3 $end $scope module in $end - $var wire 1 K clk $end - $var wire 8 N data [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ] data [7:0] $end $upscope $end $scope module out $end - $var wire 1 K clk $end - $var wire 8 O data [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ^ data [7:0] $end $upscope $end - $var wire 8 N in_wire [7:0] $end - $var wire 8 O out_1 [7:0] $end - $var wire 8 P out_2 [7:0] $end + $var wire 8 ] in_wire [7:0] $end + $var wire 8 ^ out_1 [7:0] $end + $var wire 8 _ out_2 [7:0] $end $scope module i_sub3 $end - $var wire 1 K clk $end - $var wire 8 N in [7:0] $end - $var wire 8 O out [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ] in [7:0] $end + $var wire 8 ^ out [7:0] $end $upscope $end $scope module i_sub3_2 $end - $var wire 1 K clk $end - $var wire 8 N in [7:0] $end - $var wire 8 P out [7:0] $end + $var wire 1 Z clk $end + $var wire 8 ] in [7:0] $end + $var wire 8 _ out [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3 $end - $var wire 1 R clk $end - $var wire 8 S in [7:0] $end - $var wire 8 T out [7:0] $end + $var wire 1 a clk $end + $var wire 8 b in [7:0] $end + $var wire 8 c out [7:0] $end $scope module sub3_c $end - $var wire 8 W P0 [7:0] $end - $var wire 32 X UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 Y UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 Z UNUSED [15:0] $end - $var wire 1 R clk $end - $var wire 8 S in [7:0] $end - $var wire 8 T out [7:0] $end - $var wire 8 U ff [7:0] $end - $var wire 8 T out4 [7:0] $end - $var wire 8 V out4_2 [7:0] $end + $var wire 8 f P0 [7:0] $end + $var wire 32 g UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 h UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 i UNUSED [15:0] $end + $var wire 1 a clk $end + $var wire 8 b in [7:0] $end + $var wire 8 c out [7:0] $end + $var wire 8 d ff [7:0] $end + $var wire 8 c out4 [7:0] $end + $var wire 8 e out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 1 R clk $end - $var wire 8 U in [7:0] $end - $var wire 8 T out [7:0] $end + $var wire 1 a clk $end + $var wire 8 d in [7:0] $end + $var wire 8 c out [7:0] $end $upscope $end $scope module i_sub4_1 $end - $var wire 1 R clk $end - $var wire 8 U in [7:0] $end - $var wire 8 V out [7:0] $end + $var wire 1 a clk $end + $var wire 8 d in [7:0] $end + $var wire 8 e out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0 $end - $var wire 1 ?! clk $end - $var wire 8 @! in [7:0] $end - $var wire 8 A! out [7:0] $end + $var wire 1 N! clk $end + $var wire 8 O! in [7:0] $end + $var wire 8 P! out [7:0] $end $scope module sub4_2 $end - $var wire 32 B! P0 [31:0] $end - $var real 64 C! P1 $end - $var real 64 E! P3 $end - $var wire 1 ?! clk $end - $var wire 8 @! in [7:0] $end - $var wire 8 A! out [7:0] $end - $var wire 8 \ ff [7:0] $end - $var wire 128 ] sub5_in[0][0] [127:0] $end - $var wire 128 a sub5_in[0][1] [127:0] $end - $var wire 128 e sub5_in[0][2] [127:0] $end - $var wire 128 i sub5_in[1][0] [127:0] $end - $var wire 128 m sub5_in[1][1] [127:0] $end - $var wire 128 q sub5_in[1][2] [127:0] $end - $var wire 8 3! sub5_out[0][0] [7:0] $end - $var wire 8 4! sub5_out[0][1] [7:0] $end - $var wire 8 5! sub5_out[0][2] [7:0] $end - $var wire 8 6! sub5_out[1][0] [7:0] $end - $var wire 8 7! sub5_out[1][1] [7:0] $end - $var wire 8 8! sub5_out[1][2] [7:0] $end - $var wire 32 u count [31:0] $end + $var wire 32 Q! P0 [31:0] $end + $var real 64 R! P1 $end + $var real 64 T! P3 $end + $var wire 1 N! clk $end + $var wire 8 O! in [7:0] $end + $var wire 8 P! out [7:0] $end + $var wire 8 k ff [7:0] $end + $var wire 128 l sub5_in[0][0] [127:0] $end + $var wire 128 p sub5_in[0][1] [127:0] $end + $var wire 128 t sub5_in[0][2] [127:0] $end + $var wire 128 x sub5_in[1][0] [127:0] $end + $var wire 128 | sub5_in[1][1] [127:0] $end + $var wire 128 "! sub5_in[1][2] [127:0] $end + $var wire 8 B! sub5_out[0][0] [7:0] $end + $var wire 8 C! sub5_out[0][1] [7:0] $end + $var wire 8 D! sub5_out[0][2] [7:0] $end + $var wire 8 E! sub5_out[1][0] [7:0] $end + $var wire 8 F! sub5_out[1][1] [7:0] $end + $var wire 8 G! sub5_out[1][2] [7:0] $end + $var wire 32 &! count [31:0] $end $scope module i_sub5 $end - $var wire 1 ?! clk $end - $var wire 128 y in[0][0] [127:0] $end - $var wire 128 } in[0][1] [127:0] $end - $var wire 128 #! in[0][2] [127:0] $end - $var wire 128 '! in[1][0] [127:0] $end - $var wire 128 +! in[1][1] [127:0] $end - $var wire 128 /! in[1][2] [127:0] $end - $var wire 8 9! out[0][0] [7:0] $end - $var wire 8 :! out[0][1] [7:0] $end - $var wire 8 ;! out[0][2] [7:0] $end - $var wire 8 ! out[1][2] [7:0] $end + $var wire 1 N! clk $end + $var wire 128 *! in[0][0] [127:0] $end + $var wire 128 .! in[0][1] [127:0] $end + $var wire 128 2! in[0][2] [127:0] $end + $var wire 128 6! in[1][0] [127:0] $end + $var wire 128 :! in[1][1] [127:0] $end + $var wire 128 >! in[1][2] [127:0] $end + $var wire 8 H! out[0][0] [7:0] $end + $var wire 8 I! out[0][1] [7:0] $end + $var wire 8 J! out[0][2] [7:0] $end + $var wire 8 K! out[1][0] [7:0] $end + $var wire 8 L! out[1][1] [7:0] $end + $var wire 8 M! out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 v i [31:0] $end + $var wire 32 '! i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 w j [31:0] $end + $var wire 32 (! j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 x exp [7:0] $end + $var wire 8 )! exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5 $end - $var wire 1 Y! clk $end - $var wire 128 Z! in[0][0] [127:0] $end - $var wire 128 ^! in[0][1] [127:0] $end - $var wire 128 b! in[0][2] [127:0] $end - $var wire 128 f! in[1][0] [127:0] $end - $var wire 128 j! in[1][1] [127:0] $end - $var wire 128 n! in[1][2] [127:0] $end - $var wire 8 r! out[0][0] [7:0] $end - $var wire 8 s! out[0][1] [7:0] $end - $var wire 8 t! out[0][2] [7:0] $end - $var wire 8 u! out[1][0] [7:0] $end - $var wire 8 v! out[1][1] [7:0] $end - $var wire 8 w! out[1][2] [7:0] $end + $var wire 1 n! clk $end + $var wire 128 o! in[0][0] [127:0] $end + $var wire 128 s! in[0][1] [127:0] $end + $var wire 128 w! in[0][2] [127:0] $end + $var wire 128 {! in[1][0] [127:0] $end + $var wire 128 !" in[1][1] [127:0] $end + $var wire 128 %" in[1][2] [127:0] $end + $var wire 8 )" out[0][0] [7:0] $end + $var wire 8 *" out[0][1] [7:0] $end + $var wire 8 +" out[0][2] [7:0] $end + $var wire 8 ," out[1][0] [7:0] $end + $var wire 8 -" out[1][1] [7:0] $end + $var wire 8 ." out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 Y! clk $end - $var wire 128 Z! in[0][0] [127:0] $end - $var wire 128 ^! in[0][1] [127:0] $end - $var wire 128 b! in[0][2] [127:0] $end - $var wire 128 f! in[1][0] [127:0] $end - $var wire 128 j! in[1][1] [127:0] $end - $var wire 128 n! in[1][2] [127:0] $end - $var wire 8 r! out[0][0] [7:0] $end - $var wire 8 s! out[0][1] [7:0] $end - $var wire 8 t! out[0][2] [7:0] $end - $var wire 8 u! out[1][0] [7:0] $end - $var wire 8 v! out[1][1] [7:0] $end - $var wire 8 w! out[1][2] [7:0] $end - $var wire 32 R! count [31:0] $end - $var wire 8 H! val0[0] [7:0] $end - $var wire 8 I! val0[1] [7:0] $end - $var wire 8 J! val1[0] [7:0] $end - $var wire 8 K! val1[1] [7:0] $end - $var wire 8 L! val2[0] [7:0] $end - $var wire 8 M! val2[1] [7:0] $end - $var wire 8 N! val3[0] [7:0] $end - $var wire 8 O! val3[1] [7:0] $end + $var wire 1 n! clk $end + $var wire 128 o! in[0][0] [127:0] $end + $var wire 128 s! in[0][1] [127:0] $end + $var wire 128 w! in[0][2] [127:0] $end + $var wire 128 {! in[1][0] [127:0] $end + $var wire 128 !" in[1][1] [127:0] $end + $var wire 128 %" in[1][2] [127:0] $end + $var wire 8 )" out[0][0] [7:0] $end + $var wire 8 *" out[0][1] [7:0] $end + $var wire 8 +" out[0][2] [7:0] $end + $var wire 8 ," out[1][0] [7:0] $end + $var wire 8 -" out[1][1] [7:0] $end + $var wire 8 ." out[1][2] [7:0] $end + $var wire 32 g! count [31:0] $end + $var wire 8 W! val0[0] [7:0] $end + $var wire 8 X! val0[1] [7:0] $end + $var wire 8 Y! val1[0] [7:0] $end + $var wire 8 Z! val1[1] [7:0] $end + $var wire 8 [! val2[0] [7:0] $end + $var wire 8 \! val2[1] [7:0] $end + $var wire 8 ]! val3[0] [7:0] $end + $var wire 8 ^! val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 x! P0 [31:0] $end - $var wire 32 y! P1 [31:0] $end - $var wire 8 H! out[0] [7:0] $end - $var wire 8 I! out[1] [7:0] $end + $var wire 8 _! out[0] [7:0] $end + $var wire 8 `! out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 x! P0 [31:0] $end - $var wire 32 y! P1 [31:0] $end - $var wire 8 J! out[0] [7:0] $end - $var wire 8 K! out[1] [7:0] $end + $var wire 8 a! out[0] [7:0] $end + $var wire 8 b! out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 x! P0 [31:0] $end - $var wire 32 y! P1 [31:0] $end - $var wire 8 L! out[0] [7:0] $end - $var wire 8 M! out[1] [7:0] $end + $var wire 8 c! out[0] [7:0] $end + $var wire 8 d! out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 P! out[0] [7:0] $end - $var wire 8 Q! out[1] [7:0] $end + $var wire 8 e! out[0] [7:0] $end + $var wire 8 f! out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 S! i [31:0] $end + $var wire 32 h! i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 T! j [31:0] $end + $var wire 32 i! j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 U! exp [127:0] $end + $var wire 128 j! exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end + $var wire 8 0" out[0] [7:0] $end + $var wire 8 1" out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 2" P0 [31:0] $end + $var wire 32 3" P1 [31:0] $end + $var wire 8 0" out[0] [7:0] $end + $var wire 8 1" out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end - $var wire 8 {! out[0] [7:0] $end - $var wire 8 |! out[1] [7:0] $end + $var wire 8 5" out[0] [7:0] $end + $var wire 8 6" out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 }! P0 [31:0] $end - $var wire 32 ~! P1 [31:0] $end - $var wire 8 {! out[0] [7:0] $end - $var wire 8 |! out[1] [7:0] $end + $var wire 32 7" P0 [31:0] $end + $var wire 32 8" P1 [31:0] $end + $var wire 8 5" out[0] [7:0] $end + $var wire 8 6" out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1 $end - $var wire 1 c" clk $end - $var wire 8 d" in [7:0] $end - $var wire 8 e" out [7:0] $end + $var wire 1 {" clk $end + $var wire 8 |" in [7:0] $end + $var wire 8 }" out [7:0] $end $scope module sub4_b $end - $var wire 32 f" P0 [31:0] $end - $var real 64 g" P1 $end - $var real 64 i" P3 $end - $var wire 1 c" clk $end - $var wire 8 d" in [7:0] $end - $var wire 8 e" out [7:0] $end - $var wire 8 "" ff [7:0] $end - $var wire 128 #" sub5_in[0][0] [127:0] $end - $var wire 128 '" sub5_in[0][1] [127:0] $end - $var wire 128 +" sub5_in[0][2] [127:0] $end - $var wire 128 /" sub5_in[1][0] [127:0] $end - $var wire 128 3" sub5_in[1][1] [127:0] $end - $var wire 128 7" sub5_in[1][2] [127:0] $end - $var wire 8 W" sub5_out[0][0] [7:0] $end - $var wire 8 X" sub5_out[0][1] [7:0] $end - $var wire 8 Y" sub5_out[0][2] [7:0] $end - $var wire 8 Z" sub5_out[1][0] [7:0] $end - $var wire 8 [" sub5_out[1][1] [7:0] $end - $var wire 8 \" sub5_out[1][2] [7:0] $end - $var wire 32 ;" count [31:0] $end + $var wire 32 ~" P0 [31:0] $end + $var real 64 !# P1 $end + $var real 64 ## P3 $end + $var wire 1 {" clk $end + $var wire 8 |" in [7:0] $end + $var wire 8 }" out [7:0] $end + $var wire 8 :" ff [7:0] $end + $var wire 128 ;" sub5_in[0][0] [127:0] $end + $var wire 128 ?" sub5_in[0][1] [127:0] $end + $var wire 128 C" sub5_in[0][2] [127:0] $end + $var wire 128 G" sub5_in[1][0] [127:0] $end + $var wire 128 K" sub5_in[1][1] [127:0] $end + $var wire 128 O" sub5_in[1][2] [127:0] $end + $var wire 8 o" sub5_out[0][0] [7:0] $end + $var wire 8 p" sub5_out[0][1] [7:0] $end + $var wire 8 q" sub5_out[0][2] [7:0] $end + $var wire 8 r" sub5_out[1][0] [7:0] $end + $var wire 8 s" sub5_out[1][1] [7:0] $end + $var wire 8 t" sub5_out[1][2] [7:0] $end + $var wire 32 S" count [31:0] $end $scope module i_sub5 $end - $var wire 1 c" clk $end - $var wire 128 ?" in[0][0] [127:0] $end - $var wire 128 C" in[0][1] [127:0] $end - $var wire 128 G" in[0][2] [127:0] $end - $var wire 128 K" in[1][0] [127:0] $end - $var wire 128 O" in[1][1] [127:0] $end - $var wire 128 S" in[1][2] [127:0] $end - $var wire 8 ]" out[0][0] [7:0] $end - $var wire 8 ^" out[0][1] [7:0] $end - $var wire 8 _" out[0][2] [7:0] $end - $var wire 8 `" out[1][0] [7:0] $end - $var wire 8 a" out[1][1] [7:0] $end - $var wire 8 b" out[1][2] [7:0] $end + $var wire 1 {" clk $end + $var wire 128 W" in[0][0] [127:0] $end + $var wire 128 [" in[0][1] [127:0] $end + $var wire 128 _" in[0][2] [127:0] $end + $var wire 128 c" in[1][0] [127:0] $end + $var wire 128 g" in[1][1] [127:0] $end + $var wire 128 k" in[1][2] [127:0] $end + $var wire 8 u" out[0][0] [7:0] $end + $var wire 8 v" out[0][1] [7:0] $end + $var wire 8 w" out[0][2] [7:0] $end + $var wire 8 x" out[1][0] [7:0] $end + $var wire 8 y" out[1][1] [7:0] $end + $var wire 8 z" out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 <" i [31:0] $end + $var wire 32 T" i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 =" j [31:0] $end + $var wire 32 U" j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 >" exp [7:0] $end + $var wire 8 V" exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5 $end - $var wire 1 }" clk $end - $var wire 128 ~" in[0][0] [127:0] $end - $var wire 128 $# in[0][1] [127:0] $end - $var wire 128 (# in[0][2] [127:0] $end - $var wire 128 ,# in[1][0] [127:0] $end - $var wire 128 0# in[1][1] [127:0] $end - $var wire 128 4# in[1][2] [127:0] $end - $var wire 8 8# out[0][0] [7:0] $end - $var wire 8 9# out[0][1] [7:0] $end - $var wire 8 :# out[0][2] [7:0] $end - $var wire 8 ;# out[1][0] [7:0] $end - $var wire 8 <# out[1][1] [7:0] $end - $var wire 8 =# out[1][2] [7:0] $end + $var wire 1 =# clk $end + $var wire 128 ># in[0][0] [127:0] $end + $var wire 128 B# in[0][1] [127:0] $end + $var wire 128 F# in[0][2] [127:0] $end + $var wire 128 J# in[1][0] [127:0] $end + $var wire 128 N# in[1][1] [127:0] $end + $var wire 128 R# in[1][2] [127:0] $end + $var wire 8 V# out[0][0] [7:0] $end + $var wire 8 W# out[0][1] [7:0] $end + $var wire 8 X# out[0][2] [7:0] $end + $var wire 8 Y# out[1][0] [7:0] $end + $var wire 8 Z# out[1][1] [7:0] $end + $var wire 8 [# out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 }" clk $end - $var wire 128 ~" in[0][0] [127:0] $end - $var wire 128 $# in[0][1] [127:0] $end - $var wire 128 (# in[0][2] [127:0] $end - $var wire 128 ,# in[1][0] [127:0] $end - $var wire 128 0# in[1][1] [127:0] $end - $var wire 128 4# in[1][2] [127:0] $end - $var wire 8 8# out[0][0] [7:0] $end - $var wire 8 9# out[0][1] [7:0] $end - $var wire 8 :# out[0][2] [7:0] $end - $var wire 8 ;# out[1][0] [7:0] $end - $var wire 8 <# out[1][1] [7:0] $end - $var wire 8 =# out[1][2] [7:0] $end - $var wire 32 v" count [31:0] $end - $var wire 8 l" val0[0] [7:0] $end - $var wire 8 m" val0[1] [7:0] $end - $var wire 8 n" val1[0] [7:0] $end - $var wire 8 o" val1[1] [7:0] $end - $var wire 8 p" val2[0] [7:0] $end - $var wire 8 q" val2[1] [7:0] $end - $var wire 8 r" val3[0] [7:0] $end - $var wire 8 s" val3[1] [7:0] $end + $var wire 1 =# clk $end + $var wire 128 ># in[0][0] [127:0] $end + $var wire 128 B# in[0][1] [127:0] $end + $var wire 128 F# in[0][2] [127:0] $end + $var wire 128 J# in[1][0] [127:0] $end + $var wire 128 N# in[1][1] [127:0] $end + $var wire 128 R# in[1][2] [127:0] $end + $var wire 8 V# out[0][0] [7:0] $end + $var wire 8 W# out[0][1] [7:0] $end + $var wire 8 X# out[0][2] [7:0] $end + $var wire 8 Y# out[1][0] [7:0] $end + $var wire 8 Z# out[1][1] [7:0] $end + $var wire 8 [# out[1][2] [7:0] $end + $var wire 32 6# count [31:0] $end + $var wire 8 &# val0[0] [7:0] $end + $var wire 8 '# val0[1] [7:0] $end + $var wire 8 (# val1[0] [7:0] $end + $var wire 8 )# val1[1] [7:0] $end + $var wire 8 *# val2[0] [7:0] $end + $var wire 8 +# val2[1] [7:0] $end + $var wire 8 ,# val3[0] [7:0] $end + $var wire 8 -# val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 ># P0 [31:0] $end - $var wire 32 ?# P1 [31:0] $end - $var wire 8 l" out[0] [7:0] $end - $var wire 8 m" out[1] [7:0] $end + $var wire 8 .# out[0] [7:0] $end + $var wire 8 /# out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 ># P0 [31:0] $end - $var wire 32 ?# P1 [31:0] $end - $var wire 8 n" out[0] [7:0] $end - $var wire 8 o" out[1] [7:0] $end + $var wire 8 0# out[0] [7:0] $end + $var wire 8 1# out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 ># P0 [31:0] $end - $var wire 32 ?# P1 [31:0] $end - $var wire 8 p" out[0] [7:0] $end - $var wire 8 q" out[1] [7:0] $end + $var wire 8 2# out[0] [7:0] $end + $var wire 8 3# out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 t" out[0] [7:0] $end - $var wire 8 u" out[1] [7:0] $end + $var wire 8 4# out[0] [7:0] $end + $var wire 8 5# out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 w" i [31:0] $end + $var wire 32 7# i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 x" j [31:0] $end + $var wire 32 8# j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 y" exp [127:0] $end + $var wire 128 9# exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end + $var wire 8 ]# out[0] [7:0] $end + $var wire 8 ^# out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 _# P0 [31:0] $end + $var wire 32 `# P1 [31:0] $end + $var wire 8 ]# out[0] [7:0] $end + $var wire 8 ^# out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub2.sub2.i_sub3.i_sub3.sub3_c.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end - $var wire 8 A# out[0] [7:0] $end - $var wire 8 B# out[1] [7:0] $end + $var wire 8 b# out[0] [7:0] $end + $var wire 8 c# out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 C# P0 [31:0] $end - $var wire 32 D# P1 [31:0] $end - $var wire 8 A# out[0] [7:0] $end - $var wire 8 B# out[1] [7:0] $end + $var wire 32 d# P0 [31:0] $end + $var wire 32 e# P1 [31:0] $end + $var wire 8 b# out[0] [7:0] $end + $var wire 8 c# out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3_2 $end - $var wire 1 F# clk $end - $var wire 8 G# in [7:0] $end - $var wire 8 H# out [7:0] $end + $var wire 1 g# clk $end + $var wire 8 h# in [7:0] $end + $var wire 8 i# out [7:0] $end $scope module sub3_2 $end - $var wire 8 K# P0 [7:0] $end - $var wire 32 L# UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 M# UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 N# UNUSED [15:0] $end - $var wire 1 F# clk $end - $var wire 8 G# in [7:0] $end - $var wire 8 H# out [7:0] $end - $var wire 8 I# ff [7:0] $end - $var wire 8 H# out4 [7:0] $end - $var wire 8 J# out4_2 [7:0] $end + $var wire 8 l# P0 [7:0] $end + $var wire 32 m# UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 n# UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 o# UNUSED [15:0] $end + $var wire 1 g# clk $end + $var wire 8 h# in [7:0] $end + $var wire 8 i# out [7:0] $end + $var wire 8 j# ff [7:0] $end + $var wire 8 i# out4 [7:0] $end + $var wire 8 k# out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 1 F# clk $end - $var wire 8 I# in [7:0] $end - $var wire 8 H# out [7:0] $end + $var wire 1 g# clk $end + $var wire 8 j# in [7:0] $end + $var wire 8 i# out [7:0] $end $upscope $end $scope module i_sub4_1 $end - $var wire 1 F# clk $end - $var wire 8 I# in [7:0] $end - $var wire 8 J# out [7:0] $end + $var wire 1 g# clk $end + $var wire 8 j# in [7:0] $end + $var wire 8 k# out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0 $end - $var wire 1 3$ clk $end - $var wire 8 4$ in [7:0] $end - $var wire 8 5$ out [7:0] $end + $var wire 1 T$ clk $end + $var wire 8 U$ in [7:0] $end + $var wire 8 V$ out [7:0] $end $scope module sub4_2 $end - $var wire 32 6$ P0 [31:0] $end - $var real 64 7$ P1 $end - $var real 64 9$ P3 $end - $var wire 1 3$ clk $end - $var wire 8 4$ in [7:0] $end - $var wire 8 5$ out [7:0] $end - $var wire 8 P# ff [7:0] $end - $var wire 128 Q# sub5_in[0][0] [127:0] $end - $var wire 128 U# sub5_in[0][1] [127:0] $end - $var wire 128 Y# sub5_in[0][2] [127:0] $end - $var wire 128 ]# sub5_in[1][0] [127:0] $end - $var wire 128 a# sub5_in[1][1] [127:0] $end - $var wire 128 e# sub5_in[1][2] [127:0] $end - $var wire 8 '$ sub5_out[0][0] [7:0] $end - $var wire 8 ($ sub5_out[0][1] [7:0] $end - $var wire 8 )$ sub5_out[0][2] [7:0] $end - $var wire 8 *$ sub5_out[1][0] [7:0] $end - $var wire 8 +$ sub5_out[1][1] [7:0] $end - $var wire 8 ,$ sub5_out[1][2] [7:0] $end - $var wire 32 i# count [31:0] $end + $var wire 32 W$ P0 [31:0] $end + $var real 64 X$ P1 $end + $var real 64 Z$ P3 $end + $var wire 1 T$ clk $end + $var wire 8 U$ in [7:0] $end + $var wire 8 V$ out [7:0] $end + $var wire 8 q# ff [7:0] $end + $var wire 128 r# sub5_in[0][0] [127:0] $end + $var wire 128 v# sub5_in[0][1] [127:0] $end + $var wire 128 z# sub5_in[0][2] [127:0] $end + $var wire 128 ~# sub5_in[1][0] [127:0] $end + $var wire 128 $$ sub5_in[1][1] [127:0] $end + $var wire 128 ($ sub5_in[1][2] [127:0] $end + $var wire 8 H$ sub5_out[0][0] [7:0] $end + $var wire 8 I$ sub5_out[0][1] [7:0] $end + $var wire 8 J$ sub5_out[0][2] [7:0] $end + $var wire 8 K$ sub5_out[1][0] [7:0] $end + $var wire 8 L$ sub5_out[1][1] [7:0] $end + $var wire 8 M$ sub5_out[1][2] [7:0] $end + $var wire 32 ,$ count [31:0] $end $scope module i_sub5 $end - $var wire 1 3$ clk $end - $var wire 128 m# in[0][0] [127:0] $end - $var wire 128 q# in[0][1] [127:0] $end - $var wire 128 u# in[0][2] [127:0] $end - $var wire 128 y# in[1][0] [127:0] $end - $var wire 128 }# in[1][1] [127:0] $end - $var wire 128 #$ in[1][2] [127:0] $end - $var wire 8 -$ out[0][0] [7:0] $end - $var wire 8 .$ out[0][1] [7:0] $end - $var wire 8 /$ out[0][2] [7:0] $end - $var wire 8 0$ out[1][0] [7:0] $end - $var wire 8 1$ out[1][1] [7:0] $end - $var wire 8 2$ out[1][2] [7:0] $end + $var wire 1 T$ clk $end + $var wire 128 0$ in[0][0] [127:0] $end + $var wire 128 4$ in[0][1] [127:0] $end + $var wire 128 8$ in[0][2] [127:0] $end + $var wire 128 <$ in[1][0] [127:0] $end + $var wire 128 @$ in[1][1] [127:0] $end + $var wire 128 D$ in[1][2] [127:0] $end + $var wire 8 N$ out[0][0] [7:0] $end + $var wire 8 O$ out[0][1] [7:0] $end + $var wire 8 P$ out[0][2] [7:0] $end + $var wire 8 Q$ out[1][0] [7:0] $end + $var wire 8 R$ out[1][1] [7:0] $end + $var wire 8 S$ out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 j# i [31:0] $end + $var wire 32 -$ i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 k# j [31:0] $end + $var wire 32 .$ j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 l# exp [7:0] $end + $var wire 8 /$ exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5 $end - $var wire 1 M$ clk $end - $var wire 128 N$ in[0][0] [127:0] $end - $var wire 128 R$ in[0][1] [127:0] $end - $var wire 128 V$ in[0][2] [127:0] $end - $var wire 128 Z$ in[1][0] [127:0] $end - $var wire 128 ^$ in[1][1] [127:0] $end - $var wire 128 b$ in[1][2] [127:0] $end - $var wire 8 f$ out[0][0] [7:0] $end - $var wire 8 g$ out[0][1] [7:0] $end - $var wire 8 h$ out[0][2] [7:0] $end - $var wire 8 i$ out[1][0] [7:0] $end - $var wire 8 j$ out[1][1] [7:0] $end - $var wire 8 k$ out[1][2] [7:0] $end + $var wire 1 t$ clk $end + $var wire 128 u$ in[0][0] [127:0] $end + $var wire 128 y$ in[0][1] [127:0] $end + $var wire 128 }$ in[0][2] [127:0] $end + $var wire 128 #% in[1][0] [127:0] $end + $var wire 128 '% in[1][1] [127:0] $end + $var wire 128 +% in[1][2] [127:0] $end + $var wire 8 /% out[0][0] [7:0] $end + $var wire 8 0% out[0][1] [7:0] $end + $var wire 8 1% out[0][2] [7:0] $end + $var wire 8 2% out[1][0] [7:0] $end + $var wire 8 3% out[1][1] [7:0] $end + $var wire 8 4% out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 M$ clk $end - $var wire 128 N$ in[0][0] [127:0] $end - $var wire 128 R$ in[0][1] [127:0] $end - $var wire 128 V$ in[0][2] [127:0] $end - $var wire 128 Z$ in[1][0] [127:0] $end - $var wire 128 ^$ in[1][1] [127:0] $end - $var wire 128 b$ in[1][2] [127:0] $end - $var wire 8 f$ out[0][0] [7:0] $end - $var wire 8 g$ out[0][1] [7:0] $end - $var wire 8 h$ out[0][2] [7:0] $end - $var wire 8 i$ out[1][0] [7:0] $end - $var wire 8 j$ out[1][1] [7:0] $end - $var wire 8 k$ out[1][2] [7:0] $end - $var wire 32 F$ count [31:0] $end - $var wire 8 <$ val0[0] [7:0] $end - $var wire 8 =$ val0[1] [7:0] $end - $var wire 8 >$ val1[0] [7:0] $end - $var wire 8 ?$ val1[1] [7:0] $end - $var wire 8 @$ val2[0] [7:0] $end - $var wire 8 A$ val2[1] [7:0] $end - $var wire 8 B$ val3[0] [7:0] $end - $var wire 8 C$ val3[1] [7:0] $end + $var wire 1 t$ clk $end + $var wire 128 u$ in[0][0] [127:0] $end + $var wire 128 y$ in[0][1] [127:0] $end + $var wire 128 }$ in[0][2] [127:0] $end + $var wire 128 #% in[1][0] [127:0] $end + $var wire 128 '% in[1][1] [127:0] $end + $var wire 128 +% in[1][2] [127:0] $end + $var wire 8 /% out[0][0] [7:0] $end + $var wire 8 0% out[0][1] [7:0] $end + $var wire 8 1% out[0][2] [7:0] $end + $var wire 8 2% out[1][0] [7:0] $end + $var wire 8 3% out[1][1] [7:0] $end + $var wire 8 4% out[1][2] [7:0] $end + $var wire 32 m$ count [31:0] $end + $var wire 8 ]$ val0[0] [7:0] $end + $var wire 8 ^$ val0[1] [7:0] $end + $var wire 8 _$ val1[0] [7:0] $end + $var wire 8 `$ val1[1] [7:0] $end + $var wire 8 a$ val2[0] [7:0] $end + $var wire 8 b$ val2[1] [7:0] $end + $var wire 8 c$ val3[0] [7:0] $end + $var wire 8 d$ val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 l$ P0 [31:0] $end - $var wire 32 m$ P1 [31:0] $end - $var wire 8 <$ out[0] [7:0] $end - $var wire 8 =$ out[1] [7:0] $end + $var wire 8 e$ out[0] [7:0] $end + $var wire 8 f$ out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 l$ P0 [31:0] $end - $var wire 32 m$ P1 [31:0] $end - $var wire 8 >$ out[0] [7:0] $end - $var wire 8 ?$ out[1] [7:0] $end + $var wire 8 g$ out[0] [7:0] $end + $var wire 8 h$ out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 l$ P0 [31:0] $end - $var wire 32 m$ P1 [31:0] $end - $var wire 8 @$ out[0] [7:0] $end - $var wire 8 A$ out[1] [7:0] $end + $var wire 8 i$ out[0] [7:0] $end + $var wire 8 j$ out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 D$ out[0] [7:0] $end - $var wire 8 E$ out[1] [7:0] $end + $var wire 8 k$ out[0] [7:0] $end + $var wire 8 l$ out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 G$ i [31:0] $end + $var wire 32 n$ i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 H$ j [31:0] $end + $var wire 32 o$ j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 I$ exp [127:0] $end + $var wire 128 p$ exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end + $var wire 8 6% out[0] [7:0] $end + $var wire 8 7% out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 8% P0 [31:0] $end + $var wire 32 9% P1 [31:0] $end + $var wire 8 6% out[0] [7:0] $end + $var wire 8 7% out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end - $var wire 8 o$ out[0] [7:0] $end - $var wire 8 p$ out[1] [7:0] $end + $var wire 8 ;% out[0] [7:0] $end + $var wire 8 <% out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 q$ P0 [31:0] $end - $var wire 32 r$ P1 [31:0] $end - $var wire 8 o$ out[0] [7:0] $end - $var wire 8 p$ out[1] [7:0] $end + $var wire 32 =% P0 [31:0] $end + $var wire 32 >% P1 [31:0] $end + $var wire 8 ;% out[0] [7:0] $end + $var wire 8 <% out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1 $end - $var wire 1 W% clk $end - $var wire 8 X% in [7:0] $end - $var wire 8 Y% out [7:0] $end + $var wire 1 #& clk $end + $var wire 8 $& in [7:0] $end + $var wire 8 %& out [7:0] $end $scope module sub4_b $end - $var wire 32 Z% P0 [31:0] $end - $var real 64 [% P1 $end - $var real 64 ]% P3 $end - $var wire 1 W% clk $end - $var wire 8 X% in [7:0] $end - $var wire 8 Y% out [7:0] $end - $var wire 8 t$ ff [7:0] $end - $var wire 128 u$ sub5_in[0][0] [127:0] $end - $var wire 128 y$ sub5_in[0][1] [127:0] $end - $var wire 128 }$ sub5_in[0][2] [127:0] $end - $var wire 128 #% sub5_in[1][0] [127:0] $end - $var wire 128 '% sub5_in[1][1] [127:0] $end - $var wire 128 +% sub5_in[1][2] [127:0] $end - $var wire 8 K% sub5_out[0][0] [7:0] $end - $var wire 8 L% sub5_out[0][1] [7:0] $end - $var wire 8 M% sub5_out[0][2] [7:0] $end - $var wire 8 N% sub5_out[1][0] [7:0] $end - $var wire 8 O% sub5_out[1][1] [7:0] $end - $var wire 8 P% sub5_out[1][2] [7:0] $end - $var wire 32 /% count [31:0] $end + $var wire 32 && P0 [31:0] $end + $var real 64 '& P1 $end + $var real 64 )& P3 $end + $var wire 1 #& clk $end + $var wire 8 $& in [7:0] $end + $var wire 8 %& out [7:0] $end + $var wire 8 @% ff [7:0] $end + $var wire 128 A% sub5_in[0][0] [127:0] $end + $var wire 128 E% sub5_in[0][1] [127:0] $end + $var wire 128 I% sub5_in[0][2] [127:0] $end + $var wire 128 M% sub5_in[1][0] [127:0] $end + $var wire 128 Q% sub5_in[1][1] [127:0] $end + $var wire 128 U% sub5_in[1][2] [127:0] $end + $var wire 8 u% sub5_out[0][0] [7:0] $end + $var wire 8 v% sub5_out[0][1] [7:0] $end + $var wire 8 w% sub5_out[0][2] [7:0] $end + $var wire 8 x% sub5_out[1][0] [7:0] $end + $var wire 8 y% sub5_out[1][1] [7:0] $end + $var wire 8 z% sub5_out[1][2] [7:0] $end + $var wire 32 Y% count [31:0] $end $scope module i_sub5 $end - $var wire 1 W% clk $end - $var wire 128 3% in[0][0] [127:0] $end - $var wire 128 7% in[0][1] [127:0] $end - $var wire 128 ;% in[0][2] [127:0] $end - $var wire 128 ?% in[1][0] [127:0] $end - $var wire 128 C% in[1][1] [127:0] $end - $var wire 128 G% in[1][2] [127:0] $end - $var wire 8 Q% out[0][0] [7:0] $end - $var wire 8 R% out[0][1] [7:0] $end - $var wire 8 S% out[0][2] [7:0] $end - $var wire 8 T% out[1][0] [7:0] $end - $var wire 8 U% out[1][1] [7:0] $end - $var wire 8 V% out[1][2] [7:0] $end + $var wire 1 #& clk $end + $var wire 128 ]% in[0][0] [127:0] $end + $var wire 128 a% in[0][1] [127:0] $end + $var wire 128 e% in[0][2] [127:0] $end + $var wire 128 i% in[1][0] [127:0] $end + $var wire 128 m% in[1][1] [127:0] $end + $var wire 128 q% in[1][2] [127:0] $end + $var wire 8 {% out[0][0] [7:0] $end + $var wire 8 |% out[0][1] [7:0] $end + $var wire 8 }% out[0][2] [7:0] $end + $var wire 8 ~% out[1][0] [7:0] $end + $var wire 8 !& out[1][1] [7:0] $end + $var wire 8 "& out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 0% i [31:0] $end + $var wire 32 Z% i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 1% j [31:0] $end + $var wire 32 [% j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 2% exp [7:0] $end + $var wire 8 \% exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5 $end - $var wire 1 q% clk $end - $var wire 128 r% in[0][0] [127:0] $end - $var wire 128 v% in[0][1] [127:0] $end - $var wire 128 z% in[0][2] [127:0] $end - $var wire 128 ~% in[1][0] [127:0] $end - $var wire 128 $& in[1][1] [127:0] $end - $var wire 128 (& in[1][2] [127:0] $end - $var wire 8 ,& out[0][0] [7:0] $end - $var wire 8 -& out[0][1] [7:0] $end - $var wire 8 .& out[0][2] [7:0] $end - $var wire 8 /& out[1][0] [7:0] $end - $var wire 8 0& out[1][1] [7:0] $end - $var wire 8 1& out[1][2] [7:0] $end + $var wire 1 C& clk $end + $var wire 128 D& in[0][0] [127:0] $end + $var wire 128 H& in[0][1] [127:0] $end + $var wire 128 L& in[0][2] [127:0] $end + $var wire 128 P& in[1][0] [127:0] $end + $var wire 128 T& in[1][1] [127:0] $end + $var wire 128 X& in[1][2] [127:0] $end + $var wire 8 \& out[0][0] [7:0] $end + $var wire 8 ]& out[0][1] [7:0] $end + $var wire 8 ^& out[0][2] [7:0] $end + $var wire 8 _& out[1][0] [7:0] $end + $var wire 8 `& out[1][1] [7:0] $end + $var wire 8 a& out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 q% clk $end - $var wire 128 r% in[0][0] [127:0] $end - $var wire 128 v% in[0][1] [127:0] $end - $var wire 128 z% in[0][2] [127:0] $end - $var wire 128 ~% in[1][0] [127:0] $end - $var wire 128 $& in[1][1] [127:0] $end - $var wire 128 (& in[1][2] [127:0] $end - $var wire 8 ,& out[0][0] [7:0] $end - $var wire 8 -& out[0][1] [7:0] $end - $var wire 8 .& out[0][2] [7:0] $end - $var wire 8 /& out[1][0] [7:0] $end - $var wire 8 0& out[1][1] [7:0] $end - $var wire 8 1& out[1][2] [7:0] $end - $var wire 32 j% count [31:0] $end - $var wire 8 `% val0[0] [7:0] $end - $var wire 8 a% val0[1] [7:0] $end - $var wire 8 b% val1[0] [7:0] $end - $var wire 8 c% val1[1] [7:0] $end - $var wire 8 d% val2[0] [7:0] $end - $var wire 8 e% val2[1] [7:0] $end - $var wire 8 f% val3[0] [7:0] $end - $var wire 8 g% val3[1] [7:0] $end + $var wire 1 C& clk $end + $var wire 128 D& in[0][0] [127:0] $end + $var wire 128 H& in[0][1] [127:0] $end + $var wire 128 L& in[0][2] [127:0] $end + $var wire 128 P& in[1][0] [127:0] $end + $var wire 128 T& in[1][1] [127:0] $end + $var wire 128 X& in[1][2] [127:0] $end + $var wire 8 \& out[0][0] [7:0] $end + $var wire 8 ]& out[0][1] [7:0] $end + $var wire 8 ^& out[0][2] [7:0] $end + $var wire 8 _& out[1][0] [7:0] $end + $var wire 8 `& out[1][1] [7:0] $end + $var wire 8 a& out[1][2] [7:0] $end + $var wire 32 <& count [31:0] $end + $var wire 8 ,& val0[0] [7:0] $end + $var wire 8 -& val0[1] [7:0] $end + $var wire 8 .& val1[0] [7:0] $end + $var wire 8 /& val1[1] [7:0] $end + $var wire 8 0& val2[0] [7:0] $end + $var wire 8 1& val2[1] [7:0] $end + $var wire 8 2& val3[0] [7:0] $end + $var wire 8 3& val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 2& P0 [31:0] $end - $var wire 32 3& P1 [31:0] $end - $var wire 8 `% out[0] [7:0] $end - $var wire 8 a% out[1] [7:0] $end + $var wire 8 4& out[0] [7:0] $end + $var wire 8 5& out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 2& P0 [31:0] $end - $var wire 32 3& P1 [31:0] $end - $var wire 8 b% out[0] [7:0] $end - $var wire 8 c% out[1] [7:0] $end + $var wire 8 6& out[0] [7:0] $end + $var wire 8 7& out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 2& P0 [31:0] $end - $var wire 32 3& P1 [31:0] $end - $var wire 8 d% out[0] [7:0] $end - $var wire 8 e% out[1] [7:0] $end + $var wire 8 8& out[0] [7:0] $end + $var wire 8 9& out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 h% out[0] [7:0] $end - $var wire 8 i% out[1] [7:0] $end + $var wire 8 :& out[0] [7:0] $end + $var wire 8 ;& out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 k% i [31:0] $end + $var wire 32 =& i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 l% j [31:0] $end + $var wire 32 >& j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 m% exp [127:0] $end + $var wire 128 ?& exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end + $var wire 8 c& out[0] [7:0] $end + $var wire 8 d& out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 e& P0 [31:0] $end + $var wire 32 f& P1 [31:0] $end + $var wire 8 c& out[0] [7:0] $end + $var wire 8 d& out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub3_2.sub3_2.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end - $var wire 8 5& out[0] [7:0] $end - $var wire 8 6& out[1] [7:0] $end + $var wire 8 h& out[0] [7:0] $end + $var wire 8 i& out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 7& P0 [31:0] $end - $var wire 32 8& P1 [31:0] $end - $var wire 8 5& out[0] [7:0] $end - $var wire 8 6& out[1] [7:0] $end + $var wire 32 j& P0 [31:0] $end + $var wire 32 k& P1 [31:0] $end + $var wire 8 h& out[0] [7:0] $end + $var wire 8 i& out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3 $end - $var wire 1 :& clk $end - $var wire 8 ;& in [7:0] $end - $var wire 8 <& out [7:0] $end + $var wire 1 m& clk $end + $var wire 8 n& in [7:0] $end + $var wire 8 o& out [7:0] $end $scope module sub3_d $end - $var wire 8 ?& P0 [7:0] $end - $var wire 32 @& UNPACKED_ARRAY[0] [31:0] $end - $var wire 32 A& UNPACKED_ARRAY[1] [31:0] $end - $var wire 16 B& UNUSED [15:0] $end - $var wire 1 :& clk $end - $var wire 8 ;& in [7:0] $end - $var wire 8 <& out [7:0] $end - $var wire 8 =& ff [7:0] $end - $var wire 8 <& out4 [7:0] $end - $var wire 8 >& out4_2 [7:0] $end + $var wire 8 r& P0 [7:0] $end + $var wire 32 s& UNPACKED_ARRAY[0] [31:0] $end + $var wire 32 t& UNPACKED_ARRAY[1] [31:0] $end + $var wire 16 u& UNUSED [15:0] $end + $var wire 1 m& clk $end + $var wire 8 n& in [7:0] $end + $var wire 8 o& out [7:0] $end + $var wire 8 p& ff [7:0] $end + $var wire 8 o& out4 [7:0] $end + $var wire 8 q& out4_2 [7:0] $end $scope module i_sub4_0 $end - $var wire 1 :& clk $end - $var wire 8 =& in [7:0] $end - $var wire 8 <& out [7:0] $end + $var wire 1 m& clk $end + $var wire 8 p& in [7:0] $end + $var wire 8 o& out [7:0] $end $upscope $end $scope module i_sub4_1 $end - $var wire 1 :& clk $end - $var wire 8 =& in [7:0] $end - $var wire 8 >& out [7:0] $end + $var wire 1 m& clk $end + $var wire 8 p& in [7:0] $end + $var wire 8 q& out [7:0] $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0 $end - $var wire 1 '' clk $end - $var wire 8 (' in [7:0] $end - $var wire 8 )' out [7:0] $end + $var wire 1 Z' clk $end + $var wire 8 [' in [7:0] $end + $var wire 8 \' out [7:0] $end $scope module sub4_2 $end - $var wire 32 *' P0 [31:0] $end - $var real 64 +' P1 $end - $var real 64 -' P3 $end - $var wire 1 '' clk $end - $var wire 8 (' in [7:0] $end - $var wire 8 )' out [7:0] $end - $var wire 8 D& ff [7:0] $end - $var wire 128 E& sub5_in[0][0] [127:0] $end - $var wire 128 I& sub5_in[0][1] [127:0] $end - $var wire 128 M& sub5_in[0][2] [127:0] $end - $var wire 128 Q& sub5_in[1][0] [127:0] $end - $var wire 128 U& sub5_in[1][1] [127:0] $end - $var wire 128 Y& sub5_in[1][2] [127:0] $end - $var wire 8 y& sub5_out[0][0] [7:0] $end - $var wire 8 z& sub5_out[0][1] [7:0] $end - $var wire 8 {& sub5_out[0][2] [7:0] $end - $var wire 8 |& sub5_out[1][0] [7:0] $end - $var wire 8 }& sub5_out[1][1] [7:0] $end - $var wire 8 ~& sub5_out[1][2] [7:0] $end - $var wire 32 ]& count [31:0] $end + $var wire 32 ]' P0 [31:0] $end + $var real 64 ^' P1 $end + $var real 64 `' P3 $end + $var wire 1 Z' clk $end + $var wire 8 [' in [7:0] $end + $var wire 8 \' out [7:0] $end + $var wire 8 w& ff [7:0] $end + $var wire 128 x& sub5_in[0][0] [127:0] $end + $var wire 128 |& sub5_in[0][1] [127:0] $end + $var wire 128 "' sub5_in[0][2] [127:0] $end + $var wire 128 &' sub5_in[1][0] [127:0] $end + $var wire 128 *' sub5_in[1][1] [127:0] $end + $var wire 128 .' sub5_in[1][2] [127:0] $end + $var wire 8 N' sub5_out[0][0] [7:0] $end + $var wire 8 O' sub5_out[0][1] [7:0] $end + $var wire 8 P' sub5_out[0][2] [7:0] $end + $var wire 8 Q' sub5_out[1][0] [7:0] $end + $var wire 8 R' sub5_out[1][1] [7:0] $end + $var wire 8 S' sub5_out[1][2] [7:0] $end + $var wire 32 2' count [31:0] $end $scope module i_sub5 $end - $var wire 1 '' clk $end - $var wire 128 a& in[0][0] [127:0] $end - $var wire 128 e& in[0][1] [127:0] $end - $var wire 128 i& in[0][2] [127:0] $end - $var wire 128 m& in[1][0] [127:0] $end - $var wire 128 q& in[1][1] [127:0] $end - $var wire 128 u& in[1][2] [127:0] $end - $var wire 8 !' out[0][0] [7:0] $end - $var wire 8 "' out[0][1] [7:0] $end - $var wire 8 #' out[0][2] [7:0] $end - $var wire 8 $' out[1][0] [7:0] $end - $var wire 8 %' out[1][1] [7:0] $end - $var wire 8 &' out[1][2] [7:0] $end + $var wire 1 Z' clk $end + $var wire 128 6' in[0][0] [127:0] $end + $var wire 128 :' in[0][1] [127:0] $end + $var wire 128 >' in[0][2] [127:0] $end + $var wire 128 B' in[1][0] [127:0] $end + $var wire 128 F' in[1][1] [127:0] $end + $var wire 128 J' in[1][2] [127:0] $end + $var wire 8 T' out[0][0] [7:0] $end + $var wire 8 U' out[0][1] [7:0] $end + $var wire 8 V' out[0][2] [7:0] $end + $var wire 8 W' out[1][0] [7:0] $end + $var wire 8 X' out[1][1] [7:0] $end + $var wire 8 Y' out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 ^& i [31:0] $end + $var wire 32 3' i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 _& j [31:0] $end + $var wire 32 4' j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 `& exp [7:0] $end + $var wire 8 5' exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5 $end - $var wire 1 A' clk $end - $var wire 128 B' in[0][0] [127:0] $end - $var wire 128 F' in[0][1] [127:0] $end - $var wire 128 J' in[0][2] [127:0] $end - $var wire 128 N' in[1][0] [127:0] $end - $var wire 128 R' in[1][1] [127:0] $end - $var wire 128 V' in[1][2] [127:0] $end - $var wire 8 Z' out[0][0] [7:0] $end - $var wire 8 [' out[0][1] [7:0] $end - $var wire 8 \' out[0][2] [7:0] $end - $var wire 8 ]' out[1][0] [7:0] $end - $var wire 8 ^' out[1][1] [7:0] $end - $var wire 8 _' out[1][2] [7:0] $end + $var wire 1 z' clk $end + $var wire 128 {' in[0][0] [127:0] $end + $var wire 128 !( in[0][1] [127:0] $end + $var wire 128 %( in[0][2] [127:0] $end + $var wire 128 )( in[1][0] [127:0] $end + $var wire 128 -( in[1][1] [127:0] $end + $var wire 128 1( in[1][2] [127:0] $end + $var wire 8 5( out[0][0] [7:0] $end + $var wire 8 6( out[0][1] [7:0] $end + $var wire 8 7( out[0][2] [7:0] $end + $var wire 8 8( out[1][0] [7:0] $end + $var wire 8 9( out[1][1] [7:0] $end + $var wire 8 :( out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 A' clk $end - $var wire 128 B' in[0][0] [127:0] $end - $var wire 128 F' in[0][1] [127:0] $end - $var wire 128 J' in[0][2] [127:0] $end - $var wire 128 N' in[1][0] [127:0] $end - $var wire 128 R' in[1][1] [127:0] $end - $var wire 128 V' in[1][2] [127:0] $end - $var wire 8 Z' out[0][0] [7:0] $end - $var wire 8 [' out[0][1] [7:0] $end - $var wire 8 \' out[0][2] [7:0] $end - $var wire 8 ]' out[1][0] [7:0] $end - $var wire 8 ^' out[1][1] [7:0] $end - $var wire 8 _' out[1][2] [7:0] $end - $var wire 32 :' count [31:0] $end - $var wire 8 0' val0[0] [7:0] $end - $var wire 8 1' val0[1] [7:0] $end - $var wire 8 2' val1[0] [7:0] $end - $var wire 8 3' val1[1] [7:0] $end - $var wire 8 4' val2[0] [7:0] $end - $var wire 8 5' val2[1] [7:0] $end - $var wire 8 6' val3[0] [7:0] $end - $var wire 8 7' val3[1] [7:0] $end + $var wire 1 z' clk $end + $var wire 128 {' in[0][0] [127:0] $end + $var wire 128 !( in[0][1] [127:0] $end + $var wire 128 %( in[0][2] [127:0] $end + $var wire 128 )( in[1][0] [127:0] $end + $var wire 128 -( in[1][1] [127:0] $end + $var wire 128 1( in[1][2] [127:0] $end + $var wire 8 5( out[0][0] [7:0] $end + $var wire 8 6( out[0][1] [7:0] $end + $var wire 8 7( out[0][2] [7:0] $end + $var wire 8 8( out[1][0] [7:0] $end + $var wire 8 9( out[1][1] [7:0] $end + $var wire 8 :( out[1][2] [7:0] $end + $var wire 32 s' count [31:0] $end + $var wire 8 c' val0[0] [7:0] $end + $var wire 8 d' val0[1] [7:0] $end + $var wire 8 e' val1[0] [7:0] $end + $var wire 8 f' val1[1] [7:0] $end + $var wire 8 g' val2[0] [7:0] $end + $var wire 8 h' val2[1] [7:0] $end + $var wire 8 i' val3[0] [7:0] $end + $var wire 8 j' val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 `' P0 [31:0] $end - $var wire 32 a' P1 [31:0] $end - $var wire 8 0' out[0] [7:0] $end - $var wire 8 1' out[1] [7:0] $end + $var wire 8 k' out[0] [7:0] $end + $var wire 8 l' out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 `' P0 [31:0] $end - $var wire 32 a' P1 [31:0] $end - $var wire 8 2' out[0] [7:0] $end - $var wire 8 3' out[1] [7:0] $end + $var wire 8 m' out[0] [7:0] $end + $var wire 8 n' out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 `' P0 [31:0] $end - $var wire 32 a' P1 [31:0] $end - $var wire 8 4' out[0] [7:0] $end - $var wire 8 5' out[1] [7:0] $end + $var wire 8 o' out[0] [7:0] $end + $var wire 8 p' out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 8' out[0] [7:0] $end - $var wire 8 9' out[1] [7:0] $end + $var wire 8 q' out[0] [7:0] $end + $var wire 8 r' out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 ;' i [31:0] $end + $var wire 32 t' i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 <' j [31:0] $end + $var wire 32 u' j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 =' exp [127:0] $end + $var wire 128 v' exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub0 $end + $var wire 8 <( out[0] [7:0] $end + $var wire 8 =( out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 >( P0 [31:0] $end + $var wire 32 ?( P1 [31:0] $end + $var wire 8 <( out[0] [7:0] $end + $var wire 8 =( out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_0.sub4_2.i_sub5.sub5.i_sub3 $end - $var wire 8 c' out[0] [7:0] $end - $var wire 8 d' out[1] [7:0] $end + $var wire 8 A( out[0] [7:0] $end + $var wire 8 B( out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 e' P0 [31:0] $end - $var wire 32 f' P1 [31:0] $end - $var wire 8 c' out[0] [7:0] $end - $var wire 8 d' out[1] [7:0] $end + $var wire 32 C( P0 [31:0] $end + $var wire 32 D( P1 [31:0] $end + $var wire 8 A( out[0] [7:0] $end + $var wire 8 B( out[1] [7:0] $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1 $end - $var wire 1 K( clk $end - $var wire 8 L( in [7:0] $end - $var wire 8 M( out [7:0] $end + $var wire 1 )) clk $end + $var wire 8 *) in [7:0] $end + $var wire 8 +) out [7:0] $end $scope module sub4_b $end - $var wire 32 N( P0 [31:0] $end - $var real 64 O( P1 $end - $var real 64 Q( P3 $end - $var wire 1 K( clk $end - $var wire 8 L( in [7:0] $end - $var wire 8 M( out [7:0] $end - $var wire 8 h' ff [7:0] $end - $var wire 128 i' sub5_in[0][0] [127:0] $end - $var wire 128 m' sub5_in[0][1] [127:0] $end - $var wire 128 q' sub5_in[0][2] [127:0] $end - $var wire 128 u' sub5_in[1][0] [127:0] $end - $var wire 128 y' sub5_in[1][1] [127:0] $end - $var wire 128 }' sub5_in[1][2] [127:0] $end - $var wire 8 ?( sub5_out[0][0] [7:0] $end - $var wire 8 @( sub5_out[0][1] [7:0] $end - $var wire 8 A( sub5_out[0][2] [7:0] $end - $var wire 8 B( sub5_out[1][0] [7:0] $end - $var wire 8 C( sub5_out[1][1] [7:0] $end - $var wire 8 D( sub5_out[1][2] [7:0] $end - $var wire 32 #( count [31:0] $end + $var wire 32 ,) P0 [31:0] $end + $var real 64 -) P1 $end + $var real 64 /) P3 $end + $var wire 1 )) clk $end + $var wire 8 *) in [7:0] $end + $var wire 8 +) out [7:0] $end + $var wire 8 F( ff [7:0] $end + $var wire 128 G( sub5_in[0][0] [127:0] $end + $var wire 128 K( sub5_in[0][1] [127:0] $end + $var wire 128 O( sub5_in[0][2] [127:0] $end + $var wire 128 S( sub5_in[1][0] [127:0] $end + $var wire 128 W( sub5_in[1][1] [127:0] $end + $var wire 128 [( sub5_in[1][2] [127:0] $end + $var wire 8 {( sub5_out[0][0] [7:0] $end + $var wire 8 |( sub5_out[0][1] [7:0] $end + $var wire 8 }( sub5_out[0][2] [7:0] $end + $var wire 8 ~( sub5_out[1][0] [7:0] $end + $var wire 8 !) sub5_out[1][1] [7:0] $end + $var wire 8 ") sub5_out[1][2] [7:0] $end + $var wire 32 _( count [31:0] $end $scope module i_sub5 $end - $var wire 1 K( clk $end - $var wire 128 '( in[0][0] [127:0] $end - $var wire 128 +( in[0][1] [127:0] $end - $var wire 128 /( in[0][2] [127:0] $end - $var wire 128 3( in[1][0] [127:0] $end - $var wire 128 7( in[1][1] [127:0] $end - $var wire 128 ;( in[1][2] [127:0] $end - $var wire 8 E( out[0][0] [7:0] $end - $var wire 8 F( out[0][1] [7:0] $end - $var wire 8 G( out[0][2] [7:0] $end - $var wire 8 H( out[1][0] [7:0] $end - $var wire 8 I( out[1][1] [7:0] $end - $var wire 8 J( out[1][2] [7:0] $end + $var wire 1 )) clk $end + $var wire 128 c( in[0][0] [127:0] $end + $var wire 128 g( in[0][1] [127:0] $end + $var wire 128 k( in[0][2] [127:0] $end + $var wire 128 o( in[1][0] [127:0] $end + $var wire 128 s( in[1][1] [127:0] $end + $var wire 128 w( in[1][2] [127:0] $end + $var wire 8 #) out[0][0] [7:0] $end + $var wire 8 $) out[0][1] [7:0] $end + $var wire 8 %) out[0][2] [7:0] $end + $var wire 8 &) out[1][0] [7:0] $end + $var wire 8 ') out[1][1] [7:0] $end + $var wire 8 () out[1][2] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 $( i [31:0] $end + $var wire 32 `( i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 %( j [31:0] $end + $var wire 32 a( j [31:0] $end $scope module unnamedblk3 $end - $var wire 8 &( exp [7:0] $end + $var wire 8 b( exp [7:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5 $end - $var wire 1 e( clk $end - $var wire 128 f( in[0][0] [127:0] $end - $var wire 128 j( in[0][1] [127:0] $end - $var wire 128 n( in[0][2] [127:0] $end - $var wire 128 r( in[1][0] [127:0] $end - $var wire 128 v( in[1][1] [127:0] $end - $var wire 128 z( in[1][2] [127:0] $end - $var wire 8 ~( out[0][0] [7:0] $end - $var wire 8 !) out[0][1] [7:0] $end - $var wire 8 ") out[0][2] [7:0] $end - $var wire 8 #) out[1][0] [7:0] $end - $var wire 8 $) out[1][1] [7:0] $end - $var wire 8 %) out[1][2] [7:0] $end + $var wire 1 I) clk $end + $var wire 128 J) in[0][0] [127:0] $end + $var wire 128 N) in[0][1] [127:0] $end + $var wire 128 R) in[0][2] [127:0] $end + $var wire 128 V) in[1][0] [127:0] $end + $var wire 128 Z) in[1][1] [127:0] $end + $var wire 128 ^) in[1][2] [127:0] $end + $var wire 8 b) out[0][0] [7:0] $end + $var wire 8 c) out[0][1] [7:0] $end + $var wire 8 d) out[0][2] [7:0] $end + $var wire 8 e) out[1][0] [7:0] $end + $var wire 8 f) out[1][1] [7:0] $end + $var wire 8 g) out[1][2] [7:0] $end $scope module sub5 $end - $var wire 1 e( clk $end - $var wire 128 f( in[0][0] [127:0] $end - $var wire 128 j( in[0][1] [127:0] $end - $var wire 128 n( in[0][2] [127:0] $end - $var wire 128 r( in[1][0] [127:0] $end - $var wire 128 v( in[1][1] [127:0] $end - $var wire 128 z( in[1][2] [127:0] $end - $var wire 8 ~( out[0][0] [7:0] $end - $var wire 8 !) out[0][1] [7:0] $end - $var wire 8 ") out[0][2] [7:0] $end - $var wire 8 #) out[1][0] [7:0] $end - $var wire 8 $) out[1][1] [7:0] $end - $var wire 8 %) out[1][2] [7:0] $end - $var wire 32 ^( count [31:0] $end - $var wire 8 T( val0[0] [7:0] $end - $var wire 8 U( val0[1] [7:0] $end - $var wire 8 V( val1[0] [7:0] $end - $var wire 8 W( val1[1] [7:0] $end - $var wire 8 X( val2[0] [7:0] $end - $var wire 8 Y( val2[1] [7:0] $end - $var wire 8 Z( val3[0] [7:0] $end - $var wire 8 [( val3[1] [7:0] $end + $var wire 1 I) clk $end + $var wire 128 J) in[0][0] [127:0] $end + $var wire 128 N) in[0][1] [127:0] $end + $var wire 128 R) in[0][2] [127:0] $end + $var wire 128 V) in[1][0] [127:0] $end + $var wire 128 Z) in[1][1] [127:0] $end + $var wire 128 ^) in[1][2] [127:0] $end + $var wire 8 b) out[0][0] [7:0] $end + $var wire 8 c) out[0][1] [7:0] $end + $var wire 8 d) out[0][2] [7:0] $end + $var wire 8 e) out[1][0] [7:0] $end + $var wire 8 f) out[1][1] [7:0] $end + $var wire 8 g) out[1][2] [7:0] $end + $var wire 32 B) count [31:0] $end + $var wire 8 2) val0[0] [7:0] $end + $var wire 8 3) val0[1] [7:0] $end + $var wire 8 4) val1[0] [7:0] $end + $var wire 8 5) val1[1] [7:0] $end + $var wire 8 6) val2[0] [7:0] $end + $var wire 8 7) val2[1] [7:0] $end + $var wire 8 8) val3[0] [7:0] $end + $var wire 8 9) val3[1] [7:0] $end $scope module i_sub0 $end - $var wire 32 &) P0 [31:0] $end - $var wire 32 ') P1 [31:0] $end - $var wire 8 T( out[0] [7:0] $end - $var wire 8 U( out[1] [7:0] $end + $var wire 8 :) out[0] [7:0] $end + $var wire 8 ;) out[1] [7:0] $end $upscope $end $scope module i_sub1 $end - $var wire 32 &) P0 [31:0] $end - $var wire 32 ') P1 [31:0] $end - $var wire 8 V( out[0] [7:0] $end - $var wire 8 W( out[1] [7:0] $end + $var wire 8 <) out[0] [7:0] $end + $var wire 8 =) out[1] [7:0] $end $upscope $end $scope module i_sub2 $end - $var wire 32 &) P0 [31:0] $end - $var wire 32 ') P1 [31:0] $end - $var wire 8 X( out[0] [7:0] $end - $var wire 8 Y( out[1] [7:0] $end + $var wire 8 >) out[0] [7:0] $end + $var wire 8 ?) out[1] [7:0] $end $upscope $end $scope module i_sub3 $end - $var wire 8 \( out[0] [7:0] $end - $var wire 8 ]( out[1] [7:0] $end + $var wire 8 @) out[0] [7:0] $end + $var wire 8 A) out[1] [7:0] $end $upscope $end $scope module unnamedblk1 $end - $var wire 32 _( i [31:0] $end + $var wire 32 C) i [31:0] $end $scope module unnamedblk2 $end - $var wire 32 `( j [31:0] $end + $var wire 32 D) j [31:0] $end $scope module unnamedblk3 $end - $var wire 128 a( exp [127:0] $end + $var wire 128 E) exp [127:0] $end $upscope $end $upscope $end $upscope $end $upscope $end $upscope $end + $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5.sub5.i_sub0 $end + $var wire 8 i) out[0] [7:0] $end + $var wire 8 j) out[1] [7:0] $end + $scope module sub6_f $end + $var wire 32 k) P0 [31:0] $end + $var wire 32 l) P1 [31:0] $end + $var wire 8 i) out[0] [7:0] $end + $var wire 8 j) out[1] [7:0] $end + $upscope $end + $upscope $end $scope module top.t.i_sub3.sub3_d.i_sub4_1.sub4_b.i_sub5.sub5.i_sub3 $end - $var wire 8 )) out[0] [7:0] $end - $var wire 8 *) out[1] [7:0] $end + $var wire 8 n) out[0] [7:0] $end + $var wire 8 o) out[1] [7:0] $end $scope module sub6_9 $end - $var wire 32 +) P0 [31:0] $end - $var wire 32 ,) P1 [31:0] $end - $var wire 8 )) out[0] [7:0] $end - $var wire 8 *) out[1] [7:0] $end + $var wire 32 p) P0 [31:0] $end + $var wire 32 q) P1 [31:0] $end + $var wire 8 n) out[0] [7:0] $end + $var wire 8 o) out[1] [7:0] $end $upscope $end $upscope $end $enddefinitions $end @@ -1059,469 +1112,529 @@ b00000000000000000000000000000000 + b00000000 . b00000000 / b00000000 0 -b00000000 1 +04 +b00000000 5 b00000000 6 b00000000 7 -b00000000 8 -09 -b00000000 : -b00000000 ; -0A -b00000000 B +0; +b00000000 < +b00000000 = +b00000000 > +0B b00000000 C b00000000 D -0F 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+b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 R) +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011 V) +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 Z) +b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101 ^) +b00000000 b) +b00000000 c) +b00000000 d) +b00000000 e) +b00000000 f) +b00000000 g) diff --git a/test_regress/t/t_hier_block_vlt.pl b/test_regress/t/t_hier_block_vlt.pl index 115e05367..b86c9be41 100755 --- a/test_regress/t/t_hier_block_vlt.pl +++ b/test_regress/t/t_hier_block_vlt.pl @@ -35,7 +35,7 @@ file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", qr/^\s+timeprecision\s+(\d+)ps;/m file_grep($Self->{obj_dir} . "/Vsub0/sub0.sv", /^module\s+(\S+)\s+/, "sub0"); file_grep($Self->{obj_dir} . "/Vsub1/sub1.sv", /^module\s+(\S+)\s+/, "sub1"); file_grep($Self->{obj_dir} . "/Vsub2/sub2.sv", /^module\s+(\S+)\s+/, "sub2"); -file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 13); +file_grep($Self->{stats}, qr/HierBlock,\s+Hierarchical blocks\s+(\d+)/i, 14); file_grep($Self->{run_log_filename}, qr/MACRO:(\S+) is defined/i, "cplusplus"); ok(1); diff --git a/test_regress/t/t_hier_block_vlt.vlt b/test_regress/t/t_hier_block_vlt.vlt index 60a2d4c37..81317810c 100644 --- a/test_regress/t/t_hier_block_vlt.vlt +++ b/test_regress/t/t_hier_block_vlt.vlt @@ -6,4 +6,4 @@ `verilator_config hier_block -module "sub?" -hier_block -module "delay" +hier_block -module "delay" // matches recursive modules diff --git a/test_regress/t/t_iff.out b/test_regress/t/t_iff.out deleted file mode 100644 index 24dc99876..000000000 --- a/test_regress/t/t_iff.out +++ /dev/null @@ -1,17 +0,0 @@ -%Error-UNSUPPORTED: t/t_iff.v:66:15: Unsupported: event expression 'iff' - 66 | always @(d iff enable) begin - | ^~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_iff.v:71:23: Unsupported: event expression 'iff' - 71 | always @(posedge d iff enable) begin - | ^~~ -%Error-UNSUPPORTED: t/t_iff.v:76:23: Unsupported: event expression 'iff' - 76 | always @(negedge d iff enable) begin - | ^~~ -%Error-UNSUPPORTED: t/t_iff.v:81:20: Unsupported: event expression 'iff' - 81 | always @(edge d iff enable) begin - | ^~~ -%Error-UNSUPPORTED: t/t_iff.v:86:35: Unsupported: event expression 'iff' - 86 | assert property (@(posedge clk iff enable) - | ^~~ -%Error: Exiting due to diff --git a/test_regress/t/t_iff.pl b/test_regress/t/t_iff.pl index 2966ed9a2..9a15dd2cc 100755 --- a/test_regress/t/t_iff.pl +++ b/test_regress/t/t_iff.pl @@ -11,14 +11,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); compile( - verilator_flags2 => ['--timing'], - fails => $Self->{vlt_all}, # Verilator unsupported, bug1482, iff not supported - expect_filename => $Self->{golden_filename}, ); execute( check_finished => 1, - ) if !$Self->{vlt_all}; + ); ok(1); 1; diff --git a/test_regress/t/t_iff.v b/test_regress/t/t_iff.v index 833bf411f..f7c72197c 100644 --- a/test_regress/t/t_iff.v +++ b/test_regress/t/t_iff.v @@ -16,7 +16,7 @@ module t (/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [31:0] result; // From test of Test.v + wire [63:0] result; // From test of Test.v // End of automatics Test test (.*); @@ -42,7 +42,7 @@ module t (/*AUTOARG*/ $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h390aa8652d33a691 +`define EXPECTED_SUM 64'hd55eb7da9ba3354a if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; @@ -56,7 +56,7 @@ module Test input clk, input [63:0] crc, input [31:0] cyc, - output wire [31:0] result); + output wire [63:0] result); wire enable = crc[32]; wire [7:0] d = crc[7:0]; diff --git a/test_regress/t/t_implements_new_bad.out b/test_regress/t/t_implements_new_bad.out index 3201ecfaf..22b82ace8 100644 --- a/test_regress/t/t_implements_new_bad.out +++ b/test_regress/t/t_implements_new_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_implements_new_bad.v:13:11: Illegal to call 'new' using an abstract virtual class (IEEE 1800-2017 8.21) +%Error: t/t_implements_new_bad.v:13:11: Illegal to call 'new' using an abstract virtual class 'Icls' (IEEE 1800-2017 8.21) : ... note: In instance 't' 13 | c = new; | ^~~ diff --git a/test_regress/t/t_inside_assoc_unsup.out b/test_regress/t/t_inside_assoc_unsup.out new file mode 100644 index 000000000..5fbed6e4f --- /dev/null +++ b/test_regress/t/t_inside_assoc_unsup.out @@ -0,0 +1,5 @@ +%Error: t/t_inside_assoc_unsup.v:12:15: Inside operator not specified on associative arrays (IEEE 1800-2017 11.4.13) + : ... note: In instance 't' + 12 | m = (10 inside {assoc}); + | ^~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_inside_queue_bad.pl b/test_regress/t/t_inside_assoc_unsup.pl similarity index 100% rename from test_regress/t/t_inside_queue_bad.pl rename to test_regress/t/t_inside_assoc_unsup.pl diff --git a/test_regress/t/t_inside_queue_bad.v b/test_regress/t/t_inside_assoc_unsup.v similarity index 79% rename from test_regress/t/t_inside_queue_bad.v rename to test_regress/t/t_inside_assoc_unsup.v index 4e3e0c9a8..c5b261233 100644 --- a/test_regress/t/t_inside_queue_bad.v +++ b/test_regress/t/t_inside_assoc_unsup.v @@ -5,16 +5,11 @@ // SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); - - int q[$]; int assoc[int]; - int dyn[]; bit m; initial begin - m = (10 inside {q}); m = (10 inside {assoc}); - m = (10 inside {dyn}); end endmodule diff --git a/test_regress/t/t_inside_dyn.pl b/test_regress/t/t_inside_dyn.pl new file mode 100755 index 000000000..1aa73f80a --- /dev/null +++ b/test_regress/t/t_inside_dyn.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_inside_dyn.v b/test_regress/t/t_inside_dyn.v new file mode 100644 index 000000000..e07b9fdc1 --- /dev/null +++ b/test_regress/t/t_inside_dyn.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +module t; + int q[$] = '{1, 2, 3}; + bit dyn[] = '{0, 0}; + + initial begin + if (!(1 inside {q})) $stop; + if (4 inside {q}) $stop; + if (!(4 inside {q, 4})) $stop; + + if (!(0 inside {dyn})) $stop; + if (1 inside {dyn}) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_inside_queue_bad.out b/test_regress/t/t_inside_queue_bad.out deleted file mode 100644 index 37b7be1ad..000000000 --- a/test_regress/t/t_inside_queue_bad.out +++ /dev/null @@ -1,13 +0,0 @@ -%Error: t/t_inside_queue_bad.v:15:15: Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13) - : ... note: In instance 't' - 15 | m = (10 inside {q}); - | ^~~~~~ -%Error: t/t_inside_queue_bad.v:16:15: Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13) - : ... note: In instance 't' - 16 | m = (10 inside {assoc}); - | ^~~~~~ -%Error: t/t_inside_queue_bad.v:17:15: Inside operator not legal on non-unpacked arrays (IEEE 1800-2017 11.4.13) - : ... note: In instance 't' - 17 | m = (10 inside {dyn}); - | ^~~~~~ -%Error: Exiting due to diff --git a/test_regress/t/t_inside_unpacked.pl b/test_regress/t/t_inside_unpacked.pl index 40f69d41d..9a15dd2cc 100755 --- a/test_regress/t/t_inside_unpacked.pl +++ b/test_regress/t/t_inside_unpacked.pl @@ -11,13 +11,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); compile( - fails => $Self->{vlt_all}, - expect_filename => $Self->{golden_filename}, ); execute( check_finished => 1, - ) if !$Self->{vlt_all}; + ); ok(1); 1; diff --git a/test_regress/t/t_inside_unpacked.v b/test_regress/t/t_inside_unpacked.v index 0b0760fd8..a3d203674 100644 --- a/test_regress/t/t_inside_unpacked.v +++ b/test_regress/t/t_inside_unpacked.v @@ -10,18 +10,6 @@ module t(/*AUTOARG*/ ); input clk; - localparam int CHECKLIST_P [2:0] = '{0, 1, 2}; - - localparam HIT_LP = 1; - localparam MISS_LP = 4; - localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; - localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; - - initial begin - if (HIT_INSIDE != 1) $stop; - if (MISS_INSIDE != 0) $stop; - end - integer cyc = 0; int array [10]; diff --git a/test_regress/t/t_inside_unpacked_param.out b/test_regress/t/t_inside_unpacked_param.out new file mode 100644 index 000000000..0cae5353d --- /dev/null +++ b/test_regress/t/t_inside_unpacked_param.out @@ -0,0 +1,9 @@ +%Error: t/t_inside_unpacked_param.v:13:43: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant. + : ... note: In instance 't' + 13 | localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; + | ^~~~~~~~~~~ +%Error: t/t_inside_unpacked_param.v:14:45: Expecting expression to be constant, but can't convert a CMETHODHARD 'inside' to constant. + : ... note: In instance 't' + 14 | localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; + | ^~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_inside_unpacked_param.pl b/test_regress/t/t_inside_unpacked_param.pl new file mode 100755 index 000000000..40f69d41d --- /dev/null +++ b/test_regress/t/t_inside_unpacked_param.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +execute( + check_finished => 1, + ) if !$Self->{vlt_all}; + +ok(1); +1; diff --git a/test_regress/t/t_inside_unpacked_param.v b/test_regress/t/t_inside_unpacked_param.v new file mode 100644 index 000000000..10f227af8 --- /dev/null +++ b/test_regress/t/t_inside_unpacked_param.v @@ -0,0 +1,22 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + + localparam int CHECKLIST_P [2:0] = '{0, 1, 2}; + + localparam HIT_LP = 1; + localparam MISS_LP = 4; + localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P}; + localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P}; + + initial begin + if (HIT_INSIDE != 1) $stop; + if (MISS_INSIDE != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_param_genblk.out b/test_regress/t/t_interface_param_genblk.out new file mode 100644 index 000000000..d62918ec4 --- /dev/null +++ b/test_regress/t/t_interface_param_genblk.out @@ -0,0 +1,24 @@ +-Info: t/t_interface_param_genblk.v:35:9: correct + : ... note: In instance 't.i_sub' + 35 | $info("correct"); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:44:13: i = 98, j = 2 + : ... note: In instance 't.i_sub' + 44 | $info("i = %0d, j = %0d", i, j); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:44:13: i = 98, j = 1 + : ... note: In instance 't.i_sub' + 44 | $info("i = %0d, j = %0d", i, j); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:44:13: i = 100, j = 2 + : ... note: In instance 't.i_sub' + 44 | $info("i = %0d, j = %0d", i, j); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:44:13: i = 100, j = 1 + : ... note: In instance 't.i_sub' + 44 | $info("i = %0d, j = %0d", i, j); + | ^~~~~ +-Info: t/t_interface_param_genblk.v:50:26: correct + : ... note: In instance 't.i_sub' + 50 | intf.B * 50: $info("correct"); + | ^~~~~ diff --git a/test_regress/t/t_math_shift_over_bad.pl b/test_regress/t/t_interface_param_genblk.pl similarity index 86% rename from test_regress/t/t_math_shift_over_bad.pl rename to test_regress/t/t_interface_param_genblk.pl index 9c9fb65a0..d1ed9a923 100755 --- a/test_regress/t/t_math_shift_over_bad.pl +++ b/test_regress/t/t_interface_param_genblk.pl @@ -2,7 +2,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you +# Copyright 2003 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -11,7 +11,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(linter => 1); lint( - fails => 1, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_interface_param_genblk.v b/test_regress/t/t_interface_param_genblk.v new file mode 100644 index 000000000..67092468a --- /dev/null +++ b/test_regress/t/t_interface_param_genblk.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Anthony Donlon. +// SPDX-License-Identifier: CC0-1.0 + +// See #4664 + +interface intf #( + parameter A = 10 +); + localparam B = A / A + 1; // 2 + + logic [A/10-1:0] sig; +endinterface + +module t; + intf #( + .A(100) + ) intf(); + + sub i_sub ( + .intf + ); +endmodule + +module sub ( + intf intf +); + + if (intf.A == 10) begin + $error("incorrect"); + end else if (intf.A / intf.B == 50) begin + // end else if (intf.A / $bits(intf.sig) == 10) begin // TODO: support this + $info("correct"); + end else begin + $error("incorrect"); + end + + for (genvar i = intf.A - 2; i < intf.A + 1; i += intf.B) begin + for (genvar j = intf.B; j > intf.A - 100; j--) begin + if (i < intf.A - 2) $error("error"); + if (i > intf.A) $error("error"); + $info("i = %0d, j = %0d", i, j); + end + end + + case (intf.A) + 10, intf.A - 10: $error("incorrect"); + intf.B * 50: $info("correct"); + 30: $error("incorrect"); + default: $error("incorrect"); + endcase +endmodule diff --git a/test_regress/t/t_interface_virtual_controlflow.out b/test_regress/t/t_interface_virtual_controlflow.out new file mode 100644 index 000000000..303bceb13 --- /dev/null +++ b/test_regress/t/t_interface_virtual_controlflow.out @@ -0,0 +1,19 @@ +[0] vif1.data==0000 +[0] intf2.data==0000 +[0] vif4.data==0000 +[10] intf2.data==beef +[20] vif1.data==dead +[20] vif4.data==face +[30] intf2.data==beef +[40] vif1.data==dead +[40] vif4.data==face +[50] intf2.data==beef +[60] vif1.data==dead +[60] vif4.data==face +[70] intf2.data==beef +[80] intf2.data==beef +[80] vif4.data==cafe +[90] intf2.data==beef +[100] intf2.data==beef +[100] vif4.data==deaf +*-* All Finished *-* diff --git a/test_regress/t/t_interface_virtual_controlflow.pl b/test_regress/t/t_interface_virtual_controlflow.pl new file mode 100755 index 000000000..3b4aae630 --- /dev/null +++ b/test_regress/t/t_interface_virtual_controlflow.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["-fno-reorder"], + ); + +execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_interface_virtual_controlflow.v b/test_regress/t/t_interface_virtual_controlflow.v new file mode 100644 index 000000000..4e5dd4cbd --- /dev/null +++ b/test_regress/t/t_interface_virtual_controlflow.v @@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +interface Bus1; + logic [15:0] data; +endinterface +interface Bus2; + logic [15:0] data; +endinterface +interface Bus3; + logic [15:0] data; +endinterface + +module t ( + clk +); + input clk; + integer cyc = 0; + Bus1 intf1(); + Bus2 intf2(); + Bus3 intf3(), intf4(); + virtual Bus1 vif1 = intf1; + virtual Bus2 vif2 = intf2; + virtual Bus3 vif3 = intf3, vif4 = intf4; + + // Finish on negedge so that $finish is last + always @(negedge clk) + if (cyc >= 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + function void assign_to_intf3(); + if ($c("1")) return; + intf3.data = 'hcafe; + endfunction + + always @(posedge clk) begin + logic foo = 1; + cyc <= cyc + 1; + if (cyc == 1 || cyc == 3 || cyc == 5) intf1.data = 'hdead; + else vif2.data = 'hbeef; + if (cyc == 1 || cyc == 3 || cyc == 5) begin + if (cyc >= 3) $c("// dummy statement"); + else intf3.data = 'hfafa; + intf4.data = 'hface; + end + if (cyc == 7) begin + while ($c("0")) begin + foo = 0; + intf3.data = 'hbebe; + end + intf4.data = 'hcafe; + end + if (cyc == 9) begin + assign_to_intf3; + intf4.data = 'hdeaf; + end + end + + always_comb $write("[%0t] vif1.data==%h\n", $time, vif1.data); + always_comb $write("[%0t] intf2.data==%h\n", $time, intf2.data); + always_comb $write("[%0t] vif4.data==%h\n", $time, vif4.data); +endmodule diff --git a/test_regress/t/t_interface_virtual_param.pl b/test_regress/t/t_interface_virtual_param.pl new file mode 100755 index 000000000..f45fe82b3 --- /dev/null +++ b/test_regress/t/t_interface_virtual_param.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1 + ); + +ok(1); +1; diff --git a/test_regress/t/t_interface_virtual_param.v b/test_regress/t/t_interface_virtual_param.v new file mode 100644 index 000000000..a1596b4ff --- /dev/null +++ b/test_regress/t/t_interface_virtual_param.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +interface Bus #(parameter int W = 1, X = 2); + logic [W-1:0] data; +endinterface + +interface BusTyped #(parameter type T); + T data; +endinterface + +typedef struct packed { + logic x; +} my_logic_t; + +module t; + Bus#(6, 3) intf1(); + virtual Bus#(6, 3) vintf1 = intf1; + + Bus intf2(); + virtual Bus#(.W(1), .X(2)) vintf2 = intf2; + + BusTyped#(my_logic_t) intf3(); + virtual BusTyped#(my_logic_t) vintf3 = intf3; + + initial begin + intf1.data = '1; + if (vintf1.data != 6'b111111) $stop; + if (vintf1.X != 3) $stop; + + intf2.data = '1; + if (vintf2.data != 1'b1) $stop; + if (vintf2.X != 2) $stop; + + intf3.data.x = '1; + if (vintf3.data.x != 1'b1) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_virtual_sched_act.out b/test_regress/t/t_interface_virtual_sched_act.out new file mode 100644 index 000000000..10090eb57 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_act.out @@ -0,0 +1,12 @@ +[0] data==0000 +[0] data==0000 +[10] data==0000 +[20] data==dead +[20] data==beef +[20] data==beef +[30] data==beef +[40] data==face +[40] data==cafe +[40] data==cafe +[50] data==cafe +*-* All Finished *-* diff --git a/test_regress/t/t_interface_virtual_sched_act.pl b/test_regress/t/t_interface_virtual_sched_act.pl new file mode 100755 index 000000000..6247bd126 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_act.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_interface_virtual_sched_act.v b/test_regress/t/t_interface_virtual_sched_act.v new file mode 100644 index 000000000..258ac1620 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_act.v @@ -0,0 +1,40 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +interface Bus; + logic [15:0] data; +endinterface + +module t ( + clk +); + input clk; + integer cyc = 0; + Bus intf(); + virtual Bus vif = intf; + logic [15:0] data; + + always @(posedge clk) begin + cyc <= cyc + 1; + end + + // Finish on negedge so that $finish is last + always @(negedge clk) + if (cyc >= 5) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + always @(posedge clk or data) begin + if (cyc == 1) intf.data <= 'hdead; + else if (cyc == 2) intf.data <= 'hbeef; + else if (cyc == 3) intf.data <= 'hface; + else if (cyc == 4) intf.data <= 'hcafe; + end + + assign data = vif.data; + always_comb $write("[%0t] data==%h\n", $time, data); +endmodule diff --git a/test_regress/t/t_interface_virtual_sched_ico.cpp b/test_regress/t/t_interface_virtual_sched_ico.cpp new file mode 100644 index 000000000..04d8c1cc3 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_ico.cpp @@ -0,0 +1,51 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// Copyright 2023 by Geza Lore. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#include "verilated.h" + +#include "Vt_interface_virtual_sched_ico.h" +#include "Vt_interface_virtual_sched_ico__Syms.h" + +#include + +int main(int argc, char** argv) { + const std::unique_ptr contextp{new VerilatedContext}; + contextp->debug(0); + contextp->commandArgs(argc, argv); + srand48(5); + + const std::unique_ptr topp{new VM_PREFIX}; + topp->clk = false; + topp->inc1 = 1; + topp->eval(); + topp->inc2 = 1; + topp->eval(); + + bool flop = true; + while (!contextp->gotFinish() && contextp->time() < 100000) { + contextp->timeInc(5); + if (topp->clk) { + if (flop) { + topp->inc1 += 1; + } else { + topp->inc2 += 1; + } + flop = !flop; + } + topp->clk = !topp->clk; + topp->eval(); + } + + if (!contextp->gotFinish()) { + vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); + } + return 0; +} diff --git a/test_regress/t/t_interface_virtual_sched_ico.out b/test_regress/t/t_interface_virtual_sched_ico.out new file mode 100644 index 000000000..5f94c05df --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_ico.out @@ -0,0 +1,43 @@ +[0] intf1.inc==0 +[0] vif2.inc==0 +[0] intf1.inc==1 +[0] vif2.inc==0 +[0] intf1.inc==1 +[0] vif2.inc==0 +[0] intf1.inc==1 +[0] vif2.inc==1 +[5] intf1.inc==1 +[5] vif2.inc==1 +[10] intf1.inc==2 +[10] vif2.inc==1 +[15] intf1.inc==2 +[15] vif2.inc==1 +[20] intf1.inc==2 +[20] vif2.inc==2 +[25] intf1.inc==2 +[25] vif2.inc==2 +[30] intf1.inc==3 +[30] vif2.inc==2 +[35] intf1.inc==3 +[35] vif2.inc==2 +[40] intf1.inc==3 +[40] vif2.inc==3 +[45] intf1.inc==3 +[45] vif2.inc==3 +[50] intf1.inc==4 +[50] vif2.inc==3 +[55] intf1.inc==4 +[55] vif2.inc==3 +[60] intf1.inc==4 +[60] vif2.inc==4 +[65] intf1.inc==4 +[65] vif2.inc==4 +[70] intf1.inc==5 +[70] vif2.inc==4 +[75] intf1.inc==5 +[75] vif2.inc==4 +[80] intf1.inc==5 +[80] vif2.inc==5 +[85] intf1.inc==5 +[85] vif2.inc==5 +*-* All Finished *-* diff --git a/test_regress/t/t_interface_virtual_sched_ico.pl b/test_regress/t/t_interface_virtual_sched_ico.pl new file mode 100755 index 000000000..1f4f8b7ca --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_ico.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt_all => 1); + +compile( + make_main => 0, + v_flags2 => ["--exe", "$Self->{t_dir}/$Self->{name}.cpp"], + ); + +execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_interface_virtual_sched_ico.v b/test_regress/t/t_interface_virtual_sched_ico.v new file mode 100644 index 000000000..3d85a7ec9 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_ico.v @@ -0,0 +1,41 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +interface If; + logic [31:0] inc; +endinterface + +module top ( + clk, + inc1, + inc2 +); + + input clk; + input [31:0] inc1; + input [31:0] inc2; + int cyc = 0; + + If intf1(); + If intf2(); + virtual If vif1 = intf1; + virtual If vif2 = intf2; + + assign vif1.inc = inc1; + assign intf2.inc = inc2; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc >= 8) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + always_comb $write("[%0t] intf1.inc==%0h\n", $time, intf1.inc); + always_comb $write("[%0t] vif2.inc==%0h\n", $time, vif2.inc); + +endmodule diff --git a/test_regress/t/t_interface_virtual_sched_nba.out b/test_regress/t/t_interface_virtual_sched_nba.out new file mode 100644 index 000000000..abde98039 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_nba.out @@ -0,0 +1,21 @@ +[0] intf1.data==0000 +[0] intf2.data==0000 +[0] vif3.data==0000 +[0] intf2.data==0000 +[10] intf2.data==0000 +[10] vif3.data==0000 +[20] intf1.data==dead +[20] intf2.data==0000 +[20] vif3.data==0000 +[30] intf2.data==dead +[30] vif3.data==0000 +[40] intf1.data==beef +[40] intf2.data==dead +[40] vif3.data==0000 +[50] intf2.data==beef +[50] vif3.data==0000 +[60] intf2.data==beef +[60] vif3.data==face +[70] intf2.data==beef +[70] vif3.data==cafe +*-* All Finished *-* diff --git a/test_regress/t/t_interface_virtual_sched_nba.pl b/test_regress/t/t_interface_virtual_sched_nba.pl new file mode 100755 index 000000000..6247bd126 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_nba.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_interface_virtual_sched_nba.v b/test_regress/t/t_interface_virtual_sched_nba.v new file mode 100644 index 000000000..dc610aa50 --- /dev/null +++ b/test_regress/t/t_interface_virtual_sched_nba.v @@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +interface Bus1; + logic [15:0] data; +endinterface + +interface Bus2; + logic [15:0] data; +endinterface + +interface Bus3; + logic [15:0] data; +endinterface + +module t ( + clk +); + input clk; + integer cyc = 0; + Bus1 intf1(); + Bus2 intf2(); + Bus3 intf3(); + virtual Bus1 vif1 = intf1; + virtual Bus2 vif2 = intf2; + virtual Bus3 vif3 = intf3; + + logic [15:0] data; + assign vif2.data = data; + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) + vif1.data = 'hdead; + else if (cyc == 2) + data = vif1.data; + else if (cyc == 3) + vif1.data = 'hbeef; + else if (cyc == 4) + data = vif1.data; + else if (cyc == 5) + intf3.data <= 'hface; + else if (cyc == 6) + intf3.data <= 'hcafe; + end + + // Finish on negedge so that $finish is last + always @(negedge clk) + if (cyc >= 7) begin + $write("*-* All Finished *-*\n"); + $finish; + end + + always_comb $write("[%0t] intf1.data==%h\n", $time, intf1.data); + always_comb $write("[%0t] intf2.data==%h\n", $time, intf2.data); + always_comb $write("[%0t] vif3.data==%h\n", $time, vif3.data); +endmodule diff --git a/test_regress/t/t_interface_virtual_timing.out b/test_regress/t/t_interface_virtual_timing.out new file mode 100644 index 000000000..2ca5ac2af --- /dev/null +++ b/test_regress/t/t_interface_virtual_timing.out @@ -0,0 +1,29 @@ +vif1.data==dead +intf2.data==0000 +vif1.data==dead +intf2.data==0000 +intf2.data==beef +vif1.data==dead +intf2.data==beef +intf2.data==beef +vif1.data==cafe +intf2.data==beef +intf2.data==face +vif1.data==cafe +intf2.data==face +intf2.data==face +vif1.data==feed +intf2.data==face +intf2.data==deed +vif1.data==feed +intf2.data==deed +intf2.data==deed +vif1.data==deaf +intf2.data==deed +intf2.data==fafa +vif1.data==deaf +intf2.data==fafa +intf2.data==fafa +vif1.data==bebe +intf2.data==fafa +*-* All Finished *-* diff --git a/test_regress/t/t_interface_virtual_timing.pl b/test_regress/t/t_interface_virtual_timing.pl new file mode 100755 index 000000000..0da9620d1 --- /dev/null +++ b/test_regress/t/t_interface_virtual_timing.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["--exe --main --timing"], + make_main => 0, + ); + +execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_interface_virtual_timing.v b/test_regress/t/t_interface_virtual_timing.v new file mode 100644 index 000000000..258c7d8f6 --- /dev/null +++ b/test_regress/t/t_interface_virtual_timing.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +interface Bus; + logic [15:0] data; +endinterface + +module t; + Bus intf1(), intf2(); + virtual Bus vif1 = intf1, vif2 = intf2; + + task assign_to_vif2(); + if ($c("0")) return; + #1 vif2.data = 'hfafa; #1; + endtask + + initial forever begin + intf1.data = 'hdead; + if ($c("1")) begin + #1 vif2.data = 'hbeef; #1; + end + intf1.data = 'hcafe; + if ($c("0")); else begin + #1 vif2.data = 'hface; #1; + end + intf1.data = 'hfeed; + while ($time < 5) begin + #1 vif2.data = 'hdeed; #1; + end + intf1.data = 'hdeaf; + assign_to_vif2; + intf1.data = 'hbebe; + #1 $write("*-* All Finished *-*\n"); + $finish; + end + + always_comb if ($time < 9) $write("vif1.data==%h\n", vif1.data); + always_comb if ($time < 9) $write("intf2.data==%h\n", intf2.data); +endmodule diff --git a/test_regress/t/t_interface_virtual_unsup.out b/test_regress/t/t_interface_virtual_unsup.out new file mode 100644 index 000000000..aec39ddb7 --- /dev/null +++ b/test_regress/t/t_interface_virtual_unsup.out @@ -0,0 +1,17 @@ +%Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:22:22: Unsupported: write to virtual interface in if condition + 22 | if (write_data(vif.data)) $write("dummy op"); + | ^~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:23:25: Unsupported: write to virtual interface in loop condition + 23 | while (write_data(vif.data)); + | ^~~ +%Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:24:34: Unsupported: write to virtual interface in loop condition + 24 | for (int i = 0; write_data(vif.data); i += int'(write_data(vif.data))); + | ^~~ +%Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:24:66: Unsupported: write to virtual interface in loop increment statement + 24 | for (int i = 0; write_data(vif.data); i += int'(write_data(vif.data))); + | ^~~ +%Error-UNSUPPORTED: t/t_interface_virtual_unsup.v:25:34: Unsupported: write to virtual interface in loop condition + 25 | for (int i = 0; write_data(vif.data++); i++); + | ^~~ +%Error: Exiting due to diff --git a/test_regress/t/t_interface_virtual_unsup.pl b/test_regress/t/t_interface_virtual_unsup.pl new file mode 100755 index 000000000..bd07fc421 --- /dev/null +++ b/test_regress/t/t_interface_virtual_unsup.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +execute( + check_finished => 1, + ) if !$Self->{vlt_all}; + +ok(1); +1; diff --git a/test_regress/t/t_interface_virtual_unsup.v b/test_regress/t/t_interface_virtual_unsup.v new file mode 100644 index 000000000..27870a35f --- /dev/null +++ b/test_regress/t/t_interface_virtual_unsup.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +interface Bus; + logic [15:0] data; +endinterface + +module t; + Bus intf(); + virtual Bus vif = intf; + + function logic write_data(output logic[15:0] data); + data = 'hdead; + return 1; + endfunction + + // verilator lint_off INFINITELOOP + initial begin + if (write_data(vif.data)) $write("dummy op"); + while (write_data(vif.data)); + for (int i = 0; write_data(vif.data); i += int'(write_data(vif.data))); + for (int i = 0; write_data(vif.data++); i++); + end + +endmodule diff --git a/test_regress/t/t_lint_always_comb_multidriven.out b/test_regress/t/t_lint_always_comb_multidriven.out deleted file mode 100644 index a9708f7f6..000000000 --- a/test_regress/t/t_lint_always_comb_multidriven.out +++ /dev/null @@ -1,87 +0,0 @@ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:26:16: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'out1' - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:26:16: - 26 | always_comb out1 = d; - | ^~~~ - t/t_lint_always_comb_multidriven.v:25:11: ... Location of other write - 25 | assign out1 = 1'b0; - | ^~~~ - ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest - ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:29:16: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'out2' - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:29:16: - 29 | always_comb out2 = 1'b0; - | ^~~~ - t/t_lint_always_comb_multidriven.v:28:11: ... Location of other write - 28 | assign out2 = d; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:32:11: Variable also written to in always_comb (IEEE 1800-2017 9.2.2.2): 'out3' - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:32:11: - 32 | assign out3 = 1'b0; - | ^~~~ - t/t_lint_always_comb_multidriven.v:31:16: ... Location of always_comb write - 31 | always_comb out3 = d; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:35:11: Variable also written to in always_comb (IEEE 1800-2017 9.2.2.2): 'out4' - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:35:11: - 35 | assign out4 = d; - | ^~~~ - t/t_lint_always_comb_multidriven.v:34:16: ... Location of always_comb write - 34 | always_comb out4 = 1'b0; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:38:16: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'out5' - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:38:16: - 38 | always_comb out5 = d; - | ^~~~ - t/t_lint_always_comb_multidriven.v:37:16: ... Location of other write - 37 | always_comb out5 = 1'b0; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:41:16: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'out6' - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:41:16: - 41 | always_comb out6 = 1'b0; - | ^~~~ - t/t_lint_always_comb_multidriven.v:40:16: ... Location of other write - 40 | always_comb out6 = d; - | ^~~~ -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:17:15: Bits [0:0] of signal 'out2' have multiple combinational drivers - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:28:16: ... Location of first driver - 28 | assign out2 = d; - | ^ - t/t_lint_always_comb_multidriven.v:29:21: ... Location of other driver - 29 | always_comb out2 = 1'b0; - | ^ - t/t_lint_always_comb_multidriven.v:17:15: ... Only the first driver will be respected -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:19:15: Bits [0:0] of signal 'out4' have multiple combinational drivers - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:34:21: ... Location of first driver - 34 | always_comb out4 = 1'b0; - | ^ - t/t_lint_always_comb_multidriven.v:35:16: ... Location of other driver - 35 | assign out4 = d; - | ^ - t/t_lint_always_comb_multidriven.v:19:15: ... Only the first driver will be respected -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:20:15: Bits [0:0] of signal 'out5' have multiple combinational drivers - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:37:21: ... Location of first driver - 37 | always_comb out5 = 1'b0; - | ^ - t/t_lint_always_comb_multidriven.v:38:21: ... Location of other driver - 38 | always_comb out5 = d; - | ^ - t/t_lint_always_comb_multidriven.v:20:15: ... Only the first driver will be respected -%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven.v:21:15: Bits [0:0] of signal 'out6' have multiple combinational drivers - : ... note: In instance 't' - t/t_lint_always_comb_multidriven.v:40:21: ... Location of first driver - 40 | always_comb out6 = d; - | ^ - t/t_lint_always_comb_multidriven.v:41:21: ... Location of other driver - 41 | always_comb out6 = 1'b0; - | ^ - t/t_lint_always_comb_multidriven.v:21:15: ... Only the first driver will be respected -%Error: Exiting due to diff --git a/test_regress/t/t_lint_always_comb_multidriven_bad.out b/test_regress/t/t_lint_always_comb_multidriven_bad.out new file mode 100644 index 000000000..478dab0f7 --- /dev/null +++ b/test_regress/t/t_lint_always_comb_multidriven_bad.out @@ -0,0 +1,87 @@ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:26:16: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'out1' + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:26:16: + 26 | always_comb out1 = d; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:25:11: ... Location of other write + 25 | assign out1 = 1'b0; + | ^~~~ + ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest + ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:29:16: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'out2' + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:29:16: + 29 | always_comb out2 = 1'b0; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:28:11: ... Location of other write + 28 | assign out2 = d; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:32:11: Variable also written to in always_comb (IEEE 1800-2017 9.2.2.2): 'out3' + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:32:11: + 32 | assign out3 = 1'b0; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:31:16: ... Location of always_comb write + 31 | always_comb out3 = d; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:35:11: Variable also written to in always_comb (IEEE 1800-2017 9.2.2.2): 'out4' + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:35:11: + 35 | assign out4 = d; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:34:16: ... Location of always_comb write + 34 | always_comb out4 = 1'b0; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:38:16: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'out5' + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:38:16: + 38 | always_comb out5 = d; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:37:16: ... Location of other write + 37 | always_comb out5 = 1'b0; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:41:16: Variable written to in always_comb also written by other process (IEEE 1800-2017 9.2.2.2): 'out6' + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:41:16: + 41 | always_comb out6 = 1'b0; + | ^~~~ + t/t_lint_always_comb_multidriven_bad.v:40:16: ... Location of other write + 40 | always_comb out6 = d; + | ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:17:15: Bits [0:0] of signal 'out2' have multiple combinational drivers + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:28:16: ... Location of first driver + 28 | assign out2 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:29:21: ... Location of other driver + 29 | always_comb out2 = 1'b0; + | ^ + t/t_lint_always_comb_multidriven_bad.v:17:15: ... Only the first driver will be respected +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:19:15: Bits [0:0] of signal 'out4' have multiple combinational drivers + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:34:21: ... Location of first driver + 34 | always_comb out4 = 1'b0; + | ^ + t/t_lint_always_comb_multidriven_bad.v:35:16: ... Location of other driver + 35 | assign out4 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:19:15: ... Only the first driver will be respected +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:20:15: Bits [0:0] of signal 'out5' have multiple combinational drivers + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:37:21: ... Location of first driver + 37 | always_comb out5 = 1'b0; + | ^ + t/t_lint_always_comb_multidriven_bad.v:38:21: ... Location of other driver + 38 | always_comb out5 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:20:15: ... Only the first driver will be respected +%Warning-MULTIDRIVEN: t/t_lint_always_comb_multidriven_bad.v:21:15: Bits [0:0] of signal 'out6' have multiple combinational drivers + : ... note: In instance 't' + t/t_lint_always_comb_multidriven_bad.v:40:21: ... Location of first driver + 40 | always_comb out6 = d; + | ^ + t/t_lint_always_comb_multidriven_bad.v:41:21: ... Location of other driver + 41 | always_comb out6 = 1'b0; + | ^ + t/t_lint_always_comb_multidriven_bad.v:21:15: ... Only the first driver will be respected +%Error: Exiting due to diff --git a/test_regress/t/t_lint_always_comb_multidriven.pl b/test_regress/t/t_lint_always_comb_multidriven_bad.pl similarity index 100% rename from test_regress/t/t_lint_always_comb_multidriven.pl rename to test_regress/t/t_lint_always_comb_multidriven_bad.pl diff --git a/test_regress/t/t_lint_always_comb_multidriven.v b/test_regress/t/t_lint_always_comb_multidriven_bad.v similarity index 100% rename from test_regress/t/t_lint_always_comb_multidriven.v rename to test_regress/t/t_lint_always_comb_multidriven_bad.v diff --git a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat.pl b/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.pl similarity index 82% rename from test_regress/t/t_lint_always_comb_multidriven_compile_public_flat.pl rename to test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.pl index 9cf2c191e..48576365b 100755 --- a/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat.pl +++ b/test_regress/t/t_lint_always_comb_multidriven_compile_public_flat_bad.pl @@ -10,12 +10,12 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(vlt => 1); -top_filename("t/t_lint_always_comb_multidriven.v"); +top_filename("t/t_lint_always_comb_multidriven_bad.v"); lint( verilator_flags2 => ['--public-flat-rw --lint-only'], fails => 1, - expect_filename => "t/t_lint_always_comb_multidriven.out", + expect_filename => "t/t_lint_always_comb_multidriven_bad.out", ); ok(1); diff --git a/test_regress/t/t_math_imm2.cpp b/test_regress/t/t_math_imm2.cpp index 3b2183cba..37cafbf37 100644 --- a/test_regress/t/t_math_imm2.cpp +++ b/test_regress/t/t_math_imm2.cpp @@ -5,7 +5,7 @@ #include -#include "Vt_math_imm2.h" +#include VM_PREFIX_INCLUDE double sc_time_stamp() { return 0; } diff --git a/test_regress/t/t_math_pow.out b/test_regress/t/t_math_pow.out new file mode 100644 index 000000000..9c2c5716a --- /dev/null +++ b/test_regress/t/t_math_pow.out @@ -0,0 +1,433 @@ +gold: u 7ffffffffffffffff**7ffffffffffffffff: uiii = ffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uiiq = ffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uiiw = ffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uiqi = ffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uiqq = ffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uiqw = ffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uiwi = ffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uiwq = ffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uiww = ffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uqii = 7fffeffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uqiq = 6fffeffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uqiw = 6fffeffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uqqi = 7ffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uqqq = 7ffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uqqw = 7ffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uqwi = 7ffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uqwq = 7ffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uqww = 7ffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uwii = 300007ffffffeffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uwiq = 30006fffefffeffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uwiw = 6fffefffefffeffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uwqi = 7fff7ffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uwqq = 7fffffff7ffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uwqw = 7fffffff7ffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uwwi = 7ffffffffffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uwwq = 7ffffffffffffffff +gold: u 7ffffffffffffffff**7ffffffffffffffff: uwww = 7ffffffffffffffff +gold: s -1**-1: siii = -1 +gold: s -1**-1: siiq = -1 +gold: s -1**-1: siiw = -1 +gold: s -1**-1: siqi = -1 +gold: s -1**-1: siqq = -1 +gold: s -1**-1: siqw = -1 +gold: s -1**-1: siwi = -1 +gold: s -1**-1: siwq = -1 +gold: s -1**-1: siww = -1 +gold: s -1**-1: sqii = -1 +gold: s -1**-1: sqiq = -1 +gold: s -1**-1: sqiw = -1 +gold: s -1**-1: sqqi = -1 +gold: s -1**-1: sqqq = -1 +gold: s -1**-1: sqqw = -1 +gold: s -1**-1: sqwi = -1 +gold: s -1**-1: sqwq = -1 +gold: s -1**-1: sqww = -1 +gold: s -1**-1: swii = -1 +gold: s -1**-1: swiq = -1 +gold: s -1**-1: swiw = -1 +gold: s -1**-1: swqi = -1 +gold: s -1**-1: swqq = -1 +gold: s -1**-1: swqw = -1 +gold: s -1**-1: swwi = -1 +gold: s -1**-1: swwq = -1 +gold: s -1**-1: swww = -1 +gold: u 7ffffffffffffffff**2: uiii = 1 +gold: u 7ffffffffffffffff**2: uiiq = 1 +gold: u 7ffffffffffffffff**2: uiiw = 1 +gold: u 7ffffffffffffffff**2: uiqi = 1 +gold: u 7ffffffffffffffff**2: uiqq = 1 +gold: u 7ffffffffffffffff**2: uiqw = 1 +gold: u 7ffffffffffffffff**2: uiwi = 1 +gold: u 7ffffffffffffffff**2: uiwq = 1 +gold: u 7ffffffffffffffff**2: uiww = 1 +gold: u 7ffffffffffffffff**2: uqii = fffe0001 +gold: u 7ffffffffffffffff**2: uqiq = fffe0001 +gold: u 7ffffffffffffffff**2: uqiw = fffe0001 +gold: u 7ffffffffffffffff**2: uqqi = 1 +gold: u 7ffffffffffffffff**2: uqqq = 1 +gold: u 7ffffffffffffffff**2: uqqw = 1 +gold: u 7ffffffffffffffff**2: uqwi = 1 +gold: u 7ffffffffffffffff**2: uqwq = 1 +gold: u 7ffffffffffffffff**2: uqww = 1 +gold: u 7ffffffffffffffff**2: uwii = fffe0001 +gold: u 7ffffffffffffffff**2: uwiq = fffe0001 +gold: u 7ffffffffffffffff**2: uwiw = fffe0001 +gold: u 7ffffffffffffffff**2: uwqi = 7fffffff000000001 +gold: u 7ffffffffffffffff**2: uwqq = 7fffffff000000001 +gold: u 7ffffffffffffffff**2: uwqw = 7fffffff000000001 +gold: u 7ffffffffffffffff**2: uwwi = 1 +gold: u 7ffffffffffffffff**2: uwwq = 1 +gold: u 7ffffffffffffffff**2: uwww = 1 +gold: s -1**2: siii = 1 +gold: s -1**2: siiq = 1 +gold: s -1**2: siiw = 1 +gold: s -1**2: siqi = 1 +gold: s -1**2: siqq = 1 +gold: s -1**2: siqw = 1 +gold: s -1**2: siwi = 1 +gold: s -1**2: siwq = 1 +gold: s -1**2: siww = 1 +gold: s -1**2: sqii = 1 +gold: s -1**2: sqiq = 1 +gold: s -1**2: sqiw = 1 +gold: s -1**2: sqqi = 1 +gold: s -1**2: sqqq = 1 +gold: s -1**2: sqqw = 1 +gold: s -1**2: sqwi = 1 +gold: s -1**2: sqwq = 1 +gold: s -1**2: sqww = 1 +gold: s -1**2: swii = 1 +gold: s -1**2: swiq = 1 +gold: s -1**2: swiw = 1 +gold: s -1**2: swqi = 1 +gold: s -1**2: swqq = 1 +gold: s -1**2: swqw = 1 +gold: s -1**2: swwi = 1 +gold: s -1**2: swwq = 1 +gold: s -1**2: swww = 1 +gold: u 7ffffffffffffffff**3: uiii = ffff +gold: u 7ffffffffffffffff**3: uiiq = ffff +gold: u 7ffffffffffffffff**3: uiiw = ffff +gold: u 7ffffffffffffffff**3: uiqi = ffff +gold: u 7ffffffffffffffff**3: uiqq = ffff +gold: u 7ffffffffffffffff**3: uiqw = ffff +gold: u 7ffffffffffffffff**3: uiwi = ffff +gold: u 7ffffffffffffffff**3: uiwq = ffff +gold: u 7ffffffffffffffff**3: uiww = ffff +gold: u 7ffffffffffffffff**3: uqii = 50002ffff +gold: u 7ffffffffffffffff**3: uqiq = 50002ffff +gold: u 7ffffffffffffffff**3: uqiw = 50002ffff +gold: u 7ffffffffffffffff**3: uqqi = 7ffffffff +gold: u 7ffffffffffffffff**3: uqqq = 7ffffffff +gold: u 7ffffffffffffffff**3: uqqw = 7ffffffff +gold: u 7ffffffffffffffff**3: uqwi = 7ffffffff +gold: u 7ffffffffffffffff**3: uqwq = 7ffffffff +gold: u 7ffffffffffffffff**3: uqww = 7ffffffff +gold: u 7ffffffffffffffff**3: uwii = fffd0002ffff +gold: u 7ffffffffffffffff**3: uwiq = fffd0002ffff +gold: u 7ffffffffffffffff**3: uwiw = fffd0002ffff +gold: u 7ffffffffffffffff**3: uwqi = 17ffffffff +gold: u 7ffffffffffffffff**3: uwqq = 17ffffffff +gold: u 7ffffffffffffffff**3: uwqw = 17ffffffff +gold: u 7ffffffffffffffff**3: uwwi = 7ffffffffffffffff +gold: u 7ffffffffffffffff**3: uwwq = 7ffffffffffffffff +gold: u 7ffffffffffffffff**3: uwww = 7ffffffffffffffff +gold: s -1**3: siii = -1 +gold: s -1**3: siiq = -1 +gold: s -1**3: siiw = -1 +gold: s -1**3: siqi = -1 +gold: s -1**3: siqq = -1 +gold: s -1**3: siqw = -1 +gold: s -1**3: siwi = -1 +gold: s -1**3: siwq = -1 +gold: s -1**3: siww = -1 +gold: s -1**3: sqii = -1 +gold: s -1**3: sqiq = -1 +gold: s -1**3: sqiw = -1 +gold: s -1**3: sqqi = -1 +gold: s -1**3: sqqq = -1 +gold: s -1**3: sqqw = -1 +gold: s -1**3: sqwi = -1 +gold: s -1**3: sqwq = -1 +gold: s -1**3: sqww = -1 +gold: s -1**3: swii = -1 +gold: s -1**3: swiq = -1 +gold: s -1**3: swiw = -1 +gold: s -1**3: swqi = -1 +gold: s -1**3: swqq = -1 +gold: s -1**3: swqw = -1 +gold: s -1**3: swwi = -1 +gold: s -1**3: swwq = -1 +gold: s -1**3: swww = -1 +gold: u 3**7ffffffffffffffff: uiii = aaab +gold: u 3**7ffffffffffffffff: uiiq = aaab +gold: u 3**7ffffffffffffffff: uiiw = aaab +gold: u 3**7ffffffffffffffff: uiqi = aaab +gold: u 3**7ffffffffffffffff: uiqq = aaab +gold: u 3**7ffffffffffffffff: uiqw = aaab +gold: u 3**7ffffffffffffffff: uiwi = aaab +gold: u 3**7ffffffffffffffff: uiwq = aaab +gold: u 3**7ffffffffffffffff: uiww = aaab +gold: u 3**7ffffffffffffffff: uqii = 64da6aaab +gold: u 3**7ffffffffffffffff: uqiq = 2aaaaaaab +gold: u 3**7ffffffffffffffff: uqiw = 2aaaaaaab +gold: u 3**7ffffffffffffffff: uqqi = 64da6aaab +gold: u 3**7ffffffffffffffff: uqqq = 2aaaaaaab +gold: u 3**7ffffffffffffffff: uqqw = 2aaaaaaab +gold: u 3**7ffffffffffffffff: uqwi = 64da6aaab +gold: u 3**7ffffffffffffffff: uqwq = 2aaaaaaab +gold: u 3**7ffffffffffffffff: uqww = 2aaaaaaab +gold: u 3**7ffffffffffffffff: uwii = 78fa2e79e4da6aaab +gold: u 3**7ffffffffffffffff: uwiq = 5b187c28aaaaaaaab +gold: u 3**7ffffffffffffffff: uwiw = 2aaaaaaaaaaaaaaab +gold: u 3**7ffffffffffffffff: uwqi = 78fa2e79e4da6aaab +gold: u 3**7ffffffffffffffff: uwqq = 5b187c28aaaaaaaab +gold: u 3**7ffffffffffffffff: uwqw = 2aaaaaaaaaaaaaaab +gold: u 3**7ffffffffffffffff: uwwi = 78fa2e79e4da6aaab +gold: u 3**7ffffffffffffffff: uwwq = 5b187c28aaaaaaaab +gold: u 3**7ffffffffffffffff: uwww = 2aaaaaaaaaaaaaaab +gold: s 3**-1: siii = 0 +gold: s 3**-1: siiq = 0 +gold: s 3**-1: siiw = 0 +gold: s 3**-1: siqi = 0 +gold: s 3**-1: siqq = 0 +gold: s 3**-1: siqw = 0 +gold: s 3**-1: siwi = 0 +gold: s 3**-1: siwq = 0 +gold: s 3**-1: siww = 0 +gold: s 3**-1: sqii = 0 +gold: s 3**-1: sqiq = 0 +gold: s 3**-1: sqiw = 0 +gold: s 3**-1: sqqi = 0 +gold: s 3**-1: sqqq = 0 +gold: s 3**-1: sqqw = 0 +gold: s 3**-1: sqwi = 0 +gold: s 3**-1: sqwq = 0 +gold: s 3**-1: sqww = 0 +gold: s 3**-1: swii = 0 +gold: s 3**-1: swiq = 0 +gold: s 3**-1: swiw = 0 +gold: s 3**-1: swqi = 0 +gold: s 3**-1: swqq = 0 +gold: s 3**-1: swqw = 0 +gold: s 3**-1: swwi = 0 +gold: s 3**-1: swwq = 0 +gold: s 3**-1: swww = 0 +gold: u 7fffffffffffffffe**1: uiii = fffe +gold: u 7fffffffffffffffe**1: uiiq = fffe +gold: u 7fffffffffffffffe**1: uiiw = fffe +gold: u 7fffffffffffffffe**1: uiqi = fffe +gold: u 7fffffffffffffffe**1: uiqq = fffe +gold: u 7fffffffffffffffe**1: uiqw = fffe +gold: u 7fffffffffffffffe**1: uiwi = fffe +gold: u 7fffffffffffffffe**1: uiwq = fffe +gold: u 7fffffffffffffffe**1: uiww = fffe +gold: u 7fffffffffffffffe**1: uqii = fffe +gold: u 7fffffffffffffffe**1: uqiq = fffe +gold: u 7fffffffffffffffe**1: uqiw = fffe +gold: u 7fffffffffffffffe**1: uqqi = 7fffffffe +gold: u 7fffffffffffffffe**1: uqqq = 7fffffffe +gold: u 7fffffffffffffffe**1: uqqw = 7fffffffe +gold: u 7fffffffffffffffe**1: uqwi = 7fffffffe +gold: u 7fffffffffffffffe**1: uqwq = 7fffffffe +gold: u 7fffffffffffffffe**1: uqww = 7fffffffe +gold: u 7fffffffffffffffe**1: uwii = fffe +gold: u 7fffffffffffffffe**1: uwiq = fffe +gold: u 7fffffffffffffffe**1: uwiw = fffe +gold: u 7fffffffffffffffe**1: uwqi = 7fffffffe +gold: u 7fffffffffffffffe**1: uwqq = 7fffffffe +gold: u 7fffffffffffffffe**1: uwqw = 7fffffffe +gold: u 7fffffffffffffffe**1: uwwi = 7fffffffffffffffe +gold: u 7fffffffffffffffe**1: uwwq = 7fffffffffffffffe +gold: u 7fffffffffffffffe**1: uwww = 7fffffffffffffffe +gold: s -2**1: siii = -2 +gold: s -2**1: siiq = -2 +gold: s -2**1: siiw = -2 +gold: s -2**1: siqi = -2 +gold: s -2**1: siqq = -2 +gold: s -2**1: siqw = -2 +gold: s -2**1: siwi = -2 +gold: s -2**1: siwq = -2 +gold: s -2**1: siww = -2 +gold: s -2**1: sqii = -2 +gold: s -2**1: sqiq = -2 +gold: s -2**1: sqiw = -2 +gold: s -2**1: sqqi = -2 +gold: s -2**1: sqqq = -2 +gold: s -2**1: sqqw = -2 +gold: s -2**1: sqwi = -2 +gold: s -2**1: sqwq = -2 +gold: s -2**1: sqww = -2 +gold: s -2**1: swii = -2 +gold: s -2**1: swiq = -2 +gold: s -2**1: swiw = -2 +gold: s -2**1: swqi = -2 +gold: s -2**1: swqq = -2 +gold: s -2**1: swqw = -2 +gold: s -2**1: swwi = -2 +gold: s -2**1: swwq = -2 +gold: s -2**1: swww = -2 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uiii = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uiiq = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uiiw = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uiqi = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uiqq = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uiqw = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uiwi = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uiwq = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uiww = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uqii = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uqiq = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uqiw = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uqqi = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uqqq = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uqqw = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uqwi = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uqwq = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uqww = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uwii = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uwiq = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uwiw = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uwqi = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uwqq = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uwqw = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uwwi = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uwwq = 0 +gold: u 7fffffffffffffffe**7ffffffffffffffff: uwww = 0 +gold: s -2**-1: siii = 0 +gold: s -2**-1: siiq = 0 +gold: s -2**-1: siiw = 0 +gold: s -2**-1: siqi = 0 +gold: s -2**-1: siqq = 0 +gold: s -2**-1: siqw = 0 +gold: s -2**-1: siwi = 0 +gold: s -2**-1: siwq = 0 +gold: s -2**-1: siww = 0 +gold: s -2**-1: sqii = 0 +gold: s -2**-1: sqiq = 0 +gold: s -2**-1: sqiw = 0 +gold: s -2**-1: sqqi = 0 +gold: s -2**-1: sqqq = 0 +gold: s -2**-1: sqqw = 0 +gold: s -2**-1: sqwi = 0 +gold: s -2**-1: sqwq = 0 +gold: s -2**-1: sqww = 0 +gold: s -2**-1: swii = 0 +gold: s -2**-1: swiq = 0 +gold: s -2**-1: swiw = 0 +gold: s -2**-1: swqi = 0 +gold: s -2**-1: swqq = 0 +gold: s -2**-1: swqw = 0 +gold: s -2**-1: swwi = 0 +gold: s -2**-1: swwq = 0 +gold: s -2**-1: swww = 0 +gold: u 7fffffffffffffffe**2: uiii = 4 +gold: u 7fffffffffffffffe**2: uiiq = 4 +gold: u 7fffffffffffffffe**2: uiiw = 4 +gold: u 7fffffffffffffffe**2: uiqi = 4 +gold: u 7fffffffffffffffe**2: uiqq = 4 +gold: u 7fffffffffffffffe**2: uiqw = 4 +gold: u 7fffffffffffffffe**2: uiwi = 4 +gold: u 7fffffffffffffffe**2: uiwq = 4 +gold: u 7fffffffffffffffe**2: uiww = 4 +gold: u 7fffffffffffffffe**2: uqii = fffc0004 +gold: u 7fffffffffffffffe**2: uqiq = fffc0004 +gold: u 7fffffffffffffffe**2: uqiw = fffc0004 +gold: u 7fffffffffffffffe**2: uqqi = 4 +gold: u 7fffffffffffffffe**2: uqqq = 4 +gold: u 7fffffffffffffffe**2: uqqw = 4 +gold: u 7fffffffffffffffe**2: uqwi = 4 +gold: u 7fffffffffffffffe**2: uqwq = 4 +gold: u 7fffffffffffffffe**2: uqww = 4 +gold: u 7fffffffffffffffe**2: uwii = fffc0004 +gold: u 7fffffffffffffffe**2: uwiq = fffc0004 +gold: u 7fffffffffffffffe**2: uwiw = fffc0004 +gold: u 7fffffffffffffffe**2: uwqi = 7ffffffe000000004 +gold: u 7fffffffffffffffe**2: uwqq = 7ffffffe000000004 +gold: u 7fffffffffffffffe**2: uwqw = 7ffffffe000000004 +gold: u 7fffffffffffffffe**2: uwwi = 4 +gold: u 7fffffffffffffffe**2: uwwq = 4 +gold: u 7fffffffffffffffe**2: uwww = 4 +gold: s -2**2: siii = 4 +gold: s -2**2: siiq = 4 +gold: s -2**2: siiw = 4 +gold: s -2**2: siqi = 4 +gold: s -2**2: siqq = 4 +gold: s -2**2: siqw = 4 +gold: s -2**2: siwi = 4 +gold: s -2**2: siwq = 4 +gold: s -2**2: siww = 4 +gold: s -2**2: sqii = 4 +gold: s -2**2: sqiq = 4 +gold: s -2**2: sqiw = 4 +gold: s -2**2: sqqi = 4 +gold: s -2**2: sqqq = 4 +gold: s -2**2: sqqw = 4 +gold: s -2**2: sqwi = 4 +gold: s -2**2: sqwq = 4 +gold: s -2**2: sqww = 4 +gold: s -2**2: swii = 4 +gold: s -2**2: swiq = 4 +gold: s -2**2: swiw = 4 +gold: s -2**2: swqi = 4 +gold: s -2**2: swqq = 4 +gold: s -2**2: swqw = 4 +gold: s -2**2: swwi = 4 +gold: s -2**2: swwq = 4 +gold: s -2**2: swww = 4 +gold: u 7fffffffffffffffe**3: uiii = fff8 +gold: u 7fffffffffffffffe**3: uiiq = fff8 +gold: u 7fffffffffffffffe**3: uiiw = fff8 +gold: u 7fffffffffffffffe**3: uiqi = fff8 +gold: u 7fffffffffffffffe**3: uiqq = fff8 +gold: u 7fffffffffffffffe**3: uiqw = fff8 +gold: u 7fffffffffffffffe**3: uiwi = fff8 +gold: u 7fffffffffffffffe**3: uiwq = fff8 +gold: u 7fffffffffffffffe**3: uiww = fff8 +gold: u 7fffffffffffffffe**3: uqii = 2000bfff8 +gold: u 7fffffffffffffffe**3: uqiq = 2000bfff8 +gold: u 7fffffffffffffffe**3: uqiw = 2000bfff8 +gold: u 7fffffffffffffffe**3: uqqi = 7fffffff8 +gold: u 7fffffffffffffffe**3: uqqq = 7fffffff8 +gold: u 7fffffffffffffffe**3: uqqw = 7fffffff8 +gold: u 7fffffffffffffffe**3: uqwi = 7fffffff8 +gold: u 7fffffffffffffffe**3: uqwq = 7fffffff8 +gold: u 7fffffffffffffffe**3: uqww = 7fffffff8 +gold: u 7fffffffffffffffe**3: uwii = fffa000bfff8 +gold: u 7fffffffffffffffe**3: uwiq = fffa000bfff8 +gold: u 7fffffffffffffffe**3: uwiw = fffa000bfff8 +gold: u 7fffffffffffffffe**3: uwqi = 5ffffffff8 +gold: u 7fffffffffffffffe**3: uwqq = 5ffffffff8 +gold: u 7fffffffffffffffe**3: uwqw = 5ffffffff8 +gold: u 7fffffffffffffffe**3: uwwi = 7fffffffffffffff8 +gold: u 7fffffffffffffffe**3: uwwq = 7fffffffffffffff8 +gold: u 7fffffffffffffffe**3: uwww = 7fffffffffffffff8 +gold: s -2**3: siii = -8 +gold: s -2**3: siiq = -8 +gold: s -2**3: siiw = -8 +gold: s -2**3: siqi = -8 +gold: s -2**3: siqq = -8 +gold: s -2**3: siqw = -8 +gold: s -2**3: siwi = -8 +gold: s -2**3: siwq = -8 +gold: s -2**3: siww = -8 +gold: s -2**3: sqii = -8 +gold: s -2**3: sqiq = -8 +gold: s -2**3: sqiw = -8 +gold: s -2**3: sqqi = -8 +gold: s -2**3: sqqq = -8 +gold: s -2**3: sqqw = -8 +gold: s -2**3: sqwi = -8 +gold: s -2**3: sqwq = -8 +gold: s -2**3: sqww = -8 +gold: s -2**3: swii = -8 +gold: s -2**3: swiq = -8 +gold: s -2**3: swiw = -8 +gold: s -2**3: swqi = -8 +gold: s -2**3: swqq = -8 +gold: s -2**3: swqw = -8 +gold: s -2**3: swwi = -8 +gold: s -2**3: swwq = -8 +gold: s -2**3: swww = -8 +*-* All Finished *-* diff --git a/test_regress/t/t_math_pow.pl b/test_regress/t/t_math_pow.pl index b46d46042..7dcc17df2 100755 --- a/test_regress/t/t_math_pow.pl +++ b/test_regress/t/t_math_pow.pl @@ -11,11 +11,35 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); compile( + verilator_flags2 => ['-fno-gate'], ); execute( check_finished => 1, + expect_filename => $Self->{golden_filename}, ); +# Check for coverage on all POW functions +system("cat $Self->{obj_dir}/$Self->{vm_prefix}_*.cpp > $Self->{obj_dir}/all.cpp"); + +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_III/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_IIQ/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_IIW/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQI/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQQ/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_QQW/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWI/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWQ/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POW_WWW/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_III/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_IIQ/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_IIW/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQI/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQQ/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_QQW/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWI/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWQ/); +file_grep("$Self->{obj_dir}/all.cpp", qr/VL_POWSS_WWW/); + ok(1); 1; diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v index dd18f3085..bf7236e89 100644 --- a/test_regress/t/t_math_pow.v +++ b/test_regress/t/t_math_pow.v @@ -1,11 +1,14 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2005 by Wilson Snyder. +// any use, without warranty, 2023 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +`define STRINGIFY(x) `"x`" + +`define stop $stop `ifdef VERILATOR - `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) `else `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) `endif @@ -17,89 +20,343 @@ module t (/*AUTOARG*/ input clk; - reg [60:0] p; - reg [60:0] a; - reg [20:0] b; - reg [60:0] shifted; + reg [66:0] a; + reg [66:0] b; - always @* begin - p = a[60:0] ** b[20:0]; - shifted = 2 ** b[20:0]; - end + wire [15:0] aui = a[15:0]; + wire [34:0] auq = a[34:0]; + wire [66:0] auw = a[66:0]; + wire [15:0] bui = b[15:0]; + wire [34:0] buq = b[34:0]; + wire [66:0] buw = b[66:0]; + wire signed [15:0] asi = a[15:0]; + wire signed [34:0] asq = a[34:0]; + wire signed [66:0] asw = a[66:0]; + wire signed [15:0] bsi = b[15:0]; + wire signed [34:0] bsq = b[34:0]; + wire signed [66:0] bsw = b[66:0]; + + // verilator lint_off WIDTH + wire [66:0] shifted = 2 ** b[20:0]; + + wire [15:0] uiii = aui ** bui; + wire [15:0] uiiq = aui ** buq; + wire [15:0] uiiw = aui ** buw; + wire [15:0] uiqi = auq ** bui; + wire [15:0] uiqq = auq ** buq; + wire [15:0] uiqw = auq ** buw; + wire [15:0] uiwi = auw ** bui; + wire [15:0] uiwq = auw ** buq; + wire [15:0] uiww = auw ** buw; + wire [34:0] uqii = aui ** bui; + wire [34:0] uqiq = aui ** buq; + wire [34:0] uqiw = aui ** buw; + wire [34:0] uqqi = auq ** bui; + wire [34:0] uqqq = auq ** buq; + wire [34:0] uqqw = auq ** buw; + wire [34:0] uqwi = auw ** bui; + wire [34:0] uqwq = auw ** buq; + wire [34:0] uqww = auw ** buw; + wire [66:0] uwii = aui ** bui; + wire [66:0] uwiq = aui ** buq; + wire [66:0] uwiw = aui ** buw; + wire [66:0] uwqi = auq ** bui; + wire [66:0] uwqq = auq ** buq; + wire [66:0] uwqw = auq ** buw; + wire [66:0] uwwi = auw ** bui; + wire [66:0] uwwq = auw ** buq; + wire [66:0] uwww = auw ** buw; + wire signed [15:0] siii = asi ** bsi; + wire signed [15:0] siiq = asi ** bsq; + wire signed [15:0] siiw = asi ** bsw; + wire signed [15:0] siqi = asq ** bsi; + wire signed [15:0] siqq = asq ** bsq; + wire signed [15:0] siqw = asq ** bsw; + wire signed [15:0] siwi = asw ** bsi; + wire signed [15:0] siwq = asw ** bsq; + wire signed [15:0] siww = asw ** bsw; + wire signed [34:0] sqii = asi ** bsi; + wire signed [34:0] sqiq = asi ** bsq; + wire signed [34:0] sqiw = asi ** bsw; + wire signed [34:0] sqqi = asq ** bsi; + wire signed [34:0] sqqq = asq ** bsq; + wire signed [34:0] sqqw = asq ** bsw; + wire signed [34:0] sqwi = asw ** bsi; + wire signed [34:0] sqwq = asw ** bsq; + wire signed [34:0] sqww = asw ** bsw; + wire signed [66:0] swii = asi ** bsi; + wire signed [66:0] swiq = asi ** bsq; + wire signed [66:0] swiw = asi ** bsw; + wire signed [66:0] swqi = asq ** bsi; + wire signed [66:0] swqq = asq ** bsq; + wire signed [66:0] swqw = asq ** bsw; + wire signed [66:0] swwi = asw ** bsi; + wire signed [66:0] swwq = asw ** bsq; + wire signed [66:0] swww = asw ** bsw; + // verilator lint_on WIDTH + + task checkpow(input [66:0] ures, input signed [66:0] sres); +`ifdef TEST_VERBOSE + $write("- lastcyc%0d: %0x**%0x = %0x (exp %0x)\n", last_cyc, a, b, uwww, ures); +`endif + // verilator lint_off WIDTH + `checkh(uiii, ures[15:0]); + `checkh(uiiq, ures[15:0]); + `checkh(uiiw, ures[15:0]); + `checkh(uiqi, ures[15:0]); + `checkh(uiqq, ures[15:0]); + `checkh(uiqw, ures[15:0]); + `checkh(uiwi, ures[15:0]); + `checkh(uiwq, ures[15:0]); + `checkh(uiww, ures[15:0]); + `checkh(uqii, ures[15:0]); + `checkh(uqiq, ures[15:0]); + `checkh(uqiw, ures[15:0]); + `checkh(uqqi, ures[34:0]); + `checkh(uqqq, ures[34:0]); + `checkh(uqqw, ures[34:0]); + `checkh(uqwi, ures[34:0]); + `checkh(uqwq, ures[34:0]); + `checkh(uqww, ures[34:0]); + `checkh(uwii, ures[15:0]); + `checkh(uwiq, ures[15:0]); + `checkh(uwiw, ures[15:0]); + `checkh(uwqi, ures[34:0]); + `checkh(uwqq, ures[34:0]); + `checkh(uwqw, ures[34:0]); + `checkh(uwwi, ures[66:0]); + `checkh(uwwq, ures[66:0]); + `checkh(uwww, ures[66:0]); +`ifdef TEST_VERBOSE + $write("- lastcyc%0d: %0d**%0d = signed %0d (exp %0d)\n", last_cyc, asw, bsw, swww, sres); +`endif + // verilator lint_off WIDTH + `checkh(siii, sres[15:0]); + `checkh(siiq, sres[15:0]); + `checkh(siiw, sres[15:0]); + `checkh(siqi, sres[15:0]); + `checkh(siqq, sres[15:0]); + `checkh(siqw, sres[15:0]); + `checkh(siwi, sres[15:0]); + `checkh(siwq, sres[15:0]); + `checkh(siww, sres[15:0]); + `checkh(sqii, sres[34:0]); + `checkh(sqiq, sres[34:0]); + `checkh(sqiw, sres[34:0]); + `checkh(sqqi, sres[34:0]); + `checkh(sqqq, sres[34:0]); + `checkh(sqqw, sres[34:0]); + `checkh(sqwi, sres[34:0]); + `checkh(sqwq, sres[34:0]); + `checkh(sqww, sres[34:0]); + `checkh(swii, sres[66:0]); + `checkh(swiq, sres[66:0]); + `checkh(swiw, sres[66:0]); + `checkh(swqi, sres[66:0]); + `checkh(swqq, sres[66:0]); + `checkh(swqw, sres[66:0]); + `checkh(swwi, sres[66:0]); + `checkh(swwq, sres[66:0]); + `checkh(swww, sres[66:0]); + // verilator lint_on WIDTH + endtask + +`define goldoneu(vu) \ + $write("gold: u %0x**%0x: %s = %0x\n", auw, buw, `STRINGIFY(vu), vu); +`define goldones(vs) \ + $write("gold: s %0d**%0d: %s = %0d\n", asw, bsw, `STRINGIFY(vs), vs); + + task golddump(); + // verilator lint_off WIDTH + `goldoneu(uiii); + `goldoneu(uiiq); + `goldoneu(uiiw); + `goldoneu(uiqi); + `goldoneu(uiqq); + `goldoneu(uiqw); + `goldoneu(uiwi); + `goldoneu(uiwq); + `goldoneu(uiww); + `goldoneu(uqii); + `goldoneu(uqiq); + `goldoneu(uqiw); + `goldoneu(uqqi); + `goldoneu(uqqq); + `goldoneu(uqqw); + `goldoneu(uqwi); + `goldoneu(uqwq); + `goldoneu(uqww); + `goldoneu(uwii); + `goldoneu(uwiq); + `goldoneu(uwiw); + `goldoneu(uwqi); + `goldoneu(uwqq); + `goldoneu(uwqw); + `goldoneu(uwwi); + `goldoneu(uwwq); + `goldoneu(uwww); + `goldones(siii); + `goldones(siiq); + `goldones(siiw); + `goldones(siqi); + `goldones(siqq); + `goldones(siqw); + `goldones(siwi); + `goldones(siwq); + `goldones(siww); + `goldones(sqii); + `goldones(sqiq); + `goldones(sqiw); + `goldones(sqqi); + `goldones(sqqq); + `goldones(sqqw); + `goldones(sqwi); + `goldones(sqwq); + `goldones(sqww); + `goldones(swii); + `goldones(swiq); + `goldones(swiw); + `goldones(swqi); + `goldones(swqq); + `goldones(swqw); + `goldones(swwi); + `goldones(swwq); + `goldones(swww); + // verilator lint_on WIDTH + endtask integer cyc; initial cyc=1; + integer last_cyc; always @ (posedge clk) begin if (cyc!=0) begin cyc <= cyc + 1; + last_cyc <= cyc; `ifdef TEST_VERBOSE - $write("%0x %x %x\n", cyc, p, shifted); + $write("- cyc%0d: %0x**%0x = sh %0x\n", cyc, a, b, shifted); `endif // Constant versions - `checkh(61'h1 ** 21'h31, 61'h1); - `checkh(61'h2 ** 21'h10, 61'h10000); - `checkh(61'd10 ** 21'h3, 61'h3e8); - `checkh(61'h3 ** 21'h7, 61'h88b); + `checkh(67'h0 ** 21'h0, 67'h1); + `checkh(67'h1 ** 21'h0, 67'h1); + `checkh(67'h2 ** 21'h0, 67'h1); + `checkh(67'h0 ** 21'h1, 67'h0); + `checkh(67'h0 ** 21'h4, 67'h0); + `checkh(67'h1 ** 21'h31, 67'h1); + `checkh(67'h2 ** 21'h10, 67'h10000); + `checkh(67'd10 ** 21'h3, 67'h3e8); + `checkh(67'h3 ** 21'h7, 67'h88b); + `checkh(67'h0 ** 21'h0, 67'h1); + `checkh(67'sh0 ** 21'sh0, 67'sh1); + `checkh(67'h10 ** 21'h0, 67'h1); `ifndef VCS `checkh(61'h7ab3811219 ** 21'ha6e30, 61'h01ea58c703687e81); `endif - if (cyc==1) begin - a <= 61'h0; - b <= 21'h0; - end - if (cyc==2) begin - a <= 61'h0; - b <= 21'h3; - end - if (cyc==3) begin - a <= 61'h1; - b <= 21'h31; - end - if (cyc==4) begin - a <= 61'h2; - b <= 21'h10; - end - if (cyc==5) begin - a <= 61'd10; - b <= 21'd3; - end - if (cyc==6) begin - a <= 61'd3; - b <= 21'd7; - end - if (cyc==7) begin - a <= 61'h7ab3811219; - b <= 21'ha6e30; - end - if (cyc==9) begin + if (cyc==0) begin end + else if (cyc==1) begin a <= 67'h0; b <= 67'h0; end + else if (cyc==2) begin a <= 67'h0; b <= 67'h3; end + else if (cyc==3) begin a <= 67'h1; b <= 67'h31; end + else if (cyc==4) begin a <= 67'h2; b <= 67'h10; end + else if (cyc==5) begin a <= 67'd10; b <= 67'd3; end + else if (cyc==6) begin a <= 67'd3; b <= 67'd7; end + else if (cyc==7) begin a <= 67'h7ab3811219; b <= 67'ha6e30; end + + else if (cyc==10) begin a <= 67'h0; b <= 67'h0; end + else if (cyc==11) begin a <= 67'h0; b <= 67'h1; end + else if (cyc==12) begin a <= 67'h0; b <= -67'h1; end + else if (cyc==13) begin a <= 67'h0; b <= 67'h2; end + else if (cyc==14) begin a <= 67'h0; b <= 67'h3; end + + else if (cyc==20) begin a <= 67'h1; b <= 67'h0; end + else if (cyc==21) begin a <= 67'h1; b <= 67'h1; end + else if (cyc==22) begin a <= 67'h1; b <= -67'h1; end + else if (cyc==23) begin a <= 67'h1; b <= 67'h2; end + else if (cyc==24) begin a <= 67'h1; b <= 67'h3; end + + else if (cyc==30) begin a <= -67'h1; b <= 67'h0; end + else if (cyc==31) begin a <= -67'h1; b <= 67'h1; end + else if (cyc==32) begin a <= -67'h1; b <= -67'h1; end + else if (cyc==33) begin a <= -67'h1; b <= 67'h2; end + else if (cyc==34) begin a <= -67'h1; b <= 67'h3; end + + else if (cyc==40) begin a <= 67'h2; b <= 67'h0; end + else if (cyc==41) begin a <= 67'h2; b <= 67'h1; end + else if (cyc==42) begin a <= 67'h2; b <= -67'h1; end + else if (cyc==43) begin a <= 67'h2; b <= 67'h2; end + else if (cyc==44) begin a <= 67'h2; b <= 67'h3; end + + else if (cyc==50) begin a <= 67'h3; b <= 67'h0; end + else if (cyc==51) begin a <= 67'h3; b <= 67'h1; end + else if (cyc==52) begin a <= 67'h3; b <= -67'h1; end + else if (cyc==53) begin a <= 67'h3; b <= 67'h2; end + else if (cyc==54) begin a <= 67'h3; b <= 67'h3; end + + else if (cyc==60) begin a <= -67'h2; b <= 67'h0; end + else if (cyc==61) begin a <= -67'h2; b <= 67'h1; end + else if (cyc==62) begin a <= -67'h2; b <= -67'h1; end + else if (cyc==63) begin a <= -67'h2; b <= 67'h2; end + else if (cyc==64) begin a <= -67'h2; b <= 67'h3; end + + else if (cyc==99) begin $write("*-* All Finished *-*\n"); $finish; end end - case (cyc) - 32'd00: ; - 32'd01: ; - 32'd02: ; // 0^x is indeterminate - 32'd03: ; // 0^x is indeterminate - 32'd04: `checkh(p, 61'h1); - 32'd05: `checkh(p, 61'h10000); - 32'd06: `checkh(p, 61'h3e8); - 32'd07: `checkh(p, 61'h88b); - 32'd08: `checkh(p, 61'h01ea58c703687e81); - 32'd09: `checkh(p, 61'h01ea58c703687e81); - default: $stop; + // IEEE: + // op1 < -1 op1 == -1 op1 == 0 op1 == 1 op1 > 1 + // op2 is positive op1 ** op2 op2 is odd -> -1, even -> 1 0 1 op1 ** op2 + // op2 is zero 1 1 1 1 1 + // op2 is negative 0 op2 is odd -> -1, even -> 1 'x 1 0 + case (last_cyc) + 32'd10: checkpow(67'h1, 67'h1); // 0 ** 0 -> 1 + 32'd11: checkpow(67'h0, 67'h0); // 0 ** 1 -> 1 + 32'd12: ; // 0 ** -1 -> x + 32'd13: checkpow(67'h0, 67'h0); // 0 ** 2 -> 0 + 32'd14: checkpow(67'h0, 67'h0); // 0 ** 3 -> 0 + + 32'd20: checkpow(67'h1, 67'h1); // 1 ** 0 -> 1 + 32'd21: checkpow(67'h1, 67'h1); // 1 ** 1 -> 1 +`ifndef IVERILOG + 32'd22: checkpow(67'h1, 67'h1); // 1 ** -1 -> 1 +`endif + 32'd23: checkpow(67'h1, 67'h1); // 1 ** 2 -> 1 + 32'd24: checkpow(67'h1, 67'h1); // 1 ** 3 -> 1 + + 32'd30: checkpow(67'h1, 67'h1); // -1 ** 0 -> 1 + 32'd31: checkpow(-67'h1, -67'h1); // -1 ** 1 -> -1 if odd else 1 + 32'd32: golddump(); // -1 ** -1 SEE GOLDEN + 32'd33: golddump(); // -1 ** 2 SEE GOLDEN + 32'd34: golddump(); // -1 ** 3 SEE GOLDEN + + 32'd40: checkpow(67'h1, 67'h1); // 2 ** 0 -> 1 + 32'd41: checkpow(67'h2, 67'h2); // 2 ** 1 + 32'd42: checkpow(67'h0, 67'h0); // 2 ** -1 -> 0 + 32'd43: checkpow(67'h4, 67'h4); // 2 ** 2 + 32'd44: checkpow(67'h8, 67'h8); // 2 ** 3 + + 32'd50: checkpow(67'h1, 67'h1); // 3 ** 0 -> 0 + 32'd51: checkpow(67'h3, 67'h3); // 3 ** 1 + 32'd52: golddump(); // 3 ** -1 -> 0 (if negative gives 0) + 32'd53: checkpow(67'h9, 67'h9); // 3 ** 2 + 32'd54: checkpow(67'h1b, 67'h1b); // 3 ** 3 + + 32'd60: checkpow(67'h1, 67'h1); // -2 ** 0 -> 1 + 32'd61: golddump(); // -2 ** 1 SEE GOLDEN + 32'd62: golddump(); // -2 ** -1 SEE GOLDEN + 32'd63: golddump(); // -2 ** 2 SEE GOLDEN + 32'd64: golddump(); // -2 ** 3 SEE GOLDEN + default: ; endcase case (cyc) 32'd00: ; 32'd01: ; - 32'd02: `checkh(shifted, 61'h0000000000000001); - 32'd03: `checkh(shifted, 61'h0000000000000008); - 32'd04: `checkh(shifted, 61'h0002000000000000); - 32'd05: `checkh(shifted, 61'h0000000000010000); - 32'd06: `checkh(shifted, 61'h0000000000000008); - 32'd07: `checkh(shifted, 61'h0000000000000080); - 32'd08: `checkh(shifted, 61'h0000000000000000); - 32'd09: `checkh(shifted, 61'h0000000000000000); - default: $stop; + 32'd02: `checkh(shifted, 67'h0000000000000001); + 32'd03: `checkh(shifted, 67'h0000000000000008); + 32'd04: `checkh(shifted, 67'h0002000000000000); + 32'd05: `checkh(shifted, 67'h0000000000010000); + 32'd06: `checkh(shifted, 67'h0000000000000008); + 32'd07: `checkh(shifted, 67'h0000000000000080); + 32'd08: `checkh(shifted, 67'h0000000000000000); + 32'd09: `checkh(shifted, 67'h0000000000000000); + default: ; endcase end endmodule diff --git a/test_regress/t/t_math_pow3.v b/test_regress/t/t_math_pow3.v index e16d50a07..d06344289 100644 --- a/test_regress/t/t_math_pow3.v +++ b/test_regress/t/t_math_pow3.v @@ -45,7 +45,7 @@ module t (/*AUTOARG*/); `checkh((-8'sh1 ** 8'sh2), 8'h1 ); // -1^odd=-1, -1^even=1 `checkh((-8'sh1 ** 8'sh3), 8'hff ); // -1^odd=-1, -1^even=1 `checkh(( 8'h0 ** 8'sh3), 8'h0 ); // 0 - `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 + `checkh(( 8'h1 ** 8'sh3), 8'h1 ); // 1 `checkh(( 8'h3 ** 8'sh3), 8'h1b ); // a**b (27) `checkh(( 8'sh3 ** 8'sh3), 8'h1b ); // a**b (27) `checkh(( 8'h6 ** 8'sh3), 8'hd8 ); // a**b (216) diff --git a/test_regress/t/t_math_pow6.v b/test_regress/t/t_math_pow6.v index 8b9801229..af43e5233 100644 --- a/test_regress/t/t_math_pow6.v +++ b/test_regress/t/t_math_pow6.v @@ -18,7 +18,7 @@ module t (/*AUTOARG*/ // -- Verilator 621c515 creates code that uses the undeclared function VL_POW_WWI() // verilator lint_off WIDTH - output [3:0] i65 = 65'd3 ** a; // WWI + output [3:0] i65 = 65'd3 ** a; // IWI output [3:0] j65 = a ** 65'd3; // IIW output [3:0] i33 = 33'd3 ** a; // QQI output [3:0] j33 = a ** 33'd3; // IIQ diff --git a/test_regress/t/t_math_pow7.cpp b/test_regress/t/t_math_pow7.cpp new file mode 100644 index 000000000..703e10f00 --- /dev/null +++ b/test_regress/t/t_math_pow7.cpp @@ -0,0 +1,42 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include VM_PREFIX_INCLUDE + +#include "TestCheck.h" + +int errors = 0; + +std::unique_ptr topp; +int main(int argc, char** argv) { + vluint64_t sim_time = 1100; + const std::unique_ptr contextp{new VerilatedContext}; + contextp->commandArgs(argc, argv); + topp.reset(new VM_PREFIX{"top"}); + + topp->eval(); + { contextp->timeInc(10); } + + int cyc = 0; + + while ((contextp->time() < sim_time) && !contextp->gotFinish()) { + topp->eval(); + contextp->timeInc(5); + + ++cyc; + if (cyc > 10) break; + } + + TEST_CHECK_EQ(topp->out_data, 1); + + topp->final(); + topp.reset(); + + printf("*-* All Finished *-*\n"); + return errors != 0; +} diff --git a/test_regress/t/t_math_pow7.pl b/test_regress/t/t_math_pow7.pl new file mode 100755 index 000000000..0a4dc8a6b --- /dev/null +++ b/test_regress/t/t_math_pow7.pl @@ -0,0 +1,27 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + make_top_shell => 0, + make_main => 0, + verilator_flags2 => [ + "--exe", + "$Self->{t_dir}/$Self->{name}.cpp" + ], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_pow7.v b/test_regress/t/t_math_pow7.v new file mode 100644 index 000000000..68a14e599 --- /dev/null +++ b/test_regress/t/t_math_pow7.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +`define stop $stop +`ifdef VERILATOR + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +`else + `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); end while(0) +`endif + +module t (/*AUTOARG*/ + // Outputs + out_data + ); + + output [11:0] out_data; + wire [11:0] out_data; + wire [11:0] a; + wire [2:0] b; + assign a = 12'h000 ** { b }; + assign b = 3'b0; + assign out_data = a; + +endmodule diff --git a/test_regress/t/t_math_shift_huge.pl b/test_regress/t/t_math_shift_huge.pl new file mode 100755 index 000000000..8c2ca139b --- /dev/null +++ b/test_regress/t/t_math_shift_huge.pl @@ -0,0 +1,17 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_shift_huge.v b/test_regress/t/t_math_shift_huge.v new file mode 100644 index 000000000..900bbc188 --- /dev/null +++ b/test_regress/t/t_math_shift_huge.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Outputs + outl, outr, + // Inputs + lhs + ); + input [95:0] lhs; + output [95:0] outl; + output [95:0] outr; + + assign outl = lhs << 95'hffff_00000000; + assign outr = lhs >> 95'hffff_00000000; + +endmodule diff --git a/test_regress/t/t_math_shift_over_bad.out b/test_regress/t/t_math_shift_over_bad.out deleted file mode 100644 index 09004172d..000000000 --- a/test_regress/t/t_math_shift_over_bad.out +++ /dev/null @@ -1,5 +0,0 @@ -%Error: t/t_math_shift_over_bad.v:19:20: Value too wide for 32-bits expected in this context 64'h123456789abcdef - : ... note: In instance 't' - 19 | assign o = i << 64'h01234567_89abcdef; - | ^~~~~~~~~~~~~~~~~~~~~ -%Error: Exiting due to diff --git a/test_regress/t/t_math_shift_over_bad.v b/test_regress/t/t_math_shift_over_bad.v deleted file mode 100644 index 3df5d7b74..000000000 --- a/test_regress/t/t_math_shift_over_bad.v +++ /dev/null @@ -1,21 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2016 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module t (/*AUTOARG*/ - // Outputs - o, - // Inputs - clk, i - ); - - input clk; - - input [31:0] i; - output [31:0] o; - - assign o = i << 64'h01234567_89abcdef; - -endmodule diff --git a/test_regress/t/t_math_wide_bad.out b/test_regress/t/t_math_wide_bad.out index b3c120d82..21b4f05ec 100644 --- a/test_regress/t/t_math_wide_bad.out +++ b/test_regress/t/t_math_wide_bad.out @@ -2,10 +2,10 @@ 23 | assign r = real'(a); | ^~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_math_wide_bad.v:22:18: Unsupported: operator POWSS operator of 576 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h +%Error-UNSUPPORTED: t/t_math_wide_bad.v:22:18: Unsupported: operator POWSS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 22 | assign z2 = a ** 3; | ^~ -%Error-UNSUPPORTED: t/t_math_wide_bad.v:21:17: Unsupported: operator MULS operator of 576 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h +%Error-UNSUPPORTED: t/t_math_wide_bad.v:21:17: Unsupported: operator MULS operator of 5472 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 21 | assign z = a * b; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_math_wide_bad.v b/test_regress/t/t_math_wide_bad.v index 8864a0bfc..fa8705010 100644 --- a/test_regress/t/t_math_wide_bad.v +++ b/test_regress/t/t_math_wide_bad.v @@ -11,11 +11,11 @@ module t (/*AUTOARG*/ a, b ); - input signed [17*32 : 0] a; - input signed [17*32 : 0] b; + input signed [170*32 : 0] a; + input signed [170*32 : 0] b; - output signed [17*32 : 0] z; - output signed [17*32 : 0] z2; + output signed [170*32 : 0] z; + output signed [170*32 : 0] z2; output real r; assign z = a * b; diff --git a/test_regress/t/t_mem_slot.cpp b/test_regress/t/t_mem_slot.cpp index dfaee4052..595c2768b 100644 --- a/test_regress/t/t_mem_slot.cpp +++ b/test_regress/t/t_mem_slot.cpp @@ -5,7 +5,7 @@ #include -#include "Vt_mem_slot.h" +#include VM_PREFIX_INCLUDE #include diff --git a/test_regress/t/t_multitop_sig.cpp b/test_regress/t/t_multitop_sig.cpp index b9bb8cfb0..95cc0aa7c 100644 --- a/test_regress/t/t_multitop_sig.cpp +++ b/test_regress/t/t_multitop_sig.cpp @@ -8,7 +8,7 @@ #include -#include "Vt_multitop_sig.h" +#include VM_PREFIX_INCLUDE #include diff --git a/test_regress/t/t_opt_dead_noassigns.pl b/test_regress/t/t_opt_dead_noassigns.pl new file mode 100755 index 000000000..2efc82758 --- /dev/null +++ b/test_regress/t/t_opt_dead_noassigns.pl @@ -0,0 +1,25 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['--fno-dead-assigns'], + ); + +execute( + check_finished => 1, + ); + +my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}_*.cpp"); +file_grep_any(\@files, qr/keptdead/ix); + +ok(1); +1; diff --git a/test_regress/t/t_opt_dead_noassigns.v b/test_regress/t/t_opt_dead_noassigns.v new file mode 100644 index 000000000..beb41c736 --- /dev/null +++ b/test_regress/t/t_opt_dead_noassigns.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + in + ); + input int in; + + int ass_keptdead; + + initial begin + if (in != 0) begin + ass_keptdead = 1 | in; + $display("Avoid gate removing"); + ass_keptdead = 2 | in; + end + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_opt_dead_nocells.pl b/test_regress/t/t_opt_dead_nocells.pl new file mode 100755 index 000000000..2d89b8430 --- /dev/null +++ b/test_regress/t/t_opt_dead_nocells.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +compile( + verilator_flags2 => ['--fno-inline', '--fno-dead-cells'], + ); + +my @files = glob_all("$Self->{obj_dir}/$Self->{vm_prefix}_*.h"); +file_grep_any(\@files, qr/keptdead/ix); + +ok(1); +1; diff --git a/test_regress/t/t_opt_dead_nocells.v b/test_regress/t/t_opt_dead_nocells.v new file mode 100644 index 000000000..b22bf2575 --- /dev/null +++ b/test_regress/t/t_opt_dead_nocells.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module Mod_Dead; +endmodule + +module t (/*AUTOARG*/); + + Mod_Dead cell_keptdead(); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_order_multidriven.cpp b/test_regress/t/t_order_multidriven.cpp index d8cd782a6..284330498 100644 --- a/test_regress/t/t_order_multidriven.cpp +++ b/test_regress/t/t_order_multidriven.cpp @@ -7,7 +7,7 @@ #include "verilated.h" #include "verilated_vcd_c.h" -#include "Vt_order_multidriven.h" +#include VM_PREFIX_INCLUDE double sc_time_stamp() { return 0; } diff --git a/test_regress/t/t_order_quad.cpp b/test_regress/t/t_order_quad.cpp index cf6c247f3..e15584148 100644 --- a/test_regress/t/t_order_quad.cpp +++ b/test_regress/t/t_order_quad.cpp @@ -8,7 +8,7 @@ #include -#include "Vt_order_quad.h" +#include VM_PREFIX_INCLUDE //====================================================================== diff --git a/test_regress/t/t_param_passed_to_port.pl b/test_regress/t/t_param_passed_to_port.pl new file mode 100755 index 000000000..e191e87f4 --- /dev/null +++ b/test_regress/t/t_param_passed_to_port.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile(); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_param_passed_to_port.v b/test_regress/t/t_param_passed_to_port.v new file mode 100644 index 000000000..7b1fb67d5 --- /dev/null +++ b/test_regress/t/t_param_passed_to_port.v @@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +parameter int HwDataAttr[1] = '{1}; + +module flash_mp_data_region_sel ( + input int region_attrs_i[1] +); + initial begin + int o = 0; + for (int i = 0; i < 1; i++) begin + o = region_attrs_i[i]; + end + if (o != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module t; + flash_mp_data_region_sel u_hw_sel (.region_attrs_i(HwDataAttr)); +endmodule diff --git a/test_regress/t/t_randc_oversize_bad.out b/test_regress/t/t_randc_oversize_bad.out index 6eaf0eefe..93bcf0c1b 100644 --- a/test_regress/t/t_randc_oversize_bad.out +++ b/test_regress/t/t_randc_oversize_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_randc_oversize_bad.v:8:21: Maxiumum implemented width for randc is 32 bits, 'i' is 38 bits +%Error: t/t_randc_oversize_bad.v:8:21: Maximum implemented width for randc is 32 bits, 'i' is 38 bits : ... note: In instance 't' 8 | randc bit [37:0] i; | ^ diff --git a/test_regress/t/t_randomize.out b/test_regress/t/t_randomize.out index 82e50c3f1..03a8a5ecf 100644 --- a/test_regress/t/t_randomize.out +++ b/test_regress/t/t_randomize.out @@ -1,36 +1,31 @@ -%Error-UNSUPPORTED: t/t_randomize.v:11:4: Unsupported: extern constraint - 11 | extern constraint ex; - | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Warning-CONSTRAINTIGN: t/t_randomize.v:13:4: Constraint ignored (unsupported) - 13 | constraint a { header > 0 && header < 1000; } - | ^~~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize.v:16:15: Constraint ignored (unsupported) + : ... note: In instance 't' + 16 | constraint empty {} + | ^~~~~ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. -%Warning-CONSTRAINTIGN: t/t_randomize.v:14:4: Constraint ignored (unsupported) - 14 | constraint b { - | ^~~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_randomize.v:19:4: Constraint ignored (unsupported) - 19 | constraint c { - | ^~~~~~~~~~ -%Warning-CONSTRAINTIGN: t/t_randomize.v:23:4: Constraint ignored (unsupported) - 23 | constraint d { - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_randomize.v:29:29: Unsupported: solve before - 29 | constraint order { solve length before header; } - | ^~~~~~ -%Warning-CONSTRAINTIGN: t/t_randomize.v:29:4: Constraint ignored (unsupported) - 29 | constraint order { solve length before header; } - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_randomize.v:32:9: Unsupported: dist - 32 | x dist { [100:102] :/ 1, 200 := 2, 300 := 5, 400}; - | ^~~~ -%Warning-CONSTRAINTIGN: t/t_randomize.v:30:4: Constraint ignored (unsupported) - 30 | constraint dis { - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_randomize.v:37:1: Unsupported: extern constraint - 37 | constraint Packet::ex { header > 0 }; - | ^~~~~~~~~~ -%Error: t/t_randomize.v:37:23: syntax error, unexpected '{' - 37 | constraint Packet::ex { header > 0 }; - | ^ +%Warning-CONSTRAINTIGN: t/t_randomize.v:18:15: Constraint ignored (unsupported) + : ... note: In instance 't' + 18 | constraint size { + | ^~~~ +%Warning-CONSTRAINTIGN: t/t_randomize.v:25:15: Constraint ignored (unsupported) + : ... note: In instance 't' + 25 | constraint ifs { + | ^~~ +%Warning-CONSTRAINTIGN: t/t_randomize.v:36:15: Constraint ignored (unsupported) + : ... note: In instance 't' + 36 | constraint arr_uniq { + | ^~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize.v:43:15: Constraint ignored (unsupported) + : ... note: In instance 't' + 43 | constraint order { solve length before header; } + | ^~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize.v:45:15: Constraint ignored (unsupported) + : ... note: In instance 't' + 45 | constraint dis { + | ^~~ +%Error-UNSUPPORTED: t/t_randomize.v:14:13: Unsupported: random member variable with type 'int$[0:1]' + : ... note: In instance 't' + 14 | rand int array[2]; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_randomize.v b/test_regress/t/t_randomize.v index 30634b113..f854daab2 100644 --- a/test_regress/t/t_randomize.v +++ b/test_regress/t/t_randomize.v @@ -5,37 +5,51 @@ // SPDX-License-Identifier: CC0-1.0 class Packet; - rand int header; - rand int length; + rand int header; // 0..7 + rand int length; // 0..15 + rand int sublength; // 0..15 + rand bit if_4; + rand bit iff_5_6; - extern constraint ex; + rand int array[2]; // 2,4,6 - constraint a { header > 0 && header < 1000; } - constraint b { - if (64 > header) { - header < (64'h1 << length); + constraint empty {} + + constraint size { + header > 0 && header <= 7; + length <= 15; + length >= header; + length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; + } + + constraint ifs { + if (header > 4) { + if_4 == '1; + } + if (header == 5 || header == 6) { + iff_5_6 == '1; + } else { + iff_5_6 == '0; } } - constraint c { - header >= length - 10; - header <= length; - } - constraint d { - foreach (in_use[i]) { - !(start_offset <= in_use[i].Xend_offsetX && - start_offset + length - 1 >= in_use[i].Xstart_offsetX); + + constraint arr_uniq { + foreach (array[i]) { + array[i] inside {2, 4, 6}; } + unique { array[0], array[1] } } + constraint order { solve length before header; } + constraint dis { - disable soft x; - x dist { [100:102] :/ 1, 200 := 2, 300 := 5, 400}; + soft sublength; + disable soft sublength; + sublength <= length; } endclass -constraint Packet::ex { header > 0 }; - module t (/*AUTOARG*/); Packet p; @@ -43,15 +57,12 @@ module t (/*AUTOARG*/); initial begin int v; + // TODO not testing constrained values v = p.randomize(); if (v != 1) $stop; - v = p.randomize(1); - if (v != 1) $stop; - v = p.randomize(1, 2); - if (v != 1) $stop; v = p.randomize() with {}; if (v != 1) $stop; - // Not testing other randomize forms as unused in UVM + // TODO not testing other randomize forms as unused in UVM $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_randomize_extern.out b/test_regress/t/t_randomize_extern.out new file mode 100644 index 000000000..a56aaa409 --- /dev/null +++ b/test_regress/t/t_randomize_extern.out @@ -0,0 +1,11 @@ +%Error-UNSUPPORTED: t/t_randomize_extern.v:8:4: Unsupported: pure constraint + 8 | pure constraint pur; + | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest +%Error-UNSUPPORTED: t/t_randomize_extern.v:17:4: Unsupported: extern constraint + 17 | extern constraint ex; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_randomize_extern.v:21:1: Unsupported: extern constraint + 21 | constraint Packet::ex { header == 2; } + | ^~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_randomize_extern.pl b/test_regress/t/t_randomize_extern.pl new file mode 100755 index 000000000..63947fd00 --- /dev/null +++ b/test_regress/t/t_randomize_extern.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_randomize_extern.v b/test_regress/t/t_randomize_extern.v new file mode 100644 index 000000000..cc74f0323 --- /dev/null +++ b/test_regress/t/t_randomize_extern.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +class Base; + pure constraint pur; +endclass + +class Packet extends Base; + rand int header; + rand int length; + + constraint pur { length == 3; } + + extern constraint ex; + +endclass + +constraint Packet::ex { header == 2; } + +module t (/*AUTOARG*/); + + Packet p; + + initial begin + + int v; + v = p.randomize(); + if (v != 1) $stop; + if (p.header != 2) $stop; + if (p.length != 3) $stop; + v = p.randomize(1); + if (v != 1) $stop; + if (p.header != 2) $stop; + if (p.length != 3) $stop; + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_rand_mode.pl b/test_regress/t/t_randomize_rand_mode.pl new file mode 100755 index 000000000..11d21fc86 --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['-Wno-CONSTRAINTIGN'], + ); + +execute( + check_finished => 1, + ); + + +ok(1); +1; diff --git a/test_regress/t/t_randomize_rand_mode.v b/test_regress/t/t_randomize_rand_mode.v new file mode 100644 index 000000000..1b4f4f12a --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode.v @@ -0,0 +1,106 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); + +// TODO Verilator ignores this setting currently, always returning 1 (rand on) +`ifdef VERILATOR + `define checkh_vlt1(gotv,expv) `checkh(gotv,1) +`else + `define checkh_vlt1(gotv,expv) `checkh(gotv,expv) +`endif + +class Packet; + rand int m_one; + rand int m_two; + + task test1; + m_one.rand_mode(0); + `checkh_vlt1(m_one.rand_mode(), 0); + m_two.rand_mode(0); + `checkh_vlt1(m_two.rand_mode(), 0); + verify(0, 0); + + m_one.rand_mode(0); + `checkh_vlt1(m_one.rand_mode(), 0); + m_two.rand_mode(1); + `checkh_vlt1(m_two.rand_mode(), 1); + verify(0, 1); + endtask + + task verify(int mode_one, int mode_two); + bit one_ne10 = '0; + bit two_ne10 = '0; + int v; + // TODO Verilator ignores this setting currently, always returning 1 (rand on) +`ifndef VERILATOR + if (m_one.rand_mode() != mode_one) $stop; + if (m_two.rand_mode() != mode_two) $stop; +`else + if (m_one.rand_mode() != 1) $stop; + if (m_two.rand_mode() != 1) $stop; +`endif + for (int i = 0; i < 20; ++i) begin + m_one = 10; + m_two = 10; + v = randomize(); + if (m_one != 10) one_ne10 = 1'b1; + if (m_two != 10) two_ne10 = 1'b1; +`ifdef TEST_VERBOSE + $display("one=%0d(rand_mode=%0d) two=%0d(rand_mode=%0d)", + m_one, mode_one, m_two, mode_two); +`endif + end + if (mode_one != 0 && !one_ne10) $stop; + if (mode_two != 0 && !two_ne10) $stop; +`ifndef VERILATOR + if (mode_one == 0 && one_ne10) $stop; + if (mode_two == 0 && two_ne10) $stop; +`endif + endtask + +endclass + +module t (/*AUTOARG*/); + + Packet p; + + int v; + + initial begin + p = new; + + p.test1(); + + // IEEE: function void object[.random_variable].rand_mode(bit on_off); + // IEEE: function int object.random_variable.rand_mode(); + // Not legal to get current rand() value on a class-only call + + // We call rand_mode here too becuase the parsing is different from that + // called from the class itself + p.m_one.rand_mode(0); + `checkh_vlt1(p.m_one.rand_mode(), 0); + p.m_two.rand_mode(0); + `checkh_vlt1(p.m_two.rand_mode(), 0); + p.verify(0, 0); + + p.m_one.rand_mode(0); + `checkh_vlt1(p.m_one.rand_mode(), 0); + p.m_two.rand_mode(1); + `checkh_vlt1(p.m_two.rand_mode(), 1); + p.verify(0, 1); + + p.rand_mode(1); + p.verify(1, 1); + + p.rand_mode(0); + p.verify(0, 0); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize_rand_mode_warn_bad.out b/test_regress/t/t_randomize_rand_mode_warn_bad.out new file mode 100644 index 000000000..55728b85c --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_warn_bad.out @@ -0,0 +1,115 @@ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:22:13: rand_mode ignored (unsupported) + : ... note: In instance 't' + 22 | m_one.rand_mode(0); + | ^~~~~~~~~ + ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest + ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:23:136: rand_mode ignored (unsupported) + : ... note: In instance 't' + 23 | do if ((m_one.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",23, (m_one.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:23:21: rand_mode ignored (unsupported) + : ... note: In instance 't' + 23 | do if ((m_one.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",23, (m_one.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:24:13: rand_mode ignored (unsupported) + : ... note: In instance 't' + 24 | m_two.rand_mode(0); + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:25:136: rand_mode ignored (unsupported) + : ... note: In instance 't' + 25 | do if ((m_two.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",25, (m_two.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:25:21: rand_mode ignored (unsupported) + : ... note: In instance 't' + 25 | do if ((m_two.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",25, (m_two.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:44:17: rand_mode ignored (unsupported) + : ... note: In instance 't' + 44 | if (m_one.rand_mode() != 1) $stop; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:45:17: rand_mode ignored (unsupported) + : ... note: In instance 't' + 45 | if (m_two.rand_mode() != 1) $stop; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:28:13: rand_mode ignored (unsupported) + : ... note: In instance 't' + 28 | m_one.rand_mode(0); + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:29:136: rand_mode ignored (unsupported) + : ... note: In instance 't' + 29 | do if ((m_one.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",29, (m_one.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:29:21: rand_mode ignored (unsupported) + : ... note: In instance 't' + 29 | do if ((m_one.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",29, (m_one.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:30:13: rand_mode ignored (unsupported) + : ... note: In instance 't' + 30 | m_two.rand_mode(1); + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:31:136: rand_mode ignored (unsupported) + : ... note: In instance 't' + 31 | do if ((m_two.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",31, (m_two.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:31:21: rand_mode ignored (unsupported) + : ... note: In instance 't' + 31 | do if ((m_two.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",31, (m_two.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:85:15: rand_mode ignored (unsupported) + : ... note: In instance 't' + 85 | p.m_one.rand_mode(0); + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:86:140: rand_mode ignored (unsupported) + : ... note: In instance 't' + 86 | do if ((p.m_one.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",86, (p.m_one.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:86:23: rand_mode ignored (unsupported) + : ... note: In instance 't' + 86 | do if ((p.m_one.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",86, (p.m_one.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:87:15: rand_mode ignored (unsupported) + : ... note: In instance 't' + 87 | p.m_two.rand_mode(0); + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:88:140: rand_mode ignored (unsupported) + : ... note: In instance 't' + 88 | do if ((p.m_two.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",88, (p.m_two.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:88:23: rand_mode ignored (unsupported) + : ... note: In instance 't' + 88 | do if ((p.m_two.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",88, (p.m_two.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:91:15: rand_mode ignored (unsupported) + : ... note: In instance 't' + 91 | p.m_one.rand_mode(0); + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:92:140: rand_mode ignored (unsupported) + : ... note: In instance 't' + 92 | do if ((p.m_one.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",92, (p.m_one.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:92:23: rand_mode ignored (unsupported) + : ... note: In instance 't' + 92 | do if ((p.m_one.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",92, (p.m_one.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:93:15: rand_mode ignored (unsupported) + : ... note: In instance 't' + 93 | p.m_two.rand_mode(1); + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:94:140: rand_mode ignored (unsupported) + : ... note: In instance 't' + 94 | do if ((p.m_two.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",94, (p.m_two.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:94:23: rand_mode ignored (unsupported) + : ... note: In instance 't' + 94 | do if ((p.m_two.rand_mode()) !== (1)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", "t/t_randomize_rand_mode.v",94, (p.m_two.rand_mode()), (1)); $stop; end while(0);; + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:97:9: rand_mode ignored (unsupported) + : ... note: In instance 't' + 97 | p.rand_mode(1); + | ^~~~~~~~~ +%Warning-CONSTRAINTIGN: t/t_randomize_rand_mode.v:100:9: rand_mode ignored (unsupported) + : ... note: In instance 't' + 100 | p.rand_mode(0); + | ^~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_randomize_rand_mode_warn_bad.pl b/test_regress/t/t_randomize_rand_mode_warn_bad.pl new file mode 100755 index 000000000..9c0016ff5 --- /dev/null +++ b/test_regress/t/t_randomize_rand_mode_warn_bad.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_randomize_rand_mode.v"); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_repeat.v b/test_regress/t/t_repeat.v index b80287bad..54c20c4d9 100644 --- a/test_regress/t/t_repeat.v +++ b/test_regress/t/t_repeat.v @@ -26,12 +26,8 @@ module t (/*AUTOARG*/); end if (times != 10) $stop; // - // verilator lint_off INFINITELOOP - forever begin - // verilator lint_on INFINITELOOP - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; end endmodule diff --git a/test_regress/t/t_runflag_bad.pl b/test_regress/t/t_runflag_bad.pl index 0eeef974c..d96c0ccbf 100755 --- a/test_regress/t/t_runflag_bad.pl +++ b/test_regress/t/t_runflag_bad.pl @@ -32,13 +32,13 @@ execute( ); execute( - all_run_flags => ["+verilator+prof+threads+window+0"], + all_run_flags => ["+verilator+prof+exec+window+0"], fails => 1, expect_filename => "t/" . $Self->{name} . "_d.out", ); execute( - all_run_flags => ["+verilator+prof+threads+window+1000000000000000000000000"], + all_run_flags => ["+verilator+prof+exec+window+1000000000000000000000000"], fails => 1, expect_filename => "t/" . $Self->{name} . "_e.out", ); diff --git a/test_regress/t/t_runflag_bad_d.out b/test_regress/t/t_runflag_bad_d.out index f46b3bcaa..8e6705a6c 100644 --- a/test_regress/t/t_runflag_bad_d.out +++ b/test_regress/t/t_runflag_bad_d.out @@ -1,2 +1,2 @@ -%Error: COMMAND_LINE:0: Argument '+verilator+prof+threads+window+' must be an unsigned integer, greater than 0 +%Error: COMMAND_LINE:0: Argument '+verilator+prof+exec+window+' must be an unsigned integer, greater than 0 Aborting... diff --git a/test_regress/t/t_runflag_bad_e.out b/test_regress/t/t_runflag_bad_e.out index 7ad4052fd..ed248d409 100644 --- a/test_regress/t/t_runflag_bad_e.out +++ b/test_regress/t/t_runflag_bad_e.out @@ -1,2 +1,2 @@ -%Error: COMMAND_LINE:0: Argument '+verilator+prof+threads+window+' must be an unsigned integer, greater than 0. Value out of range of uint64_t +%Error: COMMAND_LINE:0: Argument '+verilator+prof+exec+window+' must be an unsigned integer, greater than 0. Value out of range of uint64_t Aborting... diff --git a/test_regress/t/t_sc_names.cpp b/test_regress/t/t_sc_names.cpp index 4380c8064..354d27ce2 100644 --- a/test_regress/t/t_sc_names.cpp +++ b/test_regress/t/t_sc_names.cpp @@ -4,7 +4,6 @@ // SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE -#include "Vt_sc_names.h" using namespace sc_core; diff --git a/test_regress/t/t_scope_map.cpp b/test_regress/t/t_scope_map.cpp index 9d1e4a39e..93de549dc 100644 --- a/test_regress/t/t_scope_map.cpp +++ b/test_regress/t/t_scope_map.cpp @@ -10,7 +10,7 @@ #include #include -#include "Vt_scope_map.h" +#include VM_PREFIX_INCLUDE #include #include diff --git a/test_regress/t/t_selextract_in_paramextends.pl b/test_regress/t/t_selextract_in_paramextends.pl new file mode 100755 index 000000000..b267631e9 --- /dev/null +++ b/test_regress/t/t_selextract_in_paramextends.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["--timing"], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_selextract_in_paramextends.v b/test_regress/t/t_selextract_in_paramextends.v new file mode 100644 index 000000000..f371482d6 --- /dev/null +++ b/test_regress/t/t_selextract_in_paramextends.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +typedef class Foo; + +virtual class Bar #(type T); + T m_val; +endclass + +class Baz; + rand bit [3:0] m_sus; +endclass + +class Foo extends Bar#(Baz); + function new(); + Baz baz; + super.new(); + baz = new; + super.m_val = baz; + endfunction + + task update_value(Foo foo, bit [1:0] val); + m_val.m_sus[1:0] = val; + endtask +endclass + +module test(); + initial begin + Foo foo = new; + + for (int i = 0; i < 10; i++) begin + logic [3:0] v; + foo.update_value(foo, i[1:0]); + v = foo.m_val.m_sus; + if (v[1:0] != i[1:0]) $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_timescale_parse.cpp b/test_regress/t/t_timescale_parse.cpp index 0b4da3371..2a011930d 100644 --- a/test_regress/t/t_timescale_parse.cpp +++ b/test_regress/t/t_timescale_parse.cpp @@ -4,7 +4,7 @@ // any use, without warranty, 2019 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -#include "Vt_timescale_parse.h" +#include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; diff --git a/test_regress/t/t_timing_debug1.out b/test_regress/t/t_timing_debug1.out index 446a374ed..fae5ac2e7 100644 --- a/test_regress/t/t_timing_debug1.out +++ b/test_regress/t/t_timing_debug1.out @@ -6,13 +6,13 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_static -V{t#,#}+ Vt_timing_debug1___024root___eval_static__TOP -V{t#,#}+ Vt_timing_debug1___024root___eval_initial --V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__0 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 --V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__1 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 --V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__2 +-V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__2 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:50 --V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__3 +-V{t#,#}+ Vt_timing_debug1___024root___eval_initial__TOP__Vtiming__3 -V{t#,#}+ Vt_timing_debug1___024root___eval_settle -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl @@ -83,8 +83,8 @@ -V{t#,#} Awaiting time 3: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 3: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 @@ -148,9 +148,9 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 6: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -192,9 +192,9 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 +-V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 @@ -230,8 +230,8 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -288,9 +288,9 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 @@ -360,9 +360,9 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:50 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 --V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 +-V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:50 @@ -408,8 +408,8 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 @@ -587,8 +587,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 21: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -644,8 +644,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 22: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 24: Process waiting at t/t_timing_sched.v:10 +-V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 @@ -688,8 +688,8 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 24: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -731,8 +731,8 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 27: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:17 @@ -867,8 +867,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 31: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 33: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 @@ -985,9 +985,9 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 34: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Awaiting time 36: Process waiting at t/t_timing_sched.v:10 +-V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 --V{t#,#} Awaiting time 37: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:50 @@ -1102,8 +1102,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 39: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1208,8 +1208,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 43: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 44: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 @@ -1287,8 +1287,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1424,8 +1424,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 51: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1481,8 +1481,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 54: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 @@ -1525,8 +1525,8 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 @@ -1635,8 +1635,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 57: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1778,8 +1778,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 63: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1835,8 +1835,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 67: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 66: Process waiting at t/t_timing_sched.v:10 +-V{t#,#} Awaiting time 67: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 @@ -1882,8 +1882,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 67: Process waiting at t/t_timing_sched.v:17 --V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 69: Process waiting at t/t_timing_sched.v:10 +-V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 @@ -2056,8 +2056,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Awaiting time 77: Process waiting at t/t_timing_sched.v:13 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -2182,15 +2182,15 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:10 +-V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Awaiting time 79: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 88: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:52 *-* All Finished *-* +-V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:50 -V{t#,#} Suspending process waiting for @(posedge t.clk2) at t/t_timing_sched.v:50 -V{t#,#}+ Vt_timing_debug1___024root___eval_act diff --git a/test_regress/t/t_timing_debug2.out b/test_regress/t/t_timing_debug2.out index 763d17a89..ac4dd1943 100644 --- a/test_regress/t/t_timing_debug2.out +++ b/test_regress/t/t_timing_debug2.out @@ -35,16 +35,16 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2___024root___eval_initial --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__0 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__0 -V{t#,#} Suspending process waiting for @([event] t.ec.e) at t/t_timing_class.v:111 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__1 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__2 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__3 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__4 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__1 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__2 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__3 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__4 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_count_5 -V{t#,#} Suspending process waiting for @(posedge t::ClkClass.clk) at t/t_timing_class.v:97 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__5 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__6 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__5 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelayClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::new @@ -64,7 +64,7 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::__VnoInFunc_do_delay --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__7 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__7 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::_ctor_var_reset -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork @@ -74,8 +74,8 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkClass::__VnoInFunc_do_fork____Vfork_1__1____Vfork_2__1 -V{t#,#} Awaiting join of fork at: t/t_timing_class.v:250 -V{t#,#} Awaiting join of fork at: t/t_timing_class.v:245 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__8 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__9 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__8 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__9 -V{t#,#}+ Vt_timing_debug2___024root___eval_settle -V{t#,#}+ Eval -V{t#,#}+ Vt_timing_debug2___024root___eval @@ -110,13 +110,13 @@ -V{t#,#} Awaiting time 5: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:173 -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:247 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip @@ -173,22 +173,22 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:247 -V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:173 +-V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:247 +-V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 --V{t#,#} Awaiting time 10: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:247 --V{t#,#} Process forked at t/t_timing_class.v:246 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:173 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay10::__VnoInFunc_do_sth_else -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay20::__VnoInFunc_do_delay +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:247 +-V{t#,#} Process forked at t/t_timing_class.v:246 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_act @@ -230,14 +230,14 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 15: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip @@ -294,22 +294,22 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:119 --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 +-V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:252 -V{t#,#} Awaiting time 20: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:119 +-V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_wake -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:252 -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::new -V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::_ctor_var_reset -V{t#,#} Process forked at t/t_timing_class.v:251 finished --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:119 --V{t#,#}+ Vt_timing_debug2_t__03a__03aEventClass::__VnoInFunc_wake -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_act @@ -396,10 +396,10 @@ -V{t#,#} Awaiting time 25: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip @@ -488,21 +488,21 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:257 +-V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:174 -V{t#,#} Awaiting time 30: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 -V{t#,#} Resuming delayed processes +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:257 +-V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::__VnoInFunc_do_delay -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:174 -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay20::__VnoInFunc_do_sth_else -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay40::__VnoInFunc_do_delay -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:257 --V{t#,#}+ Vt_timing_debug2_t__03a__03aForkDelayClass::__VnoInFunc_do_delay -V{t#,#}+ Vt_timing_debug2___024root___eval_act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act @@ -566,12 +566,12 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 35: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 +-V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip @@ -661,12 +661,12 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:120 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 40: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 --V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:120 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 @@ -752,11 +752,11 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 45: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip @@ -817,11 +817,11 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:122 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 50: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:122 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 @@ -865,11 +865,11 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 55: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:123 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip @@ -912,11 +912,11 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:123 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 60: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:123 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 @@ -980,9 +980,9 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 65: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:76 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 @@ -1025,17 +1025,13 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:76 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:238 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 +-V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:76 -V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 --V{t#,#} Awaiting time 70: Process waiting at t/t_timing_class.v:175 -V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:76 --V{t#,#} Process forked at t/t_timing_class.v:76 finished --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 --V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:238 -V{t#,#} Process forked at t/t_timing_class.v:256 finished -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:250 @@ -1045,8 +1041,12 @@ -V{t#,#}+ Vt_timing_debug2_t__03a__03aDelay40::__VnoInFunc_do_sth_else -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::__VnoInFunc_do_delay -V{t#,#}+ Vt_timing_debug2_t__03a__03aNoDelay::__VnoInFunc_do_sth_else --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__6____Vfork_1__0 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6____Vfork_1__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::__VnoInFunc_do_assign +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:76 +-V{t#,#} Process forked at t/t_timing_class.v:76 finished +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 +-V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip -V{t#,#}+ Vt_timing_debug2___024root___eval_act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act @@ -1094,15 +1094,15 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_commit -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: --V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:224 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 +-V{t#,#} Awaiting time 75: Process waiting at t/t_timing_class.v:131 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:190 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes +-V{t#,#} Resuming: Process waiting at t/t_timing_class.v:224 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip --V{t#,#} Resuming: Process waiting at t/t_timing_class.v:224 -V{t#,#}+ Vt_timing_debug2___024root___eval_act -V{t#,#}+ Vt_timing_debug2___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug2___024root___eval_triggers__act @@ -1134,12 +1134,12 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:136 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:190 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Awaiting time 80: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:136 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:190 --V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__6____Vfork_2__0 +-V{t#,#}+ Vt_timing_debug2_t___eval_initial__TOP__t__Vtiming__6____Vfork_2__0 -V{t#,#}+ Vt_timing_debug2_t__03a__03aAssignDelayClass::__VnoInFunc_do_assign -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip @@ -1211,8 +1211,8 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:190 -V{t#,#} Awaiting time 90: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:190 -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 @@ -1248,8 +1248,8 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 95: Process waiting at t/t_timing_class.v:131 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:131 -V{t#,#}+ Vt_timing_debug2_t__03a__03aClkClass::__VnoInFunc_flip @@ -1283,8 +1283,8 @@ -V{t#,#}+ Vt_timing_debug2___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:231 --V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Awaiting time 100: Process waiting at t/t_timing_class.v:131 +-V{t#,#} Awaiting time 101: Process waiting at t/t_timing_class.v:274 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_class.v:231 *-* All Finished *-* diff --git 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+#2996600 +#2996800 +#2997000 +#2997200 +#2997400 +#2997600 +#2997800 +#2998000 +#2998200 +#2998400 +#2998600 +#2998800 +#2999000 +#2999200 +#2999400 +#2999600 +#2999800 +#3000000 diff --git a/test_regress/t/t_timing_osc.pl b/test_regress/t/t_timing_osc.pl new file mode 100755 index 000000000..63ec0902b --- /dev/null +++ b/test_regress/t/t_timing_osc.pl @@ -0,0 +1,25 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["--exe --main --timing --trace"], + make_main => 0, + ); + +execute( + check_finished => 1, + ); + +vcd_identical($Self->trace_filename, $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_timing_osc.v b/test_regress/t/t_timing_osc.v new file mode 100644 index 000000000..af184aacd --- /dev/null +++ b/test_regress/t/t_timing_osc.v @@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`define STRINGIFY(x) `"x`" + +module tb_osc; + + timeunit 1s; + timeprecision 1fs; + + logic dco_out; + + bhv_dco dco ( + // Inputs + .coarse_cw(8.0), + .medium_cw(8.0), + .fine_cw(32.0), + + // Outputs + .rf_out(dco_out) + ); + + initial begin + $dumpfile(`STRINGIFY(`TEST_DUMPFILE)); + $dumpvars; +`ifdef TEST_BENCHMARK + #200ns; +`else + #3ns; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module bhv_dco ( + input real coarse_cw, + input real medium_cw, + input real fine_cw, + output logic rf_out + ); + + parameter realtime coarse_ofst = 600ps; + parameter realtime coarse_res = 60ps; + parameter realtime medium_ofst = 130ps; + parameter realtime medium_res = 6ps; + parameter realtime fine_ofst = 70ps; + parameter realtime fine_res = 0.2ps; + + timeunit 1s; + timeprecision 1fs; + + realtime coarse_delay, medium_delay, fine_delay, jitter; + assign coarse_delay = 0.5 * (coarse_cw * coarse_res + coarse_ofst ); + assign medium_delay = 0.5 * (medium_cw * medium_res + medium_ofst ); + assign fine_delay = 0.5 * ( fine_cw * fine_res + fine_ofst + jitter); + assign jitter = 0; + + logic coarse_out, medium_out, fine_out; + + initial coarse_out = 0; + always @ (fine_out) coarse_out <= #coarse_delay ~fine_out; + assign #medium_delay medium_out = ~coarse_out; + assign #fine_delay fine_out = ~medium_out; + + assign #50ps rf_out = fine_out; + +endmodule diff --git a/test_regress/t/t_timing_trace.out b/test_regress/t/t_timing_trace.out index 015cb9eae..c5a28236b 100644 --- a/test_regress/t/t_timing_trace.out +++ b/test_regress/t/t_timing_trace.out @@ -1,6 +1,5 @@ $version Generated by VerilatedVcd $end $timescale 1ps $end - $scope module TOP $end $scope module t $end $var wire 32 * CLK_PERIOD [31:0] $end @@ -87,10 +86,3 @@ b00000000000000000000000000000101 + 1% 1' 0( -0) -#105 -1( -#110 -1' -0( -1) diff --git a/test_regress/t/t_timing_trace.v b/test_regress/t/t_timing_trace.v index fa1471eb5..393056f7a 100644 --- a/test_regress/t/t_timing_trace.v +++ b/test_regress/t/t_timing_trace.v @@ -36,10 +36,11 @@ module t; while (b) begin c = ~c; - -> ev ; + -> ev; #CLK_PERIOD; end + $write("[%0t] Done\n", $time); $write("*-* All Finished *-*\n"); $finish; end diff --git a/test_regress/t/t_timing_trace_fst.out b/test_regress/t/t_timing_trace_fst.out index 44e15ea4b..0de0227ee 100644 --- a/test_regress/t/t_timing_trace_fst.out +++ b/test_regress/t/t_timing_trace_fst.out @@ -1,5 +1,5 @@ $date - Fri Mar 31 18:34:51 2023 + Sun Nov 5 12:08:16 2023 $end $version @@ -94,10 +94,3 @@ $end 0$ 1) 1' -0& -#105 -1$ -#110 -0$ -1& -1) diff --git a/test_regress/t/t_timing_zerodly.pl b/test_regress/t/t_timing_zerodly.pl new file mode 100755 index 000000000..bbc99cfb6 --- /dev/null +++ b/test_regress/t/t_timing_zerodly.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2022 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["--exe --main --timing"], + make_main => 0, + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_timing_zerodly.v b/test_regress/t/t_timing_zerodly.v new file mode 100644 index 000000000..941c6df01 --- /dev/null +++ b/test_regress/t/t_timing_zerodly.v @@ -0,0 +1,42 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +class Foo; + static task fork_w_zerodly(longint unsigned current_time); + bit my_bit; + bit zero_dly_first = 0; + // Th code below relies on Verilator's deterministic scheduler and is not + // compatible across different simulators. + // + // The `zero_dly` block is going to be executed first and then suspended at the #0 delay. + // Then the `finish_before` block is going to be executed. Once that happens, the + // execution of `zero_dly` block should be resumed, all within a single time-slot. + // + // IF THIS TEST FAILS AFTER CHANGES TO VERILATOR'S SCHEDULER, IT DOESN'T NECESSARILY + // MEAN THE CHANGES ARE WRONG. + fork + begin : zero_dly + zero_dly_first = 1; + #0; + if (current_time != $time) $stop; + if (my_bit == 0) $stop; + end : zero_dly + begin : finish_before + if (!zero_dly_first) $stop; + my_bit = 1; + end : finish_before + join_none + #1 $display("After fork."); // Check if there's no skipped coroutine + endtask +endclass + +module test(); + initial begin + Foo::fork_w_zerodly($time); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_timing_zerodly_unsup.out b/test_regress/t/t_timing_zerodly_unsup.out index bc85c6dcb..8e56ef2cf 100644 --- a/test_regress/t/t_timing_zerodly_unsup.out +++ b/test_regress/t/t_timing_zerodly_unsup.out @@ -1,6 +1,3 @@ -%Warning-ZERODLY: t/t_timing_zerodly_unsup.v:12:13: Unsupported: #0 delays do not schedule process resumption in the Inactive region - 12 | #0 if (v) $finish; - | ^ - ... For warning description see https://verilator.org/warn/ZERODLY?v=latest - ... Use "/* verilator lint_off ZERODLY */" and lint_on around source to disable this message. -%Error: Exiting due to +%Warning: t/t_timing_zerodly_unsup.v:22: Encountered #0 delay. #0 scheduling support is incomplete and the process will be resumed before combinational logic evaluation. +%Error: t/t_timing_zerodly_unsup.v:23: Verilog $stop +Aborting... diff --git a/test_regress/t/t_timing_zerodly_unsup.pl b/test_regress/t/t_timing_zerodly_unsup.pl index 8ab3c0995..2d852adb1 100755 --- a/test_regress/t/t_timing_zerodly_unsup.pl +++ b/test_regress/t/t_timing_zerodly_unsup.pl @@ -8,10 +8,14 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(linter => 1); +scenarios(simulator => 1); -lint( - verilator_flags2 => ["--timing"], +compile( + verilator_flags2 => ["--exe --main --timing"], + make_main => 0, + ); + +execute( fails => 1, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_timing_zerodly_unsup.v b/test_regress/t/t_timing_zerodly_unsup.v index 7fba70252..5c10fa12e 100644 --- a/test_regress/t/t_timing_zerodly_unsup.v +++ b/test_regress/t/t_timing_zerodly_unsup.v @@ -5,14 +5,23 @@ // SPDX-License-Identifier: CC0-1.0 module t; - event e; - logic v = 0; - initial #1 begin - fork - #0 if (v) $finish; - else $stop; - join_none - ->e; - end - initial @e v = 1; + logic v; + int num; + + initial begin + num = 1; + #1; + if (v) $stop; + num = 21; + // Zero delay should postpone the execution and resume it after + // evaluating combinational logic which would update `v`. However, + // currently we can't postpone the resumption in the current timeframe + // past the combinatorial logic evaluation as that is intertwined with + // NBA evaluation and partitioned for multithreading. This causes `v` + // to not have its value updated despite being checked after #0 delay. + #0 if (v) $finish; + $stop; + end + + always_comb v = (num == 21); endmodule diff --git a/test_regress/t/t_trace_complex_fst.out b/test_regress/t/t_trace_complex_fst.out index 39236fad4..d4ca2fffa 100644 --- a/test_regress/t/t_trace_complex_fst.out +++ b/test_regress/t/t_trace_complex_fst.out @@ -1,5 +1,5 @@ $date - Tue Oct 24 11:00:03 2023 + Thu Dec 14 09:06:44 2023 $end $version @@ -9,6 +9,8 @@ $timescale 1ps $end $scope module top $end +$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end +$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end @@ -36,12 +38,10 @@ $var real 64 4 v_real $end $var real 64 5 v_arr_real[0] $end $var real 64 6 v_arr_real[1] $end $var logic 64 7 v_str32x2 [63:0] $end -$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var int 32 8 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 9 v_enumed2 [31:0] $end -$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 : v_enumb [2:0] $end $var logic 6 ; v_enumb2_str [5:0] $end @@ -67,8 +67,8 @@ $upscope $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars +#0 b00000000000000000000000000000000 D b00000000000000000000000000000000 C b00000000000000000000000000000011 B @@ -105,7 +105,6 @@ b00 $ b00000000000000000000000000000000 # 0" 1! -$end #10 1" b00000000000000000000000000000001 # diff --git a/test_regress/t/t_trace_complex_fst_sc.out b/test_regress/t/t_trace_complex_fst_sc.out index ceef7646a..9cb3b3fdd 100644 --- a/test_regress/t/t_trace_complex_fst_sc.out +++ b/test_regress/t/t_trace_complex_fst_sc.out @@ -1,5 +1,5 @@ $date - Tue Oct 24 11:09:24 2023 + Thu Dec 14 10:34:23 2023 $end $version @@ -9,6 +9,8 @@ $timescale 1ps $end $scope module top $end +$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end +$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end @@ -35,12 +37,10 @@ $var real 64 4 v_real $end $var real 64 5 v_arr_real[0] $end $var real 64 6 v_arr_real[1] $end $var logic 64 7 v_str32x2 [63:0] $end -$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var int 32 8 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 9 v_enumed2 [31:0] $end -$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 : v_enumb [2:0] $end $var logic 6 ; v_enumb2_str [5:0] $end @@ -66,8 +66,8 @@ $upscope $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars +#0 b00000000000000000000000000000000 D b00000000000000000000000000000000 C b00000000000000000000000000000011 B @@ -104,7 +104,6 @@ b00 $ b00000000000000000000000000000000 # 0" 1! -$end #10 1" b00000000000000000000000000000001 # diff --git a/test_regress/t/t_trace_complex_params_fst.out b/test_regress/t/t_trace_complex_params_fst.out index 803d49c16..b212749f5 100644 --- a/test_regress/t/t_trace_complex_params_fst.out +++ b/test_regress/t/t_trace_complex_params_fst.out @@ -1,5 +1,5 @@ $date - Tue Oct 24 11:02:57 2023 + Thu Dec 14 09:16:48 2023 $end $version @@ -9,6 +9,8 @@ $timescale 1ps $end $scope module top $end +$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end +$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end @@ -36,12 +38,10 @@ $var real 64 4 v_real $end $var real 64 5 v_arr_real[0] $end $var real 64 6 v_arr_real[1] $end $var logic 64 7 v_str32x2 [63:0] $end -$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var int 32 8 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 9 v_enumed2 [31:0] $end -$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 : v_enumb [2:0] $end $var logic 6 ; v_enumb2_str [5:0] $end @@ -67,8 +67,8 @@ $upscope $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars +#0 b00000000000000000000000000000000 D b00000000000000000000000000000000 C b00000000000000000000000000000011 B @@ -105,7 +105,6 @@ b00 $ b00000000000000000000000000000000 # 0" 1! -$end #10 1" b00000000000000000000000000000001 # diff --git a/test_regress/t/t_trace_complex_params_fst_sc.out b/test_regress/t/t_trace_complex_params_fst_sc.out index 46e0911c9..f05ce81a0 100644 --- a/test_regress/t/t_trace_complex_params_fst_sc.out +++ b/test_regress/t/t_trace_complex_params_fst_sc.out @@ -1,5 +1,5 @@ $date - Tue Oct 24 11:09:58 2023 + Thu Dec 14 10:35:10 2023 $end $version @@ -9,6 +9,8 @@ $timescale 1ps $end $scope module top $end +$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end +$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end @@ -35,12 +37,10 @@ $var real 64 4 v_real $end $var real 64 5 v_arr_real[0] $end $var real 64 6 v_arr_real[1] $end $var logic 64 7 v_str32x2 [63:0] $end -$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var int 32 8 v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 9 v_enumed2 [31:0] $end -$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 : v_enumb [2:0] $end $var logic 6 ; v_enumb2_str [5:0] $end @@ -66,8 +66,8 @@ $upscope $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars +#0 b00000000000000000000000000000000 D b00000000000000000000000000000000 C b00000000000000000000000000000011 B @@ -104,7 +104,6 @@ b00 $ b00000000000000000000000000000000 # 0" 1! -$end #10 1" b00000000000000000000000000000001 # diff --git a/test_regress/t/t_trace_complex_structs_fst.out b/test_regress/t/t_trace_complex_structs_fst.out index 81ae0ea36..e3ded82e6 100644 --- a/test_regress/t/t_trace_complex_structs_fst.out +++ b/test_regress/t/t_trace_complex_structs_fst.out @@ -1,5 +1,5 @@ $date - Tue Oct 24 11:01:27 2023 + Thu Dec 14 09:17:16 2023 $end $version @@ -9,6 +9,8 @@ $timescale 1ps $end $scope module top $end +$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end +$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end @@ -76,12 +78,10 @@ $upscope $end $scope struct v_str32x2[1] $end $var logic 32 C data [31:0] $end $upscope $end -$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var int 32 D v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 E v_enumed2 [31:0] $end -$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 F v_enumb [2:0] $end $scope struct v_enumb2_str $end @@ -103,8 +103,8 @@ $upscope $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars +#0 b00000000000000000000000000000000 N b00000000000000000000000000000000 M 0L @@ -151,7 +151,6 @@ b00 , b00000000000000000000000000000000 # 0" 1! -$end #10 1" b00000000000000000000000000000001 # diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.out b/test_regress/t/t_trace_complex_structs_fst_sc.out index 8bfcf9b29..05920c5f0 100644 --- a/test_regress/t/t_trace_complex_structs_fst_sc.out +++ b/test_regress/t/t_trace_complex_structs_fst_sc.out @@ -1,5 +1,5 @@ $date - Tue Oct 24 11:01:32 2023 + Thu Dec 14 10:35:37 2023 $end $version @@ -9,6 +9,8 @@ $timescale 1ps $end $scope module top $end +$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end +$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $scope module $unit $end $var bit 1 ! global_bit $end $upscope $end @@ -75,12 +77,10 @@ $upscope $end $scope struct v_str32x2[1] $end $var logic 32 C data [31:0] $end $upscope $end -$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $attrbegin misc 07 "" 1 $end $var int 32 D v_enumed [31:0] $end $attrbegin misc 07 "" 1 $end $var int 32 E v_enumed2 [31:0] $end -$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 F v_enumb [2:0] $end $scope struct v_enumb2_str $end @@ -102,8 +102,8 @@ $upscope $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars +#0 b00000000000000000000000000000000 N b00000000000000000000000000000000 M 0L @@ -150,7 +150,6 @@ b00 , b00000000000000000000000000000000 # 0" 1! -$end #10 1" b00000000000000000000000000000001 # diff --git a/test_regress/t/t_trace_enum.v b/test_regress/t/t_trace_enum.v new file mode 100644 index 000000000..2e4e7005a --- /dev/null +++ b/test_regress/t/t_trace_enum.v @@ -0,0 +1,27 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +typedef enum logic [1:0] {VAL_A, VAL_B, VAL_C, VAL_D} state_t; + +interface MyIntf; + state_t state; +endinterface + + +module t (clk); + input clk; + + MyIntf #() sink (); + state_t v_enumed; + + typedef enum logic [1:0] {VAL_X, VAL_Y, VAL_Z} other_state_t; + other_state_t v_other_enumed; + + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_trace_enum_fst.out b/test_regress/t/t_trace_enum_fst.out new file mode 100644 index 000000000..c13e7b815 --- /dev/null +++ b/test_regress/t/t_trace_enum_fst.out @@ -0,0 +1,35 @@ +$date + Tue Dec 19 07:15:22 2023 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$attrbegin misc 07 $unit::state_t 4 VAL_A VAL_B VAL_C VAL_D 00 01 10 11 1 $end +$attrbegin misc 07 t.other_state_t 3 VAL_X VAL_Y VAL_Z 00 01 10 2 $end +$var wire 1 ! clk $end +$scope module t $end +$var wire 1 ! clk $end +$scope interface sink $end +$attrbegin misc 07 "" 1 $end +$var logic 2 " state [1:0] $end +$upscope $end +$attrbegin misc 07 "" 1 $end +$var logic 2 # v_enumed [1:0] $end +$attrbegin misc 07 "" 2 $end +$var logic 2 $ v_other_enumed [1:0] $end +$upscope $end +$upscope $end +$enddefinitions $end +$dumpvars +#0 +b00 $ +b00 # +b00 " +0! +#10 +1! diff --git a/test_regress/t/t_trace_enum_fst.pl b/test_regress/t/t_trace_enum_fst.pl new file mode 100755 index 000000000..d59b6459d --- /dev/null +++ b/test_regress/t/t_trace_enum_fst.pl @@ -0,0 +1,34 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +top_filename("t/t_trace_enum.v"); + +compile( + verilator_flags2 => ['--cc --trace-fst --output-split-ctrace 1'], + ); + +execute( + check_finished => 1, + ); + +fst_identical($Self->trace_filename, $Self->{golden_filename}); + +# Five $attrbegin expected: +# - state_t declaration +# - t.v_enumed +# - t.sink.state +# - other_state_t declaration +# - t.v_other_enumed +file_grep_count($Self->{golden_filename}, qr/attrbegin/, 5); + +ok(1); +1; diff --git a/test_regress/t/t_trace_noflag_bad_c.cpp b/test_regress/t/t_trace_noflag_bad_c.cpp index 1fccdddd3..d46885332 100644 --- a/test_regress/t/t_trace_noflag_bad_c.cpp +++ b/test_regress/t/t_trace_noflag_bad_c.cpp @@ -9,7 +9,7 @@ #include #include -#include "Vt_trace_noflag_bad.h" +#include VM_PREFIX_INCLUDE int main(int argc, char** argv) { std::unique_ptr contextp{new VerilatedContext}; diff --git a/test_regress/t/t_trace_open_wrong_order_bad.cpp b/test_regress/t/t_trace_open_wrong_order_bad.cpp index 9fac96261..fa899b799 100644 --- a/test_regress/t/t_trace_open_wrong_order_bad.cpp +++ b/test_regress/t/t_trace_open_wrong_order_bad.cpp @@ -9,7 +9,7 @@ #include #include -#include "Vt_trace_open_wrong_order_bad.h" +#include VM_PREFIX_INCLUDE int main(int argc, char** argv) { VerilatedContext ctx; diff --git a/test_regress/t/t_tri_inout.cpp b/test_regress/t/t_tri_inout.cpp index 8ce735b75..812db4be0 100644 --- a/test_regress/t/t_tri_inout.cpp +++ b/test_regress/t/t_tri_inout.cpp @@ -4,7 +4,7 @@ // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 -#include "Vt_tri_inout.h" +#include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; diff --git a/test_regress/t/t_tri_pullup.cpp b/test_regress/t/t_tri_pullup.cpp index f900d0b06..311c28744 100644 --- a/test_regress/t/t_tri_pullup.cpp +++ b/test_regress/t/t_tri_pullup.cpp @@ -4,7 +4,7 @@ // without warranty, 2008 by Lane Brooks. // SPDX-License-Identifier: CC0-1.0 -#include "Vt_tri_pullup.h" +#include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; diff --git a/test_regress/t/t_tri_select.cpp b/test_regress/t/t_tri_select.cpp index b3fc80f98..fbea109aa 100644 --- a/test_regress/t/t_tri_select.cpp +++ b/test_regress/t/t_tri_select.cpp @@ -3,7 +3,7 @@ // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -#include "Vt_tri_select.h" +#include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; diff --git a/test_regress/t/t_unroll_delay.out b/test_regress/t/t_unroll_delay.out new file mode 100644 index 000000000..1991fe349 --- /dev/null +++ b/test_regress/t/t_unroll_delay.out @@ -0,0 +1,18 @@ + +[0] A 1 6 +[0] B 0 0 +[1] C 1 6 +[1] A 1 7 +[1] B 0 7 +[2] C 1 7 +[2] B 0 8 + +[11] A 2 6 +[11] B 2 8 +[12] C 2 6 +[12] A 2 7 +[12] B 2 7 +[13] C 2 7 +[13] B 2 8 +[22] B 3 8 +*-* All Finished *-* diff --git a/test_regress/t/t_unroll_delay.pl b/test_regress/t/t_unroll_delay.pl new file mode 100755 index 000000000..9a4002b2d --- /dev/null +++ b/test_regress/t/t_unroll_delay.pl @@ -0,0 +1,26 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['--binary --timing --trace'], + verilator_make_cmake => 0, + verilator_make_gmake => 0, + make_main => 0, + ); + +execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_unroll_delay.v b/test_regress/t/t_unroll_delay.v new file mode 100644 index 000000000..70cc6d5f0 --- /dev/null +++ b/test_regress/t/t_unroll_delay.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/); + integer i; + integer j; + + always @(i, j) $display("[%0t] B %0d %0d", $time, i, j); + + // See issue #4237 + + initial begin + for(i = 1; i < 3 ; i = i + 1) begin + $display(""); + for(j = 6; j < 8; j = j + 1) begin + $display("[%0t] A %0d %0d", $time, i, j); + #1; + $display("[%0t] C %0d %0d", $time, i, j); + end + #9; + end + #10; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_unroll_unopt_io.pl b/test_regress/t/t_unroll_unopt_io.pl new file mode 100755 index 000000000..1df6afd70 --- /dev/null +++ b/test_regress/t/t_unroll_unopt_io.pl @@ -0,0 +1,18 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['--x-assign fast'], + ); + +ok(1); +1; diff --git a/test_regress/t/t_unroll_unopt_io.v b/test_regress/t/t_unroll_unopt_io.v new file mode 100644 index 000000000..fe6390b24 --- /dev/null +++ b/test_regress/t/t_unroll_unopt_io.v @@ -0,0 +1,26 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Outputs + zeros, + // Inputs + num + ); + + parameter WIDTH = 1; + input logic [WIDTH-1:0] num; + output logic [$clog2(WIDTH+1)-1:0] zeros; + + integer i; + + always_comb begin + i = 0; + while ((i < WIDTH) & ~num[WIDTH-1-i]) i = i + 1; + zeros = i[$clog2(WIDTH+1) - 1 : 0]; + end + +endmodule diff --git a/test_regress/t/t_var_escape.out b/test_regress/t/t_var_escape.out index 48b83ad17..7517b1831 100644 --- a/test_regress/t/t_var_escape.out +++ b/test_regress/t/t_var_escape.out @@ -11,9 +11,11 @@ $timescale 1ps $end $var wire 1 # clk $end $var wire 32 ( cyc [31:0] $end $var wire 1 $ escaped_normal $end - $var wire 1 $ double__underscore $end - $var wire 1 $ 9num $end - $var wire 1 $ bra[ket]slash/dash-colon:9backslash\done $end + $var wire 1 % double__underscore $end + $var wire 1 $ underscore_at_the_end_ $end + $var wire 1 $ double__underscore_at_the_end__ $end + $var wire 1 & 9num $end + $var wire 1 ' bra[ket]slash/dash-colon:9backslash\done $end $var wire 1 $ wire $end $var wire 1 $ check_alias $end $var wire 1 $ check:alias $end diff --git a/test_regress/t/t_var_escape.v b/test_regress/t/t_var_escape.v index bc2b38ea5..910c61332 100644 --- a/test_regress/t/t_var_escape.v +++ b/test_regress/t/t_var_escape.v @@ -21,6 +21,15 @@ module t (/*AUTOARG*/ output double__underscore ; wire double__underscore = cyc[0]; + wire underscore_at_the_end_ = cyc[0]; + wire double__underscore_at_the_end__ = cyc[0]; + + // Only underscores, ignored in trace + wire _ = cyc[0]; + wire __ = cyc[0]; + wire ___ = cyc[0]; + wire ____ = cyc[0]; + // C doesn't allow leading non-alpha, so must escape output \9num ; wire \9num = cyc[0]; @@ -45,7 +54,12 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; if (escaped_normal != cyc[0]) $stop; if (\escaped_normal != cyc[0]) $stop; - if (double__underscore != cyc[0]) $stop; + if (underscore_at_the_end_ != cyc[0]) $stop; + if (double__underscore_at_the_end__ != cyc[0]) $stop; + if (_ != cyc[0]) $stop; + if (__ != cyc[0]) $stop; + if (___ != cyc[0]) $stop; + if (____ != cyc[0]) $stop; if (\9num != cyc[0]) $stop; if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop; if (\wire != cyc[0]) $stop; diff --git a/test_regress/t/t_var_overwidth_bad.cpp b/test_regress/t/t_var_overwidth_bad.cpp index 5a4158ca8..053be27da 100644 --- a/test_regress/t/t_var_overwidth_bad.cpp +++ b/test_regress/t/t_var_overwidth_bad.cpp @@ -11,7 +11,7 @@ #include "verilated.h" -#include "Vt_var_overwidth_bad.h" +#include VM_PREFIX_INCLUDE //====================================================================== diff --git a/test_regress/t/t_virtual_interface_method.pl b/test_regress/t/t_virtual_interface_method.pl new file mode 100755 index 000000000..2d5085be1 --- /dev/null +++ b/test_regress/t/t_virtual_interface_method.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + v_flags2 => ["--binary"], + verilator_make_gmake => 0, + make_main => 0, + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_virtual_interface_method.v b/test_regress/t/t_virtual_interface_method.v new file mode 100644 index 000000000..886e20e2c --- /dev/null +++ b/test_regress/t/t_virtual_interface_method.v @@ -0,0 +1,136 @@ +// Copyright 2003 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// Create stimulus and Drive the interface +class DriverStim; + protected virtual example_if v_if; + + task run(); + bit[7:0] x; + bit[7:0] y; + + v_if.reset(); + forever begin + x++; + y++; + + $display("[DriverStim] initiating calculation, x: %8b y: %8b", x, y); + v_if.initiate_calculation(x, y); + end + endtask: run + + function void bind_if(virtual example_if v_if); + this.v_if = v_if; + endfunction: bind_if +endclass: DriverStim +// Monitor returns from interface and check them +class MonitorCheck; + localparam NUM_TXNS = 10; + protected virtual example_if v_if; + + task run(); + logic[8:0] result; + int txns_received = 0; + + forever begin + v_if.wait_for_result(result); + $display( + "[MonitorCheck] (%d) result %7b carry_out %1b", + txns_received, result[7:0], result[8] + ); + if(++txns_received == NUM_TXNS) begin + $write("*-* All Finished *-*\n"); + $finish(); + end + end + endtask: run + + function void bind_if(virtual example_if v_if); + this.v_if = v_if; + endfunction: bind_if +endclass: MonitorCheck + +module example( + input logic clk, + input logic rstn, + input logic[7:0] x, + input logic[7:0] y, + output logic[8:0] z + ); + + // 8 bit full adder + always_ff @(posedge clk) + if(!rstn) z <= '0; + else z <= x + y; +endmodule: example +// interfaces with the DUT + +interface example_if(); + localparam CLK_FREQ_MHz = 400; + localparam CLK_PERIOD = 1/((CLK_FREQ_MHz * 1e6) * (1e-12)); + + logic clk; + logic rstn; + logic[7:0] x; + logic[7:0] y; + logic[8:0] z; + + initial begin: clk_gen + forever #(CLK_PERIOD/2) clk = !clk; + end: clk_gen + + task reset(); + $display("reset called"); + rstn = 0; + @(posedge clk); + $display("clock tick"); + rstn = 1; + @(posedge clk); + endtask: reset + + event calc_clkd; + task initiate_calculation( + input logic[7:0] x_in, + input logic[7:0] y_in + ); + + x = x_in; + y = y_in; + @(posedge clk); + ->calc_clkd; + endtask: initiate_calculation + + task wait_for_result(output logic[8:0] result); + @(calc_clkd); + result = z; + endtask: wait_for_result +endinterface: example_if + +module t(/*AUTOARG*/); + + example_if example_if_inst(); + + example DUT( + .clk (example_if_inst.clk), + .rstn(example_if_inst.rstn), + .x (example_if_inst.x), + .y (example_if_inst.y), + .z (example_if_inst.z) + ); + + + initial begin: main + DriverStim driverStim = new(); + MonitorCheck monitorCheck = new(); + + driverStim.bind_if(example_if_inst); + monitorCheck.bind_if(example_if_inst); + + fork + driverStim.run(); + monitorCheck.run(); + join_none + end: main +endmodule: t diff --git a/test_regress/t/t_virtual_interface_method_bad.out b/test_regress/t/t_virtual_interface_method_bad.out new file mode 100644 index 000000000..cb24e82c2 --- /dev/null +++ b/test_regress/t/t_virtual_interface_method_bad.out @@ -0,0 +1,5 @@ +%Error: t/t_virtual_interface_method_bad.v:11:10: Member reference from interface to 'x' is not referencing a valid task or function + : ... note: In instance 't' + 11 | v_if.x(); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_virtual_interface_method_bad.pl b/test_regress/t/t_virtual_interface_method_bad.pl new file mode 100755 index 000000000..85114ac5d --- /dev/null +++ b/test_regress/t/t_virtual_interface_method_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + verilator_flags2 => ["--lint-only --language 1800-2017"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_virtual_interface_method_bad.v b/test_regress/t/t_virtual_interface_method_bad.v new file mode 100644 index 000000000..972d60943 --- /dev/null +++ b/test_regress/t/t_virtual_interface_method_bad.v @@ -0,0 +1,35 @@ +// Copyright 2003 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +class ExampleClass; + localparam NUM_TXNS = 10; + protected virtual example_if v_if; + + task run(); + v_if.x(); + endtask: run + + function void bind_if(virtual example_if v_if); + this.v_if = v_if; + endfunction: bind_if +endclass: ExampleClass + +interface example_if(); + logic clk; + logic rstn; + logic[7:0] x; +endinterface: example_if + +module t(/*AUTOARG*/); + + example_if example_if_inst(); + + initial begin: main + ExampleClass exampleClass = new(); + + exampleClass.bind_if(example_if_inst); + exampleClass.run(); + end: main +endmodule: t diff --git a/test_regress/t/t_vpi_cb_iter.cpp b/test_regress/t/t_vpi_cb_iter.cpp index d7b4d932e..d98fe968c 100644 --- a/test_regress/t/t_vpi_cb_iter.cpp +++ b/test_regress/t/t_vpi_cb_iter.cpp @@ -12,7 +12,8 @@ #include "verilated.h" #include "verilated_vpi.h" -#include "Vt_vpi_cb_iter.h" +#include VM_PREFIX_INCLUDE + #include "vpi_user.h" #include diff --git a/test_regress/t/t_vpi_const_type.cpp b/test_regress/t/t_vpi_const_type.cpp new file mode 100644 index 000000000..587d2ac1d --- /dev/null +++ b/test_regress/t/t_vpi_const_type.cpp @@ -0,0 +1,200 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#ifdef IS_VPI + +#include "sv_vpi_user.h" + +#include + +#else + +#include "verilated.h" +#include "verilated_vcd_c.h" +#include "verilated_vpi.h" + +#include "Vt_vpi_const_type.h" +#include "Vt_vpi_const_type__Dpi.h" +#include "svdpi.h" + +#endif + +#include +#include +#include + +// These require the above. Comment prevents clang-format moving them +#include "TestSimulator.h" +#include "TestVpi.h" + +// __FILE__ is too long +#define FILENM "t_vpi_const_type.cpp" + +#define DEBUG \ + if (0) printf + +#define CHECK_RESULT_NZ(got) \ + if (!(got)) { \ + printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ + return __LINE__; \ + } + +#define CHECK_RESULT_Z(got) \ + if (got) { \ + printf("%%Error: %s:%d: GOT = !NULL EXP = NULL\n", FILENM, __LINE__); \ + return __LINE__; \ + } + +#define CHECK_RESULT(got, exp) \ + if ((got) != (exp)) { \ + std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ + << " EXP = " << (exp) << std::endl; \ + return __LINE__; \ + } + +#define CHECK_RESULT_CSTR(got, exp) \ + if (std::strcmp((got), (exp))) { \ + printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ + (got) ? (got) : "", (exp) ? (exp) : ""); \ + return __LINE__; \ + } + +extern "C" { +int mon_check() { +#ifdef TEST_VERBOSE + printf("-mon_check()\n"); +#endif + + TestVpiHandle intHandle = vpi_handle_by_name((PLI_BYTE8*)"t.intParam", NULL); + CHECK_RESULT_NZ(intHandle) + PLI_INT32 intConstType = vpi_get(vpiConstType, intHandle); + CHECK_RESULT(intConstType, vpiDecConst) + + TestVpiHandle realHandle = vpi_handle_by_name((PLI_BYTE8*)"t.realParam", NULL); + CHECK_RESULT_NZ(realHandle) + PLI_INT32 realConstType = vpi_get(vpiConstType, realHandle); + CHECK_RESULT(realConstType, vpiRealConst) + + TestVpiHandle strHandle = vpi_handle_by_name((PLI_BYTE8*)"t.strParam", NULL); + CHECK_RESULT_NZ(strHandle) + PLI_INT32 strConstType = vpi_get(vpiConstType, strHandle); + CHECK_RESULT(strConstType, vpiStringConst) + + TestVpiHandle sigHandle = vpi_handle_by_name((PLI_BYTE8*)"t.signal", NULL); + CHECK_RESULT_NZ(sigHandle) + PLI_INT32 sigConstType = vpi_get(vpiConstType, sigHandle); + // t.signal is not constant + CHECK_RESULT(sigConstType, vpiUndefined) + TestVpiHandle leftHandle = vpi_handle(vpiLeftRange, sigHandle); + CHECK_RESULT_NZ(leftHandle) + PLI_INT32 leftConstType = vpi_get(vpiConstType, leftHandle); + CHECK_RESULT(leftConstType, vpiDecConst) + + TestVpiHandle timeHandle = vpi_handle_by_name((PLI_BYTE8*)"t.timeParam", NULL); + CHECK_RESULT_NZ(timeHandle) + PLI_INT32 timeConstType = vpi_get(vpiConstType, timeHandle); + CHECK_RESULT(timeConstType, vpiDecConst) + + return 0; // Ok +} +} +//====================================================================== + +#ifdef IS_VPI + +static int mon_check_vpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpi_value; + + vpi_value.format = vpiIntVal; + vpi_value.value.integer = mon_check(); + vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); + + return 0; +} + +static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", + (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, + 0}; + +// cver entry +void vpi_compat_bootstrap(void) { + p_vpi_systf_data systf_data_p; + systf_data_p = &(vpi_systf_data[0]); + while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); +} + +// icarus entry +void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; + +#else + +int main(int argc, char** argv) { + const std::unique_ptr contextp{new VerilatedContext}; + + uint64_t sim_time = 1100; + contextp->debug(0); + contextp->commandArgs(argc, argv); + // We're going to be checking for these errors so don't crash out + contextp->fatalOnVpiError(0); + + { + // Construct and destroy + const std::unique_ptr topp{ + new VM_PREFIX{contextp.get(), + // Note null name - we're flattening it out + ""}}; + } + + // Test second construction + const std::unique_ptr topp{new VM_PREFIX{contextp.get(), + // Note null name - we're flattening it out + ""}}; + +#ifdef VERILATOR +#ifdef TEST_VERBOSE + contextp->scopesDump(); +#endif +#endif + +#if VM_TRACE + contextp->traceEverOn(true); + VL_PRINTF("Enabling waves...\n"); + VerilatedVcdC* tfp = new VerilatedVcdC; + topp->trace(tfp, 99); + tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); +#endif + + topp->eval(); + contextp->timeInc(10); + + while (contextp->time() < sim_time && !contextp->gotFinish()) { + contextp->timeInc(1); + topp->eval(); + VerilatedVpi::callValueCbs(); + // mon_do(); +#if VM_TRACE + if (tfp) tfp->dump(contextp->time()); +#endif + } + if (!contextp->gotFinish()) { + vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); + } + topp->final(); + +#if VM_TRACE + if (tfp) tfp->close(); +#endif + + return 0; +} + +#endif diff --git a/test_regress/t/t_vpi_const_type.pl b/test_regress/t/t_vpi_const_type.pl new file mode 100755 index 000000000..31a37c26f --- /dev/null +++ b/test_regress/t/t_vpi_const_type.pl @@ -0,0 +1,29 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +skip("Known compiler limitation") + if $Self->cxx_version =~ /\(GCC\) 4.4/; + +compile( + make_top_shell => 0, + make_main => 0, + make_pli => 1, + verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_const_type.cpp"], + ); + +execute( + use_libvpi => 1, + check_finished => 1 + ); + +ok(1); +1; diff --git a/test_regress/t/t_vpi_const_type.v b/test_regress/t/t_vpi_const_type.v new file mode 100644 index 000000000..ef76c8f35 --- /dev/null +++ b/test_regress/t/t_vpi_const_type.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import "DPI-C" context function int mon_check(); + +module t (/*AUTOARG*/ + ); /*verilator public_module*/ + + parameter int intParam /*verilator public_flat_rd*/ = 5; + parameter real realParam /*verilator public_flat_rd*/ = 2.3; + parameter time timeParam /*verilator public_flat_rd*/ = 0; + parameter string strParam /*verilator public_flat_rd*/ = "abc"; + + logic [31:0] signal /*verilator public_flat_rw*/; + + int status; + + initial begin + status = mon_check(); + if (status!=0) begin + $write("%%Error: t_vpi_const_type.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule : t diff --git a/test_regress/t/t_vpi_escape.cpp b/test_regress/t/t_vpi_escape.cpp new file mode 100644 index 000000000..043a62a5d --- /dev/null +++ b/test_regress/t/t_vpi_escape.cpp @@ -0,0 +1,402 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// Copyright 2010-2023 by Wilson Snyder and Marlon James. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#ifdef IS_VPI + +#include "sv_vpi_user.h" + +#else + +#include "verilated.h" +#include "verilated_vcd_c.h" +#include "verilated_vpi.h" + +#include "Vt_vpi_escape.h" +#include "Vt_vpi_escape__Dpi.h" +#include "svdpi.h" + +#endif + +#include + +// These require the above. Comment prevents clang-format moving them +#include "TestCheck.h" +#include "TestSimulator.h" +#include "TestVpi.h" + +int errors = 0; +unsigned int main_time = 0; + +//====================================================================== + +// We cannot replace those with VL_STRINGIFY, not available when PLI is build +#define STRINGIFY(x) STRINGIFY2(x) +#define STRINGIFY2(x) #x + +const char* _sim_top() { + if (TestSimulator::is_verilator() || TestSimulator::is_icarus()) { + return "\\t.has.dots "; + } else { + return "top.\\t.has.dots "; + } +} + +const char* _my_rooted(const char* obj) { + static std::string buf; + std::ostringstream os; + os << _sim_top(); + if (*obj) os << "." << obj; + buf = os.str(); + return buf.c_str(); +} + +#define MY_VPI_HANDLE(signal) vpi_handle_by_name(const_cast(_my_rooted(signal)), NULL); + +int _mon_check_var() { +#ifdef TEST_VERBOSE + printf("-mon_check_var()\n"); +#endif + TestVpiHandle vh1 = vpi_handle_by_name(const_cast(_sim_top()), NULL); + TEST_CHECK_NZ(vh1); + + TestVpiHandle vh2 = MY_VPI_HANDLE("\\check;alias "); + TEST_CHECK_NZ(vh2); + + // scope attributes + const char* p; + p = vpi_get_str(vpiName, vh1); + TEST_CHECK_CSTR(p, "\\t.has.dots "); + p = vpi_get_str(vpiFullName, vh1); + TEST_CHECK_CSTR(p, _sim_top()); + p = vpi_get_str(vpiType, vh1); + TEST_CHECK_CSTR(p, "vpiModule"); + + TestVpiHandle vh3 = vpi_handle_by_name(const_cast("escaped_normal"), vh1); + TEST_CHECK_NZ(vh3); + + // onebit attributes + PLI_INT32 d; + d = vpi_get(vpiType, vh3); + if (TestSimulator::is_verilator()) { + TEST_CHECK_EQ(d, vpiReg); + } else { + TEST_CHECK_EQ(d, vpiNet); + } + if (TestSimulator::has_get_scalar()) { + d = vpi_get(vpiVector, vh3); + TEST_CHECK_EQ(d, 0); + } + + p = vpi_get_str(vpiName, vh3); + TEST_CHECK_CSTR(p, "escaped_normal"); + p = vpi_get_str(vpiFullName, vh3); + // Toplevel port returns TOP.xxxxx + TEST_CHECK_CSTR(p, "TOP.escaped_normal"); + p = vpi_get_str(vpiType, vh3); + if (TestSimulator::is_verilator()) { + TEST_CHECK_CSTR(p, "vpiReg"); + } else { + TEST_CHECK_CSTR(p, "vpiNet"); + } + + TestVpiHandle vh4 = MY_VPI_HANDLE("\\x.y "); + TEST_CHECK_NZ(vh4); + + // Test that the toplevel TOP.xxxxx search is skipped + // when the path to the scope has more than one level. + TestVpiHandle vh5 = MY_VPI_HANDLE("\\mod.with_dot .\\b.c "); + TEST_CHECK_NZ(vh5); + p = vpi_get_str(vpiFullName, vh5); + TEST_CHECK_CSTR(p, "\\t.has.dots .\\mod.with_dot .\\b.c "); + + return errors; +} + +int _mon_check_iter() { +#ifdef TEST_VERBOSE + printf("-mon_check_iter()\n"); +#endif + const char* p; + + TestVpiHandle vh2 = MY_VPI_HANDLE("\\mod.with_dot "); + TEST_CHECK_NZ(vh2); + p = vpi_get_str(vpiName, vh2); + TEST_CHECK_CSTR(p, "\\mod.with_dot "); + if (TestSimulator::is_verilator()) { + p = vpi_get_str(vpiDefName, vh2); + TEST_CHECK_CSTR(p, ""); // Unsupported + } + + TestVpiHandle vh10 = vpi_iterate(vpiReg, vh2); + TEST_CHECK_NZ(vh10); + TEST_CHECK_EQ(vpi_get(vpiType, vh10), vpiIterator); + + { + TestVpiHandle vh11 = vpi_scan(vh10); + TEST_CHECK_NZ(vh11); + p = vpi_get_str(vpiFullName, vh11); +#ifdef TEST_VERBOSE + printf(" scanned %s\n", p); +#endif + TEST_CHECK_CSTR(p, _my_rooted("\\mod.with_dot .\\b.c ")); + } + { + TestVpiHandle vh12 = vpi_scan(vh10); + TEST_CHECK_NZ(vh12); + p = vpi_get_str(vpiFullName, vh12); +#ifdef TEST_VERBOSE + printf(" scanned %s\n", p); +#endif + TEST_CHECK_CSTR(p, _my_rooted("\\mod.with_dot .cyc")); + } + { + TestVpiHandle vh13 = vpi_scan(vh10); + TEST_CHECK_NZ(vh13); + p = vpi_get_str(vpiFullName, vh13); +#ifdef TEST_VERBOSE + printf(" scanned %s\n", p); +#endif + TEST_CHECK_CSTR(p, _my_rooted("\\mod.with_dot .subsig1")); + } + { + TestVpiHandle vh14 = vpi_scan(vh10); + TEST_CHECK_NZ(vh14); + p = vpi_get_str(vpiFullName, vh14); +#ifdef TEST_VERBOSE + printf(" scanned %s\n", p); +#endif + TEST_CHECK_CSTR(p, _my_rooted("\\mod.with_dot .subsig2")); + } + { + TestVpiHandle vh15 = vpi_scan(vh10); + vh10.freed(); // IEEE 37.2.2 vpi_scan at end does a vpi_release_handle + TEST_CHECK_EQ(vh15, 0); + } + return errors; +} + +int _mon_check_ports() { +#ifdef TEST_VERBOSE + printf("-mon_check_ports()\n"); +#endif + // test writing to input port + TestVpiHandle vh1 = MY_VPI_HANDLE("a"); + TEST_CHECK_NZ(vh1); + + PLI_INT32 d; + d = vpi_get(vpiType, vh1); + if (TestSimulator::is_verilator()) { + TEST_CHECK_EQ(d, vpiReg); + } else { + TEST_CHECK_EQ(d, vpiNet); + } + + const char* portFullName; + if (TestSimulator::is_verilator()) { + portFullName = "TOP.a"; + } else { + portFullName = "t.a"; + } + + const char* name = vpi_get_str(vpiFullName, vh1); + TEST_CHECK_EQ(strcmp(name, portFullName), 0); + std::string handleName1 = name; + + s_vpi_value v; + v.format = vpiIntVal; + vpi_get_value(vh1, &v); + TEST_CHECK_EQ(v.value.integer, 0); + + s_vpi_time t; + t.type = vpiSimTime; + t.high = 0; + t.low = 0; + v.value.integer = 2; + vpi_put_value(vh1, &v, &t, vpiNoDelay); + v.value.integer = 100; + vpi_get_value(vh1, &v); + TEST_CHECK_EQ(v.value.integer, 2); + + // get handle of toplevel module + TestVpiHandle vht = MY_VPI_HANDLE(""); + TEST_CHECK_NZ(vht); + + d = vpi_get(vpiType, vht); + TEST_CHECK_EQ(d, vpiModule); + + TestVpiHandle vhi = vpi_iterate(vpiReg, vht); + TEST_CHECK_NZ(vhi); + + TestVpiHandle vh11; + std::string handleName2; + while ((vh11 = vpi_scan(vhi))) { + const char* fn = vpi_get_str(vpiFullName, vh11); +#ifdef TEST_VERBOSE + printf(" scanned %s\n", fn); +#endif + if (0 == strcmp(fn, portFullName)) { + handleName2 = fn; + break; + } + } + TEST_CHECK_NZ(vh11); // If get zero we never found the variable + vhi.release(); + TEST_CHECK_EQ(vpi_get(vpiType, vh11), vpiReg); + + TEST_CHECK_EQ(handleName1, handleName2); + + TestVpiHandle vh2 = MY_VPI_HANDLE("\\b.c "); + TEST_CHECK_NZ(vh2); + + if (TestSimulator::is_verilator()) { + portFullName = "TOP.\\b.c "; + } else { + portFullName = "t.\\b.c "; + } + + name = vpi_get_str(vpiFullName, vh2); + TEST_CHECK_EQ(strcmp(name, portFullName), 0); + handleName1 = name; + + v.format = vpiIntVal; + vpi_get_value(vh2, &v); + TEST_CHECK_EQ(v.value.integer, 0); + + t.type = vpiSimTime; + t.high = 0; + t.low = 0; + v.value.integer = 1; + vpi_put_value(vh2, &v, &t, vpiNoDelay); + v.value.integer = 0; + vpi_get_value(vh2, &v); + TEST_CHECK_EQ(v.value.integer, 1); + + vhi = vpi_iterate(vpiReg, vht); + TEST_CHECK_NZ(vhi); + + while ((vh11 = vpi_scan(vhi))) { + const char* fn = vpi_get_str(vpiFullName, vh11); +#ifdef TEST_VERBOSE + printf(" scanned %s\n", fn); +#endif + if (0 == strcmp(fn, portFullName)) { + handleName2 = fn; + break; + } + } + TEST_CHECK_NZ(vh11); // If get zero we never found the variable + vhi.release(); + TEST_CHECK_EQ(vpi_get(vpiType, vh11), vpiReg); + + TEST_CHECK_EQ(handleName1, handleName2); + + return errors; +} + +extern "C" int mon_check() { + // Callback from initial block in monitor +#ifdef TEST_VERBOSE + printf("-mon_check()\n"); +#endif + + if (int status = _mon_check_var()) return status; + if (int status = _mon_check_iter()) return status; + if (int status = _mon_check_ports()) return status; +#ifndef IS_VPI + VerilatedVpi::selfTest(); +#endif + return 0; // Ok +} + +//====================================================================== + +#ifdef IS_VPI + +static int mon_check_vpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpi_value; + + vpi_value.format = vpiIntVal; + vpi_value.value.integer = mon_check(); + vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); + + return 0; +} + +static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", + (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, + 0}; + +// cver entry +void vpi_compat_bootstrap(void) { + p_vpi_systf_data systf_data_p; + systf_data_p = &(vpi_systf_data[0]); + while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); +} + +// icarus entry +void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; + +#else + +double sc_time_stamp() { return main_time; } +int main(int argc, char** argv) { + const std::unique_ptr contextp{new VerilatedContext}; + + uint64_t sim_time = 1100; + contextp->debug(0); + contextp->commandArgs(argc, argv); + + const std::unique_ptr topp{new VM_PREFIX{contextp.get(), + // Note null name - we're flattening it out + ""}}; + +#ifdef VERILATOR +#ifdef TEST_VERBOSE + contextp->scopesDump(); +#endif +#endif + +#if VM_TRACE + contextp->traceEverOn(true); + VL_PRINTF("Enabling waves...\n"); + VerilatedVcdC* tfp = new VerilatedVcdC; + topp->trace(tfp, 99); + tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); +#endif + + topp->eval(); + topp->clk = 0; + main_time += 10; + + while (vl_time_stamp64() < sim_time && !contextp->gotFinish()) { + main_time += 1; + topp->eval(); + VerilatedVpi::callValueCbs(); + topp->clk = !topp->clk; + // mon_do(); +#if VM_TRACE + if (tfp) tfp->dump(main_time); +#endif + } + if (!contextp->gotFinish()) { + vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); + } + topp->final(); + +#if VM_TRACE + if (tfp) tfp->close(); +#endif + + return 0; +} + +#endif diff --git a/test_regress/t/t_vpi_escape.pl b/test_regress/t/t_vpi_escape.pl new file mode 100755 index 000000000..111934bb1 --- /dev/null +++ b/test_regress/t/t_vpi_escape.pl @@ -0,0 +1,32 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +pli_filename("t_vpi_escape.cpp"); +compile( + make_top_shell => 0, + make_main => 0, + make_pli => 1, + sim_time => 100, + iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES"], + v_flags2 => ["+define+USE_VPI_NOT_DPI"], + verilator_flags2 => ["--exe --vpi --no-l2name --public-flat-rw $Self->{t_dir}/$Self->{name}.cpp"], + ); + +execute( + # run_env => "VPI_TRACE=" . Cwd::getcwd() . "/$Self->{obj_dir}/$Self->{name}_vpi.log", + # run_env => "VPI_TRACE=/tmp/$Self->{name}_vpi.log", + use_libvpi => 1, + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_vpi_escape.v b/test_regress/t/t_vpi_escape.v new file mode 100644 index 000000000..b575dc199 --- /dev/null +++ b/test_regress/t/t_vpi_escape.v @@ -0,0 +1,118 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010-2023 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +`ifdef USE_VPI_NOT_DPI +//We call it via $c so we can verify DPI isn't required - see bug572 +`else +import "DPI-C" context function int mon_check(); +`endif + +module \t.has.dots (/*AUTOARG*/ + // Outputs + \escaped_normal , double__underscore, \9num , \bra[ket]slash/dash-colon:9backslash\done , \x.y , + // Inputs + clk, \b.c , a + ); + +`ifdef VERILATOR +`systemc_header +extern "C" int mon_check(); +`verilog +`endif + + input clk; + input [7:0] a; + input \b.c ; + + integer cyc; initial cyc=1; + + output \escaped_normal ; + wire \escaped_normal = cyc[0]; + + output double__underscore ; + wire double__underscore = cyc[0]; + + // C doesn't allow leading non-alpha, so must escape + output \9num ; + wire \9num = cyc[0]; + + output \bra[ket]slash/dash-colon:9backslash\done ; + wire \bra[ket]slash/dash-colon:9backslash\done = cyc[0]; + + output \x.y ; + wire \x.y = cyc[0]; + + wire \wire = cyc[0]; + + wire \check_alias = cyc[0]; + wire \check:alias = cyc[0]; + wire \check;alias = !cyc[0]; + + // These are *different entities*, bug83 + wire [31:0] \a0.cyc = ~a0.cyc; + wire [31:0] \other.cyc = ~a0.cyc; + + integer status; + + sub a0 (.cyc(cyc)); + + sub \mod.with_dot (.cyc(cyc)); + + initial begin + +`ifdef VERILATOR + status = $c32("mon_check()"); +`endif +`ifdef IVERILOG + status = $mon_check(); +`endif +`ifndef USE_VPI_NOT_DPI + status = mon_check(); +`endif + if (status != 0) begin + $write("%%Error: C Test failed with %0d error(s)\n", status); + $stop; + end + $write("%%Info: Checking results\n"); + end + + always @ (posedge clk) begin + cyc <= cyc + 1; + if (escaped_normal != cyc[0]) $stop; + if (\escaped_normal != cyc[0]) $stop; + if (double__underscore != cyc[0]) $stop; + if (\9num != cyc[0]) $stop; + if (\bra[ket]slash/dash-colon:9backslash\done != cyc[0]) $stop; + if (\x.y != cyc[0]) $stop; + if (\wire != cyc[0]) $stop; + if (\check_alias != cyc[0]) $stop; + if (\check:alias != cyc[0]) $stop; + if (\check;alias != !cyc[0]) $stop; + if (\a0.cyc != ~cyc) $stop; + if (\other.cyc != ~cyc) $stop; + if (cyc==10) begin + if (a != 2) $stop; + if (\b.c != 1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module sub ( + input [31:0] cyc + ); + reg \b.c ; + reg subsig1; + reg subsig2; +`ifdef IVERILOG + // stop icarus optimizing signals away + wire redundant = subsig1 | subsig2 | \b.c ; +`endif +endmodule diff --git a/test_regress/t/t_vpi_onetime_cbs.cpp b/test_regress/t/t_vpi_onetime_cbs.cpp index c7632f8a9..dfd0106ed 100644 --- a/test_regress/t/t_vpi_onetime_cbs.cpp +++ b/test_regress/t/t_vpi_onetime_cbs.cpp @@ -23,7 +23,7 @@ #include "verilated.h" #include "verilated_vpi.h" -#include "Vt_vpi_onetime_cbs.h" +#include VM_PREFIX_INCLUDE #endif diff --git a/test_regress/t/t_vpi_package.cpp b/test_regress/t/t_vpi_package.cpp new file mode 100644 index 000000000..b171b3fbe --- /dev/null +++ b/test_regress/t/t_vpi_package.cpp @@ -0,0 +1,253 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// Copyright 2010-2011 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#ifdef IS_VPI + +#include "sv_vpi_user.h" + +#include + +#else + +#include "verilated.h" +#include "verilated_vcd_c.h" +#include "verilated_vpi.h" + +#include "Vt_vpi_package.h" +#include "Vt_vpi_package__Dpi.h" +#include "svdpi.h" + +#endif + +#include +#include +#include + +// These require the above. Comment prevents clang-format moving them +#include "TestSimulator.h" +#include "TestVpi.h" + +// __FILE__ is too long +#define FILENM "t_vpi_package.cpp" + +#define DEBUG \ + if (0) printf + +#define CHECK_RESULT_NZ(got) \ + if (!(got)) { \ + printf("%%Error: %s:%d: GOT = NULL EXP = !NULL\n", FILENM, __LINE__); \ + return __LINE__; \ + } + +#define CHECK_RESULT_Z(got) \ + if (got) { \ + printf("%%Error: %s:%d: GOT = !NULL EXP = NULL\n", FILENM, __LINE__); \ + return __LINE__; \ + } + +#define CHECK_RESULT(got, exp) \ + if ((got) != (exp)) { \ + std::cout << std::dec << "%Error: " << FILENM << ":" << __LINE__ << ": GOT = " << (got) \ + << " EXP = " << (exp) << std::endl; \ + return __LINE__; \ + } + +#define CHECK_RESULT_CSTR(got, exp) \ + if (std::strcmp((got), (exp))) { \ + printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ + (got) ? (got) : "", (exp) ? (exp) : ""); \ + return __LINE__; \ + } + +extern "C" { +int count_params(TestVpiHandle& handle, int expectedParams) { + TestVpiHandle it = vpi_iterate(vpiParameter, handle); + CHECK_RESULT_NZ(it) + + int params = 0; + while (true) { + TestVpiHandle handle = vpi_scan(it); + if (handle == NULL) break; + params++; + } + it.freed(); + CHECK_RESULT(params, expectedParams); + + return 0; +} + +int check_handle(char* name, vpiHandle scopeHandle) { + const TestVpiHandle handle = vpi_handle_by_name(name, scopeHandle); + CHECK_RESULT_NZ(handle) + return 0; +} + +int mon_check() { +#ifdef TEST_VERBOSE + printf("-mon_check()\n"); +#endif + + TestVpiHandle it = vpi_iterate(vpiModule, NULL); + CHECK_RESULT_NZ(it) + + bool found_t = false; + while (true) { + TestVpiHandle handle = vpi_scan(it); + if (handle == NULL) break; + CHECK_RESULT_CSTR("t", vpi_get_str(vpiName, handle)) + CHECK_RESULT_Z(found_t) + found_t = true; + } + it.freed(); + CHECK_RESULT_NZ(found_t); + + it = vpi_iterate(vpiInstance, NULL); + CHECK_RESULT_NZ(it) + + TestVpiHandle pkgHandle = NULL; + TestVpiHandle tHandle = NULL; + TestVpiHandle unitHandle = NULL; + while (true) { + TestVpiHandle handle = vpi_scan(it); + if (handle == NULL) break; + const char* name = vpi_get_str(vpiName, handle); + const char* fullname = vpi_get_str(vpiFullName, handle); + if (!strcmp("t", name)) { + CHECK_RESULT_CSTR("t", fullname) + CHECK_RESULT_Z(tHandle) + tHandle = handle; + handle.freed(); + } else if (!strcmp("somepackage", name)) { + CHECK_RESULT_CSTR("somepackage::", fullname) + CHECK_RESULT_Z(pkgHandle) + pkgHandle = handle; + handle.freed(); + } else if (!strcmp("$unit", name)) { + CHECK_RESULT_CSTR("$unit::", fullname) + CHECK_RESULT_Z(unitHandle) + unitHandle = handle; + handle.freed(); + } else { + CHECK_RESULT_NZ(0) + } + } + it.freed(); + CHECK_RESULT_NZ(pkgHandle) + CHECK_RESULT_NZ(tHandle) + CHECK_RESULT_NZ(unitHandle) + + CHECK_RESULT_Z(count_params(unitHandle, 1)); + CHECK_RESULT_Z(count_params(pkgHandle, 2)); + CHECK_RESULT_Z(count_params(tHandle, 3)); + + CHECK_RESULT_Z(check_handle(const_cast("someOtherInt"), tHandle)) + CHECK_RESULT_Z(check_handle(const_cast("t.someOtherInt"), NULL)) + CHECK_RESULT_Z(check_handle(const_cast("someInt"), pkgHandle)) + CHECK_RESULT_Z(check_handle(const_cast("somepackage::someInt"), NULL)) + CHECK_RESULT_Z(check_handle(const_cast("dollarUnitInt"), unitHandle)) + CHECK_RESULT_Z(check_handle(const_cast("$unit::dollarUnitInt"), NULL)) + CHECK_RESULT_Z(check_handle(const_cast("somepackage"), NULL)) + + return 0; // Ok +} +} +//====================================================================== + +#ifdef IS_VPI + +static int mon_check_vpi() { + TestVpiHandle href = vpi_handle(vpiSysTfCall, 0); + s_vpi_value vpi_value; + + vpi_value.format = vpiIntVal; + vpi_value.value.integer = mon_check(); + vpi_put_value(href, &vpi_value, NULL, vpiNoDelay); + + return 0; +} + +static s_vpi_systf_data vpi_systf_data[] = {{vpiSysFunc, vpiIntFunc, (PLI_BYTE8*)"$mon_check", + (PLI_INT32(*)(PLI_BYTE8*))mon_check_vpi, 0, 0, 0}, + 0}; + +// cver entry +void vpi_compat_bootstrap(void) { + p_vpi_systf_data systf_data_p; + systf_data_p = &(vpi_systf_data[0]); + while (systf_data_p->type != 0) vpi_register_systf(systf_data_p++); +} + +// icarus entry +void (*vlog_startup_routines[])() = {vpi_compat_bootstrap, 0}; + +#else + +int main(int argc, char** argv) { + const std::unique_ptr contextp{new VerilatedContext}; + + uint64_t sim_time = 1100; + contextp->debug(0); + contextp->commandArgs(argc, argv); + // We're going to be checking for these errors so don't crash out + contextp->fatalOnVpiError(0); + + { + // Construct and destroy + const std::unique_ptr topp{ + new VM_PREFIX{contextp.get(), + // Note null name - we're flattening it out + ""}}; + } + + // Test second construction + const std::unique_ptr topp{new VM_PREFIX{contextp.get(), + // Note null name - we're flattening it out + ""}}; + +#ifdef VERILATOR +#ifdef TEST_VERBOSE + contextp->scopesDump(); +#endif +#endif + +#if VM_TRACE + contextp->traceEverOn(true); + VL_PRINTF("Enabling waves...\n"); + VerilatedVcdC* tfp = new VerilatedVcdC; + topp->trace(tfp, 99); + tfp->open(STRINGIFY(TEST_OBJ_DIR) "/simx.vcd"); +#endif + + topp->eval(); + contextp->timeInc(10); + + while (contextp->time() < sim_time && !contextp->gotFinish()) { + contextp->timeInc(1); + topp->eval(); + VerilatedVpi::callValueCbs(); + // mon_do(); +#if VM_TRACE + if (tfp) tfp->dump(contextp->time()); +#endif + } + if (!contextp->gotFinish()) { + vl_fatal(FILENM, __LINE__, "main", "%Error: Timeout; never got a $finish"); + } + topp->final(); + +#if VM_TRACE + if (tfp) tfp->close(); +#endif + + return 0; +} + +#endif diff --git a/test_regress/t/t_vpi_package.pl b/test_regress/t/t_vpi_package.pl new file mode 100755 index 000000000..4cb6a2780 --- /dev/null +++ b/test_regress/t/t_vpi_package.pl @@ -0,0 +1,29 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +skip("Known compiler limitation") + if $Self->cxx_version =~ /\(GCC\) 4.4/; + +compile( + make_top_shell => 0, + make_main => 0, + make_pli => 1, + verilator_flags2 => ["--exe --vpi --no-l2name $Self->{t_dir}/t_vpi_package.cpp"], + ); + +execute( + use_libvpi => 1, + check_finished => 1 + ); + +ok(1); +1; diff --git a/test_regress/t/t_vpi_package.v b/test_regress/t/t_vpi_package.v new file mode 100644 index 000000000..9f9ca4161 --- /dev/null +++ b/test_regress/t/t_vpi_package.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import "DPI-C" context function int mon_check(); + +parameter int dollarUnitInt /*verilator public_flat_rd*/ = 3; + +package somepackage; + parameter int someInt /*verilator public_flat_rd*/ = 5; + parameter int anotherInt /*verilator public_flat_rd*/ = 6; +endpackage + +module t (/*AUTOARG*/ + ); /*verilator public_module*/ + + parameter int someOtherInt /* verilator public_flat_rd*/ = 7; + parameter int yetAnotherInt /* verilator public_flat_rd*/ = 9; + parameter int stillAnotherInt /* verilator public_flat_rd*/ = 17; + + integer status; + + initial begin + status = mon_check(); + if (status!=0) begin + $write("%%Error: t_vpi_package.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule : t diff --git a/test_regress/t/t_vpi_repetitive_cbs.cpp b/test_regress/t/t_vpi_repetitive_cbs.cpp index 84a82fa2c..aa4c0c204 100644 --- a/test_regress/t/t_vpi_repetitive_cbs.cpp +++ b/test_regress/t/t_vpi_repetitive_cbs.cpp @@ -20,7 +20,7 @@ #include "verilated.h" #include "verilated_vpi.h" -#include "Vt_vpi_repetitive_cbs.h" +#include VM_PREFIX_INCLUDE #endif #include diff --git a/test_regress/t/t_vpi_sc.cpp b/test_regress/t/t_vpi_sc.cpp index 759d6075b..71f45e2aa 100644 --- a/test_regress/t/t_vpi_sc.cpp +++ b/test_regress/t/t_vpi_sc.cpp @@ -3,7 +3,7 @@ // any use, without warranty, 2020 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -#include "Vt_vpi_sc.h" +#include VM_PREFIX_INCLUDE VM_PREFIX* tb = nullptr; diff --git a/test_regress/t/t_vpi_var.cpp b/test_regress/t/t_vpi_var.cpp index f7db91da2..465bf0891 100644 --- a/test_regress/t/t_vpi_var.cpp +++ b/test_regress/t/t_vpi_var.cpp @@ -22,6 +22,9 @@ #ifdef T_VPI_VAR2 #include "Vt_vpi_var2.h" #include "Vt_vpi_var2__Dpi.h" +#elif defined(T_VPI_VAR3) +#include "Vt_vpi_var3.h" +#include "Vt_vpi_var3__Dpi.h" #else #include "Vt_vpi_var.h" #include "Vt_vpi_var__Dpi.h" @@ -440,6 +443,79 @@ int _mon_check_varlist() { return 0; } +int _mon_check_ports() { +#ifdef TEST_VERBOSE + printf("-mon_check_ports()\n"); +#endif + // test writing to input port + TestVpiHandle vh1 = VPI_HANDLE("a"); + TEST_CHECK_NZ(vh1); + + PLI_INT32 d; + d = vpi_get(vpiType, vh1); + if (TestSimulator::is_verilator()) { + TEST_CHECK_EQ(d, vpiReg); + } else { + TEST_CHECK_EQ(d, vpiNet); + } + + const char* portFullName; + if (TestSimulator::is_verilator()) { + portFullName = "TOP.a"; + } else { + portFullName = "t.a"; + } + + const char* name = vpi_get_str(vpiFullName, vh1); + TEST_CHECK_EQ(strcmp(name, portFullName), 0); + std::string handleName1 = name; + + s_vpi_value v; + v.format = vpiIntVal; + vpi_get_value(vh1, &v); + TEST_CHECK_EQ(v.value.integer, 0); + + s_vpi_time t; + t.type = vpiSimTime; + t.high = 0; + t.low = 0; + v.value.integer = 2; + vpi_put_value(vh1, &v, &t, vpiNoDelay); + v.value.integer = 100; + vpi_get_value(vh1, &v); + TEST_CHECK_EQ(v.value.integer, 2); + + // get handle of toplevel module + TestVpiHandle vht = VPI_HANDLE(""); + TEST_CHECK_NZ(vht); + + d = vpi_get(vpiType, vht); + TEST_CHECK_EQ(d, vpiModule); + + TestVpiHandle vhi = vpi_iterate(vpiReg, vht); + TEST_CHECK_NZ(vhi); + + TestVpiHandle vh11; + std::string handleName2; + while ((vh11 = vpi_scan(vhi))) { + const char* fn = vpi_get_str(vpiFullName, vh11); +#ifdef TEST_VERBOSE + printf(" scanned %s\n", fn); +#endif + if (0 == strcmp(fn, portFullName)) { + handleName2 = fn; + break; + } + } + TEST_CHECK_NZ(vh11); // If get zero we never found the variable + vhi.release(); + TEST_CHECK_EQ(vpi_get(vpiType, vh11), vpiReg); + + TEST_CHECK_EQ(handleName1, handleName2); + + return errors; +} + int _mon_check_getput() { TestVpiHandle vh2 = VPI_HANDLE("onebit"); CHECK_RESULT_NZ(vh2); @@ -792,6 +868,10 @@ extern "C" int mon_check() { if (int status = _mon_check_var()) return status; if (int status = _mon_check_varlist()) return status; if (int status = _mon_check_var_long_name()) return status; +// Ports are not public_flat_rw in t_vpi_var +#if defined(T_VPI_VAR2) || defined(T_VPI_VAR3) + if (int status = _mon_check_ports()) return status; +#endif if (int status = _mon_check_getput()) return status; if (int status = _mon_check_getput_iter()) return status; if (int status = _mon_check_quad()) return status; diff --git a/test_regress/t/t_vpi_var.v b/test_regress/t/t_vpi_var.v index 495abb1f5..e25f0aebf 100644 --- a/test_regress/t/t_vpi_var.v +++ b/test_regress/t/t_vpi_var.v @@ -13,8 +13,10 @@ import "DPI-C" context function int mon_check(); `endif module t (/*AUTOARG*/ + // Outputs + x, // Inputs - clk + clk, a ); `ifdef VERILATOR @@ -25,6 +27,9 @@ extern "C" int mon_check(); input clk; + input [7:0] a; + output reg [7:0] x; + reg onebit /*verilator public_flat_rw @(posedge clk) */; reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */; reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */; diff --git a/test_regress/t/t_vpi_var2.v b/test_regress/t/t_vpi_var2.v index 6726f7a9b..34e4c9cc5 100644 --- a/test_regress/t/t_vpi_var2.v +++ b/test_regress/t/t_vpi_var2.v @@ -23,8 +23,10 @@ module t /* verilator public_off */ ) (/*AUTOARG*/ + // Outputs + x, // Inputs - clk + clk, a ); `ifdef VERILATOR @@ -34,6 +36,10 @@ extern "C" int mon_check(); `endif input clk; + + input [7:0] a /* verilator public_flat_rw */; + output reg [7:0] x /* verilator public_flat_rw */; + /*verilator public_flat_rw_on @(posedge clk)*/ reg onebit; reg [2:1] twoone; diff --git a/test_regress/t/t_vpi_var3.pl b/test_regress/t/t_vpi_var3.pl new file mode 100755 index 000000000..3ffa3323e --- /dev/null +++ b/test_regress/t/t_vpi_var3.pl @@ -0,0 +1,31 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +pli_filename("t_vpi_var.cpp"); +compile( + make_top_shell => 0, + make_main => 0, + make_pli => 1, + sim_time => 2100, + iv_flags2 => ["-g2005-sv -D USE_VPI_NOT_DPI -DWAVES -DT_VPI_VAR3"], + v_flags2 => ["+define+USE_VPI_NOT_DPI"], + verilator_flags2 => ["--exe --vpi --no-l2name --public-flat-rw $Self->{t_dir}/t_vpi_var.cpp"], + ); + +execute( + use_libvpi => 1, + check_finished => 1, + all_run_flags => ['+PLUS +INT=1234 +STRSTR'] + ); + +ok(1); +1; diff --git a/test_regress/t/t_vpi_var3.v b/test_regress/t/t_vpi_var3.v new file mode 100644 index 000000000..4071d0bfe --- /dev/null +++ b/test_regress/t/t_vpi_var3.v @@ -0,0 +1,155 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2010 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +`ifdef USE_VPI_NOT_DPI +//We call it via $c so we can verify DPI isn't required - see bug572 +`else +import "DPI-C" context function int mon_check(); +`endif + +module t (/*AUTOARG*/ + // Outputs + x, + // Inputs + clk, a + ); + +`ifdef VERILATOR +`systemc_header +extern "C" int mon_check(); +`verilog +`endif + + input clk; + + input [7:0] a; + output reg [7:0] x; + + reg onebit; + reg [2:1] twoone; + reg [2:1] fourthreetwoone[4:3]; + reg LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND; + + // verilator lint_off ASCRANGE + reg [0:61] quads[2:3]; + // verilator lint_on ASCRANGE + + reg [31:0] count; + reg [31:0] half_count; + + reg [7:0] text_byte; + reg [15:0] text_half; + reg [31:0] text_word; + reg [63:0] text_long; + reg [511:0] text; + + integer status; + + real real1; + string str1; + + sub sub(); + + // Test loop + initial begin + count = 0; + onebit = 1'b0; + fourthreetwoone[3] = 0; // stop icarus optimizing away + text_byte = "B"; + text_half = "Hf"; + text_word = "Word"; + text_long = "Long64b"; + text = "Verilog Test module"; + + real1 = 1.0; + str1 = "hello"; + +`ifdef VERILATOR + status = $c32("mon_check()"); +`endif +`ifdef IVERILOG + status = $mon_check(); +`endif +`ifndef USE_VPI_NOT_DPI + status = mon_check(); +`endif + if (status!=0) begin + $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $stop; + end + $write("%%Info: Checking results\n"); + if (onebit != 1'b1) $stop; + if (quads[2] != 62'h12819213_abd31a1c) $stop; + if (quads[3] != 62'h1c77bb9b_3784ea09) $stop; + if (text_byte != "A") $stop; + if (text_half != "T2") $stop; + if (text_word != "Tree") $stop; + if (text_long != "44Four44") $stop; + if (text != "lorem ipsum") $stop; + if (str1 != "something a lot longer than hello") $stop; + if (real1 > 123456.7895 || real1 < 123456.7885 ) $stop; + end + + always @(posedge clk) begin + count <= count + 2; + if (count[1]) + half_count <= half_count + 2; + + if (count == 1000) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + genvar i; + generate + for (i=1; i<=6; i=i+1) begin : arr + arr #(.LENGTH(i)) arr(); + end + endgenerate + + genvar k; + generate + for (k=1; k<=6; k=k+1) begin : subs + sub subsub(); + end + endgenerate + +endmodule : t + +module sub; + reg subsig1; + reg subsig2; +`ifdef IVERILOG + // stop icarus optimizing signals away + wire redundant = subsig1 | subsig2; +`endif +endmodule : sub + +module arr; + + parameter LENGTH = 1; + + reg [LENGTH-1:0] sig; + reg [LENGTH-1:0] rfr; + + reg check; + reg verbose; + + initial begin + sig = {LENGTH{1'b0}}; + rfr = {LENGTH{1'b0}}; + end + + always @(posedge check) begin + if (verbose) $display("%m : %x %x", sig, rfr); + if (check && sig != rfr) $stop; + check <= 0; + end + +endmodule : arr diff --git a/test_regress/t/t_vthread.pl b/test_regress/t/t_vthread.pl index 5a360513a..f3050d635 100755 --- a/test_regress/t/t_vthread.pl +++ b/test_regress/t/t_vthread.pl @@ -11,6 +11,8 @@ use IO::File; scenarios(vlt => 1); +$Self->{sanitize} = 0; # GCC takes too long otherwise + sub gen { my $filename = shift; my $n = shift; diff --git a/test_regress/t/t_wait_const.pl b/test_regress/t/t_wait_const.pl new file mode 100755 index 000000000..b2d31c26d --- /dev/null +++ b/test_regress/t/t_wait_const.pl @@ -0,0 +1,25 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2023 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +compile( + verilator_flags2 => ["--binary"], + verilator_make_cmake => 0, + verilator_make_gmake => 0, + make_main => 0, + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_wait_const.v b/test_regress/t/t_wait_const.v new file mode 100644 index 000000000..69e5de16e --- /dev/null +++ b/test_regress/t/t_wait_const.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2023 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/); + + initial begin + // This test is separate from t_wait.v because we needed a process with + // just one wait of a non-zero to see a bug where GCC gave "return value + // not used" + // verilator lint_off WAITCONST + wait (1); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_xml_flat.out b/test_regress/t/t_xml_flat.out index e17361489..454eb60d2 100644 --- a/test_regress/t/t_xml_flat.out +++ b/test_regress/t/t_xml_flat.out @@ -64,15 +64,15 @@ - + - + - + @@ -87,15 +87,15 @@ - + - + - + diff --git a/test_regress/t/t_xml_flat_no_inline_mod.out b/test_regress/t/t_xml_flat_no_inline_mod.out index d39485a05..da52f5e15 100644 --- a/test_regress/t/t_xml_flat_no_inline_mod.out +++ b/test_regress/t/t_xml_flat_no_inline_mod.out @@ -28,7 +28,7 @@ - + diff --git a/test_regress/t/t_xml_flat_pub_mod.out b/test_regress/t/t_xml_flat_pub_mod.out index 6257a743a..55f3600d4 100644 --- a/test_regress/t/t_xml_flat_pub_mod.out +++ b/test_regress/t/t_xml_flat_pub_mod.out @@ -28,7 +28,7 @@ - + diff --git a/verilator-config-version.cmake.in b/verilator-config-version.cmake.in index 7cf05f411..55a9ae285 100644 --- a/verilator-config-version.cmake.in +++ b/verilator-config-version.cmake.in @@ -7,7 +7,7 @@ # # find_package(verilate 4.0) # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index 35091d5b9..bc61bcccf 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -11,7 +11,7 @@ # add_executable(simulator ) # verilate(simulator SOURCES ) # -# Copyright 2003-2023 by Wilson Snyder. This program is free software; you +# Copyright 2003-2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0.