From d384a69877f2c01882f4907033552aa90dbe060f Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 8 Sep 2021 19:31:26 -0400
Subject: [PATCH] Fix display has no time units on class function (#3116).

---
 Changes                           | 1 +
 src/V3AstNodes.cpp                | 2 +-
 src/V3LinkLevel.cpp               | 2 ++
 src/V3LinkParse.cpp               | 3 ++-
 test_regress/t/t_class_format.out | 5 +++--
 test_regress/t/t_class_format.v   | 7 +++++++
 6 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/Changes b/Changes
index 9033c8513..cf419d12e 100644
--- a/Changes
+++ b/Changes
@@ -13,6 +13,7 @@ Verilator 4.213 devel
 
 * Include processor information in verilator_gantt data file.
 * Fix verilator_profcfunc profile accounting (#3115).
+* Fix display has no time units on class function (#3116). [Damien Pretet]
 
 
 Verilator 4.212 2021-09-01
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index ea3ecdf8e..abc85275f 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -1338,7 +1338,7 @@ void AstNodeCoverOrAssert::dump(std::ostream& str) const {
 }
 void AstDisplay::dump(std::ostream& str) const {
     this->AstNodeStmt::dump(str);
-    // str<<" "<<displayType().ascii();
+    // str << " " << displayType().ascii();
 }
 void AstEnumItemRef::dump(std::ostream& str) const {
     this->AstNodeMath::dump(str);
diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp
index d83627ef3..bbecddae1 100644
--- a/src/V3LinkLevel.cpp
+++ b/src/V3LinkLevel.cpp
@@ -132,6 +132,8 @@ void V3LinkLevel::timescaling(const ModVec& mods) {
         v3Global.rootp()->timeprecisionMerge(v3Global.rootp()->fileline(),
                                              VTimescale(VTimescale::TS_DEFAULT));
     }
+
+    // Classes under package have timescale propaged in V3LinkParse
 }
 
 //######################################################################
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index 22cc38dc8..6dff6a029 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -504,7 +504,8 @@ private:
         {
             // Module: Create sim table for entire module and iterate
             cleanFileline(nodep);
-            //
+            // Classes inherit from upper package
+            if (m_modp && nodep->timeunit().isNone()) nodep->timeunit(m_modp->timeunit());
             m_modp = nodep;
             m_genblkAbove = 0;
             m_genblkNum = 0;
diff --git a/test_regress/t/t_class_format.out b/test_regress/t/t_class_format.out
index f620c0e3f..e4886448b 100644
--- a/test_regress/t/t_class_format.out
+++ b/test_regress/t/t_class_format.out
@@ -1,3 +1,4 @@
-''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44} }'
-''{b:'h1, i:'h2a, carray4:'{'h911, 'h922, 'h933, 'h944} }'
+''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44} , name:"object_name"}'
+''{b:'h1, i:'h2a, carray4:'{'h911, 'h922, 'h933, 'h944} , name:"object_name"}'
+DEBUG: object_name (@0) message
 *-* All Finished *-*
diff --git a/test_regress/t/t_class_format.v b/test_regress/t/t_class_format.v
index 001a5284e..15a67bca9 100644
--- a/test_regress/t/t_class_format.v
+++ b/test_regress/t/t_class_format.v
@@ -15,6 +15,10 @@ class Cls;
    bit b;
    int i;
    bit [15:0] carray4 [4];
+   string     name;
+   task debug();
+      $display("DEBUG: %s (@%0t) %s", this.name, $realtime, "message");
+   endtask
 endclass
 
 module t (/*AUTOARG*/);
@@ -23,6 +27,7 @@ module t (/*AUTOARG*/);
       c = new;
       c.b = '1;
       c.i = 42;
+      c.name = "object_name";
 
       c.carray4[0] = 16'h11;
       c.carray4[1] = 16'h22;
@@ -33,6 +38,8 @@ module t (/*AUTOARG*/);
       c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944};
       $display("'%p'", c);
 
+      c.debug();
+
       $write("*-* All Finished *-*\n");
       $finish;
    end