diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 251022043..0aa867324 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -1211,7 +1211,8 @@ class LinkDotFindVisitor final : public VNVisitor {
                         return;
                     }
                     const bool nansiBad
-                        = ((findvarp->isDeclTyped() && nodep->isDeclTyped())
+                        = (((findvarp->isDeclTyped() || findvarp->isNet())
+                            && (nodep->isDeclTyped() || nodep->isNet()))
                            || (findvarp->isIO() && nodep->isIO()));  // e.g. !(output && output)
                     const bool ansiBad
                         = findvarp->isAnsi() || nodep->isAnsi();  // dup illegal with ANSI
diff --git a/test_regress/t/t_const_opt.v b/test_regress/t/t_const_opt.v
index 843bd8870..cfdcc3917 100644
--- a/test_regress/t/t_const_opt.v
+++ b/test_regress/t/t_const_opt.v
@@ -152,7 +152,7 @@ module bug3182(in, out);
       bit_source = c_fake_dependency() | in;
 
    wire [5:0] tmp = bit_source; // V3Gate should inline this
-   wire out =  ~(tmp >> 5) & (bit_source == 5'd10);
+   assign out =  ~(tmp >> 5) & (bit_source == 5'd10);
    /* verilator lint_on WIDTH */
 endmodule
 
@@ -374,7 +374,6 @@ endmodule
 // total polarity. This bug was introduced when fixing #3445.
 module bug4059(input wire clk, input wire [31:0] in, output wire out);
    wire [127:0] words_i;
-   logic [127:0] words_i;
    for (genvar i = 0; i < $bits(in); ++i) begin
       always_ff @(posedge clk)
          words_i[4 * i +: 4] <= {4{in[i]}};
diff --git a/test_regress/t/t_var_dup2_bad.out b/test_regress/t/t_var_dup2_bad.out
index 347ba1095..79d73749b 100644
--- a/test_regress/t/t_var_dup2_bad.out
+++ b/test_regress/t/t_var_dup2_bad.out
@@ -11,4 +11,16 @@
         t/t_var_dup2_bad.v:11:11: ... Location of original declaration
    11 |    output bad_o_r);
       |           ^~~~~~~
+%Error: t/t_var_dup2_bad.v:17:9: Duplicate declaration of signal: 'bad_w_r'
+   17 |    reg  bad_w_r;
+      |         ^~~~~~~
+        t/t_var_dup2_bad.v:16:9: ... Location of original declaration
+   16 |    wire bad_w_r;
+      |         ^~~~~~~
+%Error: t/t_var_dup2_bad.v:20:9: Duplicate declaration of signal: 'bad_r_w'
+   20 |    reg  bad_r_w;
+      |         ^~~~~~~
+        t/t_var_dup2_bad.v:19:9: ... Location of original declaration
+   19 |    wire bad_r_w;
+      |         ^~~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_var_dup2_bad.v b/test_regress/t/t_var_dup2_bad.v
index 21eb3cb4b..3d762be23 100644
--- a/test_regress/t/t_var_dup2_bad.v
+++ b/test_regress/t/t_var_dup2_bad.v
@@ -12,4 +12,11 @@ module t
 
    wire bad_o_w;
    reg  bad_o_r;
+
+   wire bad_w_r;
+   reg  bad_w_r;
+
+   wire bad_r_w;
+   reg  bad_r_w;
+
 endmodule
diff --git a/test_regress/t/t_var_dup_bad.out b/test_regress/t/t_var_dup_bad.out
index 4f86e876a..b029c5809 100644
--- a/test_regress/t/t_var_dup_bad.out
+++ b/test_regress/t/t_var_dup_bad.out
@@ -47,7 +47,6 @@
    64 |    output bad_reout_port
       |           ^~~~~~~~~~~~~~
 %Error: t/t_var_dup_bad.v:73:9: Duplicate declaration of signal: 'bad_rewire'
-                              : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2)
    73 |    wire bad_rewire;
       |         ^~~~~~~~~~
         t/t_var_dup_bad.v:70:16: ... Location of original declaration