diff --git a/Changes b/Changes
index c0e7a903f..918c9cba7 100644
--- a/Changes
+++ b/Changes
@@ -41,6 +41,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix creating implicit variables for expressions, bug196. [Byron Bradley]
 
+**** Fix duplicate implicit variables under generates, bug201. [Byron Bradley]
+
 **** Fix tracing with --pins-bv 1, bug195.  [Michael S]
 
 **** Fix MinGW compilation, bug184. [by Shankar Giri]
diff --git a/src/V3Link.cpp b/src/V3Link.cpp
index 7eb85a710..d1fa8b7ca 100644
--- a/src/V3Link.cpp
+++ b/src/V3Link.cpp
@@ -191,9 +191,12 @@ private:
 	    m_modp->addStmtp(newp);
 	    // Link it to signal list
 	    IdState old_id = m_idState;
+	    V3SymTable* old_varsp = m_curVarsp;
 	    m_idState = ID_FIND;
+	    m_curVarsp = symsFind(m_modp);  // Must add the variable under the module; curVarsp might be lower now
 	    newp->accept(*this);
 	    m_idState = old_id;
+	    m_curVarsp = old_varsp;
 	}
     }
 
diff --git a/test_regress/t/t_gen_if.v b/test_regress/t/t_gen_if.v
index bc6d4c3ca..33ef71071 100644
--- a/test_regress/t/t_gen_if.v
+++ b/test_regress/t/t_gen_if.v
@@ -6,19 +6,27 @@
 // without warranty.
 `timescale 1ns / 1ps
 
-module t(data_i, data_o);
+module t(data_i, data_o, single);
    parameter op_bits = 32;
    input [op_bits -1:0] data_i;
    output [31:0] data_o;
+   input single;
 
    //simplistic example, should choose 1st conditional generate and assign straight through
    //the tool also compiles the special case and determines an error (replication value is 0
    generate
       if (op_bits == 32) begin : general_case
          assign data_o = data_i;
+	 // Test implicit signals
+	 /* verilator lint_off IMPLICIT */
+	 assign imp = single;
+	 /* verilator lint_on IMPLICIT */
          end
       else begin : special_case
          assign data_o = {{(32 -op_bits){1'b0}},data_i};
+	 /* verilator lint_off IMPLICIT */
+	 assign imp = single;
+	 /* verilator lint_on IMPLICIT */
          end
    endgenerate
 endmodule