diff --git a/Changes b/Changes
index e43339098..f71daf4f1 100644
--- a/Changes
+++ b/Changes
@@ -18,6 +18,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix array of instantiations with sub-range output, bug414. [Jeremy Bennett]
 
+****  Fix BLKSEQ warnings on variables declared inside always. [Ruben Diez]
 
 * Verilator 3.830 2011/11/27
 
diff --git a/src/V3Link.cpp b/src/V3Link.cpp
index 8094a8c66..3928eae73 100644
--- a/src/V3Link.cpp
+++ b/src/V3Link.cpp
@@ -79,6 +79,7 @@ private:
     V3SymTable* m_cellVarsp;	// Symbol table of variables under cell's module
     int		m_beginNum;	// Begin block number, 0=none seen
     int		m_modBeginNum;	// Begin block number in module, 0=none seen
+    bool	m_inAlways;	// Inside an always
     bool	m_inGenerate;	// Inside a generate
     AstNodeModule*	m_valueModp;	// If set, move AstVar->valuep() initial values to this module
     vector<V3SymTable*> m_delSymps;	// Symbol tables to delete
@@ -340,6 +341,8 @@ private:
 	    if (nodep->isIO() && !m_ftaskp && !nodep->user2()) {
 		nodep->v3error("Input/output/inout does not appear in port list: "<<nodep->prettyName());
 	    }
+	    // temporaries under an always aren't expected to be blocking
+	    if (m_inAlways) nodep->fileline()->modifyWarnOff(V3ErrorCode::BLKSEQ, true);
 	    if (nodep->valuep()) {
 		// A variable with a = value can be three things:
 		FileLine* fl = nodep->valuep()->fileline();
@@ -745,7 +748,9 @@ private:
 	visitIterateNoValueMod(nodep);
     }
     virtual void visit(AstAlways* nodep, AstNUser*) {
+	m_inAlways = true;
 	visitIterateNoValueMod(nodep);
+	m_inAlways = false;
     }
     virtual void visit(AstPslCover* nodep, AstNUser*) {
 	visitIterateNoValueMod(nodep);
@@ -768,6 +773,7 @@ public:
 	m_paramNum = 0;
 	m_beginNum = 0;
 	m_modBeginNum = 0;
+	m_inAlways = false;
 	m_inGenerate = false;
 	m_valueModp = NULL;
 	//
diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v
index 41c96ef04..96955cf0c 100644
--- a/test_regress/t/t_EXAMPLE.v
+++ b/test_regress/t/t_EXAMPLE.v
@@ -13,7 +13,7 @@
 // please note it here, otherwise:**
 //
 // This file ONLY is placed into the Public Domain, for any use,
-// without warranty, 2011 by Wilson Snyder.
+// without warranty, 2012 by Wilson Snyder.
 
 module t (/*AUTOARG*/
    // Inputs
diff --git a/test_regress/t/t_lint_blksync_loop.v b/test_regress/t/t_lint_blksync_loop.v
index ae012aa70..15826e414 100644
--- a/test_regress/t/t_lint_blksync_loop.v
+++ b/test_regress/t/t_lint_blksync_loop.v
@@ -73,6 +73,12 @@ module reg_1r1w
 
     integer        x;
 
+    // Message 679
+    always @(posedge clk) begin
+       int tmp = x + 1;
+       if (tmp !== x + 1) $stop;
+    end
+
     always @(posedge clk or negedge rst_l) begin
        if (!rst_l) begin
 	  for (x=0; x<DEPTH; x=x+1) begin // <== VERILATOR FLAGS THIS LINE