From d17bcd8afe52894d0df2c8bf92449b4d029ad6df Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 22 Jan 2010 19:08:20 -0500
Subject: [PATCH] Allow 'global' reserved identifier in 1800-2009 when possible

---
 src/V3ParseImp.h            |  6 ++++++
 src/verilog.l               | 36 +++++++++++++++++++++++++++++++++---
 src/verilog.y               |  2 ++
 test_regress/t/t_var_rsvd.v |  3 +++
 4 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h
index a193d2b75..8b7ddd8de 100644
--- a/src/V3ParseImp.h
+++ b/src/V3ParseImp.h
@@ -220,6 +220,10 @@ class V3ParseImp {
     int		m_inBeginKwd;		// Inside a `begin_keywords
     int		m_lastVerilogState;	// Last LEX state in `begin_keywords
 
+    bool	m_ahead;		// aheadToken is valid
+    int		m_aheadToken;		// Token we read ahead
+    V3ParseBisonYYSType m_aheadVal;	// aheadToken's value
+
     deque<string*> m_stringps;		// Created strings for later cleanup
     deque<V3Number*> m_numberps;	// Created numbers for later cleanup
     deque<FileLine>  m_lintState;	// Current lint state for save/restore
@@ -317,6 +321,8 @@ public:
 	m_inLibrary = false;
 	m_inBeginKwd = 0;
 	m_lastVerilogState = stateVerilogRecent();
+	m_ahead = false;
+	m_aheadToken = 0;
     }
     ~V3ParseImp();
     void parserClear();
diff --git a/src/verilog.l b/src/verilog.l
index dc07e486f..fb195862e 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -490,12 +490,12 @@ escid	\\[^ \t\f\r\n]+
   /* SystemVerilog 2009 */
 <S09,PSL>{
   /*     Keywords */
+  "global"	 	{ FL; return yGLOBAL__LEX; }
   /*     Generic unsupported warnings */
   "accept_on"	 	{ yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
   "checker"	 	{ yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
   "endchecker"	 	{ yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
   "eventually"	 	{ yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
-  "global"	 	{ yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
   "implies"	 	{ yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
   "let"		 	{ yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
   "nexttime"	 	{ yyerrorf("Unsupported: SystemVerilog 2009 reserved word not implemented: %s",yytext); }
@@ -941,8 +941,38 @@ int V3ParseImp::stateVerilogRecent() { return STATE_VERILOG_RECENT; }
 
 int V3ParseImp::lexToken() {
     // called from lexToBison, has a "this"
-    // yylvalp is global
-    int token = yylexThis();
+    // Fetch next token from prefetch or real lexer
+    int token;
+    if (m_ahead) {
+	// We prefetched an extra token, give it back
+	m_ahead = false;
+	token = m_aheadToken;
+	yylval = m_aheadVal;
+    } else {
+	// Parse new token
+	token = yylexThis();
+	//yylval // Set by yylexThis()
+    }
+    // If a paren, read another
+    if (token == yGLOBAL__LEX
+	// Never put yID_* here; below symbol table resolution would break
+	) {
+	if (debugFlex()) { cout<<"   lexToken: reading ahead to find possible strength"<<endl; }
+	V3ParseBisonYYSType curValue = yylval;  // Remember value, as about to read ahead
+	int nexttok = yylexThis();
+	m_ahead = true;
+	m_aheadToken = nexttok;
+	m_aheadVal = yylval;
+	yylval = curValue;
+	// Now potentially munge the current token
+	if (token == yGLOBAL__LEX) {
+	    if (nexttok == yCLOCKING) token = yGLOBAL__CLOCKING;
+	    else { token = yaID__LEX; yylval.strp = PARSEP->newString("global"); }  // Avoid 2009 "global" conflicting with old code when we can
+	}
+	// If add to above "else if", also add to "if (token" further above
+    }
+    // If an id, change the type based on symbol table
+    // Note above sometimes converts yGLOBAL to a yaID__LEX
     if (token == yaID__LEX) {
 	AstNode* scp;
 	if (V3SymTable* look_underp = SYMP->nextId()) {
diff --git a/src/verilog.y b/src/verilog.y
index c28bf9a11..250bd3c2a 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -298,6 +298,8 @@ class AstSenTree;
 %token<fl>		yFUNCTION	"function"
 %token<fl>		yGENERATE	"generate"
 %token<fl>		yGENVAR		"genvar"
+%token<fl>		yGLOBAL__CLOCKING "global-then-clocking"
+%token<fl>		yGLOBAL__LEX	"global-in-lex"
 %token<fl>		yIF		"if"
 %token<fl>		yIFF		"iff"
 %token<fl>		yIMPORT		"import"
diff --git a/test_regress/t/t_var_rsvd.v b/test_regress/t/t_var_rsvd.v
index 1f3b0b5b0..446a17823 100644
--- a/test_regress/t/t_var_rsvd.v
+++ b/test_regress/t/t_var_rsvd.v
@@ -15,6 +15,9 @@ module t (/*AUTOARG*/
    reg  vector;	// OK, as not public
    reg  switch /*verilator public*/;	// Bad
 
+   // global is a 1800-2009 reserved word, but we allow it when possible.
+   reg  global;
+
    initial begin
       $write("*-* All Finished *-*\n");
       $finish;