From d1319cf81ea07f376ecefddf47240f2b97c80a87 Mon Sep 17 00:00:00 2001 From: Yilin Li <60502081+AllinLeeYL@users.noreply.github.com> Date: Wed, 10 Jun 2026 15:38:41 +0200 Subject: [PATCH] Fix dpi export pointers (#7742) (#7751) Fixes #7742. --- docs/CONTRIBUTORS | 1 + src/V3EmitCFunc.h | 10 ++++++-- test_regress/t/t_dpi_export_unpack.py | 20 ++++++++++++++++ test_regress/t/t_dpi_export_unpack.v | 33 +++++++++++++++++++++++++++ 4 files changed, 62 insertions(+), 2 deletions(-) create mode 100755 test_regress/t/t_dpi_export_unpack.py create mode 100644 test_regress/t/t_dpi_export_unpack.v diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 880b5608a..ef3746a76 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -325,3 +325,4 @@ Yogish Sekhar 24bit-xjkp Zubin Jain Muzaffer Kal +Yilin Li diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index c05c46afe..6eedcbc69 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -573,8 +573,14 @@ public: + "\", " + std::to_string(nodep->fileline()->lineno()) + ")->"), memberVarp, resetp->constructing()); } else { - AstVar* const varp = VN_AS(fromp, NodeVarRef)->varp(); - emitVarReset("", varp, resetp->constructing()); + AstNodeVarRef* const fromVarRefp = VN_AS(fromp, NodeVarRef); + AstVar* const varp = fromVarRefp->varp(); + const string prefix + = fromVarRefp->selfPointer().isEmpty() + ? "" + : dereferenceString( + VN_AS(fromp, NodeVarRef)->selfPointerProtect(m_useSelfForThis)); + emitVarReset(prefix, varp, resetp->constructing()); } return; } diff --git a/test_regress/t/t_dpi_export_unpack.py b/test_regress/t/t_dpi_export_unpack.py new file mode 100755 index 000000000..b365ee618 --- /dev/null +++ b/test_regress/t/t_dpi_export_unpack.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# 9-Jun-2026: Modifications for this test contributed by Yilin Li. + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_dpi_export_unpack.v b/test_regress/t/t_dpi_export_unpack.v new file mode 100644 index 000000000..91cc32577 --- /dev/null +++ b/test_regress/t/t_dpi_export_unpack.v @@ -0,0 +1,33 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2020 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// 9-Jun-2026: Modifications for this test contributed by Yilin Li. + +export "DPI-C" task readHEX; +export "DPI-C" task loadHEX; + +task readHEX; + input string file; + output logic [7:0] stimuli[32'h00010000]; + $readmemh(file, stimuli); +endtask + +task loadHEX; + input string file; + logic [7:0] stimuli[32'h00010000]; + readHEX(file, stimuli); +endtask + +module tb (); + + logic [7:0] result[32'h00010000]; + initial begin + loadHEX("dummy"); + end + +endmodule