From d04eb977c2895bbee36839d9dd3272f1966b737a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Wed, 9 Apr 2014 07:58:46 -0400
Subject: [PATCH] Fix mis-extending red xor/xand operators.

---
 Changes                       | 2 +-
 src/verilog.y                 | 4 ++--
 test_regress/t/t_math_arith.v | 8 ++++++++
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/Changes b/Changes
index 0e5c75deb..44ecd6f8c 100644
--- a/Changes
+++ b/Changes
@@ -25,7 +25,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix modport function import not-found error.
 
-****  Fix signed extension problems with -Wno-WIDTH, bug729. [Clifford Wolf]
+****  Fix expression width problems with -Wno-WIDTH, bug729, bug736. [Clifford Wolf]
 
 ****  Fix power operator calculation, bug730, bug735. [Clifford Wolf]
 
diff --git a/src/verilog.y b/src/verilog.y
index c57563aa7..bc77f9103 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -2845,8 +2845,8 @@ expr<nodep>:			// IEEE: part of expression/constant_expression/primary
 	|	'~' ~r~expr	%prec prNEGATION	{ $$ = new AstNot	($1,$2); }
 	|	'|' ~r~expr	%prec prREDUCTION	{ $$ = new AstRedOr	($1,$2); }
 	|	'^' ~r~expr	%prec prREDUCTION	{ $$ = new AstRedXor	($1,$2); }
-	|	yP_NAND ~r~expr	%prec prREDUCTION	{ $$ = new AstNot($1,new AstRedAnd($1,$2)); }
-	|	yP_NOR  ~r~expr	%prec prREDUCTION	{ $$ = new AstNot($1,new AstRedOr ($1,$2)); }
+	|	yP_NAND ~r~expr	%prec prREDUCTION	{ $$ = new AstLogNot($1,new AstRedAnd($1,$2)); }
+	|	yP_NOR  ~r~expr	%prec prREDUCTION	{ $$ = new AstLogNot($1,new AstRedOr ($1,$2)); }
 	|	yP_XNOR ~r~expr	%prec prREDUCTION	{ $$ = new AstRedXnor	($1,$2); }
 	//
 	//			// IEEE: inc_or_dec_expression
diff --git a/test_regress/t/t_math_arith.v b/test_regress/t/t_math_arith.v
index a001cdafc..36f993e6e 100644
--- a/test_regress/t/t_math_arith.v
+++ b/test_regress/t/t_math_arith.v
@@ -111,6 +111,14 @@ module t (/*AUTOARG*/
 	 // Test display extraction widthing
 	 $display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
 
+	 // bug736
+	 //verilator lint_off WIDTH
+	 if ((~| 4'b0000) != 4'b0001) $stop;
+	 if ((~| 4'b0010) != 4'b0000) $stop;
+	 if ((~& 4'b1111) != 4'b0000) $stop;
+	 if ((~& 4'b1101) != 4'b0001) $stop;
+	 //verilator lint_on WIDTH
+
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end