From ce058cc432be29f143b544b3fe528262095ee131 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 25 Mar 2025 08:28:36 -0400
Subject: [PATCH] Fix `$fscanf` not returning -1 on EOF (#5881).

---
 Changes                                       |  1 +
 include/verilated.cpp                         | 11 ++++--
 ...ile_scan_input.dat => t_sys_file_scan.dat} |  0
 test_regress/t/t_sys_file_scan.v              |  2 +-
 test_regress/t/t_sys_file_scan2.dat           |  1 +
 test_regress/t/t_sys_file_scan2.py            | 18 +++++++++
 test_regress/t/t_sys_file_scan2.v             | 37 +++++++++++++++++++
 7 files changed, 66 insertions(+), 4 deletions(-)
 rename test_regress/t/{t_sys_file_scan_input.dat => t_sys_file_scan.dat} (100%)
 create mode 100644 test_regress/t/t_sys_file_scan2.dat
 create mode 100755 test_regress/t/t_sys_file_scan2.py
 create mode 100644 test_regress/t/t_sys_file_scan2.v

diff --git a/Changes b/Changes
index 88bbb38b1..fc5ef95f2 100644
--- a/Changes
+++ b/Changes
@@ -54,6 +54,7 @@ Verilator 5.035 devel
 * Fix streaming of unpacked arrays concatenations (#5856). [Ryszard Rozak, Antmicro Ltd.]
 * Fix Windows paths in Perl (#5858) (#5860). [Tobias Jensen]
 * Fix algorithm header portability in V3Os.cpp (for std::replace) (#5861). [William D. Jones]
+* Fix `$fscanf` not returning -1 on EOF (#5881).
 
 
 Verilator 5.034 2025-02-24
diff --git a/include/verilated.cpp b/include/verilated.cpp
index 489ec7ee7..20d0cacc8 100644
--- a/include/verilated.cpp
+++ b/include/verilated.cpp
@@ -1249,9 +1249,9 @@ IData _vl_vsscanf(FILE* fp,  // If a fscanf
     bool inPct = false;
     bool inIgnore = false;
     std::string::const_iterator pos = format.cbegin();
-    for (; pos != format.cend() && !_vl_vsss_eof(fp, floc); ++pos) {
-        // VL_DBG_MSGF("_vlscan fmt='"<<pos[0]<<"' floc="<<floc<<" file='"<<_vl_vsss_peek(fp, floc,
-        // fromp, fstr)<<"'\n");
+    for (; pos != format.cend(); ++pos) {
+        // VL_DBG_MSGF("_vlscan fmt='%c' floc=%d file='%c'\n", pos[0], floc,
+        // _vl_vsss_peek(fp, floc, fromp, fstr));
         if (!inPct && pos[0] == '%') {
             inPct = true;
             inIgnore = false;
@@ -1435,7 +1435,12 @@ IData _vl_vsscanf(FILE* fp,  // If a fscanf
             }  // switch
         }
     }
+    // Processed all arguments
+    return got;
+
 done:
+    // Scan stopped early, return parsed or EOF
+    if (_vl_vsss_eof(fp, floc)) return -1;
     return got;
 }
 
diff --git a/test_regress/t/t_sys_file_scan_input.dat b/test_regress/t/t_sys_file_scan.dat
similarity index 100%
rename from test_regress/t/t_sys_file_scan_input.dat
rename to test_regress/t/t_sys_file_scan.dat
diff --git a/test_regress/t/t_sys_file_scan.v b/test_regress/t/t_sys_file_scan.v
index 3dda96aa9..545300dcc 100644
--- a/test_regress/t/t_sys_file_scan.v
+++ b/test_regress/t/t_sys_file_scan.v
@@ -11,7 +11,7 @@ module t;
    integer count, a;
 
    initial begin
-      infile = $fopen("t/t_sys_file_scan_input.dat", "r");
+      infile = $fopen("t/t_sys_file_scan.dat", "r");
       outfile = $fopen({`STRINGIFY(`TEST_OBJ_DIR),"/t_sys_file_scan_test.log"}, "w");
 
       count = 1234;
diff --git a/test_regress/t/t_sys_file_scan2.dat b/test_regress/t/t_sys_file_scan2.dat
new file mode 100644
index 000000000..6e7b1456a
--- /dev/null
+++ b/test_regress/t/t_sys_file_scan2.dat
@@ -0,0 +1 @@
+vec 6163 16
diff --git a/test_regress/t/t_sys_file_scan2.py b/test_regress/t/t_sys_file_scan2.py
new file mode 100755
index 000000000..f989a35fb
--- /dev/null
+++ b/test_regress/t/t_sys_file_scan2.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_sys_file_scan2.v b/test_regress/t/t_sys_file_scan2.v
new file mode 100644
index 000000000..254ee5805
--- /dev/null
+++ b/test_regress/t/t_sys_file_scan2.v
@@ -0,0 +1,37 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
+
+module t;
+   int cfg_file, f_stat;
+   reg [8*8:1] fname;
+   int index;
+   int count;
+
+   initial begin
+      cfg_file = $fopen("t/t_sys_file_scan2.dat", "r");
+
+      f_stat = $fscanf(cfg_file, "%s", fname);
+      `checkd(f_stat, 1);
+      `checks(fname, "vec");
+      f_stat = $fscanf(cfg_file, "%d", index);
+      `checkd(f_stat, 1);
+      `checkd(index, 6163);
+      f_stat = $fscanf(cfg_file, "%d", count);
+      `checkd(f_stat, 1);
+      `checkd(count, 16);
+
+      //eof
+      f_stat = $fscanf(cfg_file, "%s", fname);
+      `checkd(f_stat, -1);
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule