From cca759a41ec3e0a057a797ecbfa69cbf632fbb8e Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 22 May 2011 08:43:36 -0400 Subject: [PATCH] Tests: Example embedding --- test_regress/t/t_embed1.pl | 51 +++++++++++++ test_regress/t/t_embed1.v | 109 ++++++++++++++++++++++++++++ test_regress/t/t_embed1_c.cpp | 123 ++++++++++++++++++++++++++++++++ test_regress/t/t_embed1_child.v | 45 ++++++++++++ test_regress/t/t_embed1_wrap.v | 90 +++++++++++++++++++++++ 5 files changed, 418 insertions(+) create mode 100755 test_regress/t/t_embed1.pl create mode 100644 test_regress/t/t_embed1.v create mode 100644 test_regress/t/t_embed1_c.cpp create mode 100644 test_regress/t/t_embed1_child.v create mode 100644 test_regress/t/t_embed1_wrap.v diff --git a/test_regress/t/t_embed1.pl b/test_regress/t/t_embed1.pl new file mode 100755 index 000000000..9abaa2684 --- /dev/null +++ b/test_regress/t/t_embed1.pl @@ -0,0 +1,51 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +use File::Spec; + +my $self = $Self; +my $child_dir = "$Self->{obj_dir}_child"; +mkdir $child_dir; + +# Compile the child +{ + my @cmdargs = $Self->compile_vlt_flags + (VM_PREFIX => "$Self->{VM_PREFIX}_child", + top_filename => "$Self->{name}_child.v", + verilator_flags => ["-cc", "-Mdir", "${child_dir}", "--debug-check"], + ); + + $Self->_run(logfile=>"${child_dir}/vlt_compile.log", + cmd=>\@cmdargs); + + $Self->_run(logfile=>"${child_dir}/vlt_gcc.log", + cmd=>["cd ${child_dir} && ", + "make", "-f".getcwd()."/Makefile_obj", + "CPPFLAGS_DRIVER=-D".uc($self->{name}), + ($opt_verbose ? "CPPFLAGS_DRIVER2=-DTEST_VERBOSE=1":""), + "MAKE_MAIN=0", + "VM_PREFIX=$self->{VM_PREFIX}_child", + "V$self->{name}_child__ALL.a", # bypass default rule, make archive + ($param{make_flags}||""), + ]); +} + +# Compile the parent (might be with other than verilator) +compile ( + v_flags2 => [File::Spec->rel2abs("${child_dir}/V$self->{name}_child__ALL.a"), + # TODO would be nice to have this in embedded archive + "t/t_embed1_c.cpp"], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_embed1.v b/test_regress/t/t_embed1.v new file mode 100644 index 000000000..d84751fc2 --- /dev/null +++ b/test_regress/t/t_embed1.v @@ -0,0 +1,109 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire bit_in = crc[0]; + wire [30:0] vec_in = crc[31:1]; + wire [123:0] wide_in = {crc[59:0],~crc[63:0]}; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire exp_bit_out; // From reference of t_embed1_child.v + wire exp_did_init_out; // From reference of t_embed1_child.v + wire [30:0] exp_vec_out; // From reference of t_embed1_child.v + wire [123:0] exp_wide_out; // From reference of t_embed1_child.v + wire got_bit_out; // From test of t_embed1_wrap.v + wire got_did_init_out; // From test of t_embed1_wrap.v + wire [30:0] got_vec_out; // From test of t_embed1_wrap.v + wire [123:0] got_wide_out; // From test of t_embed1_wrap.v + // End of automatics + + // A non-embedded master + + /* t_embed1_child AUTO_TEMPLATE( + .\(.*_out\) (exp_\1[]), + .is_ref (1'b1)); + */ + t_embed1_child reference + (/*AUTOINST*/ + // Outputs + .bit_out (exp_bit_out), // Templated + .vec_out (exp_vec_out[30:0]), // Templated + .wide_out (exp_wide_out[123:0]), // Templated + .did_init_out (exp_did_init_out), // Templated + // Inputs + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b1)); // Templated + + // The embeded comparison + + /* t_embed1_wrap AUTO_TEMPLATE( + .\(.*_out\) (got_\1[]), + .is_ref (1'b0)); + */ + + t_embed1_wrap test + (/*AUTOINST*/ + // Outputs + .bit_out (got_bit_out), // Templated + .vec_out (got_vec_out[30:0]), // Templated + .wide_out (got_wide_out[123:0]), // Templated + .did_init_out (got_did_init_out), // Templated + // Inputs + .clk (clk), + .bit_in (bit_in), + .vec_in (vec_in[30:0]), + .wide_in (wide_in[123:0]), + .is_ref (1'b0)); // Templated + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, + got_wide_out !== exp_wide_out, + got_vec_out !== exp_vec_out, + got_bit_out !== exp_bit_out, + got_did_init_out !== exp_did_init_out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x gv=%x ev=%x\n",$time, cyc, crc, result, + got_vec_out, exp_vec_out); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + end + else if (cyc<90) begin + if (result != 64'h0) begin + $display("Bit mismatch, result=%x\n", result); + $stop; + end + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + //Child prints this: $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_embed1_c.cpp b/test_regress/t/t_embed1_c.cpp new file mode 100644 index 000000000..54261bb5c --- /dev/null +++ b/test_regress/t/t_embed1_c.cpp @@ -0,0 +1,123 @@ +// -*- C++ -*- +//************************************************************************* +// +// Copyright 2011-2011 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License. +// Version 2.0. +// +// Verilator is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +//************************************************************************* + +#include +#include "svdpi.h" + +#include "../t_embed1_child/Vt_embed1_child.h" + +//====================================================================== + +#if defined(VERILATOR) +# include "Vt_embed1__Dpi.h" +#elif defined(VCS) +# include "../vc_hdrs.h" +#elif defined(CADENCE) +# define NEED_EXTERNS +#else +# error "Unknown simulator for DPI test" +#endif + +#include "verilated.h" + +#ifdef NEED_EXTERNS +extern "C" { + + extern void t_embed_child_initial(); + extern void t_embed_child_final(); + extern void t_embed_child_eval(); + extern void t_embed_child_io_eval(); // TODO real function params here +} +#endif + +//====================================================================== + +extern int T_Embed_Child_Unique; +int T_Embed_Child_Unique = 0; // Address used for uniqueness + +Vt_embed1_child* __get_modelp() { + svScope scope = svGetScope(); + if (!scope) { + vl_fatal(__FILE__,__LINE__,__FILE__,"svGetScope failed"); + return NULL; + } + + void* __modelp = svGetUserData(scope, &T_Embed_Child_Unique); + if (!__modelp) { + // Create the model + const char* scopenamep = svGetNameFromScope(scope); + if (!scopenamep) vl_fatal(__FILE__,__LINE__,__FILE__,"svGetNameFromScope failed"); + __modelp = new Vt_embed1_child(scopenamep); + if (svPutUserData(scope, &T_Embed_Child_Unique, __modelp)) { + vl_fatal(__FILE__,__LINE__,__FILE__,"svPutUserData failed"); + } + } + return (Vt_embed1_child*)(__modelp); +} + +void t_embed_child_initial() { + VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_initial\n"); ); + Vt_embed1_child* __modelp = __get_modelp(); + __modelp->eval(); +} + +void t_embed_child_final() { + VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_final\n"); ); + Vt_embed1_child* __modelp = __get_modelp(); + __modelp->final(); +} + +void t_embed_child_eval() { + VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_eval\n"); ); + Vt_embed1_child* __modelp = __get_modelp(); + __modelp->eval(); +} + +void t_embed_child_io_eval (unsigned char clk, + unsigned char bit_in, + const svBitVecVal* vec_in, + const svBitVecVal* wide_in, + unsigned char is_ref, + unsigned char* bit_out, + svBitVecVal* vec_out, + svBitVecVal* wide_out, + unsigned char* did_init_out) { + VL_DEBUG_IF(VL_PRINTF(" t_embed1_child_io_eval\n"); ); + Vt_embed1_child* __modelp = __get_modelp(); + VL_DEBUG_IF(VL_PRINTF("[%0ld] in clk=%x b=%x V=%x R=%x\n", + VL_TIME_Q(), clk, bit_in, vec_in[0], is_ref);); + __modelp->clk = clk; + __modelp->bit_in = bit_in; + __modelp->vec_in = vec_in[0]; + __modelp->wide_in[0] = wide_in[0]; + __modelp->wide_in[1] = wide_in[1]; + __modelp->wide_in[2] = wide_in[2]; + __modelp->wide_in[3] = wide_in[3]; + __modelp->is_ref = is_ref; + // + __modelp->eval(); + // TODO maybe we should look at a "change detect" to know if we need to copy + // out the variables; can return this value to the caller verilog code too + // + *bit_out = __modelp->bit_out; + vec_out[0] = __modelp->vec_out; + wide_out[0] = __modelp->wide_out[0]; + wide_out[1] = __modelp->wide_out[1]; + wide_out[2] = __modelp->wide_out[2]; + wide_out[3] = __modelp->wide_out[3]; + *did_init_out = __modelp->did_init_out; + VL_DEBUG_IF(VL_PRINTF("[%0ld] out b=%x V=%x DI=%x\n", + VL_TIME_Q(), *bit_out, *vec_out, *did_init_out);); +} diff --git a/test_regress/t/t_embed1_child.v b/test_regress/t/t_embed1_child.v new file mode 100644 index 000000000..b7b493b21 --- /dev/null +++ b/test_regress/t/t_embed1_child.v @@ -0,0 +1,45 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t_embed1_child (/*AUTOARG*/ + // Outputs + bit_out, vec_out, wide_out, did_init_out, + // Inputs + clk, bit_in, vec_in, wide_in, is_ref + ); + + input clk; + input bit_in; + output bit_out; + input [30:0] vec_in; + output [30:0] vec_out; + input [123:0] wide_in; + output [123:0] wide_out; + output did_init_out; + + input is_ref; + + reg did_init; initial did_init = 0; + initial begin + did_init = 1; + end + + reg did_final; initial did_final = 0; + final begin + did_final = 1; + if (!is_ref) $write("*-* All Finished *-*\n"); + //$finish is in parent + end + + // Note async use! + wire bit_out = bit_in; + wire did_init_out = did_init; + + always @ (posedge clk) begin + vec_out <= vec_in; + wide_out <= wide_in; + end + +endmodule diff --git a/test_regress/t/t_embed1_wrap.v b/test_regress/t/t_embed1_wrap.v new file mode 100644 index 000000000..9be795fa9 --- /dev/null +++ b/test_regress/t/t_embed1_wrap.v @@ -0,0 +1,90 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2011 by Wilson Snyder. + +module t_embed1_wrap (/*AUTOARG*/ + // Outputs + bit_out, vec_out, wide_out, did_init_out, + // Inputs + clk, bit_in, vec_in, wide_in, is_ref + ); + + /*AUTOINOUTMODULE("t_embed1_child")*/ + // Beginning of automatic in/out/inouts (from specific module) + output bit_out; + output [30:0] vec_out; + output [123:0] wide_out; + output did_init_out; + input clk; + input bit_in; + input [30:0] vec_in; + input [123:0] wide_in; + input is_ref; + // End of automatics + +`ifdef verilator + // Import $t_embed_child__initial etc as a DPI function +`endif + + //TODO would like __'s as in {PREFIX}__initial but presently illegal for users to do this + import "DPI-C" context function void t_embed_child_initial(); + import "DPI-C" context function void t_embed_child_final(); + import "DPI-C" context function void t_embed_child_eval(); + import "DPI-C" context function void t_embed_child_io_eval + ( + //TODO we support bit, but not logic + input bit clk, + input bit bit_in, + input bit [30:0] vec_in, + input bit [123:0] wide_in, + input bit is_ref, + output bit bit_out, + output bit [30:0] vec_out, + output bit [123:0] wide_out, + output bit did_init_out); + + initial begin + // Load all values + t_embed_child_initial(); + end + + // Only if system verilog, and if a "final" block in the code + final begin + t_embed_child_final(); + end + + bit _temp_bit_out; + bit _temp_did_init_out; + bit [30:0] _temp_vec_out; + bit [123:0] _temp_wide_out; + always @* begin + t_embed_child_io_eval( + clk, + bit_in, + vec_in, + wide_in, + is_ref, + _temp_bit_out, + _temp_vec_out, + _temp_wide_out, + _temp_did_init_out + ); + // TODO might eliminate these temporaries + bit_out = _temp_bit_out; + did_init_out = _temp_did_init_out; + end + + + // Send all variables every cycle, + // or have a sensitivity routine for each? + // How to make sure we call eval at end of variable changes? + // #0 (though not verilator compatible!) + + // TODO for now, we know what changes when + always @ (posedge clk) begin + vec_out <= _temp_vec_out; + wide_out <= _temp_wide_out; + end + +endmodule