From cb7b024e8fd8c0c675926d11321d2c234b8d4c8a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 16 Oct 2022 11:10:41 -0400 Subject: [PATCH] Commentary: Spelling, and add upgrade notes (#3462) --- Changes | 24 +++++++++++++++--------- docs/guide/connecting.rst | 2 +- docs/guide/exe_verilator.rst | 2 +- docs/guide/files.rst | 2 +- docs/guide/warnings.rst | 2 +- docs/spelling.txt | 17 +++++++++++++++++ 6 files changed, 36 insertions(+), 13 deletions(-) diff --git a/Changes b/Changes index 270e8890f..1d06c5041 100644 --- a/Changes +++ b/Changes @@ -14,14 +14,20 @@ Verilator 5.001 devel **Major:** * This is a major new release. -* Fully support the Active and NBA scheduling regions as defined by the +* Require C++20 for the new --timing features. Upgrading to a C++20 or + newer compiler is strongly recommended. +* Support the Active and NBA scheduling regions as defined by the SystemVerilog standard (IEEE 1800-2017 chapter 4). This means all generated clocks are now simulated correctly (#3278, #3384). [Geza Lore, Shunyao CAD] * Support timing controls (delays, event controls in any location, wait - statements) and forks. See docs for details. [Krzysztof Bieganski, Antmicro Ltd] + statements) and forks. [Krzysztof Bieganski, Antmicro Ltd] + This may require adding --timing or --no-timing. See docs for details. * Introduce a new combinational logic optimizer (DFG), that can yield significant performance improvements on some designs. [Geza Lore, Shunyao CAD] * Add --binary option as alias of --main --exe --build --timing (#3625). + For designs where C++ was only used to make a simple testbench we + recommend abandoning that C++, and instead letting Verilator build it + with --binary (or --main). **Minor:** @@ -39,7 +45,7 @@ Verilator 4.228 2022-10-01 **Announcement:** -* The next release is anticipated primere Verilator Version 5. Please +* The next release is anticipated to premiere Verilator Version 5. Please consider beta-testing the github 'develop-v5' branch, which will soon merge into the github 'master' branch (#3383). @@ -50,12 +56,12 @@ Verilator 4.228 2022-10-01 * Add --build-jobs, and rework arguments for -j (#3623). [Kamil Rakoczy] * Rename --bin to --build-dep-bin. * Rename debug flags --dumpi-tree, --dumpi-graph, etc. [Geza Lore] -* Fix thread saftey in SystemC VL_ASSIGN_SBW/WSB (#3494) (#3513). [Mladen Slijepcevic] +* Fix thread safety in SystemC VL_ASSIGN_SBW/WSB (#3494) (#3513). [Mladen Slijepcevic] * Fix crash in gate optimization of circular logic (#3543). [Bill Flynn] * Fix arguments in non-static method call (#3547) (#3582). [Gustav Svensk] * Fix default --mod-prefix when --prefix is repeated (#3603). [Geza Lore] * Fix calling trace() after open() segfault (#3610) (#3627). [Yu-Sheng Lin] -* Fix typedef'ed class conversion to boolean (#3616). [Aleksander Kiryk] +* Fix typedef'ed class conversion to Boolean (#3616). [Aleksander Kiryk] * Fix Verilation speed when disabled warnings (#3632). [Kamil Rakoczy, Antmicro Ltd] @@ -79,17 +85,17 @@ Verilator 4.226 2022-08-31 * Fix bisonpre for MSYS2 (#3471). * Fix max memory usage (#3483). [Kamil Rakoczy, Antmicro Ltd] * Fix empty string arguments to display (#3484). [Grulfen] -* Fix table misoptimizing away display (#3488). [Stefan Post] +* Fix table optimizing away display (#3488). [Stefan Post] * Fix unique_ptr memory header for MinGW64 (#3493). -* Fix $dump systemtask with --output-split-cfuncs (#3495) (#3497). [Varun Koyyalagunta] +* Fix $dump system task with --output-split-cfuncs (#3495) (#3497). [Varun Koyyalagunta] * Fix wrong bit op tree optimization (#3509). [Nathan Graybeal] * Fix nested default assignment for struct pattern (#3511) (#3524). [Mostafa Gamal] * Fix sformat string incorrectly cleared (#3515) (#3519). [Gustav Svensk] -* Fix segfault exporting non-existant package (#3535). +* Fix segfault exporting non-existent package (#3535). * Fix void-cast queue pop_front or pop_back (#3542) (#3364). [Drew Ranck] * Fix case statement comparing string literal (#3544). [Gustav Svensk] * Fix === with some tristate constants (#3551). [Ryszard Rozak, Antmicro Ltd] -* Fix converting subclasses to string (#3552). [Arkadiusz Kozdra, Antmicro Ltd] +* Fix converting classes to string (#3552). [Arkadiusz Kozdra, Antmicro Ltd] * Fix --hierarchical with order-based pin connections (#3583) (#3585). [Kelin9298] diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst index 876f15487..638f5c33d 100644 --- a/docs/guide/connecting.rst +++ b/docs/guide/connecting.rst @@ -447,7 +447,7 @@ wrapper which calls these two functions. the user should call: * :code:`designp->eventsPending()`, which returns :code:`true` if there are - any delayed events penging, + any delayed events pending, * :code:`designp->nextTimeSlot()`, which returns the simulation time of the next delayed event. This method can only be called if :code:`designp->nextTimeSlot()` returned :code:`true`. diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 4b1e0a458..786b1d275 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -522,7 +522,7 @@ Summary: .. option:: -fno-dfg-peephole- - Disable individula DFG peephole optimizer pattern. + Disable individual DFG peephole optimizer pattern. .. option:: -fno-dfg-pre-inline diff --git a/docs/guide/files.rst b/docs/guide/files.rst index a71214983..2b797c62a 100644 --- a/docs/guide/files.rst +++ b/docs/guide/files.rst @@ -93,7 +93,7 @@ For --cc/--sc, it creates: * - *{prefix}{each_verilog_module}{__n}*\ .cpp - Additional lower C++ files * - *{prefix}{each_verilog_module}{__DepSet_hash__n}*\ .cpp - - Additional lower C++ files (hased to reduce build times) + - Additional lower C++ files (hashed to reduce build times) For --hierarchy mode, it creates: diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 1da3907b6..508b381bd 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -327,7 +327,7 @@ List Of Warnings The warning could be disabled without affecting the simulation result. But it was recommended to check the warning as it may have - degrated the performance of the Verilated model. + degraded the performance of the Verilated model. .. option:: CMPCONST diff --git a/docs/spelling.txt b/docs/spelling.txt index 0e423ba26..3e1b7e7d3 100644 --- a/docs/spelling.txt +++ b/docs/spelling.txt @@ -7,12 +7,14 @@ Ami Amir Anastasiadis Anikin +Antmicro Antonin Antwerpen Arasanipalai Arjen Asciidoc Ashutosh +Ast Atmel Aurelien Bagri @@ -108,8 +110,10 @@ Goessling Gonnen Goorah Gossner +Graphviz Graybeal Grobman +Grulfen Gunter Guo Hao @@ -131,6 +135,7 @@ Iles Inlines Inout Iru +Iyer Iztok Jacko Jae @@ -157,6 +162,7 @@ Karge Karlsson Katz Katzman +Kelin Keren Keyi Kimmitt @@ -340,6 +346,7 @@ Verilating Verilation Verilator Verilog +Vighnesh Viktor Vm Vukobratovic @@ -376,6 +383,7 @@ agrobman ahouska al ala +algrobman andit ar architected @@ -397,6 +405,7 @@ bbox benchmarking biguint biops +bisonpre bitOpTree bitOpTree bitop @@ -441,6 +450,7 @@ const constexpr constpool coredump +coroutine countbits countones cout @@ -463,6 +473,7 @@ defenv defname defparam demangling +dep der dereference desassign @@ -480,6 +491,7 @@ dsvf dtor dumpall dumpfile +dumpi dumplimit dumpoff dumpon @@ -537,6 +549,7 @@ filesystem filt flto flushCall +fno fopen forceable foreach @@ -600,6 +613,7 @@ inouts inserted instantiation instantiations +intra iostream ish isunbounded @@ -725,6 +739,7 @@ profiler prototyptes ps pthread +ptr pulldown pulldowns pullup @@ -750,6 +765,7 @@ reloop resetall respecified rodata +rolloverSize rr rst runtime @@ -764,6 +780,7 @@ seg setuphold sformat sformatf +shareefj shortint shortreal signame