diff --git a/src/verilog.y b/src/verilog.y index bc09282af..0f8c1e417 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -2226,10 +2226,11 @@ data_typeNoRef: // ==IEEE: data_type, excluding class_ty new AstDefImplicitDType{$1->fileline(), "__typeimpsu" + cvtToStr(GRAMMARP->s_typeImpNum++), VFlagChildDType{}, $1}, $2, true); } - | enumDecl - { $$ = new AstDefImplicitDType{$1->fileline(), - "__typeimpenum" + cvtToStr(GRAMMARP->s_typeImpNum++), - VFlagChildDType{}, $1}; } + | enumDecl packed_dimensionListE + { $$ = GRAMMARP->createArray( + new AstDefImplicitDType{$1->fileline(), + "__typeimpenum" + cvtToStr(GRAMMARP->s_typeImpNum++), + VFlagChildDType{}, $1}, $2, true); } | ySTRING { $$ = new AstBasicDType{$1, VBasicDTypeKwd::STRING}; } | yCHANDLE diff --git a/test_regress/t/t_enum.v b/test_regress/t/t_enum.v index 887866a37..1a4db38b8 100644 --- a/test_regress/t/t_enum.v +++ b/test_regress/t/t_enum.v @@ -47,6 +47,10 @@ module t (/*AUTOARG*/); var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2}, QPR={2'b0,2'h3 }, QACK, QRSP } inv; + enum logic [7:0] { + ENARRAY = 6 + } [3:2] enarray; + initial begin if (e0 !== 0) $stop; if (e1 !== 1) $stop; @@ -86,6 +90,11 @@ module t (/*AUTOARG*/); if ($size(array5) != 5) $stop; if ($size(array5i) != 5) $stop; + enarray[2] = ENARRAY; + enarray[3] = ENARRAY; + if (enarray[2] !== ENARRAY) $stop; + if (enarray[3] !== ENARRAY) $stop; + $write("*-* All Finished *-*\n"); $finish; end