From ca4e7ff92f29e8441982057f549926ca0ada2733 Mon Sep 17 00:00:00 2001
From: Yilou Wang <wangyilou123@gmail.com>
Date: Wed, 17 Jun 2026 12:00:30 +0200
Subject: [PATCH] refine test name and format

---
 test_regress/t/t_assert_seq_clocking.v               |  8 +++-----
 ...cking_bad.out => t_assert_seq_clocking_unsup.out} |  0
 ...locking_bad.py => t_assert_seq_clocking_unsup.py} |  0
 ..._clocking_bad.v => t_assert_seq_clocking_unsup.v} | 12 ++++--------
 4 files changed, 7 insertions(+), 13 deletions(-)
 rename test_regress/t/{t_assert_seq_clocking_bad.out => t_assert_seq_clocking_unsup.out} (100%)
 rename test_regress/t/{t_assert_seq_clocking_bad.py => t_assert_seq_clocking_unsup.py} (100%)
 rename test_regress/t/{t_assert_seq_clocking_bad.v => t_assert_seq_clocking_unsup.v} (67%)

diff --git a/test_regress/t/t_assert_seq_clocking.v b/test_regress/t/t_assert_seq_clocking.v
index ea7cb8698..f5b4be4b3 100644
--- a/test_regress/t/t_assert_seq_clocking.v
+++ b/test_regress/t/t_assert_seq_clocking.v
@@ -4,9 +4,8 @@
 // SPDX-FileCopyrightText: 2026 PlanV GmbH
 // SPDX-License-Identifier: CC0-1.0
 
-// verilog_format: off
 module t (
-    input clk
+  input clk
 );
   int unsigned crc = 32'h1;
   bit a, b;
@@ -14,20 +13,19 @@ module t (
   int fails_single = 0;
   int fails_multi = 0;
 
-  // Single-cycle clocked sequence body (IEEE 1800-2023 16.7).
+  // verilog_format: off  // verible does not support clocking events inside sequence declarations
   sequence s_single;
     @(posedge clk) a;
   endsequence
 
-  // Multi-cycle clocked sequence body.
   sequence s_multi;
     @(posedge clk) (a ##1 b);
   endsequence
 
-  // Declared but never referenced; must not reach codegen.
   sequence s_unused;
     @(posedge clk) b;
   endsequence
+  // verilog_format: on
 
   ap_single: assert property (s_single) else fails_single = fails_single + 1;
   ap_multi: assert property (s_multi) else fails_multi = fails_multi + 1;
diff --git a/test_regress/t/t_assert_seq_clocking_bad.out b/test_regress/t/t_assert_seq_clocking_unsup.out
similarity index 100%
rename from test_regress/t/t_assert_seq_clocking_bad.out
rename to test_regress/t/t_assert_seq_clocking_unsup.out
diff --git a/test_regress/t/t_assert_seq_clocking_bad.py b/test_regress/t/t_assert_seq_clocking_unsup.py
similarity index 100%
rename from test_regress/t/t_assert_seq_clocking_bad.py
rename to test_regress/t/t_assert_seq_clocking_unsup.py
diff --git a/test_regress/t/t_assert_seq_clocking_bad.v b/test_regress/t/t_assert_seq_clocking_unsup.v
similarity index 67%
rename from test_regress/t/t_assert_seq_clocking_bad.v
rename to test_regress/t/t_assert_seq_clocking_unsup.v
index 3c41045ac..5d092ea66 100644
--- a/test_regress/t/t_assert_seq_clocking_bad.v
+++ b/test_regress/t/t_assert_seq_clocking_unsup.v
@@ -4,13 +4,13 @@
 // SPDX-FileCopyrightText: 2026 PlanV GmbH
 // SPDX-License-Identifier: CC0-1.0
 
-// verilog_format: off
 module t (
-    input clk,
-    input clk2
+  input clk,
+  input clk2
 );
   logic a, b;
 
+  // verilog_format: off
   sequence s_multi;
     @(posedge clk) a;
   endsequence
@@ -22,14 +22,10 @@ module t (
   sequence s_level;
     @clk a;
   endsequence
+  // verilog_format: on
 
-  // Multiclocked: explicit assertion clock differs from the sequence clock.
   assert property (@(posedge clk2) s_multi);
-
-  // Clocking event nested inside a larger sequence expression.
   assert property (s_nest ##1 a);
-
-  // Non-edge clocking event on a sequence.
   assert property (s_level);
 
 endmodule