From c9e021924f56e958d21322f6c955765464ce0410 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 25 Sep 2025 06:52:42 -0400 Subject: [PATCH] Support class package reference on pattern keys (#5653). --- Changes | 1 + src/V3Width.cpp | 1 + src/verilog.y | 3 + ...unsup.py => t_param_pattern_init_scope.py} | 6 +- test_regress/t/t_param_pattern_init_scope.v | 55 +++++++++++++++++++ .../t/t_scoped_param_pattern_init_unsup.out | 5 -- .../t/t_scoped_param_pattern_init_unsup.v | 50 ----------------- 7 files changed, 64 insertions(+), 57 deletions(-) rename test_regress/t/{t_scoped_param_pattern_init_unsup.py => t_param_pattern_init_scope.py} (75%) create mode 100644 test_regress/t/t_param_pattern_init_scope.v delete mode 100644 test_regress/t/t_scoped_param_pattern_init_unsup.out delete mode 100644 test_regress/t/t_scoped_param_pattern_init_unsup.v diff --git a/Changes b/Changes index 010e972a2..b187d35f3 100644 --- a/Changes +++ b/Changes @@ -25,6 +25,7 @@ Verilator 5.041 devel * Deprecate sensitivity list on public_flat_rw attributes (#6443). [Geza Lore] * Deprecate clocker attribute and --clk option (#6463). [Geza Lore] * Support modports referencing clocking blocks (#4555) (#6436). [Ryszard Rozak, Antmicro Ltd.] +* Support class package reference on pattern keys (#5653). [Todd Strader] * Support digits in `$sscanf` field width formats (#6083). [Iztok Jeras] * Support pure functions in sensitivity lists (#6393). [Krzysztof Bieganski, Antmicro Ltd.] * Improve automatic selection of logic for DFG synthesis (#6370). [Geza Lore] diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 536109c32..c5aeef58a 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -8582,6 +8582,7 @@ class WidthVisitor final : public VNVisitor { for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp; patp = VN_AS(patp->nextp(), PatMember)) { if (patp->keyp()) { + V3Const::constifyParamsNoWarnEdit(patp->keyp()); if (patp->varrefp()) V3Const::constifyParamsEdit(patp->varrefp()); if (const AstConst* const constp = VN_CAST(patp->keyp(), Const)) { element = constp->toSInt(); diff --git a/src/verilog.y b/src/verilog.y index 1fe51788c..e2379830c 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -3915,6 +3915,9 @@ patternKey: // IEEE: merge structure_pattern_key, array_patt { $$ = $1; } // // expanded from simple_type ps_type_identifier (part of simple_type) // // expanded from simple_type ps_parameter_identifier (part of simple_type) + | packageClassScope id + { $$ = AstDot::newIfPkg($1, $1, + new AstParseRef{$2, VParseRefExp::PX_TEXT, *$2, nullptr, nullptr}); } | packageClassScopeE idType { AstRefDType* const refp = new AstRefDType{$2, *$2, $1, nullptr}; $$ = refp; } diff --git a/test_regress/t/t_scoped_param_pattern_init_unsup.py b/test_regress/t/t_param_pattern_init_scope.py similarity index 75% rename from test_regress/t/t_scoped_param_pattern_init_unsup.py rename to test_regress/t/t_param_pattern_init_scope.py index efe8cc01c..f989a35fb 100755 --- a/test_regress/t/t_scoped_param_pattern_init_unsup.py +++ b/test_regress/t/t_param_pattern_init_scope.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2024 by Wilson Snyder. This program is free software; you +# Copyright 2025 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. @@ -11,6 +11,8 @@ import vltest_bootstrap test.scenarios('simulator') -test.lint(fails=True, expect_filename=test.golden_filename) +test.compile() + +test.execute() test.passes() diff --git a/test_regress/t/t_param_pattern_init_scope.v b/test_regress/t/t_param_pattern_init_scope.v new file mode 100644 index 000000000..455133c8a --- /dev/null +++ b/test_regress/t/t_param_pattern_init_scope.v @@ -0,0 +1,55 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +package some_pkg; + localparam FOO = 5; + localparam BAR = 6; + + typedef enum int {QUX = 7} pkg_enum_t; +endpackage + +module t ( + input clk +); + + int cyc = 0; + + logic [31:0] package_array[8]; + + always_comb + package_array = '{ + 1: 32'h1111, + some_pkg::FOO: 32'h9876, + some_pkg::BAR: 32'h1212, + some_pkg::QUX: 32'h5432, + default: 0 + }; + + always @(posedge clk) begin + `checkh(package_array[0], 32'h0); + `checkh(package_array[1], 32'h1111); + `checkh(package_array[2], 32'h0); + `checkh(package_array[3], 32'h0); + `checkh(package_array[4], 32'h0); + `checkh(package_array[5], 32'h9876); + `checkh(package_array[6], 32'h1212); + `checkh(package_array[7], 32'h5432); + end + + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 2) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_scoped_param_pattern_init_unsup.out b/test_regress/t/t_scoped_param_pattern_init_unsup.out deleted file mode 100644 index 9fd2efc85..000000000 --- a/test_regress/t/t_scoped_param_pattern_init_unsup.out +++ /dev/null @@ -1,5 +0,0 @@ -%Error: t/t_scoped_param_pattern_init_unsup.v:30:22: syntax error, unexpected ':', expecting ',' or '}' - 30 | some_pkg::FOO: 32'h9876, - | ^ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: Exiting due to diff --git a/test_regress/t/t_scoped_param_pattern_init_unsup.v b/test_regress/t/t_scoped_param_pattern_init_unsup.v deleted file mode 100644 index ebaa9cd89..000000000 --- a/test_regress/t/t_scoped_param_pattern_init_unsup.v +++ /dev/null @@ -1,50 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under the Creative Commons Public Domain, for -// any use, without warranty, 2010 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -`define stop $stop -`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); - -package some_pkg; - localparam FOO = 5; - localparam BAR = 6; - - typedef enum int { - QUX = 7 - } pkg_enum_t; -endpackage - -module t (/*AUTOARG*/ - // Inputs - clk - ); - - input clk; - int cyc = 0; - - logic [31:0] package_array [8]; - - always_comb package_array = '{ - some_pkg::FOO: 32'h9876, - some_pkg::BAR: 32'h1212, - some_pkg::QUX: 32'h5432, - default: 0 - }; - - always_ff @(posedge clk) begin - `checkh(package_array[5], 32'h9876); - `checkh(package_array[6], 32'h1212); - `checkh(package_array[7], 32'h5432); - end - - always_ff @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 2) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - -endmodule