diff --git a/Changes b/Changes
index f1ffba38f..5a441de4c 100644
--- a/Changes
+++ b/Changes
@@ -10,6 +10,8 @@ indicates the contributor was also the author of the fix; Thanks!
       Verilated models.  This may affect packed arrays that are public or
       accessed via the VPI.
 
+***   Support wires with data types, bug608. [Ed Lander]
+
 ***   Support bind, to module names only, bug602. [Ed Lander]
 
 ***   Support VPI product info, warning calls, etc, bug588. [Rick Porter]
diff --git a/src/verilog.y b/src/verilog.y
index fb6c82e4a..4ed264996 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1042,13 +1042,30 @@ net_declaration<nodep>:		// IEEE: net_declaration - excluding implict
 	;
 
 net_declarationFront:		// IEEE: beginning of net_declaration
-		net_declRESET net_type   strengthSpecE signingE delayrange { VARDTYPE($5); $5->basicp()->setSignedState($4); }
+		net_declRESET net_type   strengthSpecE net_scalaredE net_dataType { VARDTYPE($5); }
 	;
 
 net_declRESET:
 		/* empty */ 				{ VARRESET_NONLIST(UNKNOWN); }
 	;
 
+net_scalaredE:
+		/* empty */ 				{ }
+	//UNSUP: ySCALARED/yVECTORED ignored
+	|	ySCALARED			 	{ }
+	|	yVECTORED				{ }
+	;
+
+net_dataType<dtypep>:
+	//			// If there's a SV data type there shouldn't be a delay on this wire
+	//			// Otherwise #(...) can't be determined to be a delay or parameters
+	//			// Submit this as a footnote to the committee
+		var_data_type	 			{ $$ = $1; }
+	|	signingE rangeList delayE 		{ $$ = GRAMMARP->addRange(new AstBasicDType($2->fileline(), LOGIC, $1),$2,true); }  // not implicit
+	|	signing					{ $$ = new AstBasicDType($<fl>1, LOGIC, $1); }  // not implicit
+	|	/*implicit*/ delayE 			{ $$ = new AstBasicDType(CRELINE(), LOGIC); }  // not implicit
+	;
+
 net_type:			// ==IEEE: net_type
 		ySUPPLY0				{ VARDECL(SUPPLY0); }
 	|	ySUPPLY1				{ VARDECL(SUPPLY1); }
@@ -1217,11 +1234,17 @@ data_typeNoRef<dtypep>:		// ==IEEE: data_type, excluding class_type etc referenc
 	//			// IEEE: ps_covergroup: see data_type above
 	;
 
-data_type_or_void<dtypep>:		// ==IEEE: data_type_or_void
-		data_type				{ $$=$1; }
+data_type_or_void<dtypep>:	// ==IEEE: data_type_or_void
+		data_type				{ $$ = $1; }
 	//UNSUP	yVOID					{ UNSUP }	// No yTAGGED structures
 	;
 
+var_data_type<dtypep>:		// ==IEEE: var_data_type
+		data_type				{ $$ = $1; }
+	|	yVAR data_type				{ $$ = $2; }
+	|	yVAR implicit_typeE			{ $$ = $2; }
+	;
+
 struct_unionDecl<classp>:	// IEEE: part of data_type
 	//			// packedSigningE is NOP for unpacked
 		ySTRUCT        packedSigningE '{' 	{ $<classp>$ = new AstStructDType($1, $2); SYMP->pushNew($<classp>$); }
@@ -1800,11 +1823,6 @@ rangeList<rangep>:		// IEEE: {packed_dimension}
         |	rangeList anyrange			{ $$ = $1; $1->addNext($2); }
 	;
 
-wirerangeE<dtypep>:
-		/* empty */    		               	{ $$ = new AstBasicDType(CRELINE(), LOGIC); }  // not implicit
-	|	rangeList 				{ $$ = GRAMMARP->addRange(new AstBasicDType($1->fileline(), LOGIC),$1,true); }  // not implicit
-	;
-
 // IEEE: select
 // Merged into more general idArray
 
@@ -1827,13 +1845,6 @@ packed_dimension<rangep>:	// ==IEEE: packed_dimension
 	//UNSUP	'[' ']'					{ UNSUP }
 	;
 
-delayrange<dtypep>:
-		wirerangeE delayE 			{ $$ = $1; }
-	|	ySCALARED wirerangeE delayE 		{ $$ = $2; }
-	|	yVECTORED wirerangeE delayE 		{ $$ = $2; }
-	//UNSUP: ySCALARED/yVECTORED ignored
-	;
-
 //************************************************
 // Parameters
 
diff --git a/test_regress/t/t_wire_types.pl b/test_regress/t/t_wire_types.pl
new file mode 100755
index 000000000..3deae9536
--- /dev/null
+++ b/test_regress/t/t_wire_types.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{verilated_randReset} = 1;  # allow checking if we initialize vars to zero only when needed
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_wire_types.v b/test_regress/t/t_wire_types.v
new file mode 100644
index 000000000..7145c3591
--- /dev/null
+++ b/test_regress/t/t_wire_types.v
@@ -0,0 +1,61 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d:  got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got=%g exp=%g\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
+
+   // IEEE: integer_atom_type
+   wire byte	w_byte;
+   wire shortint w_shortint;
+   wire int	w_int;
+   wire longint	w_longint;
+   wire integer	w_integer;
+
+   // IEEE: integer_atom_type
+   wire bit	w_bit;
+   wire logic	w_logic;
+
+   wire bit [1:0] 	w_bit2;
+   wire logic  [1:0]	w_logic2;
+
+   // IEEE: non_integer_type
+   //UNSUP shortreal	w_shortreal;
+   wire real		w_real;
+
+   assign w_byte = 8'h12;
+   assign w_shortint = 16'h1234;
+   assign w_int = -123456;
+   assign w_longint = -1234567;
+   assign w_integer = -123456;
+
+   assign w_bit = 1'b1;
+   assign w_logic = 1'b1;
+
+   assign w_bit2 = 2'b10;
+   assign w_logic2 = 2'b10;
+
+   assign w_real = 3.14;
+
+   always @ (posedge clk) begin
+      `checkh(w_byte, 8'h12);
+      `checkh(w_shortint, 16'h1234);
+      `checkh(w_int, -123456);
+      `checkh(w_longint, -1234567);
+      `checkh(w_integer, -123456);
+      `checkh(w_bit, 1'b1);
+      `checkh(w_logic, 1'b1);
+      `checkh(w_bit2, 2'b10);
+      `checkh(w_logic2, 2'b10);
+      `checkr(w_real, 3.14);
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule