diff --git a/Changes b/Changes index 9c06d0728..9b127722c 100644 --- a/Changes +++ b/Changes @@ -9,6 +9,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix little endian interface pin swizzling (#2475). [Don Owen] +**** Fix range inheritance on port without data type (#2753). [Embedded Go] + **** Fix TIMESCALE warnings on primitives (#2763). [Xuanqi] **** Fix $fread extra semicolon inside statements. [Leendert van Doorn] diff --git a/src/verilog.y b/src/verilog.y index d11620541..e887c3a3d 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1380,9 +1380,9 @@ portDirNetE: // IEEE: part of port, optional net type and/or direction /* empty */ { } // // Per spec, if direction given default the nettype. // // The higher level rule may override this VARDTYPE with one later in the parse. - | port_direction { VARDECL(PORT); VARDTYPE_NDECL(nullptr/*default_nettype*/); } - | port_direction { VARDECL(PORT); } net_type { VARDTYPE_NDECL(nullptr/*default_nettype*/); } // net_type calls VARDECL - | net_type { } // net_type calls VARDECL + | port_direction { VARDECL(PORT); VARDTYPE_NDECL(nullptr); } + | port_direction { VARDECL(PORT); } net_type { VARDTYPE_NDECL(nullptr); } // net_type calls VARDECL + | net_type { VARDTYPE_NDECL(nullptr); } // net_type calls VARDECL ; port_declNetE: // IEEE: part of port_declaration, optional net type diff --git a/test_regress/t/t_var_port_xml.out b/test_regress/t/t_var_port_xml.out new file mode 100644 index 000000000..b2e6f9f4f --- /dev/null +++ b/test_regress/t/t_var_port_xml.out @@ -0,0 +1,129 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/test_regress/t/t_var_port_xml.pl b/test_regress/t/t_var_port_xml.pl new file mode 100755 index 000000000..acd3ab33d --- /dev/null +++ b/test_regress/t/t_var_port_xml.pl @@ -0,0 +1,25 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2012 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; + +compile( + verilator_flags2 => ['--xml-only'], + verilator_make_gmake => 0, + make_top_shell => 0, + make_main => 0, + ); + +files_identical($out_filename, $Self->{golden_filename}); + +ok(1); +1; diff --git a/test_regress/t/t_var_port_xml.v b/test_regress/t/t_var_port_xml.v new file mode 100644 index 000000000..88418b19c --- /dev/null +++ b/test_regress/t/t_var_port_xml.v @@ -0,0 +1,59 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// This checks IEEE ports work correctly, we use XML output to make it easy to +// see all attributes are propagated + +// verilator lint_off MULTITOP + +`ifndef VERILATOR +module mh0 (wire x_inout_wire_logic); +endmodule +module mh1 (integer x_inout_wire_integer); +endmodule +`endif +module mh2 (inout integer x_inout_wire_integer); +endmodule +`ifndef VERILATOR +module mh3 ([5:0] x_inout_wire_logic_p6); +endmodule +`endif +module mh5 (input x_input_wire_logic); +endmodule +module mh6 (input var x_input_var_logic); +endmodule +module mh7 (input var integer x_input_var_integer); +endmodule +module mh8 (output x_output_wire_logic); +endmodule +module mh9 (output var x_output_var_logic); +endmodule +module mh10(output signed [5:0] x_output_wire_logic_signed_p6); +endmodule +module mh11(output integer x_output_var_integer); +endmodule +module mh12(ref [5:0] x_ref_logic_p6); +endmodule +module mh13(ref x_ref_var_logic_u6 [5:0]); +endmodule +`ifndef VERILATOR +module mh14(wire x_inout_wire_logic, y_inout_wire_logic_p8 [7:0]); +endmodule +module mh15(integer x_inout_wire_integer, signed [5:0] y_inout_wire_logic_signed6); +endmodule +module mh16([5:0] x_inout_wire_logic_p6, wire y_inout_wire_logic); +endmodule +`endif +module mh17(input var integer x_input_var_integer, wire y_input_wire_logic); +endmodule +module mh18(output var x_output_var_logic, input y_input_wire_logic); +endmodule +module mh19(output signed [5:0] x_output_wire_logic_signed_p6, integer y_output_var_integer); +endmodule +module mh20(ref [5:0] x_ref_var_logic_p6, y_ref_var_logic_p6); +endmodule +module mh21(ref ref_var_logic_u6 [5:0], y_ref_var_logic); +endmodule