diff --git a/Changes b/Changes
index 9877ca716..afe5731e2 100644
--- a/Changes
+++ b/Changes
@@ -66,6 +66,8 @@ Verilator 5.049 devel
 * Support `s_until` and `s_until_with`(#7722). [Artur Bieniek, Antmicro Ltd.]
 * Support covergroup runtime model Phase A1 (#7728). [Matthew Ballance]
 * Support reduction XOR/AND operations in constraints (#7753). [Kornel Uriasz, Antmicro Ltd.]
+* Support assertion control system tasks in classes and interfaces (#7761). [Yilou Wang]
+* Support cover sequence statement (#7764). [Yilou Wang]
 * Support unpacked struct stream (#7767). [Nick Brereton]
 * Optimize emitting to_string() for compiler speedup (#7468). [Jakub Michalski, Antmicro Ltd.]
 * Optimize additional DFG peephole cases (#7553). [Varun Koyyalagunta, Testorrent USA, Inc.]
@@ -86,6 +88,7 @@ Verilator 5.049 devel
 * Optimize bit select removal earlier in DFG (#7762). [Geza Lore, Testorrent USA, Inc.]
 * Optimize away proven redundant case statement assertions (#7771). [Geza Lore, Testorrent USA, Inc.]
 * Optimize table lookups in DFG (#7772). [Geza Lore, Testorrent USA, Inc.]
+* Optimize input combinational logic by change detection (#7784). [Geza Lore, Testorrent USA, Inc.]
 * Fix TSP variable ordering for mtasks (#5342) (#7610). [Muzaffer Kal]
 * Fix inlining static initializer in V3Gate (#5381) (#7503). [Andrew Nolte] [Geza Lore, Testorrent USA, Inc.]
 * Fix timed nested fork block with disable (#6720) (#7743). [Marco Bartoli]
@@ -161,6 +164,7 @@ Verilator 5.049 devel
 * Fix FSM detect unchecked casts and variable redeclaration (#7758). [Adam Kostrzewski, Antmicro Ltd.]
 * Fix no-scope internal error on virtual interface method calls (#7759). [Yilou Wang]
 * Fix 'case (_) inside' with x wildcards (#7766). [Geza Lore, Testorrent USA, Inc.]
+* Fix not failing assertion when RHS of a range window rejects once (#7773). [Artur Bieniek, Antmicro Ltd.]
 * Fix $fflush and autoflush with --threads (#7782).
 
 
diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst
index 73ed42486..29e3876c4 100644
--- a/docs/guide/exe_verilator.rst
+++ b/docs/guide/exe_verilator.rst
@@ -750,7 +750,7 @@ Summary:
    for top level input signals that are written within the design. Accesses via
    the VPI cannot be analyzed at compile time, therefore :vlopt:`--vpi`
    disables this optimization for all inputs; it may be turned back on by
-   explicitly passing :vlopt:`-fico-change-detect`.
+   explicitly passing :vlopt:`-fico-change-detect <-fno-ico-change-detect>`.
 
 .. option:: -fno-inline
 
diff --git a/docs/spelling.txt b/docs/spelling.txt
index c41825793..a21f66ed5 100644
--- a/docs/spelling.txt
+++ b/docs/spelling.txt
@@ -861,6 +861,7 @@ hx
 hyperthreading
 hyperthreads
 icecream
+ico
 idmap
 ifdef
 ifdefed
diff --git a/test_regress/t/t_sched_ico_change_detect_input_assigned.v b/test_regress/t/t_sched_ico_change_detect_input_assigned.v
index 0f6f9025d..9a4f79b0b 100644
--- a/test_regress/t/t_sched_ico_change_detect_input_assigned.v
+++ b/test_regress/t/t_sched_ico_change_detect_input_assigned.v
@@ -10,20 +10,23 @@
 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d:  got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
 // verilog_format: on
 
-module t(
-  clk, i, o, cyc
+module t (
+    clk,
+    i,
+    o,
+    cyc
 );
 
   input clk, i;
   output o, cyc;
 
-  logic   clk;
-  int     i; // Primary input that the design also drives
-  int     o;
-  int     cyc = 0;
+  logic clk;
+  int i;  // Primary input that the design also drives
+  int o;
+  int cyc = 0;
 
   // Logic dependent on primary input 'i'
-  always_comb  o = i + 10;
+  always_comb o = i + 10;
 
   always @(posedge clk) begin
     cyc <= cyc + 1;