From c5fd583b2c6534409f5539a3dadc079a0fc6b03a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 9 Nov 2014 18:29:52 -0500 Subject: [PATCH] Fix select when partially out-of-bound, bug823. --- Changes | 2 + src/V3Unknown.cpp | 10 ++-- test_regress/t/t_select_bound1.pl | 18 ++++++ test_regress/t/t_select_bound1.v | 91 +++++++++++++++++++++++++++++++ test_regress/t/t_select_bound2.pl | 18 ++++++ test_regress/t/t_select_bound2.v | 91 +++++++++++++++++++++++++++++++ test_regress/t/t_select_plus.v | 2 +- 7 files changed, 226 insertions(+), 6 deletions(-) create mode 100755 test_regress/t/t_select_bound1.pl create mode 100644 test_regress/t/t_select_bound1.v create mode 100755 test_regress/t/t_select_bound2.pl create mode 100644 test_regress/t/t_select_bound2.v diff --git a/Changes b/Changes index e18cdf780..6cefe24ee 100644 --- a/Changes +++ b/Changes @@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix public parameters in unused packages, bug804. [Jonathon Donaldson] +**** Fix select when partially out-of-bound, bug823. [Cliffort Wolf] + **** Fix generate unrolling with function call, bug830. [Steven Slatter] **** Fix cast-to-size context-determined sizing, bug828. [Geoff Barrett] diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index be10ab7bb..d1d9f706c 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -337,14 +337,14 @@ private: // Find range of dtype we are selecting from // Similar code in V3Const::warnSelect int maxmsb = nodep->fromp()->dtypep()->width()-1; - int maxlsb = maxmsb - nodep->width() + 1; if (debug()>=9) nodep->dumpTree(cout,"sel_old: "); - V3Number maxlsbnum (nodep->fileline(), nodep->lsbp()->width(), maxlsb); + V3Number maxmsbnum (nodep->fileline(), nodep->lsbp()->width(), maxmsb); - // See if the condition is constant true + // If (maxmsb >= selected), we're in bound AstNode* condp = new AstGte (nodep->fileline(), - new AstConst(nodep->fileline(), maxlsbnum), + new AstConst(nodep->fileline(), maxmsbnum), nodep->lsbp()->cloneTree(false)); + // See if the condition is constant true (e.g. always in bound due to constant select) // Note below has null backp(); the Edit function knows how to deal with that. condp = V3Const::constifyEdit(condp); if (condp->isOne()) { @@ -352,7 +352,7 @@ private: condp->deleteTree(); } else if (!lvalue) { - // SEL(...) -> COND(LTE(bit<=maxlsb), ARRAYSEL(...), {width{1'bx}}) + // SEL(...) -> COND(LTE(bit<=maxmsb), ARRAYSEL(...), {width{1'bx}}) AstNRelinker replaceHandle; nodep->unlinkFrBack(&replaceHandle); V3Number xnum (nodep->fileline(), nodep->width()); diff --git a/test_regress/t/t_select_bound1.pl b/test_regress/t/t_select_bound1.pl new file mode 100755 index 000000000..f91289753 --- /dev/null +++ b/test_regress/t/t_select_bound1.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_select_bound1.v b/test_regress/t/t_select_bound1.v new file mode 100644 index 000000000..8c57e1802 --- /dev/null +++ b/test_regress/t/t_select_bound1.v @@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +// bug823 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [2:0] in = crc[2:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[3:0]), + .mask (mask[3:0]), + // Inputs + .clk (clk), + .in (in[2:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out & mask}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'ha9d3a7a69d2bea75 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, mask, + // Inputs + clk, in + ); + + input clk; + input [2:0] in; + output reg [3:0] out; + output reg [3:0] mask; + localparam [15:5] p = 11'h1ac; + + always @(posedge clk) begin + // verilator lint_off WIDTH + out <= p[15 + in -: 5]; + // verilator lint_on WIDTH + mask[3] <= ((15 + in - 5) < 12); + mask[2] <= ((15 + in - 5) < 13); + mask[1] <= ((15 + in - 5) < 14); + mask[0] <= ((15 + in - 5) < 15); + end + +endmodule diff --git a/test_regress/t/t_select_bound2.pl b/test_regress/t/t_select_bound2.pl new file mode 100755 index 000000000..f91289753 --- /dev/null +++ b/test_regress/t/t_select_bound2.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_select_bound2.v b/test_regress/t/t_select_bound2.v new file mode 100644 index 000000000..ff6600d0a --- /dev/null +++ b/test_regress/t/t_select_bound2.v @@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2014 by Wilson Snyder. + +// bug823 +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [6:0] in = crc[6:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [3:0] mask; // From test of Test.v + wire [3:0] out; // From test of Test.v + // End of automatics + + Test test (/*AUTOINST*/ + // Outputs + .out (out[3:0]), + .mask (mask[3:0]), + // Inputs + .clk (clk), + .in (in[6:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out & mask}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x out=%b mask=%b\n",$time, cyc, crc, out, mask); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4e9d3a74e9d3f656 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test (/*AUTOARG*/ + // Outputs + out, mask, + // Inputs + clk, in + ); + + input clk; + input [6:0] in; // Note much wider than any index + output reg [3:0] out; + output reg [3:0] mask; + localparam [15:5] p = 11'h1ac; + + always @(posedge clk) begin + // verilator lint_off WIDTH + out <= p[15 + in -: 5]; + // verilator lint_on WIDTH + mask[3] <= ((15 + in - 5) < 12); + mask[2] <= ((15 + in - 5) < 13); + mask[1] <= ((15 + in - 5) < 14); + mask[0] <= ((15 + in - 5) < 15); + end + +endmodule diff --git a/test_regress/t/t_select_plus.v b/test_regress/t/t_select_plus.v index 09f4cfd12..0d078c374 100644 --- a/test_regress/t/t_select_plus.v +++ b/test_regress/t/t_select_plus.v @@ -66,7 +66,7 @@ module t (/*AUTOARG*/ 8'd04: begin if ((to^from)!==80'h6d000000000000000000) $stop; end 8'd05: begin if (((to^from)&~80'hf)!==80'h90000000000000000000) $stop; end // Exceed bounds, verilator may write index 0 8'd06: begin if (((to^from)&~80'hf)!==80'h00000000000000000020) $stop; end // Exceed bounds, verilator may write index 0 - 8'd07: begin if (((to^from)&~80'hf)!==80'h0c000000000000000000) $stop; end + 8'd07: begin if (((to^from)&~80'hf)!==80'h4c000000000000000000) $stop; end 8'd08: begin if ((to^from)!==80'h0004d000000000000000) $stop; end 8'd09: begin if (((to^from)&~80'hf)!==80'h00000000000000000000) $stop; end default: $stop;