From c4b9f4bccf321fb70c29adcd5cc208fbb72aa57a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 7 Mar 2019 18:29:44 -0500 Subject: [PATCH] Tests: Remove old verilator_file_descriptor --- test_regress/t/t_case_write1.v | 10 +++++----- test_regress/t/t_case_write2.v | 10 +++++----- test_regress/t/t_sys_file_basic.v | 2 +- test_regress/t/t_sys_file_scan.v | 2 +- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/test_regress/t/t_case_write1.v b/test_regress/t/t_case_write1.v index a5856066c..c0d1123bc 100644 --- a/test_regress/t/t_case_write1.v +++ b/test_regress/t/t_case_write1.v @@ -15,8 +15,8 @@ module t (/*AUTOARG*/ input clk; reg [63:0] crc; - `verilator_file_descriptor fd; - `verilator_file_descriptor fdtmp; + integer fd; + integer fdtmp; t_case_write1_tasks tasks (); @@ -33,14 +33,14 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==1) begin - crc <= 64'h00000000_00000097; + crc <= 64'h00000000_00000097; $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log\n"}); fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write1_logger.log"}, "w"); fd <= fdtmp; end if (cyc==90) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_case_write2.v b/test_regress/t/t_case_write2.v index 07215dd6d..3110fc3a2 100644 --- a/test_regress/t/t_case_write2.v +++ b/test_regress/t/t_case_write2.v @@ -15,8 +15,8 @@ module t (/*AUTOARG*/ input clk; reg [63:0] crc; - `verilator_file_descriptor fd; - `verilator_file_descriptor fdtmp; + integer fd; + integer fdtmp; t_case_write2_tasks tasks (); @@ -33,14 +33,14 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; if (cyc==1) begin - crc <= 64'h00000000_00000097; + crc <= 64'h00000000_00000097; $write("%s", {"Open ", `STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log\n"}); fdtmp = $fopen({`STRINGIFY(`TEST_OBJ_DIR), "/t_case_write2_logger.log"}, "w"); fd <= fdtmp; end if (cyc==90) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end diff --git a/test_regress/t/t_sys_file_basic.v b/test_regress/t/t_sys_file_basic.v index 13b477d95..5ec60a216 100644 --- a/test_regress/t/t_sys_file_basic.v +++ b/test_regress/t/t_sys_file_basic.v @@ -8,7 +8,7 @@ `define STRINGIFY(x) `"x`" module t; - `verilator_file_descriptor file; + integer file; integer chars; reg [1*8:1] letterl; diff --git a/test_regress/t/t_sys_file_scan.v b/test_regress/t/t_sys_file_scan.v index 30efafadf..e3c51bb1a 100644 --- a/test_regress/t/t_sys_file_scan.v +++ b/test_regress/t/t_sys_file_scan.v @@ -8,7 +8,7 @@ `define STRINGIFY(x) `"x`" module t; - `verilator_file_descriptor infile, outfile; + integer infile, outfile; integer count, a; initial begin