From c300ab6dd98571d1c405ea9aee0a50fcd499d0b3 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 18 Oct 2007 16:29:19 +0000
Subject: [PATCH] Match up with Verilog-Perl: add specify operators

git-svn-id: file://localhost/svn/verilator/trunk/verilator@956 77ca24e4-aefa-0310-84f0-b9a241c72d87
---
 src/verilog.l | 6 ++++++
 src/verilog.y | 9 +++++++++
 2 files changed, 15 insertions(+)

diff --git a/src/verilog.l b/src/verilog.l
index 5f9264ba7..811c32d03 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -568,6 +568,12 @@ escid	\\[^ \t\f\r\n]+
   "~&"			{yylval.fileline = CRELINE(); return yP_NAND;}
   "~|"			{yylval.fileline = CRELINE(); return yP_NOR;}
   "->"			{yylval.fileline = CRELINE(); return yP_MINUSGT;}
+  "=>"                  {yylval.fileline = CRELINE(); return yP_EQGT; }
+  "*>"                  {yylval.fileline = CRELINE(); return yP_ASTGT; }
+  "+=>"                 {yylval.fileline = CRELINE(); return yP_PLUSEQGT; }
+  "+*>"                 {yylval.fileline = CRELINE(); return yP_PLUSASTGT; }
+  "-=>"                 {yylval.fileline = CRELINE(); return yP_MINUSEQGT; }
+  "-*>"                 {yylval.fileline = CRELINE(); return yP_MINUSASTGT; }
 }
 
   /* Verilog 2001 Operators */
diff --git a/src/verilog.y b/src/verilog.y
index 8761a802b..b4b8b9ae9 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -248,6 +248,12 @@ class AstSenTree;
 
 %token<fileline>	yP_PLUSCOLON	"+:"
 %token<fileline>	yP_MINUSCOLON	"-:"
+%token<fileline>	yP_EQGT		"=>"
+%token<fileline>	yP_ASTGT	"*>"
+%token<fileline>	yP_PLUSEQGT	"+=>"
+%token<fileline>	yP_PLUSASTGT	"+*>"
+%token<fileline>	yP_MINUSEQGT	"-=>"
+%token<fileline>	yP_MINUSASTGT	"-*>"
 
 %token<fileline>	yPSL_BRA	"{"
 %token<fileline>	yPSL_KET	"}"
@@ -1132,6 +1138,9 @@ specifyJunk:	dlyTerm 	{} /* ignored */
 	|	yPSL_KET {}
 	|	yP_OR_MINUS_GT {}
 	|	yP_OR_EQ_GT {}
+	|	yP_EQGT {}	| yP_ASTGT {}
+	|	yP_PLUSEQGT {}	| yP_PLUSASTGT {}
+	|	yP_MINUSEQGT {} | yP_MINUSASTGT {}
 
 	|	error {}
 	;