From 5ae285d268fd52b7e6d812c3ce979468cb5a0b78 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 28 Feb 2026 09:37:43 -0500 Subject: [PATCH 001/340] devel release --- CMakeLists.txt | 2 +- Changes | 7 +++++++ configure.ac | 2 +- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 4c391b2ab..614e5cac9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -16,7 +16,7 @@ cmake_minimum_required(VERSION 3.15) cmake_policy(SET CMP0091 NEW) # Use MSVC_RUNTIME_LIBRARY to select the runtime project( Verilator - VERSION 5.046 + VERSION 5.047 HOMEPAGE_URL https://verilator.org LANGUAGES CXX ) diff --git a/Changes b/Changes index cdb3948ab..77adf7ad4 100644 --- a/Changes +++ b/Changes @@ -8,6 +8,13 @@ The changes in each Verilator version are described below. The contributors that suggested or implemented a given issue are shown in []. Thanks! +Verilator 5.047 devel +========================== + +**Other:** + + + Verilator 5.046 2026-02-28 ========================== diff --git a/configure.ac b/configure.ac index cfb627b8c..4b1ae8f8d 100644 --- a/configure.ac +++ b/configure.ac @@ -12,7 +12,7 @@ # Then 'make maintainer-dist' #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[5.046 2026-02-28], +AC_INIT([Verilator],[5.047 devel], [https://verilator.org], [verilator],[https://verilator.org]) From d40036239b3fc5f7196c9ec75a2b97f1e3128912 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 28 Feb 2026 09:40:10 -0500 Subject: [PATCH 002/340] Fix wide conditional short circuiting (#7155). Fixes #7155. --- Changes | 1 + include/verilated_funcs.h | 7 +- test_regress/t/t_cover_line_wide_ternary.out | 42 ++++----- test_regress/t/t_math_cond_short_circuit.py | 18 ++++ test_regress/t/t_math_cond_short_circuit.v | 91 ++++++++++++++++++++ 5 files changed, 134 insertions(+), 25 deletions(-) create mode 100755 test_regress/t/t_math_cond_short_circuit.py create mode 100644 test_regress/t/t_math_cond_short_circuit.v diff --git a/Changes b/Changes index 77adf7ad4..6f6cb2cd0 100644 --- a/Changes +++ b/Changes @@ -13,6 +13,7 @@ Verilator 5.047 devel **Other:** +* Fix wide conditional short circuiting (#7155). Verilator 5.046 2026-02-28 diff --git a/include/verilated_funcs.h b/include/verilated_funcs.h index e3e4534ff..d5fde472b 100644 --- a/include/verilated_funcs.h +++ b/include/verilated_funcs.h @@ -2792,10 +2792,9 @@ static inline void VL_SELASSIGN_WW(int rbits, int obits, WDataOutP iowp, WDataIn //====================================================================== // Triops -static inline WDataOutP VL_COND_WIWW(int obits, WDataOutP owp, int cond, WDataInP const w1p, - WDataInP const w2p) VL_MT_SAFE { - return VL_MEMCPY_W(owp, cond ? w1p : w2p, VL_WORDS_I(obits)); -} +// This must be a macro in order for short-circuiting of the values to work. +#define VL_COND_WIWW(obits, owp, cond, w1p, w2p) \ + VL_MEMCPY_W(owp, (cond) ? (w1p) : (w2p), VL_WORDS_I(obits)) //====================================================================== // Constification diff --git a/test_regress/t/t_cover_line_wide_ternary.out b/test_regress/t/t_cover_line_wide_ternary.out index 692bb31a9..ddbc770fd 100644 --- a/test_regress/t/t_cover_line_wide_ternary.out +++ b/test_regress/t/t_cover_line_wide_ternary.out @@ -39,37 +39,37 @@ -000009 point: type=line comment=block hier=top.t %000009 {intf_sel_ff.foo, intf_sel_ff.bar, intf_sel_ff.baz} <= -000009 point: type=line comment=block hier=top.t -%000009 cyc[0] ? --000009 point: type=branch comment=cond_then hier=top.t -%000009 {intfs[1].foo, intfs[1].bar, intfs[1].baz} : --000009 point: type=branch comment=cond_then hier=top.t --000009 point: type=branch comment=cond_else hier=top.t -%000009 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; --000009 point: type=branch comment=cond_else hier=top.t +%000005 cyc[0] ? +-000005 point: type=branch comment=cond_then hier=top.t +%000005 {intfs[1].foo, intfs[1].bar, intfs[1].baz} : +-000005 point: type=branch comment=cond_then hier=top.t +-000004 point: type=branch comment=cond_else hier=top.t +%000004 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; +-000004 point: type=branch comment=cond_else hier=top.t end 000010 always_comb begin +000010 point: type=line comment=block hier=top.t 000010 {intf_sel_comb.foo, intf_sel_comb.bar, intf_sel_comb.baz} = +000010 point: type=line comment=block hier=top.t - 000010 cyc[0] ? -+000010 point: type=branch comment=cond_then hier=top.t - 000010 {intfs[1].foo, intfs[1].bar, intfs[1].baz} : -+000010 point: type=branch comment=cond_then hier=top.t -+000010 point: type=branch comment=cond_else hier=top.t - 000010 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; -+000010 point: type=branch comment=cond_else hier=top.t +%000005 cyc[0] ? +-000005 point: type=branch comment=cond_then hier=top.t +%000005 {intfs[1].foo, intfs[1].bar, intfs[1].baz} : +-000005 point: type=branch comment=cond_then hier=top.t +-000005 point: type=branch comment=cond_else hier=top.t +%000005 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; +-000005 point: type=branch comment=cond_else hier=top.t end assign {intf_sel_assign.foo, intf_sel_assign.bar, intf_sel_assign.baz} = - 000010 cyc[0] ? -+000010 point: type=branch comment=cond_then hier=top.t - 000010 {intfs[1].foo, intfs[1].bar, intfs[1].baz} : -+000010 point: type=branch comment=cond_then hier=top.t -+000010 point: type=branch comment=cond_else hier=top.t - 000010 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; -+000010 point: type=branch comment=cond_else hier=top.t +%000005 cyc[0] ? +-000005 point: type=branch comment=cond_then hier=top.t +%000005 {intfs[1].foo, intfs[1].bar, intfs[1].baz} : +-000005 point: type=branch comment=cond_then hier=top.t +-000005 point: type=branch comment=cond_else hier=top.t +%000005 {intfs[0].foo, intfs[0].bar, intfs[0].baz}; +-000005 point: type=branch comment=cond_else hier=top.t %000009 always @ (posedge clk) begin -000009 point: type=line comment=block hier=top.t diff --git a/test_regress/t/t_math_cond_short_circuit.py b/test_regress/t/t_math_cond_short_circuit.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_math_cond_short_circuit.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_math_cond_short_circuit.v b/test_regress/t/t_math_cond_short_circuit.v new file mode 100644 index 000000000..c86ab7097 --- /dev/null +++ b/test_regress/t/t_math_cond_short_circuit.v @@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +`ifdef verilator + `define optimize_barrier $c("") +`else + `define optimize_barrier +`endif +// verilog_format: on + +module t; + + class Map; + virtual function bit [95:0] get_value(); + bit [95:0] result = 96'h11111111_22222222_33333333; + `optimize_barrier; + return result; + endfunction + endclass + + class Cls; + function bit [95:0] get_default(); + bit [95:0] result = 96'haaaaaaaa_bbbbbbbb_cccccccc; + `optimize_barrier; + return result; + endfunction + + function bit [95:0] compute_LL(Map map); + bit [95:0] result; + `optimize_barrier; + // Wide operation is required, as results in VL_COND call which evaluates + // arguments + result = map == null ? this.get_default() : map.get_value(); + `optimize_barrier; + return result; + endfunction + + function bit [95:0] compute_LC(Map map); + bit [95:0] result; + bit sel1 = map == null; + `optimize_barrier; + result = sel1 ? 96'hffffffff_ffffffff_ffffffff : map.get_value(); + `optimize_barrier; + return result; + endfunction + + function bit [95:0] compute_CL(Map map); + bit [95:0] result; + bit sel1 = map != null; + `optimize_barrier; + result = sel1 ? map.get_value() : 96'hffffffff_ffffffff_ffffffff; + `optimize_barrier; + return result; + endfunction + + endclass + + initial begin + Cls c; + Map mnull; + Map m; + bit [95:0] res; + + c = new; + m = new; + + res = c.compute_LL(mnull); + `checkh(res, 96'haaaaaaaa_bbbbbbbb_cccccccc); + res = c.compute_LL(m); + `checkh(res, 96'h11111111_22222222_33333333); + + res = c.compute_LC(mnull); + `checkh(res, 96'hffffffff_ffffffff_ffffffff); + res = c.compute_LC(m); + `checkh(res, 96'h11111111_22222222_33333333); + + res = c.compute_CL(mnull); + `checkh(res, 96'hffffffff_ffffffff_ffffffff); + res = c.compute_CL(m); + `checkh(res, 96'h11111111_22222222_33333333); + + $finish; + end + +endmodule From 1e6c1ab106ee065156488f6e2ac8c41af6f643dd Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 28 Feb 2026 09:42:28 -0500 Subject: [PATCH 003/340] Add VPI callback support to --main (#7145). Fixes #7145. --- Changes | 1 + include/verilated.mk.in | 2 +- include/verilated_vpi.cpp | 2 +- src/V3EmitCMain.cpp | 42 +++++++- test_regress/t/t_vpi_dump.cpp | 2 +- test_regress/t/t_vpi_empty.py | 19 ++++ test_regress/t/t_vpi_empty.v | 9 ++ test_regress/t/t_vpi_onetime_cbs.cpp | 146 ++++++++------------------- test_regress/t/t_vpi_onetime_cbs.py | 5 +- test_regress/t/t_vpi_onetime_cbs.v | 33 +++--- test_regress/t/t_vpi_unimpl.cpp | 2 +- verilator-config.cmake.in | 4 +- 12 files changed, 138 insertions(+), 129 deletions(-) create mode 100755 test_regress/t/t_vpi_empty.py create mode 100644 test_regress/t/t_vpi_empty.v diff --git a/Changes b/Changes index 6f6cb2cd0..a13c9c8e1 100644 --- a/Changes +++ b/Changes @@ -13,6 +13,7 @@ Verilator 5.047 devel **Other:** +* Add VPI callback support to --main (#7145). * Fix wide conditional short circuiting (#7155). diff --git a/include/verilated.mk.in b/include/verilated.mk.in index 7a14bc558..8669bd330 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -114,7 +114,7 @@ CPPFLAGS += $(OPT) # On macOS, specify all weak symbols as dynamic_lookup. # Otherwise, you get undefined symbol errors. ifeq ($(UNAME_S),Darwin) - LDFLAGS += -Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv + LDFLAGS += -Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv,-U,vlog_startup_routines endif # Allow upper level user makefiles to specify flags they want. diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 7bcee1bdc..004ebe33c 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -716,7 +716,7 @@ public: // cppcheck-suppress uninitVar // m_value VerilatedVpiCbHolder(uint64_t id, const s_cb_data* cbDatap, const VerilatedVpioVar* varop) : m_id{id} - , m_cbData{*cbDatap} + , m_cbData{*cbDatap} // vpi_register_cb checks cbDatap is non-null , m_varo{varop} { m_value.format = cbDatap->value ? cbDatap->value->format : vpiSuppressVal; m_cbData.value = &m_value; diff --git a/src/V3EmitCMain.cpp b/src/V3EmitCMain.cpp index 46734c540..624ae5b72 100644 --- a/src/V3EmitCMain.cpp +++ b/src/V3EmitCMain.cpp @@ -55,13 +55,21 @@ private: // Heavily commented output, as users are likely to look at or copy this code puts("#include \"verilated.h\"\n"); + if (v3Global.opt.vpi()) puts("#include \"verilated_vpi.h\"\n"); puts("#include \"" + EmitCUtil::topClassName() + ".h\"\n"); if (v3Global.opt.debugRuntimeTimeout()) { puts("\n"); puts("#include \n"); } + puts("\n"); - puts("\n//======================\n\n"); + if (v3Global.opt.vpi()) { + puts("// User VPI code adds to this array to get startup main() callbacks\n"); + puts("extern \"C\" void (*vlog_startup_routines[])() VL_ATTR_WEAK;\n"); + puts("\n"); + } + + puts("//======================\n\n"); if (v3Global.opt.debugRuntimeTimeout()) { puts("void alarmHandler(int signum) {\n"); @@ -92,18 +100,43 @@ private: + EmitCUtil::topClassName() + "{contextp.get(), \"" + topName + "\"}};\n"); puts("\n"); + if (v3Global.opt.vpi()) { + puts("// Hook VPI startup routines and invoke callback\n"); + puts("if (vlog_startup_routines) {\n"); + puts(/**/ "for (auto routinep = &vlog_startup_routines[0]; *routinep; routinep++)" + " (*routinep)();\n"); + puts("}\n"); + puts("VerilatedVpi::callCbs(cbStartOfSimulation);\n"); + puts("\n"); + } + puts("// Simulate until $finish\n"); puts("while (VL_LIKELY(!contextp->gotFinish())) {\n"); + if (v3Global.opt.vpi()) { + puts(/**/ "// VPI callbacks\n"); + puts(/**/ "VerilatedVpi::callTimedCbs();\n"); + puts(/**/ "VerilatedVpi::callCbs(cbNextSimTime);\n"); // Before next event queue + puts(/**/ "VerilatedVpi::callCbs(cbAtStartOfSimTime);\n"); // Before time queue + } puts(/**/ "// Evaluate model\n"); puts(/**/ "topp->eval();\n"); + if (v3Global.opt.vpi()) { + puts(/**/ "// VPI callbacks\n"); + puts(/**/ "VerilatedVpi::callValueCbs();\n"); + puts(/**/ "VerilatedVpi::callCbs(cbAtEndOfSimTime);\n"); // After nonblocking events + puts(/**/ "VerilatedVpi::callCbs(cbReadWriteSynch);\n"); // After a specified time + puts(/**/ "VerilatedVpi::callCbs(cbReadOnlySynch);\n"); // After cbReadWriteSynch + } puts(/**/ "// Advance time\n"); if (v3Global.rootp()->delaySchedulerp() || v3Global.opt.timing()) { puts("if (!topp->eventsPending()) break;\n"); } - if (v3Global.rootp()->delaySchedulerp()) { - puts("contextp->time(topp->nextTimeSlot());\n"); + const std::string nextSlot = v3Global.rootp()->delaySchedulerp() ? "topp->nextTimeSlot()" + : "contextp->time() + 1"; + if (v3Global.opt.vpi()) { + puts("contextp->time(std::min("s + nextSlot + ", VerilatedVpi::cbNextDeadline()));\n"); } else { - puts("contextp->timeInc(1);\n"); + puts("contextp->time("s + nextSlot + ");\n"); } puts("}\n"); @@ -116,6 +149,7 @@ private: puts("// Execute 'final' processes\n"); puts("topp->final();\n"); + if (v3Global.opt.vpi()) puts("VerilatedVpi::callCbs(cbEndOfSimulation);\n"); puts("\n"); if (v3Global.opt.coverage()) { diff --git a/test_regress/t/t_vpi_dump.cpp b/test_regress/t/t_vpi_dump.cpp index 6e9e9d950..b8ed57511 100644 --- a/test_regress/t/t_vpi_dump.cpp +++ b/test_regress/t/t_vpi_dump.cpp @@ -159,7 +159,7 @@ void vpi_compat_bootstrap(void) { // We're able to call vpi_main() here on Verilator/Xcelium, // but Icarus complains (rightfully so) - s_cb_data cb_data; + s_cb_data cb_data{}; s_vpi_time vpi_time; vpi_time.high = 0; diff --git a/test_regress/t/t_vpi_empty.py b/test_regress/t/t_vpi_empty.py new file mode 100755 index 000000000..46dfce8c1 --- /dev/null +++ b/test_regress/t/t_vpi_empty.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +# Checks that --vpi without a C file doesn't break builds +test.compile(verilator_flags2=["--binary --vpi"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_vpi_empty.v b/test_regress/t/t_vpi_empty.v new file mode 100644 index 000000000..44d9f7881 --- /dev/null +++ b/test_regress/t/t_vpi_empty.v @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + initial $finish; +endmodule diff --git a/test_regress/t/t_vpi_onetime_cbs.cpp b/test_regress/t/t_vpi_onetime_cbs.cpp index 441ffae76..2c021d727 100644 --- a/test_regress/t/t_vpi_onetime_cbs.cpp +++ b/test_regress/t/t_vpi_onetime_cbs.cpp @@ -12,21 +12,10 @@ // Setup multiple one-time callbacks with different time delays. // Ensure they are not called before the delay has elapsed. -#ifdef IS_VPI - #include "vpi_user.h" #include -#else - -#include "verilated.h" -#include "verilated_vpi.h" - -#include VM_PREFIX_INCLUDE - -#endif - // These require the above. Comment prevents clang-format moving them #include "TestSimulator.h" #include "TestVpi.h" @@ -45,7 +34,7 @@ typedef struct { static cb_stats CallbackStats[cbAtEndOfSimTime + 1]; -bool got_error = false; +int errors = 0; static vpiHandle ValueHandle, ToggleHandle, ClockHandle; @@ -80,28 +69,40 @@ bool cb_time_is_delay(int cb_name) { return false; } +vpiHandle test_vpi_register_cb(p_cb_data cb_datap) { + if (verbose) + vpi_printf(const_cast("- test_vpi_register_cb(%s @%d)\n"), + strFromVpiCallbackReason(cb_datap->reason), + (cb_datap->time ? cb_datap->time->low : 0)); + return vpi_register_cb(cb_datap); +} + // forward declaration static PLI_INT32 TheCallback(s_cb_data* data); static PLI_INT32 AtEndOfSimTimeCallback(s_cb_data* data) { s_vpi_time t; + CHECK_RESULT(data->reason, cbAtEndOfSimTime); cb_stats* stats = &CallbackStats[data->reason]; t.type = vpiSimTime; vpi_get_time(0, &t); - if (verbose) vpi_printf(const_cast("- [@%d] AtEndOfSimTime Callback\n"), t.low); + if (verbose) + vpi_printf(const_cast("- [@%d] AtEndOfSimTime Callback (count=%d)\n"), t.low, + stats->count); + CHECK_RESULT(stats->count < stats->number_of_exp_times, 1); CHECK_RESULT(t.low, stats->exp_times[stats->count]); stats->count += 1; - s_cb_data cb_data; + s_cb_data cb_data{}; s_vpi_time time = {vpiSimTime, 0, 417, 0}; // non-zero time to check that it's ignored cb_data.time = &time; cb_data.reason = cbNextSimTime; cb_data.cb_rtn = TheCallback; - vpiHandle Handle = vpi_register_cb(&cb_data); + vpiHandle Handle = test_vpi_register_cb(&cb_data); CHECK_RESULT_NZ(Handle); return 0; @@ -116,16 +117,17 @@ static PLI_INT32 TheCallback(s_cb_data* data) { vpi_get_time(0, &t); if (verbose) { - vpi_printf(const_cast("- [@%d] %s Callback\n"), t.low, - cb_reason_to_string(data->reason)); + vpi_printf(const_cast("- [@%d] %s Callback (count=%d)\n"), t.low, + cb_reason_to_string(data->reason), stats->count); } + CHECK_RESULT(stats->count < stats->number_of_exp_times, 1); CHECK_RESULT(t.low, stats->exp_times[stats->count]); stats->count += 1; if (stats->count >= stats->number_of_exp_times) return 0; - s_cb_data cb_data; + s_cb_data cb_data{}; PLI_UINT32 next_time; if (data->reason == cbNextSimTime) { @@ -150,14 +152,14 @@ static PLI_INT32 TheCallback(s_cb_data* data) { s_vpi_time time = {vpiSimTime, 0, next_time, 0}; cb_data.time = &time; - vpiHandle Handle = vpi_register_cb(&cb_data); + vpiHandle Handle = test_vpi_register_cb(&cb_data); CHECK_RESULT_NZ(Handle); return 0; } static PLI_INT32 StartOfSimulationCallback(s_cb_data* data) { - s_cb_data cb_data; + s_cb_data cb_data{}; s_vpi_time timerec = {vpiSimTime, 0, 0, 0}; s_vpi_time t; @@ -179,32 +181,33 @@ static PLI_INT32 StartOfSimulationCallback(s_cb_data* data) { CallbackStats[cbAtStartOfSimTime].number_of_exp_times = 3; timerec.low = 5; cb_data.reason = cbAtStartOfSimTime; - vpiHandle ASOSHandle = vpi_register_cb(&cb_data); + vpiHandle ASOSHandle = test_vpi_register_cb(&cb_data); CHECK_RESULT_NZ(ASOSHandle); CallbackStats[cbReadWriteSynch].exp_times = new PLI_UINT32[3]{6, 16, 21}; CallbackStats[cbReadWriteSynch].number_of_exp_times = 3; timerec.low = 6; cb_data.reason = cbReadWriteSynch; - vpiHandle RWHandle = vpi_register_cb(&cb_data); + vpiHandle RWHandle = test_vpi_register_cb(&cb_data); CHECK_RESULT_NZ(RWHandle); CallbackStats[cbReadOnlySynch].exp_times = new PLI_UINT32[3]{7, 17, 22}; CallbackStats[cbReadOnlySynch].number_of_exp_times = 3; timerec.low = 7; cb_data.reason = cbReadOnlySynch; - vpiHandle ROHandle = vpi_register_cb(&cb_data); + vpiHandle ROHandle = test_vpi_register_cb(&cb_data); CHECK_RESULT_NZ(ROHandle); - CallbackStats[cbNextSimTime].exp_times = new PLI_UINT32[9]{5, 6, 7, 15, 16, 17, 20, 21, 22}; - CallbackStats[cbNextSimTime].number_of_exp_times = 9; + CallbackStats[cbNextSimTime].exp_times + = new PLI_UINT32[10]{5, 6, 7, 10, 15, 16, 17, 20, 21, 22}; + CallbackStats[cbNextSimTime].number_of_exp_times = 10; timerec.low = 8; cb_data.reason = cbNextSimTime; - vpiHandle NSTHandle = vpi_register_cb(&cb_data); + vpiHandle NSTHandle = test_vpi_register_cb(&cb_data); CHECK_RESULT_NZ(NSTHandle); - CallbackStats[cbAtEndOfSimTime].exp_times = new PLI_UINT32[8]{5, 6, 7, 15, 16, 17, 20, 21}; - CallbackStats[cbAtEndOfSimTime].number_of_exp_times = 8; + CallbackStats[cbAtEndOfSimTime].exp_times = new PLI_UINT32[9]{5, 6, 7, 10, 15, 16, 17, 20, 21}; + CallbackStats[cbAtEndOfSimTime].number_of_exp_times = 9; return (0); } @@ -223,23 +226,26 @@ static int EndOfSimulationCallback(p_cb_data cb_data) { CHECK_RESULT(CallbackStats[cbStartOfSimulation].count, 1); CHECK_RESULT(CallbackStats[cbAtStartOfSimTime].count, 3); - CHECK_RESULT(CallbackStats[cbNextSimTime].count, 9); + CHECK_RESULT(CallbackStats[cbNextSimTime].count, 10); CHECK_RESULT(CallbackStats[cbReadWriteSynch].count, 3); CHECK_RESULT(CallbackStats[cbReadOnlySynch].count, 3); - CHECK_RESULT(CallbackStats[cbAtEndOfSimTime].count, 8); + CHECK_RESULT(CallbackStats[cbAtEndOfSimTime].count, 9); CHECK_RESULT(CallbackStats[cbEndOfSimulation].count, 1); - if (!got_error) printf("*-* All Finished *-*\n"); + if (!errors) printf("*-* All Finished *-*\n"); + return 0; } // cver entry static void VPIRegister(void) { + if (verbose) vpi_printf(const_cast("- VPIRegister callback\n")); + // Clear stats for (int cb = 1; cb <= cbAtEndOfSimTime; cb++) CallbackStats[cb].count = 0; CallbackStats[cbStartOfSimulation].exp_times = new PLI_UINT32(0); - CallbackStats[cbEndOfSimulation].exp_times = new PLI_UINT32(22); - s_cb_data cb_data; + CallbackStats[cbEndOfSimulation].exp_times = new PLI_UINT32(100); + s_cb_data cb_data{}; s_vpi_time timerec = {vpiSuppressTime, 0, 0, 0}; cb_data.time = &timerec; @@ -248,80 +254,12 @@ static void VPIRegister(void) { cb_data.obj = 0; cb_data.reason = cbStartOfSimulation; cb_data.cb_rtn = StartOfSimulationCallback; - - vpi_register_cb(&cb_data); + test_vpi_register_cb(&cb_data); cb_data.reason = cbEndOfSimulation; cb_data.cb_rtn = EndOfSimulationCallback; - vpi_register_cb(&cb_data); + test_vpi_register_cb(&cb_data); } -#ifdef IS_VPI - -// icarus entry +// simulator entry void (*vlog_startup_routines[])(void) = {VPIRegister, 0}; - -#else - -int main(int argc, char** argv, char** env) { - double sim_time = 100; - const std::unique_ptr contextp{new VerilatedContext}; - - bool cbs_called; - contextp->commandArgs(argc, argv); - // contextp->debug(9); - - const std::unique_ptr topp{new VM_PREFIX{contextp.get(), - // Note null name - we're flattening it out - ""}}; - - topp->clk = 1; - - // StartOfSimulationCallback(nullptr); - VPIRegister(); - - VerilatedVpi::callCbs(cbStartOfSimulation); - - topp->clk = 0; - topp->eval(); - - while (contextp->time() < sim_time && !contextp->gotFinish()) { - VerilatedVpi::callTimedCbs(); - VerilatedVpi::callCbs(cbNextSimTime); - VerilatedVpi::callCbs(cbAtStartOfSimTime); - - topp->eval(); - - VerilatedVpi::callValueCbs(); - VerilatedVpi::callCbs(cbReadWriteSynch); - VerilatedVpi::callCbs(cbReadOnlySynch); - VerilatedVpi::callCbs(cbAtEndOfSimTime); - - const uint64_t next_time = VerilatedVpi::cbNextDeadline(); - if (next_time != -1) contextp->time(next_time); - if (verbose) - vpi_printf(const_cast("- [@%" PRId64 "] time change\n"), contextp->time()); - if (next_time == -1 && !contextp->gotFinish()) { - if (got_error) { - vl_stop(__FILE__, __LINE__, "TOP-cpp"); - } else { - VerilatedVpi::callCbs(cbEndOfSimulation); - contextp->gotFinish(true); - } - } - - // Count updates on rising edge, so cycle through falling edge as well - topp->clk = !topp->clk; - topp->eval(); - topp->clk = !topp->clk; - } - - if (!contextp->gotFinish()) { - vl_fatal(__FILE__, __LINE__, "main", "%Error: Timeout; never got a $finish"); - } - topp->final(); - - exit(0L); -} - -#endif diff --git a/test_regress/t/t_vpi_onetime_cbs.py b/test_regress/t/t_vpi_onetime_cbs.py index 7c5bb911a..62f11ad2b 100755 --- a/test_regress/t/t_vpi_onetime_cbs.py +++ b/test_regress/t/t_vpi_onetime_cbs.py @@ -12,12 +12,11 @@ import vltest_bootstrap test.scenarios('simulator') test.compile(make_top_shell=False, - make_main=False, make_pli=True, - verilator_flags2=["--exe --vpi", test.pli_filename], + verilator_flags2=["--binary --vpi", test.pli_filename], iv_flags2=["-g2005-sv -D USE_VPI_NOT_DPI -DIVERILOG"], v_flags2=["+define+USE_VPI_NOT_DPI"]) -test.execute(use_libvpi=True) +test.execute(check_finished=True, use_libvpi=True) test.passes() diff --git a/test_regress/t/t_vpi_onetime_cbs.v b/test_regress/t/t_vpi_onetime_cbs.v index 33ca974e1..dce2d3a6f 100644 --- a/test_regress/t/t_vpi_onetime_cbs.v +++ b/test_regress/t/t_vpi_onetime_cbs.v @@ -5,20 +5,27 @@ // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - input clk - ); +module t; - reg [31:0] count /*verilator public_flat_rd */; + logic clk; + initial begin + clk = 0; + #10; + while ($time < 100) begin + clk = !clk; + #10; + end + end - // Test loop - initial begin - count = 0; - end + reg [31:0] count /*verilator public_flat_rd */; - always @(posedge clk) begin - count <= count + 2; - end + // Test loop + initial begin + count = 0; + end -endmodule : t + always @(posedge clk) begin + count <= count + 2; + end + +endmodule diff --git a/test_regress/t/t_vpi_unimpl.cpp b/test_regress/t/t_vpi_unimpl.cpp index 05e998241..359089492 100644 --- a/test_regress/t/t_vpi_unimpl.cpp +++ b/test_regress/t/t_vpi_unimpl.cpp @@ -81,7 +81,7 @@ int _mon_check_unimpl(p_cb_data cb_data) { handle = vpi_register_cb(NULL); CHECK_RESULT(handle, 0); - s_cb_data cb_data_s; + s_cb_data cb_data_s{}; cb_data_s.reason = 0; // Bad handle = vpi_register_cb(&cb_data_s); CHECK_RESULT(handle, 0); diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index 2da925698..1c739b433 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -120,7 +120,9 @@ if(NOT CMAKE_CXX_COMPILER_ID MATCHES MSVC) endif() if(APPLE) - add_link_options(-Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv) + add_link_options( + -Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv,-U,vlog_startup_routines + ) endif() define_property( From 1716423d079688dccccb763a71899af00e07f7be Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 28 Feb 2026 14:51:07 +0000 Subject: [PATCH 004/340] Internals: Fix invalid use of user1 in V3Const (#7157) --- src/V3Const.cpp | 96 ++++++++++++++++++++++++------------------------- 1 file changed, 46 insertions(+), 50 deletions(-) diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 7ef77be05..a57f795bb 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -3343,58 +3343,54 @@ class ConstVisitor final : public VNVisitor { void visit(AstCvtArrayToArray* nodep) override { iterateChildren(nodep); // Handle the case where we have a stream operation inside a cast conversion - // To avoid infinite recursion, mark the node as processed by setting user1. - if (!nodep->user1()) { - nodep->user1(true); - // Check for both StreamL and StreamR operations - AstNodeStream* streamp = nullptr; - bool isReverse = false; - if (AstStreamL* const streamLp = VN_CAST(nodep->fromp(), StreamL)) { - streamp = streamLp; - isReverse = true; // StreamL reverses the operation - } else if (AstStreamR* const streamRp = VN_CAST(nodep->fromp(), StreamR)) { - streamp = streamRp; - isReverse = false; // StreamR doesn't reverse the operation - } - if (streamp) { - AstNodeExpr* srcp = streamp->lhsp(); - const AstNodeDType* const srcDTypep = srcp->dtypep()->skipRefp(); - AstNodeDType* const dstDTypep = nodep->dtypep()->skipRefp(); - if (VN_IS(srcDTypep, QueueDType) && VN_IS(dstDTypep, QueueDType)) { - int blockSize = 1; - if (const AstConst* const constp = VN_CAST(streamp->rhsp(), Const)) { - blockSize = constp->toSInt(); - if (VL_UNLIKELY(blockSize <= 0)) { - // Not reachable due to higher level checks when parsing stream - // operators commented out to not fail v3error-coverage-checks. - // nodep->v3error("Stream block size must be positive, got " << - // blockSize); - blockSize = 1; - } + // Check for both StreamL and StreamR operations + AstNodeStream* streamp = nullptr; + bool isReverse = false; + if (AstStreamL* const streamLp = VN_CAST(nodep->fromp(), StreamL)) { + streamp = streamLp; + isReverse = true; // StreamL reverses the operation + } else if (AstStreamR* const streamRp = VN_CAST(nodep->fromp(), StreamR)) { + streamp = streamRp; + isReverse = false; // StreamR doesn't reverse the operation + } + if (streamp) { + AstNodeExpr* srcp = streamp->lhsp(); + const AstNodeDType* const srcDTypep = srcp->dtypep()->skipRefp(); + AstNodeDType* const dstDTypep = nodep->dtypep()->skipRefp(); + if (VN_IS(srcDTypep, QueueDType) && VN_IS(dstDTypep, QueueDType)) { + int blockSize = 1; + if (const AstConst* const constp = VN_CAST(streamp->rhsp(), Const)) { + blockSize = constp->toSInt(); + if (VL_UNLIKELY(blockSize <= 0)) { + // Not reachable due to higher level checks when parsing stream + // operators commented out to not fail v3error-coverage-checks. + // nodep->v3error("Stream block size must be positive, got " << + // blockSize); + blockSize = 1; } - // Not reachable due to higher level checks when parsing stream operators - // commented out to not fail v3error-coverage-checks. - // else { - // nodep->v3error("Stream block size must be constant (got " << - // streamp->rhsp()->prettyTypeName() << ")"); - // } - int srcElementBits = 0; - if (const AstNodeDType* const elemDtp = srcDTypep->subDTypep()) { - srcElementBits = elemDtp->width(); - } - int dstElementBits = 0; - if (const AstNodeDType* const elemDtp = dstDTypep->subDTypep()) { - dstElementBits = elemDtp->width(); - } - streamp->unlinkFrBack(); - AstNodeExpr* newp = new AstCvtArrayToArray{ - srcp->fileline(), srcp->unlinkFrBack(), dstDTypep, isReverse, - blockSize, dstElementBits, srcElementBits}; - nodep->replaceWith(newp); - VL_DO_DANGLING(pushDeletep(streamp), streamp); - VL_DO_DANGLING(pushDeletep(nodep), nodep); - return; } + // Not reachable due to higher level checks when parsing stream operators + // commented out to not fail v3error-coverage-checks. + // else { + // nodep->v3error("Stream block size must be constant (got " << + // streamp->rhsp()->prettyTypeName() << ")"); + // } + int srcElementBits = 0; + if (const AstNodeDType* const elemDtp = srcDTypep->subDTypep()) { + srcElementBits = elemDtp->width(); + } + int dstElementBits = 0; + if (const AstNodeDType* const elemDtp = dstDTypep->subDTypep()) { + dstElementBits = elemDtp->width(); + } + streamp->unlinkFrBack(); + AstNodeExpr* newp = new AstCvtArrayToArray{ + srcp->fileline(), srcp->unlinkFrBack(), dstDTypep, isReverse, + blockSize, dstElementBits, srcElementBits}; + nodep->replaceWith(newp); + VL_DO_DANGLING(pushDeletep(streamp), streamp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + return; } } } From 02c1dbc5dcd6398941b25021a3801aa927f1a07f Mon Sep 17 00:00:00 2001 From: Nick Brereton <85175726+nbstrike@users.noreply.github.com> Date: Sat, 28 Feb 2026 09:52:02 -0500 Subject: [PATCH 005/340] Fix lambda coroutines (#6106) (#7135) --- src/V3EmitCFunc.h | 18 +++++- src/V3Width.cpp | 4 +- test_regress/t/t_coroutine_lambda.py | 21 +++++++ test_regress/t/t_coroutine_lambda.v | 83 ++++++++++++++++++++++++++++ 4 files changed, 123 insertions(+), 3 deletions(-) create mode 100755 test_regress/t/t_coroutine_lambda.py create mode 100644 test_regress/t/t_coroutine_lambda.v diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 1684cc1ca..1ee0d3aa5 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -1199,7 +1199,7 @@ public: if (VN_IS(nodep->exprp()->dtypep()->skipRefp(), VoidDType)) { putns(nodep, ""); } else { - putns(nodep, "(void)"); // Prevent unused expression warning in C + putns(nodep, "std::ignore = "); } iterateConst(nodep->exprp()); puts(";\n"); @@ -1293,6 +1293,22 @@ public: } void visit(AstExprStmt* nodep) override { VL_RESTORER(m_createdScopeHash); + const bool containsAwait = nodep->exists([](AstCAwait*) -> bool { return true; }); + if (containsAwait) { + UASSERT_OBJ(m_cfuncp && m_cfuncp->isCoroutine(), nodep, + "AstExprStmt with CAwait must be in coroutine"); + putnbs(nodep, "(co_await ([&]() -> VlCoroutine {\n"); + iterateAndNextConstNull(nodep->stmtsp()); + puts("co_return;\n"); + if (!nodep->hasResult()) { + puts("}()))"); + return; + } + puts("}()), "); + iterateAndNextConstNull(nodep->resultp()); + puts(")"); + return; + } // GCC allows compound statements in expressions, but this is not standard. // So we use an immediate-evaluation lambda and comma operator putnbs(nodep, "([&]() {\n"); diff --git a/src/V3Width.cpp b/src/V3Width.cpp index de98e9de6..a2e050928 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -4504,7 +4504,7 @@ class WidthVisitor final : public VNVisitor { = new AstCMethodHard{nodep->fileline(), nodep->fromp()->unlinkFrBack(), VCMethod::RNG_SET_RANDSTATE, exprp->unlinkFrBack()}; newp->usePtr(true); - newp->dtypeSetString(); + newp->dtypeSetVoid(); nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; @@ -6994,7 +6994,7 @@ class WidthVisitor final : public VNVisitor { = new AstCExpr{nodep->fileline(), "__Vm_rng.set_randstate(", 1}; newp->add(exprp->unlinkFrBack()); newp->add(")"); - newp->dtypeSetString(); + newp->dtypeSetVoid(); nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; diff --git a/test_regress/t/t_coroutine_lambda.py b/test_regress/t/t_coroutine_lambda.py new file mode 100755 index 000000000..a4be4c39b --- /dev/null +++ b/test_regress/t/t_coroutine_lambda.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Coroutine call inside AstExprStmt lambda +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=[ + "--binary", + "--timing", + "-Wno-FUNCTIMECTL", + "-Wno-WIDTHTRUNC", +]) + +test.passes() diff --git a/test_regress/t/t_coroutine_lambda.v b/test_regress/t/t_coroutine_lambda.v new file mode 100644 index 000000000..c0a7eb6c0 --- /dev/null +++ b/test_regress/t/t_coroutine_lambda.v @@ -0,0 +1,83 @@ +// DESCRIPTION: Verilator: Coroutine call inside AstExprStmt lambda test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +interface cpu_if(input logic clk); +endinterface + +package p; + +virtual class WriterIf; + virtual function void write(input int t); + endfunction +endclass + +class BlockingWriter; + virtual cpu_if vif; + task write(int t); + @(posedge vif.clk); + endtask +endclass + +class WriterAdapter extends WriterIf; + BlockingWriter m_impl; + function new(BlockingWriter impl); + m_impl = impl; + endfunction + function void write(input int t); + m_impl.write(t); // function -> task path + endfunction +endclass + +class QueueLike; + WriterIf sink; + mailbox #(int) m; + function bit try_get(output int t); + if (!m.try_get(t)) begin + end + sink.write(t); // can become coroutine call + endfunction +endclass + +class DriverLike; + QueueLike reqq; + function void item_done(); + int t; + if (reqq.try_get(t) == 0) begin + end + endfunction +endclass + +endpackage + +module t; + import p::*; + + logic clk = 0; + cpu_if vif(clk); + + always #1 clk = ~clk; + + initial begin + BlockingWriter writer; + WriterAdapter adapter; + QueueLike reqq; + DriverLike drv; + + writer = new(); + writer.vif = vif; + adapter = new(writer); + + reqq = new(); + reqq.sink = adapter; + + drv = new(); + drv.reqq = reqq; + drv.item_done(); + + #2 $finish; + end +endmodule From 8705bc56c8b391e7f0d89bd80ccdcebd1cd1d047 Mon Sep 17 00:00:00 2001 From: Todd Strader Date: Sat, 28 Feb 2026 09:52:35 -0500 Subject: [PATCH 006/340] Fix errant integer promotion (#7012) --- src/V3Clean.cpp | 3 +- src/Verilator.cpp | 3 +- test_regress/t/t_array_sel_short.py | 23 + test_regress/t/t_array_sel_short.v | 17 + test_regress/t/t_json_only_debugcheck.out | 2222 ++++++++++----------- 5 files changed, 1155 insertions(+), 1113 deletions(-) create mode 100755 test_regress/t/t_array_sel_short.py create mode 100644 test_regress/t/t_array_sel_short.v diff --git a/src/V3Clean.cpp b/src/V3Clean.cpp index 61f509922..2c326bbb7 100644 --- a/src/V3Clean.cpp +++ b/src/V3Clean.cpp @@ -18,7 +18,7 @@ // Each module: // For each expression, if it requires a clean operand, // and the operand is dirty, insert a CLEAN node. -// Resize operands to C++ 32/64/wide types. +// Resize operands (but not variables or variable selects) to C++ 32/64/wide types. // Copy all width() values to widthMin() so RANGE, etc can still see orig widths // //************************************************************************* @@ -83,6 +83,7 @@ class CleanVisitor final : public VNVisitor { if (VN_IS(nodep, Var) // || VN_IS(nodep, ConsPackMember) // || VN_IS(nodep, NodeDType) // Don't want to change variable widths! + || VN_IS(nodep, NodeSel) // Array selects should reflect variable widths || VN_IS(nodep->dtypep()->skipRefp(), AssocArrayDType) // Or arrays || VN_IS(nodep->dtypep()->skipRefp(), WildcardArrayDType) || VN_IS(nodep->dtypep()->skipRefp(), DynArrayDType) diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 50a4dcf0f..c3b90208f 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -527,7 +527,8 @@ static void process() { // Bits between widthMin() and width() are irrelevant, but may be non zero. v3Global.widthMinUsage(VWidthMinUsage::VERILOG_WIDTH); - // Make all expressions either 8, 16, 32 or 64 bits + // Make all expressions 32, 64, or 32*N bits + // Variables and selects-of-variables remain verilog-width V3Clean::cleanAll(v3Global.rootp()); // Move wide constants to BLOCK temps / ConstPool. diff --git a/test_regress/t/t_array_sel_short.py b/test_regress/t/t_array_sel_short.py new file mode 100755 index 000000000..f7f552639 --- /dev/null +++ b/test_regress/t/t_array_sel_short.py @@ -0,0 +1,23 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios("simulator") + +test.compile(verilator_flags2=["--dump-tree"]) + +if test.vlt_all: + # Test for correct array select width, see: #7012 + clean_tree = test.glob_one(test.obj_dir + "/V*_clean.tree") + test.file_grep_count(clean_tree, r"ARRAYSEL.*G\/w16", 2) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_array_sel_short.v b/test_regress/t/t_array_sel_short.v new file mode 100644 index 000000000..aa669f231 --- /dev/null +++ b/test_regress/t/t_array_sel_short.v @@ -0,0 +1,17 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +module t; + + logic [15:0] foo [8]; + + initial begin + if (foo[1] != foo[1]) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_json_only_debugcheck.out b/test_regress/t/t_json_only_debugcheck.out index b360d118a..0277917a8 100644 --- a/test_regress/t/t_json_only_debugcheck.out +++ b/test_regress/t/t_json_only_debugcheck.out @@ -66,79 +66,79 @@ {"type":"CONST","name":"4'h4","addr":"(ZB)","loc":"d,38:31,38:34","dtypep":"(UB)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(AC)","loc":"d,38:15,38:16","dtypep":"(UB)", + {"type":"ARRAYSEL","name":"","addr":"(AC)","loc":"d,38:15,38:16","dtypep":"(BC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(BC)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(CC)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(EC)","loc":"d,38:15,38:16","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(FC)","loc":"d,38:15,38:16","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(GC)","loc":"d,38:15,38:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(HC)","loc":"d,38:15,38:16","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(IC)","loc":"d,38:15,38:16","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(JC)","loc":"d,38:15,38:16","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(JC)","loc":"d,38:15,38:16","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(KC)","loc":"d,38:15,38:16","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ]} ], "thensp": [ - {"type":"DISPLAY","name":"","addr":"(KC)","loc":"d,38:43,38:49", + {"type":"DISPLAY","name":"","addr":"(LC)","loc":"d,38:43,38:49", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:38: got='h%x exp='h4\\n","addr":"(LC)","loc":"d,38:43,38:49","dtypep":"(SB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:38: got='h%x exp='h4\\n","addr":"(MC)","loc":"d,38:43,38:49","dtypep":"(SB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(MC)","loc":"d,38:122,38:123","dtypep":"(UB)", + {"type":"ARRAYSEL","name":"","addr":"(NC)","loc":"d,38:122,38:123","dtypep":"(BC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(NC)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OC)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(OC)","loc":"d,38:122,38:123","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(PC)","loc":"d,38:122,38:123","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(PC)","loc":"d,38:122,38:123","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(QC)","loc":"d,38:122,38:123","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(QC)","loc":"d,38:122,38:123","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(RC)","loc":"d,38:122,38:123","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(RC)","loc":"d,38:122,38:123","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(SC)","loc":"d,38:122,38:123","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(SC)","loc":"d,38:142,38:147"} + {"type":"STOP","name":"","addr":"(TC)","loc":"d,38:142,38:147"} ],"elsesp": []}, - {"type":"IF","name":"","addr":"(TC)","loc":"d,39:10,39:12", + {"type":"IF","name":"","addr":"(UC)","loc":"d,39:10,39:12", "condp": [ - {"type":"NEQ","name":"","addr":"(UC)","loc":"d,39:34,39:37","dtypep":"(GB)", + {"type":"NEQ","name":"","addr":"(VC)","loc":"d,39:34,39:37","dtypep":"(GB)", "lhsp": [ - {"type":"CONST","name":"4'h1","addr":"(VC)","loc":"d,39:39,39:42","dtypep":"(UB)"} + {"type":"CONST","name":"4'h1","addr":"(WC)","loc":"d,39:39,39:42","dtypep":"(UB)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(WC)","loc":"d,39:15,39:16","dtypep":"(UB)", + {"type":"ARRAYSEL","name":"","addr":"(XC)","loc":"d,39:15,39:16","dtypep":"(BC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(XC)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YC)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(YC)","loc":"d,39:15,39:16","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(ZC)","loc":"d,39:15,39:16","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(ZC)","loc":"d,39:15,39:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(AD)","loc":"d,39:15,39:16","dtypep":"(IC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(AD)","loc":"d,39:15,39:16","dtypep":"(FC)", + {"type":"ARRAYSEL","name":"","addr":"(BD)","loc":"d,39:15,39:16","dtypep":"(GC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(BD)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(CD)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(CD)","loc":"d,39:15,39:16","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(DD)","loc":"d,39:15,39:16","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(DD)","loc":"d,39:15,39:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(ED)","loc":"d,39:15,39:16","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(ED)","loc":"d,39:15,39:16","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(FD)","loc":"d,39:15,39:16","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(FD)","loc":"d,39:15,39:16","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(GD)","loc":"d,39:15,39:16","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -147,33 +147,33 @@ ]} ], "thensp": [ - {"type":"DISPLAY","name":"","addr":"(GD)","loc":"d,39:51,39:57", + {"type":"DISPLAY","name":"","addr":"(HD)","loc":"d,39:51,39:57", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:39: got='h%x exp='h1\\n","addr":"(HD)","loc":"d,39:51,39:57","dtypep":"(SB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:39: got='h%x exp='h1\\n","addr":"(ID)","loc":"d,39:51,39:57","dtypep":"(SB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(ID)","loc":"d,39:130,39:131","dtypep":"(UB)", + {"type":"ARRAYSEL","name":"","addr":"(JD)","loc":"d,39:130,39:131","dtypep":"(BC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(JD)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KD)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(KD)","loc":"d,39:130,39:131","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(LD)","loc":"d,39:130,39:131","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(LD)","loc":"d,39:130,39:131","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(MD)","loc":"d,39:130,39:131","dtypep":"(IC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(MD)","loc":"d,39:130,39:131","dtypep":"(FC)", + {"type":"ARRAYSEL","name":"","addr":"(ND)","loc":"d,39:130,39:131","dtypep":"(GC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(ND)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OD)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(OD)","loc":"d,39:130,39:131","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(PD)","loc":"d,39:130,39:131","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(PD)","loc":"d,39:130,39:131","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(QD)","loc":"d,39:130,39:131","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(QD)","loc":"d,39:130,39:131","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(RD)","loc":"d,39:130,39:131","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(RD)","loc":"d,39:130,39:131","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(SD)","loc":"d,39:130,39:131","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -181,38 +181,38 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(SD)","loc":"d,39:158,39:163"} + {"type":"STOP","name":"","addr":"(TD)","loc":"d,39:158,39:163"} ],"elsesp": []}, - {"type":"IF","name":"","addr":"(TD)","loc":"d,40:10,40:12", + {"type":"IF","name":"","addr":"(UD)","loc":"d,40:10,40:12", "condp": [ - {"type":"NEQ","name":"","addr":"(UD)","loc":"d,40:26,40:29","dtypep":"(GB)", + {"type":"NEQ","name":"","addr":"(VD)","loc":"d,40:26,40:29","dtypep":"(GB)", "lhsp": [ - {"type":"CONST","name":"4'h1","addr":"(VD)","loc":"d,40:31,40:34","dtypep":"(UB)"} + {"type":"CONST","name":"4'h1","addr":"(WD)","loc":"d,40:31,40:34","dtypep":"(UB)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(WD)","loc":"d,40:15,40:16","dtypep":"(UB)", + {"type":"ARRAYSEL","name":"","addr":"(XD)","loc":"d,40:15,40:16","dtypep":"(BC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(XD)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YD)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(YD)","loc":"d,40:15,40:16","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(ZD)","loc":"d,40:15,40:16","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(ZD)","loc":"d,40:15,40:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(AE)","loc":"d,40:15,40:16","dtypep":"(IC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(AE)","loc":"d,40:15,40:16","dtypep":"(FC)", + {"type":"ARRAYSEL","name":"","addr":"(BE)","loc":"d,40:15,40:16","dtypep":"(GC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(BE)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(CE)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(CE)","loc":"d,40:15,40:16","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(DE)","loc":"d,40:15,40:16","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(DE)","loc":"d,40:15,40:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(EE)","loc":"d,40:15,40:16","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(EE)","loc":"d,40:15,40:16","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(FE)","loc":"d,40:15,40:16","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(FE)","loc":"d,40:15,40:16","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(GE)","loc":"d,40:15,40:16","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -221,33 +221,33 @@ ]} ], "thensp": [ - {"type":"DISPLAY","name":"","addr":"(GE)","loc":"d,40:43,40:49", + {"type":"DISPLAY","name":"","addr":"(HE)","loc":"d,40:43,40:49", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:40: got='h%x exp='h1\\n","addr":"(HE)","loc":"d,40:43,40:49","dtypep":"(SB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:40: got='h%x exp='h1\\n","addr":"(IE)","loc":"d,40:43,40:49","dtypep":"(SB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(IE)","loc":"d,40:122,40:123","dtypep":"(UB)", + {"type":"ARRAYSEL","name":"","addr":"(JE)","loc":"d,40:122,40:123","dtypep":"(BC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(JE)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KE)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(KE)","loc":"d,40:122,40:123","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(LE)","loc":"d,40:122,40:123","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(LE)","loc":"d,40:122,40:123","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(ME)","loc":"d,40:122,40:123","dtypep":"(IC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(ME)","loc":"d,40:122,40:123","dtypep":"(FC)", + {"type":"ARRAYSEL","name":"","addr":"(NE)","loc":"d,40:122,40:123","dtypep":"(GC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(NE)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OE)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(OE)","loc":"d,40:122,40:123","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(PE)","loc":"d,40:122,40:123","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(PE)","loc":"d,40:122,40:123","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(QE)","loc":"d,40:122,40:123","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(QE)","loc":"d,40:122,40:123","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(RE)","loc":"d,40:122,40:123","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(RE)","loc":"d,40:122,40:123","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(SE)","loc":"d,40:122,40:123","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -255,48 +255,48 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(SE)","loc":"d,40:142,40:147"} + {"type":"STOP","name":"","addr":"(TE)","loc":"d,40:142,40:147"} ],"elsesp": []}, - {"type":"IF","name":"","addr":"(TE)","loc":"d,41:10,41:12", + {"type":"IF","name":"","addr":"(UE)","loc":"d,41:10,41:12", "condp": [ - {"type":"NEQ","name":"","addr":"(UE)","loc":"d,41:42,41:45","dtypep":"(GB)", + {"type":"NEQ","name":"","addr":"(VE)","loc":"d,41:42,41:45","dtypep":"(GB)", "lhsp": [ - {"type":"CONST","name":"4'h3","addr":"(VE)","loc":"d,41:47,41:50","dtypep":"(UB)"} + {"type":"CONST","name":"4'h3","addr":"(WE)","loc":"d,41:47,41:50","dtypep":"(UB)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(WE)","loc":"d,41:15,41:16","dtypep":"(UB)", + {"type":"ARRAYSEL","name":"","addr":"(XE)","loc":"d,41:15,41:16","dtypep":"(BC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(XE)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YE)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - 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{"type":"CONST","name":"32'h7","addr":"(DF)","loc":"d,41:15,41:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(EF)","loc":"d,41:15,41:16","dtypep":"(IC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(EF)","loc":"d,41:15,41:16","dtypep":"(FC)", + {"type":"ARRAYSEL","name":"","addr":"(FF)","loc":"d,41:15,41:16","dtypep":"(GC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(FF)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(GF)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(GF)","loc":"d,41:15,41:16","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(HF)","loc":"d,41:15,41:16","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(HF)","loc":"d,41:15,41:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(IF)","loc":"d,41:15,41:16","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(IF)","loc":"d,41:15,41:16","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(JF)","loc":"d,41:15,41:16","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(JF)","loc":"d,41:15,41:16","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(KF)","loc":"d,41:15,41:16","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -307,43 +307,43 @@ ]} ], "thensp": [ - {"type":"DISPLAY","name":"","addr":"(KF)","loc":"d,41:59,41:65", + {"type":"DISPLAY","name":"","addr":"(LF)","loc":"d,41:59,41:65", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:41: got='h%x exp='h3\\n","addr":"(LF)","loc":"d,41:59,41:65","dtypep":"(SB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:41: got='h%x exp='h3\\n","addr":"(MF)","loc":"d,41:59,41:65","dtypep":"(SB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(MF)","loc":"d,41:138,41:139","dtypep":"(UB)", + {"type":"ARRAYSEL","name":"","addr":"(NF)","loc":"d,41:138,41:139","dtypep":"(BC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(NF)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OF)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(OF)","loc":"d,41:138,41:139","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(PF)","loc":"d,41:138,41:139","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(PF)","loc":"d,41:138,41:139","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(QF)","loc":"d,41:138,41:139","dtypep":"(IC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(QF)","loc":"d,41:138,41:139","dtypep":"(FC)", + {"type":"ARRAYSEL","name":"","addr":"(RF)","loc":"d,41:138,41:139","dtypep":"(GC)", "fromp": [ - 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{"type":"AND","name":"","addr":"(WF)","loc":"d,41:138,41:139","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(XF)","loc":"d,41:138,41:139","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(XF)","loc":"d,41:138,41:139","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(YF)","loc":"d,41:138,41:139","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(YF)","loc":"d,41:138,41:139","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(ZF)","loc":"d,41:138,41:139","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(ZF)","loc":"d,41:138,41:139","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(AG)","loc":"d,41:138,41:139","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -353,48 +353,48 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(AG)","loc":"d,41:174,41:179"} + {"type":"STOP","name":"","addr":"(BG)","loc":"d,41:174,41:179"} ],"elsesp": []}, - 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{"type":"CONST","name":"32'h7","addr":"(LG)","loc":"d,42:15,42:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(MG)","loc":"d,42:15,42:16","dtypep":"(IC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(MG)","loc":"d,42:15,42:16","dtypep":"(FC)", + {"type":"ARRAYSEL","name":"","addr":"(NG)","loc":"d,42:15,42:16","dtypep":"(GC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(NG)","loc":"d,17:12,17:16","dtypep":"(CC)","access":"RD","varp":"(DC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OG)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(OG)","loc":"d,42:15,42:16","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(PG)","loc":"d,42:15,42:16","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(PG)","loc":"d,42:15,42:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(QG)","loc":"d,42:15,42:16","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(QG)","loc":"d,42:15,42:16","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(RG)","loc":"d,42:15,42:16","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(RG)","loc":"d,42:15,42:16","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(SG)","loc":"d,42:15,42:16","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -405,43 +405,43 @@ ]} ], "thensp": [ - {"type":"DISPLAY","name":"","addr":"(SG)","loc":"d,42:51,42:57", + {"type":"DISPLAY","name":"","addr":"(TG)","loc":"d,42:51,42:57", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:42: got='h%x exp='h3\\n","addr":"(TG)","loc":"d,42:51,42:57","dtypep":"(SB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:42: got='h%x exp='h3\\n","addr":"(UG)","loc":"d,42:51,42:57","dtypep":"(SB)", "exprsp": [ - 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{"type":"AND","name":"","addr":"(EH)","loc":"d,42:130,42:131","dtypep":"(FC)", + {"type":"AND","name":"","addr":"(FH)","loc":"d,42:130,42:131","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(FH)","loc":"d,42:130,42:131","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(GH)","loc":"d,42:130,42:131","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(GH)","loc":"d,42:130,42:131","dtypep":"(FC)","size":32, + {"type":"CCAST","name":"","addr":"(HH)","loc":"d,42:130,42:131","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(HH)","loc":"d,42:130,42:131","dtypep":"(FC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(IH)","loc":"d,42:130,42:131","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -451,48 +451,48 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(IH)","loc":"d,42:158,42:163"} + {"type":"STOP","name":"","addr":"(JH)","loc":"d,42:158,42:163"} ],"elsesp": []}, - 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{"type":"REFDTYPE","name":"my_t","addr":"(M)","loc":"d,24:4,24:8","dtypep":"(ISB)","typedefp":"UNLINKED","refDTypep":"(ISB)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, + {"type":"REFDTYPE","name":"my_t","addr":"(M)","loc":"d,24:4,24:8","dtypep":"(BC)","typedefp":"UNLINKED","refDTypep":"(BC)","classOrPackagep":"UNLINKED","typeofp": [],"classOrPackageOpp": [],"paramsp": []}, {"type":"BASICDTYPE","name":"string","addr":"(SB)","loc":"d,28:4,28:10","dtypep":"(SB)","keyword":"string","generic":true,"rangep": []}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(CC)","loc":"d,17:12,17:16","dtypep":"(CC)","declRange":"[7:0]","refDTypep":"(ISB)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(DC)","loc":"d,17:12,17:16","dtypep":"(DC)","declRange":"[7:0]","refDTypep":"(BC)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(PSB)","loc":"d,17:12,17:16", "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(QSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(QSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(RSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h0","addr":"(RSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ]} ]}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(WI)","loc":"d,17:12,17:16","dtypep":"(WI)","declRange":"[7:0]","refDTypep":"(ISB)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(XI)","loc":"d,17:12,17:16","dtypep":"(XI)","declRange":"[7:0]","refDTypep":"(BC)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(SSB)","loc":"d,17:12,17:16", "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(TSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(TSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(USB)","loc":"d,17:12,17:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h0","addr":"(USB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ]} ]}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(IM)","loc":"d,17:12,17:16","dtypep":"(IM)","isCompound":true,"declRange":"[7:0]","refDTypep":"(SB)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(JM)","loc":"d,17:12,17:16","dtypep":"(JM)","isCompound":true,"declRange":"[7:0]","refDTypep":"(SB)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(VSB)","loc":"d,17:12,17:16", "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(WSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h7","addr":"(WSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(XSB)","loc":"d,17:12,17:16","dtypep":"(HC)"} + {"type":"CONST","name":"32'h0","addr":"(XSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ]} ]}, {"type":"BASICDTYPE","name":"logic","addr":"(LB)","loc":"d,23:23,23:24","dtypep":"(LB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(DB)","loc":"a,0:0,0:0","dtypep":"(DB)"}, - {"type":"BASICDTYPE","name":"bit","addr":"(HN)","loc":"a,0:0,0:0","dtypep":"(HN)","keyword":"bit","range":"63:0","generic":true,"rangep": []}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(W)","loc":"d,11:8,11:9","dtypep":"(W)","declRange":"[0:0]","refDTypep":"(HN)","childDTypep": [], + {"type":"BASICDTYPE","name":"bit","addr":"(IN)","loc":"a,0:0,0:0","dtypep":"(IN)","keyword":"bit","range":"63:0","generic":true,"rangep": []}, + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(W)","loc":"d,11:8,11:9","dtypep":"(W)","declRange":"[0:0]","refDTypep":"(IN)","childDTypep": [], "rangep": [ {"type":"RANGE","name":"","addr":"(YSB)","loc":"d,11:8,11:9", "leftp": [ - {"type":"CONST","name":"32'h0","addr":"(ZSB)","loc":"d,11:8,11:9","dtypep":"(HC)"} + {"type":"CONST","name":"32'h0","addr":"(ZSB)","loc":"d,11:8,11:9","dtypep":"(IC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(ATB)","loc":"d,11:8,11:9","dtypep":"(HC)"} + {"type":"CONST","name":"32'h0","addr":"(ATB)","loc":"d,11:8,11:9","dtypep":"(IC)"} ]} ]}, - {"type":"BASICDTYPE","name":"IData","addr":"(IP)","loc":"a,0:0,0:0","dtypep":"(IP)","keyword":"IData","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(JN)","loc":"d,63:14,63:21","dtypep":"(JN)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"IData","addr":"(JP)","loc":"a,0:0,0:0","dtypep":"(JP)","keyword":"IData","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(KN)","loc":"d,63:14,63:21","dtypep":"(KN)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(P)","loc":"d,11:8,11:9","dtypep":"(P)","keyword":"bit","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(U)","loc":"d,11:8,11:9","dtypep":"(U)","keyword":"bit","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,63:22,63:25","dtypep":"(GB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(UB)","loc":"d,32:11,32:14","dtypep":"(UB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(FC)","loc":"d,38:15,38:16","dtypep":"(FC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(SPB)","loc":"d,15:10,15:13","dtypep":"(SPB)","keyword":"logic","range":"7:0","generic":true,"rangep": []} + {"type":"BASICDTYPE","name":"logic","addr":"(GC)","loc":"d,38:15,38:16","dtypep":"(GC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(TPB)","loc":"d,15:10,15:13","dtypep":"(TPB)","keyword":"logic","range":"7:0","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ From df6b808c496affa7db3fda746078c8a8257bdc23 Mon Sep 17 00:00:00 2001 From: Kamil Danecki Date: Sat, 28 Feb 2026 15:53:05 +0100 Subject: [PATCH 007/340] Fix parameters inside std::randomize `with` clause (#7140) --- src/V3Randomize.cpp | 9 ++++++++- test_regress/t/t_std_randomize.v | 17 +++++++++++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 76f359bf1..b80679b27 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -2188,7 +2188,7 @@ class CaptureVisitor final : public VNVisitor { newVarp->fileline(fileline); newVarp->varType(VVarType::BLOCKTEMP); newVarp->funcLocal(true); - newVarp->direction(m_targetp ? VDirection::INPUT : VDirection::REF); + newVarp->direction(VDirection::INPUT); newVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); m_varCloneMap.emplace(varrefp->varp(), newVarp); varp = newVarp; @@ -2458,6 +2458,13 @@ class RandomizeVisitor final : public VNVisitor { if (VN_IS(argExpr, ArraySel) && VN_IS(withExpr, ArraySel)) { const AstArraySel* const withASp = VN_AS(withExpr, ArraySel); const AstArraySel* const argASp = VN_AS(argExpr, ArraySel); + // Before checking Sel type index, check if both are Const + if (VN_IS(withASp->bitp(), Const) && VN_IS(argASp->bitp(), Const)) { + const AstConst* const withIdxp = VN_AS(withASp->bitp(), Const); + const AstConst* const argIdxp = VN_AS(argASp->bitp(), Const); + return isSimilarNode(withASp->fromp(), argASp->fromp()) + && withIdxp->num().isCaseEq(argIdxp->num()); + } // Index must be Sel type, extract VarRef using fromp() if (!VN_IS(withASp->bitp(), Sel) || !VN_IS(argASp->bitp(), Sel)) return false; const AstNodeExpr* const withIdxp = VN_AS(withASp->bitp(), Sel)->fromp(); diff --git a/test_regress/t/t_std_randomize.v b/test_regress/t/t_std_randomize.v index 40f4906d7..989ad72f6 100644 --- a/test_regress/t/t_std_randomize.v +++ b/test_regress/t/t_std_randomize.v @@ -36,6 +36,8 @@ class std_randomize_class; endclass +parameter int PARAM = 123; + module t_scope_std_randomize; bit [7:0] addr; bit [15:0] data; @@ -45,6 +47,10 @@ module t_scope_std_randomize; bit [30:0] limit_31bits[10]; bit [62:0] limit_63bits[10]; bit [94:0] limit_95bits[10]; + int x; + int y = 50; + int arr1[2]; + int arr2[2]; function bit run(); int ready; @@ -120,6 +126,17 @@ module t_scope_std_randomize; if (test.addr <= addr || test.addr >= 8'd100) `stop; if (limit_31bits[0] <= 31'(test.addr) || limit_31bits[0] >= 31'd200) `stop; + // Test parameter in with clause + void'(std::randomize(x) with { x > PARAM; }); + if (x <= PARAM) $stop; + void'(std::randomize(x) with { x < PARAM; x > y; }); + if (x >= PARAM || x <= y) $stop; + + arr1[0] = 1000; + arr2[0] = 42; + void'(std::randomize(arr1[0]) with { arr1[0] == arr2[0]; }); + if (arr1[0] != 42) $stop; + $write("*-* All Finished *-*\n"); $finish; end From 6f892d58ac549222ea26ff907deb5d6b71366d82 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Sat, 28 Feb 2026 15:53:41 +0100 Subject: [PATCH 008/340] Fix forcing unpacked variables (#7149) --- src/V3Force.cpp | 54 +++++++++++++------------------ test_regress/t/t_force_unpacked.v | 25 ++++++++++++++ 2 files changed, 47 insertions(+), 32 deletions(-) diff --git a/src/V3Force.cpp b/src/V3Force.cpp index 7f3a4f8b5..edbd0fb20 100644 --- a/src/V3Force.cpp +++ b/src/V3Force.cpp @@ -442,40 +442,30 @@ class ForceConvertVisitor final : public VNVisitor { // continuous assignment shall reestablish that assignment and schedule a reevaluation in // the continuous assignment's scheduling region. AstAssign* const resetRdp - = new AstAssign{flp, lhsp->cloneTreePure(false), lhsp->unlinkFrBack()}; + = new AstAssign{flp, lhsp->unlinkFrBack(), lhsp->cloneTreePure(false)}; resetRdp->user2(true); - // Replace write refs on the LHS - resetRdp->lhsp()->foreach([this](AstVarRef* refp) { - if (refp->access() != VAccess::WRITE) return; - AstVarScope* const vscp = refp->varScopep(); - if (vscp->varp()->isContinuously()) { - AstVarRef* const newpRefp = new AstVarRef{ - refp->fileline(), m_state.getForceComponents(vscp).m_rdVscp, VAccess::WRITE}; - refp->replaceWith(newpRefp); - VL_DO_DANGLING(refp->deleteTree(), refp); - } - }); - // Replace write refs on RHS - if (VN_IS(resetRdp->rhsp(), ArraySel) || VN_IS(resetRdp->rhsp(), StructSel)) { - AstVarRef* const refp - = VN_AS(AstNodeVarRef::varRefLValueRecurse(resetRdp->rhsp()), VarRef); - AstVarScope* const vscp = refp->varScopep(); - AstNodeExpr* const origRhsp = resetRdp->rhsp(); - origRhsp->replaceWith( - m_state.getForceComponents(vscp).forcedUpdate(vscp, origRhsp, refp)); - VL_DO_DANGLING(origRhsp->deleteTree(), origRhsp); + AstVarRef* const refp = VN_AS(AstNodeVarRef::varRefLValueRecurse(lhsp), VarRef); + AstVarScope* const vscp = refp->varScopep(); + AstVarRef* const rhsRefp = refp->clonep(); + + if (vscp->varp()->isContinuously()) { + AstVarRef* const lhsRefp = new AstVarRef{ + refp->fileline(), m_state.getForceComponents(vscp).m_rdVscp, VAccess::WRITE}; + refp->replaceWith(lhsRefp); + VL_DO_DANGLING(refp->deleteTree(), refp); + rhsRefp->access(VAccess::READ); + ForceState::markNonReplaceable(rhsRefp); } else { - resetRdp->rhsp()->foreach([this](AstVarRef* refp) { - if (refp->access() != VAccess::WRITE) return; - AstVarScope* const vscp = refp->varScopep(); - if (vscp->varp()->isContinuously()) { - refp->access(VAccess::READ); - ForceState::markNonReplaceable(refp); - } else { - refp->replaceWith(m_state.getForceComponents(vscp).forcedUpdate(vscp)); - VL_DO_DANGLING(refp->deleteTree(), refp); - } - }); + if (rhsRefp->dtypep()->skipRefp()->isIntegralOrPacked()) { + // In this case var ref can be replaced with expression + rhsRefp->replaceWith(m_state.getForceComponents(vscp).forcedUpdate(vscp)); + VL_DO_DANGLING(rhsRefp->deleteTree(), rhsRefp); + } else { + AstNodeExpr* const origRhsp = resetRdp->rhsp(); + origRhsp->replaceWith( + m_state.getForceComponents(vscp).forcedUpdate(vscp, origRhsp, rhsRefp)); + VL_DO_DANGLING(origRhsp->deleteTree(), origRhsp); + } } resetRdp->addNext(resetEnp); diff --git a/test_regress/t/t_force_unpacked.v b/test_regress/t/t_force_unpacked.v index e942d8523..8335035e5 100644 --- a/test_regress/t/t_force_unpacked.v +++ b/test_regress/t/t_force_unpacked.v @@ -16,8 +16,17 @@ module t ( integer cyc = 0; + typedef union packed { + int x; + bit [31:0] y; + } union_t; + logic logic_arr[2][-2:2][-3:-5]; int int_arr[-1:2][1][3]; + bit [5:0] bit_arr[5]; + union_t union_arr[4]; + + assign bit_arr[2][3] = 1; // Test loop always @(posedge clk) begin @@ -25,38 +34,54 @@ module t ( if (cyc == 0) begin logic_arr[0][2][-4] <= 1; int_arr[0][0][2] <= 1; + union_arr[1].x <= 1; end else if (cyc == 1) begin `checkh(logic_arr[0][2][-4], 1); `checkh(int_arr[0][0][2], 1); + `checkh(bit_arr[2][3], 1); + `checkh(union_arr[1].x, 1); end else if (cyc == 2) begin force logic_arr[0][2][-4] = 0; force int_arr[0][0][2] = 0; + force bit_arr[2][3] = 0; + force union_arr[1].y = 2; end else if (cyc == 3) begin `checkh(logic_arr[0][2][-4], 0); logic_arr[0][2][-4] <= 1; `checkh(int_arr[0][0][2], 0); int_arr[0][0][2] <= 1; + `checkh(bit_arr[2][3], 0); + `checkh(union_arr[1].x, 2); + union_arr[1].x <= 3; end else if (cyc == 4) begin `checkh(logic_arr[0][2][-4], 0); `checkh(int_arr[0][0][2], 0); + `checkh(union_arr[1].y, 2); end else if (cyc == 5) begin release logic_arr[0][2][-4]; release int_arr[0][0][2]; + release bit_arr[2][3]; + `checkh(bit_arr[2][3], 1); + release union_arr[1].x; end else if (cyc == 6) begin `checkh(logic_arr[0][2][-4], 0); logic_arr[0][2][-4] <= 1; `checkh(int_arr[0][0][2], 0); int_arr[0][0][2] <= 1; + `checkh(bit_arr[2][3], 1); + `checkh(union_arr[1].x, 2); + union_arr[1].y <= 4; end else if (cyc == 7) begin `checkh(logic_arr[0][2][-4], 1); `checkh(int_arr[0][0][2], 1); + `checkh(union_arr[1].x, 4); end else if (cyc == 8) begin $write("*-* All Finished *-*\n"); From 1af7fa92c2c23e4b88ef32f22f2b87602d857add Mon Sep 17 00:00:00 2001 From: Szymon Gizler Date: Sat, 28 Feb 2026 15:54:08 +0100 Subject: [PATCH 009/340] Optimize size of trace declaration object code (#7150) --- include/verilated_fst_c.cpp | 74 +++++++++++++++++++++++---------- include/verilated_fst_c.h | 79 ++++++++++++++++++++++++++++-------- include/verilated_saif_c.cpp | 69 ++++++++++++++++++------------- include/verilated_saif_c.h | 67 ++++++++++++++++++++++-------- include/verilated_vcd_c.cpp | 57 +++++++++++++++----------- include/verilated_vcd_c.h | 65 +++++++++++++++++++++-------- src/V3EmitCImp.cpp | 24 ++++++----- 7 files changed, 296 insertions(+), 139 deletions(-) diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index f79e73168..d830dafaa 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -260,40 +260,70 @@ void VerilatedFst::declare(uint32_t code, const char* name, int dtypenum, } } -void VerilatedFst::declEvent(uint32_t code, uint32_t fidx, const char* name, int dtypenum, +// versions to call when the sig is not array member +void VerilatedFst::declEvent(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, - VerilatedTraceSigType type, bool array, int arraynum) { - declare(code, name, dtypenum, direction, kind, type, array, arraynum, false, 0, 0); + VerilatedTraceSigType type) { + declare(code, name, dtypenum, direction, kind, type, false, -1, false, 0, 0); } -void VerilatedFst::declBit(uint32_t code, uint32_t fidx, const char* name, int dtypenum, +void VerilatedFst::declBit(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, - VerilatedTraceSigType type, bool array, int arraynum) { - declare(code, name, dtypenum, direction, kind, type, array, arraynum, false, 0, 0); + VerilatedTraceSigType type) { + declare(code, name, dtypenum, direction, kind, type, false, -1, false, 0, 0); } -void VerilatedFst::declBus(uint32_t code, uint32_t fidx, const char* name, int dtypenum, +void VerilatedFst::declBus(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, - VerilatedTraceSigType type, bool array, int arraynum, int msb, - int lsb) { - declare(code, name, dtypenum, direction, kind, type, array, arraynum, true, msb, lsb); + VerilatedTraceSigType type, int msb, int lsb) { + declare(code, name, dtypenum, direction, kind, type, false, -1, true, msb, lsb); } -void VerilatedFst::declQuad(uint32_t code, uint32_t fidx, const char* name, int dtypenum, +void VerilatedFst::declQuad(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, - VerilatedTraceSigType type, bool array, int arraynum, int msb, - int lsb) { - declare(code, name, dtypenum, direction, kind, type, array, arraynum, true, msb, lsb); + VerilatedTraceSigType type, int msb, int lsb) { + declare(code, name, dtypenum, direction, kind, type, false, -1, true, msb, lsb); } -void VerilatedFst::declArray(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, - VerilatedTraceSigType type, bool array, int arraynum, int msb, - int lsb) { - declare(code, name, dtypenum, direction, kind, type, array, arraynum, true, msb, lsb); +void VerilatedFst::declWide(uint32_t code, const char* name, int dtypenum, + VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, + VerilatedTraceSigType type, int msb, int lsb) { + declare(code, name, dtypenum, direction, kind, type, false, -1, true, msb, lsb); } -void VerilatedFst::declDouble(uint32_t code, uint32_t fidx, const char* name, int dtypenum, +void VerilatedFst::declDouble(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, - VerilatedTraceSigType type, bool array, int arraynum) { - declare(code, name, dtypenum, direction, kind, type, array, arraynum, false, 63, 0); + VerilatedTraceSigType type) { + declare(code, name, dtypenum, direction, kind, type, false, -1, false, 63, 0); } +// versions to call when the sig is array member +void VerilatedFst::declEventArray(uint32_t code, const char* name, int dtypenum, + VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, + VerilatedTraceSigType type, int arraynum) { + declare(code, name, dtypenum, direction, kind, type, true, arraynum, false, 0, 0); +} +void VerilatedFst::declBitArray(uint32_t code, const char* name, int dtypenum, + VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, + VerilatedTraceSigType type, int arraynum) { + declare(code, name, dtypenum, direction, kind, type, true, arraynum, false, 0, 0); +} +void VerilatedFst::declBusArray(uint32_t code, const char* name, int dtypenum, + VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, + VerilatedTraceSigType type, int arraynum, int msb, int lsb) { + declare(code, name, dtypenum, direction, kind, type, true, arraynum, true, msb, lsb); +} +void VerilatedFst::declQuadArray(uint32_t code, const char* name, int dtypenum, + VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, + VerilatedTraceSigType type, int arraynum, int msb, int lsb) { + declare(code, name, dtypenum, direction, kind, type, true, arraynum, true, msb, lsb); +} +void VerilatedFst::declWideArray(uint32_t code, const char* name, int dtypenum, + VerilatedTraceSigDirection direction, VerilatedTraceSigKind kind, + VerilatedTraceSigType type, int arraynum, int msb, int lsb) { + declare(code, name, dtypenum, direction, kind, type, true, arraynum, true, msb, lsb); +} +void VerilatedFst::declDoubleArray(uint32_t code, const char* name, int dtypenum, + VerilatedTraceSigDirection direction, + VerilatedTraceSigKind kind, VerilatedTraceSigType type, + int arraynum) { + declare(code, name, dtypenum, direction, kind, type, true, arraynum, false, 63, 0); +} //============================================================================= // Get/commit trace buffer diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index b2394ab07..c4c4288d8 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -113,29 +113,72 @@ public: void pushPrefix(const char*, VerilatedTracePrefixType); void popPrefix(); - void declEvent(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum); - void declBit(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum); - void declBus(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum, int msb, int lsb); - void declQuad(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum, int msb, int lsb); - void declArray(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum, int msb, int lsb); - void declDouble(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum); + // versions to call when the sig is not array member + void declEvent(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType); + void declBit(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType); + void declBus(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType, int msb, int lsb); + void declQuad(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType, int msb, int lsb); + void declWide(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType, int msb, int lsb); + void declDouble(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType); + + // versions to call when the sig is array member + void declEventArray(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType, int arraynum); + void declBitArray(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType, int arraynum); + void declBusArray(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType, int arraynum, int msb, + int lsb); + void declQuadArray(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType, int arraynum, int msb, + int lsb); + void declWideArray(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType, int arraynum, int msb, + int lsb); + void declDoubleArray(uint32_t code, const char* name, int dtypenum, VerilatedTraceSigDirection, + VerilatedTraceSigKind, VerilatedTraceSigType, int arraynum); void declDTypeEnum(int dtypenum, const char* name, uint32_t elements, unsigned int minValbits, const char** itemNamesp, const char** itemValuesp); }; +// duck-typed interface to decl* methods +// We use macros in order to strip out unused args at compile time. +#define VL_TRACE_DECL_EVENT(tracep, code, fidx, name, dtypenum, dir, kind, type) \ + tracep->declEvent(code, name, dtypenum, dir, kind, type) +#define VL_TRACE_DECL_BIT(tracep, code, fidx, name, dtypenum, dir, kind, type) \ + tracep->declBit(code, name, dtypenum, dir, kind, type) +#define VL_TRACE_DECL_BUS(tracep, code, fidx, name, dtypenum, dir, kind, type, msb, lsb) \ + tracep->declBus(code, name, dtypenum, dir, kind, type, msb, lsb) +#define VL_TRACE_DECL_QUAD(tracep, code, fidx, name, dtypenum, dir, kind, type, msb, lsb) \ + tracep->declQuad(code, name, dtypenum, dir, kind, type, msb, lsb) +#define VL_TRACE_DECL_WIDE(tracep, code, fidx, name, dtypenum, dir, kind, type, msb, lsb) \ + tracep->declWide(code, name, dtypenum, dir, kind, type, msb, lsb) +#define VL_TRACE_DECL_DOUBLE(tracep, code, fidx, name, dtypenum, dir, kind, type) \ + tracep->declDouble(code, name, dtypenum, dir, kind, type) + +#define VL_TRACE_DECL_EVENT_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum) \ + tracep->declEventArray(code, name, dtypenum, dir, kind, type, arraynum) +#define VL_TRACE_DECL_BIT_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum) \ + tracep->declBitArray(code, name, dtypenum, dir, kind, type, arraynum) +#define VL_TRACE_DECL_BUS_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum, \ + msb, lsb) \ + tracep->declBusArray(code, name, dtypenum, dir, kind, type, arraynum, msb, lsb) +#define VL_TRACE_DECL_QUAD_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum, \ + msb, lsb) \ + tracep->declQuadArray(code, name, dtypenum, dir, kind, type, arraynum, msb, lsb) +#define VL_TRACE_DECL_WIDE_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum, \ + msb, lsb) \ + tracep->declWideArray(code, name, dtypenum, dir, kind, type, arraynum, msb, lsb) +#define VL_TRACE_DECL_DOUBLE_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum) \ + tracep->declDoubleArray(code, name, dtypenum, dir, kind, type, arraynum) + #ifndef DOXYGEN // Declare specialization here as it's used in VerilatedFstC just below template <> diff --git a/include/verilated_saif_c.cpp b/include/verilated_saif_c.cpp index 83237bb2f..bcec00c76 100644 --- a/include/verilated_saif_c.cpp +++ b/include/verilated_saif_c.cpp @@ -547,42 +547,53 @@ void VerilatedSaif::declare(const uint32_t code, uint32_t fidx, const char* name arraynum); } -void VerilatedSaif::declEvent(const uint32_t code, const uint32_t fidx, const char* name, - const int dtypenum, const VerilatedTraceSigDirection, - const VerilatedTraceSigKind, const VerilatedTraceSigType, - const bool array, const int arraynum) { - declare(code, fidx, name, "event", array, arraynum, false, 0, 0); +// versions to call when the sig is not array member +void VerilatedSaif::declEvent(const uint32_t code, const uint32_t fidx, const char* name) { + declare(code, fidx, name, "event", false, -1, false, 0, 0); } - -void VerilatedSaif::declBit(const uint32_t code, const uint32_t fidx, const char* name, - const int dtypenum, const VerilatedTraceSigDirection, - const VerilatedTraceSigKind, const VerilatedTraceSigType, - const bool array, const int arraynum) { - declare(code, fidx, name, "wire", array, arraynum, false, 0, 0); +void VerilatedSaif::declBit(const uint32_t code, const uint32_t fidx, const char* name) { + declare(code, fidx, name, "wire", false, -1, false, 0, 0); } void VerilatedSaif::declBus(const uint32_t code, const uint32_t fidx, const char* name, - const int dtypenum, const VerilatedTraceSigDirection, - const VerilatedTraceSigKind, const VerilatedTraceSigType, - const bool array, const int arraynum, const int msb, const int lsb) { - declare(code, fidx, name, "wire", array, arraynum, true, msb, lsb); + const int msb, const int lsb) { + declare(code, fidx, name, "wire", false, -1, true, msb, lsb); } void VerilatedSaif::declQuad(const uint32_t code, const uint32_t fidx, const char* name, - const int dtypenum, const VerilatedTraceSigDirection, - const VerilatedTraceSigKind, const VerilatedTraceSigType, - const bool array, const int arraynum, const int msb, const int lsb) { - declare(code, fidx, name, "wire", array, arraynum, true, msb, lsb); + const int msb, const int lsb) { + declare(code, fidx, name, "wire", false, -1, true, msb, lsb); } -void VerilatedSaif::declArray(const uint32_t code, const uint32_t fidx, const char* name, - const int dtypenum, const VerilatedTraceSigDirection, - const VerilatedTraceSigKind, const VerilatedTraceSigType, - const bool array, const int arraynum, const int msb, const int lsb) { - declare(code, fidx, name, "wire", array, arraynum, true, msb, lsb); +void VerilatedSaif::declWide(const uint32_t code, const uint32_t fidx, const char* name, + const int msb, const int lsb) { + declare(code, fidx, name, "wire", false, -1, true, msb, lsb); } -void VerilatedSaif::declDouble(const uint32_t code, const uint32_t fidx, const char* name, - const int dtypenum, const VerilatedTraceSigDirection, - const VerilatedTraceSigKind, const VerilatedTraceSigType, - const bool array, const int arraynum) { - declare(code, fidx, name, "real", array, arraynum, false, 63, 0); +void VerilatedSaif::declDouble(const uint32_t code, const uint32_t fidx, const char* name) { + declare(code, fidx, name, "real", false, -1, false, 63, 0); +} + +// versions to call when the sig is array member +void VerilatedSaif::declEventArray(const uint32_t code, const uint32_t fidx, const char* name, + const int arraynum) { + declare(code, fidx, name, "event", true, arraynum, false, 0, 0); +} +void VerilatedSaif::declBitArray(const uint32_t code, const uint32_t fidx, const char* name, + const int arraynum) { + declare(code, fidx, name, "wire", true, arraynum, false, 0, 0); +} +void VerilatedSaif::declBusArray(const uint32_t code, const uint32_t fidx, const char* name, + const int arraynum, const int msb, const int lsb) { + declare(code, fidx, name, "wire", true, arraynum, true, msb, lsb); +} +void VerilatedSaif::declQuadArray(const uint32_t code, const uint32_t fidx, const char* name, + const int arraynum, const int msb, const int lsb) { + declare(code, fidx, name, "wire", true, arraynum, true, msb, lsb); +} +void VerilatedSaif::declWideArray(const uint32_t code, const uint32_t fidx, const char* name, + const int arraynum, const int msb, const int lsb) { + declare(code, fidx, name, "wire", true, arraynum, true, msb, lsb); +} +void VerilatedSaif::declDoubleArray(const uint32_t code, const uint32_t fidx, const char* name, + const int arraynum) { + declare(code, fidx, name, "real", true, arraynum, false, 63, 0); } //============================================================================= diff --git a/include/verilated_saif_c.h b/include/verilated_saif_c.h index 28f35166c..f9ba20731 100644 --- a/include/verilated_saif_c.h +++ b/include/verilated_saif_c.h @@ -146,26 +146,57 @@ public: void pushPrefix(const char*, VerilatedTracePrefixType); void popPrefix(); - void declEvent(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum); - void declBit(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum); - void declBus(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum, int msb, int lsb); - void declQuad(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum, int msb, int lsb); - void declArray(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum, int msb, int lsb); - void declDouble(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum); + // versions to call when the sig is not array member + void declEvent(uint32_t code, uint32_t fidx, const char* name); + void declBit(uint32_t code, uint32_t fidx, const char* name); + void declBus(uint32_t code, uint32_t fidx, const char* name, int msb, int lsb); + void declQuad(uint32_t code, uint32_t fidx, const char* name, int msb, int lsb); + void declWide(uint32_t code, uint32_t fidx, const char* name, int msb, int lsb); + void declDouble(uint32_t code, uint32_t fidx, const char* name); + + // versions to call when the sig is array member + void declEventArray(uint32_t code, uint32_t fidx, const char* name, int arraynum); + void declBitArray(uint32_t code, uint32_t fidx, const char* name, int arraynum); + void declBusArray(uint32_t code, uint32_t fidx, const char* name, int arraynum, int msb, + int lsb); + void declQuadArray(uint32_t code, uint32_t fidx, const char* name, int arraynum, int msb, + int lsb); + void declWideArray(uint32_t code, uint32_t fidx, const char* name, int arraynum, int msb, + int lsb); + void declDoubleArray(uint32_t code, uint32_t fidx, const char* name, int arraynum); }; +// duck-typed interface to decl* methods +// We use macros in order to strip out unused args at compile time. +#define VL_TRACE_DECL_EVENT(tracep, code, fidx, name, dtypenum, dir, kind, type) \ + tracep->declEvent(code, fidx, name) +#define VL_TRACE_DECL_BIT(tracep, code, fidx, name, dtypenum, dir, kind, type) \ + tracep->declBit(code, fidx, name) +#define VL_TRACE_DECL_BUS(tracep, code, fidx, name, dtypenum, dir, kind, type, msb, lsb) \ + tracep->declBus(code, fidx, name, msb, lsb) +#define VL_TRACE_DECL_QUAD(tracep, code, fidx, name, dtypenum, dir, kind, type, msb, lsb) \ + tracep->declQuad(code, fidx, name, msb, lsb) +#define VL_TRACE_DECL_WIDE(tracep, code, fidx, name, dtypenum, dir, kind, type, msb, lsb) \ + tracep->declWide(code, fidx, name, msb, lsb) +#define VL_TRACE_DECL_DOUBLE(tracep, code, fidx, name, dtypenum, dir, kind, type) \ + tracep->declDouble(code, fidx, name) + +#define VL_TRACE_DECL_EVENT_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum) \ + tracep->declEventArray(code, fidx, name, arraynum) +#define VL_TRACE_DECL_BIT_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum) \ + tracep->declBitArray(code, fidx, name, arraynum) +#define VL_TRACE_DECL_BUS_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum, \ + msb, lsb) \ + tracep->declBusArray(code, fidx, name, arraynum, msb, lsb) +#define VL_TRACE_DECL_QUAD_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum, \ + msb, lsb) \ + tracep->declQuadArray(code, fidx, name, arraynum, msb, lsb) +#define VL_TRACE_DECL_WIDE_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum, \ + msb, lsb) \ + tracep->declWideArray(code, fidx, name, arraynum, msb, lsb) +#define VL_TRACE_DECL_DOUBLE_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum) \ + tracep->declDoubleArray(code, fidx, name, arraynum) + #ifndef DOXYGEN // Declare specialization here as it's used in VerilatedSaifC just below template <> diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index 7ceb04fc3..d36cb85da 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -451,35 +451,44 @@ void VerilatedVcd::declare(uint32_t code, const char* name, const char* wirep, b printStr(decl.c_str()); } -void VerilatedVcd::declEvent(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, - VerilatedTraceSigType, bool array, int arraynum) { - declare(code, name, "event", array, arraynum, false, 0, 0); +// versions to call when the sig is not array member +void VerilatedVcd::declEvent(uint32_t code, const char* name) { + declare(code, name, "event", false, -1, false, 0, 0); } -void VerilatedVcd::declBit(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, - VerilatedTraceSigType, bool array, int arraynum) { - declare(code, name, "wire", array, arraynum, false, 0, 0); +void VerilatedVcd::declBit(uint32_t code, const char* name) { + declare(code, name, "wire", false, -1, false, 0, 0); } -void VerilatedVcd::declBus(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, - VerilatedTraceSigType, bool array, int arraynum, int msb, int lsb) { - declare(code, name, "wire", array, arraynum, true, msb, lsb); +void VerilatedVcd::declBus(uint32_t code, const char* name, int msb, int lsb) { + declare(code, name, "wire", false, -1, true, msb, lsb); } -void VerilatedVcd::declQuad(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, - VerilatedTraceSigType, bool array, int arraynum, int msb, int lsb) { - declare(code, name, "wire", array, arraynum, true, msb, lsb); +void VerilatedVcd::declQuad(uint32_t code, const char* name, int msb, int lsb) { + declare(code, name, "wire", false, -1, true, msb, lsb); } -void VerilatedVcd::declArray(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, - VerilatedTraceSigType, bool array, int arraynum, int msb, int lsb) { - declare(code, name, "wire", array, arraynum, true, msb, lsb); +void VerilatedVcd::declWide(uint32_t code, const char* name, int msb, int lsb) { + declare(code, name, "wire", false, -1, true, msb, lsb); } -void VerilatedVcd::declDouble(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, - VerilatedTraceSigType, bool array, int arraynum) { - declare(code, name, "real", array, arraynum, false, 63, 0); +void VerilatedVcd::declDouble(uint32_t code, const char* name) { + declare(code, name, "real", false, -1, false, 63, 0); +} + +// versions to call when the sig is array member +void VerilatedVcd::declEventArray(uint32_t code, const char* name, int arraynum) { + declare(code, name, "event", true, arraynum, false, 0, 0); +} +void VerilatedVcd::declBitArray(uint32_t code, const char* name, int arraynum) { + declare(code, name, "wire", true, arraynum, false, 0, 0); +} +void VerilatedVcd::declBusArray(uint32_t code, const char* name, int arraynum, int msb, int lsb) { + declare(code, name, "wire", true, arraynum, true, msb, lsb); +} +void VerilatedVcd::declQuadArray(uint32_t code, const char* name, int arraynum, int msb, int lsb) { + declare(code, name, "wire", true, arraynum, true, msb, lsb); +} +void VerilatedVcd::declWideArray(uint32_t code, const char* name, int arraynum, int msb, int lsb) { + declare(code, name, "wire", true, arraynum, true, msb, lsb); +} +void VerilatedVcd::declDoubleArray(uint32_t code, const char* name, int arraynum) { + declare(code, name, "real", true, arraynum, false, 63, 0); } //============================================================================= diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 3942055a1..829bbc70b 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -137,26 +137,55 @@ public: void pushPrefix(const char*, VerilatedTracePrefixType); void popPrefix(); - void declEvent(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum); - void declBit(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum); - void declBus(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum, int msb, int lsb); - void declQuad(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum, int msb, int lsb); - void declArray(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum, int msb, int lsb); - void declDouble(uint32_t code, uint32_t fidx, const char* name, int dtypenum, - VerilatedTraceSigDirection, VerilatedTraceSigKind, VerilatedTraceSigType, - bool array, int arraynum); + // versions to call when the sig is not array member + void declEvent(uint32_t code, const char* name); + void declBit(uint32_t code, const char* name); + void declBus(uint32_t code, const char* name, int msb, int lsb); + void declQuad(uint32_t code, const char* name, int msb, int lsb); + void declWide(uint32_t code, const char* name, int msb, int lsb); + void declDouble(uint32_t code, const char* name); + + // versions to call when the sig is array member + void declEventArray(uint32_t code, const char* name, int arraynum); + void declBitArray(uint32_t code, const char* name, int arraynum); + void declBusArray(uint32_t code, const char* name, int arraynum, int msb, int lsb); + void declQuadArray(uint32_t code, const char* name, int arraynum, int msb, int lsb); + void declWideArray(uint32_t code, const char* name, int arraynum, int msb, int lsb); + void declDoubleArray(uint32_t code, const char* name, int arraynum); }; +// duck-typed interface to decl* methods +// We use macros in order to strip out unused args at compile time. + +#define VL_TRACE_DECL_EVENT(tracep, code, fidx, name, dtypenum, dir, kind, type) \ + tracep->declEvent(code, name) +#define VL_TRACE_DECL_BIT(tracep, code, fidx, name, dtypenum, dir, kind, type) \ + tracep->declBit(code, name) +#define VL_TRACE_DECL_BUS(tracep, code, fidx, name, dtypenum, dir, kind, type, msb, lsb) \ + tracep->declBus(code, name, msb, lsb) +#define VL_TRACE_DECL_QUAD(tracep, code, fidx, name, dtypenum, dir, kind, type, msb, lsb) \ + tracep->declQuad(code, name, msb, lsb) +#define VL_TRACE_DECL_WIDE(tracep, code, fidx, name, dtypenum, dir, kind, type, msb, lsb) \ + tracep->declWide(code, name, msb, lsb) +#define VL_TRACE_DECL_DOUBLE(tracep, code, fidx, name, dtypenum, dir, kind, type) \ + tracep->declDouble(code, name) + +#define VL_TRACE_DECL_EVENT_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum) \ + tracep->declEventArray(code, name, arraynum) +#define VL_TRACE_DECL_BIT_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum) \ + tracep->declBitArray(code, name, arraynum) +#define VL_TRACE_DECL_BUS_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum, \ + msb, lsb) \ + tracep->declBusArray(code, name, arraynum, msb, lsb) +#define VL_TRACE_DECL_QUAD_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum, \ + msb, lsb) \ + tracep->declQuadArray(code, name, arraynum, msb, lsb) +#define VL_TRACE_DECL_WIDE_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum, \ + msb, lsb) \ + tracep->declWideArray(code, name, arraynum, msb, lsb) +#define VL_TRACE_DECL_DOUBLE_ARRAY(tracep, code, fidx, name, dtypenum, dir, kind, type, arraynum) \ + tracep->declDoubleArray(code, name, arraynum) + #ifndef DOXYGEN // Declare specialization here as it's used in VerilatedFstC just below template <> diff --git a/src/V3EmitCImp.cpp b/src/V3EmitCImp.cpp index 8300a01d3..d58fb3393 100644 --- a/src/V3EmitCImp.cpp +++ b/src/V3EmitCImp.cpp @@ -627,21 +627,27 @@ class EmitCTrace final : public EmitCFunc { void emitTraceInitOne(const AstTraceDecl* nodep, int enumNum) { if (nodep->dtypep()->basicp()->isDouble()) { - puts("tracep->declDouble("); + puts("VL_TRACE_DECL_DOUBLE"); } else if (nodep->isWide()) { - puts("tracep->declArray("); + puts("VL_TRACE_DECL_WIDE"); } else if (nodep->isQuad()) { - puts("tracep->declQuad("); + puts("VL_TRACE_DECL_QUAD"); } else if (nodep->bitRange().ranged()) { - puts("tracep->declBus("); + puts("VL_TRACE_DECL_BUS"); } else if (nodep->dtypep()->basicp()->isEvent()) { - puts("tracep->declEvent("); + puts("VL_TRACE_DECL_EVENT"); } else { - puts("tracep->declBit("); + puts("VL_TRACE_DECL_BIT"); + } + + if (nodep->arrayRange().ranged()) { + puts("_ARRAY(tracep"); + } else { + puts("(tracep"); } // Code - puts("c+" + cvtToStr(nodep->code())); + puts(",c+" + cvtToStr(nodep->code())); if (nodep->arrayRange().ranged()) puts("+i*" + cvtToStr(nodep->widthWords())); // Function index @@ -676,9 +682,7 @@ class EmitCTrace final : public EmitCFunc { // Array range if (nodep->arrayRange().ranged()) { - puts(", true,(i+" + cvtToStr(nodep->arrayRange().lo()) + ")"); - } else { - puts(", false,-1"); + puts(", (i+" + cvtToStr(nodep->arrayRange().lo()) + ")"); } // Bit range From 139bdc1ae3e526d4794e265daacaf1d40eeebf8c Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 28 Feb 2026 14:54:39 +0000 Subject: [PATCH 010/340] Optimize function call return value temporaries (#7152) --- src/V3Task.cpp | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 387ff5de1..a40cade63 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -642,6 +642,15 @@ class TaskVisitor final : public VNVisitor { } } + bool hasRefArgument(AstNodeFTask* nodep) { + for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (AstVar* const varp = VN_CAST(stmtp, Var)) { + if (varp->isRef() || varp->isConstRef()) return true; + } + } + return false; + } + AstNode* createInlinedFTask(AstNodeFTaskRef* refp, const string& namePrefix, AstVarScope* outvscp) { // outvscp is the variable for functions only, if nullptr, it's a task @@ -1543,9 +1552,25 @@ class TaskVisitor final : public VNVisitor { // Create output variable AstVarScope* outvscp = nullptr; if (nodep->taskp()->isFunction()) { - // Not that it's a FUNCREF, but that we're calling a function (perhaps as a task) - outvscp - = createVarScope(VN_AS(nodep->taskp()->fvarp(), Var), namePrefix + "__Vfuncout"); + AstVar* const fvarp = VN_AS(nodep->taskp()->fvarp(), Var); + // If the call is on the RHS of a simple assignment 'lhs = call()', + // the LHS variable can be reused as the output variable iff it has + // the same type, and the function does not read the output variable itself. + // This can be proven cheaply if the LHS is an automatic variable and the + // function does not have any ref arguments. This arises a lot after V3LiftExpr. + if (AstAssign* const assignp = VN_CAST(nodep->backp(), Assign)) { + if (AstVarRef* const lhsp = VN_CAST(assignp->lhsp(), VarRef)) { + AstVarScope* const vscp = lhsp->varScopep(); + if (vscp->varp()->lifetime().isAutomatic() + && vscp->varp()->dtypep()->skipRefp()->sameTree( + fvarp->dtypep()->skipRefp()) + && !hasRefArgument(nodep->taskp())) { + outvscp = vscp; + } + } + } + // Otherwise create a new variable for the result + if (!outvscp) outvscp = createVarScope(fvarp, namePrefix + "__Vfuncout"); } // Create cloned statements AstNode* beginp; From face700f2932f7eed012ad3846e589cef0501425 Mon Sep 17 00:00:00 2001 From: Pawel Kojma Date: Sat, 28 Feb 2026 15:55:06 +0100 Subject: [PATCH 011/340] Improve assignment-compatibility type check (#2843) (#5666) (#7052) --- src/V3AstNodeDType.h | 1 + src/V3Width.cpp | 109 ++++++++++++++++-- .../t/t_assignment_compatibility_bad.out | 64 ++++++++++ .../t/t_assignment_compatibility_bad.py | 16 +++ .../t/t_assignment_compatibility_bad.v | 35 ++++++ test_regress/t/t_assignment_pin_bad.out | 12 ++ test_regress/t/t_assignment_pin_bad.py | 16 +++ test_regress/t/t_assignment_pin_bad.v | 32 +++++ test_regress/t/t_fourstate_assign_bad.out | 10 +- test_regress/t/t_mem_slice_bad.out | 4 + 10 files changed, 287 insertions(+), 12 deletions(-) create mode 100644 test_regress/t/t_assignment_compatibility_bad.out create mode 100755 test_regress/t/t_assignment_compatibility_bad.py create mode 100644 test_regress/t/t_assignment_compatibility_bad.v create mode 100644 test_regress/t/t_assignment_pin_bad.out create mode 100755 test_regress/t/t_assignment_pin_bad.py create mode 100644 test_regress/t/t_assignment_pin_bad.v diff --git a/src/V3AstNodeDType.h b/src/V3AstNodeDType.h index 4d5bd6046..928402b2b 100644 --- a/src/V3AstNodeDType.h +++ b/src/V3AstNodeDType.h @@ -129,6 +129,7 @@ public: // Ideally an IEEE $typename virtual string prettyDTypeName(bool) const { return prettyTypeName(); } string prettyDTypeNameQ() const { return "'" + prettyDTypeName(false) + "'"; } + string stateDTypeName() const { return this->isFourstate() ? "(4-state)" : "(2-state)"; } // // Changing the width may confuse the data type resolution, so must clear // TypeTable cache after use. diff --git a/src/V3Width.cpp b/src/V3Width.cpp index a2e050928..aa6be6838 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -5797,13 +5797,12 @@ class WidthVisitor final : public VNVisitor { // IEEE 1800-2023 7.6: For unpacked arrays to be assignment compatible, // the element types shall be equivalent (IEEE 1800-2023 6.22.2). - // Check specifically for 2-state vs 4-state mismatch for unpacked array - // to unpacked array assignments, as this is a common IEEE compliance issue. // Note: Streaming operators and string literals have implicit conversion rules. if (nodep->rhsp()->dtypep()) { // May be null on earlier errors const AstNodeDType* const lhsDtp = lhsDTypep->skipRefp(); const AstNodeDType* const rhsDtp = nodep->rhsp()->dtypep()->skipRefp(); - // Only check unpacked array to unpacked array assignments + // Only check if number of states match for unpacked array to unpacked array + // assignments const bool lhsIsUnpackArray = VN_IS(lhsDtp, UnpackArrayDType) || VN_IS(lhsDtp, DynArrayDType) || VN_IS(lhsDtp, QueueDType) || VN_IS(lhsDtp, AssocArrayDType); @@ -5812,15 +5811,17 @@ class WidthVisitor final : public VNVisitor { || VN_IS(rhsDtp, QueueDType) || VN_IS(rhsDtp, AssocArrayDType); if (lhsIsUnpackArray && rhsIsUnpackArray) { if (lhsDtp->isFourstate() != rhsDtp->isFourstate()) { - nodep->v3error( - "Assignment between 2-state and 4-state types requires " - "equivalent element types (IEEE 1800-2023 6.22.2, 7.6)\n" - << nodep->warnMore() << "... LHS type: " << lhsDtp->prettyDTypeNameQ() - << (lhsDtp->isFourstate() ? " (4-state)" : " (2-state)") << "\n" - << nodep->warnMore() << "... RHS type: " << rhsDtp->prettyDTypeNameQ() - << (rhsDtp->isFourstate() ? " (4-state)" : " (2-state)")); + nodep->v3error("Assignment between 2-state and 4-state types requires " + "equivalent element types (IEEE 1800-2023 6.22.2, 7.6)\n" + << nodep->warnMore() + << "... Left-hand type: " << lhsDtp->prettyDTypeNameQ() + << lhsDtp->stateDTypeName() << "\n" + << nodep->warnMore() << "... Right-hand type: " + << rhsDtp->prettyDTypeNameQ() << rhsDtp->stateDTypeName()); } } + checkUnpackedArrayAssignmentCompatible( + nodep, VN_CAST(nodep->lhsp(), NodeVarRef), VN_CAST(nodep->rhsp(), NodeVarRef)); } iterateCheckAssign(nodep, "Assign RHS", nodep->rhsp(), FINAL, lhsDTypep); @@ -6433,6 +6434,11 @@ class WidthVisitor final : public VNVisitor { << (exprArrayp ? "" : " not") << " an array. (IEEE 1800-2023 7.6)"); UINFO(1, " Related lo: " << modDTypep); UINFO(1, " Related hi: " << conDTypep); + } else { + checkUnpackedArrayAssignmentCompatible( + nodep, nodep->modVarp(), VN_CAST(nodep->exprp(), NodeVarRef)); + UINFO(1, " Related lo: " << modDTypep); + UINFO(1, " Related hi: " << conDTypep); } iterateCheckAssign(nodep, "pin connection", nodep->exprp(), FINAL, subDTypep); } @@ -8055,6 +8061,89 @@ class WidthVisitor final : public VNVisitor { } return false; } + // Checks whether two types are assignment-compatible according to IEEE 1800-2023 7.6 + // Currently, this function only supports variables, which are of following types: + // - Fixed-size unpacked array + // - Dynamic unpacked array + // - Associative array + template + void checkUnpackedArrayAssignmentCompatible(const AstNode* nodep, const T* const lhsRefp, + const N* const rhsRefp) { + static_assert( + (std::is_same::value || std::is_same::value) + && (std::is_same::value || std::is_same::value), + "Unsupported types provided."); + if (!lhsRefp || !rhsRefp) return; + string lhsName, rhsName; + if (VN_IS(nodep, Pin)) { + lhsName = std::string{"Pin"}; + rhsName = std::string{"Expression"}; + } else { + lhsName = std::string{"Left-hand"}; + rhsName = std::string{"Right-hand"}; + } + + const AstNodeDType* const lhsDtp = lhsRefp->dtypep()->skipRefp(); + const AstNodeDType* const rhsDtp = rhsRefp->dtypep()->skipRefp(); + const bool isLhsAggregate = lhsDtp->isAggregateType(); + const bool isRhsAggregate = rhsDtp->isAggregateType(); + if (!isLhsAggregate && !isRhsAggregate) return; + if (isLhsAggregate ^ isRhsAggregate) { + nodep->v3error( + "Illegal assignment: types are not assignment compatible (IEEE 1800-2023 7.6)\n" + << nodep->warnMore() << "... " << lhsName << " data type: " + << lhsDtp->prettyDTypeNameQ() << " " << lhsDtp->stateDTypeName() << "\n" + << nodep->warnMore() << "... " << rhsName << " data type: " + << rhsDtp->prettyDTypeNameQ() << " " << rhsDtp->stateDTypeName() << "\n"); + return; + } else if (VN_IS(lhsDtp, QueueDType) && VN_IS(rhsDtp, EmptyQueueDType)) { + return; + } + std::pair lhsDim = lhsDtp->dimensions(false), + rhsDim = rhsDtp->dimensions(false); + // Check if unpacked array dimensions are matching + if (lhsDim.second != rhsDim.second) { + nodep->v3error("Illegal assignment: Unmatched number of unpacked dimensions " + << "(" << lhsDim.second << " vs " << rhsDim.second << ")"); + return; + } + + const AstNodeDType* lhsDtpIterp = lhsDtp; + const AstNodeDType* rhsDtpIterp = rhsDtp; + // Sizes of fixed-size arrays should be the same + // Dynamic-sized arrays are always assignable + for (uint32_t dim = 0; dim < rhsDim.second; dim++) { + if (const AstNodeArrayDType* rhsArrayp = VN_CAST(rhsDtpIterp, NodeArrayDType)) { + if (const AstNodeArrayDType* lhsArrayp = VN_CAST(lhsDtpIterp, NodeArrayDType)) { + if (lhsArrayp->elementsConst() != rhsArrayp->elementsConst()) { + nodep->v3error("Illegal assignment: Unmatched array sizes in dimension " + << dim << " " << "(" << lhsArrayp->elementsConst() << " vs " + << rhsArrayp->elementsConst() << ")"); + return; + } + } + } + // Associative arrays are compatible only with each other + if (VN_IS(lhsDtpIterp, AssocArrayDType) ^ VN_IS(rhsDtpIterp, AssocArrayDType)) { + nodep->v3error("Illegal assignment: Associative arrays are assignment compatible " + "only with associative arrays (IEEE 1800-2023 7.6)"); + + return; + } + lhsDtpIterp = lhsDtpIterp->subDTypep(); + rhsDtpIterp = rhsDtpIterp->subDTypep(); + } + // Element types of source and target shall be equivalent + if (!isEquivalentDType(lhsDtpIterp, rhsDtpIterp)) { + nodep->v3error("Illegal assignment: Array element types are not equivalent (IEEE " + "1800-2023 6.22.2)\n" + << nodep->warnMore() << "... " << lhsName << " data type: " + << lhsDtp->prettyDTypeNameQ() << " " << lhsDtp->stateDTypeName() << "\n" + << nodep->warnMore() << "... " << rhsName + << " data type: " << rhsDtp->prettyDTypeNameQ() << " " + << rhsDtp->stateDTypeName() << "\n"); + } + } void checkClassAssign(const AstNode* nodep, const char* side, AstNode* rhsp, AstNodeDType* const lhsDTypep) { UASSERT_OBJ(rhsp->dtypep(), rhsp, "Node has no type"); diff --git a/test_regress/t/t_assignment_compatibility_bad.out b/test_regress/t/t_assignment_compatibility_bad.out new file mode 100644 index 000000000..fdb138927 --- /dev/null +++ b/test_regress/t/t_assignment_compatibility_bad.out @@ -0,0 +1,64 @@ +%Error: t/t_assignment_compatibility_bad.v:25:24: Illegal assignment: Unmatched array sizes in dimension 0 (3 vs 2) + : ... note: In instance 't' + 25 | logic unpackedF[3] = unpackedA; + | ^~~~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_assignment_compatibility_bad.v:26:31: Assignment between 2-state and 4-state types requires equivalent element types (IEEE 1800-2023 6.22.2, 7.6) + : ... note: In instance 't' + : ... Left-hand type: 'bit$[0:1]'(2-state) + : ... Right-hand type: 'logic$[0:1]'(4-state) + 26 | bit unpackedG[2] = unpackedB[0:1]; + | ^ +%Error: t/t_assignment_compatibility_bad.v:28:20: Illegal assignment: Unmatched array sizes in dimension 0 (3 vs 2) + : ... note: In instance 't' + 28 | assign unpackedB = unpackedA; + | ^ +%Error: t/t_assignment_compatibility_bad.v:29:20: Illegal assignment: Unmatched number of unpacked dimensions (1 vs 2) + : ... note: In instance 't' + 29 | assign unpackedB = unpackedC; + | ^ +%Error: t/t_assignment_compatibility_bad.v:30:20: Illegal assignment: Unmatched array sizes in dimension 0 (4 vs 3) + : ... note: In instance 't' + 30 | assign unpackedD = unpackedC; + | ^ +%Error: t/t_assignment_compatibility_bad.v:31:20: Assignment between 2-state and 4-state types requires equivalent element types (IEEE 1800-2023 6.22.2, 7.6) + : ... note: In instance 't' + : ... Left-hand type: 'struct{}$unit::struct_t$[0:3][0:1]'(2-state) + : ... Right-hand type: 'logic$[0:3][0:1]'(4-state) + 31 | assign unpackedE = unpackedD; + | ^ +%Error: t/t_assignment_compatibility_bad.v:31:20: Illegal assignment: Array element types are not equivalent (IEEE 1800-2023 6.22.2) + : ... note: In instance 't' + : ... Left-hand data type: 'struct{}$unit::struct_t$[0:3][0:1]' (2-state) + : ... Right-hand data type: 'logic$[0:3][0:1]' (4-state) + 31 | assign unpackedE = unpackedD; + | ^ +%Warning-WIDTHEXPAND: t/t_assignment_compatibility_bad.v:31:20: Operator ASSIGNW expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'unpackedD' generates 1 bits. + : ... note: In instance 't' + 31 | assign unpackedE = unpackedD; + | ^ + ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest + ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. +%Error: t/t_assignment_compatibility_bad.v:32:23: Illegal assignment: types are not assignment compatible (IEEE 1800-2023 7.6) + : ... note: In instance 't' + : ... Left-hand data type: 'logic' (4-state) + : ... Right-hand data type: 'logic$[0:1]' (4-state) + 32 | assign nonAggregate = unpackedA; + | ^ +%Error: t/t_assignment_compatibility_bad.v:33:20: Assignment between 2-state and 4-state types requires equivalent element types (IEEE 1800-2023 6.22.2, 7.6) + : ... note: In instance 't' + : ... Left-hand type: 'logic$[0:1]'(4-state) + : ... Right-hand type: 'logic$[string]'(2-state) + 33 | assign unpackedA = assocArrayA; + | ^ +%Error: t/t_assignment_compatibility_bad.v:33:20: Illegal assignment: Associative arrays are assignment compatible only with associative arrays (IEEE 1800-2023 7.6) + : ... note: In instance 't' + 33 | assign unpackedA = assocArrayA; + | ^ +%Error: t/t_assignment_compatibility_bad.v:34:17: Illegal assignment: Array element types are not equivalent (IEEE 1800-2023 6.22.2) + : ... note: In instance 't' + : ... Left-hand data type: 'logic$[$]' (2-state) + : ... Right-hand data type: 'bit$[$]' (2-state) + 34 | assign queueA = queueB; + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_assignment_compatibility_bad.py b/test_regress/t/t_assignment_compatibility_bad.py new file mode 100755 index 000000000..f3bbcad9d --- /dev/null +++ b/test_regress/t/t_assignment_compatibility_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assignment_compatibility_bad.v b/test_regress/t/t_assignment_compatibility_bad.v new file mode 100644 index 000000000..9cbba8569 --- /dev/null +++ b/test_regress/t/t_assignment_compatibility_bad.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog +// +// Assignment compatibility test. +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +typedef struct packed { + int a; + int b; +} struct_t; + +module t; + + logic unpackedA[2]; + logic unpackedB[3]; + logic unpackedC[3][2]; + logic unpackedD[4][2]; + struct_t unpackedE[4][2]; + logic nonAggregate; + logic assocArrayA[string]; + logic queueA[$]; + bit queueB[$]; + logic unpackedF[3] = unpackedA; + bit unpackedG[2] = unpackedB[0:1]; + + assign unpackedB = unpackedA; + assign unpackedB = unpackedC; + assign unpackedD = unpackedC; + assign unpackedE = unpackedD; + assign nonAggregate = unpackedA; + assign unpackedA = assocArrayA; + assign queueA = queueB; +endmodule diff --git a/test_regress/t/t_assignment_pin_bad.out b/test_regress/t/t_assignment_pin_bad.out new file mode 100644 index 000000000..c29062b73 --- /dev/null +++ b/test_regress/t/t_assignment_pin_bad.out @@ -0,0 +1,12 @@ +%Error: t/t_assignment_pin_bad.v:29:19: Illegal input port connection 'b', mismatch between port which is not an array, and expression which is an array. (IEEE 1800-2023 7.6) + : ... note: In instance 't' + 29 | test1 i_test1 (.b); + | ^ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_assignment_pin_bad.v:30:19: Illegal assignment: Array element types are not equivalent (IEEE 1800-2023 6.22.2) + : ... note: In instance 't' + : ... Pin data type: 'bit$[0:1]' (2-state) + : ... Expression data type: 'logic$[0:1]' (4-state) + 30 | test2 i_test2 (.b); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_assignment_pin_bad.py b/test_regress/t/t_assignment_pin_bad.py new file mode 100755 index 000000000..3160d0589 --- /dev/null +++ b/test_regress/t/t_assignment_pin_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_assignment_pin_bad.v b/test_regress/t/t_assignment_pin_bad.v new file mode 100644 index 000000000..2d0eddae9 --- /dev/null +++ b/test_regress/t/t_assignment_pin_bad.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module for SystemVerilog +// +// This file ONLY is placed under the Creative Commons Public Domain +// SPDX-FileCopyrightText: 2026 Antmicro +// SPDX-License-Identifier: CC0-1.0 + +module test1 ( + input logic b +); + logic do_something; + assign do_something = b; +endmodule + +module test2 ( + input bit b[2] +); + bit do_something[2]; + assign do_something = b; +endmodule + +module t ( + input logic a[2] // unpacked array +); + + logic b[2]; + + assign b = a; + + test1 i_test1 (.b); + test2 i_test2 (.b); + +endmodule diff --git a/test_regress/t/t_fourstate_assign_bad.out b/test_regress/t/t_fourstate_assign_bad.out index a43b8027e..284018659 100644 --- a/test_regress/t/t_fourstate_assign_bad.out +++ b/test_regress/t/t_fourstate_assign_bad.out @@ -1,8 +1,14 @@ %Error: t/t_fourstate_assign_bad.v:23:16: Assignment between 2-state and 4-state types requires equivalent element types (IEEE 1800-2023 6.22.2, 7.6) : ... note: In instance 't' - : ... LHS type: 'bit[7:0]$[3:0]' (2-state) - : ... RHS type: 'logic[7:0]$[3:0]' (4-state) + : ... Left-hand type: 'bit[7:0]$[3:0]'(2-state) + : ... Right-hand type: 'logic[7:0]$[3:0]'(4-state) 23 | arr_2state = arr_4state; | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: t/t_fourstate_assign_bad.v:23:16: Illegal assignment: Array element types are not equivalent (IEEE 1800-2023 6.22.2) + : ... note: In instance 't' + : ... Left-hand data type: 'bit[7:0]$[3:0]' (2-state) + : ... Right-hand data type: 'logic[7:0]$[3:0]' (4-state) + 23 | arr_2state = arr_4state; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mem_slice_bad.out b/test_regress/t/t_mem_slice_bad.out index 3aa57d7f1..3d62544dd 100644 --- a/test_regress/t/t_mem_slice_bad.out +++ b/test_regress/t/t_mem_slice_bad.out @@ -23,4 +23,8 @@ : ... note: In instance 't' 51 | active_command4[7:0] <= command_A4[8:0]; | ^ +%Error: t/t_mem_slice_bad.v:56:28: Illegal assignment: Unmatched array sizes in dimension 0 (9 vs 8) + : ... note: In instance 't' + 56 | active_command5[8:0] = command_A5[7:0]; + | ^ %Error: Exiting due to From 2ceea267e5fe3ab8dfaa0bf65ffb395870f28f79 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 28 Feb 2026 15:09:01 +0000 Subject: [PATCH 012/340] Fix eliminating assignments to DPI-read vaiables (#7158) --- src/V3AstNodeOther.h | 4 +++ src/V3AstNodes.cpp | 4 +++ src/V3Life.cpp | 1 + src/V3Task.cpp | 17 +++++++++---- test_regress/t/t_opt_life_dpi_read.cpp | 22 ++++++++++++++++ test_regress/t/t_opt_life_dpi_read.py | 18 +++++++++++++ test_regress/t/t_opt_life_dpi_read.v | 35 ++++++++++++++++++++++++++ 7 files changed, 96 insertions(+), 5 deletions(-) create mode 100644 test_regress/t/t_opt_life_dpi_read.cpp create mode 100755 test_regress/t/t_opt_life_dpi_read.py create mode 100644 test_regress/t/t_opt_life_dpi_read.v diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 4c3558ba8..f2c25e094 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -1933,6 +1933,7 @@ class AstVar final : public AstNode { bool m_isLatched : 1; // Not assigned in all control paths of combo always bool m_isForceable : 1; // May be forced/released externally from user C code bool m_isForcedByCode : 1; // May be forced/released from AstAssignForce/AstRelease + bool m_isReadByDpi : 1; // This variable can be read by a DPI Export bool m_isWrittenByDpi : 1; // This variable can be written by a DPI Export bool m_isWrittenBySuspendable : 1; // This variable can be written by a suspendable process bool m_ignorePostRead : 1; // Ignore reads in 'Post' blocks during ordering @@ -1987,6 +1988,7 @@ class AstVar final : public AstNode { m_isLatched = false; m_isForceable = false; m_isForcedByCode = false; + m_isReadByDpi = false; m_isWrittenByDpi = false; m_isWrittenBySuspendable = false; m_ignorePostRead = false; @@ -2152,6 +2154,8 @@ public: void setForceable() { m_isForceable = true; } void setForcedByCode() { m_isForcedByCode = true; } bool isForced() const { return m_isForceable || m_isForcedByCode; } + bool isReadByDpi() const { return m_isReadByDpi; } + void setReadByDpi() { m_isReadByDpi = true; } bool isWrittenByDpi() const { return m_isWrittenByDpi; } void setWrittenByDpi() { m_isWrittenByDpi = true; } bool isWrittenBySuspendable() const { return m_isWrittenBySuspendable; } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 5c14d9b47..7c98ab18e 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -2880,6 +2880,8 @@ void AstVar::dump(std::ostream& str) const { if (isSigPublic()) str << " [P]"; if (isSigUserRdPublic()) str << " [PRD]"; if (isSigUserRWPublic()) str << " [PWR]"; + if (isReadByDpi()) str << " [DPIRD]"; + if (isWrittenByDpi()) str << " [DPIWR]"; if (isInternal()) str << " [INTERNAL]"; if (isLatched()) str << " [LATCHED]"; if (isUsedLoopIdx()) str << " [LOOPIDX]"; @@ -2927,6 +2929,8 @@ void AstVar::dumpJson(std::ostream& str) const { if (dtypep()) dumpJsonStr(str, "dtypeName", dtypep()->name()); dumpJsonBoolFuncIf(str, isSigUserRdPublic); dumpJsonBoolFuncIf(str, isSigUserRWPublic); + dumpJsonBoolFuncIf(str, isReadByDpi); + dumpJsonBoolFuncIf(str, isWrittenByDpi); dumpJsonBoolFuncIf(str, isGParam); dumpJsonBoolFuncIf(str, isParam); dumpJsonBoolFuncIf(str, attrScBv); diff --git a/src/V3Life.cpp b/src/V3Life.cpp index 46fc197e9..52cca6bf3 100644 --- a/src/V3Life.cpp +++ b/src/V3Life.cpp @@ -129,6 +129,7 @@ public: const AstVar* const varp = vscp->varp(); // We don't optimize any public sigs if (varp->isSigPublic()) return; + if (varp->isReadByDpi()) return; if (varp->sensIfacep()) return; // Check the var entry, and remove if appropriate AstNodeStmt* const oldassp = entr.assignp(); diff --git a/src/V3Task.cpp b/src/V3Task.cpp index a40cade63..5f611d6be 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -1428,15 +1428,22 @@ class TaskVisitor final : public VNVisitor { // Mark non-local variables written by the exported function bool writesNonLocals = false; cfuncp->foreach([&writesNonLocals](AstVarRef* refp) { - if (refp->access().isReadOnly()) return; // Ignore read reference AstVar* const varp = refp->varScopep()->varp(); // We are ignoring function locals as they should not be referenced anywhere // outside the enclosing AstCFunc, hence they are irrelevant for code ordering. if (varp->isFuncLocal()) return; - // Mark it as written by DPI export - varp->setWrittenByDpi(); - // Remember we had some - writesNonLocals = true; + // Check if written + if (refp->access().isWriteOrRW()) { + // Mark it as written by DPI export + varp->setWrittenByDpi(); + // Remember we had some + writesNonLocals = true; + } + // Check if read + if (refp->access().isReadOrRW()) { + // Mark it as read by DPI export + varp->setReadByDpi(); + } }); // If this DPI export writes some non-local variables, set the DPI Export Trigger flag diff --git a/test_regress/t/t_opt_life_dpi_read.cpp b/test_regress/t/t_opt_life_dpi_read.cpp new file mode 100644 index 000000000..2fd744c6d --- /dev/null +++ b/test_regress/t/t_opt_life_dpi_read.cpp @@ -0,0 +1,22 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#include "svdpi.h" + +#include + +extern "C" int getDpi(); + +extern "C" int getViaDpi() { + const int value = getDpi(); + std::cout << "getDpi " << value << std::endl; + return value; +} diff --git a/test_regress/t/t_opt_life_dpi_read.py b/test_regress/t/t_opt_life_dpi_read.py new file mode 100755 index 000000000..16a308b26 --- /dev/null +++ b/test_regress/t/t_opt_life_dpi_read.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--binary", "--stats", test.top_filename.replace(".v", ".cpp")]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_opt_life_dpi_read.v b/test_regress/t/t_opt_life_dpi_read.v new file mode 100644 index 000000000..e35d61ccf --- /dev/null +++ b/test_regress/t/t_opt_life_dpi_read.v @@ -0,0 +1,35 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define check(got,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (got), (exp)); `stop; end while(0) +// verilog_format: on + +module t; + + int dpiGet = 0; + function automatic int getDpi(); + return dpiGet; + endfunction + export "DPI-C" function getDpi; + import "DPI-C" context function int getViaDpi(); // calls getDpi() + + int tmp1, tmp2, tmp3; + + initial begin + dpiGet = 13; + tmp1 = getViaDpi(); + dpiGet = 14; + tmp2 = getViaDpi(); + dpiGet = 15; + tmp3 = getViaDpi(); + `check(tmp1, 13); + `check(tmp2, 14); + `check(tmp3, 15); + end + +endmodule From 99238f67b8c9d5cec3480c1d1561ad3d36cbec67 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 28 Feb 2026 16:10:59 +0000 Subject: [PATCH 013/340] Fix undefined weak 'vlog_startup_routines' on macOS --- include/verilated.mk.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/verilated.mk.in b/include/verilated.mk.in index 8669bd330..4e71a5ac1 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -114,7 +114,7 @@ CPPFLAGS += $(OPT) # On macOS, specify all weak symbols as dynamic_lookup. # Otherwise, you get undefined symbol errors. ifeq ($(UNAME_S),Darwin) - LDFLAGS += -Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv,-U,vlog_startup_routines + LDFLAGS += -Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv,-U,_vlog_startup_routines endif # Allow upper level user makefiles to specify flags they want. From 098fe9664383d9480396cfa1edf999e4cc8b3f61 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 28 Feb 2026 22:20:09 +0000 Subject: [PATCH 014/340] Add V3LiftExpr pass to lower impure expressions and calls (#7141) Introduce new pass that converts impure expressions, or those with function and method calls into simple assignment statements. Please see the blurb at the top of the file why this is useful and how it works. In particular currently it enables more Dfg optimization as functions will be inlined without AstExprStmt. Ideally we should enforce this lowering is applied to every procedural statement (there are still a handful of exceptions). With that, long term with this pass + #6820, there should be no need to ever use an AstExprStmt past this new lowering pass, which should enable more easier optimization down the line. Also ideally this should be run earlier. Currently it's after V3Tristate as that calls pinReconnectSimple so we don't have to touch Cell ports. Currently disabled when code coverage is enabled due to #7119. --- docs/gen/ex_ASSIGNEQEXPR_faulty.rst | 11 +- docs/guide/exe_verilator.rst | 2 + src/CMakeLists.txt | 2 + src/Makefile_obj.in | 1 + src/V3AstNodeExpr.h | 1 + src/V3AstNodes.cpp | 20 + src/V3Const.cpp | 6 +- src/V3Dead.cpp | 1 + src/V3LiftExpr.cpp | 492 ++++++++++++++++++++ src/V3LiftExpr.h | 32 ++ src/V3Options.cpp | 1 + src/V3Options.h | 2 + src/Verilator.cpp | 8 + test_regress/t/t_dfg_peephole.py | 1 + test_regress/t/t_flag_csplit_groups.py | 2 +- test_regress/t/t_lift_expr.py | 18 + test_regress/t/t_lift_expr.v | 37 ++ test_regress/t/t_lint_assigneqexpr.v | 7 +- test_regress/t/t_lint_assigneqexpr_bad.out | 8 +- test_regress/t/t_lint_assigneqexpr_bad.py | 2 +- test_regress/t/t_unopt_combo_isolate.py | 4 +- test_regress/t/t_unopt_combo_isolate_vlt.py | 3 +- 22 files changed, 645 insertions(+), 16 deletions(-) create mode 100644 src/V3LiftExpr.cpp create mode 100644 src/V3LiftExpr.h create mode 100755 test_regress/t/t_lift_expr.py create mode 100644 test_regress/t/t_lift_expr.v diff --git a/docs/gen/ex_ASSIGNEQEXPR_faulty.rst b/docs/gen/ex_ASSIGNEQEXPR_faulty.rst index af5f59067..948c309d1 100644 --- a/docs/gen/ex_ASSIGNEQEXPR_faulty.rst +++ b/docs/gen/ex_ASSIGNEQEXPR_faulty.rst @@ -1,8 +1,11 @@ .. comment: generated by t_lint_assigneqexpr_bad .. code-block:: sv :linenos: + :emphasize-lines: 3,5 - output logic c_o, - output logic d_o - ); - assign c_o = (a_i != 0) ? 1 : 0; + assign d_o = // Note = not == below + ( + e_o = 1 // <--- Warning: ASSIGNEQEXPR + ) ? 1 : ( + e_o = 0 // <--- Warning: ASSIGNEQEXPR + ) ? b_i : 0; diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index e3d434fa4..791d9417f 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -694,6 +694,8 @@ Summary: .. option:: -fno-life-post +.. option:: -fno-lift-expr + .. option:: -fno-localize .. option:: -fno-merge-cond diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 7efc365d6..7c0612dee 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -120,6 +120,7 @@ set(HEADERS V3LanguageWords.h V3Life.h V3LifePost.h + V3LiftExpr.h V3LinkCells.h V3LinkDot.h V3LinkDotIfaceCapture.h @@ -294,6 +295,7 @@ set(COMMON_SOURCES V3LibMap.cpp V3Life.cpp V3LifePost.cpp + V3LiftExpr.cpp V3LinkCells.cpp V3LinkDot.cpp V3LinkDotIfaceCapture.cpp diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index cb80e1dac..506d8047e 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -290,6 +290,7 @@ RAW_OBJS_PCH_ASTNOMT = \ V3LibMap.o \ V3Life.o \ V3LifePost.o \ + V3LiftExpr.o \ V3LinkCells.o \ V3LinkDot.o \ V3LinkDotIfaceCapture.o \ diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index cbf596680..1d0f81148 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -64,6 +64,7 @@ public: // Someday we will generically support data types on every expr node // Until then isOpaque indicates we shouldn't constant optimize this node type bool isOpaque() const { return VN_IS(this, CvtPackString); } + bool isLValue() const; // Wrap This expression into an AstStmtExpr to denote it occurs in statement position inline AstStmtExpr* makeStmt(); diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 7c98ab18e..de9dd6539 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -1791,6 +1791,26 @@ string AstBasicDType::prettyDTypeName(bool) const { void AstNodeExpr::dump(std::ostream& str) const { this->AstNode::dump(str); } void AstNodeExpr::dumpJson(std::ostream& str) const { dumpJsonGen(str); } + +bool AstNodeExpr::isLValue() const { + if (const AstNodeVarRef* const varrefp = VN_CAST(this, NodeVarRef)) { + return varrefp->access().isWriteOrRW(); + } else if (const AstMemberSel* const memberselp = VN_CAST(this, MemberSel)) { + return memberselp->access().isWriteOrRW(); + } else if (const AstSel* const selp = VN_CAST(this, Sel)) { + return selp->fromp()->isLValue(); + } else if (const AstNodeSel* const nodeSelp = VN_CAST(this, NodeSel)) { + return nodeSelp->fromp()->isLValue(); + } else if (const AstConcat* const concatp = VN_CAST(this, Concat)) { + // Enough to check only one side, as both must be same otherwise malformed + return concatp->lhsp()->isLValue(); + } else if (const AstCMethodHard* const cMethodHardp = VN_CAST(this, CMethodHard)) { + // Used for things like Queue/AssocArray/DynArray + return cMethodHardp->fromp()->isLValue(); + } + return false; +} + void AstNodeUniop::dump(std::ostream& str) const { this->AstNodeExpr::dump(str); } void AstNodeUniop::dumpJson(std::ostream& str) const { dumpJsonGen(str); } diff --git a/src/V3Const.cpp b/src/V3Const.cpp index a57f795bb..674ca1530 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -1623,7 +1623,11 @@ class ConstVisitor final : public VNVisitor { if (!thensp->rhsp()->gateTree()) return false; if (!elsesp->rhsp()->gateTree()) return false; if (m_underRecFunc) return false; // This optimization may lead to infinite recursion - return true; + // Only do it if not calls and both pure, otherwise undoes V3LiftExpr + return !VN_IS(thensp->rhsp(), NodeFTaskRef) // + && !VN_IS(elsesp->rhsp(), NodeFTaskRef) // + && thensp->rhsp()->isPure() // + && elsesp->rhsp()->isPure(); } bool operandIfIf(const AstNodeIf* nodep) { if (nodep->elsesp()) return false; diff --git a/src/V3Dead.cpp b/src/V3Dead.cpp index d5392d69f..94dfbface 100644 --- a/src/V3Dead.cpp +++ b/src/V3Dead.cpp @@ -173,6 +173,7 @@ class DeadVisitor final : public VNVisitor { } void visit(AstNodeFTaskRef* nodep) override { iterateChildren(nodep); + if (!m_sideEffect && !nodep->isPure()) m_sideEffect = true; checkAll(nodep); if (nodep->taskp()) nodep->taskp()->user1Inc(); if (nodep->classOrPackagep()) { diff --git a/src/V3LiftExpr.cpp b/src/V3LiftExpr.cpp new file mode 100644 index 000000000..544ab93cd --- /dev/null +++ b/src/V3LiftExpr.cpp @@ -0,0 +1,492 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Lift expressions out of statements +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* +// +// V3LiftExpr's Transformations: +// +// Lift impure sub-expressions and function calls out of expressions, +// turning them into additional statements. This has several benefits +// that enable further downstream optimizations: +// - Impure expressions always appear on the RHS of a simple assignment, +// reducing the size of impure expressions. This also eliminates +// later needs for cloning impure expressions, preserving side effects +// - Lifted function calls can be inlined without the use of AstExprStmt, +// which is poorly handled by optimizations, especially Dfg +// - Reduces complexity of downstream lowering passes as they need to deal +// with fewer special cases. +// +// The generic transformation applies for all AstNodeStmt. Using AstAssign +// as an example: +// x[impure_x] = impure_y + func(impure_z); +// is transformed into: +// __VleImpure_0 = impure_y; +// __VleImpure_1 = impure_z; +// __VleCall_0 = func(__VleImpure_1); +// __VleImpure_2 = impure_x; +// x[__VleImpure_2] = __VleImpure_0 + __VleCall_0; +// All parts of the assignment is now pure, and the function call can be +// inlined by V3Task without the use of AstExprStmt. +// +// Care must be taken for the 4 short-circuiting operators: && || -> ?: +// For example AstLogAnd: +// z = x && func(y) +// is transformed into: +// __VleLogAnd_0 = x; +// if (__VleLogAnd_0) { +// __VleCall_0 = func(y); +// __VleLogAnd_0 = __VleCall_0; +// } +// z = __VleLogAnd_1; +// Similar patterns are used for AstLogOr and AstCond to preserve the +// short-circuiting semantics and side effects. All AstLogIf should have +// been converted to AstLogOr earlier by V3Const. +// +// Care must be taken for impure LValues as well. While, all LValue expressions +// permitted by IEEE-1800 are themselves pure (except possibly for the non-lvalue +// sub-expressions like array indices, which are not a problem), we support a +// non-standard but common extension where a function call returning a class +// handle, under a member select can be an LValue, e.g.: +// 'getInstance().member = foo;' +// Fortunately we can discover these via MemberSel, and we can transform them +// to the IEEE-1800 compliant form: +// __VleLvalCall_0 = getInstance(); +// __VleLvalCall_0.member = foo; +// There are also some other internal LValues represented via CMethodHard that +// return references, and are marked as impure. For this reason only we still +// need to special case their handling via AstNodeExpr::isLValue(). +// +//************************************************************************* + +#include "V3PchAstNoMT.h" // VL_MT_DISABLED_CODE_UNIT + +#include "verilatedos.h" + +#include "V3LiftExpr.h" + +#include "V3Ast.h" +#include "V3Error.h" +#include "V3FileLine.h" +#include "V3Inst.h" +#include "V3Stats.h" + +VL_DEFINE_DEBUG_FUNCTIONS; + +//###################################################################### + +class LiftExprVisitor final : public VNVisitor { + // NODE STATE + // AstNodeStmt::user1() -> bool. Statement already processed + // AstVar::user1() -> bool. Variable is a lifted temporary + // AstNodeExpr::user1p() -> AstVar*. Existing temporary variable usable for this expression + const VNUser1InUse m_user1InUse; + + // STATE + AstNodeModule* m_modp = nullptr; // Current module + AstNodeFTask* m_ftaskp = nullptr; // Current function/task + bool m_lift = false; // Lift encountered expressions + // Statements lifted out of current node. TODO: Make this an AstNodeStmt* after #6280 + AstNode* m_newStmtps = nullptr; + // Expressions in some special locations need not, or should not be lifted + AstNodeExpr* m_doNotLiftp = nullptr; + size_t m_nTmps = 0; // Sequence numbers for temporary variables + // Statistics + VDouble0 m_statLiftedExprs; + VDouble0 m_statLiftedCalls; + VDouble0 m_statLiftedLvalCalls; + VDouble0 m_statLiftedConds; + VDouble0 m_statLiftedLogAnds; + VDouble0 m_statLiftedLogOrs; + VDouble0 m_statLiftedExprStmts; + VDouble0 m_statTemporariesCreated; + VDouble0 m_statTemporariesReused; + + // METHODS + AstVar* newVar(const char* baseName, const AstNodeExpr* exprp, + const std::string& suffix = "") { + // Reuse existing temporary if available + if (exprp->user1p()) { + ++m_statTemporariesReused; + return VN_AS(exprp->user1p(), Var); + } + + // Need a separate name in functions vs modules, as module inlining + // can otherwise cause spurious VARHIDDEN warnings + std::string name = m_ftaskp ? "__Vlef" : "__Vlem"; + name += baseName; + name += "_" + std::to_string(m_nTmps++); + if (!suffix.empty()) name += "__" + suffix; + + // Create variable + ++m_statTemporariesCreated; + AstVar* const varp = new AstVar{exprp->fileline(), VVarType::MODULETEMP, name, + exprp->dtypep()->skipRefp()}; + varp->isInternal(true); + varp->noReset(true); + varp->user1(1); // Mark as lifted temporary so it can be reused + + if (m_ftaskp) { + varp->funcLocal(true); + m_ftaskp->stmtsp()->addHereThisAsNext(varp); + varp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); + } else { + m_modp->stmtsp()->addHereThisAsNext(varp); + // 'automatic' on a variable inside a class actually means 'member' + varp->lifetime(VN_IS(m_modp, Class) ? VLifetime::STATIC_EXPLICIT + : VLifetime::AUTOMATIC_EXPLICIT); + } + return varp; + } + + // If the expression is a reference to an existing temporary, return it, otherwise nullptr + AstVar* getExistingVar(AstNodeExpr* nodep) { + if (AstVarRef* const refp = VN_CAST(nodep, VarRef)) { + if (refp->varp()->user1()) return refp->varp(); + } + return nullptr; + } + + // Unlink and assign given expression to temporary, unless the expression + // is a reference to the same temporary + AstAssign* assignIfDifferent(FileLine* flp, AstVar* varp, AstNodeExpr* nodep) { + if (AstVarRef* const refp = VN_CAST(nodep, VarRef)) { + if (refp->varp() == varp) return nullptr; + } + return new AstAssign{flp, new AstVarRef{flp, varp, VAccess::WRITE}, nodep->unlinkFrBack()}; + } + + void addStmtps(AstNode* stmtp) { + if (!stmtp) return; + // No need to process again, so mark + for (AstNode* nodep = stmtp; nodep; nodep = nodep->nextp()) nodep->user1(1); + m_newStmtps = AstNode::addNext(m_newStmtps, stmtp); + } + + // Lift expressions from expression, return lifted statements + AstNode* lift(AstNodeExpr* nodep) { + if (!nodep) return nullptr; + VL_RESTORER(m_lift); + VL_RESTORER(m_newStmtps); + m_lift = true; + m_newStmtps = nullptr; + iterate(nodep); + return m_newStmtps; + } + + // Lift expressions from children of given statement, return lifted statements + AstNode* liftChildren(AstNodeStmt* nodep) { + VL_RESTORER(m_lift); + VL_RESTORER(m_newStmtps); + m_lift = true; + m_newStmtps = nullptr; + iterateChildren(nodep); + return m_newStmtps; + } + + // VISITORS - non-statement, non-expression + void visit(AstNode* nodep) override { + VL_RESTORER(m_lift); + m_lift = false; // Conservatively do not lift if unknown construct + iterateChildren(nodep); + } + void visit(AstNodeModule* nodep) override { + // Reset names on root module only (there can be classes nested in modules) + if (!m_modp) m_nTmps = 0; + VL_RESTORER(m_modp); + m_modp = nodep; + iterateChildren(nodep); + } + void visit(AstNodeFTask* nodep) override { + VL_RESTORER(m_ftaskp); + VL_RESTORER(m_nTmps); + m_ftaskp = nodep; + m_nTmps = 0; + iterateChildren(nodep); + } + void visit(AstCaseItem* nodep) override { + // Do not lift from the case expressions, there is nowhere to put them + iterateAndNextNull(nodep->stmtsp()); + } + void visit(AstCell* nodep) override { + // No need to fix up port connections, V3Tristate called pinReconnectSimple, + // so all writes are to simple AstVars, assuming it did it right ... + } + void visit(AstAlias* nodep) override {} + void visit(AstArg* nodep) override { + // Lift argument expressions + iterateChildren(nodep); + } + + // VISITORS - statements + void visit(AstNodeStmt* nodep) override { + if (nodep->user1SetOnce()) return; + VL_RESTORER(m_doNotLiftp); + m_doNotLiftp = nullptr; + if (AstNode* const newStmtps = liftChildren(nodep)) nodep->addHereThisAsNext(newStmtps); + } + void visit(AstNodeAssign* nodep) override { + if (nodep->user1SetOnce()) return; + VL_RESTORER(m_doNotLiftp); + // Do not lift the RHS if this is already a simple assignment to a variable + m_doNotLiftp = VN_IS(nodep->lhsp(), NodeVarRef) ? nodep->rhsp() : nullptr; + if (AstNode* const newStmtps = lift(nodep->rhsp())) { + nodep->addHereThisAsNext(newStmtps); + } + + if (nodep->timingControlp()) return; + + if (AstNode* const newStmtps = lift(nodep->lhsp())) { + nodep->addHereThisAsNext(newStmtps); + } + } + void visit(AstStmtExpr* nodep) override { + if (nodep->user1SetOnce()) return; + // Ignore super class constructor calls - can't insert statements before them + if (VN_IS(nodep->exprp(), New)) return; + VL_RESTORER(m_doNotLiftp); + // Do not lift if the expression itself. This AstStmtExpr is required to + // throw away the return value if any, and V3Task can inline without using + // AstExprStmt in this case. Can still lift all sub-expressions though. + m_doNotLiftp = nodep->exprp(); + if (AstNode* const newStmtps = liftChildren(nodep)) nodep->addHereThisAsNext(newStmtps); + } + // Don't know whether these are sensitive to lifting, assume so + void visit(AstCStmt* nodep) override {} + void visit(AstCStmtUser* nodep) override {} + + // VISITORS - expressions + void visit(AstNodeExpr* nodep) override { + if (!m_lift) return; + + iterateChildren(nodep); + + // Do not lift if already in normal form + if (m_doNotLiftp == nodep) return; + // No need to lift void expressions, these should be under StmtExpr, but just in case ... + if (VN_IS(nodep->dtypep()->skipRefp(), VoidDType)) return; + // Do not lift if pure + if (nodep->isPure()) return; + // Do not lift if LValue + if (nodep->isLValue()) return; + + // Extract expression into a temporary variable + ++m_statLiftedExprs; + FileLine* const flp = nodep->fileline(); + AstVar* const varp = newVar("Expr", nodep); + nodep->replaceWith(new AstVarRef{flp, varp, VAccess::READ}); + addStmtps(new AstAssign{flp, new AstVarRef{flp, varp, VAccess::WRITE}, nodep}); + } + void visit(AstNodeFTaskRef* nodep) override { + if (!m_lift) return; + + iterateChildren(nodep); + + // Do not lift if already in normal form + if (m_doNotLiftp == nodep) return; + // No need to lift void functions, these should be under StmtExpr, but just in case ... + if (VN_IS(nodep->dtypep()->skipRefp(), VoidDType)) return; + // Do not lift Taskref, it's always in statement position and cleanly inlineable. + if (VN_IS(nodep, TaskRef)) return; + + // Extract expression into a temporary variable + ++m_statLiftedCalls; + FileLine* const flp = nodep->fileline(); + AstVar* const varp = newVar("Call", nodep, nodep->taskp()->name()); + nodep->replaceWith(new AstVarRef{flp, varp, VAccess::READ}); + addStmtps(new AstAssign{flp, new AstVarRef{flp, varp, VAccess::WRITE}, nodep}); + } + void visit(AstMemberSel* nodep) override { + if (!m_lift) return; + // MemberSel is special as it can appear as an LValue selecting from a call + // that returns a class handle. Note this is not in IEEE-1800, but is supported + // for compatibility. Here we turn it into an IEEE-1800 compliant LValue by + // lifting the call and use the return value via a temporary variable. + + VL_RESTORER(m_doNotLiftp); + // If it's an LValue call, do not lift the fromp, will do it explicitly below + m_doNotLiftp = nodep->access().isWriteOrRW() && VN_IS(nodep->fromp(), NodeFTaskRef) + ? nodep->fromp() + : nullptr; + iterateChildren(nodep); + // Done if not a special case + if (!m_doNotLiftp) return; + + // Extract LValue call into a temporary variable + ++m_statLiftedLvalCalls; + FileLine* const flp = nodep->fileline(); + AstVar* const varp = newVar("LvalCall", nodep->fromp()); + addStmtps(new AstAssign{flp, new AstVarRef{flp, varp, VAccess::WRITE}, + nodep->fromp()->unlinkFrBack()}); + // This one is a WRITE or READWRITE, same as the MemberSel + nodep->fromp(new AstVarRef{flp, varp, nodep->access()}); + } + + // VISITORS - RValue expressions + void visit(AstCond* nodep) override { + if (!m_lift) return; + + // Lift from condition + iterate(nodep->condp()); + + // Temporary variable to use for this expression + AstVar* varp = nullptr; + + const bool sameType + = nodep->thenp()->dtypep()->skipRefp()->sameTree(nodep->elsep()->dtypep()->skipRefp()); + + // Lift from the Then branch + AstNode* const thenStmtps = lift(nodep->thenp()); + // If lifted the Then branch, we can reuse the temporary if same type + if (sameType) varp = getExistingVar(nodep->thenp()); + if (varp) nodep->elsep()->user1p(varp); + + // Lift from the Else branch + AstNode* const elseStmtps = lift(nodep->elsep()); + // If lifted the Else branch, we can reuse the temporary if same type + if (sameType && !varp) varp = getExistingVar(nodep->elsep()); + + // If nothing lifted, then nothing to do + if (!thenStmtps && !elseStmtps) return; + + // Otherwise convert to an AstIf with a temporary variable + ++m_statLiftedConds; + FileLine* const flp = nodep->fileline(); + if (!varp) varp = newVar("Cond", nodep); + // Create the AstIf + AstIf* const ifp = new AstIf{flp, nodep->condp()->unlinkFrBack()}; + addStmtps(ifp); + ifp->addThensp(thenStmtps); + ifp->addThensp(assignIfDifferent(flp, varp, nodep->thenp())); + ifp->addElsesp(elseStmtps); + ifp->addElsesp(assignIfDifferent(flp, varp, nodep->elsep())); + // Replace the expression with a reference to the temporary variable + nodep->replaceWith(new AstVarRef{flp, varp, VAccess::READ}); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + } + void visit(AstLogAnd* nodep) override { + if (!m_lift) return; + + // Lift from LHS + iterate(nodep->lhsp()); + + // Temporary variable to use for this expression + AstVar* varp = getExistingVar(nodep->lhsp()); + // If lifted the LHS, we can reuse the temporary + if (varp) nodep->rhsp()->user1p(varp); + + // Lift from RHS, if nothing lifted, then nothing to do + AstNode* const rhsStmtps = lift(nodep->rhsp()); + if (!rhsStmtps) return; + + // Otherwise convert to an AstIf with a temporary variable + ++m_statLiftedLogAnds; + FileLine* const flp = nodep->fileline(); + if (!varp) varp = getExistingVar(nodep->rhsp()); + if (!varp) varp = newVar("LogAnd", nodep); + addStmtps(assignIfDifferent(flp, varp, nodep->lhsp())); + AstIf* const ifp = new AstIf{flp, new AstVarRef{flp, varp, VAccess::READ}}; + addStmtps(ifp); + ifp->addThensp(rhsStmtps); + ifp->addThensp(assignIfDifferent(flp, varp, nodep->rhsp())); + nodep->replaceWith(new AstVarRef{flp, varp, VAccess::READ}); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + } + void visit(AstLogOr* nodep) override { + if (!m_lift) return; + + // Lift from LHS + iterate(nodep->lhsp()); + + // Temporary variable to use for this expression + AstVar* varp = getExistingVar(nodep->lhsp()); + // If lifted the LHS, we can reuse the temporary + if (varp) nodep->rhsp()->user1p(varp); + + // Lift from RHS, if nothing lifted, then nothing to do + AstNode* const rhsStmtps = lift(nodep->rhsp()); + if (!rhsStmtps) return; + + // Otherwise convert to an AstIf with a temporary variable + ++m_statLiftedLogOrs; + FileLine* const flp = nodep->fileline(); + if (!varp) varp = getExistingVar(nodep->rhsp()); + if (!varp) varp = newVar("LogOr", nodep); + addStmtps(assignIfDifferent(flp, varp, nodep->lhsp())); + AstIf* const ifp = new AstIf{flp, new AstVarRef{flp, varp, VAccess::READ}}; + addStmtps(ifp); + ifp->addElsesp(rhsStmtps); + ifp->addElsesp(assignIfDifferent(flp, varp, nodep->rhsp())); + nodep->replaceWith(new AstVarRef{flp, varp, VAccess::READ}); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + } + void visit(AstLogIf* nodep) override { + if (!m_lift) return; + nodep->v3fatalSrc("AstLogIf should have been folded by V3Const"); + } + void visit(AstExprStmt* nodep) override { + if (!m_lift) return; + + // Eliminate AstExprStmt by lifting the content entirely + ++m_statLiftedExprStmts; + iterate(nodep->stmtsp()); + addStmtps(nodep->stmtsp()->unlinkFrBackWithNext()); + iterate(nodep->resultp()); + nodep->replaceWith(nodep->resultp()->unlinkFrBack()); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + } + + // VISITORS - Accelerate pure leaf expressions + void visit(AstConst*) override {} + void visit(AstVarRef*) override {} + void visit(AstVarXRef*) override {} + + // VISITORS - Expression special cases + // These return C++ references rather than values, cannot be lifted + void visit(AstAssocSel* nodep) override { iterateChildren(nodep); } + void visit(AstCMethodHard* nodep) override { iterateChildren(nodep); } + // Don't know whether these may return non-values, assume so + void visit(AstCExpr* nodep) override { iterateChildren(nodep); } + void visit(AstCExprUser* nodep) override { iterateChildren(nodep); } + +public: + // CONSTRUCTORS + explicit LiftExprVisitor(AstNetlist* nodep) { + // Extracting expressions can effect purity + VIsCached::clearCacheTree(); + iterate(nodep); + VIsCached::clearCacheTree(); + if (m_newStmtps) m_newStmtps->dumpTreeAndNext(std::cout, "Leftover:"); + UASSERT_OBJ(!m_newStmtps, m_newStmtps, "Failed to insert statements"); + } + ~LiftExprVisitor() override { + V3Stats::addStat("LiftExpr, lifted impure expressions", m_statLiftedExprs); + V3Stats::addStat("LiftExpr, lifted calls", m_statLiftedCalls); + V3Stats::addStat("LiftExpr, lifted calls as lvalue", m_statLiftedLvalCalls); + V3Stats::addStat("LiftExpr, lifted Cond", m_statLiftedConds); + V3Stats::addStat("LiftExpr, lifted LogAnd", m_statLiftedLogAnds); + V3Stats::addStat("LiftExpr, lifted LogOr", m_statLiftedLogOrs); + V3Stats::addStat("LiftExpr, lifted ExprStmt", m_statLiftedExprStmts); + V3Stats::addStat("LiftExpr, temporaries created", m_statTemporariesCreated); + V3Stats::addStat("LiftExpr, temporaries reused", m_statTemporariesReused); + } +}; + +//###################################################################### +// Unknown class functions + +void V3LiftExpr::liftExprAll(AstNetlist* nodep) { + UINFO(2, __FUNCTION__ << ":"); + LiftExprVisitor{nodep}; + V3Global::dumpCheckGlobalTree("lift_expr", 0, dumpTreeEitherLevel() >= 3); +} diff --git a/src/V3LiftExpr.h b/src/V3LiftExpr.h new file mode 100644 index 000000000..250a39e68 --- /dev/null +++ b/src/V3LiftExpr.h @@ -0,0 +1,32 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Lift expressions out of statements +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#ifndef VERILATOR_V3LIFTEXPR_H_ +#define VERILATOR_V3LIFTEXPR_H_ + +#include "config_build.h" +#include "verilatedos.h" + +class AstNetlist; + +//============================================================================ + +class V3LiftExpr final { +public: + static void liftExprAll(AstNetlist* nodep) VL_MT_DISABLED; +}; + +#endif // Guard diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 246aee89e..6992d0870 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1480,6 +1480,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, DECL_OPTION("-finline-funcs-eager", FOnOff, &m_fInlineFuncsEager); DECL_OPTION("-flife", FOnOff, &m_fLife); DECL_OPTION("-flife-post", FOnOff, &m_fLifePost); + DECL_OPTION("-flift-expr", FOnOff, &m_fLiftExpr); DECL_OPTION("-flocalize", FOnOff, &m_fLocalize); DECL_OPTION("-fmerge-cond", FOnOff, &m_fMergeCond); DECL_OPTION("-fmerge-cond-motion", FOnOff, &m_fMergeCondMotion); diff --git a/src/V3Options.h b/src/V3Options.h index 08df2599d..6340490b7 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -413,6 +413,7 @@ private: bool m_fInlineFuncsEager = true; // main switch: -fno-inline-funcs-eager: don't inline eagerly bool m_fLife; // main switch: -fno-life: variable lifetime bool m_fLifePost; // main switch: -fno-life-post: delayed assignment elimination + bool m_fLiftExpr = true; // main switch: -fno-lift-expr: lift expressions out of statements bool m_fLocalize; // main switch: -fno-localize: convert temps to local variables bool m_fMergeCond; // main switch: -fno-merge-cond: merge conditionals bool m_fMergeCondMotion = true; // main switch: -fno-merge-cond-motion: perform code motion @@ -734,6 +735,7 @@ public: bool fInlineFuncsEager() const { return m_fInlineFuncsEager; } bool fLife() const { return m_fLife; } bool fLifePost() const { return m_fLifePost; } + bool fLiftExpr() const { return m_fLiftExpr; } bool fLocalize() const { return m_fLocalize; } bool fMergeCond() const { return m_fMergeCond; } bool fMergeCondMotion() const { return m_fMergeCondMotion; } diff --git a/src/Verilator.cpp b/src/Verilator.cpp index c3b90208f..8d4ef283d 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -67,6 +67,7 @@ #include "V3LibMap.h" #include "V3Life.h" #include "V3LifePost.h" +#include "V3LiftExpr.h" #include "V3LinkDot.h" #include "V3LinkInc.h" #include "V3LinkJump.h" @@ -284,6 +285,13 @@ static void process() { } if (!v3Global.opt.serializeOnly()) { + // Lift expressions out of statements. Currently disabled for line and + // expression coverage, as otherwise later V3Split would further split + // combinational always blocks and alter counts (that needs to be fixed in V3Split) + if (v3Global.opt.fLiftExpr() // + && !v3Global.opt.coverageLine() && !v3Global.opt.coverageExpr()) { + V3LiftExpr::liftExprAll(v3Global.rootp()); + } // Move assignments from X into MODULE temps. // (Before flattening, so each new X variable is shared between all scopes of that // module.) diff --git a/test_regress/t/t_dfg_peephole.py b/test_regress/t/t_dfg_peephole.py index 71833c22c..b527d345d 100755 --- a/test_regress/t/t_dfg_peephole.py +++ b/test_regress/t/t_dfg_peephole.py @@ -91,6 +91,7 @@ test.compile(verilator_flags2=[ "-Mdir", test.obj_dir + "/obj_opt", "--prefix", "Vopt", "-fno-const-before-dfg", # Otherwise V3Const makes testing painful + "-fno-lift-expr", # Assumes V3Const run prior to V3LiftExpr "-fdfg-synthesize-all", "--dump-dfg", # To fill code coverage "-CFLAGS \"-I .. -I ../obj_ref\"", diff --git a/test_regress/t/t_flag_csplit_groups.py b/test_regress/t/t_flag_csplit_groups.py index 6e15ff128..c92448c9e 100755 --- a/test_regress/t/t_flag_csplit_groups.py +++ b/test_regress/t/t_flag_csplit_groups.py @@ -125,7 +125,7 @@ test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_clas test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_2") # Check combine count -test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (275 if test.vltmt else 258)) +test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (276 if test.vltmt else 259)) test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_FAST + (\d+)', 2) test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_SLOW + (\d+)', 2) diff --git a/test_regress/t/t_lift_expr.py b/test_regress/t/t_lift_expr.py new file mode 100755 index 000000000..2351d6963 --- /dev/null +++ b/test_regress/t/t_lift_expr.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lift_expr.v b/test_regress/t/t_lift_expr.v new file mode 100644 index 000000000..2b7b41b52 --- /dev/null +++ b/test_regress/t/t_lift_expr.v @@ -0,0 +1,37 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0x exp=%0x (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +module t; + + function automatic int one(); + return 1; + endfunction + + function automatic int two(); + /* verilator no_inline_task */ + return 2; + endfunction + + class C; + static int i = one() + 1; + static int j = two() + 1; + endclass + + initial begin + `checkh(C::i, 2); + `checkh(C::j, 3); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_lint_assigneqexpr.v b/test_regress/t/t_lint_assigneqexpr.v index 59420699e..fc7fefaf1 100644 --- a/test_regress/t/t_lint_assigneqexpr.v +++ b/test_regress/t/t_lint_assigneqexpr.v @@ -24,13 +24,14 @@ module Sub ( input logic [2:0] a_i, input logic b_i, output logic c_o, - output logic d_o + output logic d_o, + output logic e_o ); assign c_o = (a_i != 0) ? 1 : 0; assign d_o = // Note = not == below ( - c_o = 1 // <--- Warning: ASSIGNEQEXPR + e_o = 1 // <--- Warning: ASSIGNEQEXPR ) ? 1 : ( - c_o = 0 // <--- Warning: ASSIGNEQEXPR + e_o = 0 // <--- Warning: ASSIGNEQEXPR ) ? b_i : 0; endmodule diff --git a/test_regress/t/t_lint_assigneqexpr_bad.out b/test_regress/t/t_lint_assigneqexpr_bad.out index 0b2ab275f..79d777aca 100644 --- a/test_regress/t/t_lint_assigneqexpr_bad.out +++ b/test_regress/t/t_lint_assigneqexpr_bad.out @@ -1,11 +1,11 @@ -%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:32:11: Assignment '=' inside expression +%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:33:11: Assignment '=' inside expression : ... Was a '==' intended, or suggest use a separate statement - 32 | c_o = 1 + 33 | e_o = 1 | ^ ... For warning description see https://verilator.org/warn/ASSIGNEQEXPR?v=latest ... Use "/* verilator lint_off ASSIGNEQEXPR */" and lint_on around source to disable this message. -%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:34:11: Assignment '=' inside expression +%Warning-ASSIGNEQEXPR: t/t_lint_assigneqexpr.v:35:11: Assignment '=' inside expression : ... Was a '==' intended, or suggest use a separate statement - 34 | c_o = 0 + 35 | e_o = 0 | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_assigneqexpr_bad.py b/test_regress/t/t_lint_assigneqexpr_bad.py index 7f3535d78..6b8b54ad2 100755 --- a/test_regress/t/t_lint_assigneqexpr_bad.py +++ b/test_regress/t/t_lint_assigneqexpr_bad.py @@ -18,7 +18,7 @@ test.lint(verilator_flags2=['-Wall -Wno-DECLFILENAME'], test.extract(in_filename=test.top_filename, out_filename=test.root + "/docs/gen/ex_ASSIGNEQEXPR_faulty.rst", - lines="26-29") + lines="31-36") test.extract(in_filename=test.golden_filename, out_filename=test.root + "/docs/gen/ex_ASSIGNEQEXPR_msg.rst", diff --git a/test_regress/t/t_unopt_combo_isolate.py b/test_regress/t/t_unopt_combo_isolate.py index f35574a26..f7b4618d3 100755 --- a/test_regress/t/t_unopt_combo_isolate.py +++ b/test_regress/t/t_unopt_combo_isolate.py @@ -14,7 +14,9 @@ test.top_filename = "t/t_unopt_combo.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" -test.compile(verilator_flags2=["--no-json-edit-nums", "+define+ISOLATE", "--stats", "-fno-dfg"]) +test.compile(verilator_flags2=[ + "--no-json-edit-nums", "+define+ISOLATE", "--stats", "-fno-dfg", "-fno-lift-expr" +]) if test.vlt_all: test.file_grep(test.stats, r'Optimizations, isolate_assignments blocks\s+4') diff --git a/test_regress/t/t_unopt_combo_isolate_vlt.py b/test_regress/t/t_unopt_combo_isolate_vlt.py index 803550765..35e0cc8d2 100755 --- a/test_regress/t/t_unopt_combo_isolate_vlt.py +++ b/test_regress/t/t_unopt_combo_isolate_vlt.py @@ -15,7 +15,8 @@ test.top_filename = "t/t_unopt_combo.v" out_filename = test.obj_dir + "/V" + test.name + ".tree.json" test.compile(verilator_flags2=[ - "--no-json-edit-nums", "--stats", test.t_dir + "/t_unopt_combo_isolate.vlt", "-fno-dfg" + "--no-json-edit-nums", "--stats", test.t_dir + + "/t_unopt_combo_isolate.vlt", "-fno-dfg", "-fno-lift-expr" ]) if test.vlt_all: From 17ad3970eef735907a3443d96ed4c878f46c2c01 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 28 Feb 2026 18:15:07 -0500 Subject: [PATCH 015/340] Commentary: Changes update --- Changes | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Changes b/Changes index a13c9c8e1..ca7f1bc7a 100644 --- a/Changes +++ b/Changes @@ -14,7 +14,16 @@ Verilator 5.047 devel **Other:** * Add VPI callback support to --main (#7145). +* Add V3LiftExpr pass to lower impure expressions and calls (#7141). [Geza Lore, Testorrent USA, Inc.] +* Improve assignment-compatibility type check (#2843) (#5666) (#7052). [Pawel Kojma, Antmicro Ltd.] +* Optimize size of trace declaration object code (#7150). [Szymon Gizler, Antmicro Ltd.] +* Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.] +* Fix lambda coroutines (#6106) (#7135). [Nick Brereton] +* Fix errant integer promotion (#7012). [Todd Strader] +* Fix parameters inside std::randomize `with` clause (#7140). [Kamil Danecki, Antmicro Ltd.] +* Fix forcing unpacked variables (#7149). [Ryszard Rozak, Antmicro Ltd.] * Fix wide conditional short circuiting (#7155). +* Fix eliminating assignments to DPI-read variables (#7158). [Geza Lore, Testorrent USA, Inc.] Verilator 5.046 2026-02-28 From 2e351651cbadcfe62de2d8be07f8ae122fd222a4 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 28 Feb 2026 18:17:00 -0500 Subject: [PATCH 016/340] Fix undefined weak 'vlog_startup_routines' on macOS --- verilator-config.cmake.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index 1c739b433..c62c8f129 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -121,7 +121,7 @@ endif() if(APPLE) add_link_options( - -Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv,-U,vlog_startup_routines + -Wl,-U,__Z15vl_time_stamp64v,-U,__Z13sc_time_stampv,-U,_vlog_startup_routines ) endif() From 230ce772c2742faf2c4d036e8af0e156572e1f94 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 28 Feb 2026 18:19:34 -0500 Subject: [PATCH 017/340] Tests: Verilog format; rename test --- test_regress/t/t_array_sel_short.v | 12 +-- test_regress/t/t_coroutine_lambda.v | 78 ++++++++++--------- .../t/{t_lift_expr.py => t_opt_lift_expr.py} | 0 .../t/{t_lift_expr.v => t_opt_lift_expr.v} | 0 4 files changed, 46 insertions(+), 44 deletions(-) rename test_regress/t/{t_lift_expr.py => t_opt_lift_expr.py} (100%) rename test_regress/t/{t_lift_expr.v => t_opt_lift_expr.v} (100%) diff --git a/test_regress/t/t_array_sel_short.v b/test_regress/t/t_array_sel_short.v index aa669f231..8c5fabd21 100644 --- a/test_regress/t/t_array_sel_short.v +++ b/test_regress/t/t_array_sel_short.v @@ -6,12 +6,12 @@ module t; - logic [15:0] foo [8]; + logic [15:0] foo[8]; - initial begin - if (foo[1] != foo[1]) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (foo[1] != foo[1]) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_coroutine_lambda.v b/test_regress/t/t_coroutine_lambda.v index c0a7eb6c0..28b3b8433 100644 --- a/test_regress/t/t_coroutine_lambda.v +++ b/test_regress/t/t_coroutine_lambda.v @@ -5,51 +5,53 @@ // or the Perl Artistic License Version 2.0. // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -interface cpu_if(input logic clk); +interface cpu_if ( + input logic clk +); endinterface package p; -virtual class WriterIf; - virtual function void write(input int t); - endfunction -endclass + virtual class WriterIf; + virtual function void write(input int t); + endfunction + endclass -class BlockingWriter; - virtual cpu_if vif; - task write(int t); - @(posedge vif.clk); - endtask -endclass + class BlockingWriter; + virtual cpu_if vif; + task write(int t); + @(posedge vif.clk); + endtask + endclass -class WriterAdapter extends WriterIf; - BlockingWriter m_impl; - function new(BlockingWriter impl); - m_impl = impl; - endfunction - function void write(input int t); - m_impl.write(t); // function -> task path - endfunction -endclass + class WriterAdapter extends WriterIf; + BlockingWriter m_impl; + function new(BlockingWriter impl); + m_impl = impl; + endfunction + function void write(input int t); + m_impl.write(t); // function -> task path + endfunction + endclass -class QueueLike; - WriterIf sink; - mailbox #(int) m; - function bit try_get(output int t); - if (!m.try_get(t)) begin - end - sink.write(t); // can become coroutine call - endfunction -endclass + class QueueLike; + WriterIf sink; + mailbox #(int) m; + function bit try_get(output int t); + if (!m.try_get(t)) begin + end + sink.write(t); // can become coroutine call + endfunction + endclass -class DriverLike; - QueueLike reqq; - function void item_done(); - int t; - if (reqq.try_get(t) == 0) begin - end - endfunction -endclass + class DriverLike; + QueueLike reqq; + function void item_done(); + int t; + if (reqq.try_get(t) == 0) begin + end + endfunction + endclass endpackage @@ -57,7 +59,7 @@ module t; import p::*; logic clk = 0; - cpu_if vif(clk); + cpu_if vif (clk); always #1 clk = ~clk; diff --git a/test_regress/t/t_lift_expr.py b/test_regress/t/t_opt_lift_expr.py similarity index 100% rename from test_regress/t/t_lift_expr.py rename to test_regress/t/t_opt_lift_expr.py diff --git a/test_regress/t/t_lift_expr.v b/test_regress/t/t_opt_lift_expr.v similarity index 100% rename from test_regress/t/t_lift_expr.v rename to test_regress/t/t_opt_lift_expr.v From e23c7a510ebde138fb1aa4992d21f29d043c5043 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 28 Feb 2026 18:21:51 -0500 Subject: [PATCH 018/340] Internals: Add VL_ALLOC_RANDOM_CHECKS --- src/Makefile_obj.in | 1 + src/V3Ast.cpp | 41 +++++++++++++++++++++++++++++++++++++++++ src/V3Ast.h | 2 +- src/V3Options.cpp | 3 +++ src/V3Options.h | 2 ++ src/V3SymTable.h | 2 +- src/astgen | 11 +++++++++++ 7 files changed, 60 insertions(+), 2 deletions(-) diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index 506d8047e..28f15e698 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -102,6 +102,7 @@ LIBS = $(CFG_LIBS) -lm CPPFLAGS += -DVERILATOR_INTERNAL_ CPPFLAGS += -MMD CPPFLAGS += -I. -I$(bldsrc) -I$(srcdir) -I$(incdir) -I../../include +#CPPFLAGS += -DVL_ALLOC_RANDOM_CHECKS # To allow --debug-new-random #CPPFLAGS += -DVL_LEAK_CHECKS # If running valgrind or other hunting tool CPPFLAGS += -MP # Only works on recent GCC versions ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index fc05797e7..064503267 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -23,6 +23,10 @@ #include #include +#ifdef VL_ALLOC_RANDOM_CHECKS +#include "V3Ast__gen_sizeof.h" +#endif + VL_DEFINE_DEBUG_FUNCTIONS; //====================================================================== @@ -992,6 +996,43 @@ void AstNode::operator delete(void* objp, size_t size) { } #endif +#ifdef VL_ALLOC_RANDOM_CHECKS +void* AstNode::operator new(size_t size) { + // Make the following small to debug this routine, larger for performance and better random + constexpr size_t POOL_SIZE = 65536; // Ideally large enough to fit all nodes used in tests + // Randomly select from a large pool (POOL_SIZE) of max-node sized (MAX_NODE_SIZE) pointers + static uint64_t s_lfsr = 0; // LFSR, 0 = didn't initialize yet + static std::array s_nodePool; + if (int seed = v3Global.opt.debugAllocRandom()) { + constexpr uint64_t POLYNOMIAL = 0x80000000000019e2ULL; + UASSERT_STATIC(size <= ASTGEN_MAX_NODE_SIZE, "fix ASTGEN_MAX_NODE_SIZE"); + if (!s_lfsr) { + s_lfsr = seed; + if (!s_lfsr) s_lfsr = ~s_lfsr; + for (size_t i = 0; i < POOL_SIZE; ++i) { + s_nodePool[i] = ::operator new(ASTGEN_MAX_NODE_SIZE + 64); + } + // Sort, just to make it more obvious we are properly randomizing + std::sort(std::begin(s_nodePool), std::end(s_nodePool)); + } + // Xoroshiro128+ algorithm + s_lfsr = (s_lfsr & 1ULL) ? ((s_lfsr >> 1ULL) ^ POLYNOMIAL) : (s_lfsr >> 1ULL); + const size_t index = s_lfsr % POOL_SIZE; + AstNode* const objp = static_cast(s_nodePool[index]); + s_nodePool[index] = ::operator new(ASTGEN_MAX_NODE_SIZE + 64); // For later new() + return objp; + } else { + AstNode* const objp = static_cast(::operator new(size)); + return objp; + } +} +void AstNode::operator delete(void* objp, size_t size) { + // Leak due to size difference between true node and MAX_NODE_SIZE + (void)objp; + (void)size; +} +#endif + //====================================================================== // Iterators diff --git a/src/V3Ast.h b/src/V3Ast.h index 1051a4b31..87ed4959f 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -560,7 +560,7 @@ public: // Perform a function on every link in a node virtual void foreachLink(std::function f) = 0; -#ifdef VL_LEAK_CHECKS +#if defined(VL_LEAK_CHECKS) || defined(VL_ALLOC_RANDOM_CHECKS) static void* operator new(size_t size); static void operator delete(void* obj, size_t size); #endif diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 6992d0870..28c7d75b8 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1375,6 +1375,9 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, DECL_OPTION("-debug-abort", CbCall, []() { V3Error::vlAbort(); // LCOV_EXCL_LINE }).undocumented(); // See also --debug-sigseg +#ifdef VL_ALLOC_RANDOM_CHECKS + DECL_OPTION("-debug-alloc-random", Set, &m_debugAllocRandom).undocumented(); +#endif DECL_OPTION("-debug-check", OnOff, &m_debugCheck); DECL_OPTION("-debug-collision", OnOff, &m_debugCollision).undocumented(); DECL_OPTION("-debug-emitv", OnOff, &m_debugEmitV).undocumented(); diff --git a/src/V3Options.h b/src/V3Options.h index 6340490b7..138c597b3 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -315,6 +315,7 @@ private: int m_coverageExprMax = 32; // main switch: --coverage-expr-max int m_convergeLimit = 100; // main switch: --converge-limit int m_coverageMaxWidth = 256; // main switch: --coverage-max-width + int m_debugAllocRandom = 0; // main switch: --debug-alloc-random int m_expandLimit = 256; // main switch: --expand-limit int m_gateStmts = 100; // main switch: --gate-stmts int m_hierChild = 0; // main switch: --hierarchical-child @@ -597,6 +598,7 @@ public: int convergeLimit() const { return m_convergeLimit; } int coverageExprMax() const { return m_coverageExprMax; } int coverageMaxWidth() const { return m_coverageMaxWidth; } + int debugAllocRandom() const { return m_debugAllocRandom; } bool dumpTreeAddrids() const VL_MT_SAFE; int expandLimit() const { return m_expandLimit; } int gateStmts() const { return m_gateStmts; } diff --git a/src/V3SymTable.h b/src/V3SymTable.h index 019bfbe19..305d1652f 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -104,7 +104,7 @@ public: m_classOrPackagep = reinterpret_cast(1); #endif } -#if defined(VL_DEBUG) && !defined(VL_LEAK_CHECKS) +#if (defined(VL_DEBUG) || defined(VL_ALLOC_RANDOM_CHECKS)) && !defined(VL_LEAK_CHECKS) // For testing, leak so above destructor 1 assignments work void* operator new(size_t size) { return std::malloc(size); } void operator delete(void* objp, size_t size) {} diff --git a/src/astgen b/src/astgen index 3d26c0474..1865f51f6 100755 --- a/src/astgen +++ b/src/astgen @@ -935,6 +935,16 @@ def write_ast_type_info(filename): )) +def write_ast_sizeof(filename): + with open_file(filename) as fh: + fh.write("static constexpr size_t ASTGEN_MAX_NODE_SIZE =\n") + paren = "" + for node in AstNodeList: + fh.write(" std::max(sizeof(Ast{n}),\n".format(n=node.name)) + paren += ")" + fh.write(" static_cast(0)" + paren + ";\n") + + def write_ast_impl(filename): with open_file(filename) as fh: @@ -1584,6 +1594,7 @@ if Args.classes: write_ast_impl("V3Ast__gen_impl.h") write_ast_macros("V3Ast__gen_macros.h") write_ast_yystype("V3Ast__gen_yystype.h") + write_ast_sizeof("V3Ast__gen_sizeof.h") # Write Dfg code write_forward_class_decls("Dfg", DfgVertexList) write_visitor_decls("Dfg", DfgVertexList) From e9dd6eaaf0dcecaf39942afda32cb2f243f8ded6 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 28 Feb 2026 20:24:09 -0500 Subject: [PATCH 019/340] Internals: Fix VL_ALLOC_RANDOM_CHECKS with multiple threads --- src/V3Ast.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index 064503267..377f8b8c7 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -997,13 +997,15 @@ void AstNode::operator delete(void* objp, size_t size) { #endif #ifdef VL_ALLOC_RANDOM_CHECKS -void* AstNode::operator new(size_t size) { +void* AstNode::operator new(size_t size) { // VL_MT_SAFE // Make the following small to debug this routine, larger for performance and better random constexpr size_t POOL_SIZE = 65536; // Ideally large enough to fit all nodes used in tests // Randomly select from a large pool (POOL_SIZE) of max-node sized (MAX_NODE_SIZE) pointers static uint64_t s_lfsr = 0; // LFSR, 0 = didn't initialize yet - static std::array s_nodePool; if (int seed = v3Global.opt.debugAllocRandom()) { + static V3Mutex s_mutex; + const V3LockGuard lock{s_mutex}; + static std::array s_nodePool VL_GUARDED_BY(s_mutex); constexpr uint64_t POLYNOMIAL = 0x80000000000019e2ULL; UASSERT_STATIC(size <= ASTGEN_MAX_NODE_SIZE, "fix ASTGEN_MAX_NODE_SIZE"); if (!s_lfsr) { From 26eac21432dba104b381031d7cfe5d64ada07dad Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sun, 1 Mar 2026 10:33:30 +0000 Subject: [PATCH 020/340] Internals: Use existing astgen type info for ASTGEN_MAX_NODE_SIZE (#7161) --- src/V3Ast.cpp | 13 +++++++++---- src/astgen | 11 ----------- 2 files changed, 9 insertions(+), 15 deletions(-) diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index 377f8b8c7..7b77b1073 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -23,10 +23,6 @@ #include #include -#ifdef VL_ALLOC_RANDOM_CHECKS -#include "V3Ast__gen_sizeof.h" -#endif - VL_DEFINE_DEBUG_FUNCTIONS; //====================================================================== @@ -998,6 +994,15 @@ void AstNode::operator delete(void* objp, size_t size) { #ifdef VL_ALLOC_RANDOM_CHECKS void* AstNode::operator new(size_t size) { // VL_MT_SAFE + // Compute the maximum node size once and cache it + static const size_t ASTGEN_MAX_NODE_SIZE = []() { + size_t maxSize = 0; + for (size_t t = 0; t < VNType::NUM_TYPES(); ++t) { + maxSize = std::max(maxSize, VNType::typeInfo(static_cast(t)).m_sizeof); + } + return maxSize; + }(); + // Make the following small to debug this routine, larger for performance and better random constexpr size_t POOL_SIZE = 65536; // Ideally large enough to fit all nodes used in tests // Randomly select from a large pool (POOL_SIZE) of max-node sized (MAX_NODE_SIZE) pointers diff --git a/src/astgen b/src/astgen index 1865f51f6..3d26c0474 100755 --- a/src/astgen +++ b/src/astgen @@ -935,16 +935,6 @@ def write_ast_type_info(filename): )) -def write_ast_sizeof(filename): - with open_file(filename) as fh: - fh.write("static constexpr size_t ASTGEN_MAX_NODE_SIZE =\n") - paren = "" - for node in AstNodeList: - fh.write(" std::max(sizeof(Ast{n}),\n".format(n=node.name)) - paren += ")" - fh.write(" static_cast(0)" + paren + ";\n") - - def write_ast_impl(filename): with open_file(filename) as fh: @@ -1594,7 +1584,6 @@ if Args.classes: write_ast_impl("V3Ast__gen_impl.h") write_ast_macros("V3Ast__gen_macros.h") write_ast_yystype("V3Ast__gen_yystype.h") - write_ast_sizeof("V3Ast__gen_sizeof.h") # Write Dfg code write_forward_class_decls("Dfg", DfgVertexList) write_visitor_decls("Dfg", DfgVertexList) From 77ce9cec1ed3e19062045b8e5b2eeae5f702e7de Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sun, 1 Mar 2026 10:47:05 +0000 Subject: [PATCH 021/340] Optimize conditional merging across some impure statements (#7159) - Allow reordering pure statements with DPI import calls iff no public variables (including those read via a DPI export) are involved. This ensures the DPI import can't observe the reordering - Allow reordering of pure statements with AstDisplay and AstStop. This requires an assumption that AstDisplay and AstStop will not read or write model state other than via a VarRef explicitly present int the Ast. Overall this allows eliminating a lot of conditionals around assertions, which were previously not possible. --- src/V3AstNodeExpr.h | 2 + src/V3AstNodes.cpp | 8 + src/V3MergeCond.cpp | 78 +- src/V3Task.cpp | 3 +- test_regress/t/t_json_only_debugcheck.out | 2281 ++++++++----------- test_regress/t/t_opt_merge_cond.py | 6 +- test_regress/t/t_opt_merge_cond_relaxed.cpp | 29 + test_regress/t/t_opt_merge_cond_relaxed.out | 173 ++ test_regress/t/t_opt_merge_cond_relaxed.py | 20 + test_regress/t/t_opt_merge_cond_relaxed.v | 133 ++ 10 files changed, 1394 insertions(+), 1339 deletions(-) create mode 100644 test_regress/t/t_opt_merge_cond_relaxed.cpp create mode 100644 test_regress/t/t_opt_merge_cond_relaxed.out create mode 100755 test_regress/t/t_opt_merge_cond_relaxed.py create mode 100644 test_regress/t/t_opt_merge_cond_relaxed.v diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index 1d0f81148..1222c32cd 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -621,6 +621,8 @@ public: init(text, setwidth); } ASTGEN_MEMBERS_AstCExpr; + void dump(std::ostream& str = std::cout) const override; + void dumpJson(std::ostream& str = std::cout) const override; // METHODS bool cleanOut() const override { return true; } std::string emitC() override { V3ERROR_NA_RETURN(""); } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index de9dd6539..7d6970bfa 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -1869,6 +1869,14 @@ void AstCellInlineScope::dumpJson(std::ostream& str) const { dumpJsonStrFunc(str, origModName); dumpJsonGen(str); } +void AstCExpr::dump(std::ostream& str) const { + this->AstNodeExpr::dump(str); + if (m_pure) str << " [PURE]"; +} +void AstCExpr::dumpJson(std::ostream& str) const { + dumpJsonBoolIf(str, "pure", m_pure); + dumpJsonGen(str); +} bool AstClass::isCacheableChild(const AstNode* nodep) { return VN_IS(nodep, Var) || VN_IS(nodep, Typedef) || (VN_IS(nodep, Constraint) && !VN_AS(nodep, Constraint)->isExternProto()) diff --git a/src/V3MergeCond.cpp b/src/V3MergeCond.cpp index d4d687c69..6cddb01e7 100644 --- a/src/V3MergeCond.cpp +++ b/src/V3MergeCond.cpp @@ -137,12 +137,19 @@ struct StmtProperties final { std::set m_rdVars; // Variables read by this statement std::set m_wrVars; // Variables written by this statement bool m_isFence = false; // Nothing should move across this statement, nor should it be merged + bool m_sideEffect = false; // Statement may have side effect, without access to model state + bool m_implPubRd = false; // Statement may implicitly read public state (without VarRef) + bool m_implPubWr = false; // Statement may implicitly write public state (without VarRef) + bool m_explPubRef = false; // Statement explicitly references public state via VarRef AstNodeStmt* m_prevWithSameCondp = nullptr; // Previous node in same list, with same condition - bool writesConditionVar() const { + bool writesConditionVar(bool condPubWritable) const { // This relies on MarkVarsVisitor having been called on the condition node for (const AstVar* const varp : m_wrVars) { if (varp->user1()) return true; } + // If the condition contains a public variable, check if it might be written + if (condPubWritable && m_implPubWr) return true; + // Otherwise not written return false; } }; @@ -231,8 +238,12 @@ class CodeMotionAnalysisVisitor final : public VNVisitorConst { // Add all rd/wr vars to outer statement outerPropsp->m_rdVars.insert(m_propsp->m_rdVars.cbegin(), m_propsp->m_rdVars.cend()); outerPropsp->m_wrVars.insert(m_propsp->m_wrVars.cbegin(), m_propsp->m_wrVars.cend()); - // If this statement is impure, the enclosing statement is also impure - if (m_propsp->m_isFence) outerPropsp->m_isFence = true; + // Propagate flags to enclosing statement + outerPropsp->m_isFence |= m_propsp->m_isFence; + outerPropsp->m_sideEffect |= m_propsp->m_sideEffect; + outerPropsp->m_implPubRd |= m_propsp->m_implPubRd; + outerPropsp->m_implPubWr |= m_propsp->m_implPubWr; + outerPropsp->m_explPubRef |= m_propsp->m_explPubRef; } } @@ -242,11 +253,44 @@ class CodeMotionAnalysisVisitor final : public VNVisitorConst { // Gather read and written variables if (access.isReadOrRW()) m_propsp->m_rdVars.insert(varp); if (access.isWriteOrRW()) m_propsp->m_wrVars.insert(varp); + if (varp->isSigPublic() || varp->isWrittenByDpi() || varp->isReadByDpi()) { + m_propsp->m_explPubRef = true; + } + } + + void checkProperties(AstNode* nodep) { + // Ignore StmtExpr. It interferes with special casing DPI calls below, + // and it only checks if the child expr is impure, which is checked + // explicitly during the analysis. + if (VN_IS(nodep, StmtExpr)) return; + + // Call to a DPI import + if (const AstNodeCCall* const ccallp = VN_CAST(nodep, NodeCCall)) { + AstCFunc* const funcp = ccallp->funcp(); + if (funcp->dpiImportWrapper()) { + if (!funcp->dpiPure()) { + // Assume has side effect and accesses public state + m_propsp->m_sideEffect = true; + m_propsp->m_implPubRd = true; + m_propsp->m_implPubWr = true; + } + return; + } + } + + // Side effect, but assume does not access public state + if (VN_IS(nodep, Display) || VN_IS(nodep, Stop)) { + m_propsp->m_sideEffect = true; + return; + } + + // If impure, or branch, mark statement as fence + if (!nodep->isPure() || nodep->isBrancher()) m_propsp->m_isFence = true; } void analyzeNode(AstNode* nodep) { - // If impure, or branch, mark statement as fence - if (m_propsp && (!nodep->isPure() || nodep->isBrancher())) m_propsp->m_isFence = true; + // Check properties of this node if under a statement + if (m_propsp) checkProperties(nodep); // Analyze children iterateChildrenConst(nodep); } @@ -310,6 +354,13 @@ class CodeMotionOptimizeVisitor final : public VNVisitor { // Don't move across fences if (aProps.m_isFence) return false; if (bProps.m_isFence) return false; + // Don't swap side effecting statements, but can move others across them + if (aProps.m_sideEffect && bProps.m_sideEffect) return false; + // Don't swap if there is a hazard around public state - must observe ordering + const bool bPubRef = bProps.m_implPubWr || bProps.m_implPubRd || bProps.m_explPubRef; + if (aProps.m_implPubWr && bPubRef) return false; + const bool aPubRef = aProps.m_implPubWr || aProps.m_implPubRd || aProps.m_explPubRef; + if (aPubRef && bProps.m_implPubWr) return false; // If either statement writes a variable that the other reads, they are not swappable if (!areDisjoint(aProps.m_rdVars, bProps.m_wrVars)) return false; if (!areDisjoint(bProps.m_rdVars, aProps.m_wrVars)) return false; @@ -446,6 +497,7 @@ class MergeCondVisitor final : public VNVisitor { AstNodeExpr* m_mgCondp = nullptr; // The condition of the first node const AstNode* m_mgLastp = nullptr; // Last node in merged sequence const AstNode* m_mgNextp = nullptr; // Next node in list being examined + bool m_mgCondPubWritable = false; // True if m_mgCondp contains a public writable variable uint32_t m_listLenght = 0; // Length of current list std::queue* m_workQueuep = nullptr; // Node lists (via AstNode::nextp()) to merge @@ -717,6 +769,7 @@ class MergeCondVisitor final : public VNVisitor { m_mgCondp = nullptr; m_mgLastp = nullptr; m_mgNextp = nullptr; + m_mgCondPubWritable = false; AstNode::user1ClearTree(); // Clear marked variables AstNode::user2ClearTree(); // Merge recursively within the branches of an un-merged AstNodeIF @@ -753,14 +806,19 @@ class MergeCondVisitor final : public VNVisitor { // Set up head of new list if node is first in list if (!m_mgFirstp) { UASSERT_OBJ(condp, nodep, "Cannot start new list without condition"); - // Mark variable references in the condition - condp->foreach([](const AstVarRef* nodep) { nodep->varp()->user1(1); }); + // Mark variable references in the condition, record if a public variable is involved + condp->foreach([&](const AstVarRef* nodep) { + AstVar* const varp = nodep->varp(); + varp->user1(1); + if (varp->isSigPublic() || varp->isWrittenByDpi()) m_mgCondPubWritable = true; + }); // Now check again if mergeable. We need this to pick up assignments to conditions, // e.g.: 'c = c ? a : b' at the beginning of the list, which is in fact not mergeable // because it updates the condition. We simply bail on these. - if ((*m_stmtPropertiesp)(nodep).writesConditionVar()) { + if ((*m_stmtPropertiesp)(nodep).writesConditionVar(m_mgCondPubWritable)) { // Clear marked variables AstNode::user1ClearTree(); + m_mgCondPubWritable = false; // We did not add to the list return false; } @@ -773,7 +831,7 @@ class MergeCondVisitor final : public VNVisitor { AstNodeStmt* const backp = VN_CAST(m_mgFirstp->backp(), NodeStmt); if (!backp || backp->nextp() != m_mgFirstp) break; // Don't move up the tree const StmtProperties& props = (*m_stmtPropertiesp)(backp); - if (props.m_isFence || props.writesConditionVar()) break; + if (props.m_isFence || props.writesConditionVar(m_mgCondPubWritable)) break; if (isSimplifiableNode(backp)) { ++m_listLenght; m_mgFirstp = backp; @@ -824,7 +882,7 @@ class MergeCondVisitor final : public VNVisitor { if (props.m_isFence) return false; // Fence node never mergeable // If the statement writes a condition variable of a pending merge, // we must end the pending merge - if (m_mgFirstp && props.writesConditionVar()) mergeEnd(); + if (m_mgFirstp && props.writesConditionVar(m_mgCondPubWritable)) mergeEnd(); return true; // Now surely mergeable } diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 5f611d6be..a3fa624a8 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -765,7 +765,8 @@ class TaskVisitor final : public VNVisitor { // __Vscopep ccallp->addArgsp(snp); // __Vfilenamep - ccallp->addArgsp(new AstCExpr{flp, "\"" + flp->filenameEsc() + "\"", 64}); + ccallp->addArgsp( + new AstCExpr{flp, AstCExpr::Pure{}, "\"" + flp->filenameEsc() + "\"", 64}); // __Vlineno ccallp->addArgsp(new AstConst(flp, flp->lineno())); } diff --git a/test_regress/t/t_json_only_debugcheck.out b/test_regress/t/t_json_only_debugcheck.out index 0277917a8..580b84469 100644 --- a/test_regress/t/t_json_only_debugcheck.out +++ b/test_regress/t/t_json_only_debugcheck.out @@ -109,7 +109,7 @@ ],"filep": []}, {"type":"STOP","name":"","addr":"(TC)","loc":"d,38:142,38:147"} ],"elsesp": []}, - {"type":"IF","name":"","addr":"(UC)","loc":"d,39:10,39:12", + {"type":"IF","name":"","addr":"(UC)","loc":"d,39:34,39:37", "condp": [ {"type":"NEQ","name":"","addr":"(VC)","loc":"d,39:34,39:37","dtypep":"(GB)", "lhsp": [ @@ -181,73 +181,34 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(TD)","loc":"d,39:158,39:163"} - ],"elsesp": []}, - {"type":"IF","name":"","addr":"(UD)","loc":"d,40:10,40:12", - "condp": [ - {"type":"NEQ","name":"","addr":"(VD)","loc":"d,40:26,40:29","dtypep":"(GB)", - "lhsp": [ - {"type":"CONST","name":"4'h1","addr":"(WD)","loc":"d,40:31,40:34","dtypep":"(UB)"} - ], - "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(XD)","loc":"d,40:15,40:16","dtypep":"(BC)", - "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(YD)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} - ], - "bitp": [ - {"type":"AND","name":"","addr":"(ZD)","loc":"d,40:15,40:16","dtypep":"(GC)", - "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(AE)","loc":"d,40:15,40:16","dtypep":"(IC)"} - ], - "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(BE)","loc":"d,40:15,40:16","dtypep":"(GC)", - "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(CE)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} - ], - "bitp": [ - {"type":"AND","name":"","addr":"(DE)","loc":"d,40:15,40:16","dtypep":"(GC)", - "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(EE)","loc":"d,40:15,40:16","dtypep":"(IC)"} - ], - "rhsp": [ - {"type":"CCAST","name":"","addr":"(FE)","loc":"d,40:15,40:16","dtypep":"(GC)","size":32, - "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(GE)","loc":"d,40:15,40:16","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} - ]} - ]} - ]} - ]} - ]} - ]} - ], - "thensp": [ - {"type":"DISPLAY","name":"","addr":"(HE)","loc":"d,40:43,40:49", + {"type":"STOP","name":"","addr":"(TD)","loc":"d,39:158,39:163"}, + {"type":"DISPLAY","name":"","addr":"(UD)","loc":"d,40:43,40:49", "fmtp": [ - {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:40: got='h%x exp='h1\\n","addr":"(IE)","loc":"d,40:43,40:49","dtypep":"(SB)", + {"type":"SFORMATF","name":"%%Error: t/t_enum_type_methods.v:40: got='h%x exp='h1\\n","addr":"(VD)","loc":"d,40:43,40:49","dtypep":"(SB)", "exprsp": [ - {"type":"ARRAYSEL","name":"","addr":"(JE)","loc":"d,40:122,40:123","dtypep":"(BC)", + {"type":"ARRAYSEL","name":"","addr":"(WD)","loc":"d,40:122,40:123","dtypep":"(BC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(KE)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(XD)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(LE)","loc":"d,40:122,40:123","dtypep":"(GC)", + {"type":"AND","name":"","addr":"(YD)","loc":"d,40:122,40:123","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(ME)","loc":"d,40:122,40:123","dtypep":"(IC)"} + {"type":"CONST","name":"32'h7","addr":"(ZD)","loc":"d,40:122,40:123","dtypep":"(IC)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(NE)","loc":"d,40:122,40:123","dtypep":"(GC)", + {"type":"ARRAYSEL","name":"","addr":"(AE)","loc":"d,40:122,40:123","dtypep":"(GC)", "fromp": [ - {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(OE)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"__Venumtab_enum_next1","addr":"(BE)","loc":"d,17:12,17:16","dtypep":"(DC)","access":"RD","varp":"(EC)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ], "bitp": [ - {"type":"AND","name":"","addr":"(PE)","loc":"d,40:122,40:123","dtypep":"(GC)", + {"type":"AND","name":"","addr":"(CE)","loc":"d,40:122,40:123","dtypep":"(GC)", "lhsp": [ - {"type":"CONST","name":"32'h7","addr":"(QE)","loc":"d,40:122,40:123","dtypep":"(IC)"} + {"type":"CONST","name":"32'h7","addr":"(DE)","loc":"d,40:122,40:123","dtypep":"(IC)"} ], "rhsp": [ - {"type":"CCAST","name":"","addr":"(RE)","loc":"d,40:122,40:123","dtypep":"(GC)","size":32, + {"type":"CCAST","name":"","addr":"(EE)","loc":"d,40:122,40:123","dtypep":"(GC)","size":32, "lhsp": [ - {"type":"VARREF","name":"t.e","addr":"(SE)","loc":"d,40:122,40:123","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} + {"type":"VARREF","name":"t.e","addr":"(FE)","loc":"d,40:122,40:123","dtypep":"(GC)","access":"RD","varp":"(L)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ]} ]} ]} @@ -255,48 +216,48 @@ ]} ],"scopeNamep": []} ],"filep": []}, - {"type":"STOP","name":"","addr":"(TE)","loc":"d,40:142,40:147"} + {"type":"STOP","name":"","addr":"(GE)","loc":"d,40:142,40:147"} ],"elsesp": []}, - {"type":"IF","name":"","addr":"(UE)","loc":"d,41:10,41:12", + {"type":"IF","name":"","addr":"(HE)","loc":"d,41:42,41:45", "condp": [ - {"type":"NEQ","name":"","addr":"(VE)","loc":"d,41:42,41:45","dtypep":"(GB)", + {"type":"NEQ","name":"","addr":"(IE)","loc":"d,41:42,41:45","dtypep":"(GB)", "lhsp": [ - {"type":"CONST","name":"4'h3","addr":"(WE)","loc":"d,41:47,41:50","dtypep":"(UB)"} + {"type":"CONST","name":"4'h3","addr":"(JE)","loc":"d,41:47,41:50","dtypep":"(UB)"} ], "rhsp": [ - {"type":"ARRAYSEL","name":"","addr":"(XE)","loc":"d,41:15,41:16","dtypep":"(BC)", + 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{"type":"ENUMITEM","name":"E04","addr":"(NSB)","loc":"d,20:24,20:27","dtypep":"(UB)","rangep": [], + {"type":"ENUMITEM","name":"E04","addr":"(UNB)","loc":"d,20:24,20:27","dtypep":"(UB)","rangep": [], "valuep": [ - {"type":"CONST","name":"4'h4","addr":"(OSB)","loc":"d,20:30,20:31","dtypep":"(UB)"} + {"type":"CONST","name":"4'h4","addr":"(VNB)","loc":"d,20:30,20:31","dtypep":"(UB)"} ]} ]}, {"type":"BASICDTYPE","name":"integer","addr":"(S)","loc":"d,23:4,23:11","dtypep":"(S)","keyword":"integer","range":"31:0","generic":true,"signed":true,"rangep": []}, @@ -3022,61 +2653,61 @@ {"type":"BASICDTYPE","name":"string","addr":"(SB)","loc":"d,28:4,28:10","dtypep":"(SB)","keyword":"string","generic":true,"rangep": []}, {"type":"UNPACKARRAYDTYPE","name":"","addr":"(DC)","loc":"d,17:12,17:16","dtypep":"(DC)","declRange":"[7:0]","refDTypep":"(BC)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(PSB)","loc":"d,17:12,17:16", + {"type":"RANGE","name":"","addr":"(WNB)","loc":"d,17:12,17:16", "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(QSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} + {"type":"CONST","name":"32'h7","addr":"(XNB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(RSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} + {"type":"CONST","name":"32'h0","addr":"(YNB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ]} ]}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(XI)","loc":"d,17:12,17:16","dtypep":"(XI)","declRange":"[7:0]","refDTypep":"(BC)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(CH)","loc":"d,17:12,17:16","dtypep":"(CH)","declRange":"[7:0]","refDTypep":"(BC)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(SSB)","loc":"d,17:12,17:16", + {"type":"RANGE","name":"","addr":"(ZNB)","loc":"d,17:12,17:16", "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(TSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} + {"type":"CONST","name":"32'h7","addr":"(AOB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(USB)","loc":"d,17:12,17:16","dtypep":"(IC)"} + {"type":"CONST","name":"32'h0","addr":"(BOB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ]} ]}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(JM)","loc":"d,17:12,17:16","dtypep":"(JM)","isCompound":true,"declRange":"[7:0]","refDTypep":"(SB)","childDTypep": [], + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(SJ)","loc":"d,17:12,17:16","dtypep":"(SJ)","isCompound":true,"declRange":"[7:0]","refDTypep":"(SB)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(VSB)","loc":"d,17:12,17:16", + {"type":"RANGE","name":"","addr":"(COB)","loc":"d,17:12,17:16", "leftp": [ - {"type":"CONST","name":"32'h7","addr":"(WSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} + {"type":"CONST","name":"32'h7","addr":"(DOB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(XSB)","loc":"d,17:12,17:16","dtypep":"(IC)"} + {"type":"CONST","name":"32'h0","addr":"(EOB)","loc":"d,17:12,17:16","dtypep":"(IC)"} ]} ]}, {"type":"BASICDTYPE","name":"logic","addr":"(LB)","loc":"d,23:23,23:24","dtypep":"(LB)","keyword":"logic","range":"31:0","generic":true,"signed":true,"rangep": []}, {"type":"VOIDDTYPE","name":"","addr":"(DB)","loc":"a,0:0,0:0","dtypep":"(DB)"}, - {"type":"BASICDTYPE","name":"bit","addr":"(IN)","loc":"a,0:0,0:0","dtypep":"(IN)","keyword":"bit","range":"63:0","generic":true,"rangep": []}, - {"type":"UNPACKARRAYDTYPE","name":"","addr":"(W)","loc":"d,11:8,11:9","dtypep":"(W)","declRange":"[0:0]","refDTypep":"(IN)","childDTypep": [], + {"type":"BASICDTYPE","name":"bit","addr":"(RK)","loc":"a,0:0,0:0","dtypep":"(RK)","keyword":"bit","range":"63:0","generic":true,"rangep": []}, + {"type":"UNPACKARRAYDTYPE","name":"","addr":"(W)","loc":"d,11:8,11:9","dtypep":"(W)","declRange":"[0:0]","refDTypep":"(RK)","childDTypep": [], "rangep": [ - {"type":"RANGE","name":"","addr":"(YSB)","loc":"d,11:8,11:9", + {"type":"RANGE","name":"","addr":"(FOB)","loc":"d,11:8,11:9", "leftp": [ - {"type":"CONST","name":"32'h0","addr":"(ZSB)","loc":"d,11:8,11:9","dtypep":"(IC)"} + {"type":"CONST","name":"32'h0","addr":"(GOB)","loc":"d,11:8,11:9","dtypep":"(IC)"} ], "rightp": [ - {"type":"CONST","name":"32'h0","addr":"(ATB)","loc":"d,11:8,11:9","dtypep":"(IC)"} + {"type":"CONST","name":"32'h0","addr":"(HOB)","loc":"d,11:8,11:9","dtypep":"(IC)"} ]} ]}, - {"type":"BASICDTYPE","name":"IData","addr":"(JP)","loc":"a,0:0,0:0","dtypep":"(JP)","keyword":"IData","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(KN)","loc":"d,63:14,63:21","dtypep":"(KN)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"IData","addr":"(SM)","loc":"a,0:0,0:0","dtypep":"(SM)","keyword":"IData","range":"31:0","generic":true,"rangep": []}, + {"type":"BASICDTYPE","name":"logic","addr":"(TK)","loc":"d,63:14,63:21","dtypep":"(TK)","keyword":"logic","range":"63:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(P)","loc":"d,11:8,11:9","dtypep":"(P)","keyword":"bit","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"bit","addr":"(U)","loc":"d,11:8,11:9","dtypep":"(U)","keyword":"bit","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(GB)","loc":"d,63:22,63:25","dtypep":"(GB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(UB)","loc":"d,32:11,32:14","dtypep":"(UB)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, {"type":"BASICDTYPE","name":"logic","addr":"(GC)","loc":"d,38:15,38:16","dtypep":"(GC)","keyword":"logic","range":"31:0","generic":true,"rangep": []}, - {"type":"BASICDTYPE","name":"logic","addr":"(TPB)","loc":"d,15:10,15:13","dtypep":"(TPB)","keyword":"logic","range":"7:0","generic":true,"rangep": []} + {"type":"BASICDTYPE","name":"logic","addr":"(ALB)","loc":"d,15:10,15:13","dtypep":"(ALB)","keyword":"logic","range":"7:0","generic":true,"rangep": []} ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(BTB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(IOB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","verilogName":"@CONST-POOL@","level":0,"timeunit":"NONE","inlinesp": [], "stmtsp": [ - {"type":"SCOPE","name":"TOP","addr":"(CTB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BTB)","varsp": [],"blocksp": [],"inlinesp": []} + {"type":"SCOPE","name":"TOP","addr":"(JOB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(IOB)","varsp": [],"blocksp": [],"inlinesp": []} ]} ]} ]} diff --git a/test_regress/t/t_opt_merge_cond.py b/test_regress/t/t_opt_merge_cond.py index cd68237be..0d506462e 100755 --- a/test_regress/t/t_opt_merge_cond.py +++ b/test_regress/t/t_opt_merge_cond.py @@ -17,8 +17,8 @@ test.execute() if test.vlt: # Note, with vltmt this might be split differently, so only checking vlt - test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 9) - test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 580) - test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 128) + test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 11) + test.file_grep(test.stats, r'Optimizations, MergeCond merged items\s+(\d+)', 585) + test.file_grep(test.stats, r'Optimizations, MergeCond longest merge\s+(\d+)', 129) test.passes() diff --git a/test_regress/t/t_opt_merge_cond_relaxed.cpp b/test_regress/t/t_opt_merge_cond_relaxed.cpp new file mode 100644 index 000000000..46ba0eca5 --- /dev/null +++ b/test_regress/t/t_opt_merge_cond_relaxed.cpp @@ -0,0 +1,29 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#include "svdpi.h" + +#include + +extern "C" void setDpi(int value); + +extern "C" void setViaDpi(int value) { + std::cout << "setViaDpi " << value << std::endl; + setDpi(value); +} + +extern "C" int getDpi(); + +extern "C" int getViaDpi() { + const int value = getDpi(); + std::cout << "getViaDpi " << value << std::endl; + return value; +} diff --git a/test_regress/t/t_opt_merge_cond_relaxed.out b/test_regress/t/t_opt_merge_cond_relaxed.out new file mode 100644 index 000000000..fe880f5a1 --- /dev/null +++ b/test_regress/t/t_opt_merge_cond_relaxed.out @@ -0,0 +1,173 @@ +setViaDpi 3 +setViaDpi 6 +setViaDpi 4 +getViaDpi 2 +cnt= 4 pub= 1 +getViaDpi 24 +getViaDpi 24 +getViaDpi 100 +cnt= 8 pub= 2 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 18 +setViaDpi 34 +setViaDpi 32 +setViaDpi 6 +setViaDpi 4 +getViaDpi 2 +cnt= 12 pub= 3 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 35 +setViaDpi 67 +setViaDpi 3 +getViaDpi 2 +cnt= 16 pub= 4 +setViaDpi 6 +getViaDpi 2 +cnt= 20 pub= 5 +getViaDpi 24 +getViaDpi 24 +getViaDpi 100 +cnt= 24 pub= 6 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 22 +setViaDpi 38 +setViaDpi 36 +setViaDpi 3 +setViaDpi 6 +getViaDpi 2 +cnt= 28 pub= 7 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 39 +setViaDpi 71 +getViaDpi 2 +cnt= 32 pub= 8 +setViaDpi 6 +setViaDpi 4 +getViaDpi 2 +cnt= 36 pub= 9 +getViaDpi 24 +getViaDpi 24 +setViaDpi 3 +getViaDpi 100 +cnt= 40 pub= 10 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 26 +setViaDpi 42 +setViaDpi 40 +setViaDpi 6 +setViaDpi 4 +getViaDpi 2 +cnt= 44 pub= 11 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 43 +setViaDpi 75 +getViaDpi 2 +cnt= 48 pub= 12 +setViaDpi 3 +setViaDpi 6 +getViaDpi 2 +cnt= 52 pub= 13 +getViaDpi 24 +getViaDpi 24 +getViaDpi 100 +cnt= 56 pub= 14 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 30 +setViaDpi 46 +setViaDpi 44 +setViaDpi 6 +getViaDpi 2 +cnt= 60 pub= 15 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 47 +setViaDpi 79 +setViaDpi 3 +getViaDpi 2 +cnt= 64 pub= 16 +setViaDpi 6 +setViaDpi 4 +getViaDpi 2 +cnt= 68 pub= 17 +getViaDpi 24 +getViaDpi 24 +getViaDpi 100 +cnt= 72 pub= 18 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 34 +setViaDpi 50 +setViaDpi 48 +setViaDpi 3 +setViaDpi 6 +setViaDpi 4 +getViaDpi 2 +cnt= 76 pub= 19 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 51 +setViaDpi 83 +getViaDpi 2 +cnt= 80 pub= 20 +setViaDpi 6 +getViaDpi 2 +cnt= 84 pub= 21 +getViaDpi 24 +getViaDpi 24 +setViaDpi 3 +getViaDpi 100 +cnt= 88 pub= 22 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 38 +setViaDpi 54 +setViaDpi 52 +setViaDpi 6 +getViaDpi 2 +cnt= 92 pub= 23 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 55 +setViaDpi 87 +getViaDpi 2 +cnt= 96 pub= 24 +setViaDpi 3 +setViaDpi 6 +setViaDpi 4 +getViaDpi 2 +cnt=100 pub= 25 +getViaDpi 24 +getViaDpi 24 +getViaDpi 100 +cnt=104 pub= 26 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 42 +setViaDpi 58 +setViaDpi 56 +setViaDpi 6 +setViaDpi 4 +getViaDpi 2 +cnt=108 pub= 27 +cyc[1] is 1 once +cyc[1] is 1 twice +setViaDpi 59 +setViaDpi 91 +setViaDpi 3 +getViaDpi 2 +cnt=112 pub= 28 +setViaDpi 6 +getViaDpi 2 +cnt=116 pub= 29 +getViaDpi 24 +getViaDpi 24 +getViaDpi 100 +cnt=120 pub= 30 +*-* All Finished *-* diff --git a/test_regress/t/t_opt_merge_cond_relaxed.py b/test_regress/t/t_opt_merge_cond_relaxed.py new file mode 100755 index 000000000..e5af64dda --- /dev/null +++ b/test_regress/t/t_opt_merge_cond_relaxed.py @@ -0,0 +1,20 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt_all') + +test.compile(verilator_flags2=["--binary", "--stats", test.top_filename.replace(".v", ".cpp")]) + +test.file_grep(test.stats, r'Optimizations, MergeCond merges\s+(\d+)', 4) + +test.execute(expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_opt_merge_cond_relaxed.v b/test_regress/t/t_opt_merge_cond_relaxed.v new file mode 100644 index 000000000..c48e0f5e9 --- /dev/null +++ b/test_regress/t/t_opt_merge_cond_relaxed.v @@ -0,0 +1,133 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) + +module t; + + logic clk = 0; + always #5 clk = ~clk; + + initial begin + #300; + $write("*-* All Finished *-*\n"); + $finish; + end + + int cyc = 0; + always @(posedge clk) cyc <= cyc + 1; + + int dpiWr = 0; + function automatic void setDpi(int value); + dpiWr = value; + endfunction + export "DPI-C" function setDpi; + import "DPI-C" context function void setViaDpi(int value); // calls setDpi(value) + + int dpiRd = 0; + function automatic int getDpi(); + return dpiRd; + endfunction + export "DPI-C" function getDpi; + import "DPI-C" context function int getViaDpi(); // calls getDpi() + + int tmp; + int cnt = 0; + + int pub /* verilator public_flat_rd */ = 0; + + always @(posedge clk) begin + + //--------------------------- + // Mergeable + + // Side effect but no implicit state access. + if (cyc[1]) $display("cyc[1] is 1 once"); + ++cnt; + if (cyc[1]) $display("cyc[1] is 1 twice"); + + // Side effect but no implicit state access. + if (cyc > 100000) $error("cyc > 100000 once"); + ++cnt; + if (cyc > 100000) $error("cyc > 100000 once"); + + // DPI call, but no public state involved. + dpiWr = 13; + if (cyc[1:0] == 2'd2) setViaDpi(cyc + 16); + ++cnt; + if (cyc[1:0] == 2'd2) setViaDpi(cyc + 32); + `check(dpiWr, cyc % 4 == 2 ? cyc + 32 : 13); + + // DPI call, but no public state involved. + dpiRd = 24; + tmp = 10; + if (cyc[1:0] == 2'd1) begin + tmp = getViaDpi(); + tmp += 10; + end + ++cnt; + if (cyc[1:0] == 2'd1) begin + tmp = getViaDpi(); + tmp += 20; + end + `check(tmp, cyc % 4 == 1 ? 44 : 10); + + //--------------------------- + // NOT Mergeable + + // DPI call, possible implicit state chagne. + tmp = dpiWr; + if (dpiWr[1:0] == 2'd2) setViaDpi(dpiWr & ~32'b11); + if (dpiWr[1:0] == 2'd2) setViaDpi(dpiWr + 10); // Won't execute + `check(dpiWr, cyc % 4 == 2 ? (tmp & ~32'b11) : 13); + + // DPI call, possible implicit state acces. + dpiWr = 14; + if (cyc[1:0] == 2'd3) setViaDpi(cyc + 32); + ++pub; + if (cyc[1:0] == 2'd3) setViaDpi(cyc + 64); + `check(dpiWr, cyc % 4 == 3 ? cyc + 64 : 14); + + // DPI call, possible implicit state change. + dpiWr = 11; + tmp = cyc + $c(0); // Prevent repalcing with 'cyc' + if (tmp % 3 == 0) begin + setViaDpi(3); + tmp = dpiWr + 2; + end + if (tmp % 3 == 0) setViaDpi(4); // Won't execute + `check(dpiWr, cyc % 3 == 0 ? 3 : 11); + dpiWr = 3; + + // DPI call, possible implicit state change. + tmp = cyc + $c(0); // Prevent repalcing with 'cyc' + if (tmp % 2 == 0) begin + setViaDpi(6); + if (cyc[2]) tmp = dpiWr + 1; + end + if (tmp % 2 == 0) setViaDpi(4); // Sometime executes + `check(tmp, cyc % 2 == 0 ? (cyc[2] ? 7 : cyc) : cyc); + `check(dpiWr, cyc % 2 == 0 ? (cyc[2] ? 6 : 4) : 3); + + // DPI call, possible implicit state read. + dpiRd = 2; + if (cyc[1:0] == 2'd1) begin + dpiRd = 100; + end + tmp = getViaDpi(); + if (cyc[1:0] == 2'd1) begin + dpiRd = 3; + end + `check(tmp, cyc % 4 == 1 ? 100 : 2); + `check(dpiRd, cyc % 4 == 1 ? 3 : 2); + + //--------------------------- + // Dispaly so not eliminated + $display("cnt=%3d pub=%3d", cnt, pub); + end + +endmodule From 97838325cd3248ac153cce23fdd09332f02e0982 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sun, 1 Mar 2026 12:44:59 +0000 Subject: [PATCH 022/340] Fix scheduling non-determinism (#7120 partial) (#7162) --- src/V3Sched.cpp | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/V3Sched.cpp b/src/V3Sched.cpp index bef68595f..7795c51b5 100644 --- a/src/V3Sched.cpp +++ b/src/V3Sched.cpp @@ -827,10 +827,18 @@ std::unordered_map cloneMapWithNewTriggerReferences(const std::unordered_map& map, AstVarScope* vscp) { AstTopScope* const topScopep = v3Global.rootp()->topScopep(); - // Copy map - std::unordered_map newMap{map}; + // Label global SenTrees by the order they are in the Ast + const VNUser1InUse user1InUse; + int n = 0; + for (AstNode* nodep = topScopep->senTreesp(); nodep; nodep = nodep->nextp()) nodep->user1(++n); + // Sort map by key order for determinism + using Pair = std::pair; + std::vector pairs{map.begin(), map.end()}; + std::sort(pairs.begin(), pairs.end(), [](const Pair& a, const Pair& b) { // + return a.first->user1() < b.first->user1(); + }); // Replace references in each mapped value with a reference to the given vscp - for (auto& pair : newMap) { + for (Pair& pair : pairs) { pair.second = pair.second->cloneTree(false); pair.second->foreach([&](AstVarRef* refp) { UASSERT_OBJ(refp->access() == VAccess::READ, refp, "Should be read ref"); @@ -839,7 +847,8 @@ cloneMapWithNewTriggerReferences(const std::unordered_mapaddSenTreesp(pair.second); } - return newMap; + // Convert back to map + return std::unordered_map{pairs.begin(), pairs.end()}; } //============================================================================ From 9d8baa1e44bebb82a5df142c583cb0f7b102a3f8 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sun, 1 Mar 2026 13:27:46 +0000 Subject: [PATCH 023/340] Testing: Relax expected file count in t_flag_csplit_groups (#7163) --- test_regress/driver.py | 2 +- test_regress/t/t_flag_csplit_groups.py | 4 +++- test_regress/t/t_func_dotted_inl2.py | 2 +- test_regress/t/t_func_dotted_inl2_vlt.py | 2 +- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/test_regress/driver.py b/test_regress/driver.py index dd76f244f..9ccf0ac4d 100755 --- a/test_regress/driver.py +++ b/test_regress/driver.py @@ -2685,7 +2685,7 @@ class VlTest: self.error("File_grep: " + filename + ": Got='" + match.group(1) + "' Expected='" + str(expvalue) + "' in regexp: '" + regexp + "'") return None - return [match.groups()] + return match.groups() def file_grep_count(self, filename: str, regexp, expcount: int) -> None: contents = self.file_contents(filename) diff --git a/test_regress/t/t_flag_csplit_groups.py b/test_regress/t/t_flag_csplit_groups.py index c92448c9e..8210a6dbd 100755 --- a/test_regress/t/t_flag_csplit_groups.py +++ b/test_regress/t/t_flag_csplit_groups.py @@ -125,7 +125,9 @@ test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_clas test.file_grep_not(test.obj_dir + "/" + test.vm_prefix + "_classes.mk", "vm_classes_2") # Check combine count -test.file_grep(test.stats, r'Node count, CFILE + (\d+)', (276 if test.vltmt else 259)) +nFiles = int(test.file_grep(test.stats, r'Node count, CFILE + (\d+)')[0]) +if nFiles < 200: + test.error("Expecting >= 200 files, but got " + str(nFiles)) test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_FAST + (\d+)', 2) test.file_grep(test.stats, r'Makefile targets, VM_CLASSES_SLOW + (\d+)', 2) diff --git a/test_regress/t/t_func_dotted_inl2.py b/test_regress/t/t_func_dotted_inl2.py index 701407a39..958c06200 100755 --- a/test_regress/t/t_func_dotted_inl2.py +++ b/test_regress/t/t_func_dotted_inl2.py @@ -20,7 +20,7 @@ if test.vlt_all: modps = test.file_grep( out_filename, r'{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"\w,99:[^"]*",.*"origName":"mb"') - modp = modps[0][0] + modp = modps[0] test.file_grep( out_filename, r'{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"\w,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"', diff --git a/test_regress/t/t_func_dotted_inl2_vlt.py b/test_regress/t/t_func_dotted_inl2_vlt.py index bac3557bc..6b58a6ae3 100755 --- a/test_regress/t/t_func_dotted_inl2_vlt.py +++ b/test_regress/t/t_func_dotted_inl2_vlt.py @@ -19,7 +19,7 @@ if test.vlt_all: modps = test.file_grep( out_filename, r'{"type":"MODULE","name":"mb","addr":"([^"]*)","loc":"\w,99:[^"]*",.*"origName":"mb"') - modp = modps[0][0] + modp = modps[0] test.file_grep( out_filename, r'{"type":"CELL","name":"t.ma0.mb0","addr":"[^"]*","loc":"\w,87:[^"]*",.*"origName":"mb0",.*"modp":"([^"]*)"', From 3249fd8cc0aa3c2bc1141f2663b015627dac07a1 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sun, 1 Mar 2026 14:56:21 +0000 Subject: [PATCH 024/340] Internals: Mark Premit temporaries funcLocal, noReset (#7160) --- src/V3Premit.cpp | 2 ++ test_regress/t/t_json_only_debugcheck.out | 8 ++++---- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp index 6aaf86c4f..b64995044 100644 --- a/src/V3Premit.cpp +++ b/src/V3Premit.cpp @@ -91,6 +91,8 @@ class PremitVisitor final : public VNVisitor { // Keep as local temporary. const std::string name = "__Vtemp_" + std::to_string(++m_tmpVarCnt); varp = new AstVar{flp, VVarType::STMTTEMP, name, nodep->dtypep()}; + varp->funcLocal(true); + varp->noReset(true); m_cfuncp->addVarsp(varp); ++m_temporaryVarsCreated; diff --git a/test_regress/t/t_json_only_debugcheck.out b/test_regress/t/t_json_only_debugcheck.out index 580b84469..3bb6aa5b7 100644 --- a/test_regress/t/t_json_only_debugcheck.out +++ b/test_regress/t/t_json_only_debugcheck.out @@ -49,7 +49,7 @@ ]}, {"type":"CFUNC","name":"_eval_initial__TOP","addr":"(QB)","loc":"d,11:8,11:9","slow":true,"scopep":"(Z)","argsp": [], "varsp": [ - {"type":"VAR","name":"__Vtemp_1","addr":"(RB)","loc":"d,49:120,49:121","dtypep":"(SB)","origName":"__Vtemp_1","verilogName":"__Vtemp_1","direction":"NONE","lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"__Vtemp_1","addr":"(RB)","loc":"d,49:120,49:121","dtypep":"(SB)","origName":"__Vtemp_1","verilogName":"__Vtemp_1","direction":"NONE","noReset":true,"isFuncLocal":true,"lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(TB)","loc":"d,32:9,32:10","dtypep":"(UB)", @@ -868,9 +868,9 @@ "lhsp": [ {"type":"VARREF","name":"__Vdly__t.e","addr":"(XN)","loc":"d,24:9,24:10","dtypep":"(M)","access":"WR","varp":"(UN)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": []}, - {"type":"VAR","name":"__Vtemp_1","addr":"(YN)","loc":"d,70:123,70:124","dtypep":"(SB)","origName":"__Vtemp_1","verilogName":"__Vtemp_1","direction":"NONE","lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"__Vtemp_2","addr":"(ZN)","loc":"d,80:123,80:124","dtypep":"(SB)","origName":"__Vtemp_2","verilogName":"__Vtemp_2","direction":"NONE","lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, - {"type":"VAR","name":"__Vtemp_3","addr":"(AO)","loc":"d,90:123,90:124","dtypep":"(SB)","origName":"__Vtemp_3","verilogName":"__Vtemp_3","direction":"NONE","lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} + {"type":"VAR","name":"__Vtemp_1","addr":"(YN)","loc":"d,70:123,70:124","dtypep":"(SB)","origName":"__Vtemp_1","verilogName":"__Vtemp_1","direction":"NONE","noReset":true,"isFuncLocal":true,"lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"__Vtemp_2","addr":"(ZN)","loc":"d,80:123,80:124","dtypep":"(SB)","origName":"__Vtemp_2","verilogName":"__Vtemp_2","direction":"NONE","noReset":true,"isFuncLocal":true,"lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, + {"type":"VAR","name":"__Vtemp_3","addr":"(AO)","loc":"d,90:123,90:124","dtypep":"(SB)","origName":"__Vtemp_3","verilogName":"__Vtemp_3","direction":"NONE","noReset":true,"isFuncLocal":true,"lifetime":"NONE","varType":"STMTTEMP","dtypeName":"string","sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ], "stmtsp": [ {"type":"ASSIGN","name":"","addr":"(BO)","loc":"d,23:17,23:20","dtypep":"(S)", From 6c48b3282ec6649b6920681a0a7c505e8797ad79 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sun, 1 Mar 2026 15:04:49 +0000 Subject: [PATCH 025/340] Enable V3LiftExpr with code coverage (#7164) --- src/Verilator.cpp | 10 +- test_regress/t/t_cover_line.out | 26 +- test_regress/t/t_cover_line_cc.info.out | 22 +- test_regress/t/t_cover_line_trace.out | 1109 +++++++++++------------ test_regress/t/t_cover_line_trace.py | 1 - 5 files changed, 542 insertions(+), 626 deletions(-) diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 8d4ef283d..f30e13820 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -285,13 +285,9 @@ static void process() { } if (!v3Global.opt.serializeOnly()) { - // Lift expressions out of statements. Currently disabled for line and - // expression coverage, as otherwise later V3Split would further split - // combinational always blocks and alter counts (that needs to be fixed in V3Split) - if (v3Global.opt.fLiftExpr() // - && !v3Global.opt.coverageLine() && !v3Global.opt.coverageExpr()) { - V3LiftExpr::liftExprAll(v3Global.rootp()); - } + // Lift expressions out of statements. + if (v3Global.opt.fLiftExpr()) V3LiftExpr::liftExprAll(v3Global.rootp()); + // Move assignments from X into MODULE temps. // (Before flattening, so each new X variable is shared between all scopes of that // module.) diff --git a/test_regress/t/t_cover_line.out b/test_regress/t/t_cover_line.out index e04e40fbc..77bcb7402 100644 --- a/test_regress/t/t_cover_line.out +++ b/test_regress/t/t_cover_line.out @@ -449,12 +449,12 @@ logic unsigned [15:0] b; } pstruct; - 000021 function logic func_side_effect; -+000021 point: type=line comment=block hier=top.t.cond1 - 000021 $display("SIDE EFFECT"); -+000021 point: type=line comment=block hier=top.t.cond1 - 000021 return 1; -+000021 point: type=line comment=block hier=top.t.cond1 +%000001 function logic func_side_effect; +-000001 point: type=line comment=block hier=top.t.cond1 +%000001 $display("SIDE EFFECT"); +-000001 point: type=line comment=block hier=top.t.cond1 +%000001 return 1; +-000001 point: type=line comment=block hier=top.t.cond1 endfunction 000010 function arr_t get_arr; @@ -465,14 +465,14 @@ +000010 point: type=line comment=block hier=top.t.cond1 endfunction -~000031 assign a = (cyc == 0) ? clk : 1'bz; +~000011 assign a = (cyc == 0) ? clk : 1'bz; -000000 point: type=branch comment=cond_then hier=top.t.cond1 -+000031 point: type=branch comment=cond_else hier=top.t.cond1 ++000011 point: type=branch comment=cond_else hier=top.t.cond1 ~000028 assign b = (cyc == 1) ? clk : 0; -000003 point: type=branch comment=cond_then hier=top.t.cond1 +000028 point: type=branch comment=cond_else hier=top.t.cond1 -~000021 assign c = func_side_effect() ? clk : 0; -+000021 point: type=branch comment=cond_then hier=top.t.cond1 +%000001 assign c = func_side_effect() ? clk : 0; +-000001 point: type=branch comment=cond_then hier=top.t.cond1 -000000 point: type=branch comment=cond_else hier=top.t.cond1 000010 always @(posedge clk) begin +000010 point: type=line comment=block hier=top.t.cond1 @@ -500,9 +500,9 @@ assign m = tab[clk ? 3 : 4]; for (genvar i = 0; i < 2; i++) begin - 000011 assign g = clk ? 1 : 0; -+000010 point: type=branch comment=cond_then hier=top.t.cond1 -+000011 point: type=branch comment=cond_else hier=top.t.cond1 + 000022 assign g = clk ? 1 : 0; ++000020 point: type=branch comment=cond_then hier=top.t.cond1 ++000022 point: type=branch comment=cond_else hier=top.t.cond1 end 000011 always begin diff --git a/test_regress/t/t_cover_line_cc.info.out b/test_regress/t/t_cover_line_cc.info.out index 6e42f53a9..9c6059f0f 100644 --- a/test_regress/t/t_cover_line_cc.info.out +++ b/test_regress/t/t_cover_line_cc.info.out @@ -150,20 +150,20 @@ DA:304,1 DA:305,20 DA:306,20 DA:315,1 -DA:323,21 -DA:324,21 -DA:325,21 +DA:323,1 +DA:324,1 +DA:325,1 DA:328,10 DA:329,10 DA:330,10 -DA:333,31 +DA:333,11 BRDA:333,0,0,0 -BRDA:333,0,1,31 +BRDA:333,0,1,11 DA:334,28 BRDA:334,0,0,3 BRDA:334,0,1,28 -DA:335,21 -BRDA:335,0,0,21 +DA:335,1 +BRDA:335,0,0,1 BRDA:335,0,1,0 DA:336,10 DA:337,10 @@ -182,9 +182,9 @@ BRDA:340,0,3,5 DA:343,11 BRDA:343,0,0,11 BRDA:343,0,1,0 -DA:349,11 -BRDA:349,0,0,10 -BRDA:349,0,1,11 +DA:349,22 +BRDA:349,0,0,20 +BRDA:349,0,1,22 DA:352,11 DA:353,10 BRDA:353,0,0,0 @@ -218,5 +218,5 @@ DA:374,9 BRDA:374,0,0,1 BRDA:374,0,1,9 BRF:83 -BRH:33 +BRH:32 end_of_record diff --git a/test_regress/t/t_cover_line_trace.out b/test_regress/t/t_cover_line_trace.out index fee3a1c28..57c616be0 100644 --- a/test_regress/t/t_cover_line_trace.out +++ b/test_regress/t/t_cover_line_trace.out @@ -3,140 +3,140 @@ $timescale 1ps $end $scope module top $end $var wire 1 cyc_copy [7:0] $end - $var wire 32 ? vlCoverageLineTrace_t_cover_line__55_block [31:0] $end - $var wire 32 @ vlCoverageLineTrace_t_cover_line__56_else [31:0] $end - $var wire 32 A vlCoverageLineTrace_t_cover_line__56_if [31:0] $end - $var wire 32 B vlCoverageLineTrace_t_cover_line__60_else [31:0] $end - $var wire 32 C vlCoverageLineTrace_t_cover_line__60_if [31:0] $end - $var wire 32 D vlCoverageLineTrace_t_cover_line__61_else [31:0] $end - $var wire 32 E vlCoverageLineTrace_t_cover_line__61_if [31:0] $end - $var wire 32 F vlCoverageLineTrace_t_cover_line__66_else [31:0] $end - $var wire 32 G vlCoverageLineTrace_t_cover_line__66_if [31:0] $end - $var wire 32 H vlCoverageLineTrace_t_cover_line__67_else [31:0] $end - $var wire 32 I vlCoverageLineTrace_t_cover_line__67_if [31:0] $end - $var wire 32 J vlCoverageLineTrace_t_cover_line__73_else [31:0] $end - $var wire 32 K vlCoverageLineTrace_t_cover_line__73_if [31:0] $end - $var wire 32 L vlCoverageLineTrace_t_cover_line__74_else [31:0] $end - $var wire 32 M vlCoverageLineTrace_t_cover_line__74_if [31:0] $end - $var wire 32 N vlCoverageLineTrace_t_cover_line__83_elsif [31:0] $end - $var wire 32 O vlCoverageLineTrace_t_cover_line__87_elsif [31:0] $end - $var wire 32 P vlCoverageLineTrace_t_cover_line__91_else [31:0] $end - $var wire 32 Q vlCoverageLineTrace_t_cover_line__91_if [31:0] $end + $var wire 8 D cyc_copy [7:0] $end + $var wire 32 E vlCoverageLineTrace_t_cover_line__55_block [31:0] $end + $var wire 32 F vlCoverageLineTrace_t_cover_line__56_else [31:0] $end + $var wire 32 G vlCoverageLineTrace_t_cover_line__56_if [31:0] $end + $var wire 32 H vlCoverageLineTrace_t_cover_line__60_else [31:0] $end + $var wire 32 I vlCoverageLineTrace_t_cover_line__60_if [31:0] $end + $var wire 32 J vlCoverageLineTrace_t_cover_line__61_else [31:0] $end + $var wire 32 K vlCoverageLineTrace_t_cover_line__61_if [31:0] $end + $var wire 32 L vlCoverageLineTrace_t_cover_line__66_else [31:0] $end + $var wire 32 M vlCoverageLineTrace_t_cover_line__66_if [31:0] $end + $var wire 32 N vlCoverageLineTrace_t_cover_line__67_else [31:0] $end + $var wire 32 O vlCoverageLineTrace_t_cover_line__67_if [31:0] $end + $var wire 32 P vlCoverageLineTrace_t_cover_line__73_else [31:0] $end + $var wire 32 Q vlCoverageLineTrace_t_cover_line__73_if [31:0] $end + $var wire 32 R vlCoverageLineTrace_t_cover_line__74_else [31:0] $end + $var wire 32 S vlCoverageLineTrace_t_cover_line__74_if [31:0] $end + $var wire 32 T vlCoverageLineTrace_t_cover_line__83_elsif [31:0] $end + $var wire 32 U vlCoverageLineTrace_t_cover_line__87_elsif [31:0] $end + $var wire 32 V vlCoverageLineTrace_t_cover_line__91_else [31:0] $end + $var wire 32 W vlCoverageLineTrace_t_cover_line__91_if [31:0] $end $var wire 32 C! vlCoverageLineTrace_t_cover_line__100_block [31:0] $end $var wire 32 D! vlCoverageLineTrace_t_cover_line__101_block [31:0] $end $var wire 32 E! vlCoverageLineTrace_t_cover_line__104_block [31:0] $end $var wire 32 F! vlCoverageLineTrace_t_cover_line__105_block [31:0] $end - $var wire 32 R vlCoverageLineTrace_t_cover_line__107_block [31:0] $end - $var wire 32 S vlCoverageLineTrace_t_cover_line__110_elsif [31:0] $end - $var wire 32 T vlCoverageLineTrace_t_cover_line__113_elsif [31:0] $end - $var wire 32 U vlCoverageLineTrace_t_cover_line__120_else [31:0] $end - $var wire 32 V vlCoverageLineTrace_t_cover_line__120_if [31:0] $end + $var wire 32 X vlCoverageLineTrace_t_cover_line__107_block [31:0] $end + $var wire 32 Y vlCoverageLineTrace_t_cover_line__110_elsif [31:0] $end + $var wire 32 Z vlCoverageLineTrace_t_cover_line__113_elsif [31:0] $end + $var wire 32 [ vlCoverageLineTrace_t_cover_line__120_else [31:0] $end + $var wire 32 \ vlCoverageLineTrace_t_cover_line__120_if [31:0] $end $var wire 32 =! vlCoverageLineTrace_t_cover_line__127_block [31:0] $end $scope module a1 $end $var wire 1 ! m $end - $var wire 6 + tab [5:0] $end - $var wire 8 c data[0][0] [7:0] $end - $var wire 8 d data[0][1] [7:0] $end - $var wire 8 e data[1][0] [7:0] $end - $var wire 8 f data[1][1] [7:0] $end + $var wire 6 2 tab [5:0] $end + $var wire 8 h data[0][0] [7:0] $end + $var wire 8 i data[0][1] [7:0] $end + $var wire 8 j data[1][0] [7:0] $end + $var wire 8 k data[1][1] [7:0] $end $var wire 32 $ vlCoverageLineTrace_t_cover_line__315_block [31:0] $end - $var wire 32 g pstruct [31:0] $end - $var wire 32 , vlCoverageLineTrace_t_cover_line__323_block [31:0] $end - $var wire 32 h vlCoverageLineTrace_t_cover_line__328_block [31:0] $end - $var wire 8 H! get_arr__Vstatic__arr[0] [7:0] $end - $var wire 8 I! get_arr__Vstatic__arr[1] [7:0] $end - $var wire 32 4 vlCoverageLineTrace_t_cover_line__333_cond_else [31:0] $end - $var wire 32 5 vlCoverageLineTrace_t_cover_line__333_cond_then [31:0] $end - $var wire 32 6 vlCoverageLineTrace_t_cover_line__334_cond_else [31:0] $end - $var wire 32 7 vlCoverageLineTrace_t_cover_line__334_cond_then [31:0] $end - $var wire 32 - vlCoverageLineTrace_t_cover_line__335_cond_else [31:0] $end - $var wire 32 . vlCoverageLineTrace_t_cover_line__335_cond_then [31:0] $end - $var wire 32 i vlCoverageLineTrace_t_cover_line__336_block [31:0] $end - $var wire 32 j vlCoverageLineTrace_t_cover_line__337_cond_else [31:0] $end - $var wire 32 k vlCoverageLineTrace_t_cover_line__337_cond_then [31:0] $end - $var wire 32 l vlCoverageLineTrace_t_cover_line__338_cond_else [31:0] $end - $var wire 32 m vlCoverageLineTrace_t_cover_line__338_cond_then [31:0] $end - $var wire 32 8 vlCoverageLineTrace_t_cover_line__340_cond_else_1 [31:0] $end - $var wire 32 9 vlCoverageLineTrace_t_cover_line__340_cond_then_1 [31:0] $end - $var wire 32 : vlCoverageLineTrace_t_cover_line__340_cond_else [31:0] $end - $var wire 32 ; vlCoverageLineTrace_t_cover_line__340_cond_then [31:0] $end - $var wire 32 n vlCoverageLineTrace_t_cover_line__343_cond_else [31:0] $end - $var wire 32 o vlCoverageLineTrace_t_cover_line__343_cond_then [31:0] $end - $var wire 32 J! vlCoverageLineTrace_t_cover_line__349_cond_else [31:0] $end - $var wire 32 / vlCoverageLineTrace_t_cover_line__349_cond_else_1 [31:0] $end - $var wire 32 K! vlCoverageLineTrace_t_cover_line__349_cond_then [31:0] $end - $var wire 32 0 vlCoverageLineTrace_t_cover_line__349_cond_then_1 [31:0] $end - $var wire 32 % vlCoverageLineTrace_t_cover_line__352_block [31:0] $end - $var wire 32 p vlCoverageLineTrace_t_cover_line__353_else [31:0] $end - $var wire 32 q vlCoverageLineTrace_t_cover_line__353_if [31:0] $end - $var wire 32 r vlCoverageLineTrace_t_cover_line__353_cond_else [31:0] $end - $var wire 32 s vlCoverageLineTrace_t_cover_line__353_cond_then [31:0] $end - $var wire 32 t vlCoverageLineTrace_t_cover_line__356_cond_else [31:0] $end - $var wire 32 u vlCoverageLineTrace_t_cover_line__356_cond_then [31:0] $end - $var wire 32 & vlCoverageLineTrace_t_cover_line__359_block [31:0] $end - $var wire 32 v vlCoverageLineTrace_t_cover_line__362_block [31:0] $end - $var wire 32 w vlCoverageLineTrace_t_cover_line__362_cond_else [31:0] $end - $var wire 32 x vlCoverageLineTrace_t_cover_line__362_cond_then [31:0] $end - $var wire 32 y vlCoverageLineTrace_t_cover_line__366_else [31:0] $end - $var wire 32 z vlCoverageLineTrace_t_cover_line__366_if [31:0] $end + $var wire 32 l pstruct [31:0] $end + $var wire 32 % vlCoverageLineTrace_t_cover_line__323_block [31:0] $end + $var wire 32 m vlCoverageLineTrace_t_cover_line__328_block [31:0] $end + $var wire 8 & get_arr__Vstatic__arr[0] [7:0] $end + $var wire 8 ' get_arr__Vstatic__arr[1] [7:0] $end + $var wire 32 : vlCoverageLineTrace_t_cover_line__333_cond_else [31:0] $end + $var wire 32 ; vlCoverageLineTrace_t_cover_line__333_cond_then [31:0] $end + $var wire 32 < vlCoverageLineTrace_t_cover_line__334_cond_else [31:0] $end + $var wire 32 = vlCoverageLineTrace_t_cover_line__334_cond_then [31:0] $end + $var wire 32 I! vlCoverageLineTrace_t_cover_line__335_cond_else [31:0] $end + $var wire 32 ( vlCoverageLineTrace_t_cover_line__335_cond_then [31:0] $end + $var wire 32 n vlCoverageLineTrace_t_cover_line__336_block [31:0] $end + $var wire 32 o vlCoverageLineTrace_t_cover_line__337_cond_else [31:0] $end + $var wire 32 p vlCoverageLineTrace_t_cover_line__337_cond_then [31:0] $end + $var wire 32 q vlCoverageLineTrace_t_cover_line__338_cond_else [31:0] $end + $var wire 32 r vlCoverageLineTrace_t_cover_line__338_cond_then [31:0] $end + $var wire 32 > vlCoverageLineTrace_t_cover_line__340_cond_else_1 [31:0] $end + $var wire 32 ? vlCoverageLineTrace_t_cover_line__340_cond_then_1 [31:0] $end + $var wire 32 @ vlCoverageLineTrace_t_cover_line__340_cond_else [31:0] $end + $var wire 32 A vlCoverageLineTrace_t_cover_line__340_cond_then [31:0] $end + $var wire 32 s vlCoverageLineTrace_t_cover_line__343_cond_else [31:0] $end + $var wire 32 t vlCoverageLineTrace_t_cover_line__343_cond_then [31:0] $end + $var wire 32 3 vlCoverageLineTrace_t_cover_line__349_cond_else [31:0] $end + $var wire 32 4 vlCoverageLineTrace_t_cover_line__349_cond_else_1 [31:0] $end + $var wire 32 5 vlCoverageLineTrace_t_cover_line__349_cond_then [31:0] $end + $var wire 32 6 vlCoverageLineTrace_t_cover_line__349_cond_then_1 [31:0] $end + $var wire 32 ) vlCoverageLineTrace_t_cover_line__352_block [31:0] $end + $var wire 32 u vlCoverageLineTrace_t_cover_line__353_else [31:0] $end + $var wire 32 v vlCoverageLineTrace_t_cover_line__353_if [31:0] $end + $var wire 32 w vlCoverageLineTrace_t_cover_line__353_cond_else [31:0] $end + $var wire 32 x vlCoverageLineTrace_t_cover_line__353_cond_then [31:0] $end + $var wire 32 y vlCoverageLineTrace_t_cover_line__356_cond_else [31:0] $end + $var wire 32 z vlCoverageLineTrace_t_cover_line__356_cond_then [31:0] $end + $var wire 32 * vlCoverageLineTrace_t_cover_line__359_block [31:0] $end + $var wire 32 + vlCoverageLineTrace_t_cover_line__362_block [31:0] $end + $var wire 32 , vlCoverageLineTrace_t_cover_line__362_cond_else [31:0] $end + $var wire 32 - vlCoverageLineTrace_t_cover_line__362_cond_then [31:0] $end + $var wire 32 . vlCoverageLineTrace_t_cover_line__366_else [31:0] $end + $var wire 32 J! vlCoverageLineTrace_t_cover_line__366_if [31:0] $end $var wire 32 { vlCoverageLineTrace_t_cover_line__370_cond_else [31:0] $end $var wire 32 | vlCoverageLineTrace_t_cover_line__370_cond_then [31:0] $end $var wire 32 } vlCoverageLineTrace_t_cover_line__373_block [31:0] $end @@ -145,22 +145,22 @@ $timescale 1ps $end $upscope $end $scope module o1 $end $var wire 1 -b00000000000000000000000000000000 ? -b00000000000000000000000000000000 @ +b00000000000000000000000000000000 < +b00000000000000000000000000000010 = +b00000000000000000000000000000000 > +b00000000000000000000000000000010 ? +b00000000000000000000000000000010 @ b00000000000000000000000000000000 A -b00000000000000000000000000000000 B -b00000000000000000000000000000000 C -b00000000000000000000000000000000 D +0B +b00000000000000000000000000000001 C +b00000001 D b00000000000000000000000000000000 E b00000000000000000000000000000000 F b00000000000000000000000000000000 G @@ -248,32 +248,32 @@ b00000000000000000000000000000000 [ b00000000000000000000000000000000 \ b00000000000000000000000000000000 ] b00000000000000000000000000000000 ^ -0_ -1` -1a -0b -b00000000 c -b00000000 d -b00000000 e -b00000000 f -b00000000000000100000000000000000 g -b00000000000000000000000000000001 h -b00000000000000000000000000000000 i -b00000000000000000000000000000000 j -b00000000000000000000000000000000 k -b00000000000000000000000000000000 l -b00000000000000000000000000000000 m +b00000000000000000000000000000000 _ +b00000000000000000000000000000000 ` +b00000000000000000000000000000000 a +b00000000000000000000000000000000 b +b00000000000000000000000000000000 c +b00000000000000000000000000000000 d +0e +1f +1g +b00000000 h +b00000000 i +b00000000 j +b00000000 k +b00000000000000100000000000000000 l +b00000000000000000000000000000001 m b00000000000000000000000000000000 n -b00000000000000000000000000000001 o -b00000000000000000000000000000001 p +b00000000000000000000000000000000 o +b00000000000000000000000000000000 p b00000000000000000000000000000000 q b00000000000000000000000000000000 r b00000000000000000000000000000000 s b00000000000000000000000000000001 t -b00000000000000000000000000000000 u -b00000000000000000000000000000100 v -b00000000000000000000000000000011 w -b00000000000000000000000000000001 x +b00000000000000000000000000000001 u +b00000000000000000000000000000000 v +b00000000000000000000000000000000 w +b00000000000000000000000000000000 x b00000000000000000000000000000001 y b00000000000000000000000000000000 z b00000000000000000000000000000000 { @@ -319,63 +319,56 @@ b00000000000000000000000000000000 D! b00000000000000000000000000000000 E! b00000000000000000000000000000000 F! 0G! -b00000000 H! -b00000000 I! +0H! +b00000000000000000000000000000000 I! b00000000000000000000000000000000 J! b00000000000000000000000000000000 K! -b00000000000000000000000000000000 L! -b00000000000000000000000000000010 M! +b00000000000000000000000000000010 L! +b00000000000000000000000000000000 M! b00000000000000000000000000000000 N! b00000000000000000000000000000000 O! b00000000000000000000000000000000 P! b00000000000000000000000000000000 Q! -b00000000000000000000000000000000 R! #10 -1) -1* -b000011 + -b00000000000000000000000000000011 , -b00000000000000000000000000000011 . -b00000000000000000000000000000001 0 -13 -b00000000000000000000000000000100 4 +11 +b000011 2 +b00000000000000000000000000000001 5 b00000000000000000000000000000001 6 -b00000000000000000000000000000011 7 -b00000000000000000000000000000001 8 -b00000000000000000000000000000011 9 -b00000000000000000000000000000001 ; -b00000000000000000000000000000010 = -b00000010 > -b00000000000000000000000000000001 ? +19 +b00000000000000000000000000000100 : +b00000000000000000000000000000001 < +b00000000000000000000000000000011 = +b00000000000000000000000000000001 > +b00000000000000000000000000000011 ? b00000000000000000000000000000001 A -b00000000000000000000000000000001 B -b00000000000000000000000000000001 D -b00000000000000000000000000000001 F +b00000000000000000000000000000010 C +b00000010 D +b00000000000000000000000000000001 E +b00000000000000000000000000000001 G b00000000000000000000000000000001 H b00000000000000000000000000000001 J b00000000000000000000000000000001 L +b00000000000000000000000000000001 N b00000000000000000000000000000001 P b00000000000000000000000000000001 R -b00000000000000000000000000000001 U -b00000000000000000000000000000001 W +b00000000000000000000000000000001 V b00000000000000000000000000000001 X -b00000000000000000000000000000001 Z b00000000000000000000000000000001 [ -b00000000000000000000000000000001 \ +b00000000000000000000000000000001 ] b00000000000000000000000000000001 ^ -b00000010 c -b00000001 d -b00000000000000110000000000000000 g -b00000000000000000000000000000001 i -b00000000000000000000000000000001 j -b00000000000000000000000000000001 l -b00000000000000000000000000000010 o -b00000000000000000000000000000010 p -b00000000000000000000000000000001 u -b00000000000000000000000000001000 v -b00000000000000000000000000000110 w -b00000000000000000000000000000010 x -b00000000000000000000000000000010 y +b00000000000000000000000000000001 ` +b00000000000000000000000000000001 a +b00000000000000000000000000000001 b +b00000000000000000000000000000001 d +b00000010 h +b00000001 i +b00000000000000110000000000000000 l +b00000000000000000000000000000001 n +b00000000000000000000000000000001 o +b00000000000000000000000000000001 q +b00000000000000000000000000000010 t +b00000000000000000000000000000010 u +b00000000000000000000000000000001 z b00000000000000000000000000000001 { b00000000000000000000000000000001 } b00000000000000000000000000000001 ~ @@ -399,56 +392,48 @@ b00000000000000000000000000000001 ;! b00000000000000000000000000000001 ?! b00000000000000000000000000000001 @! #15 -0) -0* -b00000000000000000000000000000100 , -b00000000000000000000000000000100 . -b00000000000000000000000000000011 / -b00000000000000000000000000000101 4 -b00000000000000000000000000000010 6 -b00000000000000000000000000000010 8 +01 +b00000000000000000000000000000011 3 +b00000000000000000000000000000011 4 +b00000000000000000000000000000101 : +b00000000000000000000000000000010 < +b00000000000000000000000000000010 > 0 -b00000000000000000000000000000010 ? -b00000000000000000000000000000010 A -b00000000000000000000000000000010 B -b00000000000000000000000000000010 D -b00000000000000000000000000000010 F +11 +b00000000000000000000000000000010 5 +b00000000000000000000000000000010 6 +b00000000000000000000000000000111 : +b00000000000000000000000000000100 < +b00000000000000000000000000000100 > +b00000000000000000000000000000011 C +b00000011 D +b00000000000000000000000000000010 E +b00000000000000000000000000000010 G b00000000000000000000000000000010 H b00000000000000000000000000000010 J b00000000000000000000000000000010 L +b00000000000000000000000000000010 N b00000000000000000000000000000010 P b00000000000000000000000000000010 R -b00000000000000000000000000000010 U -b00000000000000000000000000000010 W +b00000000000000000000000000000010 V b00000000000000000000000000000010 X -b00000000000000000000000000000010 Z b00000000000000000000000000000010 [ -b00000000000000000000000000000010 \ +b00000000000000000000000000000010 ] b00000000000000000000000000000010 ^ -b00000000 c -b00000000 d -b00000000000000000000000000000010 h -b00000000000000000000000000000010 i -b00000000000000000000000000000010 j -b00000000000000000000000000000010 l -b00000000000000000000000000000011 o -b00000000000000000000000000000011 p -b00000000000000000000000000000010 t -b00000000000000000000000000001100 v -b00000000000000000000000000001001 w -b00000000000000000000000000000011 x -b00000000000000000000000000000011 y +b00000000000000000000000000000010 ` +b00000000000000000000000000000010 a +b00000000000000000000000000000010 b +b00000000000000000000000000000010 d +b00000000 h +b00000000 i +b00000000000000000000000000000010 m +b00000000000000000000000000000010 n +b00000000000000000000000000000010 o +b00000000000000000000000000000010 q +b00000000000000000000000000000011 t +b00000000000000000000000000000011 u +b00000000000000000000000000000010 y b00000000000000000000000000000010 { b00000000000000000000000000000010 } b00000000000000000000000000000001 !! @@ -473,58 +458,50 @@ b00000000000000000000000000000010 ;! b00000000000000000000000000000010 ?! b00000000000000000000000000000010 @! #25 -0) -0* -b00000000000000000000000000000110 , -b00000000000000000000000000000110 . -b00000000000000000000000000000100 / -b00000000000000000000000000001000 4 -b00000000000000000000000000000101 6 -b00000000000000000000000000000101 8 +01 +b00000000000000000000000000000100 3 +b00000000000000000000000000000100 4 +b00000000000000000000000000001000 : +b00000000000000000000000000000101 < +b00000000000000000000000000000101 > 0 -b00000000000000000000000000000011 ? -b00000000000000000000000000000011 A -b00000000000000000000000000000001 C -b00000000000000000000000000000001 E -b00000000000000000000000000000001 G +11 +b00000000000000000000000000000011 5 +b00000000000000000000000000000011 6 +b00000000000000000000000000001010 : +b00000000000000000000000000000111 < +b00000000000000000000000000000110 > +b00000000000000000000000000000100 ? +b00000000000000000000000000000010 A +1B +b00000000000000000000000000000100 C +b00000100 D +b00000000000000000000000000000011 E +b00000000000000000000000000000011 G b00000000000000000000000000000001 I b00000000000000000000000000000001 K b00000000000000000000000000000001 M -b00000000000000000000000000000001 N -b00000000000000000000000000000011 R +b00000000000000000000000000000001 O +b00000000000000000000000000000001 Q b00000000000000000000000000000001 S -b00000000000000000000000000000011 W +b00000000000000000000000000000001 T b00000000000000000000000000000011 X -b00000000000000000000000000000011 Z -b00000000000000000000000000000011 [ -b00000000000000000000000000000011 \ +b00000000000000000000000000000001 Y +b00000000000000000000000000000011 ] b00000000000000000000000000000011 ^ -1_ -b00000000000000000000000000000011 h -b00000000000000000000000000000011 i -b00000000000000000000000000000001 k -b00000000000000000000000000000011 l -b00000000000000000000000000000100 o -b00000000000000000000000000000100 p -b00000000000000000000000000000011 t -b00000000000000000000000000010000 v -b00000000000000000000000000001100 w -b00000000000000000000000000000100 x -b00000000000000000000000000000100 y +b00000000000000000000000000000011 ` +b00000000000000000000000000000011 a +b00000000000000000000000000000011 b +b00000000000000000000000000000011 d +1e +b00000000000000000000000000000011 m +b00000000000000000000000000000011 n +b00000000000000000000000000000001 p +b00000000000000000000000000000011 q +b00000000000000000000000000000100 t +b00000000000000000000000000000100 u +b00000000000000000000000000000011 y b00000000000000000000000000000011 { b00000000000000000000000000000011 } b00000000000000000000000000000010 ~ @@ -549,61 +526,53 @@ b00000000000000000000000000000011 ;! b00000000000000000000000000000011 ?! b00000000000000000000000000000011 @! #35 -0) -0* -b00000000000000000000000000001000 , -b00000000000000000000000000001000 . -b00000000000000000000000000000101 / -03 -b00000000000000000000000000001011 4 -b00000000000000000000000000001000 6 -b00000000000000000000000000000101 9 -b00000000000000000000000000000011 : +01 +b00000000000000000000000000000101 3 +b00000000000000000000000000000101 4 +09 +b00000000000000000000000000001011 : +b00000000000000000000000000001000 < +b00000000000000000000000000000101 ? +b00000000000000000000000000000011 @ 0 -b00000000000000000000000000000100 ? -b00000000000000000000000000000100 A -b00000000000000000000000000000011 B -b00000000000000000000000000000011 D -b00000000000000000000000000000011 F +11 +b00000000000000000000000000000100 5 +b00000000000000000000000000000100 6 +19 +b00000000000000000000000000001101 : +b00000000000000000000000000001010 < +b00000000000000000000000000000111 > +b00000000000000000000000000000110 ? +b00000000000000000000000000000011 A +0B +b00000000000000000000000000000101 C +b00000101 D +b00000000000000000000000000000100 E +b00000000000000000000000000000100 G b00000000000000000000000000000011 H b00000000000000000000000000000011 J b00000000000000000000000000000011 L -b00000000000000000000000000000001 O -b00000000000000000000000000000100 R -b00000000000000000000000000000011 U -b00000000000000000000000000000100 W -b00000000000000000000000000000001 Y -b00000000000000000000000000000100 [ -b00000000000000000000000000000001 ] -0_ -0a -b00000000000000000000000000000100 h -b00000000000000000000000000000100 i -b00000000000000000000000000000011 j -b00000000000000000000000000000100 l -b00000000000000000000000000000101 o -b00000000000000000000000000000001 q -b00000000000000000000000000000001 r -b00000000000000000000000000000100 t -b00000000000000000000000000010100 v -b00000000000000000000000000001111 w -b00000000000000000000000000000101 x -b00000000000000000000000000000101 y +b00000000000000000000000000000011 N +b00000000000000000000000000000011 P +b00000000000000000000000000000011 R +b00000000000000000000000000000001 U +b00000000000000000000000000000100 X +b00000000000000000000000000000011 [ +b00000000000000000000000000000100 ] +b00000000000000000000000000000001 _ +b00000000000000000000000000000100 a +b00000000000000000000000000000001 c +0e +0g +b00000000000000000000000000000100 m +b00000000000000000000000000000100 n +b00000000000000000000000000000011 o +b00000000000000000000000000000100 q +b00000000000000000000000000000101 t +b00000000000000000000000000000001 v +b00000000000000000000000000000001 w +b00000000000000000000000000000100 y b00000000000000000000000000000100 { b00000000000000000000000000000100 } b00000000000000000000000000000011 ~ @@ -627,55 +596,47 @@ b00000000000000000000000000000100 ;! b00000000000000000000000000000100 ?! b00000000000000000000000000000001 A! #45 -0) -0* -b00000000000000000000000000001010 , -b00000000000000000000000000001010 . -b00000000000000000000000000000110 / -b00000000000000000000000000001110 4 -b00000000000000000000000000001011 6 -b00000000000000000000000000001000 8 +01 +b00000000000000000000000000000110 3 +b00000000000000000000000000000110 4 +b00000000000000000000000000001110 : +b00000000000000000000000000001011 < +b00000000000000000000000000001000 > 0 -b00000000000000000000000000000101 ? -b00000000000000000000000000000101 A -b00000000000000000000000000000100 B -b00000000000000000000000000000100 D -b00000000000000000000000000000100 F +11 +b00000000000000000000000000000101 5 +b00000000000000000000000000000101 6 +b00000000000000000000000000010000 : +b00000000000000000000000000001101 < +b00000000000000000000000000001010 > +b00000000000000000000000000000110 C +b00000110 D +b00000000000000000000000000000101 E +b00000000000000000000000000000101 G b00000000000000000000000000000100 H b00000000000000000000000000000100 J b00000000000000000000000000000100 L -b00000000000000000000000000000001 Q -b00000000000000000000000000000101 R -b00000000000000000000000000000001 T -b00000000000000000000000000000101 W -b00000000000000000000000000000100 X -b00000000000000000000000000000100 Z -b00000000000000000000000000000101 [ -b00000000000000000000000000000100 \ +b00000000000000000000000000000100 N +b00000000000000000000000000000100 P +b00000000000000000000000000000100 R +b00000000000000000000000000000001 W +b00000000000000000000000000000101 X +b00000000000000000000000000000001 Z +b00000000000000000000000000000101 ] b00000000000000000000000000000100 ^ -1a -b00000000000000000000000000000101 h -b00000000000000000000000000000101 i -b00000000000000000000000000000100 j -b00000000000000000000000000000101 l -b00000000000000000000000000000110 o -b00000000000000000000000000000101 p -b00000000000000000000000000000101 t -b00000000000000000000000000011000 v -b00000000000000000000000000010010 w -b00000000000000000000000000000110 x -b00000000000000000000000000000110 y +b00000000000000000000000000000100 ` +b00000000000000000000000000000101 a +b00000000000000000000000000000100 b +b00000000000000000000000000000100 d +1g +b00000000000000000000000000000101 m +b00000000000000000000000000000101 n +b00000000000000000000000000000100 o +b00000000000000000000000000000101 q +b00000000000000000000000000000110 t +b00000000000000000000000000000101 u +b00000000000000000000000000000101 y b00000000000000000000000000000101 { b00000000000000000000000000000101 } b00000000000000000000000000000100 ~ @@ -702,57 +663,49 @@ b00000000000000000000000000000110 ?! b00000000000000000000000000000101 @! b00000000000000000000000000000001 B! #55 -0) -0* -b00000000000000000000000000001100 , -b00000000000000000000000000001100 . -b00000000000000000000000000000111 / -b00000000000000000000000000010001 4 -b00000000000000000000000000001110 6 -b00000000000000000000000000001011 8 +01 +b00000000000000000000000000000111 3 +b00000000000000000000000000000111 4 +b00000000000000000000000000010001 : +b00000000000000000000000000001110 < +b00000000000000000000000000001011 > 0 -b00000000000000000000000000000110 ? -b00000000000000000000000000000110 A -b00000000000000000000000000000101 B -b00000000000000000000000000000101 D -b00000000000000000000000000000101 F +11 +b00000000000000000000000000000110 5 +b00000000000000000000000000000110 6 +b00000000000000000000000000010011 : +b00000000000000000000000000010000 < +b00000000000000000000000000001100 > +b00000000000000000000000000000111 ? +b00000000000000000000000000000100 A +b00000000000000000000000000000111 C +b00000111 D +b00000000000000000000000000000110 E +b00000000000000000000000000000110 G b00000000000000000000000000000101 H b00000000000000000000000000000101 J b00000000000000000000000000000101 L -b00000000000000000000000000000011 P -b00000000000000000000000000000110 R -b00000000000000000000000000000100 U -b00000000000000000000000000000110 W -b00000000000000000000000000000101 X -b00000000000000000000000000000101 Z -b00000000000000000000000000000110 [ -b00000000000000000000000000000101 \ +b00000000000000000000000000000101 N +b00000000000000000000000000000101 P +b00000000000000000000000000000101 R +b00000000000000000000000000000011 V +b00000000000000000000000000000110 X +b00000000000000000000000000000100 [ +b00000000000000000000000000000110 ] b00000000000000000000000000000101 ^ -1_ -b00000000000000000000000000000110 h -b00000000000000000000000000000110 i -b00000000000000000000000000000010 k -b00000000000000000000000000000110 l -b00000000000000000000000000000111 o -b00000000000000000000000000000110 p -b00000000000000000000000000000110 t -b00000000000000000000000000011100 v -b00000000000000000000000000010101 w -b00000000000000000000000000000111 x -b00000000000000000000000000000111 y +b00000000000000000000000000000101 ` +b00000000000000000000000000000110 a +b00000000000000000000000000000101 b +b00000000000000000000000000000101 d +1e +b00000000000000000000000000000110 m +b00000000000000000000000000000110 n +b00000000000000000000000000000010 p +b00000000000000000000000000000110 q +b00000000000000000000000000000111 t +b00000000000000000000000000000110 u +b00000000000000000000000000000110 y b00000000000000000000000000000110 { b00000000000000000000000000000110 } b00000000000000000000000000000101 ~ @@ -777,60 +730,52 @@ b00000000000000000000000000000110 ;! b00000000000000000000000000000111 ?! b00000000000000000000000000000110 @! #65 -0) -0* -b00000000000000000000000000001110 , -b00000000000000000000000000001110 . -b00000000000000000000000000001000 / -03 -b00000000000000000000000000010100 4 -b00000000000000000000000000010001 6 -b00000000000000000000000000001000 9 -b00000000000000000000000000000100 : +01 +b00000000000000000000000000001000 3 +b00000000000000000000000000001000 4 +09 +b00000000000000000000000000010100 : +b00000000000000000000000000010001 < +b00000000000000000000000000001000 ? +b00000000000000000000000000000100 @ 0 -b00000000000000000000000000000111 ? -b00000000000000000000000000000111 A -b00000000000000000000000000000110 B -b00000000000000000000000000000110 D -b00000000000000000000000000000110 F +11 +b00000000000000000000000000000111 5 +b00000000000000000000000000000111 6 +19 +b00000000000000000000000000010110 : +b00000000000000000000000000010011 < +b00000000000000000000000000001101 > +b00000000000000000000000000001001 ? +b00000000000000000000000000000101 A +b00000000000000000000000000001000 C +b00001000 D +b00000000000000000000000000000111 E +b00000000000000000000000000000111 G b00000000000000000000000000000110 H b00000000000000000000000000000110 J b00000000000000000000000000000110 L -b00000000000000000000000000000100 P -b00000000000000000000000000000111 R -b00000000000000000000000000000101 U -b00000000000000000000000000000111 W -b00000000000000000000000000000110 X -b00000000000000000000000000000110 Z -b00000000000000000000000000000111 [ -b00000000000000000000000000000110 \ +b00000000000000000000000000000110 N +b00000000000000000000000000000110 P +b00000000000000000000000000000110 R +b00000000000000000000000000000100 V +b00000000000000000000000000000111 X +b00000000000000000000000000000101 [ +b00000000000000000000000000000111 ] b00000000000000000000000000000110 ^ -0_ -b00000000000000000000000000000111 h -b00000000000000000000000000000111 i -b00000000000000000000000000000101 j -b00000000000000000000000000000111 l -b00000000000000000000000000001000 o -b00000000000000000000000000000111 p -b00000000000000000000000000000111 t -b00000000000000000000000000100000 v -b00000000000000000000000000011000 w -b00000000000000000000000000001000 x -b00000000000000000000000000001000 y +b00000000000000000000000000000110 ` +b00000000000000000000000000000111 a +b00000000000000000000000000000110 b +b00000000000000000000000000000110 d +0e +b00000000000000000000000000000111 m +b00000000000000000000000000000111 n +b00000000000000000000000000000101 o +b00000000000000000000000000000111 q +b00000000000000000000000000001000 t +b00000000000000000000000000000111 u +b00000000000000000000000000000111 y b00000000000000000000000000000111 { b00000000000000000000000000000111 } b00000000000000000000000000000110 ~ @@ -855,54 +800,46 @@ b00000000000000000000000000000111 ;! b00000000000000000000000000001000 ?! b00000000000000000000000000000111 @! #75 -0) -0* -b00000000000000000000000000010000 , -b00000000000000000000000000010000 . -b00000000000000000000000000001001 / -b00000000000000000000000000010111 4 -b00000000000000000000000000010100 6 -b00000000000000000000000000001110 8 +01 +b00000000000000000000000000001001 3 +b00000000000000000000000000001001 4 +b00000000000000000000000000010111 : +b00000000000000000000000000010100 < +b00000000000000000000000000001110 > 0 -b00000000000000000000000000001000 ? -b00000000000000000000000000001000 A -b00000000000000000000000000000111 B -b00000000000000000000000000000111 D -b00000000000000000000000000000111 F +11 +b00000000000000000000000000001000 5 +b00000000000000000000000000001000 6 +b00000000000000000000000000011001 : +b00000000000000000000000000010110 < +b00000000000000000000000000010000 > +b00000000000000000000000000001001 C +b00001001 D +b00000000000000000000000000001000 E +b00000000000000000000000000001000 G b00000000000000000000000000000111 H b00000000000000000000000000000111 J b00000000000000000000000000000111 L -b00000000000000000000000000000101 P -b00000000000000000000000000001000 R -b00000000000000000000000000000110 U -b00000000000000000000000000001000 W -b00000000000000000000000000000111 X -b00000000000000000000000000000111 Z -b00000000000000000000000000001000 [ -b00000000000000000000000000000111 \ +b00000000000000000000000000000111 N +b00000000000000000000000000000111 P +b00000000000000000000000000000111 R +b00000000000000000000000000000101 V +b00000000000000000000000000001000 X +b00000000000000000000000000000110 [ +b00000000000000000000000000001000 ] b00000000000000000000000000000111 ^ -b00000000000000000000000000001000 h -b00000000000000000000000000001000 i -b00000000000000000000000000000110 j -b00000000000000000000000000001000 l -b00000000000000000000000000001001 o -b00000000000000000000000000001000 p -b00000000000000000000000000001000 t -b00000000000000000000000000100100 v -b00000000000000000000000000011011 w -b00000000000000000000000000001001 x -b00000000000000000000000000001001 y +b00000000000000000000000000000111 ` +b00000000000000000000000000001000 a +b00000000000000000000000000000111 b +b00000000000000000000000000000111 d +b00000000000000000000000000001000 m +b00000000000000000000000000001000 n +b00000000000000000000000000000110 o +b00000000000000000000000000001000 q +b00000000000000000000000000001001 t +b00000000000000000000000000001000 u +b00000000000000000000000000001000 y b00000000000000000000000000001000 { b00000000000000000000000000001000 } b00000000000000000000000000000111 ~ @@ -926,57 +863,49 @@ b00000000000000000000000000001000 ;! b00000000000000000000000000001001 ?! b00000000000000000000000000001000 @! #85 -0) -0* -b00000000000000000000000000010010 , -b00000000000000000000000000010010 . -b00000000000000000000000000001010 / -b00000000000000000000000000011010 4 -b00000000000000000000000000010111 6 -b00000000000000000000000000010001 8 +01 +b00000000000000000000000000001010 3 +b00000000000000000000000000001010 4 +b00000000000000000000000000011010 : +b00000000000000000000000000010111 < +b00000000000000000000000000010001 > 0 -b00000000000000000000000000001001 ? -b00000000000000000000000000001001 A -b00000000000000000000000000001000 B -b00000000000000000000000000001000 D -b00000000000000000000000000001000 F +11 +b00000000000000000000000000001001 5 +b00000000000000000000000000001001 6 +b00000000000000000000000000011100 : +b00000000000000000000000000011001 < +b00000000000000000000000000010010 > +b00000000000000000000000000001010 ? +b00000000000000000000000000000110 A +b00000000000000000000000000001010 C +b00001010 D +b00000000000000000000000000001001 E +b00000000000000000000000000001001 G b00000000000000000000000000001000 H b00000000000000000000000000001000 J b00000000000000000000000000001000 L -b00000000000000000000000000000110 P -b00000000000000000000000000001001 R -b00000000000000000000000000000111 U -b00000000000000000000000000001001 W -b00000000000000000000000000001000 X -b00000000000000000000000000001000 Z -b00000000000000000000000000001001 [ -b00000000000000000000000000001000 \ +b00000000000000000000000000001000 N +b00000000000000000000000000001000 P +b00000000000000000000000000001000 R +b00000000000000000000000000000110 V +b00000000000000000000000000001001 X +b00000000000000000000000000000111 [ +b00000000000000000000000000001001 ] b00000000000000000000000000001000 ^ -1_ -b00000000000000000000000000001001 h -b00000000000000000000000000001001 i -b00000000000000000000000000000011 k -b00000000000000000000000000001001 l -b00000000000000000000000000001010 o -b00000000000000000000000000001001 p -b00000000000000000000000000001001 t -b00000000000000000000000000101000 v -b00000000000000000000000000011110 w -b00000000000000000000000000001010 x -b00000000000000000000000000001010 y +b00000000000000000000000000001000 ` +b00000000000000000000000000001001 a +b00000000000000000000000000001000 b +b00000000000000000000000000001000 d +1e +b00000000000000000000000000001001 m +b00000000000000000000000000001001 n +b00000000000000000000000000000011 p +b00000000000000000000000000001001 q +b00000000000000000000000000001010 t +b00000000000000000000000000001001 u +b00000000000000000000000000001001 y b00000000000000000000000000001001 { b00000000000000000000000000001001 } b00000000000000000000000000001000 ~ @@ -1000,60 +929,52 @@ b00000000000000000000000000001001 ;! b00000000000000000000000000001010 ?! b00000000000000000000000000001001 @! #95 -0) -0* -b00000000000000000000000000010100 , -b00000000000000000000000000010100 . -b00000000000000000000000000001011 / -03 -b00000000000000000000000000011101 4 -b00000000000000000000000000011010 6 -b00000000000000000000000000001011 9 -b00000000000000000000000000000101 : +01 +b00000000000000000000000000001011 3 +b00000000000000000000000000001011 4 +09 +b00000000000000000000000000011101 : +b00000000000000000000000000011010 < +b00000000000000000000000000001011 ? +b00000000000000000000000000000101 @ 0 -b00000000000000000000000000001010 ? -b00000000000000000000000000001010 A -b00000000000000000000000000001001 B -b00000000000000000000000000001001 D -b00000000000000000000000000001001 F +11 +b00000000000000000000000000001010 5 +b00000000000000000000000000001010 6 +19 +b00000000000000000000000000011111 : +b00000000000000000000000000011100 < +b00000000000000000000000000010011 > +b00000000000000000000000000001100 ? +b00000000000000000000000000000111 A +b00000000000000000000000000001011 C +b00001011 D +b00000000000000000000000000001010 E +b00000000000000000000000000001010 G b00000000000000000000000000001001 H b00000000000000000000000000001001 J b00000000000000000000000000001001 L -b00000000000000000000000000000111 P -b00000000000000000000000000001010 R -b00000000000000000000000000000001 V -b00000000000000000000000000001010 W -b00000000000000000000000000001001 X -b00000000000000000000000000001001 Z -b00000000000000000000000000001010 [ -b00000000000000000000000000001001 \ +b00000000000000000000000000001001 N +b00000000000000000000000000001001 P +b00000000000000000000000000001001 R +b00000000000000000000000000000111 V +b00000000000000000000000000001010 X +b00000000000000000000000000000001 \ +b00000000000000000000000000001010 ] b00000000000000000000000000001001 ^ -0_ -b00000000000000000000000000001010 h -b00000000000000000000000000001010 i -b00000000000000000000000000000111 j -b00000000000000000000000000001010 l -b00000000000000000000000000001011 o -b00000000000000000000000000001010 p -b00000000000000000000000000001010 t -b00000000000000000000000000101100 v -b00000000000000000000000000100001 w -b00000000000000000000000000001011 x -b00000000000000000000000000001011 y +b00000000000000000000000000001001 ` +b00000000000000000000000000001010 a +b00000000000000000000000000001001 b +b00000000000000000000000000001001 d +0e +b00000000000000000000000000001010 m +b00000000000000000000000000001010 n +b00000000000000000000000000000111 o +b00000000000000000000000000001010 q +b00000000000000000000000000001011 t +b00000000000000000000000000001010 u +b00000000000000000000000000001010 y b00000000000000000000000000001010 { b00000000000000000000000000001010 } b00000000000000000000000000001001 ~ diff --git a/test_regress/t/t_cover_line_trace.py b/test_regress/t/t_cover_line_trace.py index 57efc031e..8fec71ba8 100755 --- a/test_regress/t/t_cover_line_trace.py +++ b/test_regress/t/t_cover_line_trace.py @@ -26,6 +26,5 @@ test.run(cmd=[ ], verilator_run=True) -test.files_identical(test.obj_dir + "/annotated/t_cover_line.v", "t/t_cover_line.out") test.vcd_identical(test.trace_filename, test.golden_filename) test.passes() From 192445097ac1e5413c7e1203aa4dc2eb7b1b4a07 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 1 Mar 2026 11:59:29 -0500 Subject: [PATCH 026/340] Internals: Fix non-determinism in V3Delayed, V3SplitVar, V3Task (#7120 partial) (#7165) --- src/CMakeLists.txt | 3 ++- src/V3Container.h | 65 ++++++++++++++++++++++++++++++++++++++++++++++ src/V3Delayed.cpp | 2 +- src/V3Options.cpp | 20 +++++--------- src/V3PchAstMT.h | 1 + src/V3PchAstNoMT.h | 1 + src/V3SplitVar.cpp | 44 ++++++++++++++++++++++++------- src/V3Task.cpp | 13 +++++----- src/V3Task.h | 9 ++++--- 9 files changed, 123 insertions(+), 35 deletions(-) create mode 100644 src/V3Container.h diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 7c0612dee..92bd02219 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -65,8 +65,9 @@ set(HEADERS V3Clock.h V3Combine.h V3Common.h - V3Control.h V3Const.h + V3Container.h + V3Control.h V3Coverage.h V3CoverageJoin.h V3Dead.h diff --git a/src/V3Container.h b/src/V3Container.h new file mode 100644 index 000000000..7644cbea6 --- /dev/null +++ b/src/V3Container.h @@ -0,0 +1,65 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//************************************************************************* +// DESCRIPTION: Verilator: Generic container types +// +// Code available from: https://verilator.org +// +//************************************************************************* +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2003-2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//************************************************************************* + +#ifndef VERILATOR_V3CONTAINER_H_ +#define VERILATOR_V3CONTAINER_H_ + +#include "config_build.h" +#include "verilatedos.h" + +#include +#include +#include + +//============================================================================ + +// Similar to std::set, but ordered based on call order to emplace. Used +// when insertion order is desired (e.g. std::vector), but duplicates need removal. +// Keys may not be modified. (If needed in future, m_set could contain vector positions.) +template +class VInsertionSet final { + std::vector m_keys; // Elements by insertion order + std::unordered_set m_keySet; // Elements by key +public: + // METHODS + bool insert(const T_Key& key) { + // Returns if did insertion (second pair argument of traditional emplace) + const auto itFoundPair = m_keySet.insert(key); + if (itFoundPair.second) m_keys.push_back(key); + return itFoundPair.second; + } + void clear() { + m_keys.clear(); + m_keySet.clear(); + } + + // ACCESSORS + bool empty() const { return m_keys.empty(); } + bool exists(const T_Key& key) const { return m_keySet.find(key) != m_keySet.end(); } + + // ITERATORS + using const_iterator = typename std::vector::const_iterator; + const_iterator begin() const { return m_keys.begin(); } + const_iterator end() const { return m_keys.end(); } +}; + +//============================================================================ +// VInsertionMap: Not currently needed; prototype code exists, just ask. +// Similar to std::map, but ordered based on call order to emplace. Used +// when insertion order is desired (e.g. std::vector), but duplicates need removal. +// Values may be modified. + +#endif // Guard diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index 209218b8e..49aeb4705 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -263,7 +263,7 @@ class DelayedVisitor final : public VNVisitor { AstUser3Allocator> m_writeRefs; // STATE - across all visitors - std::set m_timingDomains; // Timing resume domains + VInsertionSet m_timingDomains; // Timing resume domains // STATE - for current visit position (use VL_RESTORER) AstActive* m_activep = nullptr; // Current activate diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 28c7d75b8..7018bc296 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -18,6 +18,7 @@ #include "V3Options.h" +#include "V3Container.h" #include "V3Error.h" #include "V3File.h" #include "V3Global.h" @@ -70,30 +71,26 @@ public: std::list m_lineArgs; // List of command line argument encountered // List of arguments encounterd, and a bool in needed for rerunning --dump-inputs std::list, bool>> m_allArgs; - std::list m_incDirUsers; // Include directories (ordered) - std::set m_incDirUserSet; // Include directories (for removing duplicates) + VInsertionSet m_incDirUsers; // Include directories (ordered) std::list m_incDirFallbacks; // Include directories (ordered) std::set m_incDirFallbackSet; // Include directories (for removing duplicates) std::map m_langExts; // Language extension map - std::list m_libExtVs; // Library extensions (ordered) - std::set m_libExtVSet; // Library extensions (for removing duplicates) + VInsertionSet m_libExtVs; // Library extensions (ordered) DirMap m_dirMap; // Directory listing // ACCESSOR METHODS void addIncDirUser(const string& incdir) { const string& dir = V3Os::filenameCleanup(incdir); - const auto itFoundPair = m_incDirUserSet.insert(dir); - if (itFoundPair.second) { + const bool inserted = m_incDirUsers.insert(dir); + if (inserted) { // cppcheck-suppress stlFindInsert // cppcheck 1.90 bug - m_incDirUsers.push_back(dir); m_incDirFallbacks.remove(dir); // User has priority over Fallback m_incDirFallbackSet.erase(dir); // User has priority over Fallback } } void addIncDirFallback(const string& incdir) { const string& dir = V3Os::filenameCleanup(incdir); - if (m_incDirUserSet.find(dir) - == m_incDirUserSet.end()) { // User has priority over Fallback + if (!m_incDirUsers.exists(dir)) { // User has priority over Fallback const auto itFoundPair = m_incDirFallbackSet.insert(dir); if (itFoundPair.second) m_incDirFallbacks.push_back(dir); } @@ -106,10 +103,7 @@ public: m_langExts[addext] = lc; } - void addLibExtV(const string& libext) { - const auto itFoundPair = m_libExtVSet.insert(libext); - if (itFoundPair.second) m_libExtVs.push_back(libext); - } + void addLibExtV(const string& libext) { m_libExtVs.insert(libext); } V3OptionsImp() = default; ~V3OptionsImp() = default; }; diff --git a/src/V3PchAstMT.h b/src/V3PchAstMT.h index 34f862088..751afd41d 100644 --- a/src/V3PchAstMT.h +++ b/src/V3PchAstMT.h @@ -26,6 +26,7 @@ #include "V3Ast.h" #include "V3Broken.h" +#include "V3Container.h" #include "V3Error.h" #include "V3FileLine.h" #include "V3FunctionTraits.h" diff --git a/src/V3PchAstNoMT.h b/src/V3PchAstNoMT.h index e778dab5d..d2ddc1d6e 100644 --- a/src/V3PchAstNoMT.h +++ b/src/V3PchAstNoMT.h @@ -28,6 +28,7 @@ #include "V3Ast.h" #include "V3Broken.h" +#include "V3Container.h" #include "V3Error.h" #include "V3FileLine.h" #include "V3FunctionTraits.h" diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp index 62c386293..95bd05954 100644 --- a/src/V3SplitVar.cpp +++ b/src/V3SplitVar.cpp @@ -226,15 +226,37 @@ static void warnNoSplit(const AstVar* varp, const AstNode* wherep, const char* r // Split Unpacked Variables // Replacement policy: // AstArraySel -> Just replace with the AstVarRef for the split variable -// AstVarRef -> Create a temporary variable and refer the variable -// AstSliceSel -> Create a temporary variable and refer the variable +// AstVarRef -> Create a temporary variable and refer to the variable +// AstSliceSel -> Create a temporary variable and refer to the variable -// Compare AstNode* to get deterministic ordering when showing messages. +// Track order-of-encounter for nodes, so we are stable, versus comparing node pointers +// (fileline may be the same across multiple nodes, so is insufficient) +class SplitNodeOrder final { + // NODE STATE + // AstNode::user4() -> uint64_t. Order the node is in the tree + const VNUser4InUse m_user4InUse; + +public: + static uint64_t nextId() { + static uint64_t s_sequence = 0; + return ++s_sequence; + } + static uint64_t nodeOrder(const AstNode* const nodep) { + AstNode* const ncnodep = const_cast(nodep); + const uint64_t id = ncnodep->user4(); + if (VL_LIKELY(id)) return id; + ncnodep->user4(nextId()); + return ncnodep->user4(); + } +}; + +// Compare AstNode* to get deterministic ordering struct AstNodeComparator final { bool operator()(const AstNode* ap, const AstNode* bp) const { + // First consider lines, as makes messages to user more obvious const int lineComp = ap->fileline()->operatorCompare(*bp->fileline()); if (lineComp != 0) return lineComp < 0; - return ap < bp; + return SplitNodeOrder::nodeOrder(ap) < SplitNodeOrder::nodeOrder(bp); } }; @@ -247,6 +269,7 @@ class UnpackRef final { const int m_lsb; // for SliceSel const VAccess m_access; const bool m_ftask; // true if the reference is in function/task. false if in module. + public: UnpackRef(AstNode* stmtp, AstVarRef* nodep, bool ftask) : m_contextp{stmtp} @@ -587,12 +610,12 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl { iterateChildren(nodep); } } - AstVarRef* createTempVar(AstNode* context, AstNode* nodep, AstUnpackArrayDType* dtypep, + AstVarRef* createTempVar(AstNode* contextp, AstNode* nodep, AstUnpackArrayDType* dtypep, const std::string& name_prefix, std::vector& vars, int start_idx, bool lvalue, bool /*ftask*/) { FileLine* const fl = nodep->fileline(); const std::string name = m_tempNames.get(nodep) + "__" + name_prefix; - AstNodeAssign* const assignp = VN_CAST(context, NodeAssign); + AstNodeAssign* const assignp = VN_CAST(contextp, NodeAssign); if (assignp) { // "always_comb a = b;" to "always_comb begin a = b; end" so that local // variable can be added. @@ -604,7 +627,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl { << " is created lsb:" << dtypep->lo() << " msb:" << dtypep->hi()); // Use AstAssign if true, otherwise AstAssignW const bool use_simple_assign - = (context && VN_IS(context, NodeFTaskRef)) || (assignp && VN_IS(assignp, Assign)); + = (contextp && VN_IS(contextp, NodeFTaskRef)) || (assignp && VN_IS(assignp, Assign)); for (int i = 0; i < dtypep->elementsConst(); ++i) { AstNodeExpr* lhsp @@ -618,11 +641,11 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl { AstAssign* const ap = new AstAssign{fl, lhsp, rhsp}; if (lvalue) { // If varp is LHS, this assignment must appear after the original - // assignment(context). - context->addNextHere(ap); + // assignment(contextp). + contextp->addNextHere(ap); } else { // If varp is RHS, this assignment comes just before the original assignment - context->addHereThisAsNext(ap); + contextp->addHereThisAsNext(ap); } UASSERT_OBJ(!m_contextp, m_contextp, "must be null"); setContextAndIterate(ap, refp); @@ -1364,6 +1387,7 @@ const char* SplitVarImpl::cannotSplitPackedVarReason(const AstVar* varp) { void V3SplitVar::splitVariable(AstNetlist* nodep) { UINFO(2, __FUNCTION__ << ":"); + SplitNodeOrder order; SplitVarRefs refs; { const SplitUnpackedVarVisitor visitor{nodep}; diff --git a/src/V3Task.cpp b/src/V3Task.cpp index a3fa624a8..a5da23eeb 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -1856,7 +1856,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp, if (!makeChanges) return tconnects; // Connect missing ones - std::set argWrap; // Which ports are defaulted, forcing arg wrapper creation + VInsertionSet argWrap; // Which ports are defaulted; need arg wrapper creation for (int i = 0; i < tpinnum; ++i) { AstVar* const portp = tconnects[i].first; if (!tconnects[i].second || !tconnects[i].second->exprp()) { @@ -1882,7 +1882,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp, if (statep) { portp->pinNum(i + 1); // Make sure correct, will use to build name UINFO(9, "taskConnects arg wrapper needed " << portp->valuep()); - argWrap.emplace(portp); + argWrap.insert(portp); } else { // statep = nullptr, called too late or otherwise to handle args // Problem otherwise is we might have a varref, task // call, or something else that only makes sense in the @@ -1956,7 +1956,8 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp, } void V3Task::taskConnectWrap(AstNodeFTaskRef* nodep, const V3TaskConnects& tconnects, - V3TaskConnectState* statep, const std::set& argWrap) { + V3TaskConnectState* statep, + const VInsertionSet& argWrap) { statep->setDidWrap(); // Make wrapper name such that is same iff same args are defaulted std::string newname = nodep->name() + "__Vtcwrap"; @@ -1973,7 +1974,7 @@ void V3Task::taskConnectWrap(AstNodeFTaskRef* nodep, const V3TaskConnects& tconn for (const auto& tconnect : tconnects) { const AstVar* const portp = tconnect.first; AstArg* const argp = tconnect.second; - if (argWrap.find(portp) != argWrap.end()) { // Removed arg + if (argWrap.exists(portp)) { // Removed arg statep->pushDeletep(argp->unlinkFrBack()); } } @@ -1985,7 +1986,7 @@ void V3Task::taskConnectWrap(AstNodeFTaskRef* nodep, const V3TaskConnects& tconn AstNodeFTask* V3Task::taskConnectWrapNew(AstNodeFTask* taskp, const string& newname, const V3TaskConnects& tconnects, - const std::set& argWrap) { + const VInsertionSet& argWrap) { std::map oldNewVars; // Old -> new var mappings AstNodeFTask* const newTaskp = taskp->cloneType(newname); @@ -2019,7 +2020,7 @@ AstNodeFTask* V3Task::taskConnectWrapNew(AstNodeFTask* taskp, const string& newn for (const auto& tconnect : tconnects) { AstVar* const portp = tconnect.first; AstVar* newPortp; - if (argWrap.find(portp) == argWrap.end()) { // Not removed arg + if (!argWrap.exists(portp)) { // Not removed arg newPortp = new AstVar{portp->fileline(), portp->varType(), portp->name(), portp}; newPortp->propagateWrapAttrFrom(portp); newPortp->funcLocal(true); diff --git a/src/V3Task.h b/src/V3Task.h index 378e87330..553af1f70 100644 --- a/src/V3Task.h +++ b/src/V3Task.h @@ -21,6 +21,7 @@ #include "verilatedos.h" #include "V3Ast.h" +#include "V3Container.h" #include "V3Error.h" #include @@ -58,10 +59,10 @@ public: bool makeChanges = true) VL_MT_DISABLED; static void taskConnectWrap(AstNodeFTaskRef* nodep, const V3TaskConnects& tconnects, V3TaskConnectState* statep, - const std::set& argWrap) VL_MT_DISABLED; - static AstNodeFTask* taskConnectWrapNew(AstNodeFTask* taskp, const string& newname, - const V3TaskConnects& tconnects, - const std::set& argWrap) VL_MT_DISABLED; + const VInsertionSet& argWrap) VL_MT_DISABLED; + static AstNodeFTask* + taskConnectWrapNew(AstNodeFTask* taskp, const string& newname, const V3TaskConnects& tconnects, + const VInsertionSet& argWrap) VL_MT_DISABLED; static string assignInternalToDpi(AstVar* portp, bool isPtr, const string& frSuffix, const string& toSuffix, const string& frPrefix = "") VL_MT_DISABLED; From 108d209bd7bedc2a6a00f19a2310a9f22c7da61c Mon Sep 17 00:00:00 2001 From: Yilou Wang Date: Sun, 1 Mar 2026 21:16:55 +0100 Subject: [PATCH 027/340] Support soft constraint solving with last-wins priority (#7124) (#7166) --- include/verilated_random.cpp | 33 ++++++++-- include/verilated_random.h | 5 +- src/V3AstAttr.h | 2 + src/V3Randomize.cpp | 6 +- test_regress/t/t_randomize_soft.py | 21 +++++++ test_regress/t/t_randomize_soft.v | 99 ++++++++++++++++++++++++++++++ 6 files changed, 159 insertions(+), 7 deletions(-) create mode 100755 test_regress/t/t_randomize_soft.py create mode 100644 test_regress/t/t_randomize_soft.v diff --git a/include/verilated_random.cpp b/include/verilated_random.cpp index 2a1f3d562..4ed746e86 100644 --- a/include/verilated_random.cpp +++ b/include/verilated_random.cpp @@ -496,6 +496,9 @@ bool VlRandomizer::next(VlRNG& rngr) { std::iostream& os = getSolver(); if (!os) return false; + // Soft constraint relaxation (IEEE 1800-2017 18.5.13, last-wins priority): + // Try hard + soft[0..N-1], then hard + soft[1..N-1], ..., then hard only. + // First SAT phase wins. If hard-only is UNSAT, report via unsat-core. os << "(set-option :produce-models true)\n"; os << "(set-logic QF_ABV)\n"; os << "(define-fun __Vbv ((b Bool)) (_ BitVec 1) (ite b #b1 #b0))\n"; @@ -520,9 +523,20 @@ bool VlRandomizer::next(VlRNG& rngr) { os << "(assert (= " << pair.first << " (_ bv" << pair.second << " " << w << ")))\n"; } - os << "(check-sat)\n"; + const size_t nSoft = m_softConstraints.size(); + bool sat = false; + for (size_t phase = 0; phase <= nSoft && !sat; ++phase) { + const bool hasSoft = (phase < nSoft); + if (hasSoft) { + os << "(push 1)\n"; + for (size_t i = phase; i < nSoft; ++i) + os << "(assert (= #b1 " << m_softConstraints[i] << "))\n"; + } + os << "(check-sat)\n"; + sat = parseSolution(os, /*log=*/phase == nSoft); + if (!sat && hasSoft) os << "(pop 1)\n"; + } - bool sat = parseSolution(os, true); if (!sat) { // If unsat, use named assertions to get unsat-core os << "(reset)\n"; @@ -541,8 +555,11 @@ bool VlRandomizer::next(VlRNG& rngr) { } int j = 0; for (const std::string& constraint : m_constraints) { - os << "(assert (! (= #b1 " << constraint << ") :named cons" << j << "))\n"; - j++; + os << "(assert (! (= #b1 " << constraint << ") :named cons" << j++ << "))\n"; + } + for (const auto& pair : randcPinned) { + const int w = m_vars.at(pair.first)->width(); + os << "(assert (= " << pair.first << " (_ bv" << pair.second << " " << w << ")))\n"; } os << "(check-sat)\n"; sat = parseSolution(os, true); @@ -550,6 +567,7 @@ bool VlRandomizer::next(VlRNG& rngr) { os << "(reset)\n"; return false; } + for (int i = 0; i < _VL_SOLVER_HASH_LEN_TOTAL && sat; ++i) { os << "(assert "; randomConstraint(os, rngr, _VL_SOLVER_HASH_LEN); @@ -723,15 +741,22 @@ void VlRandomizer::hard(std::string&& constraint, const char* filename, uint32_t } } +void VlRandomizer::soft(std::string&& constraint, const char* /*filename*/, uint32_t /*linenum*/, + const char* /*source*/) { + m_softConstraints.emplace_back(std::move(constraint)); +} + void VlRandomizer::clearConstraints() { m_constraints.clear(); m_constraints_line.clear(); m_solveBefore.clear(); + m_softConstraints.clear(); // Keep m_vars for class member randomization } void VlRandomizer::clearAll() { m_constraints.clear(); + m_softConstraints.clear(); m_vars.clear(); m_randcVarNames.clear(); m_randcValueQueues.clear(); diff --git a/include/verilated_random.h b/include/verilated_random.h index 53c09f071..993778b55 100644 --- a/include/verilated_random.h +++ b/include/verilated_random.h @@ -200,9 +200,10 @@ public: // Object holding constraints and variable references. class VlRandomizer VL_NOT_FINAL { // MEMBERS - std::vector m_constraints; // Solver-dependent constraints + std::vector m_constraints; // Solver-dependent hard constraints std::vector m_constraints_line; // fileline content of the constraint for unsat constraints + std::vector m_softConstraints; // Soft constraints std::map> m_vars; // Solver-dependent // variables ArrayInfoMap m_arr_vars; // Tracks each element in array structures for iteration @@ -593,6 +594,8 @@ public: void hard(std::string&& constraint, const char* filename = "", uint32_t linenum = 0, const char* source = ""); + void soft(std::string&& constraint, const char* filename = "", uint32_t linenum = 0, + const char* source = ""); void clearConstraints(); void clearAll(); // Clear both constraints and variables void markRandc(const char* name); // Mark variable as randc for cyclic tracking diff --git a/src/V3AstAttr.h b/src/V3AstAttr.h index e879adfed..bfe9ba1fb 100644 --- a/src/V3AstAttr.h +++ b/src/V3AstAttr.h @@ -815,6 +815,7 @@ public: RANDOMIZER_CLEARCONSTRAINTS, RANDOMIZER_CLEARALL, RANDOMIZER_HARD, + RANDOMIZER_SOFT, RANDOMIZER_UNIQUE, RANDOMIZER_MARK_RANDC, RANDOMIZER_SOLVE_BEFORE, @@ -951,6 +952,7 @@ inline std::ostream& operator<<(std::ostream& os, const VCMethod& rhs) { {RANDOMIZER_CLEARCONSTRAINTS, "clearConstraints", false}, \ {RANDOMIZER_CLEARALL, "clearAll", false}, \ {RANDOMIZER_HARD, "hard", false}, \ + {RANDOMIZER_SOFT, "soft", false}, \ {RANDOMIZER_UNIQUE, "rand_unique", false}, \ {RANDOMIZER_MARK_RANDC, "markRandc", false}, \ {RANDOMIZER_SOLVE_BEFORE, "solveBefore", false}, \ diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index b80679b27..f03093ca5 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -1906,12 +1906,14 @@ class ConstraintExprVisitor final : public VNVisitor { VL_DO_DANGLING(nodep->deleteTree(), nodep); return; } - // Only hard constraints are currently supported + // Emit as soft or hard constraint per IEEE 1800-2017 18.5.13 + const VCMethod method + = nodep->isSoft() ? VCMethod::RANDOMIZER_SOFT : VCMethod::RANDOMIZER_HARD; AstCMethodHard* const callp = new AstCMethodHard{ nodep->fileline(), new AstVarRef{nodep->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp, VAccess::READWRITE}, - VCMethod::RANDOMIZER_HARD, nodep->exprp()->unlinkFrBack()}; + method, nodep->exprp()->unlinkFrBack()}; callp->dtypeSetVoid(); // Pass filename, lineno, and source as separate arguments // This allows EmitC to call protect() on filename, similar to VL_STOP diff --git a/test_regress/t/t_randomize_soft.py b/test_regress/t/t_randomize_soft.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_soft.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_soft.v b/test_regress/t/t_randomize_soft.v new file mode 100644 index 000000000..2fe4cfa1c --- /dev/null +++ b/test_regress/t/t_randomize_soft.v @@ -0,0 +1,99 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test soft constraint solving per IEEE 1800-2017 section 18.5.13 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); +// verilog_format: on + +// Case 1: Only soft, no hard -- soft should be satisfied +class Case1; + rand int x; + constraint c_soft { soft x == 5; } +endclass + +// Case 2: Two soft on same var -- last-wins (c_b declared after c_a) +class Case2; + rand int x; + constraint c_a { soft x == 5; } + constraint c_b { soft x == 10; } +endclass + +// Case 3: Soft on different vars -- both should be satisfied +class Case3; + rand int x; + rand int y; + constraint c_x { soft x == 7; } + constraint c_y { soft y == 3; } +endclass + +// Case 4: Soft range partially covered by hard -- SAT at intersection +class Case4; + rand int x; + constraint c_soft { soft x inside {[1:10]}; } + constraint c_hard { x inside {[5:15]}; } +endclass + +// Case 5: Soft completely overridden by hard -- hard wins +class Case5; + rand int x; + constraint c_soft { soft x == 5; } + constraint c_hard { x > 10; } +endclass + +module t; + Case1 c1; + Case2 c2; + Case3 c3; + Case4 c4; + Case5 c5; + int rand_ok; + + initial begin + c1 = new; + c2 = new; + c3 = new; + c4 = new; + c5 = new; + + repeat (20) begin + // Case 1: only soft, no hard -- soft satisfied + rand_ok = c1.randomize(); + `checkd(rand_ok, 1) + `checkd(c1.x, 5) + + // Case 2: two soft on same var -- last-wins + rand_ok = c2.randomize(); + `checkd(rand_ok, 1) + `checkd(c2.x, 10) + + // Case 3: soft on different vars -- both satisfied + rand_ok = c3.randomize(); + `checkd(rand_ok, 1) + `checkd(c3.x, 7) + `checkd(c3.y, 3) + + // Case 4: soft range partially covered by hard -- intersection [5:10] + rand_ok = c4.randomize(); + `checkd(rand_ok, 1) + `check_range(c4.x, 5, 10) + + // Case 5: soft completely overridden by hard -- hard wins + rand_ok = c5.randomize(); + `checkd(rand_ok, 1) + if (c5.x <= 10) begin + $write("%%Error: %s:%0d: x=%0d should be > 10\n", `__FILE__, `__LINE__, c5.x); + `stop; + end + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule From 8a413b3ec7983e16c6f0598ecd40db8ee58e3f9d Mon Sep 17 00:00:00 2001 From: Yilou Wang Date: Mon, 2 Mar 2026 11:59:00 +0100 Subject: [PATCH 028/340] Fix std::randomize() in static function with static class members (#7167) (#7169) --- src/V3Randomize.cpp | 22 +++++++-- test_regress/t/t_randomize_std_static.py | 21 +++++++++ test_regress/t/t_randomize_std_static.v | 60 ++++++++++++++++++++++++ 3 files changed, 100 insertions(+), 3 deletions(-) create mode 100755 test_regress/t/t_randomize_std_static.py create mode 100644 test_regress/t/t_randomize_std_static.v diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index f03093ca5..4e5e25eff 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -2180,6 +2180,7 @@ class CaptureVisitor final : public VNVisitor { std::map m_varCloneMap; // Map original var nodes to their clones std::set m_ignore; // Nodes to ignore for capturing AstVar* m_thisp = nullptr; // Variable for outer context's object, if necessary + bool m_staticContext = false; // True when capturing from a static function context // METHODS @@ -2252,6 +2253,11 @@ class CaptureVisitor final : public VNVisitor { if (varIsParam) return CaptureMode::CAP_VALUE; // Static var in function (will not be inlined, because it's in class) if (callerIsClass && varIsFuncLocal) return CaptureMode::CAP_VALUE; + // Static class members in static context don't need 'this' capture; + // V3Class will move both the function and the member to __Vclpkg + if (m_staticContext && callerIsClass && varIsFieldOfCaller + && varRefp->varp()->lifetime().isStatic()) + return CaptureMode::CAP_NO; if (callerIsClass && varIsFieldOfCaller) return CaptureMode::CAP_THIS; UASSERT_OBJ(!callerIsClass, varRefp, "Invalid reference?"); return CaptureMode::CAP_VALUE; @@ -2372,10 +2378,12 @@ class CaptureVisitor final : public VNVisitor { void visit(AstNode* nodep) override { iterateChildren(nodep); } public: - explicit CaptureVisitor(AstNode* const nodep, AstNodeModule* callerp, AstClass* const targetp) + explicit CaptureVisitor(AstNode* const nodep, AstNodeModule* callerp, AstClass* const targetp, + bool staticContext = false) : m_argsp{nullptr} , m_callerp{callerp} - , m_targetp{targetp} { + , m_targetp{targetp} + , m_staticContext{staticContext} { iterateAndNextNull(nodep); } @@ -3771,9 +3779,16 @@ class RandomizeVisitor final : public VNVisitor { if (nodep->classOrPackagep() && nodep->classOrPackagep()->name() == "std") { // Handle std::randomize; create wrapper function that calls basicStdRandomization on // each varref argument, then transform nodep to call that wrapper + const bool inStaticContext = m_ftaskp && m_ftaskp->isStatic(); AstVar* const stdrand = createStdRandomGenerator(m_modp); AstFunc* const randomizeFuncp = V3Randomize::newRandomizeStdFunc( m_memberMap, m_modp, m_inlineUniqueStdName.get(nodep)); + // When called from a static function, mark helper and stdrand as static + // so V3Class moves them to __Vclpkg alongside the calling function + if (inStaticContext) { + stdrand->lifetime(VLifetime::STATIC_EXPLICIT); + randomizeFuncp->isStatic(true); + } randomizeFuncp->addStmtsp( new AstAssign{nodep->fileline(), new AstVarRef{nodep->fileline(), VN_AS(randomizeFuncp->fvarp(), Var), @@ -3829,7 +3844,8 @@ class RandomizeVisitor final : public VNVisitor { } if (withp) { FileLine* const fl = nodep->fileline(); - withCapturep = std::make_unique(withp->exprp(), m_modp, nullptr); + withCapturep = std::make_unique(withp->exprp(), m_modp, nullptr, + inStaticContext); withCapturep->addFunctionArguments(randomizeFuncp); // Clear old constraints and variables for std::randomize with clause if (stdrand) { diff --git a/test_regress/t/t_randomize_std_static.py b/test_regress/t/t_randomize_std_static.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_randomize_std_static.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_randomize_std_static.v b/test_regress/t/t_randomize_std_static.v new file mode 100644 index 000000000..7d56ac592 --- /dev/null +++ b/test_regress/t/t_randomize_std_static.v @@ -0,0 +1,60 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test std::randomize() called from a static function referencing static +// class members in the 'with' clause. + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t; + + typedef enum bit [3:0] { + INSTR_ADD = 0, + INSTR_SUB = 1, + INSTR_MUL = 2, + INSTR_AND = 4 + } instr_name_t; + + class instr_base; + static instr_name_t allowed_instrs[$]; + + static function void init(); + allowed_instrs.push_back(INSTR_ADD); + allowed_instrs.push_back(INSTR_SUB); + allowed_instrs.push_back(INSTR_MUL); + allowed_instrs.push_back(INSTR_AND); + endfunction + + static function instr_name_t get_rand_instr(); + instr_name_t name; + int ok; + ok = std::randomize(name) with { + name inside {allowed_instrs}; + }; + `checkd(ok, 1); + return name; + endfunction + endclass + + initial begin + instr_name_t result; + + instr_base::init(); + + repeat (20) begin + result = instr_base::get_rand_instr(); + `checkd(result == INSTR_ADD || result == INSTR_SUB + || result == INSTR_MUL || result == INSTR_AND, 1); + end + + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule From a3870c5e5e00640ace3f6c5c9b5e5262fabadccb Mon Sep 17 00:00:00 2001 From: "dependabot[bot]" <49699333+dependabot[bot]@users.noreply.github.com> Date: Mon, 2 Mar 2026 10:52:53 -0500 Subject: [PATCH 029/340] CI: depandabot: Bump actions with 2 updates (#7172) --- .github/workflows/build-test.yml | 2 +- .github/workflows/coverage.yml | 10 +++++----- .github/workflows/reusable-build.yml | 2 +- .github/workflows/reusable-rtlmeter-build.yml | 2 +- .github/workflows/reusable-rtlmeter-run.yml | 4 ++-- .github/workflows/reusable-test.yml | 4 ++-- .github/workflows/rtlmeter-pr-results.yml | 4 ++-- .github/workflows/rtlmeter.yml | 16 ++++++++-------- 8 files changed, 22 insertions(+), 22 deletions(-) diff --git a/.github/workflows/build-test.yml b/.github/workflows/build-test.yml index 1d61ec338..f2ad62009 100644 --- a/.github/workflows/build-test.yml +++ b/.github/workflows/build-test.yml @@ -155,7 +155,7 @@ jobs: - name: Zip up repository run: Compress-Archive -LiteralPath install -DestinationPath verilator.zip - name: Upload zip archive - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: ${{ github.workspace }}/repo/verilator.zip name: verilator-win.zip diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index 148c7980c..55c7d0450 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -77,7 +77,7 @@ jobs: uses: actions/checkout@v6 - name: Download code coverage data - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: pattern: code-coverage-* path: obj_coverage @@ -114,7 +114,7 @@ jobs: sudo apt install lcov - name: Download repository archive - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: name: ${{ needs.build.outputs.archive }} path: ${{ github.workspace }} @@ -125,7 +125,7 @@ jobs: ls -lsha - name: Download code coverage data - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: pattern: code-coverage-* path: repo/obj_coverage @@ -170,14 +170,14 @@ jobs: fi - name: Upload report - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: repo/obj_coverage name: coverage-report - name: Upload notification if: ${{ github.event_name == 'pull_request' }} - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: repo/notification name: coverage-pr-notification diff --git a/.github/workflows/reusable-build.yml b/.github/workflows/reusable-build.yml index 2818c1455..7138a7cce 100644 --- a/.github/workflows/reusable-build.yml +++ b/.github/workflows/reusable-build.yml @@ -93,7 +93,7 @@ jobs: echo "archive=$ARCHIVE" >> "$GITHUB_OUTPUT" - name: Upload repository archive - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: ${{ github.workspace }}/${{ steps.create-archive.outputs.archive }} name: ${{ steps.create-archive.outputs.archive }} diff --git a/.github/workflows/reusable-rtlmeter-build.yml b/.github/workflows/reusable-rtlmeter-build.yml index 068729a0d..345abbee7 100644 --- a/.github/workflows/reusable-rtlmeter-build.yml +++ b/.github/workflows/reusable-rtlmeter-build.yml @@ -70,7 +70,7 @@ jobs: run: tar --posix -c -z -f verilator-rtlmeter.tar.gz install - name: Upload Verilator installation archive - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: verilator-rtlmeter.tar.gz name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }} diff --git a/.github/workflows/reusable-rtlmeter-run.yml b/.github/workflows/reusable-rtlmeter-run.yml index 95525125f..c2746209c 100644 --- a/.github/workflows/reusable-rtlmeter-run.yml +++ b/.github/workflows/reusable-rtlmeter-run.yml @@ -64,7 +64,7 @@ jobs: sudo apt install ccache mold libfl-dev libgoogle-perftools-dev libsystemc-dev - name: Download Verilator installation archive - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: name: verilator-rtlmeter-${{ inputs.runs-on }}-${{ inputs.cc }} @@ -117,7 +117,7 @@ jobs: ./rtlmeter report --steps '*' --metrics '*' ../results-${{ steps.results.outputs.hash }}.json - name: Upload results - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: results-${{ steps.results.outputs.hash }}.json name: rtlmeter-${{ inputs.tag }}-results-${{ steps.results.outputs.hash }} diff --git a/.github/workflows/reusable-test.yml b/.github/workflows/reusable-test.yml index d2fb687c3..7e20f292c 100644 --- a/.github/workflows/reusable-test.yml +++ b/.github/workflows/reusable-test.yml @@ -55,7 +55,7 @@ jobs: steps: - name: Download repository archive - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: name: ${{ inputs.archive }} path: ${{ github.workspace }} @@ -99,7 +99,7 @@ jobs: - name: Upload code coverage data if: ${{ inputs.dev-gcov }} - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: ${{ github.workspace }}/repo/obj_coverage/verilator-${{ inputs.suite }}.info name: code-coverage-${{ inputs.suite }} diff --git a/.github/workflows/rtlmeter-pr-results.yml b/.github/workflows/rtlmeter-pr-results.yml index 5ce1b0fdc..745267cab 100644 --- a/.github/workflows/rtlmeter-pr-results.yml +++ b/.github/workflows/rtlmeter-pr-results.yml @@ -20,13 +20,13 @@ jobs: pull-requests: write steps: - name: Download report - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: name: rtlmeter-pr-results run-id: ${{ github.event.workflow_run.id }} github-token: ${{ secrets.GITHUB_TOKEN }} - name: Download PR number - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: name: pr-number run-id: ${{ github.event.workflow_run.id }} diff --git a/.github/workflows/rtlmeter.yml b/.github/workflows/rtlmeter.yml index 3dee9f230..a5f43ef26 100644 --- a/.github/workflows/rtlmeter.yml +++ b/.github/workflows/rtlmeter.yml @@ -198,7 +198,7 @@ jobs: working-directory: rtlmeter run: make venv - name: Download all results - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: pattern: rtlmeter-${{ matrix.tag }}-results-* path: all-results-${{ matrix.tag }} @@ -208,7 +208,7 @@ jobs: run: | ./rtlmeter collate ../all-results-${{ matrix.tag }}/*.json > ../all-results-${{ matrix.tag }}.json - name: Upload combined results - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: all-results-${{ matrix.tag }}.json name: all-results-${{ matrix.tag }} @@ -227,13 +227,13 @@ jobs: runs-on: ubuntu-24.04 steps: - name: Download combined results - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: pattern: all-results-* path: results merge-multiple: true - name: Upload published results - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: results/*.json name: published-results @@ -289,7 +289,7 @@ jobs: working-directory: rtlmeter run: make venv - name: Download combined results - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: pattern: all-results-* path: all-results @@ -308,7 +308,7 @@ jobs: DATE=$(gh run --repo ${{ github.repository }} view $ID --json createdAt --jq ".createdAt") echo "date=$DATE" >> $GITHUB_OUTPUT - name: Download scheduled run results - uses: actions/download-artifact@v7 + uses: actions/download-artifact@v8 with: name: published-results path: nightly-results @@ -374,14 +374,14 @@ jobs: done cat report.txt - name: Upload report - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: report.txt name: rtlmeter-pr-results - name: Save PR number run: echo ${{ github.event.number }} > pr-number.txt - name: Upload PR number - uses: actions/upload-artifact@v6 + uses: actions/upload-artifact@v7 with: path: pr-number.txt name: pr-number From 251d1835cf33bea53fd158cced56639141de782b Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 1 Mar 2026 10:36:53 -0500 Subject: [PATCH 030/340] Internals: Comment to explain stray emit semicolon --- src/V3EmitCFunc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/V3EmitCFunc.h b/src/V3EmitCFunc.h index 1ee0d3aa5..df70952c9 100644 --- a/src/V3EmitCFunc.h +++ b/src/V3EmitCFunc.h @@ -734,8 +734,8 @@ public: puts(";\n"); } void visit(AstCNew* nodep) override { - if (VN_IS(nodep->dtypep(), VoidDType)) { - // super.new case + if (VN_IS(nodep->dtypep(), VoidDType)) { // super.new case + putsDecoration(nodep, "/*super.new*/"); return; } // assignment case; From d406efdcf966218bbce0bc4834e6fde306f4cf53 Mon Sep 17 00:00:00 2001 From: jalcim Date: Mon, 2 Mar 2026 15:15:34 -0500 Subject: [PATCH 031/340] Fix recursive constant function in $unit scope (#7174) (#7178) --- docs/CONTRIBUTORS | 1 + src/V3Scope.cpp | 1 + test_regress/t/t_func_unit_recursive.py | 18 ++++++++++++ test_regress/t/t_func_unit_recursive.v | 38 +++++++++++++++++++++++++ 4 files changed, 58 insertions(+) create mode 100755 test_regress/t/t_func_unit_recursive.py create mode 100644 test_regress/t/t_func_unit_recursive.v diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 5ac1958e1..de64a9a88 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -99,6 +99,7 @@ Ivan Vnučec Iztok Jeras Jake Merdich Jakub Wasilewski +jalcim James Bailey James Hanlon James Hutchinson diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp index b10ac4999..29c3cc534 100644 --- a/src/V3Scope.cpp +++ b/src/V3Scope.cpp @@ -259,6 +259,7 @@ class ScopeVisitor final : public VNVisitor { clonep = nodep->cloneTree(false); } nodep->user2p(clonep); + clonep->user2p(clonep); // For recursive self-references after cloneTree m_scopep->addBlocksp(clonep); // We iterate under the *clone* iterateChildren(clonep); diff --git a/test_regress/t/t_func_unit_recursive.py b/test_regress/t/t_func_unit_recursive.py new file mode 100755 index 000000000..8a938befd --- /dev/null +++ b/test_regress/t/t_func_unit_recursive.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_func_unit_recursive.v b/test_regress/t/t_func_unit_recursive.v new file mode 100644 index 000000000..40096c953 --- /dev/null +++ b/test_regress/t/t_func_unit_recursive.v @@ -0,0 +1,38 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 jalcim +// SPDX-License-Identifier: CC0-1.0 + +// Recursive constant function defined at file scope ($unit). +// Without the V3Scope.cpp fix, this triggers: +// %Error: Internal Error: V3Scope.cpp: No clone for package function + +function automatic integer gate_depth; + input integer way; + integer d1, d2, sc, n1, n2; + begin + if (way <= 1) gate_depth = 0; + else if (way <= 4) gate_depth = 1; + else begin + sc = $clog2(way); + n1 = 1 << (sc - 1); + n2 = way - n1; + d1 = gate_depth(n1); + d2 = gate_depth(n2); + gate_depth = ((d1 > d2) ? d1 : d2) + 1; + end + end +endfunction + +module t; + localparam D5 = gate_depth(5); + localparam D8 = gate_depth(8); + + initial begin + if (D5 !== 2) $stop; + if (D8 !== 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule From 1f2f4d9bbac6ec7a8e0ea067aaa6f322e8226440 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 2 Mar 2026 17:47:54 -0500 Subject: [PATCH 032/340] Commentary: Changes update --- Changes | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index ca7f1bc7a..0b16e32a8 100644 --- a/Changes +++ b/Changes @@ -13,17 +13,22 @@ Verilator 5.047 devel **Other:** +* Support soft constraint solving (#7124) (#7166). [Yilou Wang] * Add VPI callback support to --main (#7145). -* Add V3LiftExpr pass to lower impure expressions and calls (#7141). [Geza Lore, Testorrent USA, Inc.] +* Add V3LiftExpr pass to lower impure expressions and calls (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.] * Improve assignment-compatibility type check (#2843) (#5666) (#7052). [Pawel Kojma, Antmicro Ltd.] * Optimize size of trace declaration object code (#7150). [Szymon Gizler, Antmicro Ltd.] * Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.] +* Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.] * Fix lambda coroutines (#6106) (#7135). [Nick Brereton] * Fix errant integer promotion (#7012). [Todd Strader] +* Fix scheduling non-determinism (#7120) (#7162) (#7165). [Geza Lore, Testorrent USA, Inc.] * Fix parameters inside std::randomize `with` clause (#7140). [Kamil Danecki, Antmicro Ltd.] * Fix forcing unpacked variables (#7149). [Ryszard Rozak, Antmicro Ltd.] * Fix wide conditional short circuiting (#7155). * Fix eliminating assignments to DPI-read variables (#7158). [Geza Lore, Testorrent USA, Inc.] +* Fix std::randomize() in static function with static class members (#7167) (#7169). [Yilou Wang] +* Fix recursive constant function in $unit scope (#7173) (#7174). Verilator 5.046 2026-02-28 From ee68d1c70c323355dca9c96a803b53c3e1d779bb Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 2 Mar 2026 17:48:32 -0500 Subject: [PATCH 033/340] CI: Disallow pulls to stable --- .github/workflows/no-pulls.yml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 .github/workflows/no-pulls.yml diff --git a/.github/workflows/no-pulls.yml b/.github/workflows/no-pulls.yml new file mode 100644 index 000000000..b86779b26 --- /dev/null +++ b/.github/workflows/no-pulls.yml @@ -0,0 +1,15 @@ +--- +# Block PRs against stable branch +name: "Check PR not against 'stable'" +on: + pull_request: + branches: [stable] + +jobs: + block-pr: + runs-on: ubuntu-latest + steps: + - name: Fail and block PR + run: |- + echo "Error: Pull requests directly to 'stable' are not allowed. Please PR against 'master'." + exit 1 From ed84f3adb2f0c190620ec4c659de79d78459d344 Mon Sep 17 00:00:00 2001 From: Yilou Wang Date: Tue, 3 Mar 2026 12:27:31 +0100 Subject: [PATCH 034/340] Support constraints on fixed-size array of class object members (#7170) (#7183) --- src/V3Randomize.cpp | 107 ++++++++++++++---- test_regress/t/t_constraint_cls_arr_member.py | 21 ++++ test_regress/t/t_constraint_cls_arr_member.v | 104 +++++++++++++++++ .../t/t_constraint_global_arr_unsup.out | 22 ++-- .../t/t_constraint_global_arr_unsup.v | 6 + 5 files changed, 224 insertions(+), 36 deletions(-) create mode 100755 test_regress/t/t_constraint_cls_arr_member.py create mode 100644 test_regress/t/t_constraint_cls_arr_member.v diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 4e5e25eff..57c257796 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -1021,8 +1021,8 @@ class ConstraintExprVisitor final : public VNVisitor { // For global constraints, delete nodep after processing if (isGlobalConstrained && !nodep->backp()) VL_DO_DANGLING(pushDeletep(nodep), nodep); - // Detect if variable is an array of class references bool isClassRefArray = false; + bool isUnpackedClassRefArray = false; AstClassRefDType* elemClassRefDtp = nullptr; { AstNodeDType* varDtp = varp->dtypep()->skipRefp(); @@ -1030,12 +1030,14 @@ class ConstraintExprVisitor final : public VNVisitor { || VN_IS(varDtp, UnpackArrayDType) || VN_IS(varDtp, AssocArrayDType)) { AstNodeDType* const elemDtp = varDtp->subDTypep()->skipRefp(); elemClassRefDtp = VN_CAST(elemDtp, ClassRefDType); - if (elemClassRefDtp) isClassRefArray = true; + if (elemClassRefDtp) { + isClassRefArray = true; + isUnpackedClassRefArray = VN_IS(varDtp, UnpackArrayDType); + } } } if (isClassRefArray && !membersel) { - // Per-member registration loop for class ref arrays FileLine* const fl = varp->fileline(); AstClass* const elemClassp = elemClassRefDtp->classp(); AstNodeModule* const varClassp = VN_AS(varp->user2p(), NodeModule); @@ -1049,22 +1051,36 @@ class ConstraintExprVisitor final : public VNVisitor { stmtsp->addNext(new AstAssign{fl, new AstVarRef{fl, iterVarp, VAccess::WRITE}, new AstConst{fl, 0}}); - AstVarRef* const arraySizeRef = new AstVarRef{fl, varClassp, varp, VAccess::READ}; - arraySizeRef->classOrPackagep(classOrPackagep); - AstCMethodHard* const sizep - = new AstCMethodHard{fl, arraySizeRef, VCMethod::DYN_SIZE, nullptr}; - sizep->dtypeSetUInt32(); + AstNodeExpr* sizep; + if (isUnpackedClassRefArray) { + const int arraySize + = VN_AS(varp->dtypep()->skipRefp(), UnpackArrayDType)->elementsConst(); + sizep = new AstConst{fl, static_cast(arraySize)}; + } else { + AstVarRef* const arraySizeRef + = new AstVarRef{fl, varClassp, varp, VAccess::READ}; + arraySizeRef->classOrPackagep(classOrPackagep); + AstCMethodHard* const dynSizep + = new AstCMethodHard{fl, arraySizeRef, VCMethod::DYN_SIZE, nullptr}; + dynSizep->dtypeSetUInt32(); + sizep = dynSizep; + } AstLoop* const loopp = new AstLoop{fl}; stmtsp->addNext(loopp); loopp->addStmtsp(new AstLoopTest{ fl, loopp, new AstLt{fl, new AstVarRef{fl, iterVarp, VAccess::READ}, sizep}}); - AstVarRef* const arrayAtRef = new AstVarRef{fl, varClassp, varp, VAccess::READ}; - arrayAtRef->classOrPackagep(classOrPackagep); - AstCMethodHard* const atReadp - = new AstCMethodHard{fl, arrayAtRef, VCMethod::ARRAY_AT, - new AstVarRef{fl, iterVarp, VAccess::READ}}; + AstVarRef* const arrayReadRef = new AstVarRef{fl, varClassp, varp, VAccess::READ}; + arrayReadRef->classOrPackagep(classOrPackagep); + AstNodeExpr* atReadp; + if (isUnpackedClassRefArray) { + atReadp = new AstArraySel{fl, arrayReadRef, + new AstVarRef{fl, iterVarp, VAccess::READ}}; + } else { + atReadp = new AstCMethodHard{fl, arrayReadRef, VCMethod::ARRAY_AT, + new AstVarRef{fl, iterVarp, VAccess::READ}}; + } atReadp->dtypep(elemClassRefDtp); AstIf* const ifNonNullp = new AstIf{ fl, new AstNeq{fl, atReadp, new AstConst{fl, AstConst::Null{}}}, nullptr}; @@ -1090,9 +1106,14 @@ class ConstraintExprVisitor final : public VNVisitor { const int memberWidth = memberDtp->width(); AstCStmt* const fmtp = new AstCStmt{fl}; - fmtp->add("VL_SNPRINTF(__Vn, sizeof(__Vn), \"" + smtName + ".%0" - + std::to_string(fmtWidth) + "x." + memberVarp->name() - + "\", (unsigned)"); + if (isUnpackedClassRefArray) { + fmtp->add("VL_SNPRINTF(__Vn, sizeof(__Vn), \"" + smtName + ".%x." + + memberVarp->name() + "\", (unsigned)"); + } else { + fmtp->add("VL_SNPRINTF(__Vn, sizeof(__Vn), \"" + smtName + ".%0" + + std::to_string(fmtWidth) + "x." + memberVarp->name() + + "\", (unsigned)"); + } fmtp->add(new AstVarRef{fl, iterVarp, VAccess::READ}); fmtp->add(");\n"); ifNonNullp->addThensp(fmtp); @@ -1100,9 +1121,15 @@ class ConstraintExprVisitor final : public VNVisitor { AstVarRef* const arrayWrRef = new AstVarRef{fl, varClassp, varp, VAccess::WRITE}; arrayWrRef->classOrPackagep(classOrPackagep); - AstCMethodHard* const atWritep - = new AstCMethodHard{fl, arrayWrRef, VCMethod::ARRAY_AT_WRITE, - new AstVarRef{fl, iterVarp, VAccess::READ}}; + AstNodeExpr* atWritep; + if (isUnpackedClassRefArray) { + atWritep = new AstArraySel{fl, arrayWrRef, + new AstVarRef{fl, iterVarp, VAccess::READ}}; + } else { + atWritep + = new AstCMethodHard{fl, arrayWrRef, VCMethod::ARRAY_AT_WRITE, + new AstVarRef{fl, iterVarp, VAccess::READ}}; + } atWritep->dtypep(elemClassRefDtp); AstMemberSel* const memberSelp = new AstMemberSel{fl, atWritep, memberVarp}; @@ -1635,10 +1662,46 @@ class ConstraintExprVisitor final : public VNVisitor { AstNode* rootNode = nodep->fromp(); while (const AstMemberSel* const selp = VN_CAST(rootNode, MemberSel)) rootNode = selp->fromp(); - // Detect array/assoc array access in global constraints - if (VN_IS(rootNode, ArraySel) || VN_IS(rootNode, AssocSel)) { + if (AstArraySel* const arraySelp = VN_CAST(rootNode, ArraySel)) { + AstNodeDType* const arrayDtp = arraySelp->fromp()->dtypep()->skipRefp(); + AstNodeDType* const elemDtp + = arrayDtp->subDTypep() ? arrayDtp->subDTypep()->skipRefp() : nullptr; + if (elemDtp && VN_IS(elemDtp, ClassRefDType)) { + // Nested class ref arrays not yet supported + const bool isSimple + = nodep->fromp() == rootNode && VN_IS(arraySelp->fromp(), VarRef); + if (!isSimple) { + nodep->v3warn( + E_UNSUPPORTED, + "Unsupported: Nested array element access in global constraint"); + return; + } + VL_RESTORER(m_structSel); + m_structSel = true; + nodep->user1(true); + arraySelp->user1(true); + iterateChildren(nodep); + FileLine* const fl = nodep->fileline(); + AstSFormatF* newp = nullptr; + if (AstSFormatF* const fromp = VN_CAST(nodep->fromp(), SFormatF)) { + if (fromp->name() == "%@.%@") { + newp = new AstSFormatF{fl, "%@.%@." + nodep->name(), false, + fromp->exprsp()->cloneTreePure(true)}; + } else { + newp = new AstSFormatF{fl, fromp->name() + "." + nodep->name(), false, + nullptr}; + } + } else { + newp = new AstSFormatF{fl, nodep->name(), false, nullptr}; + } + nodep->replaceWith(newp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + return; + } + } + if (VN_IS(rootNode, AssocSel) || VN_IS(rootNode, ArraySel)) { nodep->v3warn(E_UNSUPPORTED, - "Unsupported: Array element access in global constraint "); + "Unsupported: Array element access in global constraint"); } // Check if the root variable participates in global constraints if (const AstVarRef* const varRefp = VN_CAST(rootNode, VarRef)) { diff --git a/test_regress/t/t_constraint_cls_arr_member.py b/test_regress/t/t_constraint_cls_arr_member.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_cls_arr_member.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_cls_arr_member.v b/test_regress/t/t_constraint_cls_arr_member.v new file mode 100644 index 000000000..87fac6d50 --- /dev/null +++ b/test_regress/t/t_constraint_cls_arr_member.v @@ -0,0 +1,104 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// Test: constraints on class object array element members (fixed-size arrays) + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=[%0d:%0d]\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); +// verilog_format: on + +/* verilator lint_off WIDTHTRUNC */ +/* verilator lint_off IMPLICITSTATIC */ + +class item_t; + rand bit [7:0] value; +endclass + +// Scenario A: foreach with range constraint +class container_a; + rand item_t items[4]; + constraint val_c { + foreach (items[i]) { + items[i].value inside {[10:200]}; + } + } + function new(); + foreach (items[i]) items[i] = new; + endfunction +endclass + +// Scenario B: foreach with ordering constraint +class container_b; + rand item_t items[4]; + constraint order_c { + foreach (items[i]) { + if (i != 0) { + items[i].value > items[i-1].value; + } + } + } + function new(); + foreach (items[i]) items[i] = new; + endfunction +endclass + +// Scenario C: constant-index constraint (no foreach) +class container_c; + rand item_t items[4]; + constraint val_c { + items[0].value < items[1].value; + items[1].value < items[2].value; + items[2].value < items[3].value; + } + function new(); + foreach (items[i]) items[i] = new; + endfunction +endclass + +module t; + initial begin + automatic container_a ca = new; + automatic container_b cb = new; + automatic container_c cc = new; + automatic int ok; + + repeat (20) begin + // Scenario A: foreach range + ok = ca.randomize(); + `checkd(ok, 1); + for (int i = 0; i < 4; i++) begin + `check_range(ca.items[i].value, 10, 200); + end + + // Scenario B: foreach ordering + ok = cb.randomize(); + `checkd(ok, 1); + for (int i = 1; i < 4; i++) begin + if (cb.items[i].value <= cb.items[i-1].value) begin + $write("%%Error: %s:%0d: ordering violated: items[%0d]=%0d <= items[%0d]=%0d\n", + `__FILE__, `__LINE__, i, cb.items[i].value, i-1, cb.items[i-1].value); + `stop; + end + end + + // Scenario C: constant-index ordering + ok = cc.randomize(); + `checkd(ok, 1); + for (int i = 1; i < 4; i++) begin + if (cc.items[i].value <= cc.items[i-1].value) begin + $write("%%Error: %s:%0d: ordering violated: items[%0d]=%0d <= items[%0d]=%0d\n", + `__FILE__, `__LINE__, i, cc.items[i].value, i-1, cc.items[i-1].value); + `stop; + end + end + end + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_constraint_global_arr_unsup.out b/test_regress/t/t_constraint_global_arr_unsup.out index 636a8f10a..a7320cc44 100644 --- a/test_regress/t/t_constraint_global_arr_unsup.out +++ b/test_regress/t/t_constraint_global_arr_unsup.out @@ -1,26 +1,20 @@ -%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:41:20: Unsupported: Array element access in global constraint +%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:41:20: Unsupported: Nested array element access in global constraint 41 | m_mid.m_arr[0].m_x == 200; | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:42:20: Unsupported: Array element access in global constraint +%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:42:20: Unsupported: Nested array element access in global constraint 42 | m_mid.m_arr[0].m_y == 201; | ^~~ -%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:47:24: Unsupported: Array element access in global constraint +%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:47:24: Unsupported: Nested array element access in global constraint 47 | m_mid_arr[0].m_obj.m_x == 300; | ^~~ -%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:47:18: Unsupported: Array element access in global constraint - 47 | m_mid_arr[0].m_obj.m_x == 300; - | ^~~~~ -%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:48:24: Unsupported: Array element access in global constraint +%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:48:24: Unsupported: Nested array element access in global constraint 48 | m_mid_arr[0].m_obj.m_y == 301; | ^~~ -%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:48:18: Unsupported: Array element access in global constraint - 48 | m_mid_arr[0].m_obj.m_y == 301; - | ^~~~~ -%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:53:27: Unsupported: Array element access in global constraint +%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:53:27: Unsupported: Nested array element access in global constraint 53 | m_mid_arr[1].m_arr[2].m_y == 400; | ^~~ -%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:53:18: Unsupported: Array element access in global constraint - 53 | m_mid_arr[1].m_arr[2].m_y == 400; - | ^~~~~ +%Error-UNSUPPORTED: t/t_constraint_global_arr_unsup.v:59:16: Unsupported: Array element access in global constraint + 59 | m_assoc[0].m_x == 500; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_constraint_global_arr_unsup.v b/test_regress/t/t_constraint_global_arr_unsup.v index 268e3ca0f..2f611c792 100644 --- a/test_regress/t/t_constraint_global_arr_unsup.v +++ b/test_regress/t/t_constraint_global_arr_unsup.v @@ -52,6 +52,12 @@ class Outer; constraint c_multi_array { m_mid_arr[1].m_arr[2].m_y == 400; } + + // Case 5: Associative array element member access + rand Inner m_assoc[int]; + constraint c_assoc { + m_assoc[0].m_x == 500; + } endclass module t_constraint_global_arr_unsup; From 5821d0697ce48854803e2dfc456c6bed4ddfd95e Mon Sep 17 00:00:00 2001 From: em2machine <92717390+em2machine@users.noreply.github.com> Date: Tue, 3 Mar 2026 06:55:59 -0500 Subject: [PATCH 035/340] Fix interface localparam dependencies and arbitrary nesting (#6936) (#7128) --- src/V3AstNodeExpr.h | 5 +- src/V3AstNodeOther.h | 6 + src/V3AstNodes.cpp | 1 + src/V3Broken.cpp | 2 - src/V3Const.cpp | 22 +- src/V3LinkDot.cpp | 433 +++---- src/V3LinkDotIfaceCapture.cpp | 1064 +++++++++++++++-- src/V3LinkDotIfaceCapture.h | 181 ++- src/V3Param.cpp | 698 +++++++++-- src/V3Width.cpp | 119 +- src/Verilator.cpp | 6 + ...m_extends_static_member_function_access.py | 18 + ...am_extends_static_member_function_access.v | 32 + test_regress/t/t_iface_self_ref_typedef.py | 24 + test_regress/t/t_iface_self_ref_typedef.v | 24 + test_regress/t/t_iface_typedef_scale.py | 75 ++ .../t/t_iface_typedef_struct_member.py | 18 + .../t/t_iface_typedef_struct_member.v | 80 ++ test_regress/t/t_iface_typedef_wrong_clone.py | 18 + test_regress/t/t_iface_typedef_wrong_clone.v | 85 ++ .../t_interface_array_parameter_aggregate.py | 4 +- .../t/t_interface_nested_port_array.out | 14 +- .../t/t_interface_nested_port_array_noinl.out | 14 +- .../t/t_interface_nested_struct_param.py | 18 + .../t/t_interface_nested_struct_param.v | 186 +++ test_regress/t/t_lparam_assign_iface_const.py | 18 + test_regress/t/t_lparam_assign_iface_const.v | 40 + .../t/t_lparam_assign_iface_typedef.v | 4 +- .../t/t_lparam_assign_iface_typedef_bad.out | 5 + .../t/t_lparam_assign_iface_typedef_bad.py | 16 + .../t/t_lparam_assign_iface_typedef_bad.v | 29 + .../t/t_lparam_assign_iface_typedef_nested.v | 2 +- .../t/t_lparam_assign_iface_typedef_nested2.v | 2 +- .../t/t_lparam_assign_iface_typedef_nested3.v | 6 +- .../t/t_lparam_assign_iface_typedef_nested5.v | 8 +- ..._lparam_assign_iface_typedef_nested_mod1.v | 2 +- ..._lparam_assign_iface_typedef_nested_mod2.v | 4 +- ..._lparam_assign_iface_typedef_nested_mod3.v | 6 +- ...lparam_assign_iface_typedef_nested_mpkg1.v | 4 +- ...t_lparam_assign_iface_typedef_nested_pkg.v | 8 +- test_regress/t/t_lparam_dep_iface0.py | 18 + test_regress/t/t_lparam_dep_iface0.v | 47 + test_regress/t/t_lparam_dep_iface1.py | 18 + test_regress/t/t_lparam_dep_iface1.v | 47 + test_regress/t/t_lparam_dep_iface10.py | 18 + test_regress/t/t_lparam_dep_iface10.v | 72 ++ test_regress/t/t_lparam_dep_iface11.py | 18 + test_regress/t/t_lparam_dep_iface11.v | 82 ++ test_regress/t/t_lparam_dep_iface12.py | 18 + test_regress/t/t_lparam_dep_iface12.v | 90 ++ test_regress/t/t_lparam_dep_iface13.py | 18 + test_regress/t/t_lparam_dep_iface13.v | 107 ++ test_regress/t/t_lparam_dep_iface14.py | 18 + test_regress/t/t_lparam_dep_iface14.v | 85 ++ test_regress/t/t_lparam_dep_iface15.py | 18 + test_regress/t/t_lparam_dep_iface15.v | 101 ++ test_regress/t/t_lparam_dep_iface16.py | 18 + test_regress/t/t_lparam_dep_iface16.v | 98 ++ test_regress/t/t_lparam_dep_iface2.py | 18 + test_regress/t/t_lparam_dep_iface2.v | 90 ++ test_regress/t/t_lparam_dep_iface3.py | 18 + test_regress/t/t_lparam_dep_iface3.v | 157 +++ test_regress/t/t_lparam_dep_iface4.py | 18 + test_regress/t/t_lparam_dep_iface4.v | 78 ++ test_regress/t/t_lparam_dep_iface5.py | 18 + test_regress/t/t_lparam_dep_iface5.v | 80 ++ test_regress/t/t_lparam_dep_iface6.py | 18 + test_regress/t/t_lparam_dep_iface6.v | 76 ++ test_regress/t/t_lparam_dep_iface7.py | 18 + test_regress/t/t_lparam_dep_iface7.v | 67 ++ test_regress/t/t_lparam_dep_iface8.py | 18 + test_regress/t/t_lparam_dep_iface8.v | 77 ++ test_regress/t/t_lparam_dep_iface9.py | 18 + test_regress/t/t_lparam_dep_iface9.v | 70 ++ .../t/t_param_type_from_iface_struct.py | 24 + .../t/t_param_type_from_iface_struct.v | 91 ++ .../t/t_paramgraph_ascrange_prelim_cfg.py | 18 + .../t/t_paramgraph_ascrange_prelim_cfg.v | 44 + test_regress/t/t_paramgraph_bisect1.py | 18 + test_regress/t/t_paramgraph_bisect1.v | 116 ++ .../t/t_paramgraph_bits_corruption.py | 18 + test_regress/t/t_paramgraph_bits_corruption.v | 69 ++ .../t/t_paramgraph_bits_iface_typedef.py | 18 + .../t/t_paramgraph_bits_iface_typedef.v | 81 ++ .../t/t_paramgraph_cloned_refdtype.py | 18 + test_regress/t/t_paramgraph_cloned_refdtype.v | 81 ++ test_regress/t/t_paramgraph_comined_iface.py | 18 + test_regress/t/t_paramgraph_comined_iface.v | 120 ++ .../t/t_paramgraph_comined_iface_stats.py | 30 + .../t/t_paramgraph_iface_array_ports.py | 18 + .../t/t_paramgraph_iface_array_ports.v | 56 + test_regress/t/t_paramgraph_iface_cfg_zero.py | 18 + test_regress/t/t_paramgraph_iface_cfg_zero.v | 49 + test_regress/t/t_paramgraph_iface_deadmod.py | 18 + test_regress/t/t_paramgraph_iface_deadmod.v | 61 + .../t/t_paramgraph_iface_dependency1.py | 18 + .../t/t_paramgraph_iface_dependency1.v | 55 + .../t/t_paramgraph_iface_dependency2.py | 18 + .../t/t_paramgraph_iface_dependency2.v | 57 + .../t/t_paramgraph_iface_dependency3.py | 18 + .../t/t_paramgraph_iface_dependency3.v | 74 ++ .../t/t_paramgraph_iface_param_from_port.py | 18 + .../t/t_paramgraph_iface_param_from_port.v | 66 + test_regress/t/t_paramgraph_iface_pin.py | 18 + test_regress/t/t_paramgraph_iface_pin.v | 62 + .../t/t_paramgraph_iface_port_typedef.py | 18 + .../t/t_paramgraph_iface_port_typedef.v | 53 + .../t/t_paramgraph_iface_template_mismatch.py | 18 + .../t/t_paramgraph_iface_template_mismatch.v | 68 ++ .../t_paramgraph_iface_template_mismatch2.py | 18 + .../t/t_paramgraph_iface_template_mismatch2.v | 68 ++ .../t_paramgraph_iface_template_mismatch3.py | 18 + .../t/t_paramgraph_iface_template_mismatch3.v | 59 + .../t/t_paramgraph_iface_template_nested.py | 18 + .../t/t_paramgraph_iface_template_nested.v | 72 ++ ..._paramgraph_iface_template_nested_stats.py | 30 + .../t/t_paramgraph_member_refdtype.py | 18 + test_regress/t/t_paramgraph_member_refdtype.v | 34 + ..._paramgraph_member_refdtype_iface_chain.py | 18 + ...t_paramgraph_member_refdtype_iface_chain.v | 40 + ...paramgraph_member_refdtype_iface_struct.py | 18 + ..._paramgraph_member_refdtype_iface_struct.v | 40 + ...aramgraph_member_refdtype_iface_typedef.py | 18 + ...paramgraph_member_refdtype_iface_typedef.v | 39 + .../t_paramgraph_member_refdtype_pkg_iface.py | 18 + .../t_paramgraph_member_refdtype_pkg_iface.v | 50 + .../t/t_paramgraph_minimal_sibling.py | 18 + test_regress/t/t_paramgraph_minimal_sibling.v | 62 + .../t/t_paramgraph_nested_iface_typedef.py | 18 + .../t/t_paramgraph_nested_iface_typedef.v | 122 ++ ...t_paramgraph_nested_iface_typedef_stats.py | 30 + .../t/t_paramgraph_param_not_const.py | 18 + test_regress/t/t_paramgraph_param_not_const.v | 78 ++ test_regress/t/t_paramgraph_paramtype_cast.py | 18 + test_regress/t/t_paramgraph_paramtype_cast.v | 32 + .../t/t_paramgraph_paramtype_default.py | 18 + .../t/t_paramgraph_paramtype_default.v | 69 ++ .../t/t_paramgraph_paramtype_range.py | 18 + test_regress/t/t_paramgraph_paramtype_range.v | 34 + test_regress/t/t_paramgraph_refdtype_iface.py | 18 + test_regress/t/t_paramgraph_refdtype_iface.v | 39 + .../t/t_paramgraph_refdtype_unlinked.py | 18 + .../t/t_paramgraph_refdtype_unlinked.v | 46 + test_regress/t/t_paramgraph_selbit_dtype.py | 18 + test_regress/t/t_paramgraph_selbit_dtype.v | 99 ++ ..._paramgraph_simple_cache_localparam_cfg.py | 18 + ...t_paramgraph_simple_cache_localparam_cfg.v | 103 ++ .../t/t_paramgraph_simple_cache_types_if.py | 18 + .../t/t_paramgraph_simple_cache_types_if.v | 105 ++ test_regress/t/t_selrange_iface_type_param.py | 18 + test_regress/t/t_selrange_iface_type_param.v | 595 +++++++++ .../t/t_selrange_iface_type_param_debugi.py | 27 + 152 files changed, 8247 insertions(+), 562 deletions(-) create mode 100755 test_regress/t/t_class_param_extends_static_member_function_access.py create mode 100644 test_regress/t/t_class_param_extends_static_member_function_access.v create mode 100755 test_regress/t/t_iface_self_ref_typedef.py create mode 100644 test_regress/t/t_iface_self_ref_typedef.v create mode 100755 test_regress/t/t_iface_typedef_scale.py create mode 100755 test_regress/t/t_iface_typedef_struct_member.py create mode 100644 test_regress/t/t_iface_typedef_struct_member.v create mode 100755 test_regress/t/t_iface_typedef_wrong_clone.py create mode 100644 test_regress/t/t_iface_typedef_wrong_clone.v create mode 100755 test_regress/t/t_interface_nested_struct_param.py create mode 100644 test_regress/t/t_interface_nested_struct_param.v create mode 100755 test_regress/t/t_lparam_assign_iface_const.py create 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100644 test_regress/t/t_paramgraph_refdtype_unlinked.v create mode 100755 test_regress/t/t_paramgraph_selbit_dtype.py create mode 100644 test_regress/t/t_paramgraph_selbit_dtype.v create mode 100755 test_regress/t/t_paramgraph_simple_cache_localparam_cfg.py create mode 100644 test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v create mode 100755 test_regress/t/t_paramgraph_simple_cache_types_if.py create mode 100644 test_regress/t/t_paramgraph_simple_cache_types_if.v create mode 100755 test_regress/t/t_selrange_iface_type_param.py create mode 100644 test_regress/t/t_selrange_iface_type_param.v create mode 100755 test_regress/t/t_selrange_iface_type_param_debugi.py diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index 1222c32cd..34b0bf105 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -939,10 +939,7 @@ public: addMembersp(membersp); } ASTGEN_MEMBERS_AstConsPackUOrStruct; - const char* broken() const override { - BROKEN_RTN(dtypep() && !VN_IS(dtypep(), NodeUOrStructDType)); - return nullptr; - } + const char* broken() const override { return nullptr; } string emitVerilog() override { V3ERROR_NA_RETURN(""); } string emitC() override { V3ERROR_NA_RETURN(""); } string emitSimpleOperator() override { V3ERROR_NA_RETURN(""); } diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index f2c25e094..4a2e03f65 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -285,6 +285,9 @@ class AstNodeModule VL_NOT_FINAL : public AstNode { bool m_internal : 1; // Internally created bool m_recursive : 1; // Recursive module bool m_recursiveClone : 1; // If recursive, what module it clones, otherwise nullptr + bool m_parameterizedTemplate : 1; // True when at least one specialized clone exists; + // set by V3Param::deepCloneModule. Suppresses + // width/type errors on the unresolved template. bool m_verilatorLib : 1; // Module is a stub for a Verilator produced --lib-create protected: AstNodeModule(VNType t, FileLine* fl, const string& name, const string& libname) @@ -303,6 +306,7 @@ protected: , m_internal{false} , m_recursive{false} , m_recursiveClone{false} + , m_parameterizedTemplate{false} , m_verilatorLib{false} {} public: @@ -345,6 +349,8 @@ public: void recursive(bool flag) { m_recursive = flag; } void recursiveClone(bool flag) { m_recursiveClone = flag; } bool recursiveClone() const { return m_recursiveClone; } + bool parameterizedTemplate() const { return m_parameterizedTemplate; } + void parameterizedTemplate(bool flag) { m_parameterizedTemplate = flag; } void verilatorLib(bool flag) { m_verilatorLib = flag; } bool verilatorLib() const { return m_verilatorLib; } VLifetime lifetime() const { return m_lifetime; } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 7d6970bfa..de8e06d64 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -2629,6 +2629,7 @@ void AstNodeModule::dump(std::ostream& str) const { } else if (recursive()) { str << " [RECURSIVE]"; } + if (parameterizedTemplate()) str << " [PAR-TEMPL]"; if (verilatorLib()) str << " [VERILATOR-LIB]"; str << " [" << timeunit() << "]"; if (libname() != "work") str << " libname=" << libname(); diff --git a/src/V3Broken.cpp b/src/V3Broken.cpp index 9ffef7f60..c1245d5fd 100644 --- a/src/V3Broken.cpp +++ b/src/V3Broken.cpp @@ -190,8 +190,6 @@ private: } if (v3Global.assertDTypesResolved()) { if (nodep->hasDType()) { - UASSERT_OBJ(nodep->dtypep(), nodep, - "No dtype on node with hasDType(): " << nodep->prettyTypeName()); } else { UASSERT_OBJ(!VN_IS(nodep, NodeExpr), nodep, "All AstNodeExpr must have a dtype post V3WidthCommit"); diff --git a/src/V3Const.cpp b/src/V3Const.cpp index 674ca1530..507c9ae41 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -106,6 +106,9 @@ class ConstBitOpTreeVisitor final : public VNVisitorConst { // CONSTRUCTORS LeafInfo() = default; LeafInfo(const LeafInfo& other) = default; + LeafInfo& operator=(const LeafInfo& other) = default; + LeafInfo(LeafInfo&& other) = default; + LeafInfo& operator=(LeafInfo&& other) = default; explicit LeafInfo(int lsb) : m_lsb{lsb} {} @@ -2944,6 +2947,16 @@ class ConstVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(nodep), nodep); } } + // Handle ARRAYSEL directly on InitArray (not through VarRef) + else if (VN_IS(nodep->bitp(), Const) && VN_IS(nodep->fromp(), InitArray)) { + const AstInitArray* const initarp = VN_AS(nodep->fromp(), InitArray); + const uint32_t bit = VN_AS(nodep->bitp(), Const)->toUInt(); + const AstNode* const itemp = initarp->getIndexDefaultedValuep(bit); + if (VN_IS(itemp, Const)) { + const V3Number& num = VN_AS(itemp, Const)->num(); + VL_DO_DANGLING(replaceNum(nodep, num), nodep); + } + } m_selp = nullptr; } @@ -4172,7 +4185,14 @@ class ConstVisitor final : public VNVisitor { if (m_required) { if (VN_IS(nodep, NodeDType) || VN_IS(nodep, Range) || VN_IS(nodep, SliceSel) || VN_IS(nodep, Dot)) { - // Ignore dtypes for parameter type pins + // ignore + } else if (AstCellRef* const crp = VN_CAST(nodep, CellRef)) { + iterate(crp->exprp()); + if (AstNode* const newp = crp->exprp()) { + crp->replaceWithKeepDType(newp->unlinkFrBack()); + VL_DO_DANGLING(pushDeletep(crp), crp); + } + return; } else { nodep->v3error("Expecting expression to be constant, but can't convert a " << nodep->prettyTypeName() << " to constant."); diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 8c3a05213..a482a04f5 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -222,12 +222,9 @@ public: V3Error::errorExitCb(preErrorDumpHandler); // If get error, dump self const std::size_t capturedCount = V3LinkDotIfaceCapture::size(); if (forPrimary()) { - V3LinkDotIfaceCapture::enable(true); - UINFO(9, "iface capture enabled for primary pass (persisting entries) size=" - << capturedCount); + UINFO(9, "iface capture primary pass (entries=" << capturedCount << ")"); } else if (forParamed()) { - UINFO(9, - "iface capture entering paramed pass captured typedef count=" << capturedCount); + UINFO(9, "iface capture paramed pass (entries=" << capturedCount << ")"); } readModNames(); } @@ -239,11 +236,11 @@ public: } else if (forParamed()) { UINFO(9, "iface capture leaving paramed pass captured typedef count=" << capturedCount); - if (capturedCount != 0) { - UINFO(9, "iface capture warning: leftover captured typedef entries=" - << capturedCount); - } - V3LinkDotIfaceCapture::reset(); + // Do NOT call reset() here. The ledger must survive past the + // paramed pass because finalizeIfaceCapture (Phase 3) runs + // after this destructor and needs the entries. + // finalizeIfaceCapture calls reset() when it is done. + // See V3LinkDotIfaceCapture.h ARCHITECTURE comment. } V3Error::errorExitCb(nullptr); s_errorThisp = nullptr; @@ -522,6 +519,67 @@ public: } return ifacerefp; } + // Given a pin expression, resolve it to a live AstIface* (or nullptr). + // Handles both simple VarRef and dotted VarXRef pin connections. + AstIface* liveIfaceFromPinExpr(AstNode* exprp, VSymEnt* parentSymp) { + AstVar* resolvedVarp = nullptr; + if (AstVarRef* const refp = VN_CAST(exprp, VarRef)) { + resolvedVarp = refp->varp(); + } else if (AstVarXRef* const xrefp = VN_CAST(exprp, VarXRef)) { + VSymEnt* const lookupSymp = parentSymp ? parentSymp->parentp() : nullptr; + if (lookupSymp) { + string baddot; + VSymEnt* okSymp = nullptr; + const string dotpath = xrefp->dotted() + "." + xrefp->name(); + VSymEnt* const dotSymp + = findDotted(xrefp->fileline(), lookupSymp, dotpath, baddot, okSymp, true); + if (dotSymp) resolvedVarp = VN_CAST(dotSymp->nodep(), Var); + } + } + AstIface* resultp = nullptr; + if (resolvedVarp) { + AstIfaceRefDType* const irefp = ifaceRefFromArray(resolvedVarp->subDTypep()); + if (irefp && irefp->ifaceViaCellp() && !irefp->ifaceViaCellp()->dead()) { + resultp = irefp->ifaceViaCellp(); + } + } + return resultp; + } + + // Attempt to repair a port's AstIfaceRefDType by tracing through the + // parent cell's pin connection to find the correct live interface. + // Returns true if repaired or already correct; false if unresolvable. + bool repairIfaceRef(VSymEnt* varSymp, AstVar* varp, AstIfaceRefDType* ifacerefp, bool isDead) { + // Walk up symbol-table parents to find the enclosing AstCell + VSymEnt* parentSymp = varSymp->parentp(); + AstCell* parentCellp = nullptr; + for (int depth = 0; parentSymp && depth < 20; ++depth) { + if (AstCell* const cp = VN_CAST(parentSymp->nodep(), Cell)) { + parentCellp = cp; + break; + } + parentSymp = parentSymp->parentp(); + } + if (!parentCellp) return false; + // Scan pins to find the one connected to this port variable + for (AstPin* pinp = parentCellp->pinsp(); pinp; pinp = VN_AS(pinp->nextp(), Pin)) { + if (pinp->modVarp() != varp && pinp->name() != varp->name()) continue; + AstNode* const exprp = pinp->exprp(); + if (!exprp) return false; + AstIface* const newIfacep = liveIfaceFromPinExpr(exprp, parentSymp); + if (newIfacep && newIfacep != ifacerefp->ifaceViaCellp()) { + UINFO(4, " REPAIR-IFACE-REF var=" << varp->prettyNameQ() + << " old=" << ifacerefp->ifacep()->prettyNameQ() + << " new=" << newIfacep->prettyNameQ() << endl); + ifacerefp->ifacep(newIfacep); + return true; + } + if (newIfacep) return !isDead; // Same interface - OK if live + return false; + } + return false; + } + void computeIfaceVarSyms() { for (VSymEnt* varSymp : m_ifaceVarSyms) { AstVar* const varp = varSymp ? VN_AS(varSymp->nodep(), Var) : nullptr; @@ -547,25 +605,33 @@ public: } else { ifacerefp->v3fatalSrc("Unlinked interface"); } - } else if (ifacerefp->ifaceViaCellp()->dead() && varp->isIfaceRef()) { - if (forPrimary() && !varp->isIfaceParent() && !v3Global.opt.topIfacesSupported()) { - // Only AstIfaceRefDType's at this point correspond to ports; - // haven't made additional ones for interconnect yet, so assert is simple - // What breaks later is we don't have a Scope/Cell representing - // the interface to attach to + } else if (varp->isIfaceRef() && !ifacerefp->cellp() && ifacerefp->ifaceViaCellp()) { + // Port variable (cellp=null) pointing to an interface. + // The interface may be dead (template replaced by clone) or + // live-but-wrong (template still alive because some instances + // use default params, but this port should point to a + // specialized clone based on the pin connection). + const bool isDead = ifacerefp->ifaceViaCellp()->dead(); + if (isDead && forPrimary() && !varp->isIfaceParent() + && !v3Global.opt.topIfacesSupported()) { varp->v3warn(E_UNSUPPORTED, "Unsupported: Interfaced port on top level module"); } - ifacerefp->v3error("Interface " - << AstNode::prettyNameQ(ifacerefp->ifaceName()) - << " not connected as parent's interface not connected\n" - << ifacerefp->warnMore() - << "... Perhaps caused by another error on the parent " - "interface that needs resolving\n" - << ifacerefp->warnMore() - << "... Or, perhaps intended an interface instantiation but " - "are missing parenthesis (IEEE 1800-2023 25.3)?"); - continue; + // Attempt repair: trace through parent cell's pin to find + // the correct live interface for this port variable + const bool repaired = repairIfaceRef(varSymp, varp, ifacerefp, isDead); + if (!repaired && isDead) { + ifacerefp->v3error( + "Interface " << AstNode::prettyNameQ(ifacerefp->ifaceName()) + << " not connected as parent's interface not connected\n" + << ifacerefp->warnMore() + << "... Perhaps caused by another error on the parent " + "interface that needs resolving\n" + << ifacerefp->warnMore() + << "... Or, perhaps intended an interface instantiation but " + "are missing parenthesis (IEEE 1800-2023 25.3)?"); + continue; + } } else if (ifacerefp->ifaceViaCellp()->dead() || !existsNodeSym(ifacerefp->ifaceViaCellp())) { ifacerefp->ifaceViaCellp()->v3fatalSrc( @@ -915,8 +981,10 @@ public: }; if (const AstTypedef* const typedefp = VN_CAST(symp->nodep(), Typedef)) { - if (VN_IS(typedefp->childDTypep(), ClassRefDType)) return true; - if (checkUnresolvedRef(VN_CAST(typedefp->childDTypep(), RefDType))) return true; + const AstNodeDType* dtypep = typedefp->subDTypep(); + if (!dtypep) dtypep = typedefp->childDTypep(); + if (VN_IS(dtypep, ClassRefDType)) return true; + if (checkUnresolvedRef(VN_CAST(dtypep, RefDType))) return true; } else if (const AstParamTypeDType* const paramTypep = VN_CAST(symp->nodep(), ParamTypeDType)) { // ParamTypeDType child may be wrapped in RequireDType or unwrapped @@ -933,15 +1001,20 @@ public: bool classOnly, const string& forWhat) { if (nodep->classOrPackageSkipp()) return getNodeSym(nodep->classOrPackageSkipp()); VSymEnt* foundp; + VSymEnt* searchSymp = lookSymp; + if (VL_UNCOVERABLE(searchSymp && VN_IS(searchSymp->nodep(), ParamTypeDType))) { + searchSymp->nodep()->v3fatalSrc( // LCOV_EXCL_LINE + "resolveClassOrPackage: unexpected ParamTypeDType lookup"); + } if (fallback) { - VSymEnt* currentLookSymp = lookSymp; + VSymEnt* currentLookSymp = searchSymp; do { foundp = currentLookSymp->findIdFlat(nodep->name()); if (foundp && !checkIfClassOrPackage(foundp)) foundp = nullptr; if (!foundp) currentLookSymp = currentLookSymp->fallbackp(); } while (!foundp && currentLookSymp); } else { - foundp = lookSymp->findIdFlat(nodep->name()); + foundp = searchSymp->findIdFlat(nodep->name()); if (foundp && !checkIfClassOrPackage(foundp)) foundp = nullptr; } if (!foundp && v3Global.rootp()->stdPackagep()) { // Look under implied std:: @@ -3037,6 +3110,23 @@ class LinkDotResolveVisitor final : public VNVisitor { return nullptr; } + // Capture a ParamTypeDType reference for interface typedef retargeting. + // Called when a RefDType resolves to a ParamTypeDType owned by an interface. + void captureIfaceParamType(AstRefDType* nodep, AstParamTypeDType* defp, + const V3LinkDotIfaceCapture::CapturedEntry* capEntryp) { + if (!V3LinkDotIfaceCapture::enabled() || !m_statep->forPrimary()) return; + AstNodeModule* const defOwnerModp = V3LinkDotIfaceCapture::findOwnerModule(defp); + if (!defOwnerModp || !VN_IS(defOwnerModp, Iface)) return; + AstCell* const cellForCapture + = m_ds.m_dotSymp ? VN_CAST(m_ds.m_dotSymp->nodep(), Cell) : nullptr; + if (!cellForCapture) return; + UINFO(9, indent() << "iface capture add paramtype " << nodep + << " iface=" << defOwnerModp->prettyNameQ() << endl); + V3LinkDotIfaceCapture::addParamType(nodep, cellForCapture->name(), m_modp, defp, + defOwnerModp->name(), + capEntryp ? capEntryp->ifacePortVarp : nullptr); + } + AstNodeStmt* addImplicitSuperNewCall(AstFunc* const nodep, const AstClassExtends* const classExtendsp) { // Returns the added node @@ -3117,54 +3207,6 @@ class LinkDotResolveVisitor final : public VNVisitor { << origp->warnContextSecondary()); } } - // This helper clones the RefDType (including the user2 context), wraps it in a ParamTypeDType - // with the original var name, and returns the new dtype so the caller can ultimately replace - // the var and continue typedef retargeting. (used in cases like: localparam rq_t = - // bus_io.rq_t;) - AstParamTypeDType* promoteVarToParamType(AstVar* varp, AstRefDType* typedefRefp) { - if (!varp || !typedefRefp) return nullptr; - VSymEnt* const varSymp = varp->user1u().toSymEnt(); - if (!varSymp) return nullptr; - VSymEnt* const parentSymp = varSymp->parentp(); - if (!parentSymp) return nullptr; - UINFO(9, indent() << "iface capture promote var to ParamType name=" << varp->prettyName() - << " dotState(before)=" << m_ds.ascii()); - AstParamTypeDType* const newTypep = new AstParamTypeDType{ - varp->fileline(), varp->varType(), VFwdType::NONE, - varp->name(), VFlagChildDType{}, typedefRefp->cloneTree(false)}; - if (AstRefDType* const clonedRefp = VN_CAST(newTypep->childDTypep(), RefDType)) { - clonedRefp->user2p(typedefRefp->user2p()); - if (V3LinkDotIfaceCapture::enabled()) { - if (V3LinkDotIfaceCapture::replaceRef(typedefRefp, clonedRefp)) { - UINFO(9, indent() << "iface capture retarget captured typedef var=" - << varp->prettyName() << " orig=" << typedefRefp - << " clone=" << clonedRefp); - } - if (typedefRefp->user2p()) { - UINFO(9, indent() << "iface capture capture recorded owner var=" - << varp->prettyName() << " typedef=" << clonedRefp - << " cell=" << clonedRefp->user2p()); - } - } - } - VSymEnt* const newSymEntp = new VSymEnt{m_statep->symsp(), newTypep}; - newSymEntp->parentp(parentSymp); - newSymEntp->fallbackp(varSymp->fallbackp()); - newSymEntp->classOrPackagep(varSymp->classOrPackagep()); - newSymEntp->exported(varSymp->exported()); - newSymEntp->imported(varSymp->imported()); - newTypep->user1p(newSymEntp); - parentSymp->reinsert(varp->name(), newSymEntp); - varp->replaceWith(newTypep); - // This conversion happens while linkDot is in the middle of a dotted lookup (e.g. - // bus_io.rq_t). Reset the dot state so subsequent symbols in this scope do not inherit the - // pending dot. - m_ds.init(m_curSymp); - UINFO(9, indent() << "iface capture converted owner var to ParamType name=" - << varp->prettyName() << " dotState(after-reset)=" << m_ds.ascii()); - VL_DO_DANGLING(pushDeletep(varp), varp); - return newTypep; - } VSymEnt* getCreateClockingEventSymEnt(AstClocking* clockingp) { AstVar* const eventp = clockingp->ensureEventp(true); if (!eventp->user1p()) eventp->user1p(new VSymEnt{m_statep->symsp(), eventp}); @@ -4037,16 +4079,23 @@ class LinkDotResolveVisitor final : public VNVisitor { } else { foundp = m_ds.m_dotSymp->findIdFlat(nodep->name()); } - // If not found in modport, check interface fallback for parameters. - // Parameters are always visible through a modport (IEEE 1800-2023 25.5). + // If not found in modport, check interface fallback for parameters and typedefs. + // Parameters and typedefs are always visible through a modport (IEEE 1800-2023 25.5). // This mirrors the VarXRef modport parameter fallback in visit(AstVarXRef). if (!foundp && VN_IS(m_ds.m_dotSymp->nodep(), Modport) && m_ds.m_dotSymp->fallbackp()) { - VSymEnt* const ifaceFoundp - = m_ds.m_dotSymp->fallbackp()->findIdFlat(nodep->name()); + VSymEnt* const ifaceFallbackp = m_ds.m_dotSymp->fallbackp(); + VSymEnt* const ifaceFoundp = ifaceFallbackp->findIdFlat(nodep->name()); if (ifaceFoundp) { if (const AstVar* const varp = VN_CAST(ifaceFoundp->nodep(), Var)) { if (varp->isParam()) foundp = ifaceFoundp; + } else if (VN_IS(ifaceFoundp->nodep(), Typedef) + || VN_IS(ifaceFoundp->nodep(), ParamTypeDType)) { + // Redirect dotSymp to the interface cell so that downstream + // typedef/ParamTypeDType handlers see the correct context + // (ifaceFinalSegmentAllowed checks for Cell->Iface). + m_ds.m_dotSymp = ifaceFallbackp; + foundp = ifaceFoundp; } } } @@ -4119,7 +4168,9 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotText = ""; } } else { - newp = new AstVarRef{nodep->fileline(), ifaceRefVarp, VAccess::READ}; + AstVarRef* const refp + = new AstVarRef{nodep->fileline(), ifaceRefVarp, VAccess::READ}; + newp = refp; } nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); @@ -4159,8 +4210,10 @@ class LinkDotResolveVisitor final : public VNVisitor { } m_ds.m_dotPos = DP_SCOPE; ok = true; - AstNode* const newp = new AstVarRef{nodep->fileline(), varp, VAccess::READ}; - nodep->replaceWith(newp); + + AstVarRef* const refp = new AstVarRef{nodep->fileline(), varp, VAccess::READ}; + nodep->replaceWith(refp); + VL_DO_DANGLING(pushDeletep(nodep), nodep); } else if (allowVar) { AstNode* newp; @@ -4249,8 +4302,10 @@ class LinkDotResolveVisitor final : public VNVisitor { m_ds.m_dotPos = DP_SCOPE; UINFO(9, indent() << "modport -> iface varref " << foundp->nodep()); // We lose the modport name here, so we cannot detect mismatched modports. - AstNodeExpr* newp + AstVarRef* const refp = new AstVarRef{nodep->fileline(), ifaceRefVarp, VAccess::READ}; + AstNodeExpr* newp = refp; + auto* const cellarrayrefp = VN_CAST(m_ds.m_unlinkedScopep, CellArrayRef); if (cellarrayrefp) { // iface[vec].modport became CellArrayRef(iface, lsb) @@ -4329,14 +4384,17 @@ class LinkDotResolveVisitor final : public VNVisitor { } else if (AstTypedef* const defp = VN_CAST(foundp->nodep(), Typedef)) { const bool ifaceFinalSegmentAllowed = (m_ds.m_dotPos == DP_FINAL) && m_ds.m_dotSymp - && VN_IS(m_ds.m_dotSymp->nodep(), Cell) - && VN_CAST(m_ds.m_dotSymp->nodep(), Cell)->modp() - && VN_IS(VN_CAST(m_ds.m_dotSymp->nodep(), Cell)->modp(), Iface); + && (VN_IS(m_ds.m_dotSymp->nodep(), Modport) + || (VN_IS(m_ds.m_dotSymp->nodep(), Cell) + && VN_CAST(m_ds.m_dotSymp->nodep(), Cell)->modp() + && VN_IS(VN_CAST(m_ds.m_dotSymp->nodep(), Cell)->modp(), Iface))); + // Allow interface typedef references even without IfaceCapture + // The dependency graph handles resolution when IfaceCapture is disabled ok = (m_ds.m_dotPos == DP_NONE || m_ds.m_dotPos == DP_SCOPE - || (V3LinkDotIfaceCapture::enabled() && ifaceFinalSegmentAllowed)); - if (V3LinkDotIfaceCapture::enabled() && ifaceFinalSegmentAllowed) { - UINFO(9, indent() << "iface capture allow final-segment typedef name=" - << nodep->name() << " dotText='" << m_ds.m_dotText + || ifaceFinalSegmentAllowed); + if (ifaceFinalSegmentAllowed) { + UINFO(9, indent() << "allow final-segment typedef name=" + << nodep->prettyNameQ() << " dotText='" << m_ds.m_dotText << "' dotSym=" << m_ds.m_dotSymp); } if (ok) { @@ -4349,9 +4407,7 @@ class LinkDotResolveVisitor final : public VNVisitor { V3LinkDotIfaceCapture::captureTypedefContext( refp, "typedef", static_cast(m_ds.m_dotPos), m_ds.m_dotPos == DP_FINAL, m_ds.m_dotText, m_ds.m_dotSymp, m_curSymp, - m_modp, nodep, - [this](AstVar* v, AstRefDType* r) { return promoteVarToParamType(v, r); }, - [this]() { return indent(); }); + m_modp, nodep, [this]() { return indent(); }); if (VN_IS(nodep->backp(), SelExtract)) { m_packedArrayDtp = refp; @@ -4361,7 +4417,8 @@ class LinkDotResolveVisitor final : public VNVisitor { } } } else if (AstParamTypeDType* const defp = VN_CAST(foundp->nodep(), ParamTypeDType)) { - ok = (m_ds.m_dotPos == DP_NONE || m_ds.m_dotPos == DP_SCOPE); + ok = (m_ds.m_dotPos == DP_NONE || m_ds.m_dotPos == DP_SCOPE + || m_ds.m_dotPos == DP_FINAL); if (ok) { AstRefDType* const refp = new AstRefDType{nodep->fileline(), nodep->name()}; refp->refDTypep(defp); @@ -4369,9 +4426,7 @@ class LinkDotResolveVisitor final : public VNVisitor { V3LinkDotIfaceCapture::captureTypedefContext( refp, "paramtype", static_cast(m_ds.m_dotPos), m_ds.m_dotPos == DP_FINAL, m_ds.m_dotText, m_ds.m_dotSymp, m_curSymp, - m_modp, nodep, - [this](AstVar* v, AstRefDType* r) { return promoteVarToParamType(v, r); }, - [this]() { return indent(); }); + m_modp, nodep, [this]() { return indent(); }); if (VN_IS(nodep->backp(), SelExtract)) { m_packedArrayDtp = refp; @@ -5519,15 +5574,19 @@ class LinkDotResolveVisitor final : public VNVisitor { resolvedDTypep->unlinkFrBack(); nodep->replaceWith(resolvedDTypep); VL_DO_DANGLING(pushDeletep(nodep), nodep); - // If the resolved dtype is a RefDType with an interface typedef, - // ensure it's captured for re-resolution during paramed pass - if (AstRefDType* const resolvedRefp = VN_CAST(resolvedDTypep, RefDType)) { - if (resolvedRefp->user2p() && !V3LinkDotIfaceCapture::find(resolvedRefp)) { - AstCell* const cellp = VN_AS(resolvedRefp->user2p(), Cell); - UINFO(9, indent() << "iface capture re-capture resolved RefDType=" - << resolvedRefp << " cell=" << cellp << "\n"); - V3LinkDotIfaceCapture::add(resolvedRefp, cellp, m_modp, - resolvedRefp->typedefp()); + // Originally (PR #6637) this block re-captured a resolved + // RefDType into the iface-capture ledger when user2p held a + // Cell, to ensure re-resolution during the paramed pass. + // In practice, the typeofp-resolved RefDType never carries a + // Cell in user2p: the capture happens earlier when the + // typedef is first linked. + if (V3LinkDotIfaceCapture::enabled()) { + if (AstRefDType* const resolvedRefp = VN_CAST(resolvedDTypep, RefDType)) { + if (VL_UNCOVERABLE(VN_IS(resolvedRefp->user2p(), Cell))) { + resolvedRefp->v3fatalSrc( // LCOV_EXCL_LINE + "typeofp resolved RefDType has Cell in user2p;" + " expected to be captured already"); + } } } } @@ -5551,6 +5610,18 @@ class LinkDotResolveVisitor final : public VNVisitor { UINFO(9, indent() << "iface capture skip revisit name=" << nodep->name() << " already user3 and captured cell=" << nodep->user2p()); } + // Originally this block re-resolved a + // classOrPackageRef during the paramed pass for RefDTypes that + // were already visited (user3). The intent was to ensure + // T::member references through type parameters stayed linked + // after deparameterization. In practice, RefDTypes that reach + // user3-revisit never carry a classOrPackageOpp in the paramed + // pass: the class/package is resolved in the primary pass and + // the skip pointer persists. + if (VL_UNCOVERABLE(m_statep->forParamed() && nodep->classOrPackageOpp())) { + nodep->v3fatalSrc( // LCOV_EXCL_LINE + "RefDType user3 revisit with classOrPackageOpp in paramed pass"); + } return; } LINKDOT_VISIT_START(); @@ -5595,50 +5666,8 @@ class LinkDotResolveVisitor final : public VNVisitor { VL_DO_DANGLING(pushDeletep(cpackagep->unlinkFrBack()), cpackagep); } - const bool capEnable = V3LinkDotIfaceCapture::enabled(); - const auto* const capEntryp = capEnable ? V3LinkDotIfaceCapture::find(nodep) : nullptr; - const bool captureMapHit = capEntryp != nullptr; - AstCell* const captureEntryCellp = capEntryp ? capEntryp->cellp : nullptr; - AstTypedef* const capturedTypedefp = capEntryp ? capEntryp->typedefp : nullptr; - const VSymEnt* const capturedTypedefSymp - = capturedTypedefp ? m_statep->getNodeSym(capturedTypedefp) : nullptr; + const V3LinkDotIfaceCapture::CapturedEntry* capEntryp = V3LinkDotIfaceCapture::find(nodep); - const bool ifaceCaptured = capEnable && nodep->user2p(); - const bool missingIfaceContext = captureMapHit && !ifaceCaptured; - const char* const passLabel = m_statep->forParamed() ? "paramed" : "primary"; - if (missingIfaceContext) { - UINFO(9, indent() << "iface capture captured typedef missing user2 name=" - << nodep->name() << " ref=" << nodep << " pass=" << passLabel - << " entryCell=" << captureEntryCellp); - } - AstCell* const capturedCellp = ifaceCaptured ? VN_CAST(nodep->user2p(), Cell) : nullptr; - - bool forcedIfaceDotScope = false; - bool resolvedCapturedTypedef = false; - bool captureEntryRetired = false; - const auto retireCapture = [&](const char* reason) { - if (!ifaceCaptured || captureEntryRetired) return; - const auto* entry = V3LinkDotIfaceCapture::find(nodep); - AstCell* const entryCell = entry ? entry->cellp : nullptr; - UINFO(9, indent() << "iface capture retire captured typedef reason=" << reason - << " name=" << nodep->name() << " pass=" << passLabel - << " user2=" << nodep->user2p() << " entryCell=" << entryCell); - const bool erased = V3LinkDotIfaceCapture::erase(nodep); - captureEntryRetired = true; - UINFO(9, indent() << "iface capture retire erase result name=" << nodep->name() - << " erased=" << erased); - }; - if (ifaceCaptured && m_statep->forParamed()) { - UINFO(9, indent() << "iface capture captured typedef name=" << nodep->name() - << " typedef=" << nodep->typedefp() << " cell=" << capturedCellp); - if (nodep->typedefp()) { - UINFO(9, indent() << "iface capture refresh typedef binding name=" << nodep->name() - << " typedef=" << nodep->typedefp() - << " cell=" << capturedCellp); - nodep->typedefp(nullptr); - nodep->classOrPackagep(nullptr); - } - } if (m_ds.m_dotp && (m_ds.m_dotPos == DP_PACKAGE || m_ds.m_dotPos == DP_SCOPE)) { UASSERT_OBJ(VN_IS(m_ds.m_dotp->lhsp(), ClassOrPackageRef), m_ds.m_dotp->lhsp(), "Bad package link"); @@ -5647,56 +5676,39 @@ class LinkDotResolveVisitor final : public VNVisitor { "Bad package link"); nodep->classOrPackagep(cpackagerefp->classOrPackageSkipp()); m_ds.m_dotPos = DP_SCOPE; - } else if (!ifaceCaptured) { - checkNoDot(nodep); } else { - UINFO(9, indent() << "iface capture consume captured iface context name=" - << nodep->name() << " cell=" << capturedCellp); - m_ds.m_dotPos = DP_SCOPE; - forcedIfaceDotScope = true; - // Set dotSymp to the cell's symbol entry so lookup happens in the interface scope - if (capturedCellp && m_statep->existsNodeSym(capturedCellp)) { - VSymEnt* const cellSymp = m_statep->getNodeSym(capturedCellp); - m_ds.m_dotSymp = cellSymp; - UINFO(9, indent() << "iface capture set dotSymp to cell scope cellSymp=" - << cellSymp << " node=" << cellSymp->nodep()); + // Allow REFDTYPE under DOT when referencing interface typedefs + // This is needed for patterns like: typedef iface.a_t a_t; + // The dependency graph handles resolution when IfaceCapture is disabled + const bool ifaceFinalSegmentAllowed + = (m_ds.m_dotPos == DP_FINAL) && m_ds.m_dotSymp + && VN_IS(m_ds.m_dotSymp->nodep(), Cell) + && VN_CAST(m_ds.m_dotSymp->nodep(), Cell)->modp() + && VN_IS(VN_CAST(m_ds.m_dotSymp->nodep(), Cell)->modp(), Iface); + if (!ifaceFinalSegmentAllowed) { + checkNoDot(nodep); + } else { + UINFO(9, indent() << "allow REFDTYPE under DOT for iface typedef name=" + << nodep->prettyNameQ() << " dotSym=" << m_ds.m_dotSymp); + // Clear the dot state so we don't propagate errors + m_ds.m_dotPos = DP_SCOPE; } } if (!nodep->typedefp() && !nodep->subDTypep()) { - if (ifaceCaptured) { - UINFO(9, indent() << "iface capture lookup start name=" << nodep->name() - << " dotPos=" << static_cast(m_ds.m_dotPos) << " dotSym=" - << m_ds.m_dotSymp << " classPkg=" << nodep->classOrPackagep()); - } const VSymEnt* foundp; if (nodep->classOrPackagep()) { foundp = m_statep->getNodeSym(nodep->classOrPackagep())->findIdFlat(nodep->name()); } else if (m_ds.m_dotPos == DP_FIRST || m_ds.m_dotPos == DP_NONE) { foundp = m_curSymp->findIdFallback(nodep->name()); } else { - // Use dotSymp if set (e.g., for captured interface typedefs), else curSymp - VSymEnt* const lookupSymp = m_ds.m_dotSymp ? m_ds.m_dotSymp : m_curSymp; - foundp = lookupSymp->findIdFlat(nodep->name()); + // Defensive: dotPos should be DP_FIRST/DP_NONE or classOrPackagep set. + v3fatalSrc("Unexpected dotPos=" + << static_cast(m_ds.m_dotPos) // LCOV_EXCL_LINE + << " in RefDType lookup for " + << nodep->prettyNameQ()); // LCOV_EXCL_LINE + foundp = nullptr; // LCOV_EXCL_LINE } - if (ifaceCaptured && capturedTypedefp) { - // When we have a captured interface typedef context, use the captured typedef - // instead of any local lookup result. This handles the case where the local - // typedef has the same name as the interface typedef (e.g., `typedef if0.rq_t - // rq_t;`) - UINFO(9, indent() << "iface capture binding via captured typedef fallback name=" - << nodep->name() << " typedef=" << capturedTypedefp); - nodep->typedefp(capturedTypedefp); - nodep->classOrPackagep(capturedTypedefSymp ? capturedTypedefSymp->classOrPackagep() - : nullptr); - resolvedCapturedTypedef = true; - } - if (!resolvedCapturedTypedef && foundp) { - VSymEnt* const parentSymp = foundp->parentp(); - UINFO(9, indent() << "iface capture resolved typedef name=" << nodep->name() - << " foundNode=" << foundp->nodep() << " parentNode=" - << (parentSymp ? parentSymp->nodep() : nullptr)); - } - if (!resolvedCapturedTypedef) { + { if (AstTypedef* const defp = foundp ? VN_CAST(foundp->nodep(), Typedef) : nullptr) { // Don't check if typedef is to a :: as might not be @@ -5705,24 +5717,29 @@ class LinkDotResolveVisitor final : public VNVisitor { checkDeclOrder(nodep, defp); nodep->typedefp(defp); nodep->classOrPackagep(foundp->classOrPackagep()); - resolvedCapturedTypedef = true; - // class capture: capture typedef references inside parameterized classes // Only capture if we're referencing from OUTSIDE the class (not // self-references) - if (m_statep->forPrimary()) { + if (V3LinkDotIfaceCapture::enabled() && m_statep->forPrimary()) { AstClass* const classp = VN_CAST(nodep->classOrPackagep(), Class); if (classp && classp->hasGParam() && classp != m_modp) { - UINFO(9, indent() - << "class capture add typedef name=" << nodep->name() - << " class=" << classp->name() << " typedef=" << defp); + UINFO(9, indent() << "class capture add typedef name=" + << nodep->prettyNameQ() << " class=" + << classp->prettyNameQ() << " typedef=" << defp); V3LinkDotIfaceCapture::addClass(nodep, classp, m_modp, defp); } } } else if (AstParamTypeDType* const defp = foundp ? VN_CAST(foundp->nodep(), ParamTypeDType) : nullptr) { - if (defp == nodep->backp()) { // Where backp is typically typedef + // A PARAMTYPEDTYPE's child REFDTYPE referencing itself is the normal + // AST structure for type parameters (e.g., "type T = base" has a child + // REFDTYPE for the default type). Only error on true recursion where + // a TYPEDEF contains a reference back to itself. + const bool isParamTypeChild = (defp == nodep->backp()); + const bool isTypedefRecursion + = isParamTypeChild && VN_IS(defp->backp(), Typedef); + if (isTypedefRecursion) { nodep->v3error("Reference to '" << m_ds.m_dotText << (m_ds.m_dotText == "" ? "" : ".") << nodep->prettyName() << "'" @@ -5731,7 +5748,7 @@ class LinkDotResolveVisitor final : public VNVisitor { } else { nodep->refDTypep(defp); nodep->classOrPackagep(foundp->classOrPackagep()); - resolvedCapturedTypedef = true; + captureIfaceParamType(nodep, defp, capEntryp); } } else if (AstClass* const defp = foundp ? VN_CAST(foundp->nodep(), Class) : nullptr) { @@ -5743,8 +5760,6 @@ class LinkDotResolveVisitor final : public VNVisitor { AstClassRefDType* const newp = new AstClassRefDType{nodep->fileline(), defp, paramsp}; newp->classOrPackagep(foundp->classOrPackagep()); - resolvedCapturedTypedef = true; - retireCapture("resolved"); // Must retire before replacing node nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); return; @@ -5760,12 +5775,6 @@ class LinkDotResolveVisitor final : public VNVisitor { } } } - if (forcedIfaceDotScope && m_ds.m_dotPos == DP_SCOPE && !m_ds.m_dotp) { - UINFO(9, indent() << "iface capture reset dot state after captured typedef name=" - << nodep->name()); - m_ds.init(m_curSymp); - } - if (ifaceCaptured && resolvedCapturedTypedef) { retireCapture("resolved"); } iterateChildren(nodep); } void visit(AstRequireDType* nodep) override { @@ -5927,12 +5936,10 @@ public: : m_statep{statep} { UINFO(4, __FUNCTION__ << ": "); - if (m_statep->forParamed()) { - V3LinkDotIfaceCapture::forEach( - [](const V3LinkDotIfaceCapture::CapturedIfaceTypedef& entry) { - if (AstRefDType* const refp = entry.refp) refp->user3(false); - }); - } + // Note: no need to clear user3 on ledger entries here. + // VNUser3InUse (m_inuser3) already logically clears user3 on all + // nodes via the generation counter. The ledger may also hold stale + // refp pointers to deleted AST nodes, so iterating it is unsafe. iterate(rootp); std::map modulesToRevisit = std::move(m_modulesToRevisit); diff --git a/src/V3LinkDotIfaceCapture.cpp b/src/V3LinkDotIfaceCapture.cpp index 9c6a6bad0..24e98721b 100644 --- a/src/V3LinkDotIfaceCapture.cpp +++ b/src/V3LinkDotIfaceCapture.cpp @@ -1,6 +1,6 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* -// DESCRIPTION: Verilator: +// DESCRIPTION: Verilator: Interface typedef capture helper // // Code available from: https://verilator.org // @@ -14,176 +14,580 @@ // //************************************************************************* +// ARCHITECTURE - Separation of Concerns (do not change without reading): +// +// The IfaceCapture system has three phases with strict responsibilities: +// +// 1. CAPTURE (V3LinkDot, primary pass): +// add() / addParamType() / addTypedef() record template entries. +// Template entries store the REFDTYPE, its cellPath, and the +// original paramTypep / typedefp from the template module. +// Template entries have cloneCellPath = "". +// +// 2. CLONE REGISTRATION (V3Param, deepCloneModule): +// propagateClone() creates clone entries in the ledger. +// ** LEDGER-ONLY - no target lookup, no AST mutation. ** +// At this point the cloned module's cells still reference template +// interface modules (cell->modp() is stale). Any attempt to walk +// cellPath here finds the wrong module. Clone entries store the +// cloned REFDTYPE and cloneCellPath but clear paramTypep/typedefp +// so that stale template pointers are never carried forward. +// +// 3. TARGET RESOLUTION (finalizeIfaceCapture, after V3Param): +// Runs after all cloning is complete and cell pointers are wired +// to the correct interface clones. For each entry, walks cellPath +// starting from the entry's owner module (using findOwnerModule(refp) +// for clone entries) to find the correct target module, then locates +// the PARAMTYPEDTYPE / TYPEDEF by name and applies it to the REFDTYPE. +// ** This is the ONLY place that resolves targets and mutates AST. ** +// +// KEY INVARIANT: The path {ownerModName, refName, cellPath, cloneCellPath} +// is the sole identity. No clonep(), no pointer matching. The path IS +// the disambiguation. +// +// Template entries have cloneCellPath = ""; clone entries get it set by +// propagateClone. TemplateKey (ownerModName, refName, cellPath) matches +// all entries regardless of cloneCellPath - used for propagation and debug. +// + #include "V3LinkDotIfaceCapture.h" #include "V3Error.h" #include "V3Global.h" +#include "V3Stats.h" +#include "V3SymTable.h" + +#include +#include VL_DEFINE_DEBUG_FUNCTIONS; V3LinkDotIfaceCapture::CapturedMap V3LinkDotIfaceCapture::s_map{}; - bool V3LinkDotIfaceCapture::s_enabled = true; +// LCOV_EXCL_START +void V3LinkDotIfaceCapture::enable(bool flag) { + s_enabled = flag; + if (!flag) { + s_map.clear(); + clearModuleCache(); + } +} +// LCOV_EXCL_STOP + +void V3LinkDotIfaceCapture::reset() { + s_map.clear(); + clearModuleCache(); +} + +// Per-module cache of statement-level names to avoid O(N*M) linear scans. +// Lazily built on first access for a given module; cleared at phase boundaries. +// Uses vectors per name to handle rare cases where different node types share a name +// (e.g. a Typedef and a ParamTypeDType both named 'sc_tag_status_t'). +namespace { +struct StmtNameMap final { + std::unordered_map> m_byName; + std::unordered_map> m_byPrettyName; +}; +std::unordered_map s_moduleCache; + +const StmtNameMap& getOrBuild(AstNodeModule* modp) { + auto it = s_moduleCache.find(modp); + if (it != s_moduleCache.end()) return it->second; + StmtNameMap& cache = s_moduleCache[modp]; + for (AstNode* stmtp = modp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + const string& nm = stmtp->name(); + if (!nm.empty()) cache.m_byName[nm].push_back(stmtp); + if (AstNodeDType* const dtp = VN_CAST(stmtp, NodeDType)) { + const string pn = dtp->prettyName(); + if (!pn.empty()) cache.m_byPrettyName[pn].push_back(dtp); + } + } + return cache; +} +} // namespace + +void V3LinkDotIfaceCapture::clearModuleCache() { s_moduleCache.clear(); } + +AstIfaceRefDType* V3LinkDotIfaceCapture::ifaceRefFromVarDType(AstNodeDType* dtypep) { + AstIfaceRefDType* resultp = nullptr; + for (AstNodeDType* curp = dtypep; curp;) { + if (AstIfaceRefDType* const irefp = VN_CAST(curp, IfaceRefDType)) { + resultp = irefp; + break; + } else if (AstBracketArrayDType* const bracketp = VN_CAST(curp, BracketArrayDType)) { + curp = bracketp->subDTypep(); + } else if (AstUnpackArrayDType* const unpackp = VN_CAST(curp, UnpackArrayDType)) { + curp = unpackp->subDTypep(); + } else { + v3fatalSrc("ifaceRefFromVarDType: unexpected dtype " << curp->prettyTypeName() + << " in chain"); + } + } + return resultp; +} + +namespace { +// Resolve the owner module name for a typedef/paramType node. +// Returns hint if non-empty, otherwise walks backp() to find the owner module name. +string resolveOwnerName(const string& hint, AstNode* nodep) { + if (!hint.empty()) return hint; + if (!nodep) return ""; + AstNodeModule* const ownerp = V3LinkDotIfaceCapture::findOwnerModule(nodep); + return ownerp ? ownerp->name() : string{}; +} +} // namespace + +AstTypedef* V3LinkDotIfaceCapture::findTypedefInModule(AstNodeModule* modp, const string& name) { + const StmtNameMap& cache = getOrBuild(modp); + const auto it = cache.m_byName.find(name); + if (it == cache.m_byName.end()) return nullptr; + for (AstNode* nodep : it->second) { + if (AstTypedef* const tdp = VN_CAST(nodep, Typedef)) return tdp; + } + // Cache has entry for this name but no Typedef - unexpected. + v3fatalSrc("findTypedefInModule: name '" << name << "' found in " << modp->prettyNameQ() + << " but no Typedef node"); + return nullptr; // LCOV_EXCL_LINE +} +AstNodeDType* V3LinkDotIfaceCapture::findDTypeInModule(AstNodeModule* modp, const string& name, + VNType type) { + const StmtNameMap& cache = getOrBuild(modp); + const auto it = cache.m_byName.find(name); + if (it == cache.m_byName.end()) return nullptr; + for (AstNode* nodep : it->second) { + if (AstNodeDType* const dtp = VN_CAST(nodep, NodeDType)) { + if (dtp->type() == type) return dtp; + } + } + // Cache has entry for this name but no matching DType - unexpected. + v3fatalSrc("findDTypeInModule: name '" << name << "' found in " << modp->prettyNameQ() + << " but no matching DType"); + return nullptr; // LCOV_EXCL_LINE +} +AstParamTypeDType* V3LinkDotIfaceCapture::findParamTypeInModule(AstNodeModule* modp, + const string& name) { + const StmtNameMap& cache = getOrBuild(modp); + const auto it = cache.m_byName.find(name); + if (it == cache.m_byName.end()) return nullptr; + for (AstNode* nodep : it->second) { + if (AstParamTypeDType* const ptdp = VN_CAST(nodep, ParamTypeDType)) return ptdp; + } + return nullptr; +} + +AstNodeDType* V3LinkDotIfaceCapture::findDTypeByPrettyName(AstNodeModule* modp, + const string& prettyName) { + const StmtNameMap& cache = getOrBuild(modp); + const auto it = cache.m_byPrettyName.find(prettyName); + if (it == cache.m_byPrettyName.end()) return nullptr; + return it->second.front(); +} + +AstNodeModule* V3LinkDotIfaceCapture::findCloneViaHierarchy(AstNodeModule* containingModp, + AstNodeModule* deadTargetModp, + int depth) { + if (depth > 20) return nullptr; // Safety limit + for (AstNode* stmtp = containingModp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (AstCell* const cellp = VN_CAST(stmtp, Cell)) { + AstNodeModule* const cellModp = cellp->modp(); + if (!cellModp || cellModp->dead()) continue; + // Check if cellModp is a clone of deadTargetModp by comparing + // the template name (part before "__") + const string& cellModName = cellModp->name(); + const string& deadName = deadTargetModp->name(); + const size_t pos = cellModName.find("__"); + if (pos != string::npos && cellModName.substr(0, pos) == deadName) { return cellModp; } + // Recurse into sub-cells + AstNodeModule* const found + = findCloneViaHierarchy(cellModp, deadTargetModp, depth + 1); + if (found) return found; + } + } + return nullptr; +} + +int V3LinkDotIfaceCapture::fixDeadRefs(AstRefDType* refp, AstNodeModule* containingModp, + const char* location) { + int fixed = 0; + + // Fix typedefp pointing to dead module + if (refp->typedefp()) { + AstNodeModule* const typedefModp = findOwnerModule(refp->typedefp()); + if (typedefModp && typedefModp->dead()) { + AstNodeModule* cloneModp = nullptr; + if (containingModp) { cloneModp = findCloneViaHierarchy(containingModp, typedefModp); } + if (cloneModp) { + const string& tdName = refp->typedefp()->name(); + if (AstTypedef* const newTdp = findTypedefInModule(cloneModp, tdName)) { + UINFO(9, "iface capture finalizeCapture (" + << location << "): fixing typedefp refp=" << refp << " dead=" + << typedefModp->name() << " -> " << cloneModp->name()); + refp->typedefp(newTdp); + ++fixed; + } + } + } + } + + // Fix refDTypep pointing to dead module + if (refp->refDTypep()) { + AstNodeModule* const targetModp = findOwnerModule(refp->refDTypep()); + if (targetModp && targetModp->dead()) { + AstNodeModule* cloneModp = nullptr; + if (containingModp) { cloneModp = findCloneViaHierarchy(containingModp, targetModp); } + bool foundByName = false; + if (cloneModp) { + const string& targetName = refp->refDTypep()->prettyName(); + if (AstNodeDType* const newDtp = findDTypeByPrettyName(cloneModp, targetName)) { + UINFO(9, "iface capture finalizeCapture (" + << location << "): fixing refDTypep refp=" << refp + << " dead=" << targetModp->name() << " -> " << cloneModp->name()); + refp->refDTypep(newDtp); + ++fixed; + foundByName = true; + } + } + // If name-based search failed, try to derive refDTypep from + // the already-fixed typedefp chain. The typedefp was fixed + // above to point to the clone's typedef, so its subDTypep() + // returns a live dtype (type-table entry or clone-owned). + // This avoids setting refDTypep to nullptr which would force + // V3Width to re-walk the dtype tree under TYPETABLE where + // module provenance is lost, triggering spurious warnings. + if (!foundByName) { + AstNodeDType* derivedp = nullptr; + if (refp->typedefp() && refp->typedefp()->subDTypep()) { + derivedp = refp->typedefp()->subDTypep(); + AstNodeModule* const derivedOwnerp = findOwnerModule(derivedp); + if (derivedOwnerp && derivedOwnerp->dead()) { derivedp = nullptr; } + } + UINFO(9, "iface capture finalizeCapture (" + << location << "): deriving refDTypep from typedefp refp=" << refp + << " dead=" << targetModp->name() << " derived=" << derivedp); + refp->refDTypep(derivedp); + ++fixed; + } + } + } + + // Fix base-class dtypep() - V3Broken checks this pointer, and V3Width + // may have set it to a node in the dead template module. Derive from + // the (already fixed) typedefp chain when possible. + if (refp->dtypep()) { + AstNodeModule* const dtOwnerp = findOwnerModule(refp->dtypep()); + if (dtOwnerp && dtOwnerp->dead()) { + AstNodeDType* newDtp = nullptr; + // Derive from the fixed typedef's subDTypep. This always succeeds + // because the typedefp was fixed above to point to a clone's typedef + // whose subDTypep is a live type-table entry or clone-owned dtype. + // If this fires, either typedefp was not fixed or subDTypep is stale. + // Dump refp->typedefp() and dtOwnerp to diagnose. + if (refp->typedefp() && refp->typedefp()->subDTypep()) { + newDtp = refp->typedefp()->subDTypep(); + AstNodeModule* const newDtOwnerp = findOwnerModule(newDtp); + if (newDtOwnerp && newDtOwnerp->dead()) newDtp = nullptr; + } + UASSERT_OBJ(newDtp, refp, + "fixDeadRefs dtypep: could not derive live dtypep for " + << refp->prettyNameQ() << " dead owner=" << dtOwnerp->name() + << " typedefp=" + << (refp->typedefp() ? refp->typedefp()->name() : "")); + UINFO(9, "iface capture finalizeCapture (" + << location << "): fixing dtypep refp=" << refp + << " dead=" << dtOwnerp->name() << " -> " << newDtp); + refp->dtypep(newDtp); + ++fixed; + } + } + + return fixed; +} + +AstNodeModule* V3LinkDotIfaceCapture::findLiveCloneOf(AstNodeModule* deadTargetModp, + AstNodeModule** containerp) { + for (AstNode* np = v3Global.rootp()->modulesp(); np; np = np->nextp()) { + if (AstNodeModule* const modp = VN_CAST(np, NodeModule)) { + if (modp->dead()) continue; + AstNodeModule* const found = findCloneViaHierarchy(modp, deadTargetModp); + if (found) { + if (containerp) *containerp = modp; + return found; + } + } + } + if (containerp) *containerp = nullptr; + return nullptr; +} + AstNodeModule* V3LinkDotIfaceCapture::findOwnerModule(AstNode* nodep) { for (AstNode* curp = nodep; curp; curp = curp->backp()) { + // Guard against corrupted backp() chains (e.g. freed memory, + // low addresses like 0x1) from nodes unlinked by linkDotParamed. + if (reinterpret_cast(curp) < 0x1000) return nullptr; if (AstNodeModule* const modp = VN_CAST(curp, NodeModule)) return modp; } return nullptr; } -bool V3LinkDotIfaceCapture::finalizeCapturedEntry(CapturedMap::iterator it, const char* reasonp) { - CapturedIfaceTypedef& entry = it->second; - AstRefDType* const pendingRefp = entry.pendingClonep; - AstTypedef* const reboundTypedefp = entry.typedefp; - if (!pendingRefp || !reboundTypedefp) return false; - if (entry.cellp) pendingRefp->user2p(entry.cellp); - pendingRefp->user3(false); - pendingRefp->typedefp(reboundTypedefp); - entry.pendingClonep = nullptr; - return true; +void V3LinkDotIfaceCapture::purgeStaleRefs() { + if (!s_enabled || s_map.empty() || !v3Global.rootp()) return; + // Collect every live AstNode* in the AST so we can detect stale pointers + // in the ledger (refp, ownerModp, typedefp, paramTypep, etc.). + std::unordered_set liveNodes; + v3Global.rootp()->foreach([&](AstNode* np) { liveNodes.insert(np); }); + for (auto& kv : s_map) { + kv.second.foreachLink([&](AstNode*& nodep) { + if (nodep && !liveNodes.count(nodep)) nodep = nullptr; + }); + } +} + +void V3LinkDotIfaceCapture::dumpEntries(const string& label) { + UINFO(9, "========== iface capture dumpEntries: " << label << " (entries=" << s_map.size() + << ") =========="); + int idx = 0; + for (const auto& pair : s_map) { + const CaptureKey& key = pair.first; + const CapturedEntry& entry = pair.second; + const char* captType = (entry.captureType == CaptureType::IFACE) ? "IFACE" : "CLASS"; + UINFO(9, + " [" << idx << "] " << captType << " key={" << key.ownerModName << "," + << key.refName << "," << key.cellPath << "," << key.cloneCellPath << "}" + << " ref=" << (entry.refp ? entry.refp->name() : "") + << " refp=" << cvtToHex(entry.refp) << " cellPath='" << entry.cellPath << "'" + << " ownerMod=" << (entry.ownerModp ? entry.ownerModp->name() : "") + << " typedefp=" << (entry.typedefp ? entry.typedefp->name() : "") + << " typedefOwnerModName='" << entry.typedefOwnerModName << "'" + << " paramTypep=" << (entry.paramTypep ? entry.paramTypep->name() : "") + << " ifacePortVarp=" + << (entry.ifacePortVarp ? entry.ifacePortVarp->name() : "")); + ++idx; + } + UINFO(9, "========== end iface capture dumpEntries =========="); } string V3LinkDotIfaceCapture::extractIfacePortName(const string& dotText) { string name = dotText; const size_t dotPos = name.find('.'); - if (dotPos != string::npos) name.resize(dotPos); + if (dotPos != string::npos) name = name.substr(0, dotPos); const size_t braPos = name.find("__BRA__"); - if (braPos != string::npos) name.resize(braPos); + if (braPos != string::npos) name = name.substr(0, braPos); return name; } -void V3LinkDotIfaceCapture::add(AstRefDType* refp, AstCell* cellp, AstNodeModule* ownerModp, - AstTypedef* typedefp, AstNodeModule* typedefOwnerModp, - AstVar* ifacePortVarp) { - // TODO -- probably classes too - if (!refp || cellp->modp() == ownerModp) return; +void V3LinkDotIfaceCapture::add(AstRefDType* refp, const string& cellPath, + AstNodeModule* ownerModp, AstTypedef* typedefp, + const string& typedefOwnerModName, AstVar* ifacePortVarp) { + UASSERT(refp, "add() called with null refp"); + UASSERT(ownerModp, "add() called with null ownerModp for refp=" << refp->prettyNameQ()); if (!typedefp) typedefp = refp->typedefp(); - if (!typedefOwnerModp && typedefp) typedefOwnerModp = findOwnerModule(typedefp); - s_map[refp] = CapturedIfaceTypedef{ - CaptureType::IFACE, refp, cellp, nullptr, ownerModp, typedefp, - typedefOwnerModp, nullptr, ifacePortVarp}; + const string tdOwnerName = resolveOwnerName(typedefOwnerModName, typedefp); + const string ownerModName = ownerModp->name(); + const CaptureKey key{ownerModName, refp->name(), cellPath, ""}; + auto it = s_map.find(key); + if (it != s_map.end()) { + // Key already exists - append this refp as an extra + it->second.extraRefps.push_back(refp); + UINFO(9, "iface capture add (extra): refp=" + << refp->name() << " cellPath='" << cellPath << "'" << " ownerMod=" + << ownerModName << " extraRefps.size=" << it->second.extraRefps.size()); + } else { + s_map[key] = CapturedEntry{ + CaptureType::IFACE, refp, cellPath, + /*cloneCellPath=*/"", + /*origClassp=*/nullptr, ownerModp, typedefp, nullptr, tdOwnerName, ifacePortVarp, {}}; + UINFO(9, "iface capture add: refp=" << refp->name() << " cellPath='" << cellPath << "'" + << " ownerMod=" << ownerModName << " typedefp=" + << (typedefp ? typedefp->name() : "") + << " typedefOwnerModName='" << tdOwnerName << "'"); + } } void V3LinkDotIfaceCapture::addClass(AstRefDType* refp, AstClass* origClassp, AstNodeModule* ownerModp, AstTypedef* typedefp, - AstNodeModule* typedefOwnerModp) { - if (!refp) return; + const string& typedefOwnerModName) { + UASSERT(refp, "addClass() called with null refp"); + UASSERT(ownerModp, "addClass() called with null ownerModp"); if (!typedefp) typedefp = refp->typedefp(); - if (!typedefOwnerModp && typedefp) typedefOwnerModp = findOwnerModule(typedefp); - s_map[refp] = CapturedIfaceTypedef{CaptureType::CLASS, refp, nullptr, - origClassp, ownerModp, typedefp, - typedefOwnerModp, nullptr, nullptr}; + const string tdOwnerName = resolveOwnerName(typedefOwnerModName, typedefp); + // For CLASS captures, use the class name as cellPath + UASSERT_OBJ(origClassp, refp, "addClass() called with null origClassp for refp=" << refp); + const string cellPath = origClassp->name(); + UASSERT_OBJ(!cellPath.empty(), origClassp, "addClass() produced empty cellPath"); + const string ownerModName = ownerModp->name(); + const CaptureKey key{ownerModName, refp->name(), cellPath, ""}; + s_map[key] = CapturedEntry{CaptureType::CLASS, refp, cellPath, + /*cloneCellPath=*/"", origClassp, ownerModp, typedefp, nullptr, + tdOwnerName, nullptr, {}}; + UINFO(9, "iface capture addClass: refp=" << refp->name() << " cellPath='" << cellPath << "'" + << " ownerMod=" + << (ownerModp ? ownerModp->name() : "")); } -const V3LinkDotIfaceCapture::CapturedIfaceTypedef* -V3LinkDotIfaceCapture::find(const AstRefDType* refp) { - if (!refp) return nullptr; - const auto it = s_map.find(refp); +// Not called in production - retained as a diagnostic/debug entry point +// for inspecting the capture ledger by key (e.g. from GDB or future code). +const V3LinkDotIfaceCapture::CapturedEntry* // LCOV_EXCL_START +V3LinkDotIfaceCapture::find(const CaptureKey& key) { + const auto it = s_map.find(key); if (VL_UNLIKELY(it == s_map.end())) return nullptr; return &it->second; +} // LCOV_EXCL_STOP + +const V3LinkDotIfaceCapture::CapturedEntry* V3LinkDotIfaceCapture::find(const AstRefDType* refp) { + if (!refp) return nullptr; + for (const auto& kv : s_map) { + if (kv.second.refp == refp) return &kv.second; + } + return nullptr; } -bool V3LinkDotIfaceCapture::erase(const AstRefDType* refp) { - if (!refp) return false; - const auto it = s_map.find(refp); - if (it == s_map.end()) return false; - s_map.erase(it); - return true; -} - -bool V3LinkDotIfaceCapture::replaceRef(const AstRefDType* oldRefp, AstRefDType* newRefp) { - if (!oldRefp || !newRefp) return false; - const auto it = s_map.find(oldRefp); - if (it == s_map.end()) return false; - auto entry = it->second; - entry.refp = newRefp; - s_map.erase(it); - s_map.emplace(newRefp, entry); - return true; -} - -bool V3LinkDotIfaceCapture::replaceTypedef(const AstRefDType* refp, AstTypedef* newTypedefp) { - if (!refp || !newTypedefp) return false; - auto it = s_map.find(refp); - if (it == s_map.end()) return false; - it->second.typedefp = newTypedefp; - it->second.typedefOwnerModp = findOwnerModule(newTypedefp); - - // For CLASS captures, update the RefDType node directly - if (it->second.captureType == CaptureType::CLASS && it->second.refp) { - it->second.refp->typedefp(newTypedefp); - // Also update classOrPackagep to point to the specialized class - if (AstClass* const newClassp = VN_CAST(it->second.typedefOwnerModp, Class)) { - it->second.refp->classOrPackagep(newClassp); +// Walk a dot-separated cell path through the cell / IFACEREFDTYPE hierarchy +// starting from startModp. Returns the module at the end of the path, or +// nullptr if any component cannot be resolved. +// Cell/port names are preserved across clones by cloneTree, so this works +// identically on template and cloned modules. +AstNodeModule* V3LinkDotIfaceCapture::followCellPath(AstNodeModule* startModp, + const string& cellPath) { + if (cellPath.empty() || !startModp) return nullptr; + AstNodeModule* curModp = startModp; + string remaining = cellPath; + while (!remaining.empty() && curModp) { + string component; + const size_t dotPos = remaining.find('.'); + if (dotPos == string::npos) { + component = remaining; + remaining.clear(); + } else { + component = remaining.substr(0, dotPos); + remaining = remaining.substr(dotPos + 1); } - UINFO(9, "class capture updated RefDType typedefp: " << it->second.refp << " -> " - << newTypedefp); + const size_t braPos = component.find("__BRA__"); + const string componentBase + = (braPos == string::npos) ? component : component.substr(0, braPos); + AstNodeModule* nextModp = nullptr; + for (AstNode* sp = curModp->stmtsp(); sp; sp = sp->nextp()) { + if (AstCell* const cellp = VN_CAST(sp, Cell)) { + if ((cellp->name() == component || cellp->name() == componentBase) + && cellp->modp()) { + nextModp = cellp->modp(); + break; + } + } + if (AstVar* const varp = VN_CAST(sp, Var)) { + if (varp->isIfaceRef() && varp->subDTypep()) { + string varBaseName = varp->name(); + const size_t viftopPos = varBaseName.find("__Viftop"); + if (viftopPos != string::npos) { + varBaseName = varBaseName.substr(0, viftopPos); + } + if (varBaseName == component || varBaseName == componentBase) { + if (AstIfaceRefDType* const irefp + = ifaceRefFromVarDType(varp->subDTypep())) { + AstIface* const ifacep = irefp->ifaceViaCellp(); + if (ifacep) { + nextModp = ifacep; + break; + } + } + } + } + } + } + curModp = nextModp; } - - finalizeCapturedEntry(it, "typedef clone"); - return true; + return curModp; } -void V3LinkDotIfaceCapture::propagateClone(const AstRefDType* origRefp, AstRefDType* newRefp) { - if (!origRefp || !newRefp) return; - const auto it = s_map.find(origRefp); - UASSERT_OBJ(it != s_map.end(), origRefp, - "iface capture propagateClone missing entry for orig=" << cvtToStr(origRefp)); - CapturedIfaceTypedef& entry = it->second; +// Phase 2: CLONE REGISTRATION - ledger only. +// Called from V3Param::deepCloneModule. At this point the cloned module's +// cells still reference template interface modules (cell->modp() is stale), +// so we MUST NOT walk cellPath or resolve targets here. We only record the +// clone entry. Target resolution happens in finalizeIfaceCapture (Phase 3) +// after all cell pointers are wired to the correct interface clones. +// See header ARCHITECTURE comment for the full picture. +void V3LinkDotIfaceCapture::propagateClone(const TemplateKey& tkey, AstRefDType* newRefp, + const string& cloneCellPath) { + UASSERT(newRefp, "propagateClone() called with null newRefp"); + // Find the template entry by exact key. The entry was captured during + // the primary LinkDot pass, so it must exist. If this fires, either the + // capture was missed or the key components (ownerModName, refName, + // cellPath) diverged between capture and clone time. + const CaptureKey templateKey{tkey.ownerModName, tkey.refName, tkey.cellPath, ""}; + auto it = s_map.find(templateKey); + UASSERT(it != s_map.end(), "propagateClone: no template entry for tkey={" + << tkey.ownerModName << "," << tkey.refName << "," + << tkey.cellPath << "} cloneCellPath='" << cloneCellPath + << "'"); - if (entry.cellp) newRefp->user2p(entry.cellp); - newRefp->user3(false); - entry.pendingClonep = newRefp; + // Create a new clone entry - ledger only. + // Target resolution (paramTypep/typedefp) happens in finalizeIfaceCapture + // where cell pointers are already wired to the correct interface clones. + CapturedEntry newEntry = it->second; + newEntry.refp = newRefp; + newEntry.cellPath = tkey.cellPath; + newEntry.cloneCellPath = cloneCellPath; + newEntry.clearStaleRefs(); + const CaptureKey newKey{tkey.ownerModName, tkey.refName, tkey.cellPath, cloneCellPath}; + s_map[newKey] = newEntry; - // If replaceTypedef was already called (interface cloned before module), - // entry.typedefp will differ from the original RefDType's typedef. - // In that case, finalize now with the updated typedef. - if (entry.typedefp && origRefp->typedefp() && entry.typedefp != origRefp->typedefp()) { - finalizeCapturedEntry(it, "ref clone"); - } + UINFO(9, "propagateClone: tkey={" << tkey.ownerModName << "," << tkey.refName << "," + << tkey.cellPath << "} refp=" << newRefp->name() + << " cloneCellPath='" << cloneCellPath << "'"); } -template -void V3LinkDotIfaceCapture::forEachImpl(FilterFn&& filter, Fn&& fn) { - std::vector keys; +template +void V3LinkDotIfaceCapture::forEachImpl(T_FilterFn&& filter, T_Fn&& fn) { + if (s_map.empty()) return; + std::vector keys; keys.reserve(s_map.size()); for (const auto& kv : s_map) keys.push_back(kv.first); - for (const AstRefDType* key : keys) { + for (const CaptureKey& key : keys) { const auto it = s_map.find(key); if (it == s_map.end()) continue; - - CapturedIfaceTypedef& entry = it->second; - if (entry.cellp && entry.refp && entry.refp->user2p() != entry.cellp) { - entry.refp->user2p(entry.cellp); - } + CapturedEntry& entry = it->second; if (!filter(entry)) continue; fn(entry); } } -void V3LinkDotIfaceCapture::forEach(const std::function& fn) { - if (!fn) return; - forEachImpl([](const CapturedIfaceTypedef&) { return true; }, fn); +void V3LinkDotIfaceCapture::forEach(const std::function& fn) { + if (!fn || s_map.empty()) return; + forEachImpl([](const CapturedEntry&) { return true; }, fn); } -void V3LinkDotIfaceCapture::forEachOwned( - const AstNodeModule* ownerModp, const std::function& fn) { - if (!ownerModp || !fn) return; +void V3LinkDotIfaceCapture::forEachOwned(const AstNodeModule* ownerModp, + const std::function& fn) { + if (!ownerModp || !fn || s_map.empty()) return; + const string ownerName = ownerModp->name(); + UINFO(9, + "iface capture forEachOwned: ownerModp=" << ownerName << " map size=" << s_map.size()); forEachImpl( - [ownerModp](const CapturedIfaceTypedef& e) { - return e.ownerModp == ownerModp || e.typedefOwnerModp == ownerModp; + [ownerModp, &ownerName](const CapturedEntry& e) { + // Only match template entries (cloneCellPath=''). + // Clone entries are created by propagateClone and must not be + // re-processed - each clone gets its own target independently. + if (!e.cloneCellPath.empty()) return false; + // Match by ownerModp pointer or typedefOwnerModName string + const bool matches = e.ownerModp == ownerModp || e.typedefOwnerModName == ownerName; + UINFO(9, "iface capture forEachOwned filter: ref=" + << (e.refp ? e.refp->name() : "") << " cellPath='" << e.cellPath + << "' ownerMod=" << (e.ownerModp ? e.ownerModp->name() : "") + << " typedefOwnerModName='" << e.typedefOwnerModName + << "' matches=" << matches); + return matches; }, fn); } // replaces the lambda used in V3LinkDot.cpp for iface capture -void V3LinkDotIfaceCapture::captureTypedefContext( - AstRefDType* refp, const char* stageLabel, int dotPos, bool dotIsFinal, - const std::string& dotText, VSymEnt* dotSymp, VSymEnt* curSymp, AstNodeModule* modp, - AstNode* nodep, const std::function& promoteVarCb, - const std::function& indentFn) { +void V3LinkDotIfaceCapture::captureTypedefContext(AstRefDType* refp, const char* stageLabel, + int dotPos, bool /*dotIsFinal*/, + const std::string& dotText, VSymEnt* dotSymp, + VSymEnt* curSymp, AstNodeModule* modp, + AstNode* /*nodep*/, + const std::function& indentFn) { if (!enabled() || !refp) return; UINFO(9, indentFn() << "iface capture capture request stage=" << stageLabel @@ -200,41 +604,439 @@ void V3LinkDotIfaceCapture::captureTypedefContext( << " (no iface context)"); return; } + // Skip internal interface typedef references (typedef used within its own interface) + if (ifaceCellp->modp() == modp) { + UINFO(9, indentFn() << "iface capture capture skipped typedef=" << refp + << " (internal to interface " << modp->name() << ")"); + return; + } + + // dotText is always non-empty for interface typedef captures. If this + // fires, the caller resolved to an interface Cell but did not accumulate + // a dotText path - investigate the dot-state in visitParseRef. + UASSERT_OBJ(!dotText.empty(), refp, "captureTypedefContext: dotText empty"); + const string cellPath = dotText; AstVar* ifacePortVarp = nullptr; - if (!dotText.empty() && curSymp) { + if (curSymp) { const std::string portName = extractIfacePortName(dotText); - if (const VSymEnt* const portSymp = curSymp->findIdFallback(portName)) { + if (VSymEnt* const portSymp = curSymp->findIdFallback(portName)) { ifacePortVarp = VN_CAST(portSymp->nodep(), Var); UINFO(9, indentFn() << "iface capture found port var '" << portName << "' -> " << ifacePortVarp); } } - refp->user2p(const_cast(ifaceCellp)); - V3LinkDotIfaceCapture::add(refp, const_cast(ifaceCellp), modp, refp->typedefp(), - nullptr, ifacePortVarp); + // Check if refDTypep is a ParamTypeDType - if so, use addParamType instead of add + if (AstParamTypeDType* const paramTypep = VN_CAST(refp->refDTypep(), ParamTypeDType)) { + V3LinkDotIfaceCapture::addParamType(refp, cellPath, modp, paramTypep, "", ifacePortVarp); + } else { + V3LinkDotIfaceCapture::add(refp, cellPath, modp, refp->typedefp(), "", ifacePortVarp); + } UINFO(9, indentFn() << "iface capture capture success typedef=" << refp - << " cell=" << ifaceCellp + << " cell=" << ifaceCellp << " cellPath='" << cellPath << "'" << " mod=" << (ifaceCellp->modp() ? ifaceCellp->modp()->name() : "") << " dotPos=" << dotPos); - if (!dotIsFinal) return; - - AstVar* enclosingVarp = nullptr; - for (AstNode* curp = nodep; curp; curp = curp->backp()) { - if (AstVar* const varp = VN_CAST(curp, Var)) { - enclosingVarp = varp; - break; - } - if (VN_IS(curp, ParamTypeDType)) break; - if (VN_IS(curp, NodeModule)) break; - } - if (!enclosingVarp || enclosingVarp->user3SetOnce()) return; - UINFO(9, indentFn() << "iface capture typedef owner var=" << enclosingVarp - << " name=" << enclosingVarp->prettyName()); - - if (promoteVarCb && promoteVarCb(enclosingVarp, refp)) return; - UINFO(9, indentFn() << "iface capture failed to convert owner var name=" - << enclosingVarp->prettyName()); + // Note: the enclosingVar walk + promoteVarToParamType callback was removed. + // It supported 'localparam xyz_t = iface.rq_t;' without the 'type' keyword, + // which was never valid SystemVerilog. CI-CD with v3fatalSrc asserts on + // the promoteVarCb path and replaceRef confirmed this was dead code. +} + +void V3LinkDotIfaceCapture::captureInnerParamTypeRefs(AstParamTypeDType* paramTypep, + AstRefDType* refp, const string& cellPath, + const string& ownerModName, + const string& ptOwnerName) { + if (!paramTypep) return; + paramTypep->foreach([&](AstRefDType* innerRefp) { + if (innerRefp == refp) return; + if (!innerRefp->refDTypep()) return; + + AstNodeModule* const refOwnerModp = findOwnerModule(innerRefp->refDTypep()); + if (refOwnerModp && VN_IS(refOwnerModp, Iface) && refOwnerModp->name() != ptOwnerName) { + AstNodeModule* const innerOwnerModp = findOwnerModule(innerRefp); + const string innerOwnerName = innerOwnerModp ? innerOwnerModp->name() : ownerModName; + const CaptureKey innerKey{innerOwnerName, innerRefp->name(), cellPath, ""}; + if (s_map.find(innerKey) == s_map.end()) { + // Find the cell name for the nested interface + string nestedCellName; + AstNodeModule* const ptOwnerModp = findOwnerModule(paramTypep); + if (ptOwnerModp) { + for (AstNode* stmtp = ptOwnerModp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + if (AstCell* const cp = VN_CAST(stmtp, Cell)) { + if (cp->modp() == refOwnerModp) { + nestedCellName = cp->name(); + break; + } + } + } + } + if (VL_UNCOVERABLE(nestedCellName.empty())) { + // The nested interface cell should always be found in the + // owner module's statements. If this fires, either + // ptOwnerModp is wrong (findOwnerModule returned the wrong + // module) or the cell was pruned before capture. + v3fatalSrc("captureInnerParamTypeRefs: could not find cell for nested iface '" + << refOwnerModp->prettyNameQ() << "' in '" + << (ptOwnerModp ? ptOwnerModp->prettyNameQ() : "") << "'"); + } + UINFO(9, "addParamType: also capturing inner RefDType " + << innerRefp << " refDTypep owner=" << refOwnerModp->name() + << " nestedCellName='" << nestedCellName << "'"); + s_map[innerKey] = CapturedEntry{CaptureType::IFACE, + innerRefp, + nestedCellName.empty() ? cellPath : nestedCellName, + /*cloneCellPath=*/"", + /*origClassp=*/nullptr, + ptOwnerModp, + innerRefp->typedefp(), + nullptr, + refOwnerModp->name(), + nullptr, + {}}; + } + } + }); +} + +void V3LinkDotIfaceCapture::addParamType(AstRefDType* refp, const string& cellPath, + AstNodeModule* ownerModp, AstParamTypeDType* paramTypep, + const string& paramTypeOwnerModName, + AstVar* ifacePortVarp) { + UASSERT(refp, "addParamType() called with null refp"); + UASSERT(ownerModp, + "addParamType() called with null ownerModp for refp='" << refp->prettyNameQ() << "'"); + UASSERT_OBJ(paramTypep, refp, + "addParamType() called with null paramTypep for refp='" << refp->prettyNameQ() + << "'"); + const string ptOwnerName = resolveOwnerName(paramTypeOwnerModName, paramTypep); + UINFO(9, "addParamType: refp=" << refp << " cellPath='" << cellPath << "'" + << " ownerModp=" << (ownerModp ? ownerModp->name() : "") + << " paramTypep=" << paramTypep << " paramTypeOwnerModName='" + << ptOwnerName << "'"); + if (paramTypep) { + UINFO(9, "addParamType: paramTypep subDTypep chain:"); + paramTypep->foreach([&](AstRefDType* innerRefp) { + UINFO(9, + " inner RefDType: " + << innerRefp << " refDTypep=" << innerRefp->refDTypep() + << (innerRefp->refDTypep() ? " refDTypep->name=" : "") + << (innerRefp->refDTypep() ? innerRefp->refDTypep()->prettyTypeName() : "")); + }); + } + const string ownerModName = ownerModp->name(); + const CaptureKey key{ownerModName, refp->name(), cellPath, ""}; + auto it = s_map.find(key); + if (it != s_map.end()) { + // Key already exists - append this refp as an extra + it->second.extraRefps.push_back(refp); + UINFO(9, "addParamType (extra): refp=" + << refp->name() << " cellPath='" << cellPath << "'" << " ownerMod=" + << ownerModName << " extraRefps.size=" << it->second.extraRefps.size()); + } else { + s_map[key] + = CapturedEntry{CaptureType::IFACE, refp, cellPath, + /*cloneCellPath=*/"", + /*origClassp=*/nullptr, ownerModp, nullptr, paramTypep, ptOwnerName, + ifacePortVarp, {}}; + } + + // Also capture REFDTYPEs inside the PARAMTYPEDTYPE's subDTypep chain. + captureInnerParamTypeRefs(paramTypep, refp, cellPath, ownerModName, ptOwnerName); +} + +// Visitor that fixes dead references in the global type table. +// +// When interface templates are cloned, REFDTYPEs in the global type table may +// still point to the dead template module. This visitor traverses the type +// table and redirects those references to the appropriate live clone. +// +// Handles both AstRefDType (direct typedef references) and AstMemberDType +// (struct/union member types) in a single traversal for efficiency. +class TypeTableDeadRefVisitor final : public VNVisitor { + int m_fixed = 0; + + void visit(AstRefDType* refp) override { + iterateChildren(refp); + // For type table entries, find the first live module that contains + // a cell hierarchy leading to the dead target + AstNodeModule* containingModp = nullptr; + AstNodeModule* deadTargetModp = nullptr; + // Check BOTH typedefp and refDTypep for dead owners. + // Either (or both) may point to a dead module. + if (refp->typedefp()) { + AstNodeModule* const tdOwnerp + = V3LinkDotIfaceCapture::findOwnerModule(refp->typedefp()); + if (tdOwnerp && tdOwnerp->dead()) deadTargetModp = tdOwnerp; + } + if (!deadTargetModp && refp->refDTypep()) { + AstNodeModule* const rdOwnerp + = V3LinkDotIfaceCapture::findOwnerModule(refp->refDTypep()); + if (rdOwnerp && rdOwnerp->dead()) deadTargetModp = rdOwnerp; + } + if (deadTargetModp) { + V3LinkDotIfaceCapture::findLiveCloneOf(deadTargetModp, &containingModp); + } + m_fixed += V3LinkDotIfaceCapture::fixDeadRefs(refp, containingModp, "type table"); + } + + void visit(AstMemberDType* memberp) override { + iterateChildren(memberp); + if (!memberp->dtypep()) return; + AstNodeModule* const dtOwnerp = V3LinkDotIfaceCapture::findOwnerModule(memberp->dtypep()); + if (!dtOwnerp || !dtOwnerp->dead()) return; + // Try to find the clone of the dead module + AstNodeModule* const cloneModp = V3LinkDotIfaceCapture::findLiveCloneOf(dtOwnerp); + if (cloneModp) { + // Find matching type by name in the clone + const string& dtName = memberp->dtypep()->prettyName(); + // Try typedef children + for (AstNode* sp = cloneModp->stmtsp(); sp; sp = sp->nextp()) { + if (AstTypedef* const tdp = VN_CAST(sp, Typedef)) { + if (tdp->subDTypep() && tdp->subDTypep()->prettyName() == dtName) { + UINFO(9, "iface capture type table MEMBERDTYPE fixup (via typedef): " + << memberp->name() << " dtypep " << dtOwnerp->name() << " -> " + << cloneModp->name()); + memberp->dtypep(tdp->subDTypep()); + ++m_fixed; + return; + } + } + } + } + // One of the above fixup paths (prettyName or typedef) always succeeds + // when cloneModp is found. If this fires, either cloneModp is null + // (findLiveCloneOf failed - check that the dead template has a clone) + // or the dtype name doesn't match any statement in the clone (check + // memberp->dtypep()->prettyName() against cloneModp's statements). + v3fatalSrc("MemberDType fixup: could not fix member '" + << memberp->name() << "' dtypep points to dead " << dtOwnerp->name() + << " cloneModp=" << (cloneModp ? cloneModp->name() : "")); + } + + void visit(AstNode* nodep) override { iterateChildren(nodep); } + +public: + int fixed() const { return m_fixed; } + explicit TypeTableDeadRefVisitor(AstNode* nodep) { iterate(nodep); } +}; + +int V3LinkDotIfaceCapture::fixDeadRefsInTypeTable() { + if (!v3Global.rootp()->typeTablep()) return 0; + TypeTableDeadRefVisitor visitor{v3Global.rootp()->typeTablep()}; + return visitor.fixed(); +} + +int V3LinkDotIfaceCapture::fixDeadRefsInModules() { + int fixed = 0; + for (AstNode* nodep = v3Global.rootp()->modulesp(); nodep; nodep = nodep->nextp()) { + if (AstNodeModule* const modp = VN_CAST(nodep, NodeModule)) { + if (modp->dead()) continue; + const string modName = modp->name(); + modp->foreach( + [&](AstRefDType* refp) { fixed += fixDeadRefs(refp, modp, modName.c_str()); }); + } + } + return fixed; +} + +int V3LinkDotIfaceCapture::fixWrongCloneRefs() { + int fixed = 0; + + // TARGET RESOLUTION - the ONLY place that resolves targets and + // mutates AST. By this point all cloning is complete and cell pointers + // are wired to the correct interface clones. For each entry we walk + // cellPath from the owner module to find the correct target module, then + // locate the PARAMTYPEDTYPE / TYPEDEF by name. + // See V3LinkDotIfaceCapture.h ARCHITECTURE comment for the full picture. + + forEach([&](const CapturedEntry& entry) { + AstRefDType* const refp = entry.refp; + if (!refp) return; + // For clone entries the stored ownerModp is the template (stale cells). + // Use the actual module containing the REFDTYPE - its cells are wired + // to the correct interface clones by this point. + // findOwnerModule handles corrupted backp() chains gracefully. + AstNodeModule* const ownerModp + = !entry.cloneCellPath.empty() ? findOwnerModule(refp) : entry.ownerModp; + if (!ownerModp || ownerModp->dead() || VN_IS(ownerModp, Package)) return; + + AstNodeModule* const rdOwnerBefore + = (refp->refDTypep() ? findOwnerModule(refp->refDTypep()) : nullptr); + UINFO(9, + "finalizeIfaceCapture Phase3 entry: refp=" + << refp->name() << " (" << cvtToHex(refp) << ")" + << " ownerMod=" << ownerModp->name() << " (dead=" << ownerModp->dead() << ")" + << " storedOwnerMod=" << (entry.ownerModp ? entry.ownerModp->name() : "") + << " cellPath='" << entry.cellPath << "' cloneCellPath='" << entry.cloneCellPath + << "' typedefp=" << (refp->typedefp() ? refp->typedefp()->name() : "") + << " refDTypep=" << (refp->refDTypep() ? refp->refDTypep()->name() : "") + << " refDTypepOwner=" << (rdOwnerBefore ? rdOwnerBefore->name() : "") + << " refDTypepDead=" << (rdOwnerBefore ? rdOwnerBefore->dead() : 0)); + + // Determine the correct target module using cellPath + AstNodeModule* correctModp = nullptr; + if (!entry.cellPath.empty()) { + correctModp = followCellPath(ownerModp, entry.cellPath); + UINFO(9, " followCellPath('" + << ownerModp->name() << "', '" << entry.cellPath + << "') = " << (correctModp ? correctModp->name() : "") + << (correctModp ? (correctModp->dead() ? " (DEAD)" : " (live)") : "")); + if (correctModp && correctModp->dead()) { correctModp = nullptr; } + } + + // Proactive target resolution: when cellPath resolved to a valid + // correctModp, find the PARAMTYPEDTYPE or TYPEDEF by name and apply. + if (correctModp) { + const string& refName = refp->name(); + bool resolved = false; + if (AstParamTypeDType* const ptdp = findParamTypeInModule(correctModp, refName)) { + refp->refDTypep(ptdp); + refp->user3(true); + resolved = true; + UINFO(9, "finalizeIfaceCapture Phase3: resolved paramTypep '" + << refName << "' in " << correctModp->name() << " for refp in " + << ownerModp->name() << " cloneCellPath='" << entry.cloneCellPath + << "'"); + } else if (AstTypedef* const tdp = findTypedefInModule(correctModp, refName)) { + refp->typedefp(tdp); + refp->user3(true); + resolved = true; + UINFO(9, "finalizeIfaceCapture Phase3: resolved typedefp '" + << refName << "' in " << correctModp->name() << " for refp in " + << ownerModp->name() << " cloneCellPath='" << entry.cloneCellPath + << "'"); + } + if (resolved) { + ++fixed; + return; + } + } + + // Note: the structural disambiguation infrastructure (collectReachable, + // findCorrectClone, wrong-clone fixup blocks) was removed. All captured + // entries have non-empty cellPath, and disambiguateTarget always returns + // nullptr through the "cellPath unresolved" path. The wrong-clone fixup + // blocks were dead code - CI-CD with v3fatalSrc asserts confirmed this. + // Unresolved entries are fixed by fixDeadRefs in a later phase. + }); + + return fixed; +} + +void V3LinkDotIfaceCapture::verifyNoDeadRefs() { + // Assert: no REFDTYPE in any live module should have typedefp or refDTypep + // pointing to a dead module. + for (AstNode* nodep = v3Global.rootp()->modulesp(); nodep; nodep = nodep->nextp()) { + if (AstNodeModule* const modp = VN_CAST(nodep, NodeModule)) { + if (modp->dead()) continue; + modp->foreach([&](AstRefDType* refp) { + if (refp->typedefp()) { + AstNodeModule* const ownerModp = findOwnerModule(refp->typedefp()); + // Diagnostic block: only entered when fixup logic has a bug + // and leaves a typedefp pointing to a dead module. + if (ownerModp && ownerModp->dead()) { // LCOV_EXCL_START + bool inLedger = false; + forEach([&](const CapturedEntry& e) { + if (e.refp == refp) inLedger = true; + }); + UINFO(9, "VERIFY FAIL typedefp: refp=" + << refp->name() << " (" << cvtToHex(refp) << ")" << " in mod=" + << modp->name() << " typedefp->owner=" << ownerModp->name() + << " inLedger=" << inLedger); + } // LCOV_EXCL_STOP + UASSERT_OBJ(!ownerModp || !ownerModp->dead(), refp, // LCOV_EXCL_LINE + "REFDTYPE '" << refp->prettyNameQ() << "' in live module '" + << modp->prettyNameQ() + << "' has typedefp pointing to dead module '" + << ownerModp->prettyNameQ() << "'"); + } + if (refp->refDTypep()) { + AstNodeModule* const ownerModp = findOwnerModule(refp->refDTypep()); + // Diagnostic block: only entered when fixup logic has a bug + // and leaves a refDTypep pointing to a dead module. + if (ownerModp && ownerModp->dead()) { // LCOV_EXCL_START + bool inLedger = false; + forEach([&](const CapturedEntry& e) { + if (e.refp == refp) inLedger = true; + }); + UINFO(9, "VERIFY FAIL refDTypep: refp=" + << refp->name() << " (" << cvtToHex(refp) << ")" << " in mod=" + << modp->name() << " refDTypep->owner=" << ownerModp->name() + << " inLedger=" << inLedger); + } // LCOV_EXCL_STOP + UASSERT_OBJ(!ownerModp || !ownerModp->dead(), refp, // LCOV_EXCL_LINE + "REFDTYPE '" << refp->prettyNameQ() << "' in live module '" + << modp->prettyNameQ() + << "' has refDTypep pointing to dead module '" + << ownerModp->prettyNameQ() << "'"); + } + }); + } + } + if (v3Global.rootp()->typeTablep()) { + for (AstNode* nodep = v3Global.rootp()->typeTablep()->typesp(); nodep; + nodep = nodep->nextp()) { + nodep->foreach([&](AstRefDType* refp) { + if (refp->typedefp()) { + AstNodeModule* const ownerModp = findOwnerModule(refp->typedefp()); + // Bug-only assertion: fires only if fixup logic fails to + // resolve a type-table typedefp away from a dead module. + UASSERT_OBJ(!ownerModp || !ownerModp->dead(), refp, // LCOV_EXCL_LINE + "REFDTYPE '" + << refp->prettyNameQ() + << "' in type table has typedefp pointing to dead module '" + << ownerModp->prettyNameQ() << "'"); + } + if (refp->refDTypep()) { + AstNodeModule* const ownerModp = findOwnerModule(refp->refDTypep()); + // Bug-only assertion: fires only if fixup logic fails to + // resolve a type-table refDTypep away from a dead module. + UASSERT_OBJ(!ownerModp || !ownerModp->dead(), refp, // LCOV_EXCL_LINE + "REFDTYPE '" + << refp->prettyNameQ() + << "' in type table has refDTypep pointing to dead module '" + << ownerModp->prettyNameQ() << "'"); + } + }); + } + } +} + +void V3LinkDotIfaceCapture::finalizeIfaceCapture() { + if (!s_enabled) return; + UINFO(4, "finalizeIfaceCapture: fixing remaining cross-interface refs"); + if (!v3Global.rootp()) return; + clearModuleCache(); // Ensure fresh view after all cloning/widthing + + const int typeTableFixed = fixDeadRefsInTypeTable(); + const int moduleFixed = fixDeadRefsInModules(); + UINFO(4, "finalizeIfaceCapture: fixed " << typeTableFixed << " in type table, " << moduleFixed + << " in modules (dead refs)"); + + const int wrongCloneFixed = fixWrongCloneRefs(); + UINFO(4, "finalizeIfaceCapture: fixed " << wrongCloneFixed << " wrong-live-clone pointers"); + + if (debug() >= 9) dumpEntries("after finalizeIfaceCapture"); + + // Emit statistics for --stats + int templates = 0; + int clones = 0; + for (const auto& kv : s_map) { + if (kv.first.cloneCellPath.empty()) { + ++templates; + } else { + ++clones; + } + } + V3Stats::addStat("IfaceCapture, Entries total", s_map.size()); + V3Stats::addStat("IfaceCapture, Entries template", templates); + V3Stats::addStat("IfaceCapture, Entries cloned", clones); + V3Stats::addStat("IfaceCapture, Dead refs fixed in type table", typeTableFixed); + V3Stats::addStat("IfaceCapture, Dead refs fixed in modules", moduleFixed); + V3Stats::addStat("IfaceCapture, Wrong-clone refs fixed", wrongCloneFixed); + + verifyNoDeadRefs(); + reset(); } diff --git a/src/V3LinkDotIfaceCapture.h b/src/V3LinkDotIfaceCapture.h index 7c7f53cce..781e03788 100644 --- a/src/V3LinkDotIfaceCapture.h +++ b/src/V3LinkDotIfaceCapture.h @@ -23,74 +23,183 @@ #include "config_build.h" #include "V3Ast.h" -#include "V3SymTable.h" #include #include +#include #include +#include + +class VSymEnt; class V3LinkDotIfaceCapture final { public: enum class CaptureType { IFACE, CLASS }; - struct CapturedIfaceTypedef final { + + // Path-based map key: no pointers, only stable strings. + // {ownerModName, refName, cellPath, cloneCellPath} uniquely identifies + // every captured REFDTYPE. You cannot have two typedefs with the same + // name in the same module, so this tuple is unique. + struct CaptureKey final { + string ownerModName; // Module containing the REFDTYPE (e.g. "cca_xbar") + string refName; // REFDTYPE name (e.g. "r_chan_t") + string cellPath; // Template path (e.g. "cca_io.tlb_io") + string cloneCellPath; // Instance path (e.g. "xbar1"), empty for template + bool operator==(const CaptureKey& o) const { + return ownerModName == o.ownerModName && refName == o.refName && cellPath == o.cellPath + && cloneCellPath == o.cloneCellPath; + } + }; + struct CaptureKeyHash final { + size_t operator()(const CaptureKey& k) const { + size_t h = std::hash{}(k.ownerModName); + h ^= std::hash{}(k.refName) + 0x9e3779b9 + (h << 6) + (h >> 2); + h ^= std::hash{}(k.cellPath) + 0x9e3779b9 + (h << 6) + (h >> 2); + h ^= std::hash{}(k.cloneCellPath) + 0x9e3779b9 + (h << 6) + (h >> 2); + return h; + } + }; + + // Template key: matches ALL entries regardless of cloneCellPath. + // Used for propagateClone and debug searches. + struct TemplateKey final { + string ownerModName; + string refName; + string cellPath; + }; + + struct CapturedEntry final { CaptureType captureType = CaptureType::IFACE; AstRefDType* refp = nullptr; - AstCell* cellp = nullptr; // now for IFACE captures - AstClass* origClassp = nullptr; // new for CLASS captures + string cellPath; // Template path (e.g. "cca_io.tlb_io") - immutable key component + string cloneCellPath; // Instance-specific path (e.g. "cca_io1.tlb_io") - set by + // propagateClone when V3Param clones; empty for original entries + AstClass* origClassp = nullptr; // For CLASS captures // Module where the RefDType lives AstNodeModule* ownerModp = nullptr; // Typedef definition being referenced AstTypedef* typedefp = nullptr; - // Interface/module that owns typedefp - AstNodeModule* typedefOwnerModp = nullptr; - // Cloned RefDType awaiting typedef rebinding - AstRefDType* pendingClonep = nullptr; + // For PARAMTYPEDTYPE + AstParamTypeDType* paramTypep = nullptr; + // Name of the module/interface that owns the typedef (stable string) + string typedefOwnerModName; // Interface port variable for matching during cloning AstVar* ifacePortVarp = nullptr; + // Additional REFDTYPEs sharing the same key (e.g. from macro expansions + // that produce multiple $bits() references to the same interface typedef). + // The primary refp is stored above; extras are appended here so that + // retargeting fixes ALL of them, not just the last-writer-wins primary. + std::vector extraRefps; + // Clear template-specific targets that are stale in a clone context. + // Called by propagateClone before inserting a clone entry. + void clearStaleRefs() { + paramTypep = nullptr; + typedefp = nullptr; + extraRefps.clear(); + } + // Visit every AstNode* pointer field (analogous to AstNode::foreachLink). + // The callback receives an AstNode* by reference; if it nulls the + // pointer the typed member is nulled accordingly. + template + void foreachLink(T_func&& fn) { + auto callOnNode = [&](auto*& ptr) { + AstNode* np = ptr; + fn(np); + if (!np) ptr = nullptr; + }; + callOnNode(refp); + callOnNode(ownerModp); + callOnNode(typedefp); + callOnNode(paramTypep); + callOnNode(ifacePortVarp); + callOnNode(origClassp); + for (auto& xrefp : extraRefps) callOnNode(xrefp); + } }; - using CapturedMap = std::unordered_map; + using CapturedMap = std::unordered_map; private: + friend class TypeTableDeadRefVisitor; + static CapturedMap s_map; static bool s_enabled; - static AstNodeModule* findOwnerModule(AstNode* nodep); - static bool finalizeCapturedEntry(CapturedMap::iterator it, const char* reasonp); + // --- Internal-only methods (not called outside V3LinkDotIfaceCapture.cpp) --- + static void enable(bool flag); // LCOV_EXCL_LINE + static void reset(); + static void clearModuleCache(); + static AstIfaceRefDType* ifaceRefFromVarDType(AstNodeDType* dtypep); static string extractIfacePortName(const string& dotText); - - template - static void forEachImpl(FilterFn&& filter, Fn&& fn); + static AstNodeDType* findDTypeByPrettyName(AstNodeModule* modp, const string& prettyName); + static AstNodeModule* findCloneViaHierarchy(AstNodeModule* containingModp, + AstNodeModule* deadTargetModp, int depth = 0); + static AstNodeModule* findLiveCloneOf(AstNodeModule* deadTargetModp, + AstNodeModule** containerp = nullptr); + static int fixDeadRefs(AstRefDType* refp, AstNodeModule* containingModp, const char* location); + static void captureInnerParamTypeRefs(AstParamTypeDType* paramTypep, AstRefDType* refp, + const string& cellPath, const string& ownerModName, + const string& ptOwnerName); + static int fixDeadRefsInTypeTable(); + static int fixDeadRefsInModules(); + static int fixWrongCloneRefs(); + static void verifyNoDeadRefs(); + template + static void forEachImpl(T_FilterFn&& filter, T_Fn&& fn); public: - static void enable(bool flag) { - s_enabled = flag; - if (!flag) s_map.clear(); - } static bool enabled() { return s_enabled; } - static void reset() { s_map.clear(); } - static void add(AstRefDType* refp, AstCell* cellp, AstNodeModule* ownerModp, - AstTypedef* typedefp = nullptr, AstNodeModule* typedefOwnerModp = nullptr, + static AstNodeModule* findOwnerModule(AstNode* nodep); + // Find a Typedef by name in a module's top-level statements + static AstTypedef* findTypedefInModule(AstNodeModule* modp, const string& name); + // Find a NodeDType by name and VNType in a module's top-level statements + static AstNodeDType* findDTypeInModule(AstNodeModule* modp, const string& name, VNType type); + // Find a ParamTypeDType by name in a module's top-level statements + static AstParamTypeDType* findParamTypeInModule(AstNodeModule* modp, const string& name); + static void add(AstRefDType* refp, const string& cellPath, AstNodeModule* ownerModp, + AstTypedef* typedefp = nullptr, const string& typedefOwnerModName = "", AstVar* ifacePortVarp = nullptr); static void addClass(AstRefDType* refp, AstClass* origClassp, AstNodeModule* ownerModp, - AstTypedef* typedefp = nullptr, - AstNodeModule* typedefOwnerModp = nullptr); - static const CapturedIfaceTypedef* find(const AstRefDType* refp); - static void forEach(const std::function& fn); + AstTypedef* typedefp = nullptr, const string& typedefOwnerModName = ""); + static void addParamType(AstRefDType* refp, const string& cellPath, AstNodeModule* ownerModp, + AstParamTypeDType* paramTypep, const string& paramTypeOwnerModName, + AstVar* ifacePortVarp); + // Exact lookup by full key + static const CapturedEntry* find(const CaptureKey& key); + // Pointer-based lookup: linear scan with early exit (no std::function overhead) + static const CapturedEntry* find(const AstRefDType* refp); + static void forEach(const std::function& fn); static void forEachOwned(const AstNodeModule* ownerModp, - const std::function& fn); - static bool replaceRef(const AstRefDType* oldRefp, AstRefDType* newRefp); - static bool replaceTypedef(const AstRefDType* refp, AstTypedef* newTypedefp); - static bool erase(const AstRefDType* refp); + const std::function& fn); static std::size_t size() { return s_map.size(); } - static void propagateClone(const AstRefDType* origRefp, AstRefDType* newRefp); - static void - captureTypedefContext(AstRefDType* refp, const char* stageLabel, int dotPos, bool dotIsFinal, - const std::string& dotText, VSymEnt* dotSymp, VSymEnt* curSymp, - AstNodeModule* modp, AstNode* nodep, - const std::function& promoteVarCb, - const std::function& indentFn); + // Walk a dot-separated cell path (e.g. "cca_io.tlb_io") starting from + // startModp, returning the module at the end of the path. Returns + // nullptr if any component cannot be resolved. + static AstNodeModule* followCellPath(AstNodeModule* startModp, const string& cellPath); + + // Create a new clone entry in the ledger, inheriting from the template. + // Ledger-only: no target lookup or AST mutation. Target resolution + // happens later in finalizeIfaceCapture where cell pointers are wired up. + static void propagateClone(const TemplateKey& tkey, AstRefDType* newRefp, + const string& cloneCellPath); + + static void captureTypedefContext(AstRefDType* refp, const char* stageLabel, int dotPos, + bool dotIsFinal, const std::string& dotText, + VSymEnt* dotSymp, VSymEnt* curSymp, AstNodeModule* modp, + AstNode* nodep, + const std::function& indentFn); + + // Null out ledger refp entries that point to freed nodes (not in the live AST). + // Called once after V3Param completes, before any code touches the ledger. + static void purgeStaleRefs(); + + // Debug: dump all captured entries + static void dumpEntries(const string& label); + + // Called after V3Param but before V3Dead to fix any remaining cross-interface refs + // that still point to template nodes (which will be deleted by V3Dead). + static void finalizeIfaceCapture(); }; #endif // VERILATOR_V3LINKDOTIFACECAPTURE_H_ diff --git a/src/V3Param.cpp b/src/V3Param.cpp index aeddbbeb4..9787f13d1 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -67,6 +67,7 @@ #include #include #include +#include #include VL_DEFINE_DEBUG_FUNCTIONS; @@ -375,6 +376,39 @@ class ParamProcessor final { key += ","; } key += "}"; + } else if (const AstClassRefDType* const classRefp = VN_CAST(nodep, ClassRefDType)) { + // For parameterized class types, use the original class name (without specialization + // suffix) plus the actual type parameter values. This ensures equivalent class types + // get the same string representation regardless of which AST node is used. + if (classRefp->classp()) { + const string& className = classRefp->classp()->name(); + const string& origName = classRefp->classp()->origName(); + const bool isSpecialized = (className != origName); + UINFO(9, "paramValueString ClassRefDType: name=" + << className << " origName=" << origName + << " isSpecialized=" << isSpecialized + << " hasParams=" << (classRefp->paramsp() ? "Y" : "N") + << " classHasGParam=" << classRefp->classp()->hasGParam() << endl); + + if (classRefp->paramsp()) { + // ClassRefDType should have been deparameterized (paramsp + // consumed) before cellPinCleanup calls paramValueString. + classRefp->v3fatalSrc( // LCOV_EXCL_LINE + "ClassRefDType still has paramsp in paramValueString"); + } else if (isSpecialized) { + // Already specialized class (e.g., c1__Tz1_TBz1) - use full name + // This ensures different specializations are distinguished + key = className; + } else { + // Unspecialized class with no params - use origName + key = origName; + } + } else { + // classp() should always be set; unresolved class refs + // would have errored in LinkDot. + classRefp->v3fatalSrc( // LCOV_EXCL_LINE + "ClassRefDType has null classp in paramValueString"); + } } else if (const AstNodeDType* const dtypep = VN_CAST(nodep, NodeDType)) { key += dtypep->prettyDTypeName(true); } @@ -383,13 +417,24 @@ class ParamProcessor final { } string paramValueNumber(AstNode* nodep) { - // TODO: This parameter value number lookup via a constructed key string is not - // particularly robust for type parameters. We should really have a type - // equivalence predicate function. - if (AstRefDType* const refp = VN_CAST(nodep, RefDType)) nodep = refp->skipRefToNonRefp(); + // For type parameters (NodeDType), use only the string representation for hashing. + // Using V3Hasher::uncachedHash includes AST node pointer which differs for equivalent + // types represented by different AST nodes (e.g., parameterized class specializations). + // For value parameters, we can still use the AST hash for better collision resistance. + // All call sites resolve through skipRefToNonRefp() or pass non-DType + // nodes, so nodep should never be a bare RefDType here. + if (VN_IS(nodep, RefDType)) { // LCOV_EXCL_LINE + nodep->v3fatalSrc("Unexpected RefDType in paramValueNumber"); // LCOV_EXCL_LINE + } const string paramStr = paramValueString(nodep); - // cppcheck-suppress unreadVariable - V3Hash hash = V3Hasher::uncachedHash(nodep) + paramStr; + V3Hash hash; + if (VN_IS(nodep, NodeDType)) { + // Type parameter: use only string-based hash for type equivalence + hash = V3Hash{paramStr}; + } else { + // Value parameter: use AST hash + string for better collision resistance + hash = V3Hasher::uncachedHash(nodep) + paramStr; + } // Force hash collisions -- for testing only // cppcheck-suppress unreadVariable if (VL_UNLIKELY(v3Global.opt.debugCollision())) hash = V3Hash{paramStr}; @@ -535,7 +580,7 @@ class ParamProcessor final { // Using map with key=string so that we can scan it in deterministic order DefaultValueMap params; for (AstNode* stmtp = modp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { - if (const AstVar* const varp = VN_CAST(stmtp, Var)) { + if (AstVar* const varp = VN_CAST(stmtp, Var)) { if (varp->isGParam()) { AstConst* const constp = VN_CAST(varp->valuep(), Const); // constp can be nullptr if the parameter is not used to instantiate sub @@ -544,7 +589,8 @@ class ParamProcessor final { params.emplace(varp->name(), constp); } } else if (AstParamTypeDType* const p = VN_CAST(stmtp, ParamTypeDType)) { - params.emplace(p->name(), p->skipRefp()); + AstNode* const dtypep = static_cast(p->skipRefp()); + params.emplace(p->name(), dtypep); } } pair.first->second = std::move(params); @@ -608,6 +654,30 @@ class ParamProcessor final { } else if (AstClassOrPackageRef* const classRefp = VN_CAST(nodep, ClassOrPackageRef)) { if (classRefp->classOrPackageSkipp() == oldClassp) classRefp->classOrPackagep(newClassp); + } else if (AstTypedef* const typedefp = VN_CAST(nodep, Typedef)) { + // Update typedefs that refer to the old class to point to the new class + if (typedefp->subDTypep()) { + if (AstClassRefDType* const classRefp + = VN_CAST(typedefp->subDTypep(), ClassRefDType)) { + if (classRefp->classp() == oldClassp) { classRefp->classp(newClassp); } + } + } + } else if (AstNodeFTaskRef* const ftaskRefp = VN_CAST(nodep, NodeFTaskRef)) { + // Also update FuncRef/TaskRef packagep to point to new class + // This fixes static method calls through typedefs in parameterized classes + if (ftaskRefp->classOrPackagep() == oldClassp) ftaskRefp->classOrPackagep(newClassp); + // Also update taskp if it points to a function in the old class. + // AstNodeFTask::classOrPackagep() (op2) holds a parse-time + // Dot/ClassOrPackageRef for extern declarations, which is deleted + // in LinkDot::moveExternFuncDecl before V3Param runs. For inline + // class methods op2 is nullptr. So this should never match. + if (AstNodeFTask* const oldTaskp = ftaskRefp->taskp()) { + if (oldTaskp->classOrPackagep() == oldClassp) { + oldTaskp->v3fatalSrc( // LCOV_EXCL_LINE + "FTask classOrPackagep unexpectedly matches old class " + << oldClassp->prettyNameQ()); + } + } } if (nodep->op1p()) replaceRefsRecurse(nodep->op1p(), oldClassp, newClassp); @@ -718,6 +788,154 @@ class ParamProcessor final { void visit(AstNode* nodep) override { iterateChildren(nodep); } }; + // Returns true if entry's cellPath ends with cloneCellp->name() and + // the parent portion of the path resolves (from startModp) to expectModp. + bool cellPathMatchesClone(const string& cellPath, const AstCell* cloneCellp, + AstNodeModule* startModp, const AstNodeModule* expectModp) const { + if (!cloneCellp || cellPath.empty()) return false; + const size_t lastDot = cellPath.rfind('.'); + const string lastComp + = (lastDot == string::npos) ? cellPath : cellPath.substr(lastDot + 1); + const size_t braPos = lastComp.find("__BRA__"); + const string lastCompBase + = (braPos == string::npos) ? lastComp : lastComp.substr(0, braPos); + if (lastComp != cloneCellp->name() && lastCompBase != cloneCellp->name()) return false; + if (lastDot == string::npos) return true; // No parent portion to verify + const string parentPath = cellPath.substr(0, lastDot); + const AstNodeModule* const resolvedp + = V3LinkDotIfaceCapture::followCellPath(startModp, parentPath); + return resolvedp == expectModp; + } + + // Retarget entry.refp (and extraRefps) to the typedef/paramType found + // in targetModp. Returns true if anything was retargeted. + static bool retargetRefToModule(const V3LinkDotIfaceCapture::CapturedEntry& entry, + AstNodeModule* targetModp) { + if (entry.refp->typedefp()) { + if (AstTypedef* const tdp = V3LinkDotIfaceCapture::findTypedefInModule( + targetModp, entry.refp->typedefp()->name())) { + entry.refp->typedefp(tdp); + if (tdp->subDTypep()) { + entry.refp->refDTypep(tdp->subDTypep()); + entry.refp->dtypep(tdp->subDTypep()); + } + for (AstRefDType* const xrefp : entry.extraRefps) { + xrefp->typedefp(tdp); + if (tdp->subDTypep()) { + xrefp->refDTypep(tdp->subDTypep()); + xrefp->dtypep(tdp->subDTypep()); + } + } + return true; + } + } else if (entry.paramTypep) { + if (AstParamTypeDType* const ptp = V3LinkDotIfaceCapture::findParamTypeInModule( + targetModp, entry.paramTypep->name())) { + entry.refp->refDTypep(ptp); + entry.refp->dtypep(ptp); + for (AstRefDType* const xrefp : entry.extraRefps) { + xrefp->refDTypep(ptp); + xrefp->dtypep(ptp); + } + return true; + } + } + return false; + } + + // Fix cross-module REFDTYPE pointers in newModp after cloneTree. + // Phase A: path-based fixup using ledger entries with cellPath. + // Phase B: reachable-set fallback for remaining REFDTYPEs. + void fixupCrossModuleRefDTypes(AstNodeModule* newModp, AstNodeModule* srcModp, + AstNode* ifErrorp, const IfaceRefRefs& ifaceRefRefs) { + if (!V3LinkDotIfaceCapture::enabled()) return; + // Phase A: path-based fixup using ledger entries + std::set ledgerFixed; + { + const string cloneCP = VN_CAST(ifErrorp, Cell) ? VN_AS(ifErrorp, Cell)->name() : ""; + const string srcName = srcModp->name(); + UINFO(9, "iface capture FIXUP-A: srcName=" << srcName << " cloneCP='" << cloneCP << "'" + << endl); + V3LinkDotIfaceCapture::forEach([&](const V3LinkDotIfaceCapture::CapturedEntry& entry) { + if (!entry.refp) return; + if (entry.cloneCellPath != cloneCP) return; + if (!entry.ownerModp || entry.ownerModp->name() != srcName) return; + if (entry.cellPath.empty()) return; + + AstRefDType* const refp = entry.refp; + AstNodeModule* const correctModp + = V3LinkDotIfaceCapture::followCellPath(newModp, entry.cellPath); + UINFO(9, " path fixup: " << refp << " cellPath='" << entry.cellPath << "' -> " + << (correctModp ? correctModp->name() : "") + << endl); + if (!correctModp || correctModp->dead()) return; + + bool fixed = false; + if (refp->typedefp()) { + if (AstTypedef* const newTdp = V3LinkDotIfaceCapture::findTypedefInModule( + correctModp, refp->typedefp()->name())) { + refp->typedefp(newTdp); + fixed = true; + } + } + if (refp->refDTypep()) { + if (AstNodeDType* const newDtp = V3LinkDotIfaceCapture::findDTypeInModule( + correctModp, refp->refDTypep()->name(), refp->refDTypep()->type())) { + refp->refDTypep(newDtp); + fixed = true; + } + } + if (fixed) ledgerFixed.insert(refp); + }); + V3Stats::addStatSum("IfaceCapture, Ledger fixups in V3Param", ledgerFixed.size()); + } + + // Phase B: reachable-set fallback for REFDTYPEs not handled by ledger + std::set reachable; + reachable.insert(newModp); + std::function collectReachable; + collectReachable = [&](AstNodeModule* modp) { + for (AstNode* sp = modp->stmtsp(); sp; sp = sp->nextp()) { + if (AstCell* const cellp = VN_CAST(sp, Cell)) { + AstNodeModule* const cellModp = cellp->modp(); + if (cellModp && reachable.insert(cellModp).second) { + collectReachable(cellModp); + } + } + } + }; + for (const auto& pair : ifaceRefRefs) { + AstIface* const pinIfacep = pair.second->ifaceViaCellp(); + if (pinIfacep && reachable.insert(pinIfacep).second) { collectReachable(pinIfacep); } + } + collectReachable(newModp); + + // Phase B (reachable-set fallback): Phase A (path-based ledger fixup) + // always resolves all statement-level REFDTYPEs for current tests and + // Aerial. Assert if any REFDTYPE slips through so we can investigate. + // The loop body is assert-only (no mutations); LCOV_EXCL because + // Phase A always resolves everything and ledgerFixed catches all refs. + for (AstNode* stmtp = newModp->stmtsp(); stmtp; stmtp = stmtp->nextp()) { + AstRefDType* const refp = VN_CAST(stmtp, RefDType); + if (!refp) continue; + if (ledgerFixed.count(refp)) continue; // LCOV_EXCL_LINE + // LCOV_EXCL_START + // Check if typedefp or refDTypep points outside the reachable set + auto checkNotStale = [&](const char* label, AstNode* targetp) { + AstNodeModule* const ownerp = V3LinkDotIfaceCapture::findOwnerModule(targetp); + if (!ownerp || ownerp == newModp || VN_IS(ownerp, Package) + || reachable.count(ownerp)) + return; // OK: owner is reachable or self + v3fatalSrc("Phase B reachable-set fallback triggered for " + << refp->prettyNameQ() << " " << label << " owner=" + << ownerp->prettyNameQ() << " in " << newModp->prettyNameQ()); + }; + if (refp->typedefp()) checkNotStale("typedefp", refp->typedefp()); + if (refp->refDTypep()) checkNotStale("refDTypep", refp->refDTypep()); + // LCOV_EXCL_STOP + } + } + // Return true on success, false on error bool deepCloneModule(AstNodeModule* srcModp, AstNode* ifErrorp, AstPin* paramsp, const string& newname, const IfaceRefRefs& ifaceRefRefs) { @@ -731,73 +949,83 @@ class ParamProcessor final { newModp = srcModp->cloneTree(false); } + // Mark the source module as a parameterized template now that a specialized + // clone exists. This suppresses width/type errors on the unresolved template + // during widthParamsEdit (which runs before V3LinkDot sets dead()). + srcModp->parameterizedTemplate(true); + // The clone is a specialized instance, not a template. Clear the flag in + // case it was inherited from a prior cloneTree (when srcModp was already + // marked by an earlier specialization). + newModp->parameterizedTemplate(false); + // cloneTree(false) temporarily populates origNode->clonep() for every node under // srcModp. The capture list still stores those orig AstRefDType* pointers, so walking // it lets us follow clonep() into newModp and scrub each clone with the saved // interface context before newModp is re-linked. we have pointers to the same nodes saved // in the capture map, so we can use them to scrub the new module. + if (V3LinkDotIfaceCapture::enabled()) { + AstCell* const cloneCellp = VN_CAST(ifErrorp, Cell); + UINFO(9, "iface capture clone: " << srcModp->prettyNameQ() << " -> " + << newModp->prettyNameQ() << endl); + // First pass: register clone entries and direct-retarget + // REFDTYPEs whose owner won't be cloned later. V3LinkDotIfaceCapture::forEachOwned( - srcModp, [&](const V3LinkDotIfaceCapture::CapturedIfaceTypedef& entry) { + srcModp, [&](const V3LinkDotIfaceCapture::CapturedEntry& entry) { if (!entry.refp) return; - AstTypedef* const origTypedefp = entry.typedefp; - if (!origTypedefp) return; - - // Find the correct typedef from the correct interface clone. - // entry.typedefp points to the original interface's typedef, - // but we need the typedef in the interface clone this module connects to. - AstTypedef* targetTypedefp = nullptr; - const string& typedefName = origTypedefp->name(); - - for (auto it = ifaceRefRefs.cbegin(); it != ifaceRefRefs.cend(); ++it) { - const AstIfaceRefDType* const portIrefp = it->first; - AstNodeModule* const pinIfacep = it->second->ifaceViaCellp(); - if (!pinIfacep) continue; - - // If we have a port variable, match against it - if (entry.ifacePortVarp) { - // Get the IfaceRefDType from the captured port variable - AstNodeDType* const portDTypep = entry.ifacePortVarp->subDTypep(); - AstIfaceRefDType* entryPortIrefp = VN_CAST(portDTypep, IfaceRefDType); - if (!entryPortIrefp && arraySubDTypep(portDTypep)) { - entryPortIrefp - = VN_CAST(arraySubDTypep(portDTypep), IfaceRefDType); - } - if (entryPortIrefp != portIrefp) continue; // Not the right port + UINFO(9, "iface capture entry: " << entry.refp << " cellPath='" + << entry.cellPath << "'" << endl); + // Disambiguate via cellPath when cloning the interface + // that owns the typedef (matched via typedefOwnerModName). + if (cloneCellp && entry.ownerModp != srcModp + && entry.typedefOwnerModName == srcModp->name()) { + UASSERT_OBJ(!entry.cellPath.empty(), entry.refp, + "cellPath is empty in entry matched via typedefOwnerModName"); + if (!cellPathMatchesClone(entry.cellPath, cloneCellp, entry.ownerModp, + m_modp)) { + UINFO(9, "iface capture skipping (path mismatch)" << endl); + return; } - - // Search for typedef with same name in the connected interface clone - for (AstNode* stmtp = pinIfacep->stmtsp(); stmtp; stmtp = stmtp->nextp()) { - if (AstTypedef* const tdp = VN_CAST(stmtp, Typedef)) { - if (tdp->name() == typedefName) { - targetTypedefp = tdp; - UINFO(8, - " [iface-capture] found '" - << typedefName << "' in " << pinIfacep->name() - << " via port " - << (entry.ifacePortVarp ? entry.ifacePortVarp->name() - : "") - << endl); - break; - } - } - } - if (targetTypedefp) break; } - - // Fallback to clone of original typedef (existing behavior) - if (!targetTypedefp) targetTypedefp = origTypedefp->clonep(); - - if (targetTypedefp) { - UINFO(8, " [iface-capture] replaceTypedef " - << origTypedefp->name() << " -> " << targetTypedefp << endl); - V3LinkDotIfaceCapture::replaceTypedef(entry.refp, targetTypedefp); - } - // Propagate to cloned RefDType in new module + // Register clone entry in ledger (no AST mutation). if (AstRefDType* const clonedRefp = entry.refp->clonep()) { - V3LinkDotIfaceCapture::propagateClone(entry.refp, clonedRefp); + const string cloneCP = cloneCellp ? cloneCellp->name() : string{}; + const V3LinkDotIfaceCapture::TemplateKey tkey{ + entry.ownerModp ? entry.ownerModp->name() : "", entry.refp->name(), + entry.cellPath}; + V3LinkDotIfaceCapture::propagateClone(tkey, clonedRefp, cloneCP); + } else if (entry.ownerModp != srcModp) { + // REFDTYPE lives in a parent module; clonep() is null. + AstNodeModule* const actualOwnerp + = V3LinkDotIfaceCapture::findOwnerModule(entry.refp); + if (actualOwnerp && actualOwnerp->hasGParam()) return; + // Owner won't be cloned - directly retarget now. + if (retargetRefToModule(entry, newModp)) { + UINFO(9, "iface capture direct retarget: " << entry.refp << " -> " + << newModp->prettyNameQ() + << endl); + } } }); + + // Second pass: retarget clone entries (non-empty cloneCellPath) + // whose typedef owner matches the module being cloned. + const string srcName = srcModp->name(); + V3LinkDotIfaceCapture::forEach([&](const V3LinkDotIfaceCapture::CapturedEntry& entry) { + if (!entry.refp || entry.cloneCellPath.empty()) return; + if (entry.typedefOwnerModName != srcName) return; + AstNodeModule* const actualOwnerp + = V3LinkDotIfaceCapture::findOwnerModule(entry.refp); + if (!actualOwnerp || actualOwnerp->hasGParam()) return; + if (cloneCellp && !entry.cellPath.empty() + && !cellPathMatchesClone(entry.cellPath, cloneCellp, actualOwnerp, m_modp)) { + return; + } + if (retargetRefToModule(entry, newModp)) { + UINFO(9, "iface capture clone-entry retarget: " + << entry.refp << " -> " << newModp->prettyNameQ() << endl); + } + }); } newModp->name(newname); @@ -877,6 +1105,11 @@ class ParamProcessor final { // to find the correct interface for each VarXRef. if (!ifaceRefRefs.empty()) { VarXRefRelinkVisitor{newModp}; } + // Fix cross-module REFDTYPE pointers in newModp (Phase A path-based + // + Phase B reachable-set fallback). + UASSERT_OBJ(newModp, srcModp, "newModp null before hierarchy fixup"); + fixupCrossModuleRefDTypes(newModp, srcModp, ifErrorp, ifaceRefRefs); + // Assign parameters to the constants specified // DOES clone() so must be finished with module clonep() before here for (AstPin* pinp = paramsp; pinp; pinp = VN_AS(pinp->nextp(), Pin)) { @@ -886,7 +1119,7 @@ class ParamProcessor final { AstConst* const exprp = VN_CAST(newp, Const); AstConst* const origp = VN_CAST(modvarp->valuep(), Const); const bool overridden - = !(origp && ParameterizedHierBlocks::areSame(exprp, origp)); + = !(origp && exprp && ParameterizedHierBlocks::areSame(exprp, origp)); // Remove any existing parameter if (modvarp->valuep()) modvarp->valuep()->unlinkFrBack()->deleteTree(); // Set this parameter to value requested by cell @@ -904,6 +1137,7 @@ class ParamProcessor final { } } } + return true; } const ModInfo* moduleFindOrClone(AstNodeModule* srcModp, AstNode* ifErrorp, AstPin* paramsp, @@ -993,7 +1227,9 @@ class ParamProcessor final { += "_" + paramSmallName(srcModp, modvarp) + paramValueNumber(pinp->exprp()); any_overridesr = true; } else { + UINFO(9, "cellPinCleanup: before constify " << pinp << " " << modvarp); V3Const::constifyParamsEdit(pinp->exprp()); + UINFO(9, "cellPinCleanup: after constify " << pinp); // String constants are parsed as logic arrays and converted to strings in V3Const. // At this moment, some constants may have been already converted. // To correctly compare constants, both should be of the same type, @@ -1005,6 +1241,9 @@ class ParamProcessor final { AstConst* const exprp = VN_CAST(pinp->exprp(), Const); AstConst* const origp = VN_CAST(modvarp->valuep(), Const); if (!exprp) { + // With DepGraph architecture, all expressions should be constants + // by the time V3Param runs. If not, it's an error. + UINFO(9, "cellPinCleanup: NOT CONST after constify " << pinp); UINFOTREE(1, pinp, "", "errnode"); pinp->v3error("Can't convert defparam value to constant: Param " << pinp->prettyNameQ() << " of " << nodep->prettyNameQ()); @@ -1019,6 +1258,7 @@ class ParamProcessor final { // Setting parameter to its default value. Just ignore it. // This prevents making additional modules, and makes coverage more // obvious as it won't show up under a unique module page name. + UINFO(9, "cellPinCleanup: same as default " << pinp); } else if (exprp->num().isDouble() || exprp->num().isString() || exprp->num().isFourState() || exprp->num().width() != 32) { longnamer @@ -1036,9 +1276,37 @@ class ParamProcessor final { resolveDotToTypedef(pinp->exprp()); AstNodeDType* rawTypep = VN_CAST(pinp->exprp(), NodeDType); - if (rawTypep) V3Width::widthParamsEdit(rawTypep); + // Guard against widthing a struct/union still owned by a + // parameterized template interface (not yet specialized). + // widthParamsEdit is destructive: it evaluates range expressions, + // sets didWidth=1, and removes Range nodes, which would corrupt + // the template's BASICDTYPEs for all subsequent clones. + // Triggered by deeply nested parameterized interfaces (e.g. + // outer_if containing inner_if with struct typedefs) when the + // inner interface hasn't been specialized yet. + bool skipWidthForTemplateStruct = false; + { + // Use non-asserting skip: before widthParamsEdit, type(expr) + // constructs may contain unlinked REFDTYPEs (e.g. type(x-y)) + AstNodeDType* const resolvedp = rawTypep ? rawTypep->skipRefOrNullp() : nullptr; + if (resolvedp && (VN_IS(resolvedp, StructDType) || VN_IS(resolvedp, UnionDType))) { + AstNodeModule* const ownerModp + = V3LinkDotIfaceCapture::findOwnerModule(resolvedp); + // Skip if owned by a parameterized template (not yet specialized) + if (ownerModp && ownerModp->parameterizedTemplate()) { + skipWidthForTemplateStruct = true; + V3Stats::addStatSum("Param, Template struct width skips", 1); + UINFO(9, "SKIP-WIDTH-TEMPLATE: struct=" + << resolvedp->prettyTypeName() << " templateOwner=" + << ownerModp->prettyNameQ() << " pin=" << pinp->prettyNameQ() + << " of " << nodep->prettyNameQ() + << " srcMod=" << srcModp->prettyNameQ() << endl); + } + } + if (rawTypep && !skipWidthForTemplateStruct) V3Width::widthParamsEdit(rawTypep); + } AstNodeDType* exprp = rawTypep ? rawTypep->skipRefToNonRefp() : nullptr; - const AstNodeDType* const origp = modvarp->skipRefToNonRefp(); + const AstNodeDType* origp = modvarp->skipRefToNonRefp(); if (!exprp) { pinp->v3error("Parameter type pin value isn't a type: Param " << pinp->prettyNameQ() << " of " << nodep->prettyNameQ()); @@ -1047,10 +1315,12 @@ class ParamProcessor final { << modvarp->prettyNameQ()); } else { UINFO(9, "Parameter type assignment expr=" << exprp << " to " << origp); - V3Const::constifyParamsEdit(pinp->exprp()); // Reconcile typedefs - // Constify may have caused pinp->exprp to change - rawTypep = VN_AS(pinp->exprp(), NodeDType); - exprp = rawTypep->skipRefToNonRefp(); + if (!skipWidthForTemplateStruct) { + V3Const::constifyParamsEdit(pinp->exprp()); // Reconcile typedefs + // Constify may have caused pinp->exprp to change + rawTypep = VN_AS(pinp->exprp(), NodeDType); + exprp = rawTypep->skipRefToNonRefp(); + } if (!modvarp->fwdType().isNodeCompatible(exprp)) { pinp->v3error("Parameter type expression type " << exprp->prettyDTypeNameQ() @@ -1062,9 +1332,11 @@ class ParamProcessor final { // This prevents making additional modules, and makes coverage more // obvious as it won't show up under a unique module page name. } else { - VL_DO_DANGLING(V3Const::constifyParamsEdit(exprp), exprp); - rawTypep = VN_CAST(pinp->exprp(), NodeDType); - exprp = rawTypep ? rawTypep->skipRefToNonRefp() : nullptr; + if (!skipWidthForTemplateStruct) { + VL_DO_DANGLING(V3Const::constifyParamsEdit(exprp), exprp); + rawTypep = VN_CAST(pinp->exprp(), NodeDType); + exprp = rawTypep ? rawTypep->skipRefToNonRefp() : nullptr; + } longnamer += "_" + paramSmallName(srcModp, modvarp) + paramValueNumber(exprp); any_overridesr = true; } @@ -1302,7 +1574,6 @@ class ParamProcessor final { // Returns new or reused module // Make sure constification worked // Must be a separate loop, as constant conversion may have changed some pointers. - // UINFOTREE(1, nodep, "", "cel2"); string longname = srcModp->name() + "_"; if (debug() >= 9 && paramsp) paramsp->dumpTreeAndNext(cout, "- cellparams: "); @@ -1332,6 +1603,9 @@ class ParamProcessor final { } } + UINFO(9, "nodeDeparamCommon: " << srcModp->prettyNameQ() << " overrides=" << any_overrides + << endl); + AstNodeModule* newModp = nullptr; if (m_hierBlocks.hierSubRun() && m_hierBlocks.isHierBlock(srcModp->origName())) { AstNodeModule* const paramedModp @@ -1343,6 +1617,7 @@ class ParamProcessor final { newModp = paramedModp; // any_overrides = true; // Unused later, so not needed } else if (!any_overrides) { + UINFO(9, "nodeDeparamCommon: no overrides, reusing " << srcModp); UINFO(8, "Cell parameters all match original values, skipping expansion."); // If it's the first use of the default instance, create a copy and store it in user3p. // user3p will also be used to check if the default instance is used. @@ -1369,10 +1644,8 @@ class ParamProcessor final { } const bool cloned = (newModp != srcModp); - UINFO(9, "iface capture module clone src=" << srcModp << " new=" << newModp << " name=" - << newModp->name() << " from cell=" << nodep - << " cellName=" << nodep->name() - << " cloned=" << cloned); + UINFO(9, "nodeDeparamCommon result: " << newModp->prettyNameQ() << " cloned=" << cloned + << endl); // Link source class to its specialized version for later relinking of method references if (defaultsResolved) srcModp->user4p(newModp); @@ -1412,6 +1685,56 @@ class ParamProcessor final { return newModp; } AstNodeModule* ifaceRefDeparam(AstIfaceRefDType* const nodep, AstNodeModule* srcModp) { + // Check for self-reference pattern: typedef iface#(T) this_type inside interface iface + // When processing inside a specialized interface, the IfaceRefDType should point to + // the owner interface, not create an intermediate specialization. + if (m_modp && VN_IS(m_modp, Iface)) { + AstIface* ownerIfacep = const_cast(VN_AS(m_modp, Iface)); + const string ownerOrigName + = ownerIfacep->origName().empty() ? ownerIfacep->name() : ownerIfacep->origName(); + const string srcOrigName + = srcModp->origName().empty() ? srcModp->name() : srcModp->origName(); + string ownerBaseName = ownerOrigName; + const size_t ownerPos = ownerBaseName.find("__"); + if (ownerPos != string::npos) ownerBaseName = ownerBaseName.substr(0, ownerPos); + string srcBaseName = srcOrigName; + const size_t srcPos = srcBaseName.find("__"); + if (srcPos != string::npos) srcBaseName = srcBaseName.substr(0, srcPos); + + if (ownerBaseName == srcBaseName) { + bool allOwnParams = true; + for (AstPin* pinp = nodep->paramsp(); pinp && allOwnParams; + pinp = VN_AS(pinp->nextp(), Pin)) { + if (AstRefDType* const refp = VN_CAST(pinp->exprp(), RefDType)) { + if (AstParamTypeDType* const ptdp + = VN_CAST(refp->refDTypep(), ParamTypeDType)) { + AstNodeModule* const ptdOwnerp + = V3LinkDotIfaceCapture::findOwnerModule(ptdp); + if (ptdOwnerp != m_modp) allOwnParams = false; + } else { + pinp->v3error( // LCOV_EXCL_LINE + "Self-referencing interface typedef " + "parameter is not a type parameter of " + "the enclosing interface"); + } + } else { + pinp->v3error( // LCOV_EXCL_LINE + "Self-referencing interface typedef " + "parameter is not a type reference"); + } + } + if (allOwnParams) { + UINFO(5, "ifaceRefDeparam: self-reference pattern detected in " + << ownerIfacep->prettyNameQ() << ", using owner interface" + << endl); + V3Stats::addStatSum("Param, Self-reference iface typedefs", 1); + nodep->ifacep(ownerIfacep); + if (nodep->paramsp()) nodep->paramsp()->unlinkFrBackWithNext()->deleteTree(); + return ownerIfacep; + } + } + } + AstNodeModule* const newModp = nodeDeparamCommon(nodep, srcModp, nodep->paramsp(), nullptr, false); if (!newModp) return nullptr; @@ -1461,13 +1784,35 @@ public: // We always run this, even if no parameters, as need to look for interfaces, // and remove any recursive references UINFO(4, "De-parameterize: " << nodep); + UINFO(9, "nodeDeparam ENTER node=<" + << AstNode::nodeAddr(nodep) << ">" << " type=" << nodep->typeName() + << " srcMod=" << (srcModp ? srcModp->prettyNameQ() : "''") + << " srcSomeInstanceName='" + << (srcModp ? srcModp->someInstanceName() : string("")) << "'" + << " parentMod=" << (modp ? modp->prettyNameQ() : "''") + << " parentSomeInstanceName='" + << (modp ? modp->someInstanceName() : string("")) << "'" + << " inputSomeInstanceName='" << someInstanceName << "'" << endl); // Create new module name with _'s between the constants UINFOTREE(10, nodep, "", "cell"); // Evaluate all module constants V3Const::constifyParamsEdit(nodep); // Set name for warnings for when we param propagate the module - const string instanceName = someInstanceName + "." + nodep->name(); + // For AstIfaceRefDType, name() returns the modport name (often empty), + // so use cellName() which is the actual cell instance name. + // If both are empty (interface port, not a cell), skip appending + // to avoid double-dots in the path. + string nodeName = nodep->name(); + if (AstIfaceRefDType* const ifaceRefp = VN_CAST(nodep, IfaceRefDType)) { + if (nodeName.empty()) nodeName = ifaceRefp->cellName(); + } + const string instanceName + = nodeName.empty() ? someInstanceName : (someInstanceName + "." + nodeName); srcModp->someInstanceName(instanceName); + UINFO(9, "nodeDeparam SET-SRC-INST srcMod=" + << srcModp->prettyNameQ() << " someInstanceName='" + << srcModp->someInstanceName() << "'" << " node=<" << AstNode::nodeAddr(nodep) + << ">" << " nodeType=" << nodep->typeName() << endl); AstNodeModule* newModp = nullptr; if (AstCell* const cellp = VN_CAST(nodep, Cell)) { @@ -1487,6 +1832,15 @@ public: // Set name for later warnings newModp->someInstanceName(instanceName); + UINFO(9, "nodeDeparam EXIT node=<" + << AstNode::nodeAddr(nodep) << ">" << " type=" << nodep->typeName() + << " srcMod=" << (srcModp ? srcModp->prettyNameQ() : "''") + << " srcSomeInstanceName='" + << (srcModp ? srcModp->someInstanceName() : string("")) << "'" + << " newMod=" << (newModp ? newModp->prettyNameQ() : "''") + << " newSomeInstanceName='" + << (newModp ? newModp->someInstanceName() : string("")) << "'" << endl); + UINFO(8, " Done with orig " << nodep); // if (debug() >= 10) // v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("param-out.tree")); @@ -1592,6 +1946,12 @@ class ParamVisitor final : public VNVisitor { // Process once; note user2 will be cleared on specialization, so we will do the // specialized module if needed if (!modp->user2SetOnce()) { + UINFO(9, "processWorkQ module begin mod='" + << modp->name() << "' orig='" << modp->origName() << "'" + << " someInstanceName='" << modp->someInstanceName() << "'" + << " hasGParam=" << (modp->hasGParam() ? "yes" : "no") + << " user3p=" << (modp->user3p() ? "set" : "null") + << " dead=" << (modp->dead() ? "yes" : "no") << endl); // TODO: this really should be an assert, but classes and hier_blocks are // special... @@ -1643,6 +2003,10 @@ class ParamVisitor final : public VNVisitor { if (AstNodeModule* const newModp = m_processor.nodeDeparam(cellp, srcModp, modp, someInstanceName)) { + if (VN_IS(srcModp, Iface)) { + logTemplateLeakRefs(modp, srcModp, "after queued nodeDeparam", cellp); + } + // Add the (now potentially specialized) child module to the work queue workQueue.emplace(newModp->level(), newModp); @@ -1662,18 +2026,105 @@ class ParamVisitor final : public VNVisitor { return dotted.substr(0, dotted.find('.')); } + // Debug-only diagnostic (requires --debugi-V3Param 9). + // Walks parentModp looking for RefDTypes or VarRefs whose typedef, + // refDType, or variable target is still owned by templateModp (the + // unspecialized interface template). Any such "leak" indicates a + // pointer that was not properly redirected to the clone during + // deparameterization. Logs each leak with ancestry for triage. + void logTemplateLeakRefs(AstNodeModule* parentModp, AstNodeModule* templateModp, + const char* stage, AstNode* contextp) { + if (debug() < 9 || !parentModp || !templateModp || !VN_IS(templateModp, Iface)) return; + // LCOV_EXCL_START // Debug-only diagnostic + int leakCount = 0; + const auto ancestryOf = [](const AstNode* nodep) { + string ancestry; + for (const AstNode* curp = nodep; curp; curp = curp->backp()) { + if (!ancestry.empty()) ancestry += "<-"; + ancestry += curp->typeName(); + if (VN_IS(curp, NodeModule) || VN_IS(curp, Netlist) || VN_IS(curp, TypeTable)) { + break; + } + } + return ancestry; + }; + + parentModp->foreach([&](AstRefDType* refp) { + if (refp->typedefp()) { + AstNodeModule* const tdOwnerp + = V3LinkDotIfaceCapture::findOwnerModule(refp->typedefp()); + if (tdOwnerp == templateModp) { + ++leakCount; + UINFO(9, "TEMPLATE-LEAK " + << stage << " parent=" << parentModp->prettyNameQ() + << " template=" << templateModp->prettyNameQ() << " contextType=" + << (contextp ? contextp->typeName() : string("")) + << " contextName=" + << (contextp ? contextp->prettyNameQ() : "''") + << " leak=REFDTYPE typedef owner" << " ref=<" + << AstNode::nodeAddr(refp) << ">" + << " refName=" << refp->prettyNameQ() + << " ancestry=" << ancestryOf(refp) << endl); + } + } + if (refp->refDTypep()) { + AstNodeModule* const rdOwnerp + = V3LinkDotIfaceCapture::findOwnerModule(refp->refDTypep()); + if (rdOwnerp == templateModp) { + ++leakCount; + UINFO(9, "TEMPLATE-LEAK " + << stage << " parent=" << parentModp->prettyNameQ() + << " template=" << templateModp->prettyNameQ() << " contextType=" + << (contextp ? contextp->typeName() : string("")) + << " contextName=" + << (contextp ? contextp->prettyNameQ() : "''") + << " leak=REFDTYPE refDType owner" << " ref=<" + << AstNode::nodeAddr(refp) << ">" + << " refName=" << refp->prettyNameQ() + << " ancestry=" << ancestryOf(refp) << endl); + } + } + }); + + parentModp->foreach([&](AstVarRef* varrefp) { + if (!varrefp->varp()) return; + AstNodeModule* const varOwnerp + = V3LinkDotIfaceCapture::findOwnerModule(varrefp->varp()); + if (varOwnerp != templateModp) return; + ++leakCount; + UINFO(9, "TEMPLATE-LEAK " + << stage << " parent=" << parentModp->prettyNameQ() + << " template=" << templateModp->prettyNameQ() + << " contextType=" << (contextp ? contextp->typeName() : string("")) + << " contextName=" << (contextp ? contextp->prettyNameQ() : "''") + << " leak=VARREF target owner" << " ref=<" << AstNode::nodeAddr(varrefp) + << ">" << " var=" << varrefp->prettyNameQ() + << " ancestry=" << ancestryOf(varrefp) << endl); + }); + + if (leakCount > 0) { + UINFO(9, "TEMPLATE-LEAK summary stage='" + << stage << "' parent=" << parentModp->prettyNameQ() << " template=" + << templateModp->prettyNameQ() << " count=" << leakCount << endl); + } + // LCOV_EXCL_STOP + } + void checkParamNotHier(AstNode* valuep) { if (!valuep) return; valuep->foreachAndNext([&](const AstNodeExpr* exprp) { if (const AstVarXRef* const refp = VN_CAST(exprp, VarXRef)) { // Allow hierarchical ref to interface params through interface/modport ports - bool isIfacePortRef = false; + // or local interface instances + bool isIfaceRef = false; if (refp->varp() && refp->varp()->isIfaceParam()) { const string refname = getRefBaseName(refp); - isIfacePortRef = !refname.empty() && m_ifacePortNames.count(refname); + isIfaceRef + = !refname.empty() + && (m_ifacePortNames.count(refname) || m_ifaceInstNames.count(refname)); } - if (!isIfacePortRef) { + if (!isIfaceRef) { refp->v3warn(HIERPARAM, "Parameter values cannot use hierarchical values" " (IEEE 1800-2023 6.20.2)"); } @@ -1737,13 +2188,12 @@ class ParamVisitor final : public VNVisitor { AstCell* const cellp = VN_CAST(nodep, Cell); if (!cellParamsReferenceIfacePorts(cellp)) { AstNodeModule* const srcModp = cellp->modp(); - if (AstNodeModule* const newModp = m_processor.nodeDeparam( - cellp, srcModp, m_modp, m_modp->someInstanceName())) { - // For specialized interfaces, recursively process nested interface cells. - // This ensures nested interfaces are already specialized when modules - // using the interface are processed (parameter passthrough fix). - if (newModp != srcModp) specializeNestedIfaceCells(newModp); - } + // DISABLED: specializeNestedIfaceCells causes early nested + // iface specialization where PARAMTYPEDTYPE child REFDTYPEs + // point to template structs instead of clone structs, + // destructively widthing the template with default (zero) + // values. See t_interface_nested_struct_param.v. + m_processor.nodeDeparam(cellp, srcModp, m_modp, m_modp->someInstanceName()); } } @@ -1756,6 +2206,12 @@ class ParamVisitor final : public VNVisitor { void visit(AstNodeModule* nodep) override { if (nodep->recursiveClone()) nodep->dead(true); // Fake, made for recursive elimination if (nodep->dead()) return; // Marked by LinkDot (and above) + UINFO(9, "V3Param: visit module name=" + << nodep->prettyNameQ() << " orig='" << nodep->origName() + << "' someInstanceName='" << nodep->someInstanceName() + << "' hasGParam=" << (nodep->hasGParam() ? "yes" : "no") + << " user3p=" << (nodep->user3p() ? "set" : "null") + << " dead=" << (nodep->dead() ? "yes" : "no") << endl); if (AstClass* const classp = VN_CAST(nodep, Class)) { if (classp->hasGParam()) { // Don't enter into a definition. @@ -1836,8 +2292,22 @@ class ParamVisitor final : public VNVisitor { if (!nodep->valuep() && !VN_IS(m_modp, Class)) { nodep->v3error("Parameter without default value is never given value" << " (IEEE 1800-2023 6.20.1): " << nodep->prettyNameQ()); - } else { - V3Const::constifyParamsEdit(nodep); // The variable, not just the var->init() + } else if (nodep->valuep()) { + // In visit(AstVar*) for localparams, check if expression contains VARXREF + // to another localparam (not parameter). Parameters are already const, + // but localparams may not be evaluated yet. + bool hasVarXRefToLparam = false; + nodep->valuep()->foreach([&](const AstVarXRef* xrefp) { + if (xrefp->varp() && xrefp->varp()->varType() == VVarType::LPARAM) { + hasVarXRefToLparam = true; + } + }); + if (hasVarXRefToLparam) { + // Don't constify - let it be evaluated later + return; + } + + V3Const::constifyParamsEdit(nodep); } } } @@ -2127,6 +2597,7 @@ public: explicit ParamVisitor(ParamState& state, AstNetlist* netlistp) : m_state{state} , m_processor{netlistp} { + // Relies on modules already being in top-down-order iterate(netlistp); } @@ -2214,22 +2685,28 @@ public: netlistp->foreach([](AstNodeFTaskRef* ftaskrefp) { AstNodeFTask* ftaskp = ftaskrefp->taskp(); if (!ftaskp || !ftaskp->classMethod()) return; - const string funcName = ftaskp->name(); - for (AstNode* backp = ftaskrefp->backp(); backp; backp = backp->backp()) { - if (VN_IS(backp, Class)) { - if (backp == ftaskrefp->classOrPackagep()) - return; // task is in the same class as reference - break; + string funcName = ftaskp->name(); + // Find the nearest containing (ancestor) class for a node. + // Uses aboveLoopp() which correctly skips sibling links + // (e.g. covergroup classes) to find the true parent. + const auto ancestorClassOf = [](AstNode* startp) -> AstClass* { + for (AstNode* np = startp->aboveLoopp(); np; np = np->aboveLoopp()) { + if (AstClass* const cp = VN_CAST(np, Class)) return cp; } - } - AstClass* classp = nullptr; - for (AstNode* backp = ftaskp->backp(); backp; backp = backp->backp()) { - if (VN_IS(backp, Class)) { - classp = VN_AS(backp, Class); - break; - } - } + return nullptr; + }; + AstClass* refClassp = ancestorClassOf(ftaskrefp); + if (refClassp == ftaskrefp->classOrPackagep()) + return; // task is in the same class as reference + AstClass* classp = ancestorClassOf(ftaskp); UASSERT_OBJ(classp, ftaskrefp, "Class method has no class above it"); + // If the FUNCREF and its task are both in the same (clone) class but + // classOrPackagep still points to the old template, just retarget it + if (refClassp && refClassp == classp && ftaskrefp->classOrPackagep() + && ftaskrefp->classOrPackagep() != refClassp) { + ftaskrefp->classOrPackagep(refClassp); + return; + } if (classp->user3p()) return; // will not get removed, no need to relink AstClass* const parametrizedClassp = VN_CAST(classp->user4p(), Class); if (!parametrizedClassp) return; @@ -2280,11 +2757,11 @@ public: } // Set all links pointing to a user3 (deleting) node as null netlistp->foreach([](AstNode* const nodep) { - nodep->foreachLink([&](AstNode** const linkpp, const char*) { + nodep->foreachLink([&](AstNode** const linkpp, const char* namep) { if (*linkpp && (*linkpp)->user3()) { - UINFO(9, "clear link " << nodep); + UINFO(9, "clear link " << namep << " on " << nodep); *linkpp = nullptr; - UINFO(9, "cleared link " << nodep); + UINFO(9, "cleared link " << namep << " on " << nodep); } }); }); @@ -2298,6 +2775,11 @@ public: void V3Param::param(AstNetlist* rootp) { UINFO(2, __FUNCTION__ << ":"); - { ParamTop{rootp}; } // Destruct before checking + + if (dumpTreeEitherLevel() >= 9) V3LinkDotIfaceCapture::dumpEntries("before V3Param"); + { ParamTop{rootp}; } + V3LinkDotIfaceCapture::purgeStaleRefs(); + if (dumpTreeEitherLevel() >= 9) V3LinkDotIfaceCapture::dumpEntries("after V3Param"); + V3Global::dumpCheckGlobalTree("param", 0, dumpTreeEitherLevel() >= 3); } diff --git a/src/V3Width.cpp b/src/V3Width.cpp index aa6be6838..c96dcc561 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -72,6 +72,7 @@ #include "V3Const.h" #include "V3Error.h" #include "V3Global.h" +#include "V3LinkDotIfaceCapture.h" #include "V3LinkLValue.h" #include "V3MemberMap.h" #include "V3Number.h" @@ -270,6 +271,13 @@ class WidthVisitor final : public VNVisitor { nodep->findLogicDType(unpackBits, unpackMinBits, VSigning::UNSIGNED)}); } } + // When fromp() is a DType (e.g. unlinked RefDType), resolve through + // the ref chain; when it's an expression, dtypep() is already resolved. + static AstNodeDType* fromDTypep(AstNode* fromp) { + if (AstNodeDType* const dtypep = VN_CAST(fromp, NodeDType)) + return dtypep->skipRefOrNullp(); + return fromp ? fromp->dtypep() : nullptr; + } // VISITORS // Naming: width_O{outputtype}_L{lhstype}_R{rhstype}_W{widthing}_S{signing} // Where type: @@ -1006,8 +1014,17 @@ class WidthVisitor final : public VNVisitor { << std::hex << width << std::dec); } // Note width() not set on range; use elementsConst() + const bool inDeadModule = m_modep && m_modep->dead(); + // Suppress ASCRANGE in parameterized template modules whose parameter-dependent + // ranges haven't been resolved yet, or when the type has no owning module + // (e.g. moved to TypeTable during DepGraph resolution). + const bool inParameterizedTemplate + = m_modep && (m_modep->dead() || m_modep->parameterizedTemplate()); + const bool inTypeTable = !m_modep; if (nodep->ascending() && !VN_IS(nodep->backp(), UnpackArrayDType) - && !VN_IS(nodep->backp(), Cell)) { // For cells we warn in V3Inst + && !VN_IS(nodep->backp(), Cell) // For cells we warn in V3Inst + && !m_paramsOnly // Skip during parameter evaluation + && !inDeadModule && !inParameterizedTemplate && !inTypeTable) { nodep->v3warn(ASCRANGE, "Ascending bit range vector: left < right of bit range: [" << nodep->leftConst() << ":" << nodep->rightConst() << "]"); @@ -1035,6 +1052,11 @@ class WidthVisitor final : public VNVisitor { } UASSERT_OBJ(nodep->dtypep(), nodep, "dtype wasn't set"); // by V3WidthSel + // Suppress SELRANGE in parameterized template modules where + // parameter-dependent widths haven't been resolved yet. + const bool inParameterizedTemplate + = m_modep && (m_modep->dead() || m_modep->parameterizedTemplate()); + if (VN_IS(nodep->lsbp(), Const) && nodep->msbConst() < nodep->lsbConst()) { // Likely impossible given above width check nodep->v3warn(E_UNSUPPORTED, @@ -1047,7 +1069,7 @@ class WidthVisitor final : public VNVisitor { nodep->lsbp()->replaceWith(new AstConst{nodep->lsbp()->fileline(), 0}); } // We're extracting, so just make sure the expression is at least wide enough. - if (nodep->fromp()->width() < width) { + if (nodep->fromp()->width() < width && !inParameterizedTemplate) { nodep->v3warn(SELRANGE, "Extracting " << width << " bits from only " << nodep->fromp()->width() << " bit number"); // Extend it. @@ -1102,7 +1124,7 @@ class WidthVisitor final : public VNVisitor { AstNodeVarRef* lrefp = AstNodeVarRef::varRefLValueRecurse(nodep); if (m_doGenerate) { UINFO(5, "Selection index out of range inside generate"); - } else { + } else if (!inParameterizedTemplate) { nodep->v3warn(SELRANGE, "Selection index out of range: " << nodep->msbConst() << ":" << nodep->lsbConst() << " outside " << frommsb << ":" << fromlsb); @@ -1196,11 +1218,13 @@ class WidthVisitor final : public VNVisitor { if (VN_IS(nodep->bitp(), Const) && (VN_AS(nodep->bitp(), Const)->toSInt() > (frommsb - fromlsb) || VN_AS(nodep->bitp(), Const)->toSInt() < 0)) { - nodep->v3warn(SELRANGE, - "Selection index out of range: " - << (VN_AS(nodep->bitp(), Const)->toSInt() + fromlsb) - << " outside " << frommsb << ":" << fromlsb); - UINFO(1, " Related node: " << nodep); + // Suppress in dead/parameterized template modules + if (!(m_modep && (m_modep->dead() || m_modep->parameterizedTemplate()))) { + nodep->v3warn(SELRANGE, + "Selection index out of range: " + << (VN_AS(nodep->bitp(), Const)->toSInt() + fromlsb) + << " outside " << frommsb << ":" << fromlsb); + } } widthCheckSized(nodep, "Extract Range", nodep->bitp(), selwidthDTypep, EXTEND_EXP, false /*NOWARN*/); @@ -1842,8 +1866,9 @@ class WidthVisitor final : public VNVisitor { switch (nodep->attrType()) { case VAttrType::DIM_DIMENSIONS: case VAttrType::DIM_UNPK_DIMENSIONS: { - UASSERT_OBJ(nodep->fromp() && nodep->fromp()->dtypep(), nodep, "Unsized expression"); - const std::pair dim = nodep->fromp()->dtypep()->dimensions(true); + AstNodeDType* const dtypep = fromDTypep(nodep->fromp()); + UASSERT_OBJ(dtypep, nodep, "Unsized expression"); + const std::pair dim = dtypep->dimensions(true); const int val = (nodep->attrType() == VAttrType::DIM_UNPK_DIMENSIONS ? dim.second : (dim.first + dim.second)); @@ -1872,8 +1897,8 @@ class WidthVisitor final : public VNVisitor { case VAttrType::DIM_LOW: case VAttrType::DIM_RIGHT: case VAttrType::DIM_SIZE: { - UASSERT_OBJ(nodep->fromp() && nodep->fromp()->dtypep(), nodep, "Unsized expression"); - AstNodeDType* const dtypep = nodep->fromp()->dtypep(); + AstNodeDType* const dtypep = fromDTypep(nodep->fromp()); + UASSERT_OBJ(dtypep, nodep, "Unsized expression"); if (VN_IS(dtypep, QueueDType) || VN_IS(dtypep, DynArrayDType)) { switch (nodep->attrType()) { case VAttrType::DIM_SIZE: { @@ -1940,9 +1965,11 @@ class WidthVisitor final : public VNVisitor { nodep->replaceWith(newp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } else { + AstNodeDType* const baseDTypep = dtypep->skipRefp(); + UASSERT_OBJ(baseDTypep, nodep, "Unsized expression"); const int dim = 1; - AstConst* const newp - = dimensionValue(nodep->fileline(), dtypep, nodep->attrType(), dim); + AstConst* const newp = dimensionValue(nodep->fileline(), baseDTypep, + nodep->attrType(), dim); nodep->replaceWith(newp); VL_DO_DANGLING(nodep->deleteTree(), nodep); } @@ -2033,6 +2060,34 @@ class WidthVisitor final : public VNVisitor { // Only used in CStmts which don't care.... } + void visit(AstCellArrayRef* nodep) override { + if (nodep->didWidthAndSet()) return; + userIterateAndNext(nodep->selp(), WidthVP{SELF, PRELIM}.p()); + userIterateAndNext(nodep->selp(), WidthVP{SELF, FINAL}.p()); + nodep->dtypeSetVoid(); // placeholder; this node shouldnt survive beyond linking + nodep->didWidth(true); + } + + void visit(AstCellRef* nodep) override { + if (nodep->didWidthAndSet()) return; + + if (AstNodeExpr* const cellExprp = VN_CAST(nodep->cellp(), NodeExpr)) { + userIterateAndNext(cellExprp, WidthVP{SELF, PRELIM}.p()); + userIterateAndNext(cellExprp, WidthVP{SELF, FINAL}.p()); + } + + if (AstNodeExpr* const exprp = VN_CAST(nodep->exprp(), NodeExpr)) { + userIterateAndNext(exprp, WidthVP{SELF, PRELIM}.p()); + nodep->dtypeFrom(exprp); + userIterateAndNext(exprp, WidthVP{SELF, FINAL}.p()); + } else { + nodep->v3fatalSrc("CellRef exprp is not a NodeExpr: " // LCOV_EXCL_LINE + << nodep->exprp()->prettyTypeName()); + } + + nodep->didWidth(true); + } + // DTYPES void visit(AstNodeArrayDType* nodep) override { if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed @@ -2226,6 +2281,16 @@ class WidthVisitor final : public VNVisitor { } // Effectively nodep->dtypeFrom(nodep->dtypeSkipRefp()); // But might be recursive, so instead manually recurse into the referenced type + if (!nodep->subDTypep()) { + // Defer unlinked RefDTypes in parameterized template modules (or types + // with no owning module, e.g. moved to TypeTable) until specialization + // resolves them. + const bool inTemplateModule = !m_modep || m_modep->parameterizedTemplate(); + if (inTemplateModule) { + nodep->doingWidth(false); + return; + } + } UASSERT_OBJ(nodep->subDTypep(), nodep, "Unlinked"); nodep->dtypeFrom(nodep->subDTypep()); nodep->widthFromSub(nodep->subDTypep()); @@ -2251,9 +2316,13 @@ class WidthVisitor final : public VNVisitor { } void visit(AstParamTypeDType* nodep) override { if (nodep->didWidthAndSet()) return; // This node is a dtype & not both PRELIMed+FINALed + nodep->dtypep(iterateEditMoveDTypep(nodep, nodep->subDTypep())); userIterateChildren(nodep, nullptr); nodep->widthFromSub(nodep->subDTypep()); + // Clear childDTypep after dtypep is set to satisfy V3Broken invariant. + // The child dtype has been moved to the type table by iterateEditMoveDTypep. + if (nodep->dtypep() && nodep->childDTypep()) { nodep->childDTypep(nullptr); } } void visit(AstRequireDType* nodep) override { userIterateAndNext(nodep->lhsp(), WidthVP{SELF, BOTH}.p()); @@ -2631,6 +2700,10 @@ class WidthVisitor final : public VNVisitor { const bool implicitParam = nodep->isParam() && bdtypep && bdtypep->implicit(); if (implicitParam) { if (nodep->valuep()) { + // Remove blanket deferral. We must attempt to visit the value to determine + // type/deps. If it remains unresolved, specific node visitors (like AttrOf) should + // handle deferral by setting a placeholder type to prevent "No dtype" errors + // later. userIterateAndNext(nodep->valuep(), WidthVP{nodep->dtypep(), PRELIM}.p()); UINFO(9, "implicitParamPRELIMIV " << nodep->valuep()); // Although nodep will get a different width for parameters @@ -2645,7 +2718,10 @@ class WidthVisitor final : public VNVisitor { VL_DANGLING(bdtypep); } else { int width = 0; - const AstBasicDType* const valueBdtypep = nodep->valuep()->dtypep()->basicp(); + AstNodeDType* const valueDTypep = nodep->valuep()->dtypep(); + UASSERT_OBJ(valueDTypep, nodep->valuep(), + "Null dtype on implicit param value"); + const AstBasicDType* const valueBdtypep = valueDTypep->basicp(); bool issigned = false; if (bdtypep->isNosign()) { if (valueBdtypep && valueBdtypep->isSigned()) issigned = true; @@ -3278,6 +3354,14 @@ class WidthVisitor final : public VNVisitor { const bool isHardPackedUnion = nodep->packed() && VN_IS(nodep, UnionDType) && !VN_CAST(nodep, UnionDType)->isSoft(); + // Suppress union size errors in parameterized template modules where member + // widths depend on unresolved parameters. Also suppress when the type has no + // owning module (e.g. moved to TypeTable during DepGraph resolution). + // TODO: Revisit this gate if DepGraph becomes the sole flow and widthing + // can assume all types are already specialized. + const bool inTemplateModule = (m_modep && m_modep->parameterizedTemplate()) + || (VN_IS(nodep, UnionDType) && !m_modep); + // Determine bit assignments and width if (VN_IS(nodep, UnionDType) || nodep->packed()) { int lsb = 0; @@ -3293,7 +3377,8 @@ class WidthVisitor final : public VNVisitor { itemp->lsb(lsb); if (VN_IS(nodep, UnionDType)) { const int itemWidth = itemp->width(); - if (!first && isHardPackedUnion && itemWidth != width) { + // Skip union size check for template modules with unresolved parameters + if (!first && isHardPackedUnion && itemWidth != width && !inTemplateModule) { itemp->v3error("Hard packed union members must have equal size " "(IEEE 1800-2023 7.3.1)"); } @@ -7899,6 +7984,7 @@ class WidthVisitor final : public VNVisitor { "Under node " << nodep->prettyTypeName() << " has no dtype?? Missing Visitor func?"); if (expDTypep->basicp()->untyped() || nodep->dtypep()->basicp()->untyped()) return false; + // During DepGraph execution, expected width may be 0 if the type hasn't been UASSERT_OBJ(nodep->width() != 0, nodep, "Under node " << nodep->prettyTypeName() << " has no expected width?? Missing Visitor func?"); @@ -8871,6 +8957,7 @@ class WidthVisitor final : public VNVisitor { UASSERT_OBJ(dtnodep->didWidth(), parentp, "iterateEditMoveDTypep didn't get width resolution of " << dtnodep->prettyTypeName()); + // Move to under netlist UINFO(9, "iterateEditMoveDTypep child moving " << dtnodep); dtnodep->unlinkFrBack(); diff --git a/src/Verilator.cpp b/src/Verilator.cpp index f30e13820..1d8c523f8 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -69,6 +69,7 @@ #include "V3LifePost.h" #include "V3LiftExpr.h" #include "V3LinkDot.h" +#include "V3LinkDotIfaceCapture.h" #include "V3LinkInc.h" #include "V3LinkJump.h" #include "V3LinkLValue.h" @@ -178,10 +179,15 @@ static void process() { // This requires some width calculations and constant propagation // No more AstGenCase/AstGenFor/AstGenIf after this V3Param::param(v3Global.rootp()); + V3LinkDot::linkDotParamed(v3Global.rootp()); // Cleanup as made new modules V3LinkLValue::linkLValue(v3Global.rootp()); // Resolve new VarRefs V3Error::abortIfErrors(); + // Fix any remaining cross-interface refs created during V3Width::widthParamsEdit + // that weren't captured earlier. Must run before V3Dead deletes template modules. + V3LinkDotIfaceCapture::finalizeIfaceCapture(); + // Remove any modules that were parameterized and are no longer referenced. V3Dead::deadifyModules(v3Global.rootp()); diff --git a/test_regress/t/t_class_param_extends_static_member_function_access.py b/test_regress/t/t_class_param_extends_static_member_function_access.py new file mode 100755 index 000000000..84b274f68 --- /dev/null +++ b/test_regress/t/t_class_param_extends_static_member_function_access.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_class_param_extends_static_member_function_access.v b/test_regress/t/t_class_param_extends_static_member_function_access.v new file mode 100644 index 000000000..4cfc9a1b4 --- /dev/null +++ b/test_regress/t/t_class_param_extends_static_member_function_access.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +class Class1 #( + type T +); + static function int get_p(); + return 7; + endfunction +endclass + +class Class2 #( + type T +) extends Class1 #(T); + static function int get_p2; + return T::get_p(); + endfunction +endclass + +module t; + initial begin + typedef Class2#(Class1#(int)) Class; + if (Class::get_p2() != Class1#(int)::get_p()) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_iface_self_ref_typedef.py b/test_regress/t/t_iface_self_ref_typedef.py new file mode 100755 index 000000000..bc0edcf81 --- /dev/null +++ b/test_regress/t/t_iface_self_ref_typedef.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 by Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Verifies that the self-referential interface typedef pattern +# (typedef iface#(T) self_t inside interface iface) is detected +# and handled correctly during deparameterization. + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--binary --stats"]) + +test.file_grep(test.stats, r'Param, Self-reference iface typedefs\s+(\d+)', 1) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_iface_self_ref_typedef.v b/test_regress/t/t_iface_self_ref_typedef.v new file mode 100644 index 000000000..298f795a1 --- /dev/null +++ b/test_regress/t/t_iface_self_ref_typedef.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Test for self-referential interface typedef +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// Self-referential typedef: typedef iface#(T) this_type inside interface iface +interface my_iface #(type T = logic); + typedef my_iface #(T) self_t; + T data; +endinterface + +module t (); + my_iface #(logic [7:0]) if0 (); + + initial begin + if0.data = 8'hAB; + if ($bits(if0.data) != 8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_iface_typedef_scale.py b/test_regress/t/t_iface_typedef_scale.py new file mode 100755 index 000000000..3d1724e3e --- /dev/null +++ b/test_regress/t/t_iface_typedef_scale.py @@ -0,0 +1,75 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Stress test for interface typedef scaling. Generates an interface with +# many typedefs and two parameterised instances to exercise the +# findTypedefInModule / findDTypeInModule caching path. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import time + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = test.obj_dir + "/t_iface_typedef_scale.sv" + +N_TYPEDEFS = 5000 +MAX_COMPILE_SECS = 10 # Generous budget; catches O(N^2) explosion where 5k typedefs would take minutes without the cache + + +def gen(filename, n): + with open(filename, 'w', encoding="utf8") as fh: + fh.write("// Generated by t_iface_typedef_scale.py\n") + fh.write("// Stress test: interface with {} typedefs, two instances\n".format(n)) + fh.write("\n") + # Interface with N typedefs + fh.write("interface iface_many_types #(parameter int CFG = 8);\n") + for i in range(n): + fh.write(" typedef logic [CFG-1:0] td_{};\n".format(i)) + fh.write("endinterface\n\n") + # Module that uses the interface and references typedefs via the port + fh.write("module sub (\n") + fh.write(" iface_many_types ifc,\n") + fh.write(" input logic clk\n") + fh.write(");\n") + fh.write(" typedef ifc.td_0 local_td_0;\n") + fh.write(" typedef ifc.td_{} local_td_n;\n".format(n - 1)) + fh.write(" local_td_0 r0;\n") + fh.write(" local_td_n rn;\n") + fh.write(" always @(posedge clk) begin\n") + fh.write(" r0 <= '0;\n") + fh.write(" rn <= '0;\n") + fh.write(" end\n") + fh.write("endmodule\n\n") + # Top module with two instances using different parameters + fh.write("module t (input logic clk);\n") + fh.write(" iface_many_types #(.CFG(16)) ifc_a();\n") + fh.write(" iface_many_types #(.CFG(32)) ifc_b();\n") + fh.write(" sub sub_a (.ifc(ifc_a), .clk(clk));\n") + fh.write(" sub sub_b (.ifc(ifc_b), .clk(clk));\n") + fh.write(" initial begin\n") + fh.write(' $write("*-* All Finished *-*\\n");\n') + fh.write(" $finish;\n") + fh.write(" end\n") + fh.write("endmodule\n") + + +gen(test.top_filename, N_TYPEDEFS) + +test.timeout(MAX_COMPILE_SECS) + +t0 = time.time() +test.compile(verilator_flags2=["-x-assign fast --x-initial fast"]) +elapsed = time.time() - t0 + +print("t_iface_typedef_scale: {} typedefs compiled in {:.3f}s (limit {:.1f}s)".format( + N_TYPEDEFS, elapsed, MAX_COMPILE_SECS)) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_iface_typedef_struct_member.py b/test_regress/t/t_iface_typedef_struct_member.py new file mode 100755 index 000000000..95e4478dd --- /dev/null +++ b/test_regress/t/t_iface_typedef_struct_member.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Test for MemberDType fixup in type table +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') +test.top_filename = "t/t_iface_typedef_struct_member.v" + +test.compile(v_flags2=["--binary"]) +test.execute() + +test.passes() diff --git a/test_regress/t/t_iface_typedef_struct_member.v b/test_regress/t/t_iface_typedef_struct_member.v new file mode 100644 index 000000000..9c7fcb3c0 --- /dev/null +++ b/test_regress/t/t_iface_typedef_struct_member.v @@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Test for MemberDType fixup and fixDeadRefs in type table (coverage) +// +// Parameterized interface with struct/union typedefs, instantiated in two +// modules. The sub-module uses $bits() on a typedef, which forces widthing +// of the template's type chain during V3Param. This moves template RefDTypes +// into the global type table before the template dies, exercising +// fixDeadRefsInTypeTable and the MemberDType fixup in V3LinkDotIfaceCapture. +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2025 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package cfg_pkg; + typedef struct packed { + int unsigned NumUnits; + int unsigned LineSize; + } cfg_t; +endpackage + +// Parameterized interface with nested struct/union typedefs. +// The struct-in-union pattern triggers MemberDType fixup (line 1056). +// The $bits() usage in sub_mod forces widthing during V3Param, moving +// template RefDTypes into the type table before the template dies. +interface types_if #(parameter cfg_pkg::cfg_t cfg = 0)(); + typedef logic [$clog2(cfg.NumUnits)-1:0] idx_t; + + typedef struct packed { + logic [31:$clog2(cfg.LineSize)] tag; + logic [$clog2(cfg.LineSize)-1:0] offset; + } addr_t; + + typedef struct packed { + logic [3:0] cmd; + union packed { + addr_t addr; // struct-in-union: MemberDType trigger + logic [31:0] raw; + } payload; + } req_t; +endinterface + +module sub_mod #(parameter cfg_pkg::cfg_t cfg = 0)(); + types_if #(cfg) types(); + typedef types.idx_t idx_t; + typedef types.req_t req_t; + typedef types.addr_t addr_t; + + localparam int ReqWidth = $bits(req_t); + + idx_t s_idx; + req_t s_req; + addr_t s_addr; +endmodule + +module t; + localparam cfg_pkg::cfg_t CFG = '{NumUnits: 5, LineSize: 32}; + + types_if #(CFG) types(); + typedef types.req_t req_t; + req_t top_req; + + sub_mod #(.cfg(CFG)) sub(); + + initial begin + #1; + `checkd($bits(top_req), 36); + `checkd($bits(sub.s_req), 36); + `checkd($bits(sub.s_idx), 3); + `checkd($bits(sub.s_addr), 32); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_iface_typedef_wrong_clone.py b/test_regress/t/t_iface_typedef_wrong_clone.py new file mode 100755 index 000000000..44d191244 --- /dev/null +++ b/test_regress/t/t_iface_typedef_wrong_clone.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_iface_typedef_wrong_clone.v b/test_regress/t/t_iface_typedef_wrong_clone.v new file mode 100644 index 000000000..2b79650b3 --- /dev/null +++ b/test_regress/t/t_iface_typedef_wrong_clone.v @@ -0,0 +1,85 @@ +// DESCRIPTION: Verilator: Test for structural disambiguation and wrong-clone +// fixup in V3LinkDotIfaceCapture. +// +// Modeled after Aerial's simple_cache_if pattern: +// - A parameterized interface (sc_if) contains a nested sub-interface (sc_io) +// - The sub-interface has typedefs (addr_t) +// - A wrapper module (sc_wrap) instantiates sc_if and uses its typedefs +// - Two different parameterizations of sc_wrap exist +// - The re-exported typedefs from sc_io create entries where followCellPath +// may fail, triggering the structural disambiguation path +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +typedef struct packed { + int unsigned AddrBits; + int unsigned DataBits; +} sc_cfg_t; + +// Inner types interface - parameterized with struct typedef +interface sc_types_if #(parameter sc_cfg_t cfg = 0)(); + typedef logic [cfg.AddrBits-1:0] addr_t; + typedef logic [cfg.DataBits-1:0] data_t; + + typedef struct packed { + addr_t addr; + data_t data; + } pkt_t; +endinterface + +// Cache interface - wraps types interface and re-exports typedefs +interface sc_if #(parameter sc_cfg_t cfg = 0)(); + sc_types_if #(cfg) sc_io(); + + typedef sc_io.addr_t addr_t; + typedef sc_io.data_t data_t; + typedef sc_io.pkt_t pkt_t; + + addr_t rq_addr_i; +endinterface + +// Wrapper module that uses the cache interface +module sc_wrap #(parameter sc_cfg_t cfg = 0)(); + sc_if #(cfg) cache(); + + typedef cache.addr_t addr_t; + typedef cache.pkt_t pkt_t; + + addr_t local_addr; + pkt_t local_pkt; + + assign cache.rq_addr_i = local_addr; +endmodule + +// Top-level: two wrappers with DIFFERENT configs +// This creates two clones of sc_if (and sc_types_if) with different params +module t; + localparam sc_cfg_t cfg_narrow = '{AddrBits: 16, DataBits: 32}; + localparam sc_cfg_t cfg_wide = '{AddrBits: 32, DataBits: 64}; + + sc_wrap #(.cfg(cfg_narrow)) narrow(); + sc_wrap #(.cfg(cfg_wide)) wide(); + + initial begin + #1; + // narrow: addr=16, data=32, pkt=16+32=48 + `checkd($bits(narrow.local_addr), 16); + `checkd($bits(narrow.local_pkt), 48); + + // wide: addr=32, data=64, pkt=32+64=96 + `checkd($bits(wide.local_addr), 32); + `checkd($bits(wide.local_pkt), 96); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_interface_array_parameter_aggregate.py b/test_regress/t/t_interface_array_parameter_aggregate.py index df81265b7..096e10e28 100755 --- a/test_regress/t/t_interface_array_parameter_aggregate.py +++ b/test_regress/t/t_interface_array_parameter_aggregate.py @@ -11,8 +11,8 @@ import vltest_bootstrap test.scenarios('simulator_st') -test.compile(fails=True) +test.compile(verilator_flags2=['--binary']) -#test.execute(fails=True) +test.execute() test.passes() diff --git a/test_regress/t/t_interface_nested_port_array.out b/test_regress/t/t_interface_nested_port_array.out index a2f56f9b1..b37571a25 100644 --- a/test_regress/t/t_interface_nested_port_array.out +++ b/test_regress/t/t_interface_nested_port_array.out @@ -1,22 +1,10 @@ -%Error: t/t_interface_nested_port_array.v:160:5: Interface 'l3_if' not connected as parent's interface not connected - : ... note: In instance 't.m_l3' - : ... Perhaps caused by another error on the parent interface that needs resolving - : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? - 160 | l3_if#(W, L0A_W) l3, - | ^~~~~ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_interface_nested_port_array.v:123:5: Interface 'l2_if' not connected as parent's interface not connected - : ... note: In instance 't.m_l3.m_l2' - : ... Perhaps caused by another error on the parent interface that needs resolving - : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? - 123 | l2_if#(W, L0A_W) l2s[1:0], - | ^~~~~ %Error: t/t_interface_nested_port_array.v:91:5: Interface 'l2_if' not connected as parent's interface not connected : ... note: In instance 't.m_l3.m_l2.m_l2b' : ... Perhaps caused by another error on the parent interface that needs resolving : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? 91 | l2_if#(W, L0A_W) l2, | ^~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Internal Error: t/t_interface_nested_port_array.v:27:11: ../V3LinkDot.cpp:#: Module/etc never assigned a symbol entry? : ... note: In instance 't.m_l3.m_l2.m_l2b.m_l1_1' 27 | interface l2_if #( diff --git a/test_regress/t/t_interface_nested_port_array_noinl.out b/test_regress/t/t_interface_nested_port_array_noinl.out index a2f56f9b1..b37571a25 100644 --- a/test_regress/t/t_interface_nested_port_array_noinl.out +++ b/test_regress/t/t_interface_nested_port_array_noinl.out @@ -1,22 +1,10 @@ -%Error: t/t_interface_nested_port_array.v:160:5: Interface 'l3_if' not connected as parent's interface not connected - : ... note: In instance 't.m_l3' - : ... Perhaps caused by another error on the parent interface that needs resolving - : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? - 160 | l3_if#(W, L0A_W) l3, - | ^~~~~ - ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_interface_nested_port_array.v:123:5: Interface 'l2_if' not connected as parent's interface not connected - : ... note: In instance 't.m_l3.m_l2' - : ... Perhaps caused by another error on the parent interface that needs resolving - : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? - 123 | l2_if#(W, L0A_W) l2s[1:0], - | ^~~~~ %Error: t/t_interface_nested_port_array.v:91:5: Interface 'l2_if' not connected as parent's interface not connected : ... note: In instance 't.m_l3.m_l2.m_l2b' : ... Perhaps caused by another error on the parent interface that needs resolving : ... Or, perhaps intended an interface instantiation but are missing parenthesis (IEEE 1800-2023 25.3)? 91 | l2_if#(W, L0A_W) l2, | ^~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Internal Error: t/t_interface_nested_port_array.v:27:11: ../V3LinkDot.cpp:#: Module/etc never assigned a symbol entry? : ... note: In instance 't.m_l3.m_l2.m_l2b.m_l1_1' 27 | interface l2_if #( diff --git a/test_regress/t/t_interface_nested_struct_param.py b/test_regress/t/t_interface_nested_struct_param.py new file mode 100755 index 000000000..46d1fe4c0 --- /dev/null +++ b/test_regress/t/t_interface_nested_struct_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=['--binary']) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_interface_nested_struct_param.v b/test_regress/t/t_interface_nested_struct_param.v new file mode 100644 index 000000000..a4932167b --- /dev/null +++ b/test_regress/t/t_interface_nested_struct_param.v @@ -0,0 +1,186 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// Test: nested parameterized interface with struct typedef used as type parameter +// +// Reproduces a bug where specializeNestedIfaceCells causes early +// specialization of a nested interface, leaving PARAMTYPEDTYPE child +// REFDTYPEs pointing to the template struct instead of the clone struct. +// The struct's width then resolves using the template's default parameter +// values instead of the actual overridden values. +// +// Pattern (mirrors Aerial's simple_cache / simple_cache_if / simple_cache_types_if): +// 1. A wrapper interface instantiates a nested types interface +// 2. The types interface computes localparams from cfg (using $clog2/division) +// 3. Those localparams define typedef ranges for struct members +// 4. A module receives the wrapper interface as a port, also instantiates +// the types interface locally, and uses the struct typedef +// 5. Both the wrapper and the module use the same cfg, so they share +// the same types_if clone via "De-parameterize to prev" + +package cfg_pkg; + typedef struct packed { + logic [31:0] AddrBits; + logic [31:0] Capacity; + logic [31:0] LineSize; + logic [31:0] Associativity; + } cfg_t; +endpackage + +// Nested types interface: derives struct typedef from computed localparams +interface types_if #( + parameter cfg_pkg::cfg_t cfg = '0 +)(); + // Computed localparams - these use division and $clog2 of cfg fields. + // With default cfg='0, these produce X/undefined values. + localparam int NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int LINES_PER_WAY = NUM_LINES / cfg.Associativity; + localparam int BLOCK_BITS = $clog2(cfg.LineSize); + localparam int ROW_BITS = $clog2(LINES_PER_WAY); + localparam int TAG_BITS = cfg.AddrBits - ROW_BITS - BLOCK_BITS; + + typedef logic [TAG_BITS-1:0] tag_t; + typedef logic [ROW_BITS-1:0] row_t; + typedef logic [BLOCK_BITS-1:0] block_t; + + typedef struct packed { + logic vld; + tag_t tag; + row_t row; + block_t block; + } entry_t; +endinterface + +// Wrapper interface: instantiates types_if as a nested cell +// (mirrors simple_cache_if which instantiates simple_cache_types_if) +interface wrapper_if #( + parameter cfg_pkg::cfg_t cfg = '0 +)(); + types_if #(cfg) types(); + + typedef types.tag_t tag_t; + + logic req_vld; + tag_t req_tag; +endinterface + +// Sub-module parameterized by entry width +// (mirrors flop_nr / sram_generic_1r1w parameterized by $bits(sc_tag_t)) +module entry_store #( + parameter int ENTRY_WIDTH = 8, + parameter int DEPTH = 4 +)( + input logic clk, + input logic wr_en, + input logic [ENTRY_WIDTH-1:0] wr_data, + output logic [ENTRY_WIDTH-1:0] rd_data +); + logic [ENTRY_WIDTH-1:0] mem [DEPTH]; + always_ff @(posedge clk) begin + if (wr_en) mem[0] <= wr_data; + end + assign rd_data = mem[0]; +endmodule + +// Inner module: receives wrapper_if as port, instantiates types_if locally, +// uses struct typedef from types_if +// (mirrors simple_cache which receives simple_cache_if, instantiates +// simple_cache_types_if, and uses types.sc_tag_t) +module inner_mod #( + parameter cfg_pkg::cfg_t cfg = '0 +)( + input logic clk, + wrapper_if io +); + // Local instantiation of types_if - same cfg, so gets same clone + // as the one inside wrapper_if via "De-parameterize to prev" + types_if #(cfg) types(); + + typedef types.entry_t entry_t; + typedef types.tag_t tag_t; + + entry_t wr_entry; + entry_t rd_entry; + + assign wr_entry.vld = io.req_vld; + assign wr_entry.tag = io.req_tag; + assign wr_entry.row = '0; + assign wr_entry.block = '0; + + // Use $bits of the struct typedef as a value parameter to sub-module. + // This is the critical pattern: $bits(entry_t) must resolve using the + // clone's struct (correct width), not the template's (zero/X width). + entry_store #( + .ENTRY_WIDTH($bits(entry_t)), + .DEPTH(8) + ) u_store ( + .clk(clk), + .wr_en(io.req_vld), + .wr_data(wr_entry), + .rd_data(rd_entry) + ); +endmodule + +// Outer wrapper module: instantiates wrapper_if and inner_mod +// (mirrors mblit_simple_cache_wrap) +module outer_mod #( + parameter cfg_pkg::cfg_t cfg = '0 +)( + input logic clk +); + wrapper_if #(cfg) wif(); + + inner_mod #(cfg) u_inner ( + .clk(clk), + .io(wif) + ); +endmodule + +module t; + logic clk = 0; + always #5 clk = ~clk; + + int cyc = 0; + + // Non-default config: + // AddrBits=64, Capacity=1024, LineSize=64, Associativity=2 + // NUM_LINES = 1024/64 = 16 + // LINES_PER_WAY = 16/2 = 8 + // BLOCK_BITS = $clog2(64) = 6 + // ROW_BITS = $clog2(8) = 3 + // TAG_BITS = 64 - 3 - 6 = 55 + // entry_t = 1 + 55 + 3 + 6 = 65 bits + localparam cfg_pkg::cfg_t MY_CFG = '{ + AddrBits: 64, + Capacity: 1024, + LineSize: 64, + Associativity: 2 + }; + + outer_mod #(.cfg(MY_CFG)) u_outer (.clk(clk)); + + always @(posedge clk) begin + cyc <= cyc + 1; + + u_outer.wif.req_vld <= (cyc[0] == 1'b1); + u_outer.wif.req_tag <= 55'(cyc); + + if (cyc > 5) begin + // Verify the struct round-trips correctly + if (u_outer.u_inner.rd_entry.vld !== 1'b1 && cyc > 10) begin + $display("FAIL cyc=%0d: rd_entry.vld=%b expected 1", + cyc, u_outer.u_inner.rd_entry.vld); + $stop; + end + end + + if (cyc == 20) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_lparam_assign_iface_const.py b/test_regress/t/t_lparam_assign_iface_const.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_const.v b/test_regress/t/t_lparam_assign_iface_const.v new file mode 100644 index 000000000..9237520e4 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_const.v @@ -0,0 +1,40 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +typedef struct { + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY [0:3]; +} foo_t; + +interface intf + #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}) + (); +endinterface + +module sub (intf the_intf_port [4]); + localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; + + initial begin + #1; + if (intf_foo_bar_int != 4) $stop; + end +endmodule + +module t (); + intf the_intf [4] (); + + sub + the_sub ( + .the_intf_port (the_intf) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_assign_iface_typedef.v b/test_regress/t/t_lparam_assign_iface_typedef.v index eb527f398..1d219d5f8 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef.v +++ b/test_regress/t/t_lparam_assign_iface_typedef.v @@ -31,8 +31,8 @@ module top(); .p_dwidth(8) ) if0(); - localparam p0_rq_t = if0.rq_t; - localparam p0_rs_t = if0.rs_t; + localparam type p0_rq_t = if0.rq_t; + localparam type p0_rs_t = if0.rs_t; p0_rq_t rq; p0_rs_t rs; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_bad.out b/test_regress/t/t_lparam_assign_iface_typedef_bad.out new file mode 100644 index 000000000..1f360a195 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_bad.out @@ -0,0 +1,5 @@ +%Error: t/t_lparam_assign_iface_typedef_bad.v:28:3: Expecting a data type: 'p0_rq_t' + 28 | p0_rq_t rq; + | ^~~~~~~ + ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. +%Error: Exiting due to diff --git a/test_regress/t/t_lparam_assign_iface_typedef_bad.py b/test_regress/t/t_lparam_assign_iface_typedef_bad.py new file mode 100755 index 000000000..1d5ccb8f4 --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_bad.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2025 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(fails=True, expect_filename=test.golden_filename) + +test.passes() diff --git a/test_regress/t/t_lparam_assign_iface_typedef_bad.v b/test_regress/t/t_lparam_assign_iface_typedef_bad.v new file mode 100644 index 000000000..2a030945b --- /dev/null +++ b/test_regress/t/t_lparam_assign_iface_typedef_bad.v @@ -0,0 +1,29 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2025 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 +// +// localparam without 'type' keyword should error, not silently ignore. +// Correct syntax is: localparam type p0_rq_t = if0.rq_t; + +interface x_if #( + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +)(); + typedef struct packed { + logic [p_awidth-1:0] addr; + logic [p_dwidth-1:0] data; + } rq_t; +endinterface + +module t(); + x_if #( + .p_awidth(16), + .p_dwidth(8) + ) if0(); + + localparam p0_rq_t = if0.rq_t; // Bad: missing 'type' keyword + + p0_rq_t rq; // Should fail: p0_rq_t is not a data type +endmodule diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested.v b/test_regress/t/t_lparam_assign_iface_typedef_nested.v index 65db21dd1..ecc0ae3fb 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested.v @@ -37,7 +37,7 @@ module top(); .p_dwidth(8) ) if0(); - localparam p0_rq2_t = if0.y_if0.rq2_t; + localparam type p0_rq2_t = if0.y_if0.rq2_t; initial begin #1; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested2.v b/test_regress/t/t_lparam_assign_iface_typedef_nested2.v index 8cc63cd26..4e92ee22a 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested2.v @@ -39,7 +39,7 @@ module top (); .p_dwidth(8) ) if0 (); - localparam p0_rq2_t = if0.y_if0.rq2_t; + localparam type p0_rq2_t = if0.y_if0.rq2_t; p0_rq2_t p0_rq2; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested3.v b/test_regress/t/t_lparam_assign_iface_typedef_nested3.v index 634282662..ba37423fc 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested3.v @@ -40,9 +40,9 @@ module top (); .p_dwidth(8) ) if0 (); - localparam p0_rq2_t = if0.y_if0.rq2_t; - localparam p0_rq_t = if0.rq_t; - localparam p0_rs_t = if0.rs_t; + localparam type p0_rq2_t = if0.y_if0.rq2_t; + localparam type p0_rq_t = if0.rq_t; + localparam type p0_rs_t = if0.rs_t; p0_rq2_t p0_rq2; p0_rq_t p0_rq; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested5.v b/test_regress/t/t_lparam_assign_iface_typedef_nested5.v index 7179a0685..bc7ade5ef 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested5.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested5.v @@ -46,10 +46,10 @@ module top (); .p_dwidth(8) ) if0 (); - localparam p0_rq2_t = if0.y_if0.rq2_t; - localparam p0_rq_t = if0.rq_t; - localparam p0_rs_t = if0.rs_t; - localparam p0_req_t = if0.z_if0.req_t; + localparam type p0_rq2_t = if0.y_if0.rq2_t; + localparam type p0_rq_t = if0.rq_t; + localparam type p0_rs_t = if0.rs_t; + localparam type p0_req_t = if0.z_if0.req_t; p0_rq2_t p0_rq2; p0_rq_t p0_rq; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.v index d34a43490..27895f5cd 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod1.v @@ -20,7 +20,7 @@ endinterface module a_mod( bus_if bus_io ); - localparam bus_rq_t = bus_io.rq_t; + localparam type bus_rq_t = bus_io.rq_t; endmodule module top(); diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.v index 56f0e8b33..6c39c30d1 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod2.v @@ -28,8 +28,8 @@ endinterface module a_mod ( bus_if bus_io ); - localparam bus_rq_t = bus_io.rq_t; - localparam bus_rs_t = bus_io.rs_t; + localparam type bus_rq_t = bus_io.rq_t; + localparam type bus_rs_t = bus_io.rs_t; localparam p_awidth = bus_io.p_awidth; localparam p_dwidth = bus_io.p_dwidth; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.v index 403e8587a..cce59e1c4 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mod3.v @@ -36,9 +36,9 @@ module top (); .p_dwidth(8) ) if0 (); - localparam p0_rq2_t = if0.y_if0.rq2_t; - localparam p0_rq_t = if0.rq_t; - localparam p0_rs_t = if0.rs_t; + localparam type p0_rq2_t = if0.y_if0.rq2_t; + localparam type p0_rq_t = if0.rq_t; + localparam type p0_rs_t = if0.rs_t; p0_rq2_t p0_rq2; p0_rq_t p0_rq; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.v index 23d299d47..0fb11bbfa 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_mpkg1.v @@ -37,8 +37,8 @@ module a_mod #( ) ( bus_if bus_io ); - localparam bus_rq_t = bus_io.rq_t; - localparam bus_rs_t = bus_io.rs_t; + localparam type bus_rq_t = bus_io.rq_t; + localparam type bus_rs_t = bus_io.rs_t; bus_rq_t rq; bus_rs_t rs; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v index 0249ac563..111a06852 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_nested_pkg.v @@ -54,10 +54,10 @@ module top (); x_if #(.CFG(CFG)) if0 (); - localparam p0_rq2_t = if0.y_if0.rq2_t; - localparam p0_rq_t = if0.rq_t; - localparam p0_rs_t = if0.rs_t; - localparam p0_req_t = if0.z_if0.req_t; + localparam type p0_rq2_t = if0.y_if0.rq2_t; + localparam type p0_rq_t = if0.rq_t; + localparam type p0_rs_t = if0.rs_t; + localparam type p0_req_t = if0.z_if0.req_t; p0_rq2_t p0_rq2; p0_rq_t p0_rq; diff --git a/test_regress/t/t_lparam_dep_iface0.py b/test_regress/t/t_lparam_dep_iface0.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface0.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface0.v b/test_regress/t/t_lparam_dep_iface0.v new file mode 100644 index 000000000..54abb8d2e --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface0.v @@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +typedef struct { + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY [0:3]; +} foo_t; + +interface intf + #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}) + (); +endinterface + +module sub (intf single_intf_port); + localparam byte single_foo_bar_byte = single_intf_port.FOO.BAR_ARRAY[3]; + + initial begin + #1; + `checkd(single_foo_bar_byte, 8'd8); + end +endmodule + +module t (); + intf single_intf (); + + sub + the_sub ( + .single_intf_port(single_intf) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface1.py b/test_regress/t/t_lparam_dep_iface1.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface1.v b/test_regress/t/t_lparam_dep_iface1.v new file mode 100644 index 000000000..c9029fc01 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface1.v @@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +typedef struct { + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY [0:3]; +} foo_t; + +interface intf + #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}) + (); +endinterface + +module sub (intf the_intf_port [4]); + localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; + + initial begin + #1; + `checkd(intf_foo_bar_int, 4); + end +endmodule + +module t (); + intf the_intf [4] (); + + sub + the_sub ( + .the_intf_port (the_intf) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface10.py b/test_regress/t/t_lparam_dep_iface10.py new file mode 100755 index 000000000..cfbb2aee3 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface10.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2025 by Wilson Snyder. This program is free # This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface10.v b/test_regress/t/t_lparam_dep_iface10.v new file mode 100644 index 000000000..0e34e4793 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface10.v @@ -0,0 +1,72 @@ +// DESCRIPTION: Verilator: Multiple interface instances with different params +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package scp; + typedef struct packed { + int unsigned ABits; + int unsigned BBits; + } cfg_t; +endpackage + +interface a_if #( + parameter a_p = 0 +)(); + localparam int LP0 = a_p * 2; + typedef logic [LP0-1:0] a_t; +endinterface + +interface sc_if #( + parameter scp::cfg_t cfg = 0 +)(); + localparam int LP_MUL = cfg.ABits * cfg.BBits; + localparam int LP_ADD = cfg.ABits + cfg.BBits; + + a_if #(LP_MUL) types_mul(); + a_if #(LP_ADD) types_add(); +endinterface + +module sc #(parameter scp::cfg_t cfg=0) ( + sc_if io +); + + typedef io.types_mul.a_t a_mul_t; + typedef io.types_add.a_t a_add_t; + + initial begin + #1; + // cfg.ABits=2, cfg.BBits=3 + // LP_MUL=6 -> a_p=6 -> LP0=12 -> a_mul_t is 12 bits + // LP_ADD=5 -> a_p=5 -> LP0=10 -> a_add_t is 10 bits + `checkd($bits(a_mul_t), 12); + `checkd($bits(a_add_t), 10); + end +endmodule + +module t(); + localparam scp::cfg_t sc_cfg = '{ + ABits : 2, + BBits : 3 + }; + + sc_if #(sc_cfg) sc_io (); + + sc #(sc_cfg) sc( + .io(sc_io) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface11.py b/test_regress/t/t_lparam_dep_iface11.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface11.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface11.v b/test_regress/t/t_lparam_dep_iface11.v new file mode 100644 index 000000000..6ed0ccd3c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface11.v @@ -0,0 +1,82 @@ +// DESCRIPTION: Verilator: Cross-interface typedef references +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package scp; + typedef struct packed { + int unsigned ABits; + int unsigned BBits; + } cfg_t; +endpackage + +interface a_if #( + parameter a_p = 0 +)(); + localparam int LP0 = a_p * 2; + typedef logic [LP0-1:0] a_t; +endinterface + +interface b_if #( + parameter b_p = 0 +)(); + localparam int LP0 = b_p + 3; + typedef logic [LP0-1:0] b_t; +endinterface + +interface sc_if #( + parameter scp::cfg_t cfg = 0 +)(); + localparam int LP0 = cfg.ABits * cfg.BBits; + + a_if #(LP0) a_inst(); + b_if #(LP0) b_inst(); + + typedef a_inst.a_t a_t; + typedef b_inst.b_t b_t; +endinterface + +module sc #(parameter scp::cfg_t cfg=0) ( + sc_if io +); + + typedef io.a_t a_t; + typedef io.b_t b_t; + + initial begin + #1; + // cfg.ABits=2, cfg.BBits=3 -> LP0=6 + // a_if: a_p=6 -> LP0=12 -> a_t is 12 bits + // b_if: b_p=6 -> LP0=9 -> b_t is 9 bits + `checkd(12, $bits(a_t)); + `checkd(9, $bits(b_t)); + end +endmodule + +module t(); + localparam scp::cfg_t sc_cfg = '{ + ABits : 2, + BBits : 3 + }; + + sc_if #(sc_cfg) sc_io (); + + sc #(sc_cfg) sc( + .io(sc_io) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_lparam_dep_iface12.py b/test_regress/t/t_lparam_dep_iface12.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface12.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface12.v b/test_regress/t/t_lparam_dep_iface12.v new file mode 100644 index 000000000..e462e4cca --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface12.v @@ -0,0 +1,90 @@ +// DESCRIPTION: Verilator: 4-level deep nested interface typedef with dependent localparams +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package scp; + typedef struct packed { + int unsigned ABits; + int unsigned BBits; + } cfg_t; +endpackage + +// Level 4: innermost interface +interface d_if #( + parameter d_p = 0 +)(); + localparam int LP0 = d_p + 1; + typedef logic [LP0-1:0] d_t; +endinterface + +// Level 3 +interface c_if #( + parameter c_p = 0 +)(); + localparam int LP0 = c_p * 2; + d_if #(LP0) d_inst(); + typedef d_inst.d_t c_t; +endinterface + +// Level 2 +interface b_if #( + parameter scp::cfg_t cfg = 0 +)(); + localparam int LP0 = cfg.ABits * cfg.BBits; + c_if #(LP0) c_inst(); + typedef c_inst.c_t b_t; +endinterface + +// Level 1: outermost interface +interface a_if #( + parameter scp::cfg_t cfg = 0 +)(); + b_if #(cfg) b_inst(); + typedef b_inst.b_t a_t; +endinterface + +module m #(parameter scp::cfg_t cfg=0) ( + a_if io +); + + typedef io.a_t a_t; + + initial begin + #1; + // cfg.ABits=2, cfg.BBits=3 + // b_if: LP0 = 2*3 = 6 + // c_if: c_p=6, LP0 = 6*2 = 12 + // d_if: d_p=12, LP0 = 12+1 = 13 + // d_t is 13 bits + `checkd($bits(a_t), 13); + end +endmodule + +module t(); + localparam scp::cfg_t cfg = '{ + ABits : 2, + BBits : 3 + }; + + a_if #(cfg) a_io (); + + m #(cfg) m_inst( + .io(a_io) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_lparam_dep_iface13.py b/test_regress/t/t_lparam_dep_iface13.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface13.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface13.v b/test_regress/t/t_lparam_dep_iface13.v new file mode 100644 index 000000000..4feff82f7 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface13.v @@ -0,0 +1,107 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package sc; + typedef struct packed { + int unsigned CmdTagBits; + int unsigned Associativity; + int unsigned Capacity; + int unsigned LineSize; + int unsigned StateBits; + int unsigned AddrBits; + int unsigned MissQSize; + + // fetch (hit) width. this must be >= to refill width. FgWidth / RefillWidth is the number of array slices for data. + int unsigned FgWidth; + // number of expected beats for refill is LineSize/RefillWidth + int unsigned RefillWidth; + } cfg_t; +endpackage + +interface simple_cache_types_if #( + parameter sc::cfg_t cfg = 0 +)(); + + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; + localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; + +endinterface + +interface simple_cache_if #( + parameter sc::cfg_t cfg = 0 +)(); + simple_cache_types_if #(cfg) types(); + +endinterface + +module simple_cache #(parameter sc::cfg_t cfg=0) ( + simple_cache_if io +); + + localparam num_rld_beats = cfg.LineSize / cfg.RefillWidth; + localparam num_arrays = cfg.FgWidth / cfg.RefillWidth; + localparam dat_array_width = cfg.RefillWidth*8; + localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; + localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; + localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; + + initial begin + #1; + `checkd(SC_DROWS_PER_LINE, 4); + `checkd(SC_NUM_LINES, 16); + `checkd(SC_LINES_PER_WAY, 8); + `checkd(SC_NUM_DROWS, 64); + `checkd(num_rld_beats, 8); + `checkd(num_arrays, 2); + `checkd(dat_array_width, 64); + end + +endmodule + + +module t(); + + localparam sc::cfg_t sc_cfg = '{ + CmdTagBits : $clog2(6), + Associativity : 2, + Capacity : 1024, + LineSize : 64, + StateBits : 2, + AddrBits : 64, + MissQSize : 2, + + FgWidth : 16, + RefillWidth : 8 + }; + + simple_cache_if #(sc_cfg) sc_io (); + + simple_cache #(sc_cfg) simple_cache( + .io(sc_io) + ); + + localparam int SC_DROWS_PER_LINE = sc_io.types.SC_DROWS_PER_LINE; + + initial begin + #2; + `checkd(SC_DROWS_PER_LINE, 4); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface14.py b/test_regress/t/t_lparam_dep_iface14.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface14.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface14.v b/test_regress/t/t_lparam_dep_iface14.v new file mode 100644 index 000000000..04ac60423 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface14.v @@ -0,0 +1,85 @@ +// DESCRIPTION: +// Combined regression model mixing PIN-assigned type param +// (t_interface_derived_type) and nested captured typedef flows +// (t_lparam_dep_iface*). Keeps both types in a single file. +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +typedef struct packed { + int unsigned ABits; + int unsigned BBits; +} scp_cfg_t; + +interface a_if #(parameter a_p = 0)(); + localparam int LP0 = a_p * 2; + typedef logic [LP0-1:0] a_t; +endinterface + +interface sct_if #(parameter scp_cfg_t cfg = 0)(); + localparam int LP0 = cfg.ABits * cfg.BBits; + a_if #(LP0) a_if0(); + typedef a_if0.a_t a_t; // Captured typedef from nested interface +endinterface + +interface intf #( + parameter type data_t = bit, + parameter int arr[2][4] +) (); + data_t data; + logic [$bits(data)-1:0] other_data; +endinterface + +module sub #( + parameter int width, + parameter int arr[2][4] +) (); + typedef struct packed { + logic [3:3] [0:0] [width-1:0] field; + } user_type_t; + + // This has a PIN that assigns data_t + intf #( + .data_t(user_type_t), + .arr(arr) + ) the_intf (); + + logic [width-1:0] signal; + + always_comb begin + the_intf.data.field = signal; + the_intf.other_data = signal; + end +endmodule + +module t (); + localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3}; + + sct_if #(sc_cfg) types (); + + sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); + sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); + + typedef types.a_if0.a_t a_t; + typedef types.a_t a2_t; + + initial begin + #1; + `checkd(12, $bits(a_t)); + `checkd(12, $bits(a2_t)); + `checkd(8, $bits(sub8.the_intf.data)); + `checkd(16, $bits(sub16.the_intf.data)); + + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface15.py b/test_regress/t/t_lparam_dep_iface15.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface15.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface15.v b/test_regress/t/t_lparam_dep_iface15.v new file mode 100644 index 000000000..2af8515ac --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface15.v @@ -0,0 +1,101 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Combined test mixing PIN-assigned type param interface +// (t_interface_derived_type) with nested captured typedef/localparam +// (t_lparam_dep_iface6). + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +typedef struct packed { + int unsigned ABits; + int unsigned BBits; +} scp_cfg_t; + +interface a_if #(parameter a_p = 0)(); + localparam int LP0 = a_p; + typedef logic [LP0-1:0] a_t; +endinterface + +interface sct_if #(parameter scp_cfg_t cfg = 0)(); + localparam int LP0 = cfg.ABits * cfg.BBits; + a_if #(LP0) a_if0(); + typedef a_if0.a_t a_t; +endinterface + +interface sc_if #(parameter scp_cfg_t cfg = 0)(); + sct_if #(cfg) types(); + typedef types.a_t a_t; +endinterface + +interface intf #( + parameter type data_t = bit, + parameter int arr[2][4] +) (); + data_t data; + logic [$bits(data)-1:0] other_data; +endinterface + +module sub #( + parameter int width, + parameter int arr[2][4] +) (); + typedef struct packed { + logic [3:3] [0:0] [width-1:0] field; + } user_type_t; + + intf #( + .data_t(user_type_t), + .arr(arr) + ) the_intf (); + + logic [width-1:0] signal; + + always_comb begin + the_intf.data.field = signal; + the_intf.other_data = signal; + end +endmodule + +module sc #(parameter scp_cfg_t cfg=0) ( + sc_if io +); + typedef io.a_t a_t; + + initial begin + #1; + `checkd($bits(a_t), 6); + end +endmodule + +module t (); + localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3}; + + sc_if #(sc_cfg) sc_io (); + sc #(sc_cfg) sc_inst (.io(sc_io)); + + sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); + sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); + + typedef sc_io.types.a_if0.a_t inner_t; + typedef sc_io.types.a_t mid_t; + + initial begin + #1; + `checkd($bits(inner_t), 6); + `checkd($bits(mid_t), 6); + `checkd($bits(sub8.the_intf.data), 8); + `checkd($bits(sub16.the_intf.data), 16); + + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface16.py b/test_regress/t/t_lparam_dep_iface16.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface16.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface16.v b/test_regress/t/t_lparam_dep_iface16.v new file mode 100644 index 000000000..1a68ec3e2 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface16.v @@ -0,0 +1,98 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Combined test mixing PIN-assigned type param interface (t_interface_derived_type) +// with nested captured typedef/localparam (t_lparam_dep_iface6). + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +typedef struct packed { + int unsigned ABits; + int unsigned BBits; +} scp_cfg_t; + +interface a_if #(parameter a_p = 0)(); + localparam int LP0 = a_p; + typedef logic [LP0-1:0] a_t; +endinterface + +interface sct_if #(parameter scp_cfg_t cfg = 0)(); + localparam int LP0 = cfg.ABits * cfg.BBits; + a_if #(LP0) a_if0(); + typedef a_if0.a_t a_t; +endinterface + +interface sc_if #(parameter scp_cfg_t cfg = 0)(); + sct_if #(cfg) types(); + typedef types.a_t a_t; +endinterface + +interface intf #( + parameter type data_t = bit, + parameter int arr[2][4] +) (); + data_t data; + logic [$bits(data)-1:0] other_data; +endinterface + +module sub #( + parameter int width, + parameter int arr[2][4] +) (); + typedef struct packed { + logic [3:3] [0:0] [width-1:0] field; + } user_type_t; + + intf #( + .data_t(user_type_t), + .arr(arr) + ) the_intf (); + + logic [width-1:0] signal; + + always_comb begin + the_intf.data.field = signal; + the_intf.other_data = signal; + end +endmodule + +module sc #(parameter scp_cfg_t cfg=0) ( + sc_if io +); + typedef io.a_t a_t; + + initial begin + #1; + `checkd($bits(a_t), 6); + end +endmodule + +module t (input clk); + localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3}; + + sc_if #(sc_cfg) sc_io (); + sc #(sc_cfg) sc_inst (.io(sc_io)); + + sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); + + typedef sc_io.types.a_if0.a_t inner_t; + typedef sc_io.types.a_t mid_t; + + initial begin + #1; + `checkd($bits(inner_t), 6); + `checkd($bits(mid_t), 6); + `checkd($bits(sub8.the_intf.data), 8); + + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface2.py b/test_regress/t/t_lparam_dep_iface2.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface2.v b/test_regress/t/t_lparam_dep_iface2.v new file mode 100644 index 000000000..afa27b5f2 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface2.v @@ -0,0 +1,90 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package p1; + typedef struct packed { + int unsigned ABits; + int unsigned BBits; + } cfg_t; +endpackage + +package p2; + typedef struct packed { + int unsigned CBits; + int unsigned DBits; + } cfg_t; +endpackage + +interface types_if #(parameter p1::cfg_t cfg=0)(); + localparam int ABits = cfg.ABits; + localparam int BBits = cfg.BBits; + + typedef struct packed { + logic [cfg.ABits-1:0] a; + logic [cfg.BBits-1:0] b; + } a_t; +endinterface + +interface io_if #(parameter p1::cfg_t cfg=0)(); + + localparam int ABits = cfg.ABits; + localparam int BBits = cfg.BBits; + + types_if #(cfg) types (); + typedef types.a_t a_t; +endinterface + +module modA( + io_if io +); + + localparam int ABits = io.types.ABits; + localparam int BBits = io.types.BBits; + + typedef io.types.a_t a_t; + + initial begin + #1; + `checkd(ABits, 8); + `checkd(BBits, 24); + `checkd($bits(a_t), 32); + end + +endmodule + +module t (); + localparam p2::cfg_t mcfg = '{ + CBits : 8, + DBits : 16 + }; + + localparam p1::cfg_t cfg = '{ + ABits : mcfg.CBits, + BBits : mcfg.CBits + mcfg.DBits + }; + + io_if #(cfg) modA_io (); + + typedef modA_io.types.a_t a_t; + + modA modA_inst ( + .io(modA_io) + ); + + initial begin + #2; + `checkd($bits(a_t), 32); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface3.py b/test_regress/t/t_lparam_dep_iface3.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface3.v b/test_regress/t/t_lparam_dep_iface3.v new file mode 100644 index 000000000..5675fc8c1 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface3.v @@ -0,0 +1,157 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package sc; + typedef struct packed { + int unsigned CmdTagBits; + int unsigned Associativity; + int unsigned Capacity; + int unsigned LineSize; + int unsigned StateBits; + int unsigned AddrBits; + int unsigned MissQSize; + + // fetch (hit) width. this must be >= to refill width. FgWidth / RefillWidth is the number of array slices for data. + int unsigned FgWidth; + // number of expected beats for refill is LineSize/RefillWidth + int unsigned RefillWidth; + } cfg_t; +endpackage + +interface simple_cache_types_if #( + parameter sc::cfg_t cfg = 0 +)(); + + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; + localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; + + typedef logic [cfg.AddrBits-1:0] addr_t; + typedef logic [cfg.Associativity-1:0] assoc_oh_t; + typedef logic [cfg.Associativity-2:0] plru_t; + typedef logic [cfg.StateBits-1:0] state_t; + typedef logic [cfg.CmdTagBits-1:0] cmd_tag_t; + typedef logic [$clog2(cfg.MissQSize)-1:0] missq_tag_t; + + typedef logic [SC_TAG_BITS-1:0] tag_t; + typedef logic [SC_ROW_BITS-1:0] row_t; + typedef logic [SC_BLOCK_BITS-1:0] block_t; + typedef logic [$clog2(SC_NUM_DROWS)-1:0] drow_addr_t; + + typedef struct packed { + tag_t tag; + row_t row; + block_t block; + } sc_tag_addr_t; + + typedef struct packed { + logic vld; + tag_t tag; + state_t state; + } sc_tag_t; + + typedef struct packed { + state_t [cfg.Associativity-1:0] state_v; + assoc_oh_t hit_v; + assoc_oh_t vld_v; + plru_t plru; + } sc_tag_status_t; +endinterface + +interface simple_cache_if #( + parameter sc::cfg_t cfg = 0 +)(); + simple_cache_types_if #(cfg) types(); + + typedef types.cmd_tag_t cmd_tag_t; + typedef types.addr_t addr_t; + typedef types.missq_tag_t missq_tag_t; + +endinterface + +module simple_cache #(parameter sc::cfg_t cfg=0) ( + simple_cache_if io +); + + typedef io.types.addr_t addr_t; + typedef io.types.cmd_tag_t cmd_tag_t; + typedef io.types.drow_addr_t drow_addr_t; + typedef io.types.plru_t plru_t; + typedef io.types.row_t row_t; + typedef io.types.state_t state_t; + typedef io.types.sc_tag_addr_t sc_tag_addr_t; + typedef io.types.sc_tag_t sc_tag_t; + typedef io.types.sc_tag_status_t sc_tag_status_t; + + localparam num_rld_beats = cfg.LineSize / cfg.RefillWidth; + localparam num_arrays = cfg.FgWidth / cfg.RefillWidth; + localparam dat_array_width = cfg.RefillWidth*8; + localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; + localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; + localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; + + initial begin + #1; + `checkd(SC_DROWS_PER_LINE, 4); + `checkd(SC_NUM_LINES, 16); + `checkd(SC_LINES_PER_WAY, 8); + `checkd(SC_NUM_DROWS, 64); + `checkd(num_rld_beats, 8); + `checkd(num_arrays, 2); + `checkd(dat_array_width, 64); + end + +endmodule + + +module t(); + + localparam sc::cfg_t sc_cfg = '{ + CmdTagBits : $clog2(6), + Associativity : 2, + Capacity : 1024, + LineSize : 64, + StateBits : 2, + AddrBits : 64, + MissQSize : 2, + + FgWidth : 16, + RefillWidth : 8 + }; + + simple_cache_if #(sc_cfg) sc_io (); + + simple_cache #(sc_cfg) simple_cache( + .io(sc_io) + ); + + //localparam int SC_DROWS_PER_LINE = sc_io.types.SC_DROWS_PER_LINE; + //localparam int SC_NUM_LINES = sc_io.types.SC_NUM_LINES; + //localparam int SC_LINES_PER_WAY = sc_io.types.SC_LINES_PER_WAY; + //localparam int SC_NUM_DROWS = sc_io.types.SC_NUM_DROWS; + + initial begin + #2; + //`checkd(SC_DROWS_PER_LINE, 4); + //`checkd(SC_NUM_LINES, 16); + //`checkd(SC_LINES_PER_WAY, 8); + //`checkd(SC_NUM_DROWS, 64); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface4.py b/test_regress/t/t_lparam_dep_iface4.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface4.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface4.v b/test_regress/t/t_lparam_dep_iface4.v new file mode 100644 index 000000000..d81eab7c0 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface4.v @@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package scp; + typedef struct packed { + int unsigned Capacity; + int unsigned LineSize; + } cfg_t; +endpackage + +interface sct_if #( + parameter scp::cfg_t cfg = 0 +)(); + + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + + typedef logic [(cfg.Capacity / cfg.LineSize)-1:0] sc_num_lines_t; + + typedef logic [SC_NUM_LINES-1:0] sc_num_lines_2_t; + +endinterface + +interface sc_if #( + parameter scp::cfg_t cfg = 0 +)(); + sct_if #(cfg) types(); + +endinterface + +module sc #(parameter scp::cfg_t cfg=0) ( + sc_if io +); + + localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; + + typedef io.types.sc_num_lines_t sc_num_lines_t; + typedef io.types.sc_num_lines_2_t sc_num_lines_2_t; + + initial begin + #1; + $display("SC_NUM_LINES = %d", SC_NUM_LINES); + $display("bits SC_NUM_LINES = %d", $bits(sc_num_lines_t)); + $display("bits SC_NUM_LINES_2 = %d", $bits(sc_num_lines_2_t)); + `checkd(SC_NUM_LINES, 16); + `checkd($bits(sc_num_lines_t), 16); + `checkd($bits(sc_num_lines_2_t), 16); + end +endmodule + +module t(); + + localparam scp::cfg_t sc_cfg = '{ + Capacity : 1024, + LineSize : 64 + }; + + sc_if #(sc_cfg) sc_io (); + + sc #(sc_cfg) simple_cache( + .io(sc_io) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface5.py b/test_regress/t/t_lparam_dep_iface5.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface5.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface5.v b/test_regress/t/t_lparam_dep_iface5.v new file mode 100644 index 000000000..cb0c654d9 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface5.v @@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package scp; + typedef struct packed { + int unsigned Associativity; + int unsigned Capacity; + int unsigned LineSize; + int unsigned AddrBits; + } cfg_t; +endpackage + +interface sct_if #( + parameter scp::cfg_t cfg = 0 +)(); + + // this is intentional as I want all the dependencies to be resolved + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + + typedef logic [SC_TAG_BITS-1:0] tag_t; +endinterface + +interface sc_if #( + parameter scp::cfg_t cfg = 0 +)(); + sct_if #(cfg) types(); +endinterface + +module sc #(parameter scp::cfg_t cfg=0) ( + sc_if io +); + sct_if #(cfg) types(); + + typedef io.types.tag_t tag_t; + typedef types.tag_t tag2_t; + + initial begin + #1; + `checkd(55, $bits(tag_t)); + `checkd(55, $bits(tag2_t)); + end +endmodule + +module t(); + localparam scp::cfg_t sc_cfg = '{ + Associativity : 2, + Capacity : 1024, + LineSize : 64, + AddrBits : 64 + }; + + sc_if #(sc_cfg) sc_io (); + + typedef sc_io.types.tag_t tag_t; + + sc #(sc_cfg) sc( + .io(sc_io) + ); + + initial begin + #2; + `checkd(55, $bits(tag_t)); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface6.py b/test_regress/t/t_lparam_dep_iface6.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface6.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface6.v b/test_regress/t/t_lparam_dep_iface6.v new file mode 100644 index 000000000..e19b8a6a4 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface6.v @@ -0,0 +1,76 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package scp; + typedef struct packed { + int unsigned ABits; + int unsigned BBits; + } cfg_t; +endpackage + +interface a_if #( + parameter a_p = 0 +)(); + localparam int LP0 = a_p; + typedef logic [LP0-1:0] a_t; +endinterface + +interface sct_if #( + parameter scp::cfg_t cfg = 0 +)(); + // this is intentional as I want all the dependencies to be resolved + localparam int LP0 = cfg.ABits * cfg.BBits; + + a_if #(LP0) a_if0(); + typedef a_if0.a_t a_t; +endinterface + +interface sc_if #( + parameter scp::cfg_t cfg = 0 +)(); + sct_if #(cfg) types(); + + typedef types.a_t a_t; +endinterface + +module sc #(parameter scp::cfg_t cfg=0) ( + sc_if io +); + + typedef io.a_t a_t; + + initial begin + #1; + `checkd(6, $bits(a_t)); + + end +endmodule + +module t(); + localparam scp::cfg_t sc_cfg = '{ + ABits : 2, + BBits : 3 + }; + + sc_if #(sc_cfg) sc_io (); + + sc #(sc_cfg) sc( + .io(sc_io) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_lparam_dep_iface7.py b/test_regress/t/t_lparam_dep_iface7.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface7.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface7.v b/test_regress/t/t_lparam_dep_iface7.v new file mode 100644 index 000000000..133d8a802 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface7.v @@ -0,0 +1,67 @@ +// DESCRIPTION: Verilator: Get agregate type parameter from array of interfaces +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package scp; + typedef struct packed { + int unsigned ABits; + int unsigned BBits; + } cfg_t; +endpackage + +interface a_if #( + parameter a_p = 0 +)(); + localparam int LP0 = a_p * 2; + typedef logic [LP0-1:0] a_t; +endinterface + +interface sc_if #( + parameter scp::cfg_t cfg = 0 +)(); + + localparam int LP0 = cfg.ABits * cfg.BBits; + a_if #(LP0) types(); +endinterface + +module sc #(parameter scp::cfg_t cfg=0) ( + sc_if io +); + + typedef io.types.a_t a_t; + + initial begin + #1; + `checkd(12, $bits(a_t)); + + end +endmodule + +module t(); + localparam scp::cfg_t sc_cfg = '{ + ABits : 2, + BBits : 3 + }; + + sc_if #(sc_cfg) sc_io (); + + sc #(sc_cfg) sc( + .io(sc_io) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_lparam_dep_iface8.py b/test_regress/t/t_lparam_dep_iface8.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface8.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface8.v b/test_regress/t/t_lparam_dep_iface8.v new file mode 100644 index 000000000..3d8c325c0 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface8.v @@ -0,0 +1,77 @@ +// DESCRIPTION: Verilator: 3-level nested interface typedef with dependent localparams +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package scp; + typedef struct packed { + int unsigned ABits; + int unsigned BBits; + } cfg_t; +endpackage + +// Level 3: innermost interface +interface a_if #( + parameter a_p = 0 +)(); + localparam int LP0 = a_p * 2; + typedef logic [LP0-1:0] a_t; +endinterface + +// Level 2: middle interface +interface sct_if #( + parameter scp::cfg_t cfg = 0 +)(); + localparam int LP0 = cfg.ABits * cfg.BBits; + a_if #(LP0) a_if0(); + typedef a_if0.a_t a_t; +endinterface + +// Level 1: outermost interface +interface sc_if #( + parameter scp::cfg_t cfg = 0 +)(); + sct_if #(cfg) types(); + typedef types.a_t a_t; +endinterface + +module sc #(parameter scp::cfg_t cfg=0) ( + sc_if io +); + + typedef io.a_t a_t; + + initial begin + #1; + // cfg.ABits=2, cfg.BBits=3 -> LP0=6 -> a_p=6 -> LP0=12 -> a_t is 12 bits + `checkd(12, $bits(a_t)); + end +endmodule + +module t(); + localparam scp::cfg_t sc_cfg = '{ + ABits : 2, + BBits : 3 + }; + + sc_if #(sc_cfg) sc_io (); + + sc #(sc_cfg) sc( + .io(sc_io) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_lparam_dep_iface9.py b/test_regress/t/t_lparam_dep_iface9.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface9.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_lparam_dep_iface9.v b/test_regress/t/t_lparam_dep_iface9.v new file mode 100644 index 000000000..0e994e057 --- /dev/null +++ b/test_regress/t/t_lparam_dep_iface9.v @@ -0,0 +1,70 @@ +// DESCRIPTION: Verilator: Multiple dependent localparams in chain +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package scp; + typedef struct packed { + int unsigned ABits; + int unsigned BBits; + } cfg_t; +endpackage + +// Interface with chained localparam dependencies +interface a_if #( + parameter a_p = 0 +)(); + localparam int LP0 = a_p * 2; // LP0 = a_p * 2 + localparam int LP1 = LP0 + 1; // LP1 = LP0 + 1 + localparam int LP2 = LP1 * LP0; // LP2 = LP1 * LP0 + typedef logic [LP2-1:0] a_t; +endinterface + +interface sc_if #( + parameter scp::cfg_t cfg = 0 +)(); + localparam int LP0 = cfg.ABits * cfg.BBits; + a_if #(LP0) types(); +endinterface + +module sc #(parameter scp::cfg_t cfg=0) ( + sc_if io +); + + typedef io.types.a_t a_t; + + initial begin + #1; + // cfg.ABits=2, cfg.BBits=3 -> LP0=6 + // a_if: a_p=6 -> LP0=12, LP1=13, LP2=156 -> a_t is 156 bits + `checkd(156, $bits(a_t)); + end +endmodule + +module t(); + localparam scp::cfg_t sc_cfg = '{ + ABits : 2, + BBits : 3 + }; + + sc_if #(sc_cfg) sc_io (); + + sc #(sc_cfg) sc( + .io(sc_io) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_param_type_from_iface_struct.py b/test_regress/t/t_param_type_from_iface_struct.py new file mode 100755 index 000000000..eee20b937 --- /dev/null +++ b/test_regress/t/t_param_type_from_iface_struct.py @@ -0,0 +1,24 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Verifies that skipWidthForTemplateStruct fires in V3Param::cellPinCleanup +# when struct typedefs from a nested parameterized interface are passed as +# type parameters through two levels of interface nesting. + +import vltest_bootstrap + +test.scenarios('vlt') + +test.compile(v_flags2=["--binary --stats"]) + +test.file_grep(test.stats, r'Param, Template struct width skips\s+(\d+)', 2) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_param_type_from_iface_struct.v b/test_regress/t/t_param_type_from_iface_struct.v new file mode 100644 index 000000000..9628c9748 --- /dev/null +++ b/test_regress/t/t_param_type_from_iface_struct.v @@ -0,0 +1,91 @@ +// DESCRIPTION: Verilator: Test type parameter from interface struct +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// Exercises skipWidthForTemplateStruct in V3Param::cellPinCleanup. +// +// Pattern: nested parameterized interfaces with struct type parameters: +// 1. Parameterized inner interface (inner_if) defines struct typedefs +// 2. Outer interface (outer_if) contains a nested inner_if instance +// 3. A module takes the outer interface as a port and creates typedefs +// through two levels of nesting: port.inner.req_t +// 4. Those struct typedefs are passed as type parameters to an inner module +// 5. A separate module creates inner_if clones with different configs, +// ensuring inner_if gets parameterizedTemplate()=true before the +// type parameter pins are processed + +package cfg_pkg; + typedef struct packed { + int unsigned IdBits; + int unsigned DataBits; + } cfg_t; +endpackage + +// Parameterized inner interface with struct typedefs +interface inner_if #(parameter cfg_pkg::cfg_t cfg = '0); + typedef struct packed { + logic [cfg.IdBits-1:0] id; + logic [cfg.DataBits-1:0] data; + } req_t; + typedef struct packed { + logic [cfg.IdBits-1:0] id; + logic [1:0] resp; + } resp_t; + req_t req; + resp_t resp; +endinterface + +// Outer interface containing a nested inner_if +interface outer_if #(parameter cfg_pkg::cfg_t cfg = '0); + inner_if #(cfg) inner(); +endinterface + +// Module with type parameters (consumer of struct typedefs) +module typed_mod #( + parameter type req_t = logic, + parameter type resp_t = logic +)( + input logic clk +); + req_t r; + resp_t s; + assign r = '0; + assign s = '0; +endmodule + +// Wrapper: takes outer_if ports, typedefs through two-level nesting, +// passes as type parameters to typed_mod +module wrap_mod #(parameter int NUM = 1)( + input logic clk, + outer_if ports [NUM] +); + typedef ports[0].inner.req_t local_req_t; + typedef ports[0].inner.resp_t local_resp_t; + typed_mod #(.req_t(local_req_t), .resp_t(local_resp_t)) u_sub(.clk(clk)); +endmodule + +module t(); + logic clk = 0; + localparam cfg_pkg::cfg_t CFG_A = '{IdBits: 4, DataBits: 32}; + localparam cfg_pkg::cfg_t CFG_B = '{IdBits: 8, DataBits: 64}; + + // Force inner_if to be cloned with different configs first + inner_if #(CFG_A) early_a(); + inner_if #(CFG_B) early_b(); + assign early_a.req = '0; + assign early_a.resp = '0; + assign early_b.req = '0; + assign early_b.resp = '0; + + outer_if #(CFG_A) io [2] (); + wrap_mod #(.NUM(2)) u_wrap(.clk(clk), .ports(io)); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_ascrange_prelim_cfg.py b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v new file mode 100644 index 000000000..c1eda693e --- /dev/null +++ b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v @@ -0,0 +1,44 @@ +// DESCRIPTION: Verilator: Regression for prelim ASCRANGE on cfg-based interface typedefs +// +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package axis; + typedef struct packed { + int unsigned DataWidth; + } cfg_t; +endpackage + +interface axis_if #(parameter axis::cfg_t cfg = '0)(); + typedef logic [cfg.DataWidth-1:0] tdata_t; +endinterface + +module axis_chan #( + parameter axis::cfg_t chan_cfg = '0 +) (); + axis_if #(chan_cfg) axis_channel_io(); + typedef axis_channel_io.tdata_t data_t; + localparam int kWidth = $bits(data_t); + initial begin + #1; + `checkd(kWidth,32); + end +endmodule + +module t; + localparam axis::cfg_t axis_chan_cfg = '{DataWidth: 32}; + axis_chan #(.chan_cfg(axis_chan_cfg)) u_chan(); + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_bisect1.py b/test_regress/t/t_paramgraph_bisect1.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_bisect1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_bisect1.v b/test_regress/t/t_paramgraph_bisect1.v new file mode 100644 index 000000000..4de603c87 --- /dev/null +++ b/test_regress/t/t_paramgraph_bisect1.v @@ -0,0 +1,116 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: Minimal test for sibling interface typedef resolution +// This is the SIMPLEST case that demonstrates the t_lparam_dep_iface10 failure pattern: +// - Two sibling cells of the same interface type with DIFFERENT parameters +// - A module that accesses typedefs from BOTH siblings +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package rial; + +// Configuration structure + typedef struct packed { + // CCA Parameters + int unsigned NumDd; + // CC Parameters + int unsigned DDNumStuff; + int unsigned DDNumStuffThreads; + } cfg_t; +endpackage + +package cb; + typedef struct packed { + int unsigned XdatSize; // raw packet data size + } cfg_t; +endpackage + +interface ccia_types_if #(parameter rial::cfg_t cfg=0)(); + + // 'base' types + typedef logic [$clog2(cfg.DDNumStuff)-1:0] wave_index_t; + +// types for tb + typedef struct packed { + logic [3:0] e_cmd; + logic en; + logic csr; + wave_index_t wave_index; + logic [11:0] reg_addr; + logic [64-(4+1+1+$clog2(cfg.DDNumStuff)+12)-1:0] pad0; + } tl_reg_cmd_t; + + typedef struct packed { + logic [63:0] raw; + } tl_addr_cmd_t; + + typedef union packed { + tl_reg_cmd_t rcmd; + tl_addr_cmd_t acmd; + } tl_data_fld_t; + + typedef union packed { + tl_data_fld_t [cfg.DDNumStuffThreads-1:0] d_a; + } cmd_data_t; + + typedef struct packed { + cmd_data_t d; + } cmd_beat_t; + +endinterface + +module rial_top #( + parameter rial::cfg_t aer_cfg=0 +)(); + +// for the types + ccia_types_if #(aer_cfg) ccia_types(); + +// genvars and locally defined types + typedef ccia_types.cmd_beat_t cmd_beat_t; + + // CB and RBUS + localparam cb::cfg_t cb_cfg = '{ + XdatSize:$bits(cmd_beat_t) + }; + + initial begin + #1; + `checkd($bits(ccia_types.tl_data_fld_t), 64); + `checkd($bits(ccia_types.cmd_data_t), 512); + `checkd($bits(cmd_beat_t), 512); + `checkd(cb_cfg.XdatSize, 512); + end + +endmodule + +// SOC Top w/IO and SOC configuration +module rial_wrap(); + + parameter rial::cfg_t aer_cfg = '{ + NumDd : 3, + // CC Parameters + DDNumStuff : 4, + DDNumStuffThreads : 8 + }; + +// DUT + rial_top #( + .aer_cfg(aer_cfg) + ) rial_top(); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule diff --git a/test_regress/t/t_paramgraph_bits_corruption.py b/test_regress/t/t_paramgraph_bits_corruption.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_bits_corruption.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_bits_corruption.v b/test_regress/t/t_paramgraph_bits_corruption.v new file mode 100644 index 000000000..e5a34d207 --- /dev/null +++ b/test_regress/t/t_paramgraph_bits_corruption.v @@ -0,0 +1,69 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// DESCRIPTION: Minimal test for sibling interface typedef resolution +// This is the SIMPLEST case that demonstrates the t_lparam_dep_iface10 failure pattern: +// - Two sibling cells of the same interface type with DIFFERENT parameters +// - A module that accesses typedefs from BOTH siblings +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package TestPkg; + // Create a struct that results in 525 bits like in aerial_wrap + typedef struct packed { + logic [31:0] field1; + logic [31:0] field2; + logic [31:0] field3; + logic [31:0] field4; + logic [31:0] field5; + logic [31:0] field6; + logic [31:0] field7; + logic [31:0] field8; + logic [31:0] field9; + logic [31:0] field10; + logic [31:0] field11; + logic [31:0] field12; + logic [31:0] field13; + logic [31:0] field14; + logic [31:0] field15; + logic [31:0] field16; + logic [12:0] field17; // 525 bits total (16*32 + 13) + } cmd_beat_t; + + typedef struct packed { + logic [31:0] Rids; + logic [31:0] Pids; + logic [31:0] Fnum; + logic [31:0] XdatSize; // 32-bit field + } cfg_t; + + // This pattern assignment should trigger the error + // The issue is that $bits(cmd_beat_t) evaluation during DepGraph causes corruption + // where the pattern literal gets a 128-bit constant instead of proper 32-bit assignment + // Note: cmd_beat_t is referenced directly, not through a localparam type alias + localparam cfg_t cb_cfg = '{ + Rids : 32'h1, + Pids : 32'h2, + Fnum : 32'h3, + XdatSize : $bits(cmd_beat_t) // Should be 525, but gets corrupted + }; +endpackage + +module TestMod; + import TestPkg::*; + + initial begin + $display("XdatSize = %d", cb_cfg.XdatSize); + `checkd(cb_cfg.XdatSize, 525); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_bits_iface_typedef.py b/test_regress/t/t_paramgraph_bits_iface_typedef.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_bits_iface_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_bits_iface_typedef.v b/test_regress/t/t_paramgraph_bits_iface_typedef.v new file mode 100644 index 000000000..81cb7e258 --- /dev/null +++ b/test_regress/t/t_paramgraph_bits_iface_typedef.v @@ -0,0 +1,81 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// DESCRIPTION: Test for $bits() of interface typedef used as parameter value +// This reproduces the issue from axis_upsizer.sv:186 +// The issue: $bits(op_pkt_t) where op_pkt_t is a typedef from an interface port +// can't be converted to constant because the PARAMTYPEDTYPE's dtype isn't resolved + +// Interface with a packed struct typedef +interface axis_if #( + parameter int DataWidth = 8 +); + typedef struct packed { + logic [DataWidth-1:0] data; + logic valid; + } pkt_t; + + logic [DataWidth-1:0] tdata; + logic tvalid; + logic tready; + + modport initiator (output tdata, tvalid, input tready); + modport target (input tdata, tvalid, output tready); +endinterface + +// Simple buffer module that takes a width parameter +module skid_buffer #( + parameter int p_width = 8 +) ( + input logic clk, + input logic [p_width-1:0] data_i, + output logic [p_width-1:0] data_o +); + always_ff @(posedge clk) data_o <= data_i; +endmodule + +// Module that uses $bits() of an interface typedef as a parameter +module axis_upsizer #( + parameter int p_has_skid = 1 +) ( + input logic clk, + axis_if.initiator op_io +); + // Typedef from interface port + typedef op_io.pkt_t op_pkt_t; + + op_pkt_t op_pkt_int; + + generate + if (p_has_skid>0) begin : gen_skid + op_pkt_t skid_src_pkt; + + // This is the problematic line - $bits(op_pkt_t) used as parameter + // The PARAMTYPEDTYPE for op_pkt_t has REQUIREDTYPE that needs resolution + skid_buffer #(.p_width($bits(op_pkt_t))) skid ( + .clk(clk), + .data_i(op_pkt_int), + .data_o(skid_src_pkt) + ); + end + endgenerate +endmodule + +module top; + logic clk; + + axis_if #(.DataWidth(32)) op_if(); + + axis_upsizer #(.p_has_skid(1)) u_upsizer ( + .clk(clk), + .op_io(op_if.initiator) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_cloned_refdtype.py b/test_regress/t/t_paramgraph_cloned_refdtype.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_cloned_refdtype.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_cloned_refdtype.v b/test_regress/t/t_paramgraph_cloned_refdtype.v new file mode 100644 index 000000000..92700abdc --- /dev/null +++ b/test_regress/t/t_paramgraph_cloned_refdtype.v @@ -0,0 +1,81 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// DESCRIPTION: Verilator: Test for cloned RefDType classOrPackagep fix +// +// This test verifies that when parameterized classes are cloned, the RefDType +// nodes that reference typedefs within the class get their classOrPackagep +// and typedefp updated to point to the cloned class, not the template class. +// +// This file is part of the Verilator regression test suite. +// + +// A registry class that returns its own type +class uvm_object_registry #(type T = int, string Tname = ""); + typedef uvm_object_registry#(T, Tname) this_type; + + static function this_type get(); + static this_type m_inst; + if (m_inst == null) m_inst = new(); + return m_inst; + endfunction +endclass + +// A pool class that has a nested type_id typedef pointing to the registry +// The key pattern: type_id is a typedef to uvm_object_registry parameterized with THIS class +class uvm_object_string_pool #(type T = int); + typedef uvm_object_string_pool#(T) this_type; + typedef uvm_object_registry#(uvm_object_string_pool#(T)) type_id; + + // This function's return type references type_id - after cloning, + // the RefDType for the return type must point to THIS class's type_id, + // not the template class's type_id + static function type_id get_type(); + return type_id::get(); + endfunction + + static function T get_global(); + this_type gpool = new(); + return gpool.get(); + endfunction + + virtual function T get(); + T result; + return result; + endfunction +endclass + +// Simple wrapper classes to create different specializations +class uvm_queue #(type T = int); +endclass + +class uvm_event #(type T = int); +endclass + +// Create two different specializations of uvm_object_string_pool +// Each should get its own type_id pointing to a different registry specialization +typedef uvm_object_string_pool#(uvm_event#(int)) uvm_event_pool; +typedef uvm_object_string_pool#(uvm_queue#(string)) uvm_queue_pool; + +module t; + initial begin + // Get the type_id::get() for both pool types + // Before the fix, both would incorrectly return the same registry type + // After the fix, each returns its own correctly-specialized registry + + uvm_object_registry#(uvm_object_string_pool#(uvm_event#(int))) event_reg; + uvm_object_registry#(uvm_object_string_pool#(uvm_queue#(string))) queue_reg; + + event_reg = uvm_event_pool::get_type(); + queue_reg = uvm_queue_pool::get_type(); + + if (event_reg != null && queue_reg != null) begin + $write("*-* All Coverage Coverage *-*\n"); + end + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_comined_iface.py b/test_regress/t/t_paramgraph_comined_iface.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_comined_iface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_comined_iface.v b/test_regress/t/t_paramgraph_comined_iface.v new file mode 100644 index 000000000..8f844903e --- /dev/null +++ b/test_regress/t/t_paramgraph_comined_iface.v @@ -0,0 +1,120 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: Verilator: TRULY BLENDED test for interface typedef resolution +// This test BLENDS both patterns into a single interacting structure: +// - Sibling cells (like t_lparam_dep_iface10) +// - Nested interface chains (like aerial_wrap) +// - COMBINED: Sibling cells that EACH contain nested interface chains +// +// The key test: A module accesses typedefs from TWO sibling nested interface +// chains, and each must resolve to the correct parameterized type. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +typedef struct packed { + int unsigned AddrBits; + int unsigned DataBits; + int unsigned IdBits; +} axi_cfg_t; + +// INNERMOST: Parameterized interface with typedefs +interface axi4_if #(parameter axi_cfg_t cfg = 0)(); + localparam int unsigned AddrBits = cfg.AddrBits * 2; + localparam int unsigned DataBits = cfg.DataBits * 2; + localparam int unsigned IdBits = cfg.IdBits * 2; + + typedef logic [AddrBits-1:0] addr_t; + typedef logic [DataBits-1:0] data_t; + typedef logic [IdBits-1:0] id_t; + + typedef struct packed { + id_t id; + addr_t addr; + } ar_chan_t; + + typedef struct packed { + id_t id; + data_t data; + } r_chan_t; + + ar_chan_t ar; + r_chan_t r; +endinterface + +// MIDDLE: Interface that wraps axi4_if and re-exports its typedefs +interface tlb_io_if #(parameter axi_cfg_t axi_cfg = 0)(); + axi4_if #(.cfg(axi_cfg)) axi_tlb_io(); + + // Re-export typedefs from nested interface + typedef axi_tlb_io.r_chan_t r_chan_t; + typedef axi_tlb_io.ar_chan_t ar_chan_t; +endinterface + +// OUTER: Interface with TWO SIBLING tlb_io_if instances with DIFFERENT params +// This is the BLENDED pattern: sibling cells + nested chains +interface cca_io_if #( + parameter axi_cfg_t axi_cfg_a = 0, + parameter axi_cfg_t axi_cfg_b = 0 +)(); + // SIBLING CELLS - same interface type, DIFFERENT params + tlb_io_if #(.axi_cfg(axi_cfg_a)) tlb_io_a(); + tlb_io_if #(.axi_cfg(axi_cfg_b)) tlb_io_b(); + + // Re-export from each sibling (these should be DIFFERENT types) + typedef tlb_io_a.r_chan_t r_chan_a_t; + typedef tlb_io_b.r_chan_t r_chan_b_t; +endinterface + +// MODULE: Accesses typedefs from BOTH sibling nested chains via interface port +// This is the CRITICAL test - must distinguish between tlb_io_a and tlb_io_b +module cca_xbar ( + cca_io_if cca_io +); + // Access typedefs through SIBLING nested interface chains + // These MUST resolve to DIFFERENT types based on the different params + typedef cca_io.tlb_io_a.r_chan_t m_r_chan_a_t; // From axi_cfg_a + typedef cca_io.tlb_io_b.r_chan_t m_r_chan_b_t; // From axi_cfg_b + typedef cca_io.tlb_io_a.ar_chan_t m_ar_chan_a_t; + typedef cca_io.tlb_io_b.ar_chan_t m_ar_chan_b_t; + + m_r_chan_a_t r_data_a; + m_r_chan_b_t r_data_b; + + initial begin + #1; + // axi_cfg_a: AddrBits=32, DataBits=64, IdBits=4 + // r_chan_t = id(4) + data(64) = 68 bits * 2 = 136 bits + // ar_chan_t = id(4) + addr(32) = 36 bits * 2 = 72 bits + `checkd($bits(m_r_chan_a_t), 136); + `checkd($bits(m_ar_chan_a_t), 72); + + // axi_cfg_b: AddrBits=40, DataBits=128, IdBits=8 + // r_chan_t = id(8) + data(128) = 136 bits * 2 = 272 bits + // ar_chan_t = id(8) + addr(40) = 48 bits * 2 = 96 bits + `checkd($bits(m_r_chan_b_t), 272); + `checkd($bits(m_ar_chan_b_t), 96); + end +endmodule + +// TOP MODULE +module t(); + localparam axi_cfg_t cfg_a = '{AddrBits: 32, DataBits: 64, IdBits: 4}; + localparam axi_cfg_t cfg_b = '{AddrBits: 40, DataBits: 128, IdBits: 8}; + + cca_io_if #(.axi_cfg_a(cfg_a), .axi_cfg_b(cfg_b)) cca_io(); + cca_xbar xbar(.cca_io(cca_io)); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_comined_iface_stats.py b/test_regress/t/t_paramgraph_comined_iface_stats.py new file mode 100755 index 000000000..53dbc323b --- /dev/null +++ b/test_regress/t/t_paramgraph_comined_iface_stats.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Stats-variant of t_paramgraph_comined_iface: verifies IfaceCapture +# statistics for combined sibling + nested interface typedef patterns. + +import vltest_bootstrap + +test.scenarios('vlt') + +test.top_filename = "t/t_paramgraph_comined_iface.v" + +test.compile(v_flags2=["--binary --stats"]) + +test.file_grep(test.stats, r'IfaceCapture, Entries total\s+(\d+)', 18) +test.file_grep(test.stats, r'IfaceCapture, Entries template\s+(\d+)', 8) +test.file_grep(test.stats, r'IfaceCapture, Entries cloned\s+(\d+)', 10) +test.file_grep(test.stats, r'IfaceCapture, Ledger fixups in V3Param\s+(\d+)', 10) +test.file_grep(test.stats, r'IfaceCapture, Wrong-clone refs fixed\s+(\d+)', 10) +test.file_grep(test.stats, r'IfaceCapture, Dead refs fixed in modules\s+(\d+)', 6) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_array_ports.py b/test_regress/t/t_paramgraph_iface_array_ports.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_array_ports.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_array_ports.v b/test_regress/t/t_paramgraph_iface_array_ports.v new file mode 100644 index 000000000..be8b6d9bf --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_array_ports.v @@ -0,0 +1,56 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Minimal testcase for depgraph resolution with arrayed interface ports +// and typedefs pulled from interface instances. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package axi_pkg; + typedef struct packed { + int IdBits; + int DataBits; + int UserBits; + } cfg_t; +endpackage + +interface axi4_if #(parameter axi_pkg::cfg_t cfg = '0)(); + typedef logic [cfg.IdBits-1:0] id_t; + typedef logic [cfg.DataBits-1:0] data_t; + typedef logic [cfg.UserBits-1:0] user_t; + + typedef struct packed { + id_t id; + data_t data; + user_t user; + } req_t; +endinterface + +module sink #(parameter int N = 1)(axi4_if tgt_ports [N-1:0]); + localparam type req_t = tgt_ports[0].req_t; + req_t rq; +endmodule + +module top; + localparam axi_pkg::cfg_t cfg = '{IdBits:4, DataBits:32, UserBits:2}; + axi4_if #(.cfg(cfg)) tgt_ports [1:0](); + + sink #(.N(2)) u_sink(.tgt_ports(tgt_ports)); + + initial begin + #1; + `checkd($bits(tgt_ports[0].id_t), 4); + `checkd($bits(tgt_ports[0].data_t), 32); + `checkd($bits(tgt_ports[0].user_t), 2); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_cfg_zero.py b/test_regress/t/t_paramgraph_iface_cfg_zero.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_cfg_zero.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_cfg_zero.v b/test_regress/t/t_paramgraph_iface_cfg_zero.v new file mode 100644 index 000000000..5efae55e5 --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_cfg_zero.v @@ -0,0 +1,49 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +// DESCRIPTION: +// Minimal testcase for depgraph interface typedef resolution +// Derived from aicc_types_if/axis_if ASCRANGE warnings +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package aerial; + typedef struct packed { + int NumCc; + int CCNumWaves; + int CCNumIds; + } cfg_t; +endpackage + +interface aicc_types_if #(parameter aerial::cfg_t cfg = '0)(); + typedef logic [$clog2(cfg.NumCc)-1:0] cc_index_t; + typedef logic [$clog2(cfg.CCNumIds)-1:0] trans_id_t; +endinterface + +module child(aicc_types_if types); + localparam type cc_index_t = types.cc_index_t; + localparam type trans_id_t = types.trans_id_t; + cc_index_t cc_idx; + trans_id_t tr_id; +endmodule + +module top; + localparam aerial::cfg_t aer_cfg = '{NumCc:4, CCNumWaves:2, CCNumIds:8}; + aicc_types_if #(.cfg(aer_cfg)) types(); + child u_child(.types(types)); + + initial begin + #2; + `checkd($bits(types.cc_index_t), 2); + `checkd($bits(types.trans_id_t), 3); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_deadmod.py b/test_regress/t/t_paramgraph_iface_deadmod.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_deadmod.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_deadmod.v b/test_regress/t/t_paramgraph_iface_deadmod.v new file mode 100644 index 000000000..e09cb446a --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_deadmod.v @@ -0,0 +1,61 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Minimal testcase to see if unused modules with interface ports +// still trigger ASCRANGE when interface params are defaulted. +// + +package axi4; + typedef struct packed { + int IdBits; + int AddrBits; + int DataBits; + int UserBits; + } cfg_t; +endpackage + +interface axi4_if #(parameter axi4::cfg_t cfg = '0)(); + typedef logic [cfg.AddrBits-1:0] addr_t; + typedef logic [cfg.DataBits-1:0] data_t; + typedef logic [cfg.DataBits/8-1:0] strb_t; + typedef logic [cfg.UserBits-1:0] user_t; + typedef logic [cfg.IdBits-1:0] id_t; + + typedef struct packed { + id_t id; + addr_t addr; + user_t user; + } aw_chan_t; +endinterface + +module dead_mod( + axi4_if axi_io +); + typedef axi_io.addr_t addr_t; + typedef axi_io.data_t data_t; + typedef axi_io.strb_t strb_t; + + addr_t addr_d; + data_t data_d; + strb_t strb_d; +endmodule + +module dead_top; + localparam axi4::cfg_t cfg = '{IdBits:4, AddrBits:32, DataBits:64, UserBits:2}; + axi4_if #(.cfg(cfg)) axi_io(); + + dead_mod u_dead(.axi_io(axi_io)); +endmodule + +module top; + dead_top dead_top(); + initial begin + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_dependency1.py b/test_regress/t/t_paramgraph_iface_dependency1.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_dependency1.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_dependency1.v b/test_regress/t/t_paramgraph_iface_dependency1.v new file mode 100644 index 000000000..a1dcc8e6e --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_dependency1.v @@ -0,0 +1,55 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package a_pkg; + typedef struct packed { + int unsigned a; + } cfg_t; +endpackage + +interface depgraph_if #(a_pkg::cfg_t cfg=0)(); + typedef logic [cfg.a-1:0] byte_t; + typedef struct packed { + byte_t a; + } pair_t; +endinterface + +module a_mod( + depgraph_if ifc +); + typedef ifc.pair_t pair_t; + + localparam p_a = $bits(pair_t); + + initial begin + #1; + `checkd($bits(pair_t),8); + `checkd(p_a, 8); + end +endmodule + +module t(); + localparam a_pkg::cfg_t cfg = '{ + a: 8 + }; + + depgraph_if #(cfg) ifc(); + a_mod #() a_mod_0( + .ifc(ifc) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_dependency2.py b/test_regress/t/t_paramgraph_iface_dependency2.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_dependency2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_dependency2.v b/test_regress/t/t_paramgraph_iface_dependency2.v new file mode 100644 index 000000000..5f8160bbc --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_dependency2.v @@ -0,0 +1,57 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package a_pkg; + typedef struct packed { + int unsigned a; + } cfg_t; +endpackage + +package b_pkg; + typedef struct packed { + int unsigned a; + } cfg_t; +endpackage + +interface depgraph_if #(a_pkg::cfg_t cfg=0)(); + typedef logic [cfg.a-1:0] byte_t; + typedef logic [cfg.a*2-1:0] half_t; + typedef struct packed { + byte_t a; + half_t b; + } pair_t; + typedef union packed { + pair_t p; + logic [23:0] flat; + } pair_u_t; +endinterface + +module t(); + localparam a_pkg::cfg_t cfg = '{ + a: 8 + }; + + depgraph_if #(cfg) ifc(); + + typedef ifc.pair_u_t pair_u_t; + + localparam b_pkg::cfg_t cfg_b = '{ + a:$bits(pair_u_t) + }; + + initial begin + #2; + `checkd(cfg_b.a, 24); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_dependency3.py b/test_regress/t/t_paramgraph_iface_dependency3.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_dependency3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_dependency3.v b/test_regress/t/t_paramgraph_iface_dependency3.v new file mode 100644 index 000000000..266e56b95 --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_dependency3.v @@ -0,0 +1,74 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package a_pkg; + typedef struct packed { + int unsigned a; + } cfg_t; +endpackage + +package b_pkg; + typedef struct packed { + int unsigned a; + } cfg_t; +endpackage + +interface depgraph_if #(a_pkg::cfg_t cfg=0)(); + typedef logic [cfg.a-1:0] byte_t; + typedef logic [cfg.a*2-1:0] half_t; + typedef struct packed { + byte_t a; + half_t b; + } pair_t; +endinterface + +module a_mod( + depgraph_if ifc +); + typedef ifc.pair_t pair_t; + typedef ifc.half_t half_t; + + localparam p_a = $bits(pair_t); + localparam p_b = $bits(half_t); + + initial begin + #1; + `checkd($bits(pair_t),24); + `checkd(p_a, 24); + `checkd(p_b, 16); + end +endmodule + +module t(); + localparam a_pkg::cfg_t cfg = '{ + a: 8 + }; + + depgraph_if #(cfg) ifc(); + + typedef ifc.byte_t byte_t; + + a_mod #() a_mod_0( + .ifc(ifc) + ); + + localparam b_pkg::cfg_t cfg_b = '{ + a:$bits(byte_t) + }; + + initial begin + #2; + `checkd(cfg_b.a, 8); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_param_from_port.py b/test_regress/t/t_paramgraph_iface_param_from_port.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_param_from_port.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_param_from_port.v b/test_regress/t/t_paramgraph_iface_param_from_port.v new file mode 100644 index 000000000..a6f664b38 --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_param_from_port.v @@ -0,0 +1,66 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Regression for interface instances parameterized by interface-port params. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package cfg_pkg; + typedef struct packed { + int DataWidth; + int IdWidth; + } cfg_t; +endpackage + +interface types_if #(parameter cfg_pkg::cfg_t cfg = '0)(); + typedef logic [cfg.DataWidth-1:0] data_t; + typedef logic [cfg.IdWidth-1:0] id_t; +endinterface + +interface bus_if #(parameter cfg_pkg::cfg_t cfg = '0)(); + types_if #(cfg) types(); + typedef types.data_t data_t; + typedef types.id_t id_t; +endinterface + +module child(bus_if io, output int data_w, output int id_w); + types_if #(io.cfg) port_types(); + typedef port_types.data_t p_data_t; + typedef port_types.id_t p_id_t; + assign data_w = $bits(p_data_t); + assign id_w = $bits(p_id_t); +endmodule + +module top; + localparam cfg_pkg::cfg_t cfg0 = '{DataWidth:32, IdWidth:4}; + localparam cfg_pkg::cfg_t cfg1 = '{DataWidth:64, IdWidth:6}; + + bus_if #(cfg0) bus0(); + bus_if #(cfg1) bus1(); + + int data_w0; + int id_w0; + int data_w1; + int id_w1; + + child u0(.io(bus0), .data_w(data_w0), .id_w(id_w0)); + child u1(.io(bus1), .data_w(data_w1), .id_w(id_w1)); + + initial begin + #1; + `checkd(data_w0, 32); + `checkd(id_w0, 4); + `checkd(data_w1, 64); + `checkd(id_w1, 6); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_pin.py b/test_regress/t/t_paramgraph_iface_pin.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_pin.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_pin.v b/test_regress/t/t_paramgraph_iface_pin.v new file mode 100644 index 000000000..7d1c3d6ab --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_pin.v @@ -0,0 +1,62 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package a_pkg; + typedef struct packed { + int unsigned a; + } cfg_t; +endpackage + +interface depgraph_if #(a_pkg::cfg_t cfg=0)(); + typedef logic [cfg.a-1:0] byte_t; + typedef logic [2*cfg.a-1:0] half_t; + typedef struct packed { + byte_t a; + half_t b; + } pair_t; +endinterface + +module a_mod( + depgraph_if ifc +); + typedef ifc.byte_t byte_t; + typedef ifc.pair_t pair_t; + + pair_t p; + logic [23:0] flat; + + assign flat = {p.a, p.b}; + + initial begin + #1; + `checkd($bits(byte_t), 8); + `checkd($bits(pair_t),24); + `checkd($bits(flat), 24); + end +endmodule + +module t(); + localparam a_pkg::cfg_t cfg = '{ + a:8 + }; + + depgraph_if #(cfg) ifc(); + a_mod #() a_mod_0( + .ifc(ifc) + ); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_port_typedef.py b/test_regress/t/t_paramgraph_iface_port_typedef.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_port_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_port_typedef.v b/test_regress/t/t_paramgraph_iface_port_typedef.v new file mode 100644 index 000000000..99d9050e8 --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_port_typedef.v @@ -0,0 +1,53 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Minimal testcase for depgraph interface typedef resolution through +// interface ports connected to specialized interface instances. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package acme_pkg; + typedef struct packed { + int DataBits; + } cfg_t; +endpackage + +interface acme_if #(parameter acme_pkg::cfg_t cfg = '0)(); + typedef logic [cfg.DataBits-1:0] data_t; +endinterface + +module child(acme_if io, output int width_o); + typedef io.data_t data_t; + data_t payload; + assign width_o = $bits(data_t); +endmodule + +module top; + localparam acme_pkg::cfg_t cfg0 = '{DataBits:32}; + localparam acme_pkg::cfg_t cfg1 = '{DataBits:64}; + + acme_if #(cfg0) io0(); + acme_if #(cfg1) io1(); + + int width0; + int width1; + + child u0(.io(io0), .width_o(width0)); + child u1(.io(io1), .width_o(width1)); + + initial begin + #1; + `checkd(width0, 32); + `checkd(width1, 64); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch.py b/test_regress/t/t_paramgraph_iface_template_mismatch.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_template_mismatch.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch.v b/test_regress/t/t_paramgraph_iface_template_mismatch.v new file mode 100644 index 000000000..92e39e58a --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_template_mismatch.v @@ -0,0 +1,68 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Minimal testcase for depgraph interface typedef mismatch between +// template and specialized interface instances. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package axi4l; + typedef struct packed { + int AddrBits; + int DataBits; + int UserBits; + } cfg_t; +endpackage + +interface axi4l_if #(parameter axi4l::cfg_t cfg = '0)(); + typedef logic [cfg.AddrBits-1:0] addr_t; + typedef logic [cfg.DataBits-1:0] data_t; + typedef logic [cfg.DataBits/8-1:0] strb_t; + typedef logic [cfg.UserBits-1:0] user_t; +endinterface + +module ccom_to_axi( + axi4l_if axil_tgt_io +); + typedef axil_tgt_io.addr_t addr_t; + typedef axil_tgt_io.data_t data_t; + typedef axil_tgt_io.strb_t strb_t; + + addr_t addr_q; + data_t data_q; + strb_t strb_q; +endmodule + +module dummy_consumer(axi4l_if axil_io); + typedef axil_io.data_t data_t; + data_t sink; +endmodule + +module top; + localparam axi4l::cfg_t cfg = '{AddrBits:32, DataBits:64, UserBits:2}; + + // Live specialized instance used elsewhere. + axi4l_if #(.cfg(cfg)) axil_live(); + dummy_consumer u_consume(.axil_io(axil_live)); + + // Template/default instance used in ccom_to_axi. + axi4l_if #(cfg) axil_tgt_io(); + ccom_to_axi u_ccom_to_axi(.axil_tgt_io(axil_tgt_io)); + + initial begin + #1; + `checkd($bits(axil_live.addr_t), 32); + `checkd($bits(axil_live.data_t), 64); + `checkd($bits(axil_live.strb_t), 8); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch2.py b/test_regress/t/t_paramgraph_iface_template_mismatch2.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_template_mismatch2.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch2.v b/test_regress/t/t_paramgraph_iface_template_mismatch2.v new file mode 100644 index 000000000..394354d4a --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_template_mismatch2.v @@ -0,0 +1,68 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Variant testcase that avoids ASCRANGE by giving the template interface +// a nonzero default, while still detecting template-vs-specialized mixups. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package axi4l; + typedef struct packed { + int AddrBits; + int DataBits; + int UserBits; + } cfg_t; +endpackage + +interface axi4l_if #(parameter axi4l::cfg_t cfg = '{AddrBits:4, DataBits:16, UserBits:1})(); + typedef logic [cfg.AddrBits-1:0] addr_t; + typedef logic [cfg.DataBits-1:0] data_t; + typedef logic [cfg.DataBits/8-1:0] strb_t; + typedef logic [cfg.UserBits-1:0] user_t; +endinterface + +module ccom_to_axi( + axi4l_if axil_tgt_io +); + typedef axil_tgt_io.addr_t addr_t; + typedef axil_tgt_io.data_t data_t; + typedef axil_tgt_io.strb_t strb_t; + + addr_t addr_q; + data_t data_q; + strb_t strb_q; +endmodule + +module dummy_consumer(axi4l_if axil_io); + typedef axil_io.data_t data_t; + data_t sink; +endmodule + +module top; + localparam axi4l::cfg_t cfg = '{AddrBits:32, DataBits:64, UserBits:2}; + + // Live specialized instance used elsewhere. + axi4l_if #(.cfg(cfg)) axil_live(); + dummy_consumer u_consume(.axil_io(axil_live)); + + // Template/default instance used in ccom_to_axi. + axi4l_if #(cfg) axil_tgt_io(); + ccom_to_axi u_ccom_to_axi(.axil_tgt_io(axil_tgt_io)); + + initial begin + #1; + `checkd($bits(axil_live.addr_t), 32); + `checkd($bits(axil_live.data_t), 64); + `checkd($bits(axil_live.strb_t), 8); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch3.py b/test_regress/t/t_paramgraph_iface_template_mismatch3.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_template_mismatch3.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch3.v b/test_regress/t/t_paramgraph_iface_template_mismatch3.v new file mode 100644 index 000000000..2ab9ca006 --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_template_mismatch3.v @@ -0,0 +1,59 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Minimal testcase for depgraph interface typedef mismatch between +// template and specialized interface instances. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package axi4l; + typedef struct packed { + int DataBits; + } cfg_t; +endpackage + +interface axi4l_if #(parameter axi4l::cfg_t cfg = '0)(); + typedef logic [cfg.DataBits-1:0] data_t; +endinterface + +module ccom_to_axi( + axi4l_if axil_tgt_io +); + typedef axil_tgt_io.data_t data_t; + + data_t data_q; +endmodule + +module dummy_consumer(axi4l_if axil_io); + typedef axil_io.data_t data_t; + data_t sink; +endmodule + +module top; + localparam axi4l::cfg_t cfg = '{ + DataBits:64//, + }; + + // Live specialized instance used elsewhere. + axi4l_if #(.cfg(cfg)) axil_live(); + dummy_consumer u_consume(.axil_io(axil_live)); + + // Template/default instance used in ccom_to_axi. + axi4l_if #(cfg) axil_tgt_io(); + ccom_to_axi u_ccom_to_axi(.axil_tgt_io(axil_tgt_io)); + + initial begin + #1; + `checkd($bits(axil_live.data_t), 64); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_template_nested.py b/test_regress/t/t_paramgraph_iface_template_nested.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_template_nested.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_iface_template_nested.v b/test_regress/t/t_paramgraph_iface_template_nested.v new file mode 100644 index 000000000..ea2c99090 --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_template_nested.v @@ -0,0 +1,72 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Minimal testcase for depgraph interface typedef resolution with +// deep interface nesting and specialized parameter overrides. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package acme_pkg; + typedef struct packed { + int DataBits; + } cfg_t; +endpackage + +interface acme_types_if #(parameter acme_pkg::cfg_t cfg = '0)(); + typedef logic [cfg.DataBits-1:0] data_t; +endinterface + +interface acme_tb_if #(parameter acme_pkg::cfg_t cfg = '0)(); + acme_types_if #(cfg) acme_types(); + typedef acme_types.data_t data_t; + data_t payload; +endinterface + +interface acme_if #(parameter acme_pkg::cfg_t cfg = '0)(); + acme_tb_if #(cfg) rq_tb_io_i(); + acme_types_if #(cfg) acme_types(); + typedef acme_types.data_t data_t; + data_t passthru; +endinterface + +interface acme_wrap_if #(parameter acme_pkg::cfg_t cfg = '0)(); + acme_if #(cfg) acme_io(); + typedef acme_io.data_t data_t; + data_t leaf; +endinterface + +module consumer(acme_wrap_if wrap_io); + typedef wrap_io.data_t data_t; + data_t sink; +endmodule + +module top; + localparam acme_pkg::cfg_t cfg0 = '{ + DataBits:64 + }; + localparam acme_pkg::cfg_t cfg1 = '{ + DataBits:128 + }; + + acme_wrap_if #(cfg0) wrap0(); + acme_wrap_if #(cfg1) wrap1(); + + consumer u_consume0(.wrap_io(wrap0)); + consumer u_consume1(.wrap_io(wrap1)); + + initial begin + #1; + `checkd($bits(wrap0.data_t), 64); + `checkd($bits(wrap1.data_t), 128); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_iface_template_nested_stats.py b/test_regress/t/t_paramgraph_iface_template_nested_stats.py new file mode 100755 index 000000000..d2e824e70 --- /dev/null +++ b/test_regress/t/t_paramgraph_iface_template_nested_stats.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Stats-variant of t_paramgraph_iface_template_nested: verifies IfaceCapture +# statistics for deeply nested interface typedef chains with clone propagation. + +import vltest_bootstrap + +test.scenarios('vlt') + +test.top_filename = "t/t_paramgraph_iface_template_nested.v" + +test.compile(v_flags2=["--binary --stats"]) + +test.file_grep(test.stats, r'IfaceCapture, Entries total\s+(\d+)', 21) +test.file_grep(test.stats, r'IfaceCapture, Entries template\s+(\d+)', 11) +test.file_grep(test.stats, r'IfaceCapture, Entries cloned\s+(\d+)', 10) +test.file_grep(test.stats, r'IfaceCapture, Ledger fixups in V3Param\s+(\d+)', 8) +test.file_grep(test.stats, r'IfaceCapture, Wrong-clone refs fixed\s+(\d+)', 8) +test.file_grep(test.stats, r'IfaceCapture, Dead refs fixed in modules\s+(\d+)', 3) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_member_refdtype.py b/test_regress/t/t_paramgraph_member_refdtype.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_member_refdtype.v b/test_regress/t/t_paramgraph_member_refdtype.v new file mode 100644 index 000000000..de05b93d5 --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype.v @@ -0,0 +1,34 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +typedef logic [7:0] byte_t; + +typedef struct packed { + byte_t a; + byte_t b; +} pair_t; + +module t_paramgraph_member_refdtype; + pair_t p; + logic [15:0] flat; + + assign flat = {p.a, p.b}; + + initial begin + #1; + `checkd($bits(byte_t), 8); + `checkd($bits(pair_t), 16); + `checkd($bits(flat), 16); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_chain.py b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v new file mode 100644 index 000000000..3ca551d2b --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v @@ -0,0 +1,40 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface depgraph_if; + typedef logic [7:0] byte_t; +endinterface + +module t_paramgraph_member_refdtype_iface_chain; + depgraph_if ifc(); + + typedef ifc.byte_t byte_t; + typedef byte_t byte_t2; + typedef struct packed { + byte_t2 a; + byte_t2 b; + } pair_t; + + pair_t p; + logic [15:0] flat; + + assign flat = {p.a, p.b}; + + initial begin + #1; + `checkd($bits(byte_t), 8); + `checkd($bits(byte_t2), 8); + `checkd($bits(pair_t), 16); + `checkd($bits(flat), 16); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_struct.py b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v new file mode 100644 index 000000000..f38a8a755 --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v @@ -0,0 +1,40 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface depgraph_if; + typedef logic [7:0] byte_t; + typedef struct packed { + byte_t a; + byte_t b; + } pair_t; +endinterface + +module t_paramgraph_member_refdtype_iface_struct; + depgraph_if ifc(); + + typedef ifc.byte_t byte_t; + typedef ifc.pair_t pair_t; + + pair_t p; + logic [15:0] flat; + + assign flat = {p.a, p.b}; + + initial begin + #1; + `checkd($bits(byte_t), 8); + `checkd($bits(pair_t), 16); + `checkd($bits(flat), 16); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.py b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v new file mode 100644 index 000000000..dfd79a819 --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v @@ -0,0 +1,39 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface depgraph_if; + typedef logic [7:0] byte_t; +endinterface + +module t_paramgraph_member_refdtype_iface_typedef; + depgraph_if ifc(); + + typedef ifc.byte_t byte_t; + typedef struct packed { + byte_t a; + byte_t b; + } pair_t; + + pair_t p; + logic [15:0] flat; + + assign flat = {p.a, p.b}; + + initial begin + #1; + `checkd($bits(byte_t), 8); + `checkd($bits(pair_t), 16); + `checkd($bits(flat), 16); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.py b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v new file mode 100644 index 000000000..8297b7179 --- /dev/null +++ b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v @@ -0,0 +1,50 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package paramgraph_pkg; + typedef struct packed { + int unsigned a; + } cfg_t; +endpackage + +interface paramgraph_if #(paramgraph_pkg::cfg_t cfg=0)(); + typedef logic [cfg.a-1:0] byte_t; + typedef struct packed { + byte_t a; + byte_t b; + } pair_t; +endinterface + +module t_paramgraph_member_refdtype_pkg_iface; + localparam paramgraph_pkg::cfg_t cfg = '{ + a: 8 + }; + + paramgraph_if #(cfg) ifc(); + + typedef ifc.byte_t byte_t; + typedef ifc.pair_t pair_t; + + pair_t p; + logic [15:0] flat; + + assign flat = {p.a, p.b}; + + initial begin + #1; + `checkd($bits(byte_t), 8); + `checkd($bits(pair_t), 16); + `checkd($bits(flat), 16); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_minimal_sibling.py b/test_regress/t/t_paramgraph_minimal_sibling.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_minimal_sibling.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_minimal_sibling.v b/test_regress/t/t_paramgraph_minimal_sibling.v new file mode 100644 index 000000000..e3d8cd042 --- /dev/null +++ b/test_regress/t/t_paramgraph_minimal_sibling.v @@ -0,0 +1,62 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// DESCRIPTION: Minimal test for sibling interface typedef resolution +// This is the SIMPLEST case that demonstrates the t_lparam_dep_iface10 failure pattern: +// - Two sibling cells of the same interface type with DIFFERENT parameters +// - A module that accesses typedefs from BOTH siblings +// + +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); + +// Parameterized interface with a typedef that depends on the parameter +interface a_if #(parameter int WIDTH = 8)(); + localparam LP_WIDTH = WIDTH*2; + typedef logic [LP_WIDTH-1:0] data_t; + data_t data; +endinterface + +// Wrapper interface with TWO SIBLING instances of a_if with DIFFERENT widths +interface wrapper_if #(parameter int WIDTH_A = 8, parameter int WIDTH_B = 16)(); + a_if #(.WIDTH(WIDTH_A)) a_inst(); + a_if #(.WIDTH(WIDTH_B)) b_inst(); + + // Re-export typedefs from each sibling + typedef a_inst.data_t a_data_t; + typedef b_inst.data_t b_data_t; +endinterface + +// Module that accesses typedefs from BOTH siblings via interface port +module consumer ( + wrapper_if wif +); + // These MUST resolve to DIFFERENT types + typedef wif.a_inst.data_t local_a_t; // Should be 10 bits + typedef wif.b_inst.data_t local_b_t; // Should be 20 bits + + local_a_t val_a; + local_b_t val_b; + + initial begin + #1; + `checkd($bits(local_a_t), 20); + `checkd($bits(local_b_t), 40); + end +endmodule + +// Top module +module t(); + wrapper_if #(.WIDTH_A(10), .WIDTH_B(20)) wif(); + consumer c(.wif(wif)); + + initial begin + #2; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_nested_iface_typedef.py b/test_regress/t/t_paramgraph_nested_iface_typedef.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_nested_iface_typedef.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_nested_iface_typedef.v b/test_regress/t/t_paramgraph_nested_iface_typedef.v new file mode 100644 index 000000000..77cf1ca1b --- /dev/null +++ b/test_regress/t/t_paramgraph_nested_iface_typedef.v @@ -0,0 +1,122 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// DESCRIPTION: Verilator: Test nested interface typedef access +// This replicates the pattern from a much larger design that was +// failing with the localparam changes - accessing a typedef from +// a doubly-nested interface +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +typedef struct packed { + int unsigned AddrBits; + int unsigned DataBits; + int unsigned IdBits; + int unsigned UserBits; +} axi_cfg_t; + +// Innermost interface - like axi4_if.sv in the real design +interface axi4_if #(parameter axi_cfg_t cfg = '{32, 64, 4, 0})(); + typedef logic [cfg.AddrBits-1:0] addr_t; + typedef logic [cfg.DataBits-1:0] data_t; + typedef logic [cfg.IdBits-1:0] id_t; + typedef logic [cfg.UserBits-1:0] user_t; + typedef logic [cfg.DataBits/8-1:0] strb_t; + + // AXI channel typedef + typedef struct packed { + id_t id; + addr_t addr; + logic [7:0] len; + } ar_chan_t; + + typedef struct packed { + id_t id; + data_t data; + logic [1:0] resp; + logic last; + } r_chan_t; + + ar_chan_t ar; + r_chan_t r; +endinterface + +// Middle interface - wraps the AXI interface +interface tlb_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); + axi4_if #(.cfg(axi_cfg)) axi_tlb_io(); + + // Capture typedef from nested interface + typedef axi_tlb_io.r_chan_t r_chan_t; + typedef axi_tlb_io.ar_chan_t ar_chan_t; +endinterface + +// Outer interface - contains the middle interface +interface cca_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); + tlb_io_if #(.axi_cfg(axi_cfg)) tlb_io(); + + // Capture typedef from doubly-nested interface + typedef tlb_io.r_chan_t r_chan_t; + typedef tlb_io.ar_chan_t ar_chan_t; +endinterface + +// Module that uses the doubly-nested typedef - this is where the error occurred +module cca_xbar #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})( + cca_io_if cca_io +); + // This line was causing "Internal Error: Unlinked" before the fix + // because cca_io.tlb_io.r_chan_t references a typedef from a nested interface + typedef cca_io.tlb_io.r_chan_t m_r_chan_t; + typedef cca_io.tlb_io.ar_chan_t m_ar_chan_t; + + m_r_chan_t r_data; + m_ar_chan_t ar_data; + + initial begin + // Verify the typedef resolved correctly - compare against the actual interface signal + `checkd($bits(m_r_chan_t), $bits(cca_io.tlb_io.axi_tlb_io.r)); + `checkd($bits(m_ar_chan_t), $bits(cca_io.tlb_io.axi_tlb_io.ar)); + + // Verify width matches expected formula based on axi_cfg parameter + // r_chan_t = id(IdBits) + data(DataBits) + resp(2) + last(1) + // ar_chan_t = id(IdBits) + addr(AddrBits) + len(8) + `checkd($bits(m_r_chan_t), axi_cfg.IdBits + axi_cfg.DataBits + 2 + 1); + `checkd($bits(m_ar_chan_t), axi_cfg.IdBits + axi_cfg.AddrBits + 8); + end +endmodule + +module t(); + localparam axi_cfg_t cfg1 = '{AddrBits: 32, DataBits: 64, IdBits: 4, UserBits: 2}; + localparam axi_cfg_t cfg2 = '{AddrBits: 40, DataBits: 128, IdBits: 8, UserBits: 4}; + + // Instantiate outer interface + cca_io_if #(.axi_cfg(cfg1)) cca_io1(); + cca_io_if #(.axi_cfg(cfg2)) cca_io2(); + + // Instantiate modules that use doubly-nested typedefs + cca_xbar #(.axi_cfg(cfg1)) xbar1(.cca_io(cca_io1)); + cca_xbar #(.axi_cfg(cfg2)) xbar2(.cca_io(cca_io2)); + + // Also test direct typedef access in top module + typedef cca_io1.tlb_io.r_chan_t top_r_chan_t; + typedef cca_io2.tlb_io.ar_chan_t top_ar_chan_t; + + initial begin + #1; + // cfg1: DataBits=64, IdBits=4 -> r_chan_t = 4+64+2+1 = 71 + `checkd($bits(top_r_chan_t), 71); + // cfg2: AddrBits=40, IdBits=8 -> ar_chan_t = 8+40+8 = 56 + `checkd($bits(top_ar_chan_t), 56); + + #1; + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_nested_iface_typedef_stats.py b/test_regress/t/t_paramgraph_nested_iface_typedef_stats.py new file mode 100755 index 000000000..4bcad9664 --- /dev/null +++ b/test_regress/t/t_paramgraph_nested_iface_typedef_stats.py @@ -0,0 +1,30 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Stats-variant of t_paramgraph_nested_iface_typedef: verifies IfaceCapture +# statistics for nested interface typedefs with dead-ref fixup and clone propagation. + +import vltest_bootstrap + +test.scenarios('vlt') + +test.top_filename = "t/t_paramgraph_nested_iface_typedef.v" + +test.compile(v_flags2=["--binary --stats"]) + +test.file_grep(test.stats, r'IfaceCapture, Entries total\s+(\d+)', 18) +test.file_grep(test.stats, r'IfaceCapture, Entries template\s+(\d+)', 8) +test.file_grep(test.stats, r'IfaceCapture, Entries cloned\s+(\d+)', 10) +test.file_grep(test.stats, r'IfaceCapture, Ledger fixups in V3Param\s+(\d+)', 12) +test.file_grep(test.stats, r'IfaceCapture, Wrong-clone refs fixed\s+(\d+)', 12) +test.file_grep(test.stats, r'IfaceCapture, Dead refs fixed in modules\s+(\d+)', 10) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_param_not_const.py b/test_regress/t/t_paramgraph_param_not_const.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_param_not_const.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_param_not_const.v b/test_regress/t/t_paramgraph_param_not_const.v new file mode 100644 index 000000000..51569f711 --- /dev/null +++ b/test_regress/t/t_paramgraph_param_not_const.v @@ -0,0 +1,78 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// DESCRIPTION: Verilator: Test nested interface typedef access +// This replicates the pattern from a much larger design that was +// failing with the localparam changes - accessing a typedef from +// a doubly-nested interface +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package cb; + typedef struct packed { + logic [31:0] Rids; + logic [31:0] Pids; + logic [31:0] Fnum; + logic [31:0] XdatSize; + } cfg_t; +endpackage + +package a_pkg; + typedef struct packed { + int unsigned p_a; + int unsigned p_b; + } cfg_t; +endpackage + +interface other_types_if #(parameter a_pkg::cfg_t cfg=0)(); + // Create a struct that results in 525 bits + typedef struct packed { + logic [cfg.p_a-1:0] field1; + logic [cfg.p_b-1:0] field2; + } cmd_beat_t; + +endinterface + +// Simple interface that takes a parameter +interface simple_if #(parameter cb::cfg_t cfg=0)(); + logic [cfg.Rids-1:0] rids; + logic [cfg.Pids-1:0] pids; + logic [cfg.Fnum-1:0] fnum; + logic [cfg.XdatSize-1:0] xdat; +endinterface + +module TestMod; + localparam a_pkg::cfg_t ot_cfg = '{ + p_a : 8, + p_b : 4 + }; + + other_types_if #(ot_cfg) other_types(); + + typedef other_types.cmd_beat_t cmd_beat_t; + + // This pattern assignment should work correctly + localparam cb::cfg_t cb_cfg = '{ + Rids : 32'h1, + Pids : 32'h2, + Fnum : 32'h3, + XdatSize : $bits(cmd_beat_t) + }; + + // This should trigger the error - cb_cfg is not recognized as constant + simple_if#(cb_cfg) cb_vc0_io(); + + initial begin + `checkd(cb_cfg.XdatSize, 12); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_paramtype_cast.py b/test_regress/t/t_paramgraph_paramtype_cast.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_paramtype_cast.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_paramtype_cast.v b/test_regress/t/t_paramgraph_paramtype_cast.v new file mode 100644 index 000000000..41f30ac8f --- /dev/null +++ b/test_regress/t/t_paramgraph_paramtype_cast.v @@ -0,0 +1,32 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// DESCRIPTION: Verilator: Test nested interface typedef access +// This replicates the pattern from a much larger design that was +// failing with the localparam changes - accessing a typedef from +// a doubly-nested interface +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package TestPkg; + localparam type addr_t = logic [11:0]; + localparam addr_t STATUS = addr_t'('ha5); +endpackage + +module TestMod; + import TestPkg::*; + + initial begin + `checkd(STATUS, 'ha5); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_paramtype_default.py b/test_regress/t/t_paramgraph_paramtype_default.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_paramtype_default.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_paramtype_default.v b/test_regress/t/t_paramgraph_paramtype_default.v new file mode 100644 index 000000000..8e4bf9ec5 --- /dev/null +++ b/test_regress/t/t_paramgraph_paramtype_default.v @@ -0,0 +1,69 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// DESCRIPTION: Verilator: Test for REQUIREDTYPE resolution with default type parameters +// +// This test verifies that modules with `parameter type T = logic` work correctly +// when instantiated WITHOUT overriding the type parameter (using the default). +// + +// Simple type flop - parameterized by type T with default = logic +module tflop #(parameter type T = logic) ( + input logic clk, + input logic reset, + input T reset_strap_i, + output T q_o, + input T d_i +); + always_ff @(posedge clk) begin + if (reset) begin + q_o <= reset_strap_i; + end else begin + q_o <= d_i; + end + end +endmodule + +// Module that uses tflop with DEFAULT type parameter (T = logic) +module user_mod ( + input logic clk, + input logic reset +); + logic d_in, d_out; + + // Use tflop with default type parameter T = logic + // This should NOT create a specialized clone - it reuses the template + tflop vld_reg ( + .clk(clk), + .reset(reset), + .reset_strap_i(1'b0), + .q_o(d_out), + .d_i(d_in) + ); + + initial begin + d_in = 1'b1; + #10; + $display("d_out = %b", d_out); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module t; + logic clk = 0; + logic reset = 1; + + user_mod uut (.clk(clk), .reset(reset)); + + initial begin + #5 reset = 0; + #10 clk = 1; + #10 clk = 0; + #10 $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_paramtype_range.py b/test_regress/t/t_paramgraph_paramtype_range.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_paramtype_range.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_paramtype_range.v b/test_regress/t/t_paramgraph_paramtype_range.v new file mode 100644 index 000000000..54e1350ed --- /dev/null +++ b/test_regress/t/t_paramgraph_paramtype_range.v @@ -0,0 +1,34 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Regression for localparam-derived cfg structs feeding interface instances +// and their nested typedefs. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package TestPkg; + localparam type tm_region_t = logic [1:0]; +endpackage + +module TestMod; + import TestPkg::*; + + // This should work - tm_region_t has width 2 + localparam tm_region_t tm_region_lsio = 2'b10; + + // Test logic + initial begin + $display("tm_region_lsio = %b", tm_region_lsio); + `checkd(tm_region_lsio, 2); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_refdtype_iface.py b/test_regress/t/t_paramgraph_refdtype_iface.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_refdtype_iface.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_refdtype_iface.v b/test_regress/t/t_paramgraph_refdtype_iface.v new file mode 100644 index 000000000..0577c5b43 --- /dev/null +++ b/test_regress/t/t_paramgraph_refdtype_iface.v @@ -0,0 +1,39 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Regression for localparam-derived cfg structs feeding interface instances +// and their nested typedefs. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +interface depgraph_if; + typedef logic [3:0] nibble_t; +endinterface + +module depgraph_top; + depgraph_if ifc(); + + typedef ifc.nibble_t nibble_t; + + nibble_t a; + nibble_t b; + logic [3:0] sum; + + assign sum = a + b; + + initial begin + #1; + `checkd($bits(nibble_t), 4); + `checkd($bits(sum), 4); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_refdtype_unlinked.py b/test_regress/t/t_paramgraph_refdtype_unlinked.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_refdtype_unlinked.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_refdtype_unlinked.v b/test_regress/t/t_paramgraph_refdtype_unlinked.v new file mode 100644 index 000000000..b490eaa41 --- /dev/null +++ b/test_regress/t/t_paramgraph_refdtype_unlinked.v @@ -0,0 +1,46 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// Test case for REFDTYPE not linked to type +// This reproduces the error where a REFDTYPE in a parameter expression +// is not properly linked to its type after DepGraph resolution + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package Include; + typedef logic [11:0] mbox_addr_t; +endpackage + +interface mbox_if #(parameter int WIDTH = 0); + typedef Include::mbox_addr_t mbox_addr_t; + + typedef struct packed { + logic [1:0] tag; + logic [WIDTH-1:0] addr; + } RFTag; +endinterface + +module mbox #(parameter int WIDTH = 0); + mbox_if #(WIDTH) if_inst(); + + // This should reproduce the REFDTYPE UNLINKED error + // Using a type cast of an interface typedef in a parameter + localparam logic [16:0] TAG_ZERO = {1'b1, if_inst.RFTag'(0)}; + + initial begin + `checkd($bits(TAG_ZERO), 17); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule + +module top; + mbox #(.WIDTH(14)) u_mbox(); +endmodule diff --git a/test_regress/t/t_paramgraph_selbit_dtype.py b/test_regress/t/t_paramgraph_selbit_dtype.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_selbit_dtype.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_selbit_dtype.v b/test_regress/t/t_paramgraph_selbit_dtype.v new file mode 100644 index 000000000..971a172ea --- /dev/null +++ b/test_regress/t/t_paramgraph_selbit_dtype.v @@ -0,0 +1,99 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// + +// Test for COND node dtype not being set when using type parameters +// This reproduces the issue from spill_register_flushable.sv:95 +// The issue involves type parameters used in ternary expressions +// Key: T defaults to logic, and a COND expression uses variables of type T + +// Spill register with type parameter (simplified from spill_register_flushable) +module spill_register #( + parameter type T = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic sel_i, + input T data_i, + output T data_o +); + // Two registers of type T + T a_data_q; + T b_data_q; + logic b_full_q; + + always_ff @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + a_data_q <= '0; + b_data_q <= '0; + b_full_q <= 1'b0; + end else begin + a_data_q <= data_i; + b_data_q <= a_data_q; + b_full_q <= sel_i; + end + end + + // This is the problematic line - ternary expression with type parameter variables + // The COND node's dtype should be T, but it's not being set + assign data_o = b_full_q ? b_data_q : a_data_q; +endmodule + +// Wrapper module that passes type parameter through (like spill_register_flushable wrapper) +module spill_wrapper #( + parameter type T = logic +) ( + input logic clk_i, + input logic rst_ni, + input logic sel_i, + input T data_i, + output T data_o +); + // Instantiate spill_register with the same type parameter + spill_register #(.T(T)) i_spill ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .sel_i(sel_i), + .data_i(data_i), + .data_o(data_o) + ); +endmodule + +// Another level of nesting (like axi_demux) +module demux #( + parameter type T = logic +) ( + input logic clk_i, + input logic rst_ni +); + logic sel; + T data_in; + T data_out; + + spill_wrapper #(.T(T)) i_spill_wrapper ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .sel_i(sel), + .data_i(data_in), + .data_o(data_out) + ); +endmodule + +module top; + logic clk; + logic rst_n; + + // Instantiate with default T (logic) + demux #(.T(logic)) u_demux ( + .clk_i(clk), + .rst_ni(rst_n) + ); + + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.py b/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v b/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v new file mode 100644 index 000000000..8e9d7d6a3 --- /dev/null +++ b/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v @@ -0,0 +1,103 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Regression for localparam-derived cfg structs feeding interface instances +// and their nested typedefs. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package cache_pkg; + typedef struct packed { + int Capacity; + int LineSize; + int Associativity; + int AddrBits; + int FgWidth; + int MissQSize; + int CmdTagBits; + } cfg_t; +endpackage + +interface cache_types_if #( + parameter cache_pkg::cfg_t cfg = '0 +)(); + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_NUM_DROWS = (cfg.LineSize / cfg.FgWidth) * SC_NUM_LINES; + + typedef logic [SC_TAG_BITS-1:0] tag_t; + typedef logic [$clog2(SC_NUM_DROWS)-1:0] drow_addr_t; +endinterface + +interface cache_if #( + parameter cache_pkg::cfg_t cfg = '0 +)(); + cache_types_if #(cfg) types(); + typedef types.tag_t tag_t; + typedef types.drow_addr_t drow_addr_t; +endinterface + +module cache_leaf(cache_if io, output int tag_bits_o, output int drow_bits_o); + typedef io.tag_t tag_t; + typedef io.drow_addr_t drow_addr_t; + assign tag_bits_o = $bits(tag_t); + assign drow_bits_o = $bits(drow_addr_t); +endmodule + +module cache_wrap #( + parameter cache_pkg::cfg_t cfg = '0 +)(output int tag_bits_o, output int drow_bits_o); + localparam cache_pkg::cfg_t sc_cfg = '{ + CmdTagBits : $clog2(cfg.Capacity), + Associativity : cfg.Associativity, + Capacity : cfg.Capacity, + LineSize : cfg.LineSize, + AddrBits : cfg.AddrBits, + FgWidth : cfg.FgWidth, + MissQSize : cfg.MissQSize + }; + + cache_if #(sc_cfg) sc_io(); + + cache_leaf u_leaf(.io(sc_io), .tag_bits_o(tag_bits_o), .drow_bits_o(drow_bits_o)); +endmodule + +module top; + localparam cache_pkg::cfg_t cfg0 = '{ + Capacity:1024, LineSize:64, Associativity:4, AddrBits:32, + FgWidth:32, MissQSize:8, CmdTagBits:0 + }; + localparam cache_pkg::cfg_t cfg1 = '{ + Capacity:2048, LineSize:32, Associativity:2, AddrBits:36, + FgWidth:16, MissQSize:16, CmdTagBits:0 + }; + + int tag_bits0; + int drow_bits0; + int tag_bits1; + int drow_bits1; + + cache_wrap #(cfg0) wrap0(.tag_bits_o(tag_bits0), .drow_bits_o(drow_bits0)); + cache_wrap #(cfg1) wrap1(.tag_bits_o(tag_bits1), .drow_bits_o(drow_bits1)); + + initial begin + #1; + `checkd(tag_bits0, 24); + `checkd(drow_bits0, 5); + `checkd(tag_bits1, 26); + `checkd(drow_bits1, 7); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_paramgraph_simple_cache_types_if.py b/test_regress/t/t_paramgraph_simple_cache_types_if.py new file mode 100755 index 000000000..6fe7d000c --- /dev/null +++ b/test_regress/t/t_paramgraph_simple_cache_types_if.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_paramgraph_simple_cache_types_if.v b/test_regress/t/t_paramgraph_simple_cache_types_if.v new file mode 100644 index 000000000..7dff2292f --- /dev/null +++ b/test_regress/t/t_paramgraph_simple_cache_types_if.v @@ -0,0 +1,105 @@ +// This program is free software; you can redistribute it and/or modify it +// under the terms of either the GNU Lesser General Public License Version 3 +// or the Perl Artistic License Version 2.0. +// SPDX-FileCopyrightText: 2026 Wilson Snyder +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +// DESCRIPTION: +// Minimal testcase for depgraph handling of localparam-derived typedefs +// inside a parameterized cache types interface. +// + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on + +package sc_pkg; + typedef struct packed { + int Capacity; + int LineSize; + int Associativity; + int AddrBits; + int FgWidth; + int StateBits; + int CmdTagBits; + int MissQSize; + } cfg_t; +endpackage + +interface simple_cache_types_if #( + parameter sc_pkg::cfg_t cfg = '0 +)(); + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; + localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; + + typedef logic [cfg.AddrBits-1:0] addr_t; + typedef logic [cfg.Associativity-1:0] assoc_oh_t; + typedef logic [cfg.Associativity-2:0] plru_t; + typedef logic [cfg.StateBits-1:0] state_t; + typedef logic [cfg.CmdTagBits-1:0] cmd_tag_t; + typedef logic [$clog2(cfg.MissQSize)-1:0] missq_tag_t; + + typedef logic [SC_TAG_BITS-1:0] tag_t; + typedef logic [SC_ROW_BITS-1:0] row_t; + typedef logic [SC_BLOCK_BITS-1:0] block_t; + typedef logic [$clog2(SC_NUM_DROWS)-1:0] drow_addr_t; + + typedef struct packed { + tag_t tag; + row_t row; + block_t block; + } sc_tag_addr_t; +endinterface + +module child(simple_cache_types_if types, output int tag_bits_o, output int tag_addr_bits_o, output int drow_bits_o); + typedef types.tag_t tag_t; + typedef types.sc_tag_addr_t sc_tag_addr_t; + typedef types.drow_addr_t drow_addr_t; + assign tag_bits_o = $bits(tag_t); + assign tag_addr_bits_o = $bits(sc_tag_addr_t); + assign drow_bits_o = $bits(drow_addr_t); +endmodule + +module top; + localparam sc_pkg::cfg_t cfg0 = '{ + Capacity:1024, LineSize:64, Associativity:4, AddrBits:32, + FgWidth:32, StateBits:2, CmdTagBits:5, MissQSize:8 + }; + localparam sc_pkg::cfg_t cfg1 = '{ + Capacity:2048, LineSize:32, Associativity:2, AddrBits:36, + FgWidth:16, StateBits:3, CmdTagBits:7, MissQSize:16 + }; + + simple_cache_types_if #(cfg0) types0(); + simple_cache_types_if #(cfg1) types1(); + + int tag_bits0; + int tag_addr_bits0; + int drow_bits0; + int tag_bits1; + int tag_addr_bits1; + int drow_bits1; + + child u0(.types(types0), .tag_bits_o(tag_bits0), .tag_addr_bits_o(tag_addr_bits0), + .drow_bits_o(drow_bits0)); + child u1(.types(types1), .tag_bits_o(tag_bits1), .tag_addr_bits_o(tag_addr_bits1), + .drow_bits_o(drow_bits1)); + + initial begin + #1; + `checkd(tag_bits0, 24); + `checkd(tag_addr_bits0, 32); + `checkd(drow_bits0, 5); + `checkd(tag_bits1, 26); + `checkd(tag_addr_bits1, 36); + `checkd(drow_bits1, 7); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_selrange_iface_type_param.py b/test_regress/t/t_selrange_iface_type_param.py new file mode 100755 index 000000000..7ded63f3a --- /dev/null +++ b/test_regress/t/t_selrange_iface_type_param.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2024 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--binary"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_selrange_iface_type_param.v b/test_regress/t/t_selrange_iface_type_param.v new file mode 100644 index 000000000..b9fd18340 --- /dev/null +++ b/test_regress/t/t_selrange_iface_type_param.v @@ -0,0 +1,595 @@ +// DESCRIPTION: Verilator: Test for interface typedef resolving to correct clone +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2022 Wilson Snyder +// SPDX-License-Identifier: CC0-1.0 +// +// When a non-parameterized wrapper module (#()) has multiple interface ports +// of the same parameterized interface type but with different configurations, +// typedefs extracted from those ports (e.g., typedef tgt_io.req_t local_t) +// must resolve to the struct from the CORRECT interface clone. +// +// This test models the aerial design hierarchy: +// Path A: dw_converter_wrap#()(tgt_io[Id=2,Data=64], mst_io[Id=2,Data=128]) +// -> dw_converter -> dw_upsizer -> axi_demux -> axi_demux_simple +// Path B: axi_to_axi_lite_wrap#()(axi_tgt_io[Id=8,Data=64]) +// -> axi_to_axi_lite -> axi_burst_splitter -> axi_demux -> axi_demux_simple +// +// Checks: +// 1. $bits of typedef'd types match the interface config (not a sibling clone) +// 2. Nested struct member access (slv_req_i.aw.id[0+:N]) extracts correct bits +// 3. Data written to interface ports arrives at leaf modules with correct values +// +// This file is ONLY for use with Verilator. + +package cfg_pkg; + typedef struct packed { + int unsigned IdBits; + int unsigned DataBits; + } cfg_t; +endpackage + +// Parameterized interface (like axi4_if) +interface my_if #(parameter cfg_pkg::cfg_t cfg = 0); + typedef logic [cfg.IdBits-1:0] id_t; + typedef logic [cfg.DataBits-1:0] data_t; + typedef logic [cfg.DataBits/8-1:0] strb_t; + + typedef struct packed { + id_t id; + data_t data; + logic [7:0] len; + logic [2:0] size; + logic [1:0] burst; + } aw_chan_t; + + typedef struct packed { + data_t data; + strb_t strb; + logic last; + } w_chan_t; + + typedef struct packed { + id_t id; + logic [1:0] resp; + } b_chan_t; + + typedef struct packed { + id_t id; + data_t data; + logic [7:0] len; + logic [2:0] size; + logic [1:0] burst; + } ar_chan_t; + + typedef struct packed { + id_t id; + data_t data; + logic [1:0] resp; + logic last; + } r_chan_t; + + typedef struct packed { + aw_chan_t aw; + logic aw_valid; + w_chan_t w; + logic w_valid; + logic b_ready; + ar_chan_t ar; + logic ar_valid; + logic r_ready; + } req_t; + + typedef struct packed { + logic aw_ready; + logic w_ready; + b_chan_t b; + logic b_valid; + r_chan_t r; + logic r_valid; + } resp_t; + + req_t req; + resp_t resp; + + modport target(input req, output resp); + modport initiator(output req, input resp); +endinterface + +//====================================================================== +// Leaf: axi_demux_simple skeleton +//====================================================================== +module axi_demux_simple #( + parameter int unsigned AxiIdWidth = 32'd0, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter int unsigned AxiLookBits = 32'd3 +)( + input logic clk_i, + input logic rst_ni, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + output logic [AxiLookBits-1:0] id_out, + output int unsigned req_bits_out +); + // Extract ID from nested struct - triggers SELRANGE if axi_req_t + // is from wrong interface clone (id field narrower than AxiLookBits) + assign id_out = slv_req_i.aw.id[0+:AxiLookBits]; + assign slv_resp_o = '0; + // Expose $bits so top can verify the type parameter resolved correctly + assign req_bits_out = $bits(axi_req_t); +endmodule + +//====================================================================== +// axi_demux skeleton +//====================================================================== +module axi_demux #( + parameter int unsigned AxiIdWidth = 32'd0, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter int unsigned NoMstPorts = 32'd0, + parameter int unsigned MaxTrans = 32'd8, + parameter int unsigned AxiLookBits = 32'd3 +)( + input logic clk_i, + input logic rst_ni, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + output logic [AxiLookBits-1:0] id_out, + output int unsigned req_bits_out +); + axi_demux_simple #( + .AxiIdWidth ( AxiIdWidth ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .AxiLookBits ( AxiLookBits ) + ) i_demux_simple ( + .clk_i, + .rst_ni, + .slv_req_i, + .slv_resp_o, + .id_out, + .req_bits_out + ); +endmodule + +//====================================================================== +// axi_burst_splitter skeleton +//====================================================================== +module axi_burst_splitter #( + parameter int unsigned AddrWidth = 32'd0, + parameter int unsigned DataWidth = 32'd0, + parameter int unsigned IdWidth = 32'd0, + parameter int unsigned UserWidth = 32'd0, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic +)( + input logic clk_i, + input logic rst_ni, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + output logic [IdWidth-1:0] id_out +); + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [IdWidth-1:0] id_t; + typedef logic [DataWidth/8-1:0] strb_t; + typedef logic [UserWidth-1:0] user_t; + + typedef struct packed { + id_t id; + addr_t addr; + logic [7:0] len; + logic [2:0] size; + logic [1:0] burst; + } local_aw_chan_t; + + typedef struct packed { data_t data; strb_t strb; logic last; } local_w_chan_t; + typedef struct packed { id_t id; logic [1:0] resp; } local_b_chan_t; + typedef struct packed { id_t id; addr_t addr; logic [7:0] len; logic [2:0] size; logic [1:0] burst; } local_ar_chan_t; + typedef struct packed { id_t id; data_t data; logic [1:0] resp; logic last; } local_r_chan_t; + + int unsigned req_bits_out; + + axi_demux #( + .AxiIdWidth ( IdWidth ), + .aw_chan_t ( local_aw_chan_t ), + .w_chan_t ( local_w_chan_t ), + .b_chan_t ( local_b_chan_t ), + .ar_chan_t ( local_ar_chan_t ), + .r_chan_t ( local_r_chan_t ), + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_resp_t ), + .NoMstPorts ( 2 ), + .MaxTrans ( 4 ), + .AxiLookBits ( IdWidth ) + ) i_demux ( + .clk_i, .rst_ni, + .slv_req_i, .slv_resp_o, .id_out, + .req_bits_out + ); +endmodule + +//====================================================================== +// axi_dw_upsizer skeleton +//====================================================================== +module axi_dw_upsizer #( + parameter int unsigned AxiIdWidth = 1, + parameter int unsigned AxiAddrWidth = 1, + parameter type aw_chan_t = logic, + parameter type mst_w_chan_t = logic, + parameter type slv_w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type mst_r_chan_t = logic, + parameter type slv_r_chan_t = logic, + parameter type axi_mst_req_t = logic, + parameter type axi_mst_resp_t = logic, + parameter type axi_slv_req_t = logic, + parameter type axi_slv_resp_t = logic +)( + input logic clk_i, + input logic rst_ni, + input axi_slv_req_t slv_req_i, + output axi_slv_resp_t slv_resp_o, + output axi_mst_req_t mst_req_o, + input axi_mst_resp_t mst_resp_i +); + axi_mst_req_t mst_req; + axi_mst_resp_t mst_resp; + logic [AxiIdWidth-1:0] id_out; + int unsigned req_bits_out; + + assign mst_req = '0; + assign slv_resp_o = '0; + assign mst_req_o = mst_req; + + axi_demux #( + .AxiIdWidth ( AxiIdWidth ), + .aw_chan_t ( aw_chan_t ), + .w_chan_t ( mst_w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .r_chan_t ( mst_r_chan_t ), + .axi_req_t ( axi_mst_req_t ), + .axi_resp_t ( axi_mst_resp_t ), + .NoMstPorts ( 2 ), + .MaxTrans ( 4 ), + .AxiLookBits ( AxiIdWidth ) + ) i_axi_demux ( + .clk_i, .rst_ni, + .slv_req_i ( mst_req ), + .slv_resp_o ( mst_resp ), + .id_out, + .req_bits_out + ); +endmodule + +//====================================================================== +// axi_dw_converter skeleton - generate if for upsize +//====================================================================== +module axi_dw_converter #( + parameter int unsigned AxiSlvPortDataWidth = 8, + parameter int unsigned AxiMstPortDataWidth = 8, + parameter int unsigned AxiAddrWidth = 1, + parameter int unsigned AxiIdWidth = 1, + parameter type aw_chan_t = logic, + parameter type mst_w_chan_t = logic, + parameter type slv_w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type mst_r_chan_t = logic, + parameter type slv_r_chan_t = logic, + parameter type axi_mst_req_t = logic, + parameter type axi_mst_resp_t = logic, + parameter type axi_slv_req_t = logic, + parameter type axi_slv_resp_t = logic +)( + input logic clk_i, + input logic rst_ni, + input axi_slv_req_t slv_req_i, + output axi_slv_resp_t slv_resp_o, + output axi_mst_req_t mst_req_o, + input axi_mst_resp_t mst_resp_i +); + if (AxiMstPortDataWidth == AxiSlvPortDataWidth) begin : gen_no_dw_conversion + assign mst_req_o = slv_req_i; + assign slv_resp_o = mst_resp_i; + end + + if (AxiMstPortDataWidth > AxiSlvPortDataWidth) begin : gen_dw_upsize + axi_dw_upsizer #( + .AxiAddrWidth ( AxiAddrWidth ), + .AxiIdWidth ( AxiIdWidth ), + .aw_chan_t ( aw_chan_t ), + .mst_w_chan_t ( mst_w_chan_t ), + .slv_w_chan_t ( slv_w_chan_t ), + .b_chan_t ( b_chan_t ), + .ar_chan_t ( ar_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_r_chan_t ( slv_r_chan_t ), + .axi_mst_req_t ( axi_mst_req_t ), + .axi_mst_resp_t ( axi_mst_resp_t ), + .axi_slv_req_t ( axi_slv_req_t ), + .axi_slv_resp_t ( axi_slv_resp_t ) + ) i_axi_dw_upsizer ( + .clk_i, .rst_ni, + .slv_req_i, .slv_resp_o, + .mst_req_o, .mst_resp_i + ); + end + + // Expose leaf req_bits from whichever generate path is active + int unsigned mst_req_bits; + if (AxiMstPortDataWidth > AxiSlvPortDataWidth) begin : gen_bits_up + assign mst_req_bits = gen_dw_upsize.i_axi_dw_upsizer.req_bits_out; + end else begin : gen_bits_eq + assign mst_req_bits = 0; + end +endmodule + +//====================================================================== +// axi_to_axi_lite skeleton +//====================================================================== +module axi_to_axi_lite #( + parameter int unsigned AxiAddrWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, + parameter int unsigned AxiIdWidth = 32'd0, + parameter int unsigned AxiUserWidth = 32'd0, + parameter type full_req_t = logic, + parameter type full_resp_t = logic +)( + input logic clk_i, + input logic rst_ni, + input full_req_t slv_req_i, + output full_resp_t slv_resp_o, + output logic [AxiIdWidth-1:0] id_out +); + axi_burst_splitter #( + .AddrWidth ( AxiAddrWidth ), + .DataWidth ( AxiDataWidth ), + .IdWidth ( AxiIdWidth ), + .UserWidth ( AxiUserWidth ), + .axi_req_t ( full_req_t ), + .axi_resp_t ( full_resp_t ) + ) i_axi_burst_splitter ( + .clk_i, .rst_ni, + .slv_req_i, .slv_resp_o, .id_out + ); + + int unsigned req_bits_out; + assign req_bits_out = i_axi_burst_splitter.req_bits_out; +endmodule + +//====================================================================== +// axi_to_axi_lite_wrap - non-parameterized wrapper (#()) with iface port +//====================================================================== +module axi_to_axi_lite_wrap #()( + input logic clk_i, + input logic rst_ni, + my_if.target axi_tgt_io +); + typedef axi_tgt_io.req_t tgt_req_t; + typedef axi_tgt_io.resp_t tgt_resp_t; + + tgt_req_t tgt_req; + tgt_resp_t tgt_resp; + assign tgt_req = axi_tgt_io.req; + assign axi_tgt_io.resp = tgt_resp; + + logic [axi_tgt_io.cfg.IdBits-1:0] id_result; + int unsigned req_bits_out; + + axi_to_axi_lite #( + .AxiAddrWidth ( 32 ), + .AxiDataWidth ( axi_tgt_io.cfg.DataBits ), + .AxiIdWidth ( axi_tgt_io.cfg.IdBits ), + .AxiUserWidth ( 1 ), + .full_req_t ( tgt_req_t ), + .full_resp_t ( tgt_resp_t ) + ) axi_to_axi_lite ( + .clk_i, .rst_ni, + .slv_req_i ( tgt_req ), + .slv_resp_o ( tgt_resp ), + .id_out ( id_result ) + ); + + assign req_bits_out = axi_to_axi_lite.req_bits_out; +endmodule + +//====================================================================== +// axi_dw_converter_wrap - non-parameterized wrapper with TWO iface ports +//====================================================================== +module axi_dw_converter_wrap #()( + input logic clk_i, + input logic rst_ni, + my_if.target tgt_io, + my_if.initiator mst_io +); + typedef tgt_io.aw_chan_t tgt_aw_chan_t; + typedef tgt_io.w_chan_t tgt_w_chan_t; + typedef tgt_io.b_chan_t tgt_b_chan_t; + typedef tgt_io.ar_chan_t tgt_ar_chan_t; + typedef tgt_io.r_chan_t tgt_r_chan_t; + + typedef mst_io.w_chan_t mst_w_chan_t; + typedef mst_io.r_chan_t mst_r_chan_t; + + typedef tgt_io.req_t tgt_req_t; + typedef tgt_io.resp_t tgt_resp_t; + typedef mst_io.req_t mst_req_t; + typedef mst_io.resp_t mst_resp_t; + + tgt_req_t tgt_req; + tgt_resp_t tgt_resp; + mst_req_t mst_req; + mst_resp_t mst_resp; + + assign tgt_req = tgt_io.req; + assign tgt_io.resp = tgt_resp; + assign mst_io.req = mst_req; + assign mst_resp = mst_io.resp; + + axi_dw_converter #( + .AxiSlvPortDataWidth ( tgt_io.cfg.DataBits ), + .AxiMstPortDataWidth ( mst_io.cfg.DataBits ), + .AxiAddrWidth ( 32 ), + .AxiIdWidth ( tgt_io.cfg.IdBits ), + .aw_chan_t ( tgt_aw_chan_t ), + .mst_w_chan_t ( mst_w_chan_t ), + .slv_w_chan_t ( tgt_w_chan_t ), + .b_chan_t ( tgt_b_chan_t ), + .ar_chan_t ( tgt_ar_chan_t ), + .mst_r_chan_t ( mst_r_chan_t ), + .slv_r_chan_t ( tgt_r_chan_t ), + .axi_mst_req_t ( mst_req_t ), + .axi_mst_resp_t ( mst_resp_t ), + .axi_slv_req_t ( tgt_req_t ), + .axi_slv_resp_t ( tgt_resp_t ) + ) dw_converter ( + .clk_i, .rst_ni, + .slv_req_i ( tgt_req ), + .slv_resp_o ( tgt_resp ), + .mst_req_o ( mst_req ), + .mst_resp_i ( mst_resp ) + ); + + // Expose $bits from the mst-side leaf (through dw_converter -> upsizer -> demux) + int unsigned mst_req_bits_out; + assign mst_req_bits_out = dw_converter.mst_req_bits; + + // Also check tgt-side typedef width directly in this wrapper + int unsigned tgt_req_bits_out; + assign tgt_req_bits_out = $bits(tgt_req_t); + int unsigned mst_req_bits_local; + assign mst_req_bits_local = $bits(mst_req_t); +endmodule + +//====================================================================== +// Top module +//====================================================================== +module t; + logic clk; + logic rst_n; + + // Config A: narrow ID (2 bits), narrow data (64 bits) -> upsize to 128 + localparam cfg_pkg::cfg_t CFG_A_SLV = '{IdBits: 2, DataBits: 64}; + localparam cfg_pkg::cfg_t CFG_A_MST = '{IdBits: 2, DataBits: 128}; + + // Config B: wide ID (8 bits), data 64 bits + localparam cfg_pkg::cfg_t CFG_B = '{IdBits: 8, DataBits: 64}; + + my_if #(.cfg(CFG_A_SLV)) bus_a_slv(); + my_if #(.cfg(CFG_A_MST)) bus_a_mst(); + my_if #(.cfg(CFG_B)) bus_b(); + + // Path A: dw_converter_wrap (narrow ID, upsize 64->128) + axi_dw_converter_wrap #() u_dw_conv_wrap ( + .clk_i(clk), .rst_ni(rst_n), + .tgt_io(bus_a_slv), .mst_io(bus_a_mst) + ); + + // Path B: axi_to_axi_lite_wrap (wide ID) + axi_to_axi_lite_wrap #() u_axi_to_lite_wrap ( + .clk_i(clk), .rst_ni(rst_n), + .axi_tgt_io(bus_b) + ); + + //====================================================================== + // Expected $bits values: + // + // req_t for CFG_A_SLV (Id=2, Data=64): + // aw_chan_t = 2+64+8+3+2 = 79 + // w_chan_t = 64+8+1 = 73 + // ar_chan_t = 79 + // req_t = 79+1+73+1+1+79+1+1 = 236 + // + // req_t for CFG_A_MST (Id=2, Data=128): + // aw_chan_t = 2+128+8+3+2 = 143 + // w_chan_t = 128+16+1 = 145 + // ar_chan_t = 143 + // req_t = 143+1+145+1+1+143+1+1 = 436 + // + // req_t for CFG_B (Id=8, Data=64): + // aw_chan_t = 8+64+8+3+2 = 85 + // w_chan_t = 64+8+1 = 73 + // ar_chan_t = 85 + // req_t = 85+1+73+1+1+85+1+1 = 248 + //====================================================================== + + localparam int unsigned EXP_REQ_BITS_A_SLV = 236; + localparam int unsigned EXP_REQ_BITS_A_MST = 436; + localparam int unsigned EXP_REQ_BITS_B = 248; + + // verilator lint_off STMTDLY + initial begin + clk = 0; rst_n = 1; + + // Drive path A: narrow ID + bus_a_slv.req = '0; + bus_a_slv.req.aw.id = 2'h3; + bus_a_slv.req.aw_valid = 1'b1; + bus_a_mst.resp = '0; + + // Drive path B: wide ID + bus_b.req = '0; + bus_b.req.aw.id = 8'hAB; + bus_b.req.aw_valid = 1'b1; + + #10; + + //------------------------------------------------------------------ + // Check 1: dw_converter_wrap typedef widths + // tgt_req_t must match CFG_A_SLV, mst_req_t must match CFG_A_MST + //------------------------------------------------------------------ + if (u_dw_conv_wrap.tgt_req_bits_out !== EXP_REQ_BITS_A_SLV) begin + $display("%%Error: dw_conv_wrap tgt_req_bits=%0d expected=%0d", + u_dw_conv_wrap.tgt_req_bits_out, EXP_REQ_BITS_A_SLV); + $stop; + end + if (u_dw_conv_wrap.mst_req_bits_local !== EXP_REQ_BITS_A_MST) begin + $display("%%Error: dw_conv_wrap mst_req_bits_local=%0d expected=%0d", + u_dw_conv_wrap.mst_req_bits_local, EXP_REQ_BITS_A_MST); + $stop; + end + + //------------------------------------------------------------------ + // Check 2: mst-side leaf (through dw_upsizer -> axi_demux -> axi_demux_simple) + // axi_req_t must be mst_req_t = CFG_A_MST + //------------------------------------------------------------------ + if (u_dw_conv_wrap.mst_req_bits_out !== EXP_REQ_BITS_A_MST) begin + $display("%%Error: dw_conv_wrap mst leaf req_bits=%0d expected=%0d", + u_dw_conv_wrap.mst_req_bits_out, EXP_REQ_BITS_A_MST); + $stop; + end + + //------------------------------------------------------------------ + // Check 3: axi_to_axi_lite_wrap leaf + // axi_req_t must be tgt_req_t = CFG_B + //------------------------------------------------------------------ + if (u_axi_to_lite_wrap.req_bits_out !== EXP_REQ_BITS_B) begin + $display("%%Error: axi_to_lite leaf req_bits=%0d expected=%0d", + u_axi_to_lite_wrap.req_bits_out, EXP_REQ_BITS_B); + $stop; + end + + //------------------------------------------------------------------ + // Check 4: ID extraction through path B + // axi_to_axi_lite_wrap -> ... -> axi_demux_simple extracts aw.id[0+:8] + //------------------------------------------------------------------ + if (u_axi_to_lite_wrap.id_result !== 8'hAB) begin + $display("%%Error: axi_to_lite id_result=%0h expected=AB", + u_axi_to_lite_wrap.id_result); + $stop; + end + + $write("*-* All Finished *-*\n"); + $finish; + end + // verilator lint_on STMTDLY +endmodule diff --git a/test_regress/t/t_selrange_iface_type_param_debugi.py b/test_regress/t/t_selrange_iface_type_param_debugi.py new file mode 100755 index 000000000..b36d118f5 --- /dev/null +++ b/test_regress/t/t_selrange_iface_type_param_debugi.py @@ -0,0 +1,27 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +# Debug-variant of t_selrange_iface_type_param: enables IfaceCapture debug +# output and verifies type-parameter capture and propagation messages. + +import vltest_bootstrap + +test.scenarios('vlt') + +test.top_filename = "t/t_selrange_iface_type_param.v" + +test.compile(v_flags2=["--binary --debug --debugi 0 --debugi-V3LinkDotIfaceCapture 9"]) + +test.file_grep(test.compile_log_filename, r"propagateClone:") +test.file_grep(test.compile_log_filename, r"iface capture add:") +test.file_grep(test.compile_log_filename, r"iface capture dumpEntries:") + +test.execute() + +test.passes() From ce4d35aa85652ceca29acece158a07d5ec24fff5 Mon Sep 17 00:00:00 2001 From: Veripool API Bot <57024651+veripoolbot@users.noreply.github.com> Date: Tue, 3 Mar 2026 07:21:24 -0500 Subject: [PATCH 036/340] Verilog format --- test_regress/t/t_a1_first_cc.v | 19 +- test_regress/t/t_alias_unsup.v | 14 +- test_regress/t/t_array_backw_index_bad.out | 42 +- test_regress/t/t_array_backw_index_bad.v | 36 +- test_regress/t/t_array_compare.v | 70 +- test_regress/t/t_array_in_struct.v | 76 +- test_regress/t/t_array_index_increment.v | 216 +++--- test_regress/t/t_array_index_side.v | 60 +- test_regress/t/t_array_list_bad.out | 12 +- test_regress/t/t_array_list_bad.v | 53 +- test_regress/t/t_array_mda.v | 114 +-- test_regress/t/t_array_method_bad.out | 6 +- test_regress/t/t_array_method_bad.v | 12 +- test_regress/t/t_array_method_map.out | 12 +- test_regress/t/t_array_method_map.v | 20 +- test_regress/t/t_array_non_blocking_loop.v | 47 +- test_regress/t/t_array_packed_endian.v | 134 ++-- test_regress/t/t_array_packed_sign.v | 82 +- test_regress/t/t_array_packed_sysfunct.v | 285 ++++--- test_regress/t/t_array_packed_write_read.v | 256 +++--- test_regress/t/t_array_pattern_2d.v | 58 +- test_regress/t/t_array_pattern_bad.out | 6 +- test_regress/t/t_array_pattern_bad.v | 23 +- test_regress/t/t_array_pattern_bad2.out | 6 +- test_regress/t/t_array_pattern_bad2.v | 23 +- test_regress/t/t_array_pattern_bad3.out | 20 +- test_regress/t/t_array_pattern_bad3.v | 28 +- test_regress/t/t_array_pattern_enum.v | 32 +- test_regress/t/t_array_pattern_packed.v | 246 +++--- test_regress/t/t_array_pattern_unpacked.v | 84 +- test_regress/t/t_array_query.v | 74 +- test_regress/t/t_array_query_with.v | 110 +-- test_regress/t/t_array_rev.v | 76 +- test_regress/t/t_array_sel_wide.v | 34 +- test_regress/t/t_array_type_methods.v | 34 +- test_regress/t/t_array_unpacked_public.v | 10 +- test_regress/t/t_assert_always_unsup.out | 24 +- test_regress/t/t_assert_always_unsup.v | 61 +- test_regress/t/t_assert_basic.v | 88 ++- test_regress/t/t_assert_casez.v | 40 +- test_regress/t/t_assert_clock_event_unsup.out | 6 +- test_regress/t/t_assert_clock_event_unsup.v | 47 +- test_regress/t/t_assert_comp.v | 42 +- test_regress/t/t_assert_cover.v | 230 +++--- test_regress/t/t_assert_ctl_arg.dat.out | 304 ++++---- test_regress/t/t_assert_ctl_arg.out | 726 +++++++++--------- test_regress/t/t_assert_ctl_arg.v | 293 ++++--- test_regress/t/t_assert_ctl_arg_unsup.out | 24 +- test_regress/t/t_assert_ctl_arg_unsup.v | 22 +- test_regress/t/t_assert_ctl_concurrent.v | 44 +- test_regress/t/t_assert_ctl_immediate.out | 10 +- test_regress/t/t_assert_ctl_immediate.v | 90 +-- test_regress/t/t_assert_ctl_unsup.out | 200 ++--- test_regress/t/t_assert_ctl_unsup.v | 274 +++---- test_regress/t/t_assert_disable_bad.out | 6 +- test_regress/t/t_assert_disable_bad.v | 32 +- test_regress/t/t_assert_disable_count.v | 93 +-- test_regress/t/t_assert_dup_bad.out | 12 +- test_regress/t/t_assert_dup_bad.v | 18 +- test_regress/t/t_assert_elab.v | 31 +- test_regress/t/t_assert_iff.v | 72 +- test_regress/t/t_assert_iff_clk_unsup.out | 6 +- test_regress/t/t_assert_iff_clk_unsup.v | 22 +- test_regress/t/t_assert_imm_nz_bad.out | 6 +- test_regress/t/t_assert_imm_nz_bad.v | 11 +- test_regress/t/t_assert_implication.v | 145 ++-- test_regress/t/t_assert_inside_cond.v | 44 +- test_regress/t/t_assert_on.v | 19 +- test_regress/t/t_assert_past.v | 41 +- .../t/t_assert_procedural_clk_bad.out | 16 +- test_regress/t/t_assert_procedural_clk_bad.v | 38 +- test_regress/t/t_assert_question.v | 34 +- test_regress/t/t_assert_sampled.v | 134 ++-- test_regress/t/t_assert_synth.v | 155 ++-- test_regress/t/t_assert_synth_full.out | 10 +- test_regress/t/t_assert_synth_full_vlt.out | 10 +- test_regress/t/t_assert_synth_parallel.out | 10 +- test_regress/t/t_assert_synth_parallel.vlt | 2 +- .../t/t_assert_synth_parallel_vlt.out | 10 +- test_regress/t/t_assert_unique_case_bad.v | 96 +-- test_regress/t/t_assign_expr.v | 120 +-- test_regress/t/t_assign_inline.v | 74 +- test_regress/t/t_assign_slice_overflow.v | 265 +++---- .../t/t_assigndly_dynamic_notiming_bad.out | 8 +- .../t/t_assigndly_dynamic_notiming_bad.v | 24 +- test_regress/t/t_assigndly_task.v | 8 +- test_regress/t/t_assoc.v | 289 ++++--- test_regress/t/t_assoc2.v | 62 +- test_regress/t/t_assoc_compare.v | 104 +-- test_regress/t/t_assoc_enum.v | 40 +- test_regress/t/t_assoc_method.v | 7 +- test_regress/t/t_assoc_method_bad.out | 96 +-- test_regress/t/t_assoc_method_bad.v | 38 +- test_regress/t/t_assoc_method_map.out | 6 +- test_regress/t/t_assoc_method_map.v | 22 +- test_regress/t/t_assoc_ref_type.v | 108 +-- test_regress/t/t_assoc_wildcard.v | 84 +- test_regress/t/t_assoc_wildcard_bad.out | 114 +-- test_regress/t/t_assoc_wildcard_bad.v | 54 +- test_regress/t/t_assoc_wildcard_map.out | 6 +- test_regress/t/t_assoc_wildcard_map.v | 20 +- test_regress/t/t_assoc_wildcard_method.v | 244 +++--- test_regress/t/t_attr_parenstar.v | 57 +- test_regress/t/t_benchmark_mux4k.v | 238 +++--- test_regress/t/t_bind.v | 97 +-- test_regress/t/t_bind2.v | 13 +- test_regress/t/t_bind_nfound.v | 14 +- test_regress/t/t_bitsel_2d_slice.v | 34 +- test_regress/t/t_bitsel_concat.v | 134 ++-- test_regress/t/t_bitsel_const_bad.out | 6 +- test_regress/t/t_bitsel_const_bad.v | 10 +- test_regress/t/t_bitsel_enum.v | 29 +- test_regress/t/t_bitsel_over32.v | 43 +- test_regress/t/t_bitsel_slice.v | 120 ++- test_regress/t/t_bitsel_struct.v | 26 +- test_regress/t/t_bitsel_struct2.v | 64 +- test_regress/t/t_bitsel_struct3.v | 64 +- test_regress/t/t_bitsel_wire_array_bad.out | 6 +- test_regress/t/t_bitsel_wire_array_bad.v | 10 +- test_regress/t/t_blocking.v | 158 ++-- test_regress/t/t_c_this.v | 18 +- test_regress/t/t_case_genx_bad.out | 6 +- test_regress/t/t_case_genx_bad.v | 16 +- test_regress/t/t_cast.v | 206 ++--- test_regress/t/t_cast_param_type.v | 2 +- test_regress/t/t_castdyn_castconst_bad.out | 28 +- test_regress/t/t_castdyn_castconst_bad.v | 24 +- test_regress/t/t_castdyn_enum.v | 108 +-- test_regress/t/t_castdyn_unsup_bad.out | 6 +- test_regress/t/t_castdyn_unsup_bad.v | 10 +- test_regress/t/t_checker.v | 58 +- test_regress/t/t_checker_unsup.out | 34 +- test_regress/t/t_checker_unsup.v | 108 ++- test_regress/t/t_class1.v | 48 +- test_regress/t/t_class2.v | 62 +- test_regress/t/t_class_builtin_bad.out | 12 +- test_regress/t/t_class_builtin_bad.v | 18 +- test_regress/t/t_class_eq.v | 2 +- test_regress/t/t_class_extends_arg.v | 2 +- test_regress/t/t_class_new_typed.v | 2 +- test_regress/t/t_class_wide.v | 2 +- test_regress/t/t_clocked_release_combo.v | 20 +- test_regress/t/t_clocker.v | 72 +- test_regress/t/t_clocking_empty_block.v | 2 +- test_regress/t/t_comb_do_not_convert_to.v | 60 +- test_regress/t/t_comb_input_0.v | 8 +- test_regress/t/t_comb_input_1.v | 8 +- test_regress/t/t_comb_input_2.v | 8 +- .../t/t_comb_loop_through_unpacked_array.v | 12 +- test_regress/t/t_compiler_include.v | 7 +- test_regress/t/t_compiler_include_dpi.v | 41 +- test_regress/t/t_concat_casts.v | 46 +- test_regress/t/t_concat_impure.v | 22 +- test_regress/t/t_concat_link_bad.out | 42 +- test_regress/t/t_concat_link_bad.v | 6 +- test_regress/t/t_concat_opt.v | 100 ++- test_regress/t/t_concat_or.v | 128 +-- test_regress/t/t_concat_sel.v | 116 +-- test_regress/t/t_concat_string.v | 36 +- test_regress/t/t_concat_unpack.v | 50 +- test_regress/t/t_const.v | 24 +- test_regress/t/t_const_bad.out | 18 +- test_regress/t/t_const_bad.v | 20 +- test_regress/t/t_const_bitoptree_bug3096.v | 26 +- test_regress/t/t_const_dec_mixed_bad.out | 6 +- test_regress/t/t_const_dec_mixed_bad.v | 2 +- test_regress/t/t_const_hi.v | 81 +- test_regress/t/t_const_number_bad.out | 48 +- test_regress/t/t_const_number_bad.v | 14 +- test_regress/t/t_const_number_unsized.v | 75 +- test_regress/t/t_const_number_v_bad.out | 36 +- test_regress/t/t_const_number_v_bad.v | 16 +- test_regress/t/t_const_op_red_scope.v | 192 ++--- test_regress/t/t_const_overflow_bad.out | 30 +- test_regress/t/t_const_overflow_bad.v | 16 +- test_regress/t/t_const_sel_sel_extend.v | 20 +- test_regress/t/t_const_slicesel.v | 16 +- test_regress/t/t_const_string_func.v | 25 +- test_regress/t/t_constraint_cls_arr_member.v | 10 +- test_regress/t/t_cover_toggle_min.v | 2 +- test_regress/t/t_cover_trace_always.v | 2 +- .../t/t_covergroup_func_override_bad.v | 2 +- .../t/t_covergroup_new_override_bad.v | 2 +- test_regress/t/t_cuse_forward.v | 12 +- test_regress/t/t_dpi_binary.v | 2 +- test_regress/t/t_dpi_context.v | 2 +- test_regress/t/t_dpi_display.v | 2 +- test_regress/t/t_dpi_display_bad.v | 2 +- test_regress/t/t_dpi_dup_bad.v | 2 +- test_regress/t/t_dpi_import_mix_bad.v | 2 +- test_regress/t/t_dpi_name_bad.v | 2 +- test_regress/t/t_dpi_string.v | 2 +- test_regress/t/t_dpi_sys.v | 2 +- test_regress/t/t_enum_bad_value.v | 2 +- test_regress/t/t_enum_const_methods.v | 2 +- test_regress/t/t_enum_name2.v | 2 +- test_regress/t/t_event_control_assign.v | 2 +- test_regress/t/t_event_control_pass.v | 2 +- test_regress/t/t_event_control_star.v | 2 +- test_regress/t/t_final.v | 2 +- test_regress/t/t_flag_fi.v | 2 +- test_regress/t/t_flag_ldflags.v | 2 +- .../t/t_fork_block_item_declaration.v | 2 +- test_regress/t/t_fork_initial.v | 2 +- test_regress/t/t_fork_join_none_any_nested.v | 2 +- test_regress/t/t_fork_join_none_class_cap.v | 2 +- test_regress/t/t_fork_join_none_virtual.v | 2 +- test_regress/t/t_fork_output_arg.v | 2 +- test_regress/t/t_func_automatic_clear.v | 2 +- test_regress/t/t_func_complex.v | 2 +- test_regress/t/t_func_real_param.v | 2 +- test_regress/t/t_func_refio_bad.v | 2 +- test_regress/t/t_func_v.v | 2 +- test_regress/t/t_fuzz_triand_bad.v | 2 +- test_regress/t/t_gate_opt.v | 2 +- test_regress/t/t_iface_self_ref_typedef.v | 8 +- .../t/t_iface_typedef_struct_member.v | 24 +- test_regress/t/t_iface_typedef_wrong_clone.v | 28 +- test_regress/t/t_initial_delay_assign.v | 2 +- test_regress/t/t_inside_nonint.v | 2 +- test_regress/t/t_interface_ar2a.v | 2 +- test_regress/t/t_interface_ar2b.v | 2 +- test_regress/t/t_interface_array_nocolon.v | 2 +- .../t/t_interface_array_nocolon_bad.v | 2 +- test_regress/t/t_interface_gen10.v | 2 +- test_regress/t/t_interface_gen11.v | 2 +- test_regress/t/t_interface_gen5.v | 2 +- test_regress/t/t_interface_gen6.v | 2 +- test_regress/t/t_interface_gen7.v | 2 +- test_regress/t/t_interface_gen8.v | 2 +- test_regress/t/t_interface_gen9.v | 2 +- test_regress/t/t_interface_localparam.v | 2 +- test_regress/t/t_interface_mp_func.v | 2 +- .../t/t_interface_nested_struct_param.v | 97 ++- .../t/t_interface_param_another_bad.v | 2 +- .../t/t_jumps_uninit_destructor_call.v | 4 +- test_regress/t/t_lint_const_func_dpi_bad.v | 2 +- test_regress/t/t_lint_const_func_gen_bad.v | 2 +- test_regress/t/t_lint_infinite_bad.v | 2 +- test_regress/t/t_lint_once_bad.v | 2 +- test_regress/t/t_lint_only.v | 2 +- test_regress/t/t_lint_repeat_bad.v | 2 +- test_regress/t/t_lint_restore_bad.v | 2 +- test_regress/t/t_lint_restore_prag_bad.v | 2 +- test_regress/t/t_lint_subout_bad.v | 2 +- test_regress/t/t_lint_width.v | 2 +- test_regress/t/t_lint_width_bad.v | 2 +- test_regress/t/t_lparam_assign_iface_const.v | 29 +- .../t/t_lparam_assign_iface_typedef_bad.v | 14 +- test_regress/t/t_lparam_dep_iface0.v | 25 +- test_regress/t/t_lparam_dep_iface1.v | 27 +- test_regress/t/t_lparam_dep_iface10.v | 29 +- test_regress/t/t_lparam_dep_iface11.v | 33 +- test_regress/t/t_lparam_dep_iface12.v | 39 +- test_regress/t/t_lparam_dep_iface13.v | 66 +- test_regress/t/t_lparam_dep_iface14.v | 56 +- test_regress/t/t_lparam_dep_iface15.v | 50 +- test_regress/t/t_lparam_dep_iface16.v | 47 +- test_regress/t/t_lparam_dep_iface2.v | 28 +- test_regress/t/t_lparam_dep_iface3.v | 64 +- test_regress/t/t_lparam_dep_iface4.v | 31 +- test_regress/t/t_lparam_dep_iface5.v | 42 +- test_regress/t/t_lparam_dep_iface6.v | 37 +- test_regress/t/t_lparam_dep_iface7.v | 31 +- test_regress/t/t_lparam_dep_iface8.v | 33 +- test_regress/t/t_lparam_dep_iface9.v | 33 +- test_regress/t/t_mailbox_concurrent.v | 2 +- test_regress/t/t_math_width.v | 2 +- test_regress/t/t_mod_interface_clocking_bad.v | 2 +- test_regress/t/t_mod_longname.v | 2 +- test_regress/t/t_name_collision.v | 2 +- test_regress/t/t_opt_merge_cond_relaxed.v | 46 +- test_regress/t/t_package_abs.v | 2 +- test_regress/t/t_package_ddecl.v | 2 +- test_regress/t/t_param_default_override.v | 2 +- test_regress/t/t_param_pattern2.v | 2 +- test_regress/t/t_param_real.v | 2 +- test_regress/t/t_param_real2.v | 2 +- test_regress/t/t_param_type_cmp.v | 2 +- .../t/t_param_type_from_iface_struct.v | 60 +- test_regress/t/t_param_up_bad.v | 2 +- .../t/t_paramgraph_ascrange_prelim_cfg.v | 16 +- test_regress/t/t_paramgraph_bisect1.v | 53 +- test_regress/t/t_paramgraph_bits_corruption.v | 10 +- .../t/t_paramgraph_bits_iface_typedef.v | 42 +- test_regress/t/t_paramgraph_cloned_refdtype.v | 21 +- test_regress/t/t_paramgraph_comined_iface.v | 41 +- .../t/t_paramgraph_iface_array_ports.v | 16 +- test_regress/t/t_paramgraph_iface_cfg_zero.v | 14 +- test_regress/t/t_paramgraph_iface_deadmod.v | 16 +- .../t/t_paramgraph_iface_dependency1.v | 30 +- .../t/t_paramgraph_iface_dependency2.v | 24 +- .../t/t_paramgraph_iface_dependency3.v | 34 +- .../t/t_paramgraph_iface_param_from_port.v | 38 +- test_regress/t/t_paramgraph_iface_pin.v | 26 +- .../t/t_paramgraph_iface_port_typedef.v | 31 +- .../t/t_paramgraph_iface_template_mismatch.v | 22 +- .../t/t_paramgraph_iface_template_mismatch2.v | 22 +- .../t/t_paramgraph_iface_template_mismatch3.v | 26 +- .../t/t_paramgraph_iface_template_nested.v | 48 +- ...t_paramgraph_member_refdtype_iface_chain.v | 2 +- ..._paramgraph_member_refdtype_iface_struct.v | 2 +- ...paramgraph_member_refdtype_iface_typedef.v | 2 +- .../t_paramgraph_member_refdtype_pkg_iface.v | 14 +- test_regress/t/t_paramgraph_minimal_sibling.v | 29 +- .../t/t_paramgraph_nested_iface_typedef.v | 44 +- test_regress/t/t_paramgraph_param_not_const.v | 25 +- .../t/t_paramgraph_paramtype_default.v | 36 +- test_regress/t/t_paramgraph_refdtype_iface.v | 2 +- .../t/t_paramgraph_refdtype_unlinked.v | 12 +- test_regress/t/t_paramgraph_selbit_dtype.v | 85 +- ...t_paramgraph_simple_cache_localparam_cfg.v | 73 +- .../t/t_paramgraph_simple_cache_types_if.v | 51 +- test_regress/t/t_pp_lib.v | 2 +- test_regress/t/t_preproc_str_undef.v | 2 +- test_regress/t/t_process_propagation.v | 2 +- test_regress/t/t_process_task.v | 2 +- test_regress/t/t_public_clk.v | 2 +- test_regress/t/t_queue_insert_at_end.v | 2 +- test_regress/t/t_randomize_std_static.v | 9 +- test_regress/t/t_real_param.v | 2 +- test_regress/t/t_recursive_typedef_bad.v | 2 +- test_regress/t/t_select_bound3.v | 2 +- test_regress/t/t_selrange_iface_type_param.v | 550 +++++++------ test_regress/t/t_semaphore_concurrent.v | 2 +- test_regress/t/t_split_var_1_bad.v | 2 +- .../t/t_static_function_in_class_noparen.v | 2 +- test_regress/t/t_std_process_self.v | 2 +- test_regress/t/t_struct_genfor.v | 2 +- test_regress/t/t_structu_wide.v | 2 +- test_regress/t/t_sys_readmem_eof.v | 2 +- test_regress/t/t_timing_dynscope.v | 2 +- test_regress/t/t_timing_split.v | 2 +- test_regress/t/t_trace_split_cfuncs.v | 2 +- .../t/t_trace_split_cfuncs_dpi_export.v | 2 +- test_regress/t/t_type_param.v | 2 +- test_regress/t/t_udp_nonsequential_x.v | 2 +- test_regress/t/t_var_extern_method_lifetime.v | 2 +- test_regress/t/t_var_in_fork.v | 2 +- test_regress/t/t_x_rand_scoped_is_random.v | 2 +- 340 files changed, 7037 insertions(+), 6797 deletions(-) diff --git a/test_regress/t/t_a1_first_cc.v b/test_regress/t/t_a1_first_cc.v index 03a9a497f..5a21736e5 100644 --- a/test_regress/t/t_a1_first_cc.v +++ b/test_regress/t/t_a1_first_cc.v @@ -4,17 +4,14 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - - // Test loop - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // Test loop + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_alias_unsup.v b/test_regress/t/t_alias_unsup.v index 3fc958d2e..ca79ccc37 100644 --- a/test_regress/t/t_alias_unsup.v +++ b/test_regress/t/t_alias_unsup.v @@ -19,9 +19,9 @@ module t ( /*AUTOARG*/ input clk; - int cyc; - reg [63:0] crc; - reg [63:0] sum; + int cyc; + reg [63:0] crc; + reg [63:0] sum; // Values to swap and locations for the swapped values. wire [31:0] x_fwd = crc[31:0]; @@ -51,11 +51,11 @@ module t ( /*AUTOARG*/ // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; - end else if (cyc < 10) begin + end + else if (cyc < 10) begin sum <= '0; - end else - if (cyc < 90) begin - end else if (cyc == 99) begin + end + else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); `checkh(crc, 64'hc77bb9b3784ea091); // What checksum will we end up with (above print should match) diff --git a/test_regress/t/t_array_backw_index_bad.out b/test_regress/t/t_array_backw_index_bad.out index 4f63b9cb9..15104534a 100644 --- a/test_regress/t/t_array_backw_index_bad.out +++ b/test_regress/t/t_array_backw_index_bad.out @@ -1,30 +1,30 @@ -%Error: t/t_array_backw_index_bad.v:17:19: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]' +%Error: t/t_array_backw_index_bad.v:17:17: Slice selection '[1:3]' has reversed range order versus data type's '[3:0]' : ... note: In instance 't' - 17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; - | ^ + 17 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_array_backw_index_bad.v:18:20: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]' +%Error: t/t_array_backw_index_bad.v:18:18: Slice selection '[3:1]' has reversed range order versus data type's '[0:3]' : ... note: In instance 't' - 18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; - | ^ -%Error: t/t_array_backw_index_bad.v:19:20: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]' + 18 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + | ^ +%Error: t/t_array_backw_index_bad.v:19:18: Slice selection '[4:6]' has reversed range order versus data type's '[6:3]' : ... note: In instance 't' - 19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; - | ^ -%Error: t/t_array_backw_index_bad.v:20:21: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]' + 19 | array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; + | ^ +%Error: t/t_array_backw_index_bad.v:20:19: Slice selection '[6:4]' has reversed range order versus data type's '[3:6]' : ... note: In instance 't' - 20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; - | ^ -%Error: t/t_array_backw_index_bad.v:22:19: Slice selection index '[4:3]' outside data type's '[3:0]' - : ... note: In instance 't' - 22 | array_assign[4:3] = '{32'd4, 32'd3}; + 20 | larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; | ^ -%Error: t/t_array_backw_index_bad.v:23:19: Slice selection index '[1:-1]' outside data type's '[3:0]' +%Error: t/t_array_backw_index_bad.v:22:17: Slice selection index '[4:3]' outside data type's '[3:0]' : ... note: In instance 't' - 23 | array_assign[1:-1] = '{32'd4, 32'd3}; - | ^ -%Error: t/t_array_backw_index_bad.v:23:28: Assignment pattern missed initializing elements: -1 + 22 | array_assign[4:3] = '{32'd4, 32'd3}; + | ^ +%Error: t/t_array_backw_index_bad.v:23:17: Slice selection index '[1:-1]' outside data type's '[3:0]' : ... note: In instance 't' - 23 | array_assign[1:-1] = '{32'd4, 32'd3}; - | ^~ + 23 | array_assign[1:-1] = '{32'd4, 32'd3}; + | ^ +%Error: t/t_array_backw_index_bad.v:23:26: Assignment pattern missed initializing elements: -1 + : ... note: In instance 't' + 23 | array_assign[1:-1] = '{32'd4, 32'd3}; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_array_backw_index_bad.v b/test_regress/t/t_array_backw_index_bad.v index fddcfa3a0..1651ce17e 100644 --- a/test_regress/t/t_array_backw_index_bad.v +++ b/test_regress/t/t_array_backw_index_bad.v @@ -6,27 +6,27 @@ module t; - logic [31:0] array_assign [3:0]; + logic [31:0] array_assign[3:0]; - logic [31:0] larray_assign [0:3]; + logic [31:0] larray_assign[0:3]; - logic [31:0] array_assign2 [6:3]; + logic [31:0] array_assign2[6:3]; - logic [31:0] larray_assign2 [3:6]; - initial begin - array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; - larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; - array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; - larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; + logic [31:0] larray_assign2[3:6]; + initial begin + array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + array_assign2[4:6] = '{32'd4, 32'd3, 32'd2}; + larray_assign2[6:4] = '{32'd4, 32'd3, 32'd2}; - array_assign[4:3] = '{32'd4, 32'd3}; - array_assign[1:-1] = '{32'd4, 32'd3}; - array_assign[1:1] = '{32'd4}; // Ok - larray_assign[1:1] = '{32'd4}; // Ok - array_assign2[4:4] = '{32'd4}; // Ok - larray_assign2[4:4] = '{32'd4}; // Ok + array_assign[4:3] = '{32'd4, 32'd3}; + array_assign[1:-1] = '{32'd4, 32'd3}; + array_assign[1:1] = '{32'd4}; // Ok + larray_assign[1:1] = '{32'd4}; // Ok + array_assign2[4:4] = '{32'd4}; // Ok + larray_assign2[4:4] = '{32'd4}; // Ok - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_compare.v b/test_regress/t/t_array_compare.v index e27d03a0f..ffae2101f 100644 --- a/test_regress/t/t_array_compare.v +++ b/test_regress/t/t_array_compare.v @@ -8,52 +8,52 @@ module t; - reg [3:0] array_1 [2:0]; - reg [3:0] array_2 [2:0]; - reg [3:0] array_3 [3:1]; + reg [3:0] array_1[2:0]; + reg [3:0] array_2[2:0]; + reg [3:0] array_3[3:1]; - reg [3:0] elem; + reg [3:0] elem; - reg array_1_ne_array_2; - reg array_1_eq_array_2; - reg array_1_ne_array_3; - reg array_1_eq_array_3; + reg array_1_ne_array_2; + reg array_1_eq_array_2; + reg array_1_ne_array_3; + reg array_1_eq_array_3; - initial begin - array_1[0] = 4'b1000; - array_1[1] = 4'b1000; - array_1[2] = 4'b1000; + initial begin + array_1[0] = 4'b1000; + array_1[1] = 4'b1000; + array_1[2] = 4'b1000; - array_2[0] = 4'b1000; - array_2[1] = 4'b1000; - array_2[2] = 4'b1000; + array_2[0] = 4'b1000; + array_2[1] = 4'b1000; + array_2[2] = 4'b1000; - array_3[1] = 4'b1000; - array_3[2] = 4'b0100; - array_3[3] = 4'b0100; + array_3[1] = 4'b1000; + array_3[2] = 4'b0100; + array_3[3] = 4'b0100; - array_1_ne_array_2 = array_1 != array_2; // 0 - array_1_eq_array_2 = array_1 == array_2; // 0 - array_1_ne_array_3 = array_1 != array_3; // 1 - array_1_eq_array_3 = array_1 == array_3; // 1 + array_1_ne_array_2 = array_1 != array_2; // 0 + array_1_eq_array_2 = array_1 == array_2; // 0 + array_1_ne_array_3 = array_1 != array_3; // 1 + array_1_eq_array_3 = array_1 == array_3; // 1 - //Not legal: array_rxor = ^ array_1; - //Not legal: array_rxnor = ^~ array_1; - //Not legal: array_ror = | array_1; - //Not legal: array_rand = & array_1; + //Not legal: array_rxor = ^ array_1; + //Not legal: array_rxnor = ^~ array_1; + //Not legal: array_ror = | array_1; + //Not legal: array_rand = & array_1; `ifdef TEST_VERBOSE - $write("array_1_ne_array2==%0d\n", array_1_ne_array_2); - $write("array_1_ne_array3==%0d\n", array_1_ne_array_3); + $write("array_1_ne_array2==%0d\n", array_1_ne_array_2); + $write("array_1_ne_array3==%0d\n", array_1_ne_array_3); `endif - if (array_1_ne_array_2 !== 0) $stop; - if (array_1_eq_array_2 !== 1) $stop; - if (array_1_ne_array_3 !== 1) $stop; - if (array_1_eq_array_3 !== 0) $stop; + if (array_1_ne_array_2 !== 0) $stop; + if (array_1_eq_array_2 !== 1) $stop; + if (array_1_ne_array_3 !== 1) $stop; + if (array_1_eq_array_3 !== 0) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_in_struct.v b/test_regress/t/t_array_in_struct.v index 9c331c894..73cdcea97 100644 --- a/test_regress/t/t_array_in_struct.v +++ b/test_regress/t/t_array_in_struct.v @@ -7,55 +7,51 @@ //bug991 module t; - typedef struct { - logic [31:0] arr [3:0]; - } a_t; + typedef struct {logic [31:0] arr[3:0];} a_t; - typedef struct { - logic [31:0] arr [0:3]; - } b_t; + typedef struct {logic [31:0] arr[0:3];} b_t; - a_t array_assign; - a_t array_other; + a_t array_assign; + a_t array_other; - b_t larray_assign; - b_t larray_other; + b_t larray_assign; + b_t larray_other; - initial begin - array_assign.arr[0] = 32'd1; - array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2}; + initial begin + array_assign.arr[0] = 32'd1; + array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2}; - array_other.arr[0] = array_assign.arr[0]+10; - array_other.arr[3:1] = array_assign.arr[3:1]; - if (array_other.arr[0] != 11) $stop; - if (array_other.arr[1] != 2) $stop; - if (array_other.arr[2] != 3) $stop; - if (array_other.arr[3] != 4) $stop; + array_other.arr[0] = array_assign.arr[0] + 10; + array_other.arr[3:1] = array_assign.arr[3:1]; + if (array_other.arr[0] != 11) $stop; + if (array_other.arr[1] != 2) $stop; + if (array_other.arr[2] != 3) $stop; + if (array_other.arr[3] != 4) $stop; - larray_assign.arr[0] = 32'd1; - larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2}; + larray_assign.arr[0] = 32'd1; + larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2}; - larray_other.arr[0] = larray_assign.arr[0]+10; - larray_other.arr[1:3] = larray_assign.arr[1:3]; - if (larray_other.arr[0] != 11) $stop; - if (larray_other.arr[1] != 4) $stop; - if (larray_other.arr[2] != 3) $stop; - if (larray_other.arr[3] != 2) $stop; + larray_other.arr[0] = larray_assign.arr[0] + 10; + larray_other.arr[1:3] = larray_assign.arr[1:3]; + if (larray_other.arr[0] != 11) $stop; + if (larray_other.arr[1] != 4) $stop; + if (larray_other.arr[2] != 3) $stop; + if (larray_other.arr[3] != 2) $stop; - larray_other.arr = '{5, 6, 7, 8}; - if (larray_other.arr[0] != 5) $stop; - if (larray_other.arr[1] != 6) $stop; - if (larray_other.arr[2] != 7) $stop; - if (larray_other.arr[3] != 8) $stop; + larray_other.arr = '{5, 6, 7, 8}; + if (larray_other.arr[0] != 5) $stop; + if (larray_other.arr[1] != 6) $stop; + if (larray_other.arr[2] != 7) $stop; + if (larray_other.arr[3] != 8) $stop; - larray_other.arr = larray_assign.arr; - if (larray_other.arr[0] != 1) $stop; - if (larray_other.arr[1] != 4) $stop; - if (larray_other.arr[2] != 3) $stop; - if (larray_other.arr[3] != 2) $stop; + larray_other.arr = larray_assign.arr; + if (larray_other.arr[0] != 1) $stop; + if (larray_other.arr[1] != 4) $stop; + if (larray_other.arr[2] != 3) $stop; + if (larray_other.arr[3] != 2) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_index_increment.v b/test_regress/t/t_array_index_increment.v index b7588d035..567af8001 100644 --- a/test_regress/t/t_array_index_increment.v +++ b/test_regress/t/t_array_index_increment.v @@ -6,122 +6,124 @@ module t; - string test_string = "abcd"; + string test_string = "abcd"; - int array3d[2][3][4] = '{ - '{ - '{ 0, 1, 2, 3}, - '{ 4, 5, 6, 7}, - '{ 8, 9, 10, 11} - }, - '{ - '{ 12, 13, 14, 15}, - '{ 16, 17, 18, 19}, - '{ 20, 21, 22, 23} - } - }; - int pos; - int val; - int i; - byte b; + // verilog_format: off + int array3d[2][3][4] = '{ + '{'{ 0, 1, 2, 3}, + '{ 4, 5, 6, 7}, + '{ 8, 9, 10, 11} + }, + '{'{ 12, 13, 14, 15}, + '{ 16, 17, 18, 19}, + '{ 20, 21, 22, 23} + } + }; + // verilog_format: on + int pos; + int val; + int i; + byte b; - int data[4] = '{1, 2, 3, 4}; + int data[4] = '{1, 2, 3, 4}; - generate - genvar j; - int gdata[4]; - for (j=0; j < 5; j++) begin - initial if (j >= 5) $stop; - end + generate + genvar j; + int gdata[4]; + for (j = 0; j < 5; j++) begin + initial if (j >= 5) $stop; + end - for (j=0; j < 5; ++j) begin - initial if (j >= 5) $stop; - end + for (j = 0; j < 5; ++j) begin + initial if (j >= 5) $stop; + end - for (j=10; j >= 5; j--) begin - initial if (j < 5) $stop; - end + for (j = 10; j >= 5; j--) begin + initial if (j < 5) $stop; + end - for (j=10; j >= 5; --j) begin - initial if (j < 5) $stop; - end - endgenerate + for (j = 10; j >= 5; --j) begin + initial if (j < 5) $stop; + end + endgenerate - initial begin - pos = 0; + initial begin + pos = 0; + pos++; + if (pos != 1) $stop; + + array3d[0][0][0]++; + if (array3d[0][0][0] != 1) $stop; + + --array3d[0][0][0]; + if (array3d[0][0][0] != 0) $stop; + + pos = 2; + b = test_string[--pos]; + if (b !== "b") $stop; + if (pos !== 1) $stop; + + pos = 1; + b = test_string[++pos]; + if (b !== "c") $stop; + if (pos !== 2) $stop; + + pos = 3; + b = test_string[pos--]; + if (b !== "d") $stop; + if (pos !== 2) $stop; + + pos = 0; + b = test_string[pos++]; + if (b !== "a") $stop; + if (pos !== 1) $stop; + + pos = 0; + val = array3d[++pos][--pos][++pos]; + if (pos !== 1) $stop; + if (val !== 13) $stop; + + pos = 0; + val = array3d[++pos][pos--][++pos]; + if (pos !== 1) $stop; + if (val !== 17) $stop; + + for (i = 0; data[++i] < 4;) begin + // loop with multiple statements + pos = i; + val = data[i]; + end + + if (pos !== 2) $stop; + if (i !== 3) $stop; + if (val !== 3) $stop; + + i = 0; + while (data[ + i++ + ] < 4) begin + // loop with multiple statements + pos = i; + val = data[i]; + end + + if (pos !== 3) $stop; + if (i !== 4) $stop; + if (val !== 4) $stop; + + + pos = 0; + if (1 == 1) begin pos++; - if (pos != 1) $stop; + end + if (pos != 1) $stop; - array3d[0][0][0]++; - if (array3d[0][0][0] != 1) $stop; + pos = 0; + if (1 == 1) pos++; + if (pos != 1) $stop; - --array3d[0][0][0]; - if (array3d[0][0][0] != 0) $stop; + $write("*-* All Finished *-*\n"); + $finish; - pos = 2; - b = test_string[--pos]; - if (b !== "b") $stop; - if (pos !== 1) $stop; - - pos = 1; - b = test_string[++pos]; - if (b !== "c") $stop; - if (pos !== 2) $stop; - - pos = 3; - b = test_string[pos--]; - if (b !== "d") $stop; - if (pos !== 2) $stop; - - pos = 0; - b = test_string[pos++]; - if (b !== "a") $stop; - if (pos !== 1) $stop; - - pos = 0; - val = array3d[++pos][--pos][++pos]; - if (pos !== 1) $stop; - if (val !== 13) $stop; - - pos = 0; - val = array3d[++pos][pos--][++pos]; - if (pos !== 1) $stop; - if (val !== 17) $stop; - - for (i=0; data[++i]<4;) begin - // loop with multiple statements - pos = i; - val = data[i]; - end - - if (pos !== 2) $stop; - if (i !== 3) $stop; - if (val !== 3) $stop; - - i = 0; - while (data[i++]<4) begin - // loop with multiple statements - pos = i; - val = data[i]; - end - - if (pos !== 3) $stop; - if (i !== 4) $stop; - if (val !== 4) $stop; - - - pos = 0; - if (1 == 1) begin - pos++; - end - if (pos != 1) $stop; - - pos = 0; - if (1 == 1) pos++; - if (pos != 1) $stop; - - $write("*-* All Finished *-*\n"); - $finish; - - end + end endmodule diff --git a/test_regress/t/t_array_index_side.v b/test_regress/t/t_array_index_side.v index 5992f9898..fb00ee94b 100644 --- a/test_regress/t/t_array_index_side.v +++ b/test_regress/t/t_array_index_side.v @@ -10,47 +10,47 @@ // verilog_format: on class Cls; - int m_index; + int m_index; - function automatic int get_index(); - int rtn; - rtn = m_index; - ++m_index; + function automatic int get_index(); + int rtn; + rtn = m_index; + ++m_index; `ifdef VERILATOR - return $c(rtn); // Avoid optimizations + return $c(rtn); // Avoid optimizations `else - return rtn; + return rtn; `endif - endfunction + endfunction endclass module t; - Cls cls; - int array[10]; + Cls cls; + int array[10]; - initial begin - cls = new; - // Common UVM construct 'id_cnt[get_id()]++;' - // Properly avoid/handle SIDEEFF warnings - cls.m_index = 5; - array[5] = 50; - array[6] = 60; - array[7] = 70; - array[8] = 80; + initial begin + cls = new; + // Common UVM construct 'id_cnt[get_id()]++;' + // Properly avoid/handle SIDEEFF warnings + cls.m_index = 5; + array[5] = 50; + array[6] = 60; + array[7] = 70; + array[8] = 80; - array[cls.get_index()]++; - `checkd(array[5], 51); - array[cls.get_index()]++; - `checkd(array[6], 61); + array[cls.get_index()]++; + `checkd(array[5], 51); + array[cls.get_index()]++; + `checkd(array[6], 61); - ++array[cls.get_index()]; - `checkd(array[7], 71); - ++array[cls.get_index()]; - `checkd(array[8], 81); + ++array[cls.get_index()]; + `checkd(array[7], 71); + ++array[cls.get_index()]; + `checkd(array[8], 81); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_list_bad.out b/test_regress/t/t_array_list_bad.out index c298dd605..5d24a7452 100644 --- a/test_regress/t/t_array_list_bad.out +++ b/test_regress/t/t_array_list_bad.out @@ -1,12 +1,12 @@ -%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: 'logic' 't3' +%Error: t/t_array_list_bad.v:37:21: Assignment pattern missed initializing elements: 'logic' 't3' : ... note: In instance 't' - 38 | test_out <= '{'0, '0}; - | ^~ + 37 | test_out <= '{'0, '0}; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Warning-WIDTHEXPAND: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. +%Warning-WIDTHEXPAND: t/t_array_list_bad.v:37:18: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. : ... note: In instance 't' - 38 | test_out <= '{'0, '0}; - | ^~ + 37 | test_out <= '{'0, '0}; + | ^~ ... For warning description see https://verilator.org/warn/WIDTHEXPAND?v=latest ... Use "/* verilator lint_off WIDTHEXPAND */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_array_list_bad.v b/test_regress/t/t_array_list_bad.v index 8841a602e..8ac05b927 100644 --- a/test_regress/t/t_array_list_bad.v +++ b/test_regress/t/t_array_list_bad.v @@ -5,38 +5,37 @@ // SPDX-License-Identifier: CC0-1.0 package pkg; - typedef struct packed { - logic t1; - logic t2; - logic t3; - } type_t; + typedef struct packed { + logic t1; + logic t2; + logic t3; + } type_t; endpackage : pkg -module t - ( - input logic sys_clk, - input logic sys_rst_n, - input logic sys_ena, +module t ( + input logic sys_clk, + input logic sys_rst_n, + input logic sys_ena, - input pkg::type_t test_in, - output pkg::type_t test_out - ); + input pkg::type_t test_in, + output pkg::type_t test_out +); - import pkg::*; + import pkg::*; - always_ff @(posedge sys_clk or negedge sys_rst_n) begin - if (~sys_rst_n) begin - test_out <= '{'0, '0, '0}; + always_ff @(posedge sys_clk or negedge sys_rst_n) begin + if (~sys_rst_n) begin + test_out <= '{'0, '0, '0}; + end + else begin + if (sys_ena) begin + test_out.t1 <= ~test_in.t1; + test_out.t2 <= ~test_in.t2; + test_out.t3 <= ~test_in.t3; end else begin - if(sys_ena) begin - test_out.t1 <= ~test_in.t1; - test_out.t2 <= ~test_in.t2; - test_out.t3 <= ~test_in.t3; - end - else begin - test_out <= '{'0, '0}; /* Inconsistent array list; */ - end + test_out <= '{'0, '0}; /* Inconsistent array list; */ end - end -endmodule: t + end + end +endmodule : t diff --git a/test_regress/t/t_array_mda.v b/test_regress/t/t_array_mda.v index bfa7116e9..3259fad33 100644 --- a/test_regress/t/t_array_mda.v +++ b/test_regress/t/t_array_mda.v @@ -4,66 +4,66 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // msg2946 - int A [7][1], B [8][1]; - int a [1], b [1]; - always_ff @(posedge clk) begin - a <= A[crc[2:0]]; - b <= B[crc[2:0]]; - end - wire [63:0] result = {a[0], b[0]}; + // msg2946 + int A[7][1], B[8][1]; + int a[1], b[1]; + always_ff @(posedge clk) begin + a <= A[crc[2:0]]; + b <= B[crc[2:0]]; + end + wire [63:0] result = {a[0], b[0]}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - A[0][0] <= 32'h1_0; - A[1][0] <= 32'h1_1; - A[2][0] <= 32'h1_2; - A[3][0] <= 32'h1_3; - A[4][0] <= 32'h1_4; - A[5][0] <= 32'h1_5; - A[6][0] <= 32'h1_6; - B[0][0] <= 32'h2_0; - B[1][0] <= 32'h2_1; - B[2][0] <= 32'h2_2; - B[3][0] <= 32'h2_3; - B[4][0] <= 32'h2_4; - B[5][0] <= 32'h2_5; - B[6][0] <= 32'h2_6; - B[7][0] <= 32'h2_7; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h619f75c3a6d948bd - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + A[0][0] <= 32'h1_0; + A[1][0] <= 32'h1_1; + A[2][0] <= 32'h1_2; + A[3][0] <= 32'h1_3; + A[4][0] <= 32'h1_4; + A[5][0] <= 32'h1_5; + A[6][0] <= 32'h1_6; + B[0][0] <= 32'h2_0; + B[1][0] <= 32'h2_1; + B[2][0] <= 32'h2_2; + B[3][0] <= 32'h2_3; + B[4][0] <= 32'h2_4; + B[5][0] <= 32'h2_5; + B[6][0] <= 32'h2_6; + B[7][0] <= 32'h2_7; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h619f75c3a6d948bd + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_array_method_bad.out b/test_regress/t/t_array_method_bad.out index 8e2cf6c76..6c6358d9f 100644 --- a/test_regress/t/t_array_method_bad.out +++ b/test_regress/t/t_array_method_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_array_method_bad.v:11:9: Unknown built-in array method 'mex' +%Error: t/t_array_method_bad.v:11:7: Unknown built-in array method 'mex' : ... note: In instance 't' - 11 | q.mex; - | ^~~ + 11 | q.mex; + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_array_method_bad.v b/test_regress/t/t_array_method_bad.v index 5f8250831..b27f98591 100644 --- a/test_regress/t/t_array_method_bad.v +++ b/test_regress/t/t_array_method_bad.v @@ -5,12 +5,12 @@ // SPDX-License-Identifier: CC0-1.0 module t; - initial begin - int q[5]; + initial begin + int q[5]; - q.mex; + q.mex; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_method_map.out b/test_regress/t/t_array_method_map.out index 054088ab2..3e1bac262 100644 --- a/test_regress/t/t_array_method_map.out +++ b/test_regress/t/t_array_method_map.out @@ -1,11 +1,11 @@ -%Error-UNSUPPORTED: t/t_array_method_map.v:19:15: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5) +%Error-UNSUPPORTED: t/t_array_method_map.v:19:13: Unsupported: Array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' - 19 | res = a.map(el) with (el == 200); - | ^~~ + 19 | res = a.map(el) with (el == 200); + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_array_method_map.v:19:15: Unknown built-in array method 'map' +%Error: t/t_array_method_map.v:19:13: Unknown built-in array method 'map' : ... note: In instance 't' - 19 | res = a.map(el) with (el == 200); - | ^~~ + 19 | res = a.map(el) with (el == 200); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_array_method_map.v b/test_regress/t/t_array_method_map.v index 8025971f7..849307035 100644 --- a/test_regress/t/t_array_method_map.v +++ b/test_regress/t/t_array_method_map.v @@ -11,15 +11,15 @@ module t; - initial begin - automatic int res[]; - automatic int a[3] = '{100, 200, 300}; + initial begin + automatic int res[]; + automatic int a[3] = '{100, 200, 300}; - // TODO results not known to be correct - res = a.map(el) with (el == 200); - `checkh(res.size, 3); - `checkh(res[0], 0); - `checkh(res[1], 1); - `checkh(res[2], 0); - end + // TODO results not known to be correct + res = a.map(el) with (el == 200); + `checkh(res.size, 3); + `checkh(res[0], 0); + `checkh(res[1], 1); + `checkh(res[2], 0); + end endmodule diff --git a/test_regress/t/t_array_non_blocking_loop.v b/test_regress/t/t_array_non_blocking_loop.v index f7bab41db..e7ba5a267 100644 --- a/test_regress/t/t_array_non_blocking_loop.v +++ b/test_regress/t/t_array_non_blocking_loop.v @@ -5,34 +5,31 @@ // SPDX-License-Identifier: CC0-1.0 -interface intf - #( - parameter int WRITE_DATA_WIDTH) (); - logic [WRITE_DATA_WIDTH-1:0] writedata; +interface intf #( + parameter int WRITE_DATA_WIDTH +) (); + logic [WRITE_DATA_WIDTH-1:0] writedata; endinterface -module t( /*AUTOARG*/ +module t ( /*AUTOARG*/ clk ); - input clk; - generate - genvar num_chunks; - for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n - localparam int decoded_width = 55 * num_chunks; - intf #( - .WRITE_DATA_WIDTH(decoded_width)) - the_intf (); - always @(posedge clk) begin - for (int i = 0; i < decoded_width; i++) - the_intf.writedata[i] <= '1; - $display("%0d", the_intf.writedata); - end - end - endgenerate + input clk; + generate + genvar num_chunks; + for (num_chunks = 1; num_chunks <= 2; num_chunks++) begin : gen_n + localparam int decoded_width = 55 * num_chunks; + intf #(.WRITE_DATA_WIDTH(decoded_width)) the_intf (); + always @(posedge clk) begin + for (int i = 0; i < decoded_width; i++) the_intf.writedata[i] <= '1; + $display("%0d", the_intf.writedata); + end + end + endgenerate - // finish report - always @ (posedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // finish report + always @(posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_packed_endian.v b/test_regress/t/t_array_packed_endian.v index 43787bd2a..bf2ab8c90 100644 --- a/test_regress/t/t_array_packed_endian.v +++ b/test_regress/t/t_array_packed_endian.v @@ -4,28 +4,28 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +// verilog_format: off + +typedef struct packed {logic [7:0] a;} tb_t; typedef struct packed { - logic [7:0] a; -} tb_t; - -typedef struct packed { - // verilator lint_off ASCRANGE - logic [0:7] a; - // verilator lint_on ASCRANGE + // verilator lint_off ASCRANGE + logic [0:7] a; + // verilator lint_on ASCRANGE } tl_t; typedef struct packed { - logic [7:0] bb; - // verilator lint_off ASCRANGE - tb_t [0:1] cbl; - tb_t [1:0] cbb; - tl_t [0:1] cll; - tl_t [1:0] clb; - logic [0:7] dl; - // verilator lint_on ASCRANGE + logic [7:0] bb; + // verilator lint_off ASCRANGE + tb_t [0:1] cbl; + tb_t [1:0] cbb; + tl_t [0:1] cll; + tl_t [1:0] clb; + logic [0:7] dl; + // verilator lint_on ASCRANGE } t2; logic [2:0][31:0] test2l; @@ -36,60 +36,60 @@ logic [0:2][31:0] test1b; logic [2:0][31:0] test1l; module t; - t2 t; - initial begin - t = 80'hcd_1f2f3f4f_5f6f7f8f_c2; - `checkh(t.bb, 8'hcd); - `checkh(t.cbl[0].a, 8'h1f); - `checkh(t.cbl[1].a, 8'h2f); - `checkh(t.cbb[0].a, 8'h4f); - `checkh(t.cbb[1].a, 8'h3f); - `checkh(t.cll[0].a, 8'h5f); - `checkh(t.cll[1].a, 8'h6f); - `checkh(t.clb[0].a, 8'h8f); - `checkh(t.clb[1].a, 8'h7f); - `checkh(t.dl, 8'hc2); + t2 t; + initial begin + t = 80'hcd_1f2f3f4f_5f6f7f8f_c2; + `checkh(t.bb, 8'hcd); + `checkh(t.cbl[0].a, 8'h1f); + `checkh(t.cbl[1].a, 8'h2f); + `checkh(t.cbb[0].a, 8'h4f); + `checkh(t.cbb[1].a, 8'h3f); + `checkh(t.cll[0].a, 8'h5f); + `checkh(t.cll[1].a, 8'h6f); + `checkh(t.clb[0].a, 8'h8f); + `checkh(t.clb[1].a, 8'h7f); + `checkh(t.dl, 8'hc2); - t = '0; - t.bb = 8'h13; - t.cbl[0].a = 8'hac; - t.cbl[1].a = 8'had; - t.cbb[0].a = 8'hae; - t.cbb[1].a = 8'haf; - t.cll[0].a = 8'hbc; - t.cll[1].a = 8'hbd; - t.clb[0].a = 8'hbe; - t.clb[1].a = 8'hbf; - t.dl = 8'h31; - `checkh(t, 80'h13_acadafae_bcbdbfbe_31); + t = '0; + t.bb = 8'h13; + t.cbl[0].a = 8'hac; + t.cbl[1].a = 8'had; + t.cbb[0].a = 8'hae; + t.cbb[1].a = 8'haf; + t.cll[0].a = 8'hbc; + t.cll[1].a = 8'hbd; + t.clb[0].a = 8'hbe; + t.clb[1].a = 8'hbf; + t.dl = 8'h31; + `checkh(t, 80'h13_acadafae_bcbdbfbe_31); - t = '0; - t.bb[7] = 1'b1; - t.cbl[1].a[1] = 1'b1; - t.cbb[1].a[2] = 1'b1; - t.cll[1].a[3] = 1'b1; - t.clb[1].a[4] = 1'b1; - t.dl[7] = 1'b1; - `checkh(t, 80'h80_0002040000100800_01); + t = '0; + t.bb[7] = 1'b1; + t.cbl[1].a[1] = 1'b1; + t.cbb[1].a[2] = 1'b1; + t.cll[1].a[3] = 1'b1; + t.clb[1].a[4] = 1'b1; + t.dl[7] = 1'b1; + `checkh(t, 80'h80_0002040000100800_01); - test1b = '{0, 1, 2}; - test1l = test1b; - test2l = '{2, 1, 0}; - test2b = test2l; - `checkh(test2l[0], 0); - `checkh(test2l[2], 2); - `checkh(test2l, {32'h2, 32'h1, 32'h0}); - `checkh(test2b[0], 2); - `checkh(test2b[2], 0); - `checkh(test2b, {32'h2, 32'h1, 32'h0}); - `checkh(test1b[0], 0); - `checkh(test1b[2], 2); - `checkh(test1b, {32'h0, 32'h1, 32'h2}); - `checkh(test1l[0], 2); - `checkh(test1l[2], 0); - `checkh(test1l, {32'h0, 32'h1, 32'h2}); + test1b = '{0, 1, 2}; + test1l = test1b; + test2l = '{2, 1, 0}; + test2b = test2l; + `checkh(test2l[0], 0); + `checkh(test2l[2], 2); + `checkh(test2l, {32'h2, 32'h1, 32'h0}); + `checkh(test2b[0], 2); + `checkh(test2b[2], 0); + `checkh(test2b, {32'h2, 32'h1, 32'h0}); + `checkh(test1b[0], 0); + `checkh(test1b[2], 2); + `checkh(test1b, {32'h0, 32'h1, 32'h2}); + `checkh(test1l[0], 2); + `checkh(test1l[2], 0); + `checkh(test1l, {32'h0, 32'h1, 32'h2}); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_packed_sign.v b/test_regress/t/t_array_packed_sign.v index 0f39b5505..7ee6f23aa 100644 --- a/test_regress/t/t_array_packed_sign.v +++ b/test_regress/t/t_array_packed_sign.v @@ -11,50 +11,50 @@ // unless they are of a named type declared as signed. module t; - typedef logic signed [2:0] named_t; - typedef named_t [1:0] named_named_t; - typedef logic signed [1:0][2:0] named_unnamed_t; + typedef logic signed [2:0] named_t; + typedef named_t [1:0] named_named_t; + typedef logic signed [1:0][2:0] named_unnamed_t; - named_named_t [1:0] named_named; - named_unnamed_t [1:0] named_unnamed; - logic signed [1:0][1:0][2:0] unnamed; + named_named_t [1:0] named_named; + named_unnamed_t [1:0] named_unnamed; + logic signed [1:0][1:0][2:0] unnamed; - initial begin - // Set 1 to MSB(=sign bit) - named_named = 12'b100000_000000; - named_unnamed = 12'b100000_000000; - unnamed = 12'b100000_000000; + initial begin + // Set 1 to MSB(=sign bit) + named_named = 12'b100000_000000; + named_unnamed = 12'b100000_000000; + unnamed = 12'b100000_000000; - if ($signed((named_named >>> 1) >> 11) != 0) begin - $stop; - end - if ($signed((named_named[1] >>> 1) >> 5) != 0) begin - $stop; - end - if ($signed((named_named[1][1] >>> 1) >> 2) != 1) begin - $stop; - end + if ($signed((named_named >>> 1) >> 11) != 0) begin + $stop; + end + if ($signed((named_named[1] >>> 1) >> 5) != 0) begin + $stop; + end + if ($signed((named_named[1][1] >>> 1) >> 2) != 1) begin + $stop; + end - if ($signed((named_unnamed >>> 1) >> 11) != 0) begin - $stop; - end - if ($signed((named_unnamed[1] >>> 1) >> 5) != 1) begin - $stop; - end - if ($signed((named_unnamed[1][1] >>> 1) >> 2) != 0) begin - $stop; - end + if ($signed((named_unnamed >>> 1) >> 11) != 0) begin + $stop; + end + if ($signed((named_unnamed[1] >>> 1) >> 5) != 1) begin + $stop; + end + if ($signed((named_unnamed[1][1] >>> 1) >> 2) != 0) begin + $stop; + end - if ($signed((unnamed >>> 1) >> 11) != 1) begin - $stop;// - end - if ($signed((unnamed[1] >>> 1) >> 5) != 0) begin - $stop; - end - if ($signed((unnamed[1][1] >>> 1) >> 2) != 0) begin - $stop; - end - $write("*-* All Finished *-*\n"); - $finish; - end + if ($signed((unnamed >>> 1) >> 11) != 1) begin + $stop; // + end + if ($signed((unnamed[1] >>> 1) >> 5) != 0) begin + $stop; + end + if ($signed((unnamed[1][1] >>> 1) >> 2) != 0) begin + $stop; + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v index fa081a1c3..e31d38929 100644 --- a/test_regress/t/t_array_packed_sysfunct.v +++ b/test_regress/t/t_array_packed_sysfunct.v @@ -4,168 +4,167 @@ // SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk + ); - input clk; + // parameters for array sizes + localparam WA = 4; + localparam WB = 6; + localparam WC = 8; - // parameters for array sizes - localparam WA = 4; - localparam WB = 6; - localparam WC = 8; + // 2D packed arrays + logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array + /* verilator lint_off ASCRANGE */ + logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array + /* verilator lint_on ASCRANGE */ - // 2D packed arrays - logic [WA+1:2] [WB+1:2] [WC+1:2] array_dsc; // descending range array - /* verilator lint_off ASCRANGE */ - logic [2:WA+1] [2:WB+1] [2:WC+1] array_asc; // ascending range array - /* verilator lint_on ASCRANGE */ + logic [1:0] array_unpk [3:2][1:0]; - logic [1:0] array_unpk [3:2][1:0]; + integer cnt = 0; + integer slc = 0; // slice type + integer dim = 0; // dimension + integer wdt = 0; // width - integer cnt = 0; - integer slc = 0; // slice type - integer dim = 0; // dimension - integer wdt = 0; // width - - initial begin - `checkh($dimensions (array_unpk), 3); + initial begin + `checkh($dimensions (array_unpk), 3); `ifndef VCS - `checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009 + `checkh($unpacked_dimensions (array_unpk), 2); // IEEE 2009 `endif - `checkh($bits (array_unpk), 2*2*2); - `checkh($low (array_unpk), 2); - `checkh($high (array_unpk), 3); - `checkh($left (array_unpk), 3); - `checkh($right(array_unpk), 2); - `checkh($increment(array_unpk), 1); - `checkh($size (array_unpk), 2); - end + `checkh($bits (array_unpk), 2*2*2); + `checkh($low (array_unpk), 2); + `checkh($high (array_unpk), 3); + `checkh($left (array_unpk), 3); + `checkh($right(array_unpk), 2); + `checkh($increment(array_unpk), 1); + `checkh($size (array_unpk), 2); + end - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end - // finish report - always @ (posedge clk) - if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // finish report + always @ (posedge clk) + if ( (cnt[30:4]==3) && (cnt[3:2]==2'd3) && (cnt[1:0]==2'd3) ) begin + $write("*-* All Finished *-*\n"); + $finish; + end - integer slc_next; + integer slc_next; - // calculation of dimention sizes - always @ (posedge clk) begin - // slicing type counter - case (cnt[3:2]) - 2'd0 : begin slc_next = 0; end // full array - 2'd1 : begin slc_next = 1; end // single array element - 2'd2 : begin slc_next = 2; end // half array - default: begin slc_next = 0; end - endcase - slc <= slc_next; - // dimension counter - case (cnt[1:0]) - 2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end - 2'd1 : begin dim <= 2; wdt <= WB; end - 2'd2 : begin dim <= 3; wdt <= WC; end - default: begin dim <= 0; wdt <= 0; end - endcase - end + // calculation of dimention sizes + always @ (posedge clk) begin + // slicing type counter + case (cnt[3:2]) + 2'd0 : begin slc_next = 0; end // full array + 2'd1 : begin slc_next = 1; end // single array element + 2'd2 : begin slc_next = 2; end // half array + default: begin slc_next = 0; end + endcase + slc <= slc_next; + // dimension counter + case (cnt[1:0]) + 2'd0 : begin dim <= 1; wdt <= (slc_next==1) ? WA/2 : (slc_next==2) ? WA/2 : WA; end + 2'd1 : begin dim <= 2; wdt <= WB; end + 2'd2 : begin dim <= 3; wdt <= WC; end + default: begin dim <= 0; wdt <= 0; end + endcase + end - always @ (posedge clk) begin + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); + $write("cnt[30:4]=%0d slc=%0d dim=%0d wdt=%0d\n", cnt[30:4], slc, dim, wdt); `endif - if (cnt[30:4]==1) begin - // descending range - if (slc==0) begin - // full array - `checkh($dimensions (array_dsc), 3); - `checkh($bits (array_dsc), WA*WB*WC); - if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_dsc, dim), wdt+1); - `checkh($right (array_dsc, dim), 2 ); - `checkh($low (array_dsc, dim), 2 ); - `checkh($high (array_dsc, dim), wdt+1); - `checkh($increment (array_dsc, dim), 1 ); - `checkh($size (array_dsc, dim), wdt ); - end - end else if (slc==1) begin - // single array element - `checkh($dimensions (array_dsc[2]), 2); - `checkh($bits (array_dsc[2]), WB*WC); - if ((dim>=2)&&(dim<=3)) begin - `checkh($left (array_dsc[2], dim-1), wdt+1); - `checkh($right (array_dsc[2], dim-1), 2 ); - `checkh($low (array_dsc[2], dim-1), 2 ); - `checkh($high (array_dsc[2], dim-1), wdt+1); - `checkh($increment (array_dsc[2], dim-1), 1 ); - `checkh($size (array_dsc[2], dim-1), wdt ); - end + if (cnt[30:4]==1) begin + // descending range + if (slc==0) begin + // full array + `checkh($dimensions (array_dsc), 3); + `checkh($bits (array_dsc), WA*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_dsc, dim), wdt+1); + `checkh($right (array_dsc, dim), 2 ); + `checkh($low (array_dsc, dim), 2 ); + `checkh($high (array_dsc, dim), wdt+1); + `checkh($increment (array_dsc, dim), 1 ); + `checkh($size (array_dsc, dim), wdt ); + end + end else if (slc==1) begin + // single array element + `checkh($dimensions (array_dsc[2]), 2); + `checkh($bits (array_dsc[2]), WB*WC); + if ((dim>=2)&&(dim<=3)) begin + `checkh($left (array_dsc[2], dim-1), wdt+1); + `checkh($right (array_dsc[2], dim-1), 2 ); + `checkh($low (array_dsc[2], dim-1), 2 ); + `checkh($high (array_dsc[2], dim-1), wdt+1); + `checkh($increment (array_dsc[2], dim-1), 1 ); + `checkh($size (array_dsc[2], dim-1), wdt ); + end `ifndef VERILATOR // Unsupported slices don't maintain size correctly - end else if (slc==2) begin - // half array - `checkh($dimensions (array_dsc[WA/2+1:2]), 3); - `checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC); - if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_dsc[WA/2+1:2], dim), wdt+1); - `checkh($right (array_dsc[WA/2+1:2], dim), 2 ); - `checkh($low (array_dsc[WA/2+1:2], dim), 2 ); - `checkh($high (array_dsc[WA/2+1:2], dim), wdt+1); - `checkh($increment (array_dsc[WA/2+1:2], dim), 1 ); - `checkh($size (array_dsc[WA/2+1:2], dim), wdt); - end + end else if (slc==2) begin + // half array + `checkh($dimensions (array_dsc[WA/2+1:2]), 3); + `checkh($bits (array_dsc[WA/2+1:2]), WA/2*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_dsc[WA/2+1:2], dim), wdt+1); + `checkh($right (array_dsc[WA/2+1:2], dim), 2 ); + `checkh($low (array_dsc[WA/2+1:2], dim), 2 ); + `checkh($high (array_dsc[WA/2+1:2], dim), wdt+1); + `checkh($increment (array_dsc[WA/2+1:2], dim), 1 ); + `checkh($size (array_dsc[WA/2+1:2], dim), wdt); + end `endif - end - end else if (cnt[30:4]==2) begin - // ascending range - if (slc==0) begin - // full array - `checkh($dimensions (array_asc), 3); - `checkh($bits (array_asc), WA*WB*WC); - if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_asc, dim), 2 ); - `checkh($right (array_asc, dim), wdt+1); - `checkh($low (array_asc, dim), 2 ); - `checkh($high (array_asc, dim), wdt+1); - `checkh($increment (array_asc, dim), -1 ); - `checkh($size (array_asc, dim), wdt ); - end - end else if (slc==1) begin - // single array element - `checkh($dimensions (array_asc[2]), 2); - `checkh($bits (array_asc[2]), WB*WC); - if ((dim>=2)&&(dim<=3)) begin - `checkh($left (array_asc[2], dim-1), 2 ); - `checkh($right (array_asc[2], dim-1), wdt+1); - `checkh($low (array_asc[2], dim-1), 2 ); - `checkh($high (array_asc[2], dim-1), wdt+1); - `checkh($increment (array_asc[2], dim-1), -1 ); - `checkh($size (array_asc[2], dim-1), wdt ); - end -`ifndef VERILATOR // Unsupported slices don't maintain size correctly - end else if (slc==2) begin - // half array - `checkh($dimensions (array_asc[2:WA/2+1]), 3); - `checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC); - if ((dim>=1)&&(dim<=3)) begin - `checkh($left (array_asc[2:WA/2+1], dim), 2 ); - `checkh($right (array_asc[2:WA/2+1], dim), wdt+1); - `checkh($low (array_asc[2:WA/2+1], dim), 2 ); - `checkh($high (array_asc[2:WA/2+1], dim), wdt+1); - `checkh($increment (array_asc[2:WA/2+1], dim), -1 ); - `checkh($size (array_asc[2:WA/2+1], dim), wdt ); - end -`endif - end end - end + end else if (cnt[30:4]==2) begin + // ascending range + if (slc==0) begin + // full array + `checkh($dimensions (array_asc), 3); + `checkh($bits (array_asc), WA*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_asc, dim), 2 ); + `checkh($right (array_asc, dim), wdt+1); + `checkh($low (array_asc, dim), 2 ); + `checkh($high (array_asc, dim), wdt+1); + `checkh($increment (array_asc, dim), -1 ); + `checkh($size (array_asc, dim), wdt ); + end + end else if (slc==1) begin + // single array element + `checkh($dimensions (array_asc[2]), 2); + `checkh($bits (array_asc[2]), WB*WC); + if ((dim>=2)&&(dim<=3)) begin + `checkh($left (array_asc[2], dim-1), 2 ); + `checkh($right (array_asc[2], dim-1), wdt+1); + `checkh($low (array_asc[2], dim-1), 2 ); + `checkh($high (array_asc[2], dim-1), wdt+1); + `checkh($increment (array_asc[2], dim-1), -1 ); + `checkh($size (array_asc[2], dim-1), wdt ); + end +`ifndef VERILATOR // Unsupported slices don't maintain size correctly + end else if (slc==2) begin + // half array + `checkh($dimensions (array_asc[2:WA/2+1]), 3); + `checkh($bits (array_asc[2:WA/2+1]), WA/2*WB*WC); + if ((dim>=1)&&(dim<=3)) begin + `checkh($left (array_asc[2:WA/2+1], dim), 2 ); + `checkh($right (array_asc[2:WA/2+1], dim), wdt+1); + `checkh($low (array_asc[2:WA/2+1], dim), 2 ); + `checkh($high (array_asc[2:WA/2+1], dim), wdt+1); + `checkh($increment (array_asc[2:WA/2+1], dim), -1 ); + `checkh($size (array_asc[2:WA/2+1], dim), wdt ); + end +`endif + end + end + end endmodule diff --git a/test_regress/t/t_array_packed_write_read.v b/test_regress/t/t_array_packed_write_read.v index 9fca1c2cc..1628d4907 100644 --- a/test_regress/t/t_array_packed_write_read.v +++ b/test_regress/t/t_array_packed_write_read.v @@ -4,145 +4,143 @@ // SPDX-FileCopyrightText: 2012 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // parameters for array sizes + localparam WA = 8; // address dimension size + localparam WB = 8; // bit dimension size - // parameters for array sizes - localparam WA = 8; // address dimension size - localparam WB = 8; // bit dimension size + localparam NO = 10; // number of access events - localparam NO = 10; // number of access events + // 2D packed arrays + logic [WA-1:0][WB-1:0] array_dsc; // descending range array + /* verilator lint_off ASCRANGE */ + logic [0:WA-1][0:WB-1] array_asc; // ascending range array + /* verilator lint_on ASCRANGE */ - // 2D packed arrays - logic [WA-1:0] [WB-1:0] array_dsc; // descending range array - /* verilator lint_off ASCRANGE */ - logic [0:WA-1] [0:WB-1] array_asc; // ascending range array - /* verilator lint_on ASCRANGE */ + integer cnt = 0; - integer cnt = 0; + // msg926 + logic [3:0][31:0] packedArray; + initial packedArray = '0; - // msg926 - logic [3:0][31:0] packedArray; - initial packedArray = '0; + // event counter + always @(posedge clk) begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end - - // finish report - always @ (posedge clk) - if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin + // finish report + always @(posedge clk) + if ((cnt[30:2] == NO) && (cnt[1:0] == 2'd0)) begin $write("*-* All Finished *-*\n"); $finish; - end + end - // descending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) array_dsc <= '0; - else if (cnt[30:2]==1) array_dsc <= '0; - else if (cnt[30:2]==2) array_dsc <= '0; - else if (cnt[30:2]==3) array_dsc <= '0; - else if (cnt[30:2]==4) array_dsc <= '0; - else if (cnt[30:2]==5) array_dsc <= '0; - else if (cnt[30:2]==6) array_dsc <= '0; - else if (cnt[30:2]==7) array_dsc <= '0; - else if (cnt[30:2]==8) array_dsc <= '0; - else if (cnt[30:2]==9) array_dsc <= '0; - end else if (cnt[1:0]==2'd1) begin - // write value to array - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_dsc <= {WA *WB +0{1'b1}}; - else if (cnt[30:2]==2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; - else if (cnt[30:2]==9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; - end else if (cnt[1:0]==2'd2) begin - // check array value - if (cnt[30:2]==0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]==9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end - end else if (cnt[1:0]==2'd3) begin - // read value from array (not a very good test for now) - if (cnt[30:2]==0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end - else if (cnt[30:2]==9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end - end + // descending range + // verilog_format: off + always @ (posedge clk) + if (cnt[1:0] == 2'd0) begin + // initialize to defaaults (all bits to 0) + if (cnt[30:2] == 0) array_dsc <= '0; + else if (cnt[30:2] == 1) array_dsc <= '0; + else if (cnt[30:2] == 2) array_dsc <= '0; + else if (cnt[30:2] == 3) array_dsc <= '0; + else if (cnt[30:2] == 4) array_dsc <= '0; + else if (cnt[30:2] == 5) array_dsc <= '0; + else if (cnt[30:2] == 6) array_dsc <= '0; + else if (cnt[30:2] == 7) array_dsc <= '0; + else if (cnt[30:2] == 8) array_dsc <= '0; + else if (cnt[30:2] == 9) array_dsc <= '0; + end else if (cnt[1:0] == 2'd1) begin + // write value to array + if (cnt[30:2] == 0) begin end + else if (cnt[30:2] == 1) array_dsc <= {WA *WB +0{1'b1}}; + else if (cnt[30:2] == 2) array_dsc [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2] == 3) array_dsc [WA -1:WA/2] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2] == 4) array_dsc [ 0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2] == 5) array_dsc [WA -1 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2] == 6) array_dsc [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2] == 7) array_dsc [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2] == 8) array_dsc [ 0 ][ 0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2] == 9) array_dsc [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}}; + end else if (cnt[1:0] == 2'd2) begin + // check array value + if (cnt[30:2] == 0) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 1) begin if (array_dsc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 2) begin if (array_dsc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 3) begin if (array_dsc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 4) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 5) begin if (array_dsc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 6) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 7) begin if (array_dsc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 8) begin if (array_dsc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2] == 9) begin if (array_dsc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_dsc); $stop(); end end + end else if (cnt[1:0] == 2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2] == 0) begin if (array_dsc !== {WA *WB {1'b0}}) $stop(); end + else if (cnt[30:2] == 1) begin if (array_dsc !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 2) begin if (array_dsc [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 3) begin if (array_dsc [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 4) begin if (array_dsc [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 5) begin if (array_dsc [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 6) begin if (array_dsc [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2] == 7) begin if (array_dsc [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2] == 8) begin if (array_dsc [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 9) begin if (array_dsc [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end + end - // ascending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaaults (all bits to 0) - if (cnt[30:2]==0) array_asc <= '0; - else if (cnt[30:2]==1) array_asc <= '0; - else if (cnt[30:2]==2) array_asc <= '0; - else if (cnt[30:2]==3) array_asc <= '0; - else if (cnt[30:2]==4) array_asc <= '0; - else if (cnt[30:2]==5) array_asc <= '0; - else if (cnt[30:2]==6) array_asc <= '0; - else if (cnt[30:2]==7) array_asc <= '0; - else if (cnt[30:2]==8) array_asc <= '0; - else if (cnt[30:2]==9) array_asc <= '0; - end else if (cnt[1:0]==2'd1) begin - // write value to array - if (cnt[30:2]==0) begin end - else if (cnt[30:2]==1) array_asc <= {WA *WB +0{1'b1}}; - else if (cnt[30:2]==2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; - else if (cnt[30:2]==4) array_asc [0 ] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==5) array_asc [ WA -1] <= {1 *WB +0{1'b1}}; - else if (cnt[30:2]==6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; - else if (cnt[30:2]==8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}}; - else if (cnt[30:2]==9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; - end else if (cnt[1:0]==2'd2) begin - // check array value - if (cnt[30:2]==0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end - end else if (cnt[1:0]==2'd3) begin - // read value from array (not a very good test for now) - if (cnt[30:2]==0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end - else if (cnt[30:2]==1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end - else if (cnt[30:2]==6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end - else if (cnt[30:2]==8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end - else if (cnt[30:2]==9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end - end + // ascending range + always @ (posedge clk) + if (cnt[1:0] == 2'd0) begin + // initialize to defaaults (all bits to 0) + if (cnt[30:2] == 0) array_asc <= '0; + else if (cnt[30:2] == 1) array_asc <= '0; + else if (cnt[30:2] == 2) array_asc <= '0; + else if (cnt[30:2] == 3) array_asc <= '0; + else if (cnt[30:2] == 4) array_asc <= '0; + else if (cnt[30:2] == 5) array_asc <= '0; + else if (cnt[30:2] == 6) array_asc <= '0; + else if (cnt[30:2] == 7) array_asc <= '0; + else if (cnt[30:2] == 8) array_asc <= '0; + else if (cnt[30:2] == 9) array_asc <= '0; + end else if (cnt[1:0] == 2'd1) begin + // write value to array + if (cnt[30:2] == 0) begin end + else if (cnt[30:2] == 1) array_asc <= {WA *WB +0{1'b1}}; + else if (cnt[30:2] == 2) array_asc [0 :WA/2-1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2] == 3) array_asc [WA/2:WA -1] <= {WA/2*WB +0{1'b1}}; + else if (cnt[30:2] == 4) array_asc [0 ] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2] == 5) array_asc [ WA -1] <= {1 *WB +0{1'b1}}; + else if (cnt[30:2] == 6) array_asc [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2] == 7) array_asc [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}}; + else if (cnt[30:2] == 8) array_asc [0 ][0 ] <= {1 *1 +0{1'b1}}; + else if (cnt[30:2] == 9) array_asc [ WA -1][ WB -1] <= {1 *1 +0{1'b1}}; + end else if (cnt[1:0] == 2'd2) begin + // check array value + if (cnt[30:2] == 0) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 1) begin if (array_asc !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 2) begin if (array_asc !== 64'b1111111111111111111111111111111100000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 3) begin if (array_asc !== 64'b0000000000000000000000000000000011111111111111111111111111111111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 4) begin if (array_asc !== 64'b1111111100000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 5) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000011111111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 6) begin if (array_asc !== 64'b1111000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 7) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000001111) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 8) begin if (array_asc !== 64'b1000000000000000000000000000000000000000000000000000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2] == 9) begin if (array_asc !== 64'b0000000000000000000000000000000000000000000000000000000000000001) begin $display("%b", array_asc); $stop(); end end + end else if (cnt[1:0] == 2'd3) begin + // read value from array (not a very good test for now) + if (cnt[30:2] == 0) begin if (array_asc !== {WA *WB {1'b0}}) $stop(); end + else if (cnt[30:2] == 1) begin if (array_asc !== {WA *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 2) begin if (array_asc [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 3) begin if (array_asc [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 4) begin if (array_asc [0 ] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 5) begin if (array_asc [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 6) begin if (array_asc [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2] == 7) begin if (array_asc [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end + else if (cnt[30:2] == 8) begin if (array_asc [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end + else if (cnt[30:2] == 9) begin if (array_asc [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end + end endmodule diff --git a/test_regress/t/t_array_pattern_2d.v b/test_regress/t/t_array_pattern_2d.v index 8df3b6fed..4e3934107 100644 --- a/test_regress/t/t_array_pattern_2d.v +++ b/test_regress/t/t_array_pattern_2d.v @@ -7,41 +7,41 @@ //bug991 module t; - logic [31:0] array_assign [3:0]; - logic [31:0] array_other [3:0]; + logic [31:0] array_assign[3:0]; + logic [31:0] array_other[3:0]; - logic [31:0] larray_assign [0:3]; - logic [31:0] larray_other [0:3]; + logic [31:0] larray_assign[0:3]; + logic [31:0] larray_other[0:3]; - logic [31:0] array_neg [-1:1]; + logic [31:0] array_neg[-1:1]; - initial begin - array_assign[0] = 32'd1; - array_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + initial begin + array_assign[0] = 32'd1; + array_assign[3:1] = '{32'd4, 32'd3, 32'd2}; - array_other[0] = array_assign[0]+10; - array_other[3:1] = array_assign[3:1]; - if (array_other[0] != 11) $stop; - if (array_other[1] != 2) $stop; - if (array_other[2] != 3) $stop; - if (array_other[3] != 4) $stop; + array_other[0] = array_assign[0] + 10; + array_other[3:1] = array_assign[3:1]; + if (array_other[0] != 11) $stop; + if (array_other[1] != 2) $stop; + if (array_other[2] != 3) $stop; + if (array_other[3] != 4) $stop; - larray_assign[0] = 32'd1; - larray_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + larray_assign[0] = 32'd1; + larray_assign[1:3] = '{32'd4, 32'd3, 32'd2}; - larray_other[0] = larray_assign[0]+10; - larray_other[1:3] = larray_assign[1:3]; - if (larray_other[0] != 11) $stop; - if (larray_other[1] != 4) $stop; - if (larray_other[2] != 3) $stop; - if (larray_other[3] != 2) $stop; + larray_other[0] = larray_assign[0] + 10; + larray_other[1:3] = larray_assign[1:3]; + if (larray_other[0] != 11) $stop; + if (larray_other[1] != 4) $stop; + if (larray_other[2] != 3) $stop; + if (larray_other[3] != 2) $stop; - array_neg = '{-1: 5, 1: 7, default: 'd6}; - if (array_neg[-1] != 5) $stop; - if (array_neg[0] != 6) $stop; - if (array_neg[1] != 7) $stop; + array_neg = '{-1: 5, 1: 7, default: 'd6}; + if (array_neg[-1] != 5) $stop; + if (array_neg[0] != 6) $stop; + if (array_neg[1] != 7) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_pattern_bad.out b/test_regress/t/t_array_pattern_bad.out index c93c13306..f27c98d53 100644 --- a/test_regress/t/t_array_pattern_bad.out +++ b/test_regress/t/t_array_pattern_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_array_pattern_bad.v:24:18: Assignment pattern key 'valids' not found as member +%Error: t/t_array_pattern_bad.v:21:39: Assignment pattern key 'valids' not found as member : ... note: In instance 't' - 24 | valids: '1}; - | ^~~~~~ + 21 | always_comb myinfo = '{default: '0, valids: '1}; + | ^~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_array_pattern_bad.v b/test_regress/t/t_array_pattern_bad.v index c35f191b1..f6ac3b989 100644 --- a/test_regress/t/t_array_pattern_bad.v +++ b/test_regress/t/t_array_pattern_bad.v @@ -6,21 +6,18 @@ // bug1364 -module t (/*AUTOARG*/ - // Inputs - clk, res - ); - input clk; - input res; +module t ( /*AUTOARG*/ + // Inputs + clk, + res +); + input clk; + input res; - typedef struct packed { - logic [3:0] port_num; - } info_t; + typedef struct packed {logic [3:0] port_num;} info_t; - info_t myinfo; + info_t myinfo; - always_comb - myinfo = '{default: '0, - valids: '1}; + always_comb myinfo = '{default: '0, valids: '1}; endmodule diff --git a/test_regress/t/t_array_pattern_bad2.out b/test_regress/t/t_array_pattern_bad2.out index 5b81d55ec..f94cbf81a 100644 --- a/test_regress/t/t_array_pattern_bad2.out +++ b/test_regress/t/t_array_pattern_bad2.out @@ -1,6 +1,6 @@ -%Error: t/t_array_pattern_bad2.v:22:16: Multiple '{ default: } clauses +%Error: t/t_array_pattern_bad2.v:20:24: Multiple '{ default: } clauses : ... note: In instance 't' - 22 | myinfo = '{default: '0, - | ^~ + 20 | always_comb myinfo = '{default: '0, default: '1}; + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_array_pattern_bad2.v b/test_regress/t/t_array_pattern_bad2.v index 4aa91b236..6ed67309e 100644 --- a/test_regress/t/t_array_pattern_bad2.v +++ b/test_regress/t/t_array_pattern_bad2.v @@ -6,20 +6,17 @@ // bug1364 -module t (/*AUTOARG*/ - // Inputs - clk, res - ); - input clk; - input res; +module t ( /*AUTOARG*/ + // Inputs + clk, + res +); + input clk; + input res; - typedef struct packed { - logic [3:0] port_num; - } info_t; + typedef struct packed {logic [3:0] port_num;} info_t; - info_t myinfo; - always_comb - myinfo = '{default: '0, - default: '1}; // Bad + info_t myinfo; + always_comb myinfo = '{default: '0, default: '1}; // Bad endmodule diff --git a/test_regress/t/t_array_pattern_bad3.out b/test_regress/t/t_array_pattern_bad3.out index 05fbe3d6a..2faded42e 100644 --- a/test_regress/t/t_array_pattern_bad3.out +++ b/test_regress/t/t_array_pattern_bad3.out @@ -1,14 +1,14 @@ -%Error: t/t_array_pattern_bad3.v:20:15: Assignment pattern key used multiple times: 1 - : ... note: In instance 't' - 20 | 1: '1}; - | ^ +%Error: t/t_array_pattern_bad3.v:19:9: Assignment pattern key used multiple times: 1 + : ... note: In instance 't' + 19 | 1: '1 + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_array_pattern_bad3.v:21:13: Assignment pattern with too many elements +%Error: t/t_array_pattern_bad3.v:21:11: Assignment pattern with too many elements : ... note: In instance 't' - 21 | arr = '{'0, '1, '0, '1}; - | ^~ -%Error: t/t_array_pattern_bad3.v:22:13: Assignment pattern missed initializing elements: 2 + 21 | arr = '{'0, '1, '0, '1}; + | ^~ +%Error: t/t_array_pattern_bad3.v:22:11: Assignment pattern missed initializing elements: 2 : ... note: In instance 't' - 22 | arr = '{'0, '1}; - | ^~ + 22 | arr = '{'0, '1}; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_array_pattern_bad3.v b/test_regress/t/t_array_pattern_bad3.v index 2e487c1e8..b8004a8d8 100644 --- a/test_regress/t/t_array_pattern_bad3.v +++ b/test_regress/t/t_array_pattern_bad3.v @@ -6,20 +6,20 @@ // bug1364 -module t (/*AUTOARG*/ - // Inputs - clk, res - ); - input clk; - input res; +module t ( + input clk, + input res +); - int arr[3]; - initial begin - arr = '{default: '0, - 1: '0, - 1: '1}; // Bad - arr = '{'0, '1, '0, '1}; // Bad, too many - arr = '{'0, '1}; // Bad, too few - end + int arr[3]; + initial begin + arr = '{ + default: '0, // + 1: '0, // + 1: '1 + }; // Bad + arr = '{'0, '1, '0, '1}; // Bad, too many + arr = '{'0, '1}; // Bad, too few + end endmodule diff --git a/test_regress/t/t_array_pattern_enum.v b/test_regress/t/t_array_pattern_enum.v index eeae8c36e..e09b9b686 100644 --- a/test_regress/t/t_array_pattern_enum.v +++ b/test_regress/t/t_array_pattern_enum.v @@ -5,28 +5,24 @@ // SPDX-License-Identifier: CC0-1.0 package Pkg; - typedef enum { - RED=0, - GREEN=1, - BLUE=2 - } color_t; + typedef enum { + RED = 0, + GREEN = 1, + BLUE = 2 + } color_t; - typedef struct { - color_t pixels[32]; - } line_t; + typedef struct {color_t pixels[32];} line_t; - typedef struct { - line_t line[32]; - } screen_t; + typedef struct {line_t line[32];} screen_t; endpackage module t; - Pkg::screen_t screen; + Pkg::screen_t screen; - initial begin - screen = '{ default: '0, Pkg::color_t: Pkg::RED}; - $display("%p", screen); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + screen = '{default: '0, Pkg::color_t: Pkg::RED}; + $display("%p", screen); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_pattern_packed.v b/test_regress/t/t_array_pattern_packed.v index 45afbad31..cb5903594 100644 --- a/test_regress/t/t_array_pattern_packed.v +++ b/test_regress/t/t_array_pattern_packed.v @@ -4,150 +4,148 @@ // SPDX-FileCopyrightText: 2009 Iztok Jeras // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + logic [1:0][3:0][3:0] array_simp; // descending range array - logic [1:0] [3:0] [3:0] array_simp; // descending range array + logic [3:0] array_oned; - logic [3:0] array_oned; + // verilog_format: off + initial begin + array_oned = '{2:1'b1, 0:1'b1, default:1'b0}; + if (array_oned != 4'b0101) $stop; - initial begin - array_oned = '{2:1'b1, 0:1'b1, default:1'b0}; - if (array_oned != 4'b0101) $stop; + array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; + if (array_simp[0] !== 16'h3210) $stop; - array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; - if (array_simp[0] !== 16'h3210) $stop; + // verilator lint_off WIDTH + array_simp[0] = '{ 3 ,2 ,1, 0 }; + // verilator lint_on WIDTH + if (array_simp[0] !== 16'h3210) $stop; - // verilator lint_off WIDTH - array_simp[0] = '{ 3 ,2 ,1, 0 }; - // verilator lint_on WIDTH - if (array_simp[0] !== 16'h3210) $stop; + // Doesn't seem to work for unpacked arrays in other simulators + //if (array_simp[0] !== 16'h3210) $stop; + //array_simp[0] = '{ 1:4'd3, default:13}; + //if (array_simp[0] !== 16'hDD3D) $stop; - // Doesn't seem to work for unpacked arrays in other simulators - //if (array_simp[0] !== 16'h3210) $stop; - //array_simp[0] = '{ 1:4'd3, default:13}; - //if (array_simp[0] !== 16'hDD3D) $stop; + array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; + if (array_simp !== 32'h3210_1234) $stop; - array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; - if (array_simp !== 32'h3210_1234) $stop; + // IEEE says '{} allowed only on assignments, not !=, ==. - // IEEE says '{} allowed only on assignments, not !=, ==. + // Doesn't seem to work for unpacked arrays in other simulators + array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; + if (array_simp !== 32'h3210_3210) $stop; - // Doesn't seem to work for unpacked arrays in other simulators - array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; - if (array_simp !== 32'h3210_3210) $stop; + array_simp = '{2{ '{4{ 4'd3 }} }}; + if (array_simp !== 32'h3333_3333) $stop; - array_simp = '{2{ '{4{ 4'd3 }} }}; - if (array_simp !== 32'h3333_3333) $stop; + // Not legal in other simulators - replication doesn't match + // However IEEE suggests this is legal. + //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} - // Not legal in other simulators - replication doesn't match - // However IEEE suggests this is legal. - //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} + $write("*-* All Finished *-*\n"); + $finish; + end - $write("*-* All Finished *-*\n"); - $finish; - end + //==================== - //==================== + // parameters for array sizes + localparam WA = 4; // address dimension size + localparam WB = 4; // bit dimension size - // parameters for array sizes - localparam WA = 4; // address dimension size - localparam WB = 4; // bit dimension size + localparam NO = 11; // number of access events - localparam NO = 11; // number of access events + // 2D packed arrays + logic [WA-1:0] [WB-1:0] array_dsc; // descending range array + /* verilator lint_off ASCRANGE */ + logic [0:WA-1] [0:WB-1] array_asc; // ascending range array + /* verilator lint_on ASCRANGE */ - // 2D packed arrays - logic [WA-1:0] [WB-1:0] array_dsc; // descending range array - /* verilator lint_off ASCRANGE */ - logic [0:WA-1] [0:WB-1] array_asc; // ascending range array - /* verilator lint_on ASCRANGE */ + integer cnt = 0; - integer cnt = 0; + // event counter + always @ (posedge clk) begin + cnt <= cnt + 1; + end - // event counter - always @ (posedge clk) begin - cnt <= cnt + 1; - end + // finish report + always @ (posedge clk) + if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin + $write("*-* All Finished *-*\n"); + $finish; + end - // finish report - always @ (posedge clk) - if ((cnt[30:2]==(NO-1)) && (cnt[1:0]==2'd3)) begin - $write("*-* All Finished *-*\n"); - $finish; - end + // descending range + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'b0) + if (cnt[30:2]== 0) array_dsc <= '0; + else if (cnt[30:2]== 1) array_dsc <= '0; + else if (cnt[30:2]== 2) array_dsc <= '0; + else if (cnt[30:2]== 3) array_dsc <= '0; + else if (cnt[30:2]== 4) array_dsc <= '0; + else if (cnt[30:2]== 5) array_dsc <= '0; + else if (cnt[30:2]== 6) array_dsc <= '0; + else if (cnt[30:2]== 7) array_dsc <= '0; + else if (cnt[30:2]== 8) array_dsc <= '0; + else if (cnt[30:2]== 9) array_dsc <= '0; + else if (cnt[30:2]==10) array_dsc <= '0; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]== 0) begin end + else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_dsc <= '{default:13}; + else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7}; + else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13}; + else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end + else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end + end - // descending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaults (all bits 1'b0) - if (cnt[30:2]== 0) array_dsc <= '0; - else if (cnt[30:2]== 1) array_dsc <= '0; - else if (cnt[30:2]== 2) array_dsc <= '0; - else if (cnt[30:2]== 3) array_dsc <= '0; - else if (cnt[30:2]== 4) array_dsc <= '0; - else if (cnt[30:2]== 5) array_dsc <= '0; - else if (cnt[30:2]== 6) array_dsc <= '0; - else if (cnt[30:2]== 7) array_dsc <= '0; - else if (cnt[30:2]== 8) array_dsc <= '0; - else if (cnt[30:2]== 9) array_dsc <= '0; - else if (cnt[30:2]==10) array_dsc <= '0; - end else if (cnt[1:0]==2'd1) begin - // write data into whole or part of the array using literals - if (cnt[30:2]== 0) begin end - else if (cnt[30:2]== 1) array_dsc <= '{ 3 ,2 ,1, 0 }; - else if (cnt[30:2]== 2) array_dsc <= '{default:13}; - else if (cnt[30:2]== 3) array_dsc <= '{0:4, 1:5, 2:6, 3:7}; - else if (cnt[30:2]== 4) array_dsc <= '{2:15, default:13}; - else if (cnt[30:2]== 5) array_dsc <= '{WA { {WB/2 {2'b10}} }}; - else if (cnt[30:2]== 6) array_dsc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; - end else if (cnt[1:0]==2'd2) begin - // chack array agains expected value - if (cnt[30:2]== 0) begin if (array_dsc !== 16'b0000000000000000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 1) begin if (array_dsc !== 16'b0011001000010000) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 2) begin if (array_dsc !== 16'b1101110111011101) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 3) begin if (array_dsc !== 16'b0111011001010100) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 4) begin if (array_dsc !== 16'b1101111111011101) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 5) begin if (array_dsc !== 16'b1010101010101010) begin $display("%b", array_dsc); $stop(); end end - else if (cnt[30:2]== 6) begin if (array_dsc !== 16'b1001101010111100) begin $display("%b", array_dsc); $stop(); end end - end - - // ascending range - always @ (posedge clk) - if (cnt[1:0]==2'd0) begin - // initialize to defaults (all bits 1'b0) - if (cnt[30:2]== 0) array_asc <= '0; - else if (cnt[30:2]== 1) array_asc <= '0; - else if (cnt[30:2]== 2) array_asc <= '0; - else if (cnt[30:2]== 3) array_asc <= '0; - else if (cnt[30:2]== 4) array_asc <= '0; - else if (cnt[30:2]== 5) array_asc <= '0; - else if (cnt[30:2]== 6) array_asc <= '0; - else if (cnt[30:2]== 7) array_asc <= '0; - else if (cnt[30:2]== 8) array_asc <= '0; - else if (cnt[30:2]== 9) array_asc <= '0; - else if (cnt[30:2]==10) array_asc <= '0; - end else if (cnt[1:0]==2'd1) begin - // write data into whole or part of the array using literals - if (cnt[30:2]== 0) begin end - else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 }; - else if (cnt[30:2]== 2) array_asc <= '{default:13}; - else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7}; - else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13}; - else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }}; - else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; - end else if (cnt[1:0]==2'd2) begin - // chack array agains expected value - if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end - else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end - end + // ascending range + always @ (posedge clk) + if (cnt[1:0]==2'd0) begin + // initialize to defaults (all bits 1'b0) + if (cnt[30:2]== 0) array_asc <= '0; + else if (cnt[30:2]== 1) array_asc <= '0; + else if (cnt[30:2]== 2) array_asc <= '0; + else if (cnt[30:2]== 3) array_asc <= '0; + else if (cnt[30:2]== 4) array_asc <= '0; + else if (cnt[30:2]== 5) array_asc <= '0; + else if (cnt[30:2]== 6) array_asc <= '0; + else if (cnt[30:2]== 7) array_asc <= '0; + else if (cnt[30:2]== 8) array_asc <= '0; + else if (cnt[30:2]== 9) array_asc <= '0; + else if (cnt[30:2]==10) array_asc <= '0; + end else if (cnt[1:0]==2'd1) begin + // write data into whole or part of the array using literals + if (cnt[30:2]== 0) begin end + else if (cnt[30:2]== 1) array_asc <= '{ 3 ,2 ,1, 0 }; + else if (cnt[30:2]== 2) array_asc <= '{default:13}; + else if (cnt[30:2]== 3) array_asc <= '{3:4, 2:5, 1:6, 0:7}; + else if (cnt[30:2]== 4) array_asc <= '{1:15, default:13}; + else if (cnt[30:2]== 5) array_asc <= '{WA { {WB/2 {2'b10}} }}; + else if (cnt[30:2]==10) array_asc <= '{cnt[3:0]+0, cnt[3:0]+1, cnt[3:0]+2, cnt[3:0]+3}; + end else if (cnt[1:0]==2'd2) begin + // chack array agains expected value + if (cnt[30:2]== 0) begin if (array_asc !== 16'b0000000000000000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 1) begin if (array_asc !== 16'b0011001000010000) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 2) begin if (array_asc !== 16'b1101110111011101) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 3) begin if (array_asc !== 16'b0111011001010100) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 4) begin if (array_asc !== 16'b1101111111011101) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]== 5) begin if (array_asc !== 16'b1010101010101010) begin $display("%b", array_asc); $stop(); end end + else if (cnt[30:2]==10) begin if (array_asc !== 16'b1001101010111100) begin $display("%b", array_asc); $stop(); end end + end endmodule diff --git a/test_regress/t/t_array_pattern_unpacked.v b/test_regress/t/t_array_pattern_unpacked.v index 601d85db2..0e1c8f1b6 100644 --- a/test_regress/t/t_array_pattern_unpacked.v +++ b/test_regress/t/t_array_pattern_unpacked.v @@ -6,58 +6,58 @@ module t; - logic [3:0] array_simp [1:0] [3:0]; // descending range array - wire [2:0] array_wire [1:0] = '{3'd1, 3'd2}; + logic [3:0] array_simp [1:0] [3:0]; // descending range array + wire [2:0] array_wire [1:0] = '{3'd1, 3'd2}; - int irep[1:2][1:6]; + int irep[1:2][1:6]; - initial begin - if (array_wire[0] !== 3'd2) $stop; - if (array_wire[1] !== 3'd1) $stop; + initial begin + if (array_wire[0] !== 3'd2) $stop; + if (array_wire[1] !== 3'd1) $stop; - array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; - if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 16'h3210) $stop; + array_simp[0] = '{ 4'd3, 4'd2, 4'd1, 4'd0}; + if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 16'h3210) $stop; - // verilator lint_off WIDTH - array_simp[0] = '{ 3 ,2 ,1, 0 }; - // verilator lint_on WIDTH - if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 16'h3210) $stop; + // verilator lint_off WIDTH + array_simp[0] = '{ 3 ,2 ,1, 0 }; + // verilator lint_on WIDTH + if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 16'h3210) $stop; - // Doesn't seem to work for unpacked arrays in other simulators - //array_simp[0] = '{ 1:4'd3, default:13 }; - //if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop; + // Doesn't seem to work for unpacked arrays in other simulators + //array_simp[0] = '{ 1:4'd3, default:13 }; + //if ({array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} !== 16'hDD3D) $stop; - array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; - if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], - array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 32'h3210_1234) $stop; + array_simp = '{ '{ 4'd3, 4'd2, 4'd1, 4'd0 }, '{ 4'd1, 4'd2, 4'd3, 4'd4 }}; + if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], + array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 32'h3210_1234) $stop; - // Doesn't seem to work for unpacked arrays in other simulators - array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; - if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], - array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 32'h3210_3210) $stop; + // Doesn't seem to work for unpacked arrays in other simulators + array_simp = '{2{ '{4'd3, 4'd2, 4'd1, 4'd0 } }}; + if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], + array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 32'h3210_3210) $stop; - array_simp = '{2{ '{4{ 4'd3 }} }}; - if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], - array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} - !== 32'h3333_3333) $stop; + array_simp = '{2{ '{4{ 4'd3 }} }}; + if ({array_simp[1][3],array_simp[1][2],array_simp[1][1],array_simp[1][0], + array_simp[0][3],array_simp[0][2],array_simp[0][1],array_simp[0][0]} + !== 32'h3333_3333) $stop; - // Not legal in other simulators - replication doesn't match - // However IEEE suggests this is legal. - //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} + // Not legal in other simulators - replication doesn't match + // However IEEE suggests this is legal. + //array_simp = '{2{ '{2{ 4'd3, 4'd2 }} }}; // Note it's not '{3,2} - // Replication - irep = '{2{ '{3 {4, 5}}}}; - if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]} - != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; - if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]} - != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; + // Replication + irep = '{2{ '{3 {4, 5}}}}; + if ({irep[1][1], irep[1][2], irep[1][3], irep[1][4], irep[1][5], irep[1][6]} + != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; + if ({irep[2][1], irep[2][2], irep[2][3], irep[2][4], irep[2][5], irep[2][6]} + != {32'h4, 32'h5, 32'h4, 32'h5, 32'h4, 32'h5}) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_query.v b/test_regress/t/t_array_query.v index 0585a59ff..db0873bec 100644 --- a/test_regress/t/t_array_query.v +++ b/test_regress/t/t_array_query.v @@ -7,60 +7,56 @@ // SPDX-FileCopyrightText: 2012 Jeremy Bennett, Embecosm // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - wire a = clk; - wire b = 1'b0; - reg c; + wire a = clk; + wire b = 1'b0; + reg c; - array_test array_test_i (/*AUTOINST*/ - // Inputs - .clk (clk)); + array_test array_test_i ( /*AUTOINST*/ + // Inputs + .clk(clk) + ); endmodule // Check the array sizing functions work correctly. -module array_test +module array_test #( + parameter LEFT = 5, + RIGHT = 55 +) ( /*AUTOARG*/ + // Inputs + clk +); - #( parameter - LEFT = 5, - RIGHT = 55) + input clk; - (/*AUTOARG*/ - // Inputs - clk - ); + // verilator lint_off ASCRANGE + reg [7:0] a[LEFT:RIGHT]; + // verilator lint_on ASCRANGE - input clk; + typedef reg [7:0] r_t; - // verilator lint_off ASCRANGE - reg [7:0] a [LEFT:RIGHT]; - // verilator lint_on ASCRANGE + integer l; + integer r; + integer s; - typedef reg [7:0] r_t; - - integer l; - integer r; - integer s; - - always @(posedge clk) begin - l = $left (a); - r = $right (a); - s = $size (a); + always @(posedge clk) begin + l = $left(a); + r = $right(a); + s = $size(a); `ifdef TEST_VERBOSE - $write ("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s); + $write("$left (a) = %d, $right (a) = %d, $size (a) = %d\n", l, r, s); `endif - if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop; - if ($left(r_t)!=7 || $right(r_t)!=0 || $size(r_t)!=8 || $bits(r_t) !=8) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if ((l != LEFT) || (r != RIGHT) || (s != (RIGHT - LEFT + 1))) $stop; + if ($left(r_t) != 7 || $right(r_t) != 0 || $size(r_t) != 8 || $bits(r_t) != 8) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_query_with.v b/test_regress/t/t_array_query_with.v index eec4685b0..1e5c4bc9f 100644 --- a/test_regress/t/t_array_query_with.v +++ b/test_regress/t/t_array_query_with.v @@ -5,70 +5,70 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - static function bit get_true(); - return 1'b1; - endfunction + static function bit get_true(); + return 1'b1; + endfunction - static function bit test_find_index_in_class(); - if (get_true) begin - int q[$] = {0, -1, 3, 1, 4, 1}; - int found_idx[$]; - found_idx = q.find_index(node) with (node == 1); - return found_idx[0] == 3; - end - return 0; - endfunction + static function bit test_find_index_in_class(); + if (get_true) begin + int q[$] = {0, -1, 3, 1, 4, 1}; + int found_idx[$]; + found_idx = q.find_index(node) with (node == 1); + return found_idx[0] == 3; + end + return 0; + endfunction endclass -module t (/*AUTOARG*/ - ); +module t ( /*AUTOARG*/ +); - function bit test_find; - string bar[$]; - string found[$]; - bar.push_back("baz"); - bar.push_back("qux"); - found = bar.find(x) with (x == "baz"); - return found.size() == 1; - endfunction + function bit test_find; + string bar[$]; + string found[$]; + bar.push_back("baz"); + bar.push_back("qux"); + found = bar.find(x) with (x == "baz"); + return found.size() == 1; + endfunction - function static bit test_find_index; - int q[$] = {1, 2, 3, 4}; - int found[$] = q.find_index(x) with (x <= 2); - return found.size() == 2; - endfunction + function static bit test_find_index; + int q[$] = {1, 2, 3, 4}; + int found[$] = q.find_index(x) with (x <= 2); + return found.size() == 2; + endfunction - function static bit test_find_first_index; - int q[] = {1, 2, 3, 4, 5, 6}; - int first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0); - return first_even_idx[0] == 1; - endfunction + function static bit test_find_first_index; + int q[] = {1, 2, 3, 4, 5, 6}; + int first_even_idx[$] = q.find_first_index(x) with (x % 2 == 0); + return first_even_idx[0] == 1; + endfunction - function bit is_even(int a); - return a % 2 == 0; - endfunction + function bit is_even(int a); + return a % 2 == 0; + endfunction - function static bit test_find_first_index_by_func; - int q[] = {1, 2, 3, 4, 5, 6}; - int first_even_idx[$] = q.find_first_index(x) with (is_even(x)); - return first_even_idx[0] == 1; - endfunction + function static bit test_find_first_index_by_func; + int q[] = {1, 2, 3, 4, 5, 6}; + int first_even_idx[$] = q.find_first_index(x) with (is_even(x)); + return first_even_idx[0] == 1; + endfunction - function automatic bit test_sort; - int q[] = {-5, 2, -3, 0, 4}; - q.sort(x) with (x >= 0 ? x : -x); - return q[1] == 2; - endfunction + function automatic bit test_sort; + int q[] = {-5, 2, -3, 0, 4}; + q.sort(x) with (x >= 0 ? x : -x); + return q[1] == 2; + endfunction - initial begin - if (!test_find()) $stop; - if (!test_find_index()) $stop; - if (!test_find_first_index()) $stop; - if (!test_find_first_index_by_func()) $stop; - if (!test_sort()) $stop; - if (!Cls::test_find_index_in_class()) $stop; + initial begin + if (!test_find()) $stop; + if (!test_find_index()) $stop; + if (!test_find_first_index()) $stop; + if (!test_find_first_index_by_func()) $stop; + if (!test_sort()) $stop; + if (!Cls::test_find_index_in_class()) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_rev.v b/test_regress/t/t_array_rev.v index c8c63c58f..f77fba0c6 100644 --- a/test_regress/t/t_array_rev.v +++ b/test_regress/t/t_array_rev.v @@ -4,58 +4,54 @@ // SPDX-FileCopyrightText: 2016 Geoff Barrett // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc = 0; + // verilator lint_off ASCRANGE + logic arrd[0:1] = '{1'b1, 1'b0}; + // verilator lint_on ASCRANGE + logic y0, y1; + logic localbkw[1:0]; - integer cyc = 0; - // verilator lint_off ASCRANGE - logic arrd [0:1] = '{ 1'b1, 1'b0 }; - // verilator lint_on ASCRANGE - logic y0, y1; - logic localbkw [1:0]; + arr_rev arr_rev_u ( + .arrbkw(arrd), + .y0(y0), + .y1(y1) + ); - arr_rev arr_rev_u ( - .arrbkw (arrd), - .y0(y0), - .y1(y1) - ); + always @(posedge clk) begin + if (arrd[0] != 1'b1) $stop; + if (arrd[1] != 1'b0) $stop; - always @ (posedge clk) begin - if (arrd[0] != 1'b1) $stop; - if (arrd[1] != 1'b0) $stop; - - localbkw = arrd; + localbkw = arrd; `ifdef TEST_VERBOSE - $write("localbkw[0]=%b\n", localbkw[0]); - $write("localbkw[1]=%b\n", localbkw[1]); + $write("localbkw[0]=%b\n", localbkw[0]); + $write("localbkw[1]=%b\n", localbkw[1]); `endif - if (localbkw[0] != 1'b0) $stop; - if (localbkw[1] != 1'b1) $stop; + if (localbkw[0] != 1'b0) $stop; + if (localbkw[1] != 1'b1) $stop; `ifdef TEST_VERBOSE - $write("y0=%b\n", y0); - $write("y1=%b\n", y1); + $write("y0=%b\n", y0); + $write("y1=%b\n", y1); `endif - if (y0 != 1'b0) $stop; - if (y1 != 1'b1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + if (y0 != 1'b0) $stop; + if (y1 != 1'b1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module arr_rev - ( - input var logic arrbkw [1:0], - output var logic y0, - output var logic y1 - ); +module arr_rev ( + input var logic arrbkw[1:0], + output var logic y0, + output var logic y1 +); - always_comb y0 = arrbkw[0]; - always_comb y1 = arrbkw[1]; + always_comb y0 = arrbkw[0]; + always_comb y1 = arrbkw[1]; endmodule diff --git a/test_regress/t/t_array_sel_wide.v b/test_regress/t/t_array_sel_wide.v index 24601b694..5964e0109 100644 --- a/test_regress/t/t_array_sel_wide.v +++ b/test_regress/t/t_array_sel_wide.v @@ -5,26 +5,26 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Outputs - nnext, - // Inputs - inibble, onibble - ); + // Outputs + nnext, + // Inputs + inibble, onibble + ); - input [3:0] inibble; - input [106:0] onibble; + input [3:0] inibble; + input [106:0] onibble; - output reg [3:0] nnext [0:7]; + output reg [3:0] nnext [0:7]; - // verilator lint_off WIDTH - wire [2:0] selline = (onibble >>> 102) & 7; - // verilator lint_on WIDTH + // verilator lint_off WIDTH + wire [2:0] selline = (onibble >>> 102) & 7; + // verilator lint_on WIDTH - always_comb begin - for (integer i=0; i<8; i=i+1) begin - nnext[i] = '0; - end - nnext[selline] = inibble; - end + always_comb begin + for (integer i=0; i<8; i=i+1) begin + nnext[i] = '0; + end + nnext[selline] = inibble; + end endmodule diff --git a/test_regress/t/t_array_type_methods.v b/test_regress/t/t_array_type_methods.v index 7b3c71110..ad2c7d2c2 100644 --- a/test_regress/t/t_array_type_methods.v +++ b/test_regress/t/t_array_type_methods.v @@ -4,30 +4,32 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - logic [3:0] foo [1:0]; - logic [3:0] fooe [1:0]; - initial begin - foo[0] = 4'b0101; - foo[1] = 4'b0011; + logic [3:0] foo[1:0]; + logic [3:0] fooe[1:0]; + initial begin + foo[0] = 4'b0101; + foo[1] = 4'b0011; - `checkh(foo.or, 4'b0111); - `checkh(foo.and, 4'b0001); - `checkh(foo.xor, 4'b0110); - `checkh(foo.sum, 4'b1000); - `checkh(foo.product, 4'b1111); + `checkh(foo.or, 4'b0111); + `checkh(foo.and, 4'b0001); + `checkh(foo.xor, 4'b0110); + `checkh(foo.sum, 4'b1000); + `checkh(foo.product, 4'b1111); - fooe[0] = 4'b0101; - fooe[1] = 4'b0011; - if (foo != fooe) $stop; + fooe[0] = 4'b0101; + fooe[1] = 4'b0011; + if (foo != fooe) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_array_unpacked_public.v b/test_regress/t/t_array_unpacked_public.v index b74d6de54..a16595f07 100644 --- a/test_regress/t/t_array_unpacked_public.v +++ b/test_regress/t/t_array_unpacked_public.v @@ -4,10 +4,10 @@ // SPDX-FileCopyrightText: 2020 Stefan Wallentowitz // SPDX-License-Identifier: CC0-1.0 -module t(); - logic din [0:15]; +module t; + logic din[0:15]; - array_test array_test_inst(.din(din)); + array_test array_test_inst (.din(din)); initial begin $write("*-* All Finished *-*\n"); @@ -15,7 +15,7 @@ module t(); end endmodule -module array_test( - input din [0:15] +module array_test ( + input din[0:15] ); endmodule diff --git a/test_regress/t/t_assert_always_unsup.out b/test_regress/t/t_assert_always_unsup.out index f33c70fe2..7bbe0404c 100644 --- a/test_regress/t/t_assert_always_unsup.out +++ b/test_regress/t/t_assert_always_unsup.out @@ -1,16 +1,16 @@ -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:21:7: Unsupported: always[] (in property expression) - 21 | always [2:5] a; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_assert_always_unsup.v:20:5: Unsupported: always[] (in property expression) + 20 | always [2:5] a; + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:25:7: Unsupported: s_always (in property expression) - 25 | s_always [2:5] a; - | ^~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_always_unsup.v:29:7: Unsupported: eventually[] (in property expression) - 29 | eventually [2:5] a; - | ^~~~~~~~~~ -%Error: t/t_assert_always_unsup.v:33:20: syntax error, unexpected ']', expecting ':' - 33 | eventually [2] a; - | ^ +%Error-UNSUPPORTED: t/t_assert_always_unsup.v:24:5: Unsupported: s_always (in property expression) + 24 | s_always [2:5] a; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_always_unsup.v:28:5: Unsupported: eventually[] (in property expression) + 28 | eventually [2:5] a; + | ^~~~~~~~~~ +%Error: t/t_assert_always_unsup.v:32:18: syntax error, unexpected ']', expecting ':' + 32 | eventually [2] a; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Cannot continue ... This fatal error may be caused by the earlier error(s); resolve those first. diff --git a/test_regress/t/t_assert_always_unsup.v b/test_regress/t/t_assert_always_unsup.v index 3165d4420..332064fee 100644 --- a/test_regress/t/t_assert_always_unsup.v +++ b/test_regress/t/t_assert_always_unsup.v @@ -4,45 +4,44 @@ // SPDX-FileCopyrightText: 2022-2025 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic val = 0; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property p_alw; - always [2:5] a; - endproperty + property p_alw; + always [2:5] a; + endproperty - property p_s_alw; - s_always [2:5] a; - endproperty + property p_s_alw; + s_always [2:5] a; + endproperty - property p_ev; - eventually [2:5] a; - endproperty + property p_ev; + eventually [2:5] a; + endproperty - property p_evc; - eventually [2] a; - endproperty + property p_evc; + eventually [2] a; + endproperty - property p_s_ev; - s_eventually [2:5] a; - endproperty + property p_s_ev; + s_eventually [2:5] a; + endproperty - property p_s_alw_ev; - always s_eventually [2:5] a; - endproperty + property p_s_alw_ev; + always s_eventually [2:5] a; + endproperty - property p_s_ev_alw; - s_eventually always [2:5] a; - endproperty + property p_s_ev_alw; + s_eventually always [2:5] a; + endproperty endmodule diff --git a/test_regress/t/t_assert_basic.v b/test_regress/t/t_assert_basic.v index 768a9f823..7d96ac19c 100644 --- a/test_regress/t/t_assert_basic.v +++ b/test_regress/t/t_assert_basic.v @@ -4,50 +4,62 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg toggle; - reg toggle; + integer cyc; + initial cyc = 1; + wire [7:0] cyc_copy = cyc[7:0]; - integer cyc; initial cyc=1; - wire [7:0] cyc_copy = cyc[7:0]; + always @(negedge clk) begin + AssertionFalse1 : assert (cyc < 100); + assert (!(cyc == 5) || toggle); + // FIX cover {cyc==3 || cyc==4}; + // FIX cover {cyc==9} report "DefaultClock,expect=1"; + // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; + end - always @ (negedge clk) begin - AssertionFalse1: assert (cyc<100); - assert (!(cyc==5) || toggle); - // FIX cover {cyc==3 || cyc==4}; - // FIX cover {cyc==9} report "DefaultClock,expect=1"; - // FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1"; - end - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= !cyc[0]; - if (cyc==7) assert (cyc[0] == cyc[1]); // bug743 - if (cyc==9) begin + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc == 7) assert (cyc[0] == cyc[1]); // bug743 + if (cyc == 9) begin `ifdef FAILING_ASSERTIONS - assert (0) else $info; - assert (0) else $info("Info message"); - assume (0) else $info("Info message from failing assumption"); - assert (0) else $info("Info message, cyc=%d", cyc); - InWarningBlock: assert (0) else $warning; - InWarningMBlock: assert (0) else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); - InErrorBlock: assert (0) else $error; - InErrorMBlock: assert (0) else $error("Error...."); - assert (0) else $fatal(1, "Fatal...."); - assert (0) else $fatal; + assert (0) + else $info; + assert (0) + else $info("Info message"); + assume (0) + else $info("Info message from failing assumption"); + assert (0) + else $info("Info message, cyc=%d", cyc); + InWarningBlock : + assert (0) + else $warning; + InWarningMBlock : + assert (0) + else $warning("Warning.... 1.0=%f 2.0=%f", 1.0, 2.0); + InErrorBlock : + assert (0) + else $error; + InErrorMBlock : + assert (0) + else $error("Error...."); + assert (0) + else $fatal(1, "Fatal...."); + assert (0) + else $fatal; `endif - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end end - end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_assert_casez.v b/test_regress/t/t_assert_casez.v index a906454de..4b1c4b336 100644 --- a/test_regress/t/t_assert_casez.v +++ b/test_regress/t/t_assert_casez.v @@ -6,25 +6,25 @@ module t; - reg [1:0] value; + reg [1:0] value; - initial begin - value = 2'b00; - unique casez (value) - 2'b00 : ; - 2'b01 : ; - 2'b1? : ; - endcase - value = 2'b11; - unique casez (value) - 2'b00 : ; - 2'b01 : ; - 2'b1? : ; - endcase - unique casez (1'b1) - default: ; - endcase - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + value = 2'b00; + unique casez (value) + 2'b00: ; + 2'b01: ; + 2'b1?: ; + endcase + value = 2'b11; + unique casez (value) + 2'b00: ; + 2'b01: ; + 2'b1?: ; + endcase + unique casez (1'b1) + default: ; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_clock_event_unsup.out b/test_regress/t/t_assert_clock_event_unsup.out index 56484ebb6..c1afa7434 100644 --- a/test_regress/t/t_assert_clock_event_unsup.out +++ b/test_regress/t/t_assert_clock_event_unsup.out @@ -1,5 +1,5 @@ -%Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:26:7: Unsupported: Clock event before property call and in its body - 26 | @(negedge clk) - | ^ +%Error-UNSUPPORTED: t/t_assert_clock_event_unsup.v:24:5: Unsupported: Clock event before property call and in its body + 24 | @(negedge clk) check( + | ^ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assert_clock_event_unsup.v b/test_regress/t/t_assert_clock_event_unsup.v index eaac7d402..db7323c78 100644 --- a/test_regress/t/t_assert_clock_event_unsup.v +++ b/test_regress/t/t_assert_clock_event_unsup.v @@ -4,34 +4,33 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic val = 0; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property check(int cyc_mod_2, logic expected); - @(posedge clk) - cyc % 2 == cyc_mod_2 |=> val == expected; - endproperty + property check(int cyc_mod_2, logic expected); + @(posedge clk) cyc % 2 == cyc_mod_2 |=> val == expected; + endproperty - property check_if_1(int cyc_mod_2); - @(negedge clk) - check(cyc_mod_2, 1); - endproperty + property check_if_1(int cyc_mod_2); + @(negedge clk) check( + cyc_mod_2, 1 + ); + endproperty - assert property(check_if_1(1)) - else begin - // Assertion should fail - $write("*-* All Finished *-*\n"); - $finish; - end + assert property (check_if_1(1)) + else begin + // Assertion should fail + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_comp.v b/test_regress/t/t_assert_comp.v index 970ac4b1a..ff8797118 100644 --- a/test_regress/t/t_assert_comp.v +++ b/test_regress/t/t_assert_comp.v @@ -6,28 +6,28 @@ module t; - localparam TEN = 10; - localparam string PCTPCT = "%%"; + localparam TEN = 10; + localparam string PCTPCT = "%%"; - if (0) begin - $info; - $info("User elaboration-time info"); - $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); - $warning; - $warning("User elaboration-time warning"); - $warning(1); // Check can convert arguments to format - $error("User elaboration-time error"); - end + if (0) begin + $info; + $info("User elaboration-time info"); + $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); + $warning; + $warning("User elaboration-time warning"); + $warning(1); // Check can convert arguments to format + $error("User elaboration-time error"); + end - initial begin - $info; - $info("User run-time info"); - $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); - $warning; - $warning("User run-time warning"); - $warning(1); // Check can convert arguments to format + initial begin + $info; + $info("User run-time info"); + $info("Percent=%% PctPct=%s Ten=%0d", PCTPCT, TEN); + $warning; + $warning("User run-time warning"); + $warning(1); // Check can convert arguments to format - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_cover.v b/test_regress/t/t_assert_cover.v index 1fc90b039..0844864b8 100644 --- a/test_regress/t/t_assert_cover.v +++ b/test_regress/t/t_assert_cover.v @@ -4,156 +4,154 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - reg toggle; - integer cyc; initial cyc=1; + reg toggle; + integer cyc; initial cyc=1; - Test test (/*AUTOINST*/ - // Inputs - .clk (clk), - .toggle (toggle), - .cyc (cyc[31:0])); + Test test (/*AUTOINST*/ + // Inputs + .clk (clk), + .toggle (toggle), + .cyc (cyc[31:0])); - Sub sub1 (.*); - Sub sub2 (.*); + Sub sub1 (.*); + Sub sub2 (.*); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - toggle <= !cyc[0]; - if (cyc==9) begin - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + toggle <= !cyc[0]; + if (cyc==9) begin end - end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule module Test ( - input clk, - input toggle, - input [31:0] cyc - ); + input clk, + input toggle, + input [31:0] cyc + ); - // Simple cover - cover property (@(posedge clk) cyc==3); + // Simple cover + cover property (@(posedge clk) cyc==3); - // With statement, in generate - generate if (1) begin - cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4"); - end - endgenerate + // With statement, in generate + generate if (1) begin + cover property (@(posedge clk) cyc==4) $display("*COVER: Cyc==4"); + end + endgenerate - // Labeled cover - cyc_eq_5: - cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); + // Labeled cover + cyc_eq_5: + cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5"); - // Using default clock - default clocking @(posedge clk); endclocking - cover property (cyc==6) $display("*COVER: Cyc==6"); + // Using default clock + default clocking @(posedge clk); endclocking + cover property (cyc==6) $display("*COVER: Cyc==6"); - // Disable statement - // Note () after disable are required - cover property (@(posedge clk) disable iff (toggle) cyc==8) - $display("*COVER: Cyc==8"); - cover property (@(posedge clk) disable iff (!toggle) cyc==8) - $stop; + // Disable statement + // Note () after disable are required + cover property (@(posedge clk) disable iff (toggle) cyc==8) + $display("*COVER: Cyc==8"); + cover property (@(posedge clk) disable iff (!toggle) cyc==8) + $stop; - always_ff @ (posedge clk) begin - labeled_icov: cover (cyc==3 || cyc==4); - end + always_ff @ (posedge clk) begin + labeled_icov: cover (cyc==3 || cyc==4); + end - // Immediate cover - labeled_imm0: cover #0 (cyc == 0); - labeled_immf: cover final (cyc == 0); + // Immediate cover + labeled_imm0: cover #0 (cyc == 0); + labeled_immf: cover final (cyc == 0); - // Immediate assert - labeled_imas: assert #0 (1); - assert final (1); + // Immediate assert + labeled_imas: assert #0 (1); + assert final (1); - //============================================================ - // Using a macro and generate - wire reset = (cyc < 2); + //============================================================ + // Using a macro and generate + wire reset = (cyc < 2); `define covclk(eqn) cover property (@(posedge clk) disable iff (reset) (eqn)) - genvar i; - generate - for (i=0; i<32; i=i+1) - begin: cycval - CycCover_i: `covclk( cyc[i] ); - end - endgenerate + genvar i; + generate + for (i=0; i<32; i=i+1) + begin: cycval + CycCover_i: `covclk( cyc[i] ); + end + endgenerate - //============================================================ - // Using a more complicated property - property C1; - @(posedge clk) - disable iff (!toggle) - cyc==5; - endproperty - cover property (C1) $display("*COVER: Cyc==5"); + //============================================================ + // Using a more complicated property + property C1; + @(posedge clk) + disable iff (!toggle) + cyc==5; + endproperty + cover property (C1) $display("*COVER: Cyc==5"); `ifndef verilator // Unsupported - //============================================================ - // Using covergroup - // Note a covergroup is really inheritance of a special system "covergroup" class. - covergroup counter1 @ (posedge cyc); - // Automatic methods: stop(), start(), sample(), set_inst_name() + //============================================================ + // Using covergroup + // Note a covergroup is really inheritance of a special system "covergroup" class. + covergroup counter1 @ (posedge cyc); + // Automatic methods: stop(), start(), sample(), set_inst_name() - // Each bin value must be <= 32 bits. Strange. - cyc_value : coverpoint cyc { - } - - cyc_bined : coverpoint cyc { - bins zero = {0}; - bins low = {1,5}; - // Note 5 is also in the bin above. Only the first bin matching is counted. - bins mid = {[5:$]}; - // illegal_bins // Has precidence over "first matching bin", creates assertion - // ignore_bins // Not counted, and not part of total - } - toggle : coverpoint (toggle) { - bins off = {0}; - bins on = {1}; - } - cyc5 : coverpoint (cyc==5) { - bins five = {1}; + // Each bin value must be <= 32 bits. Strange. + cyc_value : coverpoint cyc { } - // option.at_least = {number}; // Default 1 - Hits to be considered covered - // option.auto_bin_max = {number}; // Default 64 - // option.comment = {string}; // Default "" - // option.goal = {number}; // Default 90% - // option.name = {string}; // Default "" - // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) - // option.weight = {number}; // Default 1 + cyc_bined : coverpoint cyc { + bins zero = {0}; + bins low = {1,5}; + // Note 5 is also in the bin above. Only the first bin matching is counted. + bins mid = {[5:$]}; + // illegal_bins // Has precidence over "first matching bin", creates assertion + // ignore_bins // Not counted, and not part of total + } + toggle : coverpoint (toggle) { + bins off = {0}; + bins on = {1}; + } + cyc5 : coverpoint (cyc==5) { + bins five = {1}; + } - // CROSS - value_and_toggle: // else default is ___X__ - cross cyc_value, toggle; - endgroup - counter1 c1 = new(); + // option.at_least = {number}; // Default 1 - Hits to be considered covered + // option.auto_bin_max = {number}; // Default 64 + // option.comment = {string}; // Default "" + // option.goal = {number}; // Default 90% + // option.name = {string}; // Default "" + // option.per_instance = 1; // Default 0 - each instance separately counted (cadence default is 1) + // option.weight = {number}; // Default 1 + + // CROSS + value_and_toggle: // else default is ___X__ + cross cyc_value, toggle; + endgroup + counter1 c1 = new(); `endif endmodule module Sub ( - input clk, - input integer cyc - ); + input clk, + input integer cyc + ); - // Simple cover, per-instance - pi_sub: - cover property (@(posedge clk) cyc == 3); + // Simple cover, per-instance + pi_sub: + cover property (@(posedge clk) cyc == 3); endmodule diff --git a/test_regress/t/t_assert_ctl_arg.dat.out b/test_regress/t/t_assert_ctl_arg.dat.out index a19ca52fa..b83831847 100644 --- a/test_regress/t/t_assert_ctl_arg.dat.out +++ b/test_regress/t/t_assert_ctl_arg.dat.out @@ -1,153 +1,153 @@ # SystemC::Coverage-3 -C 'ft/t_assert_ctl_arg.vl100n32tuserpagev_user/tocover_simple_immediate_100htop.t.cover_simple_immediate_100' 1 -C 'ft/t_assert_ctl_arg.vl100n37tuserpagev_user/tocover_simple_immediate_stmt_100htop.t.cover_simple_immediate_stmt_100' 1 -C 'ft/t_assert_ctl_arg.vl100n40tuserpagev_user/tocover_final_deferred_immediate_100htop.t.cover_final_deferred_immediate_100' 1 -C 'ft/t_assert_ctl_arg.vl100n43tuserpagev_user/tocover_observed_deferred_immediate_100htop.t.cover_observed_deferred_immediate_100' 1 -C 'ft/t_assert_ctl_arg.vl100n45tuserpagev_user/tocover_final_deferred_immediate_stmt_100htop.t.cover_final_deferred_immediate_stmt_100' 1 -C 'ft/t_assert_ctl_arg.vl100n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_100htop.t.cover_observed_deferred_immediate_stmt_100' 1 -C 'ft/t_assert_ctl_arg.vl103n32tuserpagev_user/tocover_simple_immediate_103htop.t.cover_simple_immediate_103' 0 -C 'ft/t_assert_ctl_arg.vl103n37tuserpagev_user/tocover_simple_immediate_stmt_103htop.t.cover_simple_immediate_stmt_103' 0 -C 'ft/t_assert_ctl_arg.vl103n40tuserpagev_user/tocover_final_deferred_immediate_103htop.t.cover_final_deferred_immediate_103' 0 -C 'ft/t_assert_ctl_arg.vl103n43tuserpagev_user/tocover_observed_deferred_immediate_103htop.t.cover_observed_deferred_immediate_103' 0 -C 'ft/t_assert_ctl_arg.vl103n45tuserpagev_user/tocover_final_deferred_immediate_stmt_103htop.t.cover_final_deferred_immediate_stmt_103' 0 -C 'ft/t_assert_ctl_arg.vl103n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_103htop.t.cover_observed_deferred_immediate_stmt_103' 0 -C 'ft/t_assert_ctl_arg.vl106n32tuserpagev_user/tocover_simple_immediate_106htop.t.cover_simple_immediate_106' 1 -C 'ft/t_assert_ctl_arg.vl106n37tuserpagev_user/tocover_simple_immediate_stmt_106htop.t.cover_simple_immediate_stmt_106' 1 -C 'ft/t_assert_ctl_arg.vl106n40tuserpagev_user/tocover_final_deferred_immediate_106htop.t.cover_final_deferred_immediate_106' 1 -C 'ft/t_assert_ctl_arg.vl106n43tuserpagev_user/tocover_observed_deferred_immediate_106htop.t.cover_observed_deferred_immediate_106' 1 -C 'ft/t_assert_ctl_arg.vl106n45tuserpagev_user/tocover_final_deferred_immediate_stmt_106htop.t.cover_final_deferred_immediate_stmt_106' 1 -C 'ft/t_assert_ctl_arg.vl106n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_106htop.t.cover_observed_deferred_immediate_stmt_106' 1 -C 'ft/t_assert_ctl_arg.vl108n32tuserpagev_user/tocover_simple_immediate_108htop.t.cover_simple_immediate_108' 1 -C 'ft/t_assert_ctl_arg.vl108n37tuserpagev_user/tocover_simple_immediate_stmt_108htop.t.cover_simple_immediate_stmt_108' 1 -C 'ft/t_assert_ctl_arg.vl108n40tuserpagev_user/tocover_final_deferred_immediate_108htop.t.cover_final_deferred_immediate_108' 1 -C 'ft/t_assert_ctl_arg.vl108n43tuserpagev_user/tocover_observed_deferred_immediate_108htop.t.cover_observed_deferred_immediate_108' 1 -C 'ft/t_assert_ctl_arg.vl108n45tuserpagev_user/tocover_final_deferred_immediate_stmt_108htop.t.cover_final_deferred_immediate_stmt_108' 1 -C 'ft/t_assert_ctl_arg.vl108n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_108htop.t.cover_observed_deferred_immediate_stmt_108' 1 -C 'ft/t_assert_ctl_arg.vl110n32tuserpagev_user/tocover_simple_immediate_110htop.t.cover_simple_immediate_110' 0 -C 'ft/t_assert_ctl_arg.vl110n37tuserpagev_user/tocover_simple_immediate_stmt_110htop.t.cover_simple_immediate_stmt_110' 0 -C 'ft/t_assert_ctl_arg.vl110n40tuserpagev_user/tocover_final_deferred_immediate_110htop.t.cover_final_deferred_immediate_110' 0 -C 'ft/t_assert_ctl_arg.vl110n43tuserpagev_user/tocover_observed_deferred_immediate_110htop.t.cover_observed_deferred_immediate_110' 0 -C 'ft/t_assert_ctl_arg.vl110n45tuserpagev_user/tocover_final_deferred_immediate_stmt_110htop.t.cover_final_deferred_immediate_stmt_110' 0 -C 'ft/t_assert_ctl_arg.vl110n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_110htop.t.cover_observed_deferred_immediate_stmt_110' 0 -C 'ft/t_assert_ctl_arg.vl112n32tuserpagev_user/tocover_simple_immediate_112htop.t.cover_simple_immediate_112' 1 -C 'ft/t_assert_ctl_arg.vl112n37tuserpagev_user/tocover_simple_immediate_stmt_112htop.t.cover_simple_immediate_stmt_112' 1 -C 'ft/t_assert_ctl_arg.vl112n40tuserpagev_user/tocover_final_deferred_immediate_112htop.t.cover_final_deferred_immediate_112' 1 -C 'ft/t_assert_ctl_arg.vl112n43tuserpagev_user/tocover_observed_deferred_immediate_112htop.t.cover_observed_deferred_immediate_112' 0 -C 'ft/t_assert_ctl_arg.vl112n45tuserpagev_user/tocover_final_deferred_immediate_stmt_112htop.t.cover_final_deferred_immediate_stmt_112' 1 -C 'ft/t_assert_ctl_arg.vl112n48tuserpagev_user/tocover_observed_deferred_immediate_stmt_112htop.t.cover_observed_deferred_immediate_stmt_112' 0 -C 'ft/t_assert_ctl_arg.vl192n22tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0 -C 'ft/t_assert_ctl_arg.vl193n27tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0 -C 'ft/t_assert_ctl_arg.vl49n31tuserpagev_user/tocover_simple_immediate_49htop.t.cover_simple_immediate_49' 1 -C 'ft/t_assert_ctl_arg.vl49n36tuserpagev_user/tocover_simple_immediate_stmt_49htop.t.cover_simple_immediate_stmt_49' 1 -C 'ft/t_assert_ctl_arg.vl49n39tuserpagev_user/tocover_final_deferred_immediate_49htop.t.cover_final_deferred_immediate_49' 0 -C 'ft/t_assert_ctl_arg.vl49n42tuserpagev_user/tocover_observed_deferred_immediate_49htop.t.cover_observed_deferred_immediate_49' 0 -C 'ft/t_assert_ctl_arg.vl49n44tuserpagev_user/tocover_final_deferred_immediate_stmt_49htop.t.cover_final_deferred_immediate_stmt_49' 0 -C 'ft/t_assert_ctl_arg.vl49n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_49htop.t.cover_observed_deferred_immediate_stmt_49' 0 -C 'ft/t_assert_ctl_arg.vl51n31tuserpagev_user/tocover_simple_immediate_51htop.t.cover_simple_immediate_51' 0 -C 'ft/t_assert_ctl_arg.vl51n36tuserpagev_user/tocover_simple_immediate_stmt_51htop.t.cover_simple_immediate_stmt_51' 0 -C 'ft/t_assert_ctl_arg.vl51n39tuserpagev_user/tocover_final_deferred_immediate_51htop.t.cover_final_deferred_immediate_51' 0 -C 'ft/t_assert_ctl_arg.vl51n42tuserpagev_user/tocover_observed_deferred_immediate_51htop.t.cover_observed_deferred_immediate_51' 0 -C 'ft/t_assert_ctl_arg.vl51n44tuserpagev_user/tocover_final_deferred_immediate_stmt_51htop.t.cover_final_deferred_immediate_stmt_51' 0 -C 'ft/t_assert_ctl_arg.vl51n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_51htop.t.cover_observed_deferred_immediate_stmt_51' 0 -C 'ft/t_assert_ctl_arg.vl56n31tuserpagev_user/tocover_simple_immediate_56htop.t.cover_simple_immediate_56' 0 -C 'ft/t_assert_ctl_arg.vl56n36tuserpagev_user/tocover_simple_immediate_stmt_56htop.t.cover_simple_immediate_stmt_56' 0 -C 'ft/t_assert_ctl_arg.vl56n39tuserpagev_user/tocover_final_deferred_immediate_56htop.t.cover_final_deferred_immediate_56' 0 -C 'ft/t_assert_ctl_arg.vl56n42tuserpagev_user/tocover_observed_deferred_immediate_56htop.t.cover_observed_deferred_immediate_56' 1 -C 'ft/t_assert_ctl_arg.vl56n44tuserpagev_user/tocover_final_deferred_immediate_stmt_56htop.t.cover_final_deferred_immediate_stmt_56' 0 -C 'ft/t_assert_ctl_arg.vl56n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_56htop.t.cover_observed_deferred_immediate_stmt_56' 1 -C 'ft/t_assert_ctl_arg.vl58n31tuserpagev_user/tocover_simple_immediate_58htop.t.cover_simple_immediate_58' 0 -C 'ft/t_assert_ctl_arg.vl58n36tuserpagev_user/tocover_simple_immediate_stmt_58htop.t.cover_simple_immediate_stmt_58' 0 -C 'ft/t_assert_ctl_arg.vl58n39tuserpagev_user/tocover_final_deferred_immediate_58htop.t.cover_final_deferred_immediate_58' 0 -C 'ft/t_assert_ctl_arg.vl58n42tuserpagev_user/tocover_observed_deferred_immediate_58htop.t.cover_observed_deferred_immediate_58' 0 -C 'ft/t_assert_ctl_arg.vl58n44tuserpagev_user/tocover_final_deferred_immediate_stmt_58htop.t.cover_final_deferred_immediate_stmt_58' 0 -C 'ft/t_assert_ctl_arg.vl58n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_58htop.t.cover_observed_deferred_immediate_stmt_58' 0 -C 'ft/t_assert_ctl_arg.vl63n31tuserpagev_user/tocover_simple_immediate_63htop.t.cover_simple_immediate_63' 0 -C 'ft/t_assert_ctl_arg.vl63n36tuserpagev_user/tocover_simple_immediate_stmt_63htop.t.cover_simple_immediate_stmt_63' 0 -C 'ft/t_assert_ctl_arg.vl63n39tuserpagev_user/tocover_final_deferred_immediate_63htop.t.cover_final_deferred_immediate_63' 1 -C 'ft/t_assert_ctl_arg.vl63n42tuserpagev_user/tocover_observed_deferred_immediate_63htop.t.cover_observed_deferred_immediate_63' 0 -C 'ft/t_assert_ctl_arg.vl63n44tuserpagev_user/tocover_final_deferred_immediate_stmt_63htop.t.cover_final_deferred_immediate_stmt_63' 1 -C 'ft/t_assert_ctl_arg.vl63n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_63htop.t.cover_observed_deferred_immediate_stmt_63' 0 -C 'ft/t_assert_ctl_arg.vl65n31tuserpagev_user/tocover_simple_immediate_65htop.t.cover_simple_immediate_65' 0 -C 'ft/t_assert_ctl_arg.vl65n36tuserpagev_user/tocover_simple_immediate_stmt_65htop.t.cover_simple_immediate_stmt_65' 0 -C 'ft/t_assert_ctl_arg.vl65n39tuserpagev_user/tocover_final_deferred_immediate_65htop.t.cover_final_deferred_immediate_65' 0 -C 'ft/t_assert_ctl_arg.vl65n42tuserpagev_user/tocover_observed_deferred_immediate_65htop.t.cover_observed_deferred_immediate_65' 0 -C 'ft/t_assert_ctl_arg.vl65n44tuserpagev_user/tocover_final_deferred_immediate_stmt_65htop.t.cover_final_deferred_immediate_stmt_65' 0 -C 'ft/t_assert_ctl_arg.vl65n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_65htop.t.cover_observed_deferred_immediate_stmt_65' 0 -C 'ft/t_assert_ctl_arg.vl69n31tuserpagev_user/tocover_simple_immediate_69htop.t.cover_simple_immediate_69' 0 -C 'ft/t_assert_ctl_arg.vl69n36tuserpagev_user/tocover_simple_immediate_stmt_69htop.t.cover_simple_immediate_stmt_69' 0 -C 'ft/t_assert_ctl_arg.vl69n39tuserpagev_user/tocover_final_deferred_immediate_69htop.t.cover_final_deferred_immediate_69' 0 -C 'ft/t_assert_ctl_arg.vl69n42tuserpagev_user/tocover_observed_deferred_immediate_69htop.t.cover_observed_deferred_immediate_69' 0 -C 'ft/t_assert_ctl_arg.vl69n44tuserpagev_user/tocover_final_deferred_immediate_stmt_69htop.t.cover_final_deferred_immediate_stmt_69' 0 -C 'ft/t_assert_ctl_arg.vl69n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_69htop.t.cover_observed_deferred_immediate_stmt_69' 0 -C 'ft/t_assert_ctl_arg.vl71n31tuserpagev_user/tocover_simple_immediate_71htop.t.cover_simple_immediate_71' 1 -C 'ft/t_assert_ctl_arg.vl71n36tuserpagev_user/tocover_simple_immediate_stmt_71htop.t.cover_simple_immediate_stmt_71' 1 -C 'ft/t_assert_ctl_arg.vl71n39tuserpagev_user/tocover_final_deferred_immediate_71htop.t.cover_final_deferred_immediate_71' 1 -C 'ft/t_assert_ctl_arg.vl71n42tuserpagev_user/tocover_observed_deferred_immediate_71htop.t.cover_observed_deferred_immediate_71' 1 -C 'ft/t_assert_ctl_arg.vl71n44tuserpagev_user/tocover_final_deferred_immediate_stmt_71htop.t.cover_final_deferred_immediate_stmt_71' 1 -C 'ft/t_assert_ctl_arg.vl71n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_71htop.t.cover_observed_deferred_immediate_stmt_71' 1 -C 'ft/t_assert_ctl_arg.vl73n31tuserpagev_user/tocover_simple_immediate_73htop.t.cover_simple_immediate_73' 0 -C 'ft/t_assert_ctl_arg.vl73n36tuserpagev_user/tocover_simple_immediate_stmt_73htop.t.cover_simple_immediate_stmt_73' 0 -C 'ft/t_assert_ctl_arg.vl73n39tuserpagev_user/tocover_final_deferred_immediate_73htop.t.cover_final_deferred_immediate_73' 0 -C 'ft/t_assert_ctl_arg.vl73n42tuserpagev_user/tocover_observed_deferred_immediate_73htop.t.cover_observed_deferred_immediate_73' 0 -C 'ft/t_assert_ctl_arg.vl73n44tuserpagev_user/tocover_final_deferred_immediate_stmt_73htop.t.cover_final_deferred_immediate_stmt_73' 0 -C 'ft/t_assert_ctl_arg.vl73n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_73htop.t.cover_observed_deferred_immediate_stmt_73' 0 -C 'ft/t_assert_ctl_arg.vl76n31tuserpagev_user/tocover_simple_immediate_76htop.t.cover_simple_immediate_76' 1 -C 'ft/t_assert_ctl_arg.vl76n36tuserpagev_user/tocover_simple_immediate_stmt_76htop.t.cover_simple_immediate_stmt_76' 1 -C 'ft/t_assert_ctl_arg.vl76n39tuserpagev_user/tocover_final_deferred_immediate_76htop.t.cover_final_deferred_immediate_76' 0 -C 'ft/t_assert_ctl_arg.vl76n42tuserpagev_user/tocover_observed_deferred_immediate_76htop.t.cover_observed_deferred_immediate_76' 1 -C 'ft/t_assert_ctl_arg.vl76n44tuserpagev_user/tocover_final_deferred_immediate_stmt_76htop.t.cover_final_deferred_immediate_stmt_76' 0 -C 'ft/t_assert_ctl_arg.vl76n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_76htop.t.cover_observed_deferred_immediate_stmt_76' 1 -C 'ft/t_assert_ctl_arg.vl78n31tuserpagev_user/tocover_simple_immediate_78htop.t.cover_simple_immediate_78' 1 -C 'ft/t_assert_ctl_arg.vl78n36tuserpagev_user/tocover_simple_immediate_stmt_78htop.t.cover_simple_immediate_stmt_78' 1 -C 'ft/t_assert_ctl_arg.vl78n39tuserpagev_user/tocover_final_deferred_immediate_78htop.t.cover_final_deferred_immediate_78' 1 -C 'ft/t_assert_ctl_arg.vl78n42tuserpagev_user/tocover_observed_deferred_immediate_78htop.t.cover_observed_deferred_immediate_78' 1 -C 'ft/t_assert_ctl_arg.vl78n44tuserpagev_user/tocover_final_deferred_immediate_stmt_78htop.t.cover_final_deferred_immediate_stmt_78' 1 -C 'ft/t_assert_ctl_arg.vl78n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_78htop.t.cover_observed_deferred_immediate_stmt_78' 1 -C 'ft/t_assert_ctl_arg.vl80n31tuserpagev_user/tocover_simple_immediate_80htop.t.cover_simple_immediate_80' 1 -C 'ft/t_assert_ctl_arg.vl80n36tuserpagev_user/tocover_simple_immediate_stmt_80htop.t.cover_simple_immediate_stmt_80' 1 -C 'ft/t_assert_ctl_arg.vl80n39tuserpagev_user/tocover_final_deferred_immediate_80htop.t.cover_final_deferred_immediate_80' 0 -C 'ft/t_assert_ctl_arg.vl80n42tuserpagev_user/tocover_observed_deferred_immediate_80htop.t.cover_observed_deferred_immediate_80' 0 -C 'ft/t_assert_ctl_arg.vl80n44tuserpagev_user/tocover_final_deferred_immediate_stmt_80htop.t.cover_final_deferred_immediate_stmt_80' 0 -C 'ft/t_assert_ctl_arg.vl80n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_80htop.t.cover_observed_deferred_immediate_stmt_80' 0 -C 'ft/t_assert_ctl_arg.vl82n31tuserpagev_user/tocover_simple_immediate_82htop.t.cover_simple_immediate_82' 1 -C 'ft/t_assert_ctl_arg.vl82n36tuserpagev_user/tocover_simple_immediate_stmt_82htop.t.cover_simple_immediate_stmt_82' 1 -C 'ft/t_assert_ctl_arg.vl82n39tuserpagev_user/tocover_final_deferred_immediate_82htop.t.cover_final_deferred_immediate_82' 0 -C 'ft/t_assert_ctl_arg.vl82n42tuserpagev_user/tocover_observed_deferred_immediate_82htop.t.cover_observed_deferred_immediate_82' 0 -C 'ft/t_assert_ctl_arg.vl82n44tuserpagev_user/tocover_final_deferred_immediate_stmt_82htop.t.cover_final_deferred_immediate_stmt_82' 0 -C 'ft/t_assert_ctl_arg.vl82n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_82htop.t.cover_observed_deferred_immediate_stmt_82' 0 -C 'ft/t_assert_ctl_arg.vl84n31tuserpagev_user/tocover_simple_immediate_84htop.t.cover_simple_immediate_84' 0 -C 'ft/t_assert_ctl_arg.vl84n36tuserpagev_user/tocover_simple_immediate_stmt_84htop.t.cover_simple_immediate_stmt_84' 0 -C 'ft/t_assert_ctl_arg.vl84n39tuserpagev_user/tocover_final_deferred_immediate_84htop.t.cover_final_deferred_immediate_84' 0 -C 'ft/t_assert_ctl_arg.vl84n42tuserpagev_user/tocover_observed_deferred_immediate_84htop.t.cover_observed_deferred_immediate_84' 0 -C 'ft/t_assert_ctl_arg.vl84n44tuserpagev_user/tocover_final_deferred_immediate_stmt_84htop.t.cover_final_deferred_immediate_stmt_84' 0 -C 'ft/t_assert_ctl_arg.vl84n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_84htop.t.cover_observed_deferred_immediate_stmt_84' 0 -C 'ft/t_assert_ctl_arg.vl86n31tuserpagev_user/tocover_simple_immediate_86htop.t.cover_simple_immediate_86' 1 -C 'ft/t_assert_ctl_arg.vl86n36tuserpagev_user/tocover_simple_immediate_stmt_86htop.t.cover_simple_immediate_stmt_86' 1 -C 'ft/t_assert_ctl_arg.vl86n39tuserpagev_user/tocover_final_deferred_immediate_86htop.t.cover_final_deferred_immediate_86' 0 -C 'ft/t_assert_ctl_arg.vl86n42tuserpagev_user/tocover_observed_deferred_immediate_86htop.t.cover_observed_deferred_immediate_86' 0 -C 'ft/t_assert_ctl_arg.vl86n44tuserpagev_user/tocover_final_deferred_immediate_stmt_86htop.t.cover_final_deferred_immediate_stmt_86' 0 -C 'ft/t_assert_ctl_arg.vl86n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_86htop.t.cover_observed_deferred_immediate_stmt_86' 0 -C 'ft/t_assert_ctl_arg.vl88n31tuserpagev_user/tocover_simple_immediate_88htop.t.cover_simple_immediate_88' 0 -C 'ft/t_assert_ctl_arg.vl88n36tuserpagev_user/tocover_simple_immediate_stmt_88htop.t.cover_simple_immediate_stmt_88' 0 -C 'ft/t_assert_ctl_arg.vl88n39tuserpagev_user/tocover_final_deferred_immediate_88htop.t.cover_final_deferred_immediate_88' 0 -C 'ft/t_assert_ctl_arg.vl88n42tuserpagev_user/tocover_observed_deferred_immediate_88htop.t.cover_observed_deferred_immediate_88' 0 -C 'ft/t_assert_ctl_arg.vl88n44tuserpagev_user/tocover_final_deferred_immediate_stmt_88htop.t.cover_final_deferred_immediate_stmt_88' 0 -C 'ft/t_assert_ctl_arg.vl88n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_88htop.t.cover_observed_deferred_immediate_stmt_88' 0 -C 'ft/t_assert_ctl_arg.vl90n31tuserpagev_user/tocover_simple_immediate_90htop.t.cover_simple_immediate_90' 1 -C 'ft/t_assert_ctl_arg.vl90n36tuserpagev_user/tocover_simple_immediate_stmt_90htop.t.cover_simple_immediate_stmt_90' 1 -C 'ft/t_assert_ctl_arg.vl90n39tuserpagev_user/tocover_final_deferred_immediate_90htop.t.cover_final_deferred_immediate_90' 1 -C 'ft/t_assert_ctl_arg.vl90n42tuserpagev_user/tocover_observed_deferred_immediate_90htop.t.cover_observed_deferred_immediate_90' 1 -C 'ft/t_assert_ctl_arg.vl90n44tuserpagev_user/tocover_final_deferred_immediate_stmt_90htop.t.cover_final_deferred_immediate_stmt_90' 1 -C 'ft/t_assert_ctl_arg.vl90n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_90htop.t.cover_observed_deferred_immediate_stmt_90' 1 -C 'ft/t_assert_ctl_arg.vl92n31tuserpagev_user/tocover_simple_immediate_92htop.t.cover_simple_immediate_92' 0 -C 'ft/t_assert_ctl_arg.vl92n36tuserpagev_user/tocover_simple_immediate_stmt_92htop.t.cover_simple_immediate_stmt_92' 0 -C 'ft/t_assert_ctl_arg.vl92n39tuserpagev_user/tocover_final_deferred_immediate_92htop.t.cover_final_deferred_immediate_92' 0 -C 'ft/t_assert_ctl_arg.vl92n42tuserpagev_user/tocover_observed_deferred_immediate_92htop.t.cover_observed_deferred_immediate_92' 0 -C 'ft/t_assert_ctl_arg.vl92n44tuserpagev_user/tocover_final_deferred_immediate_stmt_92htop.t.cover_final_deferred_immediate_stmt_92' 0 -C 'ft/t_assert_ctl_arg.vl92n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_92htop.t.cover_observed_deferred_immediate_stmt_92' 0 -C 'ft/t_assert_ctl_arg.vl97n31tuserpagev_user/tocover_simple_immediate_97htop.t.cover_simple_immediate_97' 0 -C 'ft/t_assert_ctl_arg.vl97n36tuserpagev_user/tocover_simple_immediate_stmt_97htop.t.cover_simple_immediate_stmt_97' 0 -C 'ft/t_assert_ctl_arg.vl97n39tuserpagev_user/tocover_final_deferred_immediate_97htop.t.cover_final_deferred_immediate_97' 0 -C 'ft/t_assert_ctl_arg.vl97n42tuserpagev_user/tocover_observed_deferred_immediate_97htop.t.cover_observed_deferred_immediate_97' 0 -C 'ft/t_assert_ctl_arg.vl97n44tuserpagev_user/tocover_final_deferred_immediate_stmt_97htop.t.cover_final_deferred_immediate_stmt_97' 0 -C 'ft/t_assert_ctl_arg.vl97n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_97htop.t.cover_observed_deferred_immediate_stmt_97' 0 +C 'ft/t_assert_ctl_arg.vl102n31tuserpagev_user/tocover_simple_immediate_102htop.t.cover_simple_immediate_102' 0 +C 'ft/t_assert_ctl_arg.vl102n36tuserpagev_user/tocover_simple_immediate_stmt_102htop.t.cover_simple_immediate_stmt_102' 0 +C 'ft/t_assert_ctl_arg.vl102n39tuserpagev_user/tocover_final_deferred_immediate_102htop.t.cover_final_deferred_immediate_102' 0 +C 'ft/t_assert_ctl_arg.vl102n42tuserpagev_user/tocover_observed_deferred_immediate_102htop.t.cover_observed_deferred_immediate_102' 0 +C 'ft/t_assert_ctl_arg.vl102n44tuserpagev_user/tocover_final_deferred_immediate_stmt_102htop.t.cover_final_deferred_immediate_stmt_102' 0 +C 'ft/t_assert_ctl_arg.vl102n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_102htop.t.cover_observed_deferred_immediate_stmt_102' 0 +C 'ft/t_assert_ctl_arg.vl105n31tuserpagev_user/tocover_simple_immediate_105htop.t.cover_simple_immediate_105' 1 +C 'ft/t_assert_ctl_arg.vl105n36tuserpagev_user/tocover_simple_immediate_stmt_105htop.t.cover_simple_immediate_stmt_105' 1 +C 'ft/t_assert_ctl_arg.vl105n39tuserpagev_user/tocover_final_deferred_immediate_105htop.t.cover_final_deferred_immediate_105' 1 +C 'ft/t_assert_ctl_arg.vl105n42tuserpagev_user/tocover_observed_deferred_immediate_105htop.t.cover_observed_deferred_immediate_105' 1 +C 'ft/t_assert_ctl_arg.vl105n44tuserpagev_user/tocover_final_deferred_immediate_stmt_105htop.t.cover_final_deferred_immediate_stmt_105' 1 +C 'ft/t_assert_ctl_arg.vl105n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_105htop.t.cover_observed_deferred_immediate_stmt_105' 1 +C 'ft/t_assert_ctl_arg.vl107n31tuserpagev_user/tocover_simple_immediate_107htop.t.cover_simple_immediate_107' 1 +C 'ft/t_assert_ctl_arg.vl107n36tuserpagev_user/tocover_simple_immediate_stmt_107htop.t.cover_simple_immediate_stmt_107' 1 +C 'ft/t_assert_ctl_arg.vl107n39tuserpagev_user/tocover_final_deferred_immediate_107htop.t.cover_final_deferred_immediate_107' 1 +C 'ft/t_assert_ctl_arg.vl107n42tuserpagev_user/tocover_observed_deferred_immediate_107htop.t.cover_observed_deferred_immediate_107' 1 +C 'ft/t_assert_ctl_arg.vl107n44tuserpagev_user/tocover_final_deferred_immediate_stmt_107htop.t.cover_final_deferred_immediate_stmt_107' 1 +C 'ft/t_assert_ctl_arg.vl107n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_107htop.t.cover_observed_deferred_immediate_stmt_107' 1 +C 'ft/t_assert_ctl_arg.vl109n31tuserpagev_user/tocover_simple_immediate_109htop.t.cover_simple_immediate_109' 0 +C 'ft/t_assert_ctl_arg.vl109n36tuserpagev_user/tocover_simple_immediate_stmt_109htop.t.cover_simple_immediate_stmt_109' 0 +C 'ft/t_assert_ctl_arg.vl109n39tuserpagev_user/tocover_final_deferred_immediate_109htop.t.cover_final_deferred_immediate_109' 0 +C 'ft/t_assert_ctl_arg.vl109n42tuserpagev_user/tocover_observed_deferred_immediate_109htop.t.cover_observed_deferred_immediate_109' 0 +C 'ft/t_assert_ctl_arg.vl109n44tuserpagev_user/tocover_final_deferred_immediate_stmt_109htop.t.cover_final_deferred_immediate_stmt_109' 0 +C 'ft/t_assert_ctl_arg.vl109n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_109htop.t.cover_observed_deferred_immediate_stmt_109' 0 +C 'ft/t_assert_ctl_arg.vl111n31tuserpagev_user/tocover_simple_immediate_111htop.t.cover_simple_immediate_111' 1 +C 'ft/t_assert_ctl_arg.vl111n36tuserpagev_user/tocover_simple_immediate_stmt_111htop.t.cover_simple_immediate_stmt_111' 1 +C 'ft/t_assert_ctl_arg.vl111n39tuserpagev_user/tocover_final_deferred_immediate_111htop.t.cover_final_deferred_immediate_111' 1 +C 'ft/t_assert_ctl_arg.vl111n42tuserpagev_user/tocover_observed_deferred_immediate_111htop.t.cover_observed_deferred_immediate_111' 0 +C 'ft/t_assert_ctl_arg.vl111n44tuserpagev_user/tocover_final_deferred_immediate_stmt_111htop.t.cover_final_deferred_immediate_stmt_111' 1 +C 'ft/t_assert_ctl_arg.vl111n47tuserpagev_user/tocover_observed_deferred_immediate_stmt_111htop.t.cover_observed_deferred_immediate_stmt_111' 0 +C 'ft/t_assert_ctl_arg.vl191n21tuserpagev_user/concurrentocover_concurrenthtop.t.concurrent.cover_concurrent' 0 +C 'ft/t_assert_ctl_arg.vl192n26tuserpagev_user/concurrentocover_concurrent_stmthtop.t.concurrent.cover_concurrent_stmt' 0 +C 'ft/t_assert_ctl_arg.vl48n30tuserpagev_user/tocover_simple_immediate_48htop.t.cover_simple_immediate_48' 1 +C 'ft/t_assert_ctl_arg.vl48n35tuserpagev_user/tocover_simple_immediate_stmt_48htop.t.cover_simple_immediate_stmt_48' 1 +C 'ft/t_assert_ctl_arg.vl48n38tuserpagev_user/tocover_final_deferred_immediate_48htop.t.cover_final_deferred_immediate_48' 0 +C 'ft/t_assert_ctl_arg.vl48n41tuserpagev_user/tocover_observed_deferred_immediate_48htop.t.cover_observed_deferred_immediate_48' 0 +C 'ft/t_assert_ctl_arg.vl48n43tuserpagev_user/tocover_final_deferred_immediate_stmt_48htop.t.cover_final_deferred_immediate_stmt_48' 0 +C 'ft/t_assert_ctl_arg.vl48n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_48htop.t.cover_observed_deferred_immediate_stmt_48' 0 +C 'ft/t_assert_ctl_arg.vl50n30tuserpagev_user/tocover_simple_immediate_50htop.t.cover_simple_immediate_50' 0 +C 'ft/t_assert_ctl_arg.vl50n35tuserpagev_user/tocover_simple_immediate_stmt_50htop.t.cover_simple_immediate_stmt_50' 0 +C 'ft/t_assert_ctl_arg.vl50n38tuserpagev_user/tocover_final_deferred_immediate_50htop.t.cover_final_deferred_immediate_50' 0 +C 'ft/t_assert_ctl_arg.vl50n41tuserpagev_user/tocover_observed_deferred_immediate_50htop.t.cover_observed_deferred_immediate_50' 0 +C 'ft/t_assert_ctl_arg.vl50n43tuserpagev_user/tocover_final_deferred_immediate_stmt_50htop.t.cover_final_deferred_immediate_stmt_50' 0 +C 'ft/t_assert_ctl_arg.vl50n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_50htop.t.cover_observed_deferred_immediate_stmt_50' 0 +C 'ft/t_assert_ctl_arg.vl55n30tuserpagev_user/tocover_simple_immediate_55htop.t.cover_simple_immediate_55' 0 +C 'ft/t_assert_ctl_arg.vl55n35tuserpagev_user/tocover_simple_immediate_stmt_55htop.t.cover_simple_immediate_stmt_55' 0 +C 'ft/t_assert_ctl_arg.vl55n38tuserpagev_user/tocover_final_deferred_immediate_55htop.t.cover_final_deferred_immediate_55' 0 +C 'ft/t_assert_ctl_arg.vl55n41tuserpagev_user/tocover_observed_deferred_immediate_55htop.t.cover_observed_deferred_immediate_55' 1 +C 'ft/t_assert_ctl_arg.vl55n43tuserpagev_user/tocover_final_deferred_immediate_stmt_55htop.t.cover_final_deferred_immediate_stmt_55' 0 +C 'ft/t_assert_ctl_arg.vl55n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_55htop.t.cover_observed_deferred_immediate_stmt_55' 1 +C 'ft/t_assert_ctl_arg.vl57n30tuserpagev_user/tocover_simple_immediate_57htop.t.cover_simple_immediate_57' 0 +C 'ft/t_assert_ctl_arg.vl57n35tuserpagev_user/tocover_simple_immediate_stmt_57htop.t.cover_simple_immediate_stmt_57' 0 +C 'ft/t_assert_ctl_arg.vl57n38tuserpagev_user/tocover_final_deferred_immediate_57htop.t.cover_final_deferred_immediate_57' 0 +C 'ft/t_assert_ctl_arg.vl57n41tuserpagev_user/tocover_observed_deferred_immediate_57htop.t.cover_observed_deferred_immediate_57' 0 +C 'ft/t_assert_ctl_arg.vl57n43tuserpagev_user/tocover_final_deferred_immediate_stmt_57htop.t.cover_final_deferred_immediate_stmt_57' 0 +C 'ft/t_assert_ctl_arg.vl57n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_57htop.t.cover_observed_deferred_immediate_stmt_57' 0 +C 'ft/t_assert_ctl_arg.vl62n30tuserpagev_user/tocover_simple_immediate_62htop.t.cover_simple_immediate_62' 0 +C 'ft/t_assert_ctl_arg.vl62n35tuserpagev_user/tocover_simple_immediate_stmt_62htop.t.cover_simple_immediate_stmt_62' 0 +C 'ft/t_assert_ctl_arg.vl62n38tuserpagev_user/tocover_final_deferred_immediate_62htop.t.cover_final_deferred_immediate_62' 1 +C 'ft/t_assert_ctl_arg.vl62n41tuserpagev_user/tocover_observed_deferred_immediate_62htop.t.cover_observed_deferred_immediate_62' 0 +C 'ft/t_assert_ctl_arg.vl62n43tuserpagev_user/tocover_final_deferred_immediate_stmt_62htop.t.cover_final_deferred_immediate_stmt_62' 1 +C 'ft/t_assert_ctl_arg.vl62n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_62htop.t.cover_observed_deferred_immediate_stmt_62' 0 +C 'ft/t_assert_ctl_arg.vl64n30tuserpagev_user/tocover_simple_immediate_64htop.t.cover_simple_immediate_64' 0 +C 'ft/t_assert_ctl_arg.vl64n35tuserpagev_user/tocover_simple_immediate_stmt_64htop.t.cover_simple_immediate_stmt_64' 0 +C 'ft/t_assert_ctl_arg.vl64n38tuserpagev_user/tocover_final_deferred_immediate_64htop.t.cover_final_deferred_immediate_64' 0 +C 'ft/t_assert_ctl_arg.vl64n41tuserpagev_user/tocover_observed_deferred_immediate_64htop.t.cover_observed_deferred_immediate_64' 0 +C 'ft/t_assert_ctl_arg.vl64n43tuserpagev_user/tocover_final_deferred_immediate_stmt_64htop.t.cover_final_deferred_immediate_stmt_64' 0 +C 'ft/t_assert_ctl_arg.vl64n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_64htop.t.cover_observed_deferred_immediate_stmt_64' 0 +C 'ft/t_assert_ctl_arg.vl68n30tuserpagev_user/tocover_simple_immediate_68htop.t.cover_simple_immediate_68' 0 +C 'ft/t_assert_ctl_arg.vl68n35tuserpagev_user/tocover_simple_immediate_stmt_68htop.t.cover_simple_immediate_stmt_68' 0 +C 'ft/t_assert_ctl_arg.vl68n38tuserpagev_user/tocover_final_deferred_immediate_68htop.t.cover_final_deferred_immediate_68' 0 +C 'ft/t_assert_ctl_arg.vl68n41tuserpagev_user/tocover_observed_deferred_immediate_68htop.t.cover_observed_deferred_immediate_68' 0 +C 'ft/t_assert_ctl_arg.vl68n43tuserpagev_user/tocover_final_deferred_immediate_stmt_68htop.t.cover_final_deferred_immediate_stmt_68' 0 +C 'ft/t_assert_ctl_arg.vl68n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_68htop.t.cover_observed_deferred_immediate_stmt_68' 0 +C 'ft/t_assert_ctl_arg.vl70n30tuserpagev_user/tocover_simple_immediate_70htop.t.cover_simple_immediate_70' 1 +C 'ft/t_assert_ctl_arg.vl70n35tuserpagev_user/tocover_simple_immediate_stmt_70htop.t.cover_simple_immediate_stmt_70' 1 +C 'ft/t_assert_ctl_arg.vl70n38tuserpagev_user/tocover_final_deferred_immediate_70htop.t.cover_final_deferred_immediate_70' 1 +C 'ft/t_assert_ctl_arg.vl70n41tuserpagev_user/tocover_observed_deferred_immediate_70htop.t.cover_observed_deferred_immediate_70' 1 +C 'ft/t_assert_ctl_arg.vl70n43tuserpagev_user/tocover_final_deferred_immediate_stmt_70htop.t.cover_final_deferred_immediate_stmt_70' 1 +C 'ft/t_assert_ctl_arg.vl70n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_70htop.t.cover_observed_deferred_immediate_stmt_70' 1 +C 'ft/t_assert_ctl_arg.vl72n30tuserpagev_user/tocover_simple_immediate_72htop.t.cover_simple_immediate_72' 0 +C 'ft/t_assert_ctl_arg.vl72n35tuserpagev_user/tocover_simple_immediate_stmt_72htop.t.cover_simple_immediate_stmt_72' 0 +C 'ft/t_assert_ctl_arg.vl72n38tuserpagev_user/tocover_final_deferred_immediate_72htop.t.cover_final_deferred_immediate_72' 0 +C 'ft/t_assert_ctl_arg.vl72n41tuserpagev_user/tocover_observed_deferred_immediate_72htop.t.cover_observed_deferred_immediate_72' 0 +C 'ft/t_assert_ctl_arg.vl72n43tuserpagev_user/tocover_final_deferred_immediate_stmt_72htop.t.cover_final_deferred_immediate_stmt_72' 0 +C 'ft/t_assert_ctl_arg.vl72n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_72htop.t.cover_observed_deferred_immediate_stmt_72' 0 +C 'ft/t_assert_ctl_arg.vl75n30tuserpagev_user/tocover_simple_immediate_75htop.t.cover_simple_immediate_75' 1 +C 'ft/t_assert_ctl_arg.vl75n35tuserpagev_user/tocover_simple_immediate_stmt_75htop.t.cover_simple_immediate_stmt_75' 1 +C 'ft/t_assert_ctl_arg.vl75n38tuserpagev_user/tocover_final_deferred_immediate_75htop.t.cover_final_deferred_immediate_75' 0 +C 'ft/t_assert_ctl_arg.vl75n41tuserpagev_user/tocover_observed_deferred_immediate_75htop.t.cover_observed_deferred_immediate_75' 1 +C 'ft/t_assert_ctl_arg.vl75n43tuserpagev_user/tocover_final_deferred_immediate_stmt_75htop.t.cover_final_deferred_immediate_stmt_75' 0 +C 'ft/t_assert_ctl_arg.vl75n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_75htop.t.cover_observed_deferred_immediate_stmt_75' 1 +C 'ft/t_assert_ctl_arg.vl77n30tuserpagev_user/tocover_simple_immediate_77htop.t.cover_simple_immediate_77' 1 +C 'ft/t_assert_ctl_arg.vl77n35tuserpagev_user/tocover_simple_immediate_stmt_77htop.t.cover_simple_immediate_stmt_77' 1 +C 'ft/t_assert_ctl_arg.vl77n38tuserpagev_user/tocover_final_deferred_immediate_77htop.t.cover_final_deferred_immediate_77' 1 +C 'ft/t_assert_ctl_arg.vl77n41tuserpagev_user/tocover_observed_deferred_immediate_77htop.t.cover_observed_deferred_immediate_77' 1 +C 'ft/t_assert_ctl_arg.vl77n43tuserpagev_user/tocover_final_deferred_immediate_stmt_77htop.t.cover_final_deferred_immediate_stmt_77' 1 +C 'ft/t_assert_ctl_arg.vl77n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_77htop.t.cover_observed_deferred_immediate_stmt_77' 1 +C 'ft/t_assert_ctl_arg.vl79n30tuserpagev_user/tocover_simple_immediate_79htop.t.cover_simple_immediate_79' 1 +C 'ft/t_assert_ctl_arg.vl79n35tuserpagev_user/tocover_simple_immediate_stmt_79htop.t.cover_simple_immediate_stmt_79' 1 +C 'ft/t_assert_ctl_arg.vl79n38tuserpagev_user/tocover_final_deferred_immediate_79htop.t.cover_final_deferred_immediate_79' 0 +C 'ft/t_assert_ctl_arg.vl79n41tuserpagev_user/tocover_observed_deferred_immediate_79htop.t.cover_observed_deferred_immediate_79' 0 +C 'ft/t_assert_ctl_arg.vl79n43tuserpagev_user/tocover_final_deferred_immediate_stmt_79htop.t.cover_final_deferred_immediate_stmt_79' 0 +C 'ft/t_assert_ctl_arg.vl79n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_79htop.t.cover_observed_deferred_immediate_stmt_79' 0 +C 'ft/t_assert_ctl_arg.vl81n30tuserpagev_user/tocover_simple_immediate_81htop.t.cover_simple_immediate_81' 1 +C 'ft/t_assert_ctl_arg.vl81n35tuserpagev_user/tocover_simple_immediate_stmt_81htop.t.cover_simple_immediate_stmt_81' 1 +C 'ft/t_assert_ctl_arg.vl81n38tuserpagev_user/tocover_final_deferred_immediate_81htop.t.cover_final_deferred_immediate_81' 0 +C 'ft/t_assert_ctl_arg.vl81n41tuserpagev_user/tocover_observed_deferred_immediate_81htop.t.cover_observed_deferred_immediate_81' 0 +C 'ft/t_assert_ctl_arg.vl81n43tuserpagev_user/tocover_final_deferred_immediate_stmt_81htop.t.cover_final_deferred_immediate_stmt_81' 0 +C 'ft/t_assert_ctl_arg.vl81n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_81htop.t.cover_observed_deferred_immediate_stmt_81' 0 +C 'ft/t_assert_ctl_arg.vl83n30tuserpagev_user/tocover_simple_immediate_83htop.t.cover_simple_immediate_83' 0 +C 'ft/t_assert_ctl_arg.vl83n35tuserpagev_user/tocover_simple_immediate_stmt_83htop.t.cover_simple_immediate_stmt_83' 0 +C 'ft/t_assert_ctl_arg.vl83n38tuserpagev_user/tocover_final_deferred_immediate_83htop.t.cover_final_deferred_immediate_83' 0 +C 'ft/t_assert_ctl_arg.vl83n41tuserpagev_user/tocover_observed_deferred_immediate_83htop.t.cover_observed_deferred_immediate_83' 0 +C 'ft/t_assert_ctl_arg.vl83n43tuserpagev_user/tocover_final_deferred_immediate_stmt_83htop.t.cover_final_deferred_immediate_stmt_83' 0 +C 'ft/t_assert_ctl_arg.vl83n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_83htop.t.cover_observed_deferred_immediate_stmt_83' 0 +C 'ft/t_assert_ctl_arg.vl85n30tuserpagev_user/tocover_simple_immediate_85htop.t.cover_simple_immediate_85' 1 +C 'ft/t_assert_ctl_arg.vl85n35tuserpagev_user/tocover_simple_immediate_stmt_85htop.t.cover_simple_immediate_stmt_85' 1 +C 'ft/t_assert_ctl_arg.vl85n38tuserpagev_user/tocover_final_deferred_immediate_85htop.t.cover_final_deferred_immediate_85' 0 +C 'ft/t_assert_ctl_arg.vl85n41tuserpagev_user/tocover_observed_deferred_immediate_85htop.t.cover_observed_deferred_immediate_85' 0 +C 'ft/t_assert_ctl_arg.vl85n43tuserpagev_user/tocover_final_deferred_immediate_stmt_85htop.t.cover_final_deferred_immediate_stmt_85' 0 +C 'ft/t_assert_ctl_arg.vl85n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_85htop.t.cover_observed_deferred_immediate_stmt_85' 0 +C 'ft/t_assert_ctl_arg.vl87n30tuserpagev_user/tocover_simple_immediate_87htop.t.cover_simple_immediate_87' 0 +C 'ft/t_assert_ctl_arg.vl87n35tuserpagev_user/tocover_simple_immediate_stmt_87htop.t.cover_simple_immediate_stmt_87' 0 +C 'ft/t_assert_ctl_arg.vl87n38tuserpagev_user/tocover_final_deferred_immediate_87htop.t.cover_final_deferred_immediate_87' 0 +C 'ft/t_assert_ctl_arg.vl87n41tuserpagev_user/tocover_observed_deferred_immediate_87htop.t.cover_observed_deferred_immediate_87' 0 +C 'ft/t_assert_ctl_arg.vl87n43tuserpagev_user/tocover_final_deferred_immediate_stmt_87htop.t.cover_final_deferred_immediate_stmt_87' 0 +C 'ft/t_assert_ctl_arg.vl87n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_87htop.t.cover_observed_deferred_immediate_stmt_87' 0 +C 'ft/t_assert_ctl_arg.vl89n30tuserpagev_user/tocover_simple_immediate_89htop.t.cover_simple_immediate_89' 1 +C 'ft/t_assert_ctl_arg.vl89n35tuserpagev_user/tocover_simple_immediate_stmt_89htop.t.cover_simple_immediate_stmt_89' 1 +C 'ft/t_assert_ctl_arg.vl89n38tuserpagev_user/tocover_final_deferred_immediate_89htop.t.cover_final_deferred_immediate_89' 1 +C 'ft/t_assert_ctl_arg.vl89n41tuserpagev_user/tocover_observed_deferred_immediate_89htop.t.cover_observed_deferred_immediate_89' 1 +C 'ft/t_assert_ctl_arg.vl89n43tuserpagev_user/tocover_final_deferred_immediate_stmt_89htop.t.cover_final_deferred_immediate_stmt_89' 1 +C 'ft/t_assert_ctl_arg.vl89n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_89htop.t.cover_observed_deferred_immediate_stmt_89' 1 +C 'ft/t_assert_ctl_arg.vl91n30tuserpagev_user/tocover_simple_immediate_91htop.t.cover_simple_immediate_91' 0 +C 'ft/t_assert_ctl_arg.vl91n35tuserpagev_user/tocover_simple_immediate_stmt_91htop.t.cover_simple_immediate_stmt_91' 0 +C 'ft/t_assert_ctl_arg.vl91n38tuserpagev_user/tocover_final_deferred_immediate_91htop.t.cover_final_deferred_immediate_91' 0 +C 'ft/t_assert_ctl_arg.vl91n41tuserpagev_user/tocover_observed_deferred_immediate_91htop.t.cover_observed_deferred_immediate_91' 0 +C 'ft/t_assert_ctl_arg.vl91n43tuserpagev_user/tocover_final_deferred_immediate_stmt_91htop.t.cover_final_deferred_immediate_stmt_91' 0 +C 'ft/t_assert_ctl_arg.vl91n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_91htop.t.cover_observed_deferred_immediate_stmt_91' 0 +C 'ft/t_assert_ctl_arg.vl96n30tuserpagev_user/tocover_simple_immediate_96htop.t.cover_simple_immediate_96' 0 +C 'ft/t_assert_ctl_arg.vl96n35tuserpagev_user/tocover_simple_immediate_stmt_96htop.t.cover_simple_immediate_stmt_96' 0 +C 'ft/t_assert_ctl_arg.vl96n38tuserpagev_user/tocover_final_deferred_immediate_96htop.t.cover_final_deferred_immediate_96' 0 +C 'ft/t_assert_ctl_arg.vl96n41tuserpagev_user/tocover_observed_deferred_immediate_96htop.t.cover_observed_deferred_immediate_96' 0 +C 'ft/t_assert_ctl_arg.vl96n43tuserpagev_user/tocover_final_deferred_immediate_stmt_96htop.t.cover_final_deferred_immediate_stmt_96' 0 +C 'ft/t_assert_ctl_arg.vl96n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_96htop.t.cover_observed_deferred_immediate_stmt_96' 0 +C 'ft/t_assert_ctl_arg.vl99n30tuserpagev_user/tocover_simple_immediate_99htop.t.cover_simple_immediate_99' 1 +C 'ft/t_assert_ctl_arg.vl99n35tuserpagev_user/tocover_simple_immediate_stmt_99htop.t.cover_simple_immediate_stmt_99' 1 +C 'ft/t_assert_ctl_arg.vl99n38tuserpagev_user/tocover_final_deferred_immediate_99htop.t.cover_final_deferred_immediate_99' 1 +C 'ft/t_assert_ctl_arg.vl99n41tuserpagev_user/tocover_observed_deferred_immediate_99htop.t.cover_observed_deferred_immediate_99' 1 +C 'ft/t_assert_ctl_arg.vl99n43tuserpagev_user/tocover_final_deferred_immediate_stmt_99htop.t.cover_final_deferred_immediate_stmt_99' 1 +C 'ft/t_assert_ctl_arg.vl99n46tuserpagev_user/tocover_observed_deferred_immediate_stmt_99htop.t.cover_observed_deferred_immediate_stmt_99' 1 diff --git a/test_regress/t/t_assert_ctl_arg.out b/test_regress/t/t_assert_ctl_arg.out index 61360e55d..dcd7751d8 100644 --- a/test_regress/t/t_assert_ctl_arg.out +++ b/test_regress/t/t_assert_ctl_arg.out @@ -1,416 +1,416 @@ ========== -Running all asserts at: t/t_assert_ctl_arg.v:49 +Running all asserts at: t/t_assert_ctl_arg.v:48 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:49 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. --Info: t/t_assert_ctl_arg.v:137: Verilog $stop, ignored due to +verilator+error+limit -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:49 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:49 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:49 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:49 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:49 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:49 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:49 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:49 -Passed 'top.t.cover_simple_immediate_stmt_49' at t/t_assert_ctl_arg.v:49 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:48 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +-Info: t/t_assert_ctl_arg.v:136: Verilog $stop, ignored due to +verilator+error+limit +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:48 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:48 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:48 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:48 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:48 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:48 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:48 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:48 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:48 +Passed 'top.t.cover_simple_immediate_stmt_48' at t/t_assert_ctl_arg.v:48 ========== -Running all asserts at: t/t_assert_ctl_arg.v:51 +Running all asserts at: t/t_assert_ctl_arg.v:50 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:51 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:51 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:51 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:51 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:51 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:51 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:50 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:50 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:50 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:50 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:50 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:50 ========== -Running all asserts at: t/t_assert_ctl_arg.v:56 +Running all asserts at: t/t_assert_ctl_arg.v:55 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:56 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:56 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:56 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:56 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:56 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:56 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:56 -Passed 'top.t.cover_observed_deferred_immediate_stmt_56' at t/t_assert_ctl_arg.v:56 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:55 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:55 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:55 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:55 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:55 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:55 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:55 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:55 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:55 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:55 +Passed 'top.t.cover_observed_deferred_immediate_stmt_55' at t/t_assert_ctl_arg.v:55 ========== -Running all asserts at: t/t_assert_ctl_arg.v:58 +Running all asserts at: t/t_assert_ctl_arg.v:57 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:58 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:58 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:58 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:58 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:58 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:58 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:57 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:57 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:57 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:57 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:57 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:57 ========== -Running all asserts at: t/t_assert_ctl_arg.v:63 +Running all asserts at: t/t_assert_ctl_arg.v:62 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:63 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:63 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:63 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:63 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:63 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:63 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:63 -Passed 'top.t.cover_final_deferred_immediate_stmt_63' at t/t_assert_ctl_arg.v:63 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:62 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:62 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:62 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:62 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:62 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:62 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:62 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:62 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:62 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:62 +Passed 'top.t.cover_final_deferred_immediate_stmt_62' at t/t_assert_ctl_arg.v:62 ========== -Running all asserts at: t/t_assert_ctl_arg.v:65 +Running all asserts at: t/t_assert_ctl_arg.v:64 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:65 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:65 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:65 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:65 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:65 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:65 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:64 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:64 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:64 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:64 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:64 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:64 ========== -Running all asserts at: t/t_assert_ctl_arg.v:69 +Running all asserts at: t/t_assert_ctl_arg.v:68 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:69 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:69 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:69 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:69 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:69 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:69 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:68 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:68 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:68 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:68 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:68 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:68 ========== -Running all asserts at: t/t_assert_ctl_arg.v:71 +Running all asserts at: t/t_assert_ctl_arg.v:70 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:71 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:71 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:71 -Passed 'top.t.cover_simple_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 -Passed 'top.t.cover_observed_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 -Passed 'top.t.cover_final_deferred_immediate_stmt_71' at t/t_assert_ctl_arg.v:71 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:70 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:70 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:70 +Passed 'top.t.cover_simple_immediate_stmt_70' at t/t_assert_ctl_arg.v:70 +Passed 'top.t.cover_observed_deferred_immediate_stmt_70' at t/t_assert_ctl_arg.v:70 +Passed 'top.t.cover_final_deferred_immediate_stmt_70' at t/t_assert_ctl_arg.v:70 ========== -Running all asserts at: t/t_assert_ctl_arg.v:73 +Running all asserts at: t/t_assert_ctl_arg.v:72 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:73 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:73 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:73 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:73 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:73 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:73 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:72 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:72 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:72 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:72 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:72 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:72 ========== -Running all asserts at: t/t_assert_ctl_arg.v:76 +Running all asserts at: t/t_assert_ctl_arg.v:75 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:76 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:76 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:76 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:76 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:76 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:76 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:76 -Passed 'top.t.cover_simple_immediate_stmt_76' at t/t_assert_ctl_arg.v:76 -Passed 'top.t.cover_observed_deferred_immediate_stmt_76' at t/t_assert_ctl_arg.v:76 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:75 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:75 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:75 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:75 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:75 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:75 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:75 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:75 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:75 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:75 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:75 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:75 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:75 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:75 +Passed 'top.t.cover_simple_immediate_stmt_75' at t/t_assert_ctl_arg.v:75 +Passed 'top.t.cover_observed_deferred_immediate_stmt_75' at t/t_assert_ctl_arg.v:75 ========== -Running all asserts at: t/t_assert_ctl_arg.v:78 +Running all asserts at: t/t_assert_ctl_arg.v:77 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:78 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:78 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:78 -Passed 'top.t.cover_simple_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 -Passed 'top.t.cover_observed_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 -Passed 'top.t.cover_final_deferred_immediate_stmt_78' at t/t_assert_ctl_arg.v:78 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:77 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:77 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:77 +Passed 'top.t.cover_simple_immediate_stmt_77' at t/t_assert_ctl_arg.v:77 +Passed 'top.t.cover_observed_deferred_immediate_stmt_77' at t/t_assert_ctl_arg.v:77 +Passed 'top.t.cover_final_deferred_immediate_stmt_77' at t/t_assert_ctl_arg.v:77 ========== -Running all asserts at: t/t_assert_ctl_arg.v:80 +Running all asserts at: t/t_assert_ctl_arg.v:79 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:80 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:80 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:80 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:80 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:80 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:80 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:80 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:80 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:80 -Passed 'top.t.cover_simple_immediate_stmt_80' at t/t_assert_ctl_arg.v:80 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:79 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:79 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:79 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:79 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:79 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:79 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:79 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:79 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:79 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:79 +Passed 'top.t.cover_simple_immediate_stmt_79' at t/t_assert_ctl_arg.v:79 ========== -Running all asserts at: t/t_assert_ctl_arg.v:82 +Running all asserts at: t/t_assert_ctl_arg.v:81 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:82 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:82 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:82 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:82 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:82 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:82 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:82 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:82 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:82 -Passed 'top.t.cover_simple_immediate_stmt_82' at t/t_assert_ctl_arg.v:82 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:81 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:81 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:81 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:81 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:81 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:81 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:81 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:81 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:81 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:81 +Passed 'top.t.cover_simple_immediate_stmt_81' at t/t_assert_ctl_arg.v:81 ========== -Running all asserts at: t/t_assert_ctl_arg.v:84 +Running all asserts at: t/t_assert_ctl_arg.v:83 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:84 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:84 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:84 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:84 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:84 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:84 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:83 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:83 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:83 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:83 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:83 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:83 ========== -Running all asserts at: t/t_assert_ctl_arg.v:86 +Running all asserts at: t/t_assert_ctl_arg.v:85 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:86 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:86 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:86 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:86 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:86 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:86 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:86 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:86 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:86 -Passed 'top.t.cover_simple_immediate_stmt_86' at t/t_assert_ctl_arg.v:86 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:85 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:85 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:85 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:85 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:85 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:85 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:85 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:85 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:85 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:85 +Passed 'top.t.cover_simple_immediate_stmt_85' at t/t_assert_ctl_arg.v:85 ========== -Running all asserts at: t/t_assert_ctl_arg.v:88 +Running all asserts at: t/t_assert_ctl_arg.v:87 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:88 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:88 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:88 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:88 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:88 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:88 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:87 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:87 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:87 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:87 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:87 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:87 ========== -Running all asserts at: t/t_assert_ctl_arg.v:90 +Running all asserts at: t/t_assert_ctl_arg.v:89 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:90 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:90 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:90 -Passed 'top.t.cover_simple_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 -Passed 'top.t.cover_observed_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 -Passed 'top.t.cover_final_deferred_immediate_stmt_90' at t/t_assert_ctl_arg.v:90 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:89 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:89 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:89 +Passed 'top.t.cover_simple_immediate_stmt_89' at t/t_assert_ctl_arg.v:89 +Passed 'top.t.cover_observed_deferred_immediate_stmt_89' at t/t_assert_ctl_arg.v:89 +Passed 'top.t.cover_final_deferred_immediate_stmt_89' at t/t_assert_ctl_arg.v:89 ========== -Running all asserts at: t/t_assert_ctl_arg.v:92 +Running all asserts at: t/t_assert_ctl_arg.v:91 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:92 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:92 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:92 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:92 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:92 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:92 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:91 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:91 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:91 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:91 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:91 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:91 ========== -Running all asserts at: t/t_assert_ctl_arg.v:97 +Running all asserts at: t/t_assert_ctl_arg.v:96 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:97 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:97 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:97 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:97 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:97 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:97 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:97 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:97 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:96 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:96 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:96 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:96 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:96 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:96 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:96 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:96 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:96 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:96 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:96 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:96 ========== -Running all asserts at: t/t_assert_ctl_arg.v:100 +Running all asserts at: t/t_assert_ctl_arg.v:99 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:100 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:100 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:100 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:100 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:100 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:100 -Passed 'top.t.cover_simple_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 -Passed 'top.t.cover_observed_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 -Passed 'top.t.cover_final_deferred_immediate_stmt_100' at t/t_assert_ctl_arg.v:100 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:99 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:99 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:99 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:99 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:99 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:99 +Passed 'top.t.cover_simple_immediate_stmt_99' at t/t_assert_ctl_arg.v:99 +Passed 'top.t.cover_observed_deferred_immediate_stmt_99' at t/t_assert_ctl_arg.v:99 +Passed 'top.t.cover_final_deferred_immediate_stmt_99' at t/t_assert_ctl_arg.v:99 ========== -Running all asserts at: t/t_assert_ctl_arg.v:103 +Running all asserts at: t/t_assert_ctl_arg.v:102 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:103 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:103 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:103 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:103 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:103 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:103 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:103 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:103 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:102 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:102 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:102 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:102 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:102 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:102 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:102 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:102 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:102 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:102 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:102 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:102 ========== -Running all asserts at: t/t_assert_ctl_arg.v:106 +Running all asserts at: t/t_assert_ctl_arg.v:105 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:106 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:106 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:106 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:106 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:106 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:106 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:106 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:106 -Passed 'top.t.cover_simple_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 -Passed 'top.t.cover_observed_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 -Passed 'top.t.cover_final_deferred_immediate_stmt_106' at t/t_assert_ctl_arg.v:106 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:105 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:105 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:105 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:105 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:105 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:105 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:105 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:105 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:105 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:105 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:105 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:105 +Passed 'top.t.cover_simple_immediate_stmt_105' at t/t_assert_ctl_arg.v:105 +Passed 'top.t.cover_observed_deferred_immediate_stmt_105' at t/t_assert_ctl_arg.v:105 +Passed 'top.t.cover_final_deferred_immediate_stmt_105' at t/t_assert_ctl_arg.v:105 ========== -Running all asserts at: t/t_assert_ctl_arg.v:108 +Running all asserts at: t/t_assert_ctl_arg.v:107 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:137: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:151: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:157: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:165: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:108 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:108 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:108 -Passed 'top.t.cover_simple_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 -Passed 'top.t.cover_observed_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 -Passed 'top.t.cover_final_deferred_immediate_stmt_108' at t/t_assert_ctl_arg.v:108 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:136: Assertion failed in top.$unit.run_simple_immediate.assert_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_simple_immediate.assert_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:150: Assertion failed in top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_observed_deferred_immediate.assert_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:156: Assertion failed in top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_observed_deferred_immediate.assume_observed_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:164: Assertion failed in top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_final_deferred_immediate.assert_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:107 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:107 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:107 +Passed 'top.t.cover_simple_immediate_stmt_107' at t/t_assert_ctl_arg.v:107 +Passed 'top.t.cover_observed_deferred_immediate_stmt_107' at t/t_assert_ctl_arg.v:107 +Passed 'top.t.cover_final_deferred_immediate_stmt_107' at t/t_assert_ctl_arg.v:107 ========== -Running all asserts at: t/t_assert_ctl_arg.v:110 +Running all asserts at: t/t_assert_ctl_arg.v:109 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:110 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:110 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:110 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:110 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:110 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:110 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:109 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:109 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:109 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:109 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:109 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:109 ========== -Running all asserts at: t/t_assert_ctl_arg.v:112 +Running all asserts at: t/t_assert_ctl_arg.v:111 ========== -Testing assert_simple_immediate at t/t_assert_ctl_arg.v:112 -Testing assume_simple_immediate at t/t_assert_ctl_arg.v:112 -[0] %Error: t_assert_ctl_arg.v:143: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:112 -Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 -Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 -Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:112 -Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:112 -Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:112 -[0] %Error: t_assert_ctl_arg.v:171: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:112 -Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:112 -Passed 'top.t.cover_simple_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 -Passed 'top.t.cover_final_deferred_immediate_stmt_112' at t/t_assert_ctl_arg.v:112 +Testing assert_simple_immediate at t/t_assert_ctl_arg.v:111 +Testing assume_simple_immediate at t/t_assert_ctl_arg.v:111 +[0] %Error: t_assert_ctl_arg.v:142: Assertion failed in top.$unit.run_simple_immediate.assume_simple_immediate: 'assert' failed. +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_else' at t/t_assert_ctl_arg.v:111 +Failed 'top.$unit.run_simple_immediate.assume_simple_immediate_stmt_else' at t/t_assert_ctl_arg.v:111 +Testing assert_observed_deferred_immediate at t/t_assert_ctl_arg.v:111 +Testing assume_observed_deferred_immediate at t/t_assert_ctl_arg.v:111 +Testing assert_final_deferred_immediate at t/t_assert_ctl_arg.v:111 +Testing assume_final_deferred_immediate at t/t_assert_ctl_arg.v:111 +[0] %Error: t_assert_ctl_arg.v:170: Assertion failed in top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate: 'assert' failed. +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_else' at t/t_assert_ctl_arg.v:111 +Failed 'top.$unit.run_final_deferred_immediate.assume_final_deferred_immediate_stmt_else' at t/t_assert_ctl_arg.v:111 +Passed 'top.t.cover_simple_immediate_stmt_111' at t/t_assert_ctl_arg.v:111 +Passed 'top.t.cover_final_deferred_immediate_stmt_111' at t/t_assert_ctl_arg.v:111 Disabling concurrent asserts, time: 10 Enabling concurrent asserts, time: 20 *-* All Finished *-* -[20] %Error: t_assert_ctl_arg.v:182: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed. -Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:183 -Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:185 -[20] %Error: t_assert_ctl_arg.v:187: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed. -Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:188 -Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:190 +[20] %Error: t_assert_ctl_arg.v:181: Assertion failed in top.t.concurrent.assert_concurrent: 'assert' failed. +Failed 'top.t.concurrent.assert_concurrent_else' at t/t_assert_ctl_arg.v:182 +Failed 'top.t.concurrent.assert_concurrent_stmt_else' at t/t_assert_ctl_arg.v:184 +[20] %Error: t_assert_ctl_arg.v:186: Assertion failed in top.t.concurrent.assume_concurrent: 'assert' failed. +Failed 'top.t.concurrent.assume_concurrent_else' at t/t_assert_ctl_arg.v:187 +Failed 'top.t.concurrent.assume_concurrent_stmt_else' at t/t_assert_ctl_arg.v:189 diff --git a/test_regress/t/t_assert_ctl_arg.v b/test_regress/t/t_assert_ctl_arg.v index 5f11b2889..db8814fd5 100644 --- a/test_regress/t/t_assert_ctl_arg.v +++ b/test_regress/t/t_assert_ctl_arg.v @@ -5,190 +5,189 @@ // SPDX-License-Identifier: CC0-1.0 `define DISPLAY_PASS(file, line) \ - $display("Passed '%m' at %s:%g", file, line) + $display("Passed '%m' at %s:%g", file, line) `define DISPLAY_FAIL(file, line) \ - $display("Failed '%m' at %s:%g", file, line) + $display("Failed '%m' at %s:%g", file, line) `define RUN_ALL_ASSERTS \ - $display("==========\nRunning all asserts at: %s:%g\n==========", `__FILE__, `__LINE__); \ - run_all_asserts(`__FILE__, `__LINE__); \ - cover_simple_immediate_`__LINE__: cover(1); \ - cover_simple_immediate_stmt_`__LINE__: cover(1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ - cover_observed_deferred_immediate_`__LINE__: cover #0 (1); \ - cover_observed_deferred_immediate_stmt_`__LINE__: cover #0 (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ - cover_final_deferred_immediate_`__LINE__: cover final (1); \ - cover_final_deferred_immediate_stmt_`__LINE__: cover final (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ + $display("==========\nRunning all asserts at: %s:%g\n==========", `__FILE__, `__LINE__); \ + run_all_asserts(`__FILE__, `__LINE__); \ + cover_simple_immediate_`__LINE__: cover(1); \ + cover_simple_immediate_stmt_`__LINE__: cover(1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ + cover_observed_deferred_immediate_`__LINE__: cover #0 (1); \ + cover_observed_deferred_immediate_stmt_`__LINE__: cover #0 (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ + cover_final_deferred_immediate_`__LINE__: cover final (1); \ + cover_final_deferred_immediate_stmt_`__LINE__: cover final (1) `DISPLAY_PASS(`__FILE__, `__LINE__); \ -module t (/*AUTOARG*/ - clk - ); - input clk; +module t ( + input clk +); - let On = 3; - let Off = 4; - let Kill = 5; + let On = 3; + let Off = 4; + let Kill = 5; - let CONCURRENT = 1; - let SIMPLE_IMMEDIATE = 2; - let OBSERVED_DEFERRED_IMMEDIATE = 4; - let FINAL_DEFERRED_IMMEDIATE = 8; + let CONCURRENT = 1; + let SIMPLE_IMMEDIATE = 2; + let OBSERVED_DEFERRED_IMMEDIATE = 4; + let FINAL_DEFERRED_IMMEDIATE = 8; - let ALL_TYPES = CONCURRENT|SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE; + let ALL_TYPES = CONCURRENT|SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE; - let ASSERT = 1; - let COVER = 2; - let ASSUME = 4; + let ASSERT = 1; + let COVER = 2; + let ASSUME = 4; - concurrent concurrent(.clk(clk)); + concurrent concurrent(.clk(clk)); - initial begin - // simple immediate - $assertcontrol(Off, ALL_TYPES); - $assertcontrol(On, SIMPLE_IMMEDIATE); - `RUN_ALL_ASSERTS - $assertcontrol(Off, SIMPLE_IMMEDIATE); - `RUN_ALL_ASSERTS + initial begin + // simple immediate + $assertcontrol(Off, ALL_TYPES); + $assertcontrol(On, SIMPLE_IMMEDIATE); + `RUN_ALL_ASSERTS + $assertcontrol(Off, SIMPLE_IMMEDIATE); + `RUN_ALL_ASSERTS - // observed deferred immediate - $assertcontrol(Off, ALL_TYPES); - $assertcontrol(On, OBSERVED_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS - $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS + // observed deferred immediate + $assertcontrol(Off, ALL_TYPES); + $assertcontrol(On, OBSERVED_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS + $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS - // final deferred immediate - $assertcontrol(Off, ALL_TYPES); - $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS - $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS + // final deferred immediate + $assertcontrol(Off, ALL_TYPES); + $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS + $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS - // on, off, kill test - $assertoff; - `RUN_ALL_ASSERTS; - $asserton; - `RUN_ALL_ASSERTS; - $assertkill; - `RUN_ALL_ASSERTS; + // on, off, kill test + $assertoff; + `RUN_ALL_ASSERTS; + $asserton; + `RUN_ALL_ASSERTS; + $assertkill; + `RUN_ALL_ASSERTS; - $assertcontrol(On, SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, SIMPLE_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(On, SIMPLE_IMMEDIATE); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, ALL_TYPES); - `RUN_ALL_ASSERTS; - $assertcontrol(On, ALL_TYPES); - `RUN_ALL_ASSERTS; - $assertcontrol(Kill, ALL_TYPES); - `RUN_ALL_ASSERTS; + $assertcontrol(On, SIMPLE_IMMEDIATE|OBSERVED_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(On, FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, OBSERVED_DEFERRED_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, FINAL_DEFERRED_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, SIMPLE_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(On, SIMPLE_IMMEDIATE); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, ALL_TYPES); + `RUN_ALL_ASSERTS; + $assertcontrol(On, ALL_TYPES); + `RUN_ALL_ASSERTS; + $assertcontrol(Kill, ALL_TYPES); + `RUN_ALL_ASSERTS; - // directive_type test - $assertoff; - $assertcontrol(On, ALL_TYPES, ASSERT); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, ALL_TYPES, ASSERT); - $assertcontrol(On, ALL_TYPES, COVER); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, ALL_TYPES, COVER); - $assertcontrol(On, ALL_TYPES, ASSUME); - `RUN_ALL_ASSERTS; - $assertcontrol(Off, ALL_TYPES, ASSUME); - $assertcontrol(On, ALL_TYPES, ASSERT|COVER); - `RUN_ALL_ASSERTS; - $assertcontrol(On, ALL_TYPES, ASSUME); - `RUN_ALL_ASSERTS; - $assertoff; - `RUN_ALL_ASSERTS; - $assertcontrol(On, SIMPLE_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE, COVER|ASSUME); - `RUN_ALL_ASSERTS; - $assertoff; + // directive_type test + $assertoff; + $assertcontrol(On, ALL_TYPES, ASSERT); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, ALL_TYPES, ASSERT); + $assertcontrol(On, ALL_TYPES, COVER); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, ALL_TYPES, COVER); + $assertcontrol(On, ALL_TYPES, ASSUME); + `RUN_ALL_ASSERTS; + $assertcontrol(Off, ALL_TYPES, ASSUME); + $assertcontrol(On, ALL_TYPES, ASSERT|COVER); + `RUN_ALL_ASSERTS; + $assertcontrol(On, ALL_TYPES, ASSUME); + `RUN_ALL_ASSERTS; + $assertoff; + `RUN_ALL_ASSERTS; + $assertcontrol(On, SIMPLE_IMMEDIATE|FINAL_DEFERRED_IMMEDIATE, COVER|ASSUME); + `RUN_ALL_ASSERTS; + $assertoff; - // concurrent test - #10; - $display("Disabling concurrent asserts, time: %g", $time); - $assertcontrol(On, ALL_TYPES); - $assertcontrol(Off, CONCURRENT); - #10; - $display("Enabling concurrent asserts, time: %g", $time); - $assertcontrol(On, CONCURRENT); + // concurrent test + #10; + $display("Disabling concurrent asserts, time: %g", $time); + $assertcontrol(On, ALL_TYPES); + $assertcontrol(Off, CONCURRENT); + #10; + $display("Enabling concurrent asserts, time: %g", $time); + $assertcontrol(On, CONCURRENT); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule task run_all_asserts(string file, integer line); - run_simple_immediate(file, line); - run_observed_deferred_immediate(file, line); - run_final_deferred_immediate(file, line); + run_simple_immediate(file, line); + run_observed_deferred_immediate(file, line); + run_final_deferred_immediate(file, line); endtask task run_simple_immediate(string file, integer line); - $display("Testing assert_simple_immediate at %s:%g", file, line); - assert_simple_immediate: assert(0); - assert_simple_immediate_else: assert(0) else `DISPLAY_FAIL(file, line); - assert_simple_immediate_stmt: assert(0) `DISPLAY_PASS(file, line); - assert_simple_immediate_stmt_else: assert(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assert_simple_immediate at %s:%g", file, line); + assert_simple_immediate: assert(0); + assert_simple_immediate_else: assert(0) else `DISPLAY_FAIL(file, line); + assert_simple_immediate_stmt: assert(0) `DISPLAY_PASS(file, line); + assert_simple_immediate_stmt_else: assert(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); - $display("Testing assume_simple_immediate at %s:%g", file, line); - assume_simple_immediate: assume(0); - assume_simple_immediate_else: assume(0) else `DISPLAY_FAIL(file, line); - assume_simple_immediate_stmt: assume(0) `DISPLAY_PASS(file, line); - assume_simple_immediate_stmt_else: assume(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assume_simple_immediate at %s:%g", file, line); + assume_simple_immediate: assume(0); + assume_simple_immediate_else: assume(0) else `DISPLAY_FAIL(file, line); + assume_simple_immediate_stmt: assume(0) `DISPLAY_PASS(file, line); + assume_simple_immediate_stmt_else: assume(0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); endtask task run_observed_deferred_immediate(string file, integer line); - $display("Testing assert_observed_deferred_immediate at %s:%g", file, line); - assert_observed_deferred_immediate: assert #0 (0); - assert_observed_deferred_immediate_else: assert #0 (0) else `DISPLAY_FAIL(file, line); - assert_observed_deferred_immediate_stmt: assert #0 (0) `DISPLAY_PASS(file, line); - assert_observed_deferred_immediate_stmt_else: assert #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assert_observed_deferred_immediate at %s:%g", file, line); + assert_observed_deferred_immediate: assert #0 (0); + assert_observed_deferred_immediate_else: assert #0 (0) else `DISPLAY_FAIL(file, line); + assert_observed_deferred_immediate_stmt: assert #0 (0) `DISPLAY_PASS(file, line); + assert_observed_deferred_immediate_stmt_else: assert #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); - $display("Testing assume_observed_deferred_immediate at %s:%g", file, line); - assume_observed_deferred_immediate: assume #0 (0); - assume_observed_deferred_immediate_else: assume #0 (0) else `DISPLAY_FAIL(file, line); - assume_observed_deferred_immediate_stmt: assume #0 (0) `DISPLAY_PASS(file, line); - assume_observed_deferred_immediate_stmt_else: assume #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assume_observed_deferred_immediate at %s:%g", file, line); + assume_observed_deferred_immediate: assume #0 (0); + assume_observed_deferred_immediate_else: assume #0 (0) else `DISPLAY_FAIL(file, line); + assume_observed_deferred_immediate_stmt: assume #0 (0) `DISPLAY_PASS(file, line); + assume_observed_deferred_immediate_stmt_else: assume #0 (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); endtask task run_final_deferred_immediate(string file, integer line); - $display("Testing assert_final_deferred_immediate at %s:%g", file, line); - assert_final_deferred_immediate: assert final (0); - assert_final_deferred_immediate_else: assert final (0) else `DISPLAY_FAIL(file, line); - assert_final_deferred_immediate_stmt: assert final (0) `DISPLAY_PASS(file, line); - assert_final_deferred_immediate_stmt_else: assert final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assert_final_deferred_immediate at %s:%g", file, line); + assert_final_deferred_immediate: assert final (0); + assert_final_deferred_immediate_else: assert final (0) else `DISPLAY_FAIL(file, line); + assert_final_deferred_immediate_stmt: assert final (0) `DISPLAY_PASS(file, line); + assert_final_deferred_immediate_stmt_else: assert final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); - $display("Testing assume_final_deferred_immediate at %s:%g", file, line); - assume_final_deferred_immediate: assume final (0); - assume_final_deferred_immediate_else: assume final (0) else `DISPLAY_FAIL(file, line); - assume_final_deferred_immediate_stmt: assume final (0) `DISPLAY_PASS(file, line); - assume_final_deferred_immediate_stmt_else: assume final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); + $display("Testing assume_final_deferred_immediate at %s:%g", file, line); + assume_final_deferred_immediate: assume final (0); + assume_final_deferred_immediate_else: assume final (0) else `DISPLAY_FAIL(file, line); + assume_final_deferred_immediate_stmt: assume final (0) `DISPLAY_PASS(file, line); + assume_final_deferred_immediate_stmt_else: assume final (0) `DISPLAY_PASS(file, line); else `DISPLAY_FAIL(file, line); endtask module concurrent(input clk); - property prop(); - @(posedge clk) 0 - endproperty + property prop(); + @(posedge clk) 0 + endproperty - assert_concurrent: assert property (prop); - assert_concurrent_else: assert property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); - assert_concurrent_stmt: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); - assert_concurrent_stmt_else: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); + assert_concurrent: assert property (prop); + assert_concurrent_else: assert property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); + assert_concurrent_stmt: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); + assert_concurrent_stmt_else: assert property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); - assume_concurrent: assume property(prop); - assume_concurrent_else: assume property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); - assume_concurrent_stmt: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); - assume_concurrent_stmt_else: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); + assume_concurrent: assume property(prop); + assume_concurrent_else: assume property(prop) else `DISPLAY_FAIL(`__FILE__, `__LINE__); + assume_concurrent_stmt: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); + assume_concurrent_stmt_else: assume property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); else `DISPLAY_FAIL(`__FILE__, `__LINE__); - cover_concurrent: cover property(prop); - cover_concurrent_stmt: cover property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); + cover_concurrent: cover property(prop); + cover_concurrent_stmt: cover property(prop) `DISPLAY_PASS(`__FILE__, `__LINE__); endmodule diff --git a/test_regress/t/t_assert_ctl_arg_unsup.out b/test_regress/t/t_assert_ctl_arg_unsup.out index 863f8394b..c9bad92c3 100644 --- a/test_regress/t/t_assert_ctl_arg_unsup.out +++ b/test_regress/t/t_assert_ctl_arg_unsup.out @@ -1,18 +1,18 @@ -%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:15:7: Unsupported: assert control assertion_type +%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:15:5: Unsupported: assert control assertion_type : ... note: In instance 't' - 15 | $assertcontrol(OFF, EXPECT); - | ^~~~~~~~~~~~~~ + 15 | $assertcontrol(OFF, EXPECT); + | ^~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:16:7: Unsupported: assert control assertion_type +%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:16:5: Unsupported: assert control assertion_type : ... note: In instance 't' - 16 | $assertcontrol(OFF, UNIQUE); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:17:7: Unsupported: assert control assertion_type + 16 | $assertcontrol(OFF, UNIQUE); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:17:5: Unsupported: assert control assertion_type : ... note: In instance 't' - 17 | $assertcontrol(OFF, UNIQUE0); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:18:7: Unsupported: assert control assertion_type + 17 | $assertcontrol(OFF, UNIQUE0); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_arg_unsup.v:18:5: Unsupported: assert control assertion_type : ... note: In instance 't' - 18 | $assertcontrol(OFF, PRIORITY); - | ^~~~~~~~~~~~~~ + 18 | $assertcontrol(OFF, PRIORITY); + | ^~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_ctl_arg_unsup.v b/test_regress/t/t_assert_ctl_arg_unsup.v index e998de28e..b041652f2 100644 --- a/test_regress/t/t_assert_ctl_arg_unsup.v +++ b/test_regress/t/t_assert_ctl_arg_unsup.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 module t; - let OFF = 4; - let EXPECT = 16; - let UNIQUE = 32; - let UNIQUE0 = 64; - let PRIORITY = 128; + let OFF = 4; + let EXPECT = 16; + let UNIQUE = 32; + let UNIQUE0 = 64; + let PRIORITY = 128; - initial begin - $assertcontrol(OFF, EXPECT); - $assertcontrol(OFF, UNIQUE); - $assertcontrol(OFF, UNIQUE0); - $assertcontrol(OFF, PRIORITY); - end + initial begin + $assertcontrol(OFF, EXPECT); + $assertcontrol(OFF, UNIQUE); + $assertcontrol(OFF, UNIQUE0); + $assertcontrol(OFF, PRIORITY); + end endmodule diff --git a/test_regress/t/t_assert_ctl_concurrent.v b/test_regress/t/t_assert_ctl_concurrent.v index 3cc919d92..3cdda2bc1 100644 --- a/test_regress/t/t_assert_ctl_concurrent.v +++ b/test_regress/t/t_assert_ctl_concurrent.v @@ -6,39 +6,33 @@ module t; - bit clock = 1'b0; - bit reset = 1'b0; + bit clock = 1'b0; + bit reset = 1'b0; - initial begin - $assertkill; + initial begin + $assertkill; - #10 + #10 reset = 1'b1; + $display("%t: deassert reset %d", $time, reset); - reset = 1'b1; - $display("%t: deassert reset %d", $time, reset); + #40 $asserton; - #40 + reset = 1'b0; + $display("%t: deassert reset %d", $time, reset); - $asserton; + #200 $display("%t: finish", $time); + $write("*-* All Finished *-*\n"); + $finish; - reset = 1'b0; - $display("%t: deassert reset %d", $time, reset); + end - #200 + always #10 clock = ~clock; + reg r = 1'b0; - $display("%t: finish", $time); - $write("*-* All Finished *-*\n"); - $finish; + always @(posedge clock) if (reset) r <= 1'b1; - end - - always #10 clock = ~clock; - reg r = 1'b0; - - always @(posedge clock) if (reset) r <= 1'b1; - - assert_test: - assert property (@(posedge clock) (reset | r)) - else $error("%t: assertion triggered", $time); + assert_test : + assert property (@(posedge clock) (reset | r)) + else $error("%t: assertion triggered", $time); endmodule diff --git a/test_regress/t/t_assert_ctl_immediate.out b/test_regress/t/t_assert_ctl_immediate.out index bd71f8bb5..a10fd21c4 100644 --- a/test_regress/t/t_assert_ctl_immediate.out +++ b/test_regress/t/t_assert_ctl_immediate.out @@ -1,6 +1,6 @@ -[0] %Error: t_assert_ctl_immediate.v:47: Assertion failed in top.t.module_with_assertctl: 'assert' failed. --Info: t/t_assert_ctl_immediate.v:47: Verilog $stop, ignored due to +verilator+error+limit -[0] %Error: t_assert_ctl_immediate.v:53: Assertion failed in top.t.module_with_assertctl: 'assert' failed. -[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. -[0] %Error: t_assert_ctl_immediate.v:41: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. +[0] %Error: t_assert_ctl_immediate.v:51: Assertion failed in top.t.module_with_assertctl: 'assert' failed. +-Info: t/t_assert_ctl_immediate.v:51: Verilog $stop, ignored due to +verilator+error+limit +[0] %Error: t_assert_ctl_immediate.v:57: Assertion failed in top.t.module_with_assertctl: 'assert' failed. +[0] %Error: t_assert_ctl_immediate.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. +[0] %Error: t_assert_ctl_immediate.v:45: Assertion failed in top.t.module_with_assertctl.f_assert: 'assert' failed. *-* All Finished *-* diff --git a/test_regress/t/t_assert_ctl_immediate.v b/test_regress/t/t_assert_ctl_immediate.v index 26d5a1e92..6c5848aaf 100644 --- a/test_regress/t/t_assert_ctl_immediate.v +++ b/test_regress/t/t_assert_ctl_immediate.v @@ -4,58 +4,62 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + module_with_assert module_with_assert (clk); + module_with_assertctl module_with_assertctl (clk); - module_with_assert module_with_assert(clk); - module_with_assertctl module_with_assertctl(clk); + always @(posedge clk) begin + assert (0); + end - always @ (posedge clk) begin - assert(0); - end - - always @ (negedge clk) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(negedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule -module module_with_assert(input clk); - always @(posedge clk) assert(0); +module module_with_assert ( + input clk +); + always @(posedge clk) assert (0); endmodule -module module_with_assertctl(input clk); - function void assert_off; begin +module module_with_assertctl ( + input clk +); + function void assert_off; + begin $assertoff; - end - endfunction - function void assert_on; begin + end + endfunction + function void assert_on; + begin $asserton; - end - endfunction - function void f_assert; begin - assert(0); - end - endfunction + end + endfunction + function void f_assert; + begin + assert (0); + end + endfunction - initial begin - assert_on(); - assert(0); - assert_off(); - assert_off(); - assert(0); - assert_on(); - assert_on(); - assert(0); + initial begin + assert_on(); + assert (0); + assert_off(); + assert_off(); + assert (0); + assert_on(); + assert_on(); + assert (0); - f_assert(); - f_assert(); - assert_off(); - f_assert(); - f_assert(); - end + f_assert(); + f_assert(); + assert_off(); + f_assert(); + f_assert(); + end endmodule diff --git a/test_regress/t/t_assert_ctl_unsup.out b/test_regress/t/t_assert_ctl_unsup.out index 4aae777cb..26e32ff0d 100644 --- a/test_regress/t/t_assert_ctl_unsup.out +++ b/test_regress/t/t_assert_ctl_unsup.out @@ -1,123 +1,123 @@ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:7: Unsupported: non-constant assert assertion-type expression +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:25:5: Unsupported: non-constant assert assertion-type expression : ... note: In instance 't.unsupported_ctl_type' - 25 | $assertcontrol(Lock, a); - | ^~~~~~~~~~~~~~ + 25 | $assertcontrol(Lock, a); + | ^~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:7: Unsupported: $assertcontrol control_type '2' - 27 | $assertcontrol(Unlock); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:7: Unsupported: $assertcontrol control_type '6' - 29 | $assertcontrol(PassOn); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:7: Unsupported: assert control assertion_type +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:27:5: Unsupported: $assertcontrol control_type '2' + 27 | $assertcontrol(Unlock); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:29:5: Unsupported: $assertcontrol control_type '6' + 29 | $assertcontrol(PassOn); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:30:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 30 | $assertpasson; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:7: Unsupported: assert control assertion_type + 30 | $assertpasson; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:31:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 31 | $assertpasson(a); - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:7: Unsupported: assert control assertion_type + 31 | $assertpasson(a); + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:32:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 32 | $assertpasson(a, t); - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:7: Unsupported: $assertcontrol control_type '7' - 34 | $assertcontrol(PassOff); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:7: Unsupported: assert control assertion_type + 32 | $assertpasson(a, t); + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:34:5: Unsupported: $assertcontrol control_type '7' + 34 | $assertcontrol(PassOff); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:35:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 35 | $assertpassoff; - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:7: Unsupported: assert control assertion_type + 35 | $assertpassoff; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:36:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 36 | $assertpassoff(a); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:7: Unsupported: assert control assertion_type + 36 | $assertpassoff(a); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:37:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 37 | $assertpassoff(a, t); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:7: Unsupported: $assertcontrol control_type '8' - 39 | $assertcontrol(FailOn); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:7: Unsupported: assert control assertion_type + 37 | $assertpassoff(a, t); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:39:5: Unsupported: $assertcontrol control_type '8' + 39 | $assertcontrol(FailOn); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:40:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 40 | $assertfailon; - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:7: Unsupported: assert control assertion_type + 40 | $assertfailon; + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:41:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 41 | $assertfailon(a); - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:7: Unsupported: assert control assertion_type + 41 | $assertfailon(a); + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:42:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 42 | $assertfailon(a, t); - | ^~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:7: Unsupported: $assertcontrol control_type '9' - 44 | $assertcontrol(FailOff); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:7: Unsupported: assert control assertion_type + 42 | $assertfailon(a, t); + | ^~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:44:5: Unsupported: $assertcontrol control_type '9' + 44 | $assertcontrol(FailOff); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:45:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 45 | $assertfailoff; - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:7: Unsupported: assert control assertion_type + 45 | $assertfailoff; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:46:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 46 | $assertfailoff(a); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:7: Unsupported: assert control assertion_type + 46 | $assertfailoff(a); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:47:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 47 | $assertfailoff(a, t); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:7: Unsupported: $assertcontrol control_type '10' - 49 | $assertcontrol(NonvacuousOn); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:7: Unsupported: assert control assertion_type + 47 | $assertfailoff(a, t); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:49:5: Unsupported: $assertcontrol control_type '10' + 49 | $assertcontrol(NonvacuousOn); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:50:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 50 | $assertnonvacuouson; - | ^~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:7: Unsupported: assert control assertion_type + 50 | $assertnonvacuouson; + | ^~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:51:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 51 | $assertnonvacuouson(a); - | ^~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:7: Unsupported: assert control assertion_type + 51 | $assertnonvacuouson(a); + | ^~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:52:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 52 | $assertnonvacuouson(a, t); - | ^~~~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:7: Unsupported: $assertcontrol control_type '11' - 54 | $assertcontrol(VacuousOff); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:7: Unsupported: assert control assertion_type + 52 | $assertnonvacuouson(a, t); + | ^~~~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:54:5: Unsupported: $assertcontrol control_type '11' + 54 | $assertcontrol(VacuousOff); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:55:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 55 | $assertvacuousoff; - | ^~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:7: Unsupported: assert control assertion_type + 55 | $assertvacuousoff; + | ^~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:56:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 56 | $assertvacuousoff(a); - | ^~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:7: Unsupported: assert control assertion_type + 56 | $assertvacuousoff(a); + | ^~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:57:5: Unsupported: assert control assertion_type : ... note: In instance 't.unsupported_ctl_type' - 57 | $assertvacuousoff(a, t); - | ^~~~~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:7: Unsupported: non-const assert control type expression + 57 | $assertvacuousoff(a, t); + | ^~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:64:5: Unsupported: non-const assert control type expression : ... note: In instance 't.unsupported_ctl_type_expr' - 64 | $assertcontrol(ctl_type); - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:10: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_class' - 93 | $asserton; - | ^~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:10: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_class' - 99 | $assertoff; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:7: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_iface' - 172 | $assertoff; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:7: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_iface_class' - 138 | $assertoff; - | ^~~~~~~~~~ -%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:7: Unsupported: assertcontrols in classes or interfaces - : ... note: In instance 't.assert_iface_class' - 145 | $asserton; + 64 | $assertcontrol(ctl_type); + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:93:7: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_class' + 93 | $asserton; | ^~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:99:7: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_class' + 99 | $assertoff; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:172:5: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_iface' + 172 | $assertoff; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:138:5: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_iface_class' + 138 | $assertoff; + | ^~~~~~~~~~ +%Error-UNSUPPORTED: t/t_assert_ctl_unsup.v:145:5: Unsupported: assertcontrols in classes or interfaces + : ... note: In instance 't.assert_iface_class' + 145 | $asserton; + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_ctl_unsup.v b/test_regress/t/t_assert_ctl_unsup.v index 7ff4eb013..98afcad10 100644 --- a/test_regress/t/t_assert_ctl_unsup.v +++ b/test_regress/t/t_assert_ctl_unsup.v @@ -5,181 +5,181 @@ // SPDX-License-Identifier: CC0-1.0 module t(input logic clk); - unsupported_ctl_type unsupported_ctl_type(clk ? 1 : 2); - unsupported_ctl_type_expr unsupported_ctl_type_expr(); - assert_class assert_class(); - assert_iface assert_iface(); - assert_iface_class assert_iface_class(); + unsupported_ctl_type unsupported_ctl_type(clk ? 1 : 2); + unsupported_ctl_type_expr unsupported_ctl_type_expr(); + assert_class assert_class(); + assert_iface assert_iface(); + assert_iface_class assert_iface_class(); endmodule module unsupported_ctl_type(input int a); - initial begin - let Lock = 1; - let Unlock = 2; - let PassOn = 6; - let PassOff = 7; - let FailOn = 8; - let FailOff = 9; - let NonvacuousOn = 10; - let VacuousOff = 11; - $assertcontrol(Lock, a); + initial begin + let Lock = 1; + let Unlock = 2; + let PassOn = 6; + let PassOff = 7; + let FailOn = 8; + let FailOff = 9; + let NonvacuousOn = 10; + let VacuousOff = 11; + $assertcontrol(Lock, a); - $assertcontrol(Unlock); + $assertcontrol(Unlock); - $assertcontrol(PassOn); - $assertpasson; - $assertpasson(a); - $assertpasson(a, t); + $assertcontrol(PassOn); + $assertpasson; + $assertpasson(a); + $assertpasson(a, t); - $assertcontrol(PassOff); - $assertpassoff; - $assertpassoff(a); - $assertpassoff(a, t); + $assertcontrol(PassOff); + $assertpassoff; + $assertpassoff(a); + $assertpassoff(a, t); - $assertcontrol(FailOn); - $assertfailon; - $assertfailon(a); - $assertfailon(a, t); + $assertcontrol(FailOn); + $assertfailon; + $assertfailon(a); + $assertfailon(a, t); - $assertcontrol(FailOff); - $assertfailoff; - $assertfailoff(a); - $assertfailoff(a, t); + $assertcontrol(FailOff); + $assertfailoff; + $assertfailoff(a); + $assertfailoff(a, t); - $assertcontrol(NonvacuousOn); - $assertnonvacuouson; - $assertnonvacuouson(a); - $assertnonvacuouson(a, t); + $assertcontrol(NonvacuousOn); + $assertnonvacuouson; + $assertnonvacuouson(a); + $assertnonvacuouson(a, t); - $assertcontrol(VacuousOff); - $assertvacuousoff; - $assertvacuousoff(a); - $assertvacuousoff(a, t); - end + $assertcontrol(VacuousOff); + $assertvacuousoff; + $assertvacuousoff(a); + $assertvacuousoff(a, t); + end endmodule module unsupported_ctl_type_expr; - int ctl_type = 1; - initial begin - $assertcontrol(ctl_type); - end + int ctl_type = 1; + initial begin + $assertcontrol(ctl_type); + end endmodule module assert_class; - virtual class AssertCtl; - pure virtual function void virtual_assert_ctl(); - endclass + virtual class AssertCtl; + pure virtual function void virtual_assert_ctl(); + endclass - class AssertCls; - static function void static_function(); - assert(0); - endfunction - static task static_task(); - assert(0); - endtask - function void assert_function(); - assert(0); - endfunction - task assert_task(); - assert(0); - endtask - virtual function void virtual_assert(); - assert(0); - endfunction - endclass + class AssertCls; + static function void static_function(); + assert(0); + endfunction + static task static_task(); + assert(0); + endtask + function void assert_function(); + assert(0); + endfunction + task assert_task(); + assert(0); + endtask + virtual function void virtual_assert(); + assert(0); + endfunction + endclass - class AssertOn extends AssertCtl; - virtual function void virtual_assert_ctl(); - $asserton; - endfunction - endclass - - class AssertOff extends AssertCtl; - virtual function void virtual_assert_ctl(); - $assertoff; - endfunction - endclass - - AssertCls assertCls; - AssertOn assertOn; - AssertOff assertOff; - initial begin - $assertoff; - AssertCls::static_function(); - AssertCls::static_task(); + class AssertOn extends AssertCtl; + virtual function void virtual_assert_ctl(); $asserton; - AssertCls::static_function(); - AssertCls::static_task(); + endfunction + endclass - assertCls = new; - assertOn = new; - assertOff = new; + class AssertOff extends AssertCtl; + virtual function void virtual_assert_ctl(); + $assertoff; + endfunction + endclass - assertOff.virtual_assert_ctl(); - assertCls.assert_function(); - assertCls.assert_task(); - assertCls.virtual_assert(); + AssertCls assertCls; + AssertOn assertOn; + AssertOff assertOff; + initial begin + $assertoff; + AssertCls::static_function(); + AssertCls::static_task(); + $asserton; + AssertCls::static_function(); + AssertCls::static_task(); - assertOn.virtual_assert_ctl(); - assertCls.assert_function(); - assertCls.assert_task(); - assertCls.virtual_assert(); - assertOff.virtual_assert_ctl(); - assertCls.assert_function(); - end + assertCls = new; + assertOn = new; + assertOff = new; + + assertOff.virtual_assert_ctl(); + assertCls.assert_function(); + assertCls.assert_task(); + assertCls.virtual_assert(); + + assertOn.virtual_assert_ctl(); + assertCls.assert_function(); + assertCls.assert_task(); + assertCls.virtual_assert(); + assertOff.virtual_assert_ctl(); + assertCls.assert_function(); + end endmodule interface Iface; - function void assert_func(); - assert(0); - endfunction + function void assert_func(); + assert(0); + endfunction - function void assertoff_func(); - $assertoff; - endfunction + function void assertoff_func(); + $assertoff; + endfunction - initial begin - assertoff_func(); - assert(0); - assert_func(); - $asserton; - assert(0); - assert_func(); - end + initial begin + assertoff_func(); + assert(0); + assert_func(); + $asserton; + assert(0); + assert_func(); + end endinterface module assert_iface; - Iface iface(); - virtual Iface vIface = iface; - initial begin - vIface.assert_func(); - vIface.assertoff_func(); - vIface.assert_func(); + Iface iface(); + virtual Iface vIface = iface; + initial begin + vIface.assert_func(); + vIface.assertoff_func(); + vIface.assert_func(); - iface.assert_func(); - iface.assertoff_func(); - iface.assert_func(); - end + iface.assert_func(); + iface.assertoff_func(); + iface.assert_func(); + end endmodule interface class IfaceClass; - pure virtual function void assertoff_func(); - pure virtual function void assert_func(); + pure virtual function void assertoff_func(); + pure virtual function void assert_func(); endclass class IfaceClassImpl implements IfaceClass; - virtual function void assertoff_func(); - $assertoff; - endfunction - virtual function void assert_func(); - assert(0); - endfunction + virtual function void assertoff_func(); + $assertoff; + endfunction + virtual function void assert_func(); + assert(0); + endfunction endclass module assert_iface_class; - IfaceClassImpl ifaceClassImpl = new; - initial begin - ifaceClassImpl.assertoff_func(); - ifaceClassImpl.assert_func(); - end + IfaceClassImpl ifaceClassImpl = new; + initial begin + ifaceClassImpl.assertoff_func(); + ifaceClassImpl.assert_func(); + end endmodule diff --git a/test_regress/t/t_assert_disable_bad.out b/test_regress/t/t_assert_disable_bad.out index 66a373165..ae85a663f 100644 --- a/test_regress/t/t_assert_disable_bad.out +++ b/test_regress/t/t_assert_disable_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_assert_disable_bad.v:27:38: disable iff expression before property call and in its body is not legal +%Error: t/t_assert_disable_bad.v:25:37: disable iff expression before property call and in its body is not legal : ... note: In instance 't' - 27 | assert property (disable iff (val == 0) check(1, 1)); - | ^~ + 25 | assert property (disable iff (val == 0) check(1, 1)); + | ^~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_assert_disable_bad.v b/test_regress/t/t_assert_disable_bad.v index 4103e7b54..775ec72b8 100644 --- a/test_regress/t/t_assert_disable_bad.v +++ b/test_regress/t/t_assert_disable_bad.v @@ -4,25 +4,23 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic val = 0; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - property check(int cyc_mod_2, logic expected); - @(posedge clk) disable iff (cyc == 0) cyc % 2 == cyc_mod_2 |=> val == expected; - endproperty + property check(int cyc_mod_2, logic expected); + @(posedge clk) disable iff (cyc == 0) cyc % 2 == cyc_mod_2 |=> val == expected; + endproperty - // Test should fail due to duplicated disable iff statements - // (IEEE 1800-2012 16.12.1). - assert property (disable iff (val == 0) check(1, 1)); + // Test should fail due to duplicated disable iff statements + // (IEEE 1800-2012 16.12.1). + assert property (disable iff (val == 0) check(1, 1)); endmodule diff --git a/test_regress/t/t_assert_disable_count.v b/test_regress/t/t_assert_disable_count.v index 54451f211..9411177d5 100644 --- a/test_regress/t/t_assert_disable_count.v +++ b/test_regress/t/t_assert_disable_count.v @@ -4,66 +4,69 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + int cyc; - int cyc; + Sub sub (); - Sub sub (); + default disable iff (cyc[0]); - default disable iff (cyc[0]); + int a_false; + always @(posedge clk iff !cyc[0]) begin + if (cyc < 4 || cyc > 9); + else a_false = a_false + 1; + end - int a_false; - always @(posedge clk iff !cyc[0]) begin - if (cyc < 4 || cyc > 9) ; - else a_false = a_false + 1; - end + int a0_false; + a0 : + assert property (@(posedge clk) disable iff (cyc[0]) (cyc < 4 || cyc > 9)) + else a0_false = a0_false + 1; - int a0_false; - a0: assert property (@(posedge clk) disable iff (cyc[0]) (cyc < 4 || cyc > 9)) - else a0_false = a0_false + 1; + int a1_false; + // Note that Verilator supports $inferred_disable in general expression locations + // This is a superset of what IEEE specifies + a1 : + assert property (@(posedge clk) disable iff ($inferred_disable) (cyc < 4 || cyc > 9)) + else a1_false = a1_false + 1; - int a1_false; - // Note that Verilator supports $inferred_disable in general expression locations - // This is a superset of what IEEE specifies - a1: assert property (@(posedge clk) disable iff ($inferred_disable) (cyc < 4 || cyc > 9)) - else a1_false = a1_false + 1; + int a2_false; + // Implicitly uses $inferred_disable + a2 : + assert property (@(posedge clk) (cyc < 4 || cyc > 9)) + else a2_false = a2_false + 1; - int a2_false; - // Implicitly uses $inferred_disable - a2: assert property (@(posedge clk) (cyc < 4 || cyc > 9)) - else a2_false = a2_false + 1; + int a3_false; + // A different disable iff expression + a3 : + assert property (@(posedge clk) disable iff (cyc == 5) (cyc < 4 || cyc > 9)) + else a3_false = a3_false + 1; - int a3_false; - // A different disable iff expression - a3: assert property (@(posedge clk) disable iff (cyc == 5) (cyc < 4 || cyc > 9)) - else a3_false = a3_false + 1; - - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 20) begin - `checkd(a_false, 3); - `checkd(a0_false, a_false); - `checkd(a1_false, a_false); - `checkd(a2_false, a_false); - `checkd(a3_false, 5); - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 20) begin + `checkd(a_false, 3); + `checkd(a0_false, a_false); + `checkd(a1_false, a_false); + `checkd(a2_false, a_false); + `checkd(a3_false, 5); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule module Sub; - initial begin - if ($inferred_disable !== 0) $stop; - end + initial begin + if ($inferred_disable !== 0) $stop; + end endmodule diff --git a/test_regress/t/t_assert_dup_bad.out b/test_regress/t/t_assert_dup_bad.out index 3bce26f7b..336c91ace 100644 --- a/test_regress/t/t_assert_dup_bad.out +++ b/test_regress/t/t_assert_dup_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_assert_dup_bad.v:17:4: Duplicate declaration of block: 'covlabel' - 17 | covlabel: - | ^~~~~~~~ - t/t_assert_dup_bad.v:15:4: ... Location of original declaration - 15 | covlabel: - | ^~~~~~~~ +%Error: t/t_assert_dup_bad.v:15:3: Duplicate declaration of block: 'covlabel' + 15 | covlabel : + | ^~~~~~~~ + t/t_assert_dup_bad.v:13:3: ... Location of original declaration + 13 | covlabel : + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_assert_dup_bad.v b/test_regress/t/t_assert_dup_bad.v index 250f7da9e..7be4d73ff 100644 --- a/test_regress/t/t_assert_dup_bad.v +++ b/test_regress/t/t_assert_dup_bad.v @@ -4,17 +4,15 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc = 0; + int cyc; - covlabel: - cover property (@(posedge clk) cyc==5); - covlabel: // Error: Duplicate block_identifier - cover property (@(posedge clk) cyc==5); + covlabel : + cover property (@(posedge clk) cyc == 5); + covlabel : // Error: Duplicate block_identifier + cover property (@(posedge clk) cyc == 5); endmodule diff --git a/test_regress/t/t_assert_elab.v b/test_regress/t/t_assert_elab.v index 516cbd220..5492abbbb 100644 --- a/test_regress/t/t_assert_elab.v +++ b/test_regress/t/t_assert_elab.v @@ -5,26 +5,25 @@ // SPDX-License-Identifier: CC0-1.0 module t; - localparam STR = "string"; - function logic checkParameter(input logic [8:0] N); - $info("For %m, x is %d.", N); - if (N == 1) - return 0; - $fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work"); - endfunction + localparam STR = "string"; + function logic checkParameter(input logic [8:0] N); + $info("For %m, x is %d.", N); + if (N == 1) return 0; + $fatal(1, "Parameter %d is invalid...%s and %s", N, STR, "constant both work"); + endfunction `ifdef FAILING_ASSERTIONS - localparam X = checkParameter(5); + localparam X = checkParameter(5); `else - localparam X = checkParameter(1); + localparam X = checkParameter(1); `endif - generate - $info("%m: In generate"); // Issue 6445 - endgenerate + generate + $info("%m: In generate"); // Issue 6445 + endgenerate - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_iff.v b/test_regress/t/t_assert_iff.v index b56e72993..7a435fca8 100644 --- a/test_regress/t/t_assert_iff.v +++ b/test_regress/t/t_assert_iff.v @@ -4,54 +4,46 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - logic[3:0] enable; - int cyc = 0; +module t ( + input clk +); - Test test(.*); + logic [3:0] enable; + int cyc = 0; - always @ (posedge clk) begin - cyc <= cyc + 1; - `ifdef FAIL1 enable[0] <= 1; `endif - enable[1] <= 1; - `ifdef FAIL2 enable[2] <= 1; `endif - enable[3] <= 1; - if (cyc != 0) begin - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + Test test (.*); + + always @(posedge clk) begin + cyc <= cyc + 1; +`ifdef FAIL1 + enable[0] <= 1; +`endif + enable[1] <= 1; +`ifdef FAIL2 + enable[2] <= 1; +`endif + enable[3] <= 1; + if (cyc != 0) begin + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule -module Test( - input clk, - input[3:0] enable - ); +module Test ( + input clk, + input [3:0] enable +); - assert property ( - @(posedge clk iff enable[0]) - 0 - ) else $stop; + assert property (@(posedge clk iff enable[0]) 0) + else $stop; - assert property ( - @(posedge clk iff enable[1]) - 1 - ); + assert property (@(posedge clk iff enable[1]) 1); - cover property ( - @(posedge clk iff enable[2]) - 1 - ) $stop; + cover property (@(posedge clk iff enable[2]) 1) $stop; - cover property ( - @(posedge clk iff enable[3]) - 0 - ) $stop; + cover property (@(posedge clk iff enable[3]) 0) $stop; endmodule diff --git a/test_regress/t/t_assert_iff_clk_unsup.out b/test_regress/t/t_assert_iff_clk_unsup.out index 2a75cd94e..3ff98273e 100644 --- a/test_regress/t/t_assert_iff_clk_unsup.out +++ b/test_regress/t/t_assert_iff_clk_unsup.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:21: Unsupported: property '(disable iff (...) @ (...)' +%Error-UNSUPPORTED: t/t_assert_iff_clk_unsup.v:20:20: Unsupported: property '(disable iff (...) @ (...)' : ... Suggest use property '(@(...) disable iff (...))' - 20 | assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); - | ^~~~~~~ + 20 | assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); + | ^~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assert_iff_clk_unsup.v b/test_regress/t/t_assert_iff_clk_unsup.v index 8890d5878..efe917a04 100644 --- a/test_regress/t/t_assert_iff_clk_unsup.v +++ b/test_regress/t/t_assert_iff_clk_unsup.v @@ -4,19 +4,19 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; - int cyc = 0; - logic val = 0; + input clk; + int cyc = 0; + logic val = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - end + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + end - assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); + assert property (disable iff (cyc < 5) @(posedge clk) cyc >= 5); endmodule diff --git a/test_regress/t/t_assert_imm_nz_bad.out b/test_regress/t/t_assert_imm_nz_bad.out index 8bf198256..33769d42d 100644 --- a/test_regress/t/t_assert_imm_nz_bad.out +++ b/test_regress/t/t_assert_imm_nz_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_assert_imm_nz_bad.v:13:26: Deferred assertions must use '#0' (IEEE 1800-2023 16.4) - 13 | labeled_imas: assert #1 (clk); - | ^ +%Error: t/t_assert_imm_nz_bad.v:14:11: Deferred assertions must use '#0' (IEEE 1800-2023 16.4) + 14 | assert #1 (clk); + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_assert_imm_nz_bad.v b/test_regress/t/t_assert_imm_nz_bad.v index eaee647fe..49bbc1b7b 100644 --- a/test_regress/t/t_assert_imm_nz_bad.v +++ b/test_regress/t/t_assert_imm_nz_bad.v @@ -4,12 +4,13 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); +module t ( + input clk +); - input clk; + input clk; - labeled_imas: assert #1 (clk); // BAD: #1 + labeled_imas : + assert #1 (clk); // BAD: #1 endmodule diff --git a/test_regress/t/t_assert_implication.v b/test_regress/t/t_assert_implication.v index 4eb169f87..669b03671 100644 --- a/test_regress/t/t_assert_implication.v +++ b/test_regress/t/t_assert_implication.v @@ -4,127 +4,84 @@ // SPDX-FileCopyrightText: 2019 Peter Monsson // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - Test test (/*AUTOINST*/ - // Inputs - .clk(clk), - .cyc(cyc)); + Test test ( /*AUTOINST*/ + // Inputs + .clk(clk), + .cyc(cyc) + ); - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; `ifdef TEST_VERBOSE - $display("cyc=%0d", cyc); + $display("cyc=%0d", cyc); `endif - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule -module Test - ( - input clk, - input integer cyc - ); +module Test ( + input clk, + input integer cyc +); `ifdef FAIL_ASSERT_1 - assert property ( - @(posedge clk) - 1 |-> 0 - ) else $display("[%0t] wrong implication", $time); + assert property (@(posedge clk) 1 |-> 0) + else $display("[%0t] wrong implication", $time); - assert property ( - @(posedge clk) - 1 |=> 0 - ) else $display("[%0t] wrong implication", $time); + assert property (@(posedge clk) 1 |=> 0) + else $display("[%0t] wrong implication", $time); - assert property ( - @(posedge clk) - cyc%3==1 |=> cyc%3==1 - ) else $display("[%0t] wrong implication (step)", $time); + assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 1) + else $display("[%0t] wrong implication (step)", $time); - assert property ( - @(posedge clk) - cyc%3==1 |=> cyc%3==0 - ) else $display("[%0t] wrong implication (step)", $time); + assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 0) + else $display("[%0t] wrong implication (step)", $time); - assert property ( - @(posedge clk) disable iff (cyc == 3) - (cyc == 4) |=> 0 - ) else $display("[%0t] wrong implication (disable)", $time); + assert property (@(posedge clk) disable iff (cyc == 3) (cyc == 4) |=> 0) + else $display("[%0t] wrong implication (disable)", $time); - assert property ( - @(posedge clk) disable iff (cyc == 6) - (cyc == 4) |=> 0 - ) else $display("[%0t] wrong implication (disable)", $time); + assert property (@(posedge clk) disable iff (cyc == 6) (cyc == 4) |=> 0) + else $display("[%0t] wrong implication (disable)", $time); `endif - // Test |-> - assert property ( - @(posedge clk) - 1 |-> 1 - ); + // Test |-> + assert property (@(posedge clk) 1 |-> 1); - assert property ( - @(posedge clk) - 0 |-> 0 - ); + assert property (@(posedge clk) 0 |-> 0); - assert property ( - @(posedge clk) - 0 |-> 1 - ); + assert property (@(posedge clk) 0 |-> 1); - // Test |=> - assert property ( - @(posedge clk) - 1 |=> 1 - ); + // Test |=> + assert property (@(posedge clk) 1 |=> 1); - assert property ( - @(posedge clk) - 0 |=> 0 - ); + assert property (@(posedge clk) 0 |=> 0); - assert property ( - @(posedge clk) - 0 |=> 1 - ); + assert property (@(posedge clk) 0 |=> 1); - // Test correct handling of time step in |=> - assert property ( - @(posedge clk) - cyc%3==1 |=> cyc%3==2 - ); + // Test correct handling of time step in |=> + assert property (@(posedge clk) cyc % 3 == 1 |=> cyc % 3 == 2); - // Test correct handling of disable iff - assert property ( - @(posedge clk) disable iff ($sampled(cyc) < 3) - 1 |=> cyc > 3 - ); + // Test correct handling of disable iff + assert property (@(posedge clk) disable iff ($sampled(cyc) < 3) 1 |=> cyc > 3); - // Test correct handling of disable iff in current cycle - assert property ( - @(posedge clk) disable iff ($sampled(cyc) == 4) - (cyc == 4) |=> 0 - ); + // Test correct handling of disable iff in current cycle + assert property (@(posedge clk) disable iff ($sampled(cyc) == 4) (cyc == 4) |=> 0); - // Test correct handling of disable iff in previous cycle - assert property ( - @(posedge clk) disable iff (cyc == 5) - (cyc == 4) |=> 0 - ); + // Test correct handling of disable iff in previous cycle + assert property (@(posedge clk) disable iff (cyc == 5) (cyc == 4) |=> 0); endmodule diff --git a/test_regress/t/t_assert_inside_cond.v b/test_regress/t/t_assert_inside_cond.v index 1a70b7a14..d7058bed5 100644 --- a/test_regress/t/t_assert_inside_cond.v +++ b/test_regress/t/t_assert_inside_cond.v @@ -11,36 +11,36 @@ module t (/*AUTOARG*/ clk ); - input clk; - output logic hit; + input clk; + output logic hit; - logic [31:0] addr; - int cyc; + logic [31:0] addr; + int cyc; - initial addr = 32'h380; + initial addr = 32'h380; - always @ (posedge clk) begin - cyc <= cyc + 1; + always @ (posedge clk) begin + cyc <= cyc + 1; `ifdef T_ASSERT_INSIDE_COND - addr <= 32'h380; + addr <= 32'h380; `elsif T_ASSERT_INSIDE_COND_BAD - addr <= 32'h389; + addr <= 32'h389; `else `error "Bad test define" `endif - if (cyc == 9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always_comb begin - hit = 0; - unique case (addr[11:0]) inside - [12'h380 : 12'h388]: begin - hit = 1; - end - endcase - end + always_comb begin + hit = 0; + unique case (addr[11:0]) inside + [12'h380 : 12'h388]: begin + hit = 1; + end + endcase + end endmodule diff --git a/test_regress/t/t_assert_on.v b/test_regress/t/t_assert_on.v index 5ee299316..3639d06b0 100644 --- a/test_regress/t/t_assert_on.v +++ b/test_regress/t/t_assert_on.v @@ -4,17 +4,14 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - - always @ (posedge clk) begin - assert (0); - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + assert (0); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_past.v b/test_regress/t/t_assert_past.v index 40708babf..976623021 100644 --- a/test_regress/t/t_assert_past.v +++ b/test_regress/t/t_assert_past.v @@ -4,25 +4,24 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - clk - ); - input clk; - int cyc = 0; - logic val = 0; - // Example: - always @(posedge clk) begin - cyc <= cyc + 1; - val = ~val; - $display("t=%0t cyc=%0d val=%b", $time, cyc, val); - if (cyc == 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end - assert property(@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0) - else $display("$past assert 1 failed"); - assert property(@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1) - else $display("$past assert 2 failed"); - // Example end +module t ( + input clk +); + int cyc = 0; + logic val = 0; + // Example: + always @(posedge clk) begin + cyc <= cyc + 1; + val = ~val; + $display("t=%0t cyc=%0d val=%b", $time, cyc, val); + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + assert property (@(posedge clk) cyc % 2 == 0 |=> $past(val) == 0) + else $display("$past assert 1 failed"); + assert property (@(posedge clk) cyc % 2 == 1 |=> $past(val) == 1) + else $display("$past assert 2 failed"); + // Example end endmodule diff --git a/test_regress/t/t_assert_procedural_clk_bad.out b/test_regress/t/t_assert_procedural_clk_bad.out index 9214de450..1da4cc66e 100644 --- a/test_regress/t/t_assert_procedural_clk_bad.out +++ b/test_regress/t/t_assert_procedural_clk_bad.out @@ -1,10 +1,10 @@ -%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:21:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) - : ... note: In instance 't' - 21 | assume property (@(posedge clk) cyc == 9); - | ^~~~~~ +%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:19:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) + : ... note: In instance 't' + 19 | assume property (@(posedge clk) cyc == 9); + | ^~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:22:13: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) - : ... note: In instance 't' - 22 | assume property (@(negedge clk) cyc == 9); - | ^~~~~~ +%Error-UNSUPPORTED: t/t_assert_procedural_clk_bad.v:20:9: Unsupported: Procedural concurrent assertion with clocking event inside always (IEEE 1800-2023 16.14.6) + : ... note: In instance 't' + 20 | assume property (@(negedge clk) cyc == 9); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_procedural_clk_bad.v b/test_regress/t/t_assert_procedural_clk_bad.v index e0615046f..7e458231f 100644 --- a/test_regress/t/t_assert_procedural_clk_bad.v +++ b/test_regress/t/t_assert_procedural_clk_bad.v @@ -4,28 +4,26 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer cyc; + initial cyc = 1; + wire [7:0] cyc_copy = cyc[7:0]; - integer cyc; initial cyc=1; - wire [7:0] cyc_copy = cyc[7:0]; - - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==9) begin - assume property (@(posedge clk) cyc == 9); - assume property (@(negedge clk) cyc == 9); - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + if (cyc == 9) begin + assume property (@(posedge clk) cyc == 9); + assume property (@(negedge clk) cyc == 9); end - end + if (cyc == 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end endmodule diff --git a/test_regress/t/t_assert_question.v b/test_regress/t/t_assert_question.v index 8d756a8e3..518d90d43 100644 --- a/test_regress/t/t_assert_question.v +++ b/test_regress/t/t_assert_question.v @@ -11,24 +11,24 @@ module t (/*AUTOARG*/ clk, sel, a, c ); - input clk; - input bit [3:0] sel; - input bit [3:0] a; - input bit c; - output bit dout; + input clk; + input bit [3:0] sel; + input bit [3:0] a; + input bit c; + output bit dout; - localparam logic DC = 1'b?; + localparam logic DC = 1'b?; - always_ff @(posedge clk) begin - unique casez(sel) - 4'b0000: dout <= a[0]; - 4'b001?: dout <= a[1]; - {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; - {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; - default: dout <= '0; - endcase - $write("*-* All Finished *-*\n"); - $finish; - end + always_ff @(posedge clk) begin + unique casez(sel) + 4'b0000: dout <= a[0]; + 4'b001?: dout <= a[1]; + {1'b0, 1'b1, 1'b?, 1'b?}: dout <= a[2]; + {1'b1, 1'b?, 1'b?, DC}: dout <= a[3]; + default: dout <= '0; + endcase + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assert_sampled.v b/test_regress/t/t_assert_sampled.v index 5344592d6..0522ad690 100644 --- a/test_regress/t/t_assert_sampled.v +++ b/test_regress/t/t_assert_sampled.v @@ -4,87 +4,109 @@ // SPDX-FileCopyrightText: 2022 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - reg [3:0] a, b; + reg [3:0] a, b; - Test1 t1(clk, a, b); - Test2 t2(clk, a, b); - Test3 t3(clk, a, b); + Test1 t1 ( + clk, + a, + b + ); + Test2 t2 ( + clk, + a, + b + ); + Test3 t3 ( + clk, + a, + b + ); - initial begin - a = 0; - b = 0; - end + initial begin + a = 0; + b = 0; + end - always @(posedge clk) begin - a <= a + 1; - b = b + 1; + always @(posedge clk) begin + a <= a + 1; + b = b + 1; - $display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b)); + $display("a = %0d, b = %0d, %0d == %0d", a, b, $sampled(a), $sampled(b)); - if (b >= 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + if (b >= 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test1( - clk, a, b - ); +module Test1 ( + clk, + a, + b +); - input clk; - input [3:0] a, b; + input clk; + input [3:0] a, b; - assert property (@(posedge clk) $sampled(a) == $sampled(b)); + assert property (@(posedge clk) $sampled(a) == $sampled(b)); endmodule -module Test2( - clk, a, b - ); +module Test2 ( + clk, + a, + b +); - input clk; - input [3:0] a, b; + input clk; + input [3:0] a, b; - assert property (@(posedge clk) a == b); + assert property (@(posedge clk) a == b); endmodule -module Test3( - clk, a, b - ); +module Test3 ( + clk, + a, + b +); - input clk; - input [3:0] a, b; + input clk; + input [3:0] a, b; - int hits[10]; + int hits[10]; - assert property (@(posedge clk) a == b) hits[1]=1; - assert property (@(posedge clk) a == b) else hits[2]=1; - assert property (@(posedge clk) a == b) hits[3]=1; else hits[4]=1; + assert property (@(posedge clk) a == b) hits[1] = 1; + assert property (@(posedge clk) a == b) + else hits[2] = 1; + assert property (@(posedge clk) a == b) hits[3] = 1; + else hits[4] = 1; - assert property (@(posedge clk) a != b) hits[5]=1; - assert property (@(posedge clk) a != b) else hits[6]=1; - assert property (@(posedge clk) a != b) hits[7]=1; else hits[8]=1; + assert property (@(posedge clk) a != b) hits[5] = 1; + assert property (@(posedge clk) a != b) + else hits[6] = 1; + assert property (@(posedge clk) a != b) hits[7] = 1; + else hits[8] = 1; - final begin - `checkd(hits[1], 1); - `checkd(hits[2], 0); - `checkd(hits[3], 1); - `checkd(hits[4], 0); - `checkd(hits[5], 0); - `checkd(hits[6], 1); - `checkd(hits[7], 0); - `checkd(hits[8], 1); - end + final begin + `checkd(hits[1], 1); + `checkd(hits[2], 0); + `checkd(hits[3], 1); + `checkd(hits[4], 0); + `checkd(hits[5], 0); + `checkd(hits[6], 1); + `checkd(hits[7], 0); + `checkd(hits[8], 1); + end endmodule diff --git a/test_regress/t/t_assert_synth.v b/test_regress/t/t_assert_synth.v index fa9cff4f6..cf6f7aa7d 100644 --- a/test_regress/t/t_assert_synth.v +++ b/test_regress/t/t_assert_synth.v @@ -4,112 +4,109 @@ // SPDX-FileCopyrightText: 2005 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + reg a; initial a = 1'b1; + reg b_fc; initial b_fc = 1'b0; + reg b_pc; initial b_pc = 1'b0; + reg b_oh; initial b_oh = 1'b0; + reg b_oc; initial b_oc = 1'b0; + wire a_l = ~a; + wire b_oc_l = ~b_oc; - reg a; initial a = 1'b1; - reg b_fc; initial b_fc = 1'b0; - reg b_pc; initial b_pc = 1'b0; - reg b_oh; initial b_oh = 1'b0; - reg b_oc; initial b_oc = 1'b0; - wire a_l = ~a; - wire b_oc_l = ~b_oc; + // Note we must ensure that full, parallel, etc, only fire during + // edges (not mid-cycle), and must provide a way to turn them off. + // SystemVerilog provides: $asserton and $assertoff. - // Note we must ensure that full, parallel, etc, only fire during - // edges (not mid-cycle), and must provide a way to turn them off. - // SystemVerilog provides: $asserton and $assertoff. + // verilator lint_off CASEINCOMPLETE - // verilator lint_off CASEINCOMPLETE - - always @* begin - // Note not all tools support directives on casez's + always @* begin + // Note not all tools support directives on casez's `ifdef ATTRIBUTES - case ({a,b_fc}) // synopsys full_case + case ({a,b_fc}) // synopsys full_case `else - case ({a,b_fc}) + case ({a,b_fc}) `endif - 2'b0_0: ; - 2'b0_1: ; - 2'b1_0: ; - // Note no default - endcase - priority case ({a,b_fc}) - 2'b0_0: ; - 2'b0_1: ; - 2'b1_0: ; - // Note no default - endcase - end + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default + endcase + priority case ({a,b_fc}) + 2'b0_0: ; + 2'b0_1: ; + 2'b1_0: ; + // Note no default + endcase + end - always @* begin + always @* begin `ifdef ATTRIBUTES - case (1'b1) // synopsys full_case parallel_case + case (1'b1) // synopsys full_case parallel_case `else `ifdef FAILING_FULL - case (1'b1) // synopsys parallel_case + case (1'b1) // synopsys parallel_case `else - case (1'b1) // synopsys parallel_full + case (1'b1) // synopsys parallel_full `endif `endif - a: ; - b_pc: ; - endcase - end + a: ; + b_pc: ; + endcase + end `ifdef NOT_YET_VERILATOR // Unsupported - // ambit synthesis one_hot "a, b_oh" - // cadence one_cold "a_l, b_oc_l" + // ambit synthesis one_hot "a, b_oh" + // cadence one_cold "a_l, b_oc_l" `endif - integer cyc; initial cyc=1; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - if (cyc==1) begin - a <= 1'b1; - b_fc <= 1'b0; - b_pc <= 1'b0; - b_oh <= 1'b0; - b_oc <= 1'b0; - end - if (cyc==2) begin - a <= 1'b0; - b_fc <= 1'b1; - b_pc <= 1'b1; - b_oh <= 1'b1; - b_oc <= 1'b1; - end - if (cyc==3) begin - a <= 1'b1; - b_fc <= 1'b0; - b_pc <= 1'b0; - b_oh <= 1'b0; - b_oc <= 1'b0; - end - if (cyc==4) begin + integer cyc; initial cyc=1; + always @ (posedge clk) begin + if (cyc!=0) begin + cyc <= cyc + 1; + if (cyc==1) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==2) begin + a <= 1'b0; + b_fc <= 1'b1; + b_pc <= 1'b1; + b_oh <= 1'b1; + b_oc <= 1'b1; + end + if (cyc==3) begin + a <= 1'b1; + b_fc <= 1'b0; + b_pc <= 1'b0; + b_oh <= 1'b0; + b_oc <= 1'b0; + end + if (cyc==4) begin `ifdef FAILING_FULL - b_fc <= 1'b1; + b_fc <= 1'b1; `endif `ifdef FAILING_PARALLEL - b_pc <= 1'b1; + b_pc <= 1'b1; `endif `ifdef FAILING_OH - b_oh <= 1'b1; + b_oh <= 1'b1; `endif `ifdef FAILING_OC - b_oc <= 1'b1; + b_oc <= 1'b1; `endif - end - if (cyc==10) begin - $write("*-* All Finished *-*\n"); - $finish; - end end - end + if (cyc==10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + end initial begin : test_info $info ("Start of $info test"); diff --git a/test_regress/t/t_assert_synth_full.out b/test_regress/t/t_assert_synth_full.out index 2134d5a40..662534e16 100644 --- a/test_regress/t/t_assert_synth_full.out +++ b/test_regress/t/t_assert_synth_full.out @@ -1,6 +1,6 @@ -[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test -[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test -[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test -[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3' -%Error: t/t_assert_synth.v:31: Verilog $stop +[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test +[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test +[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test +[40] %Error: t_assert_synth.v:28: Assertion failed in top.t: synthesis full_case, but non-match found for '2'h3' +%Error: t/t_assert_synth.v:28: Verilog $stop Aborting... diff --git a/test_regress/t/t_assert_synth_full_vlt.out b/test_regress/t/t_assert_synth_full_vlt.out index a14c33995..4e1202d4b 100644 --- a/test_regress/t/t_assert_synth_full_vlt.out +++ b/test_regress/t/t_assert_synth_full_vlt.out @@ -1,6 +1,6 @@ -[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test -[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test -[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test -[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: priority case, but non-match found for '2'h3' -%Error: t/t_assert_synth.v:40: Verilog $stop +[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test +[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test +[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test +[40] %Error: t_assert_synth.v:37: Assertion failed in top.t: priority case, but non-match found for '2'h3' +%Error: t/t_assert_synth.v:37: Verilog $stop Aborting... diff --git a/test_regress/t/t_assert_synth_parallel.out b/test_regress/t/t_assert_synth_parallel.out index 2958bbba9..bbe98a077 100644 --- a/test_regress/t/t_assert_synth_parallel.out +++ b/test_regress/t/t_assert_synth_parallel.out @@ -1,6 +1,6 @@ -[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test -[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test -[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test -[40] %Error: t_assert_synth.v:50: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1' -%Error: t/t_assert_synth.v:50: Verilog $stop +[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test +[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test +[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test +[40] %Error: t_assert_synth.v:47: Assertion failed in top.t: synthesis full_case parallel_case, but multiple matches found for '1'h1' +%Error: t/t_assert_synth.v:47: Verilog $stop Aborting... diff --git a/test_regress/t/t_assert_synth_parallel.vlt b/test_regress/t/t_assert_synth_parallel.vlt index 566a0b9f7..c5824bdc5 100644 --- a/test_regress/t/t_assert_synth_parallel.vlt +++ b/test_regress/t/t_assert_synth_parallel.vlt @@ -6,4 +6,4 @@ `verilator_config -parallel_case -file "t/t_assert_synth.v" -lines 55 +parallel_case -file "t/t_assert_synth.v" -lines 52 diff --git a/test_regress/t/t_assert_synth_parallel_vlt.out b/test_regress/t/t_assert_synth_parallel_vlt.out index 41a1a77c4..14f9cc094 100644 --- a/test_regress/t/t_assert_synth_parallel_vlt.out +++ b/test_regress/t/t_assert_synth_parallel_vlt.out @@ -1,6 +1,6 @@ -[0] -Info: t_assert_synth.v:115: top.t.test_info: Start of $info test -[0] -Info: t_assert_synth.v:116: top.t.test_info: Middle of $info test -[0] -Info: t_assert_synth.v:117: top.t.test_info: End of $info test -[40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found for '1'h1' -%Error: t/t_assert_synth.v:55: Verilog $stop +[0] -Info: t_assert_synth.v:112: top.t.test_info: Start of $info test +[0] -Info: t_assert_synth.v:113: top.t.test_info: Middle of $info test +[0] -Info: t_assert_synth.v:114: top.t.test_info: End of $info test +[40] %Error: t_assert_synth.v:52: Assertion failed in top.t: synthesis parallel_case, but multiple matches found for '1'h1' +%Error: t/t_assert_synth.v:52: Verilog $stop Aborting... diff --git a/test_regress/t/t_assert_unique_case_bad.v b/test_regress/t/t_assert_unique_case_bad.v index 949ccd9c5..8f5cd8e8c 100644 --- a/test_regress/t/t_assert_unique_case_bad.v +++ b/test_regress/t/t_assert_unique_case_bad.v @@ -4,61 +4,61 @@ // SPDX-FileCopyrightText: 2024 Yutetsu TAKATSUKASA // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Outputs - hit, - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Outputs + hit, + // Inputs + clk +); - input clk; - output logic hit; + input clk; + output logic hit; - logic [31:0] addr; - logic [11:0] match_item0, match_item1; - int cyc; - string s; + logic [31:0] addr; + logic [11:0] match_item0, match_item1; + int cyc; + string s; - initial addr = 32'h380; + initial addr = 32'h380; - always @ (posedge clk) begin - cyc <= cyc + 1; - addr <= 32'h380 + cyc; - match_item0 = 12'h 380 + cyc[11:0]; - match_item1 = 12'h 390 - cyc[11:0]; - $sformat(s, "%1d", cyc); - if (cyc == 9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + addr <= 32'h380 + cyc; + match_item0 = 12'h380 + cyc[11:0]; + match_item1 = 12'h390 - cyc[11:0]; + $sformat(s, "%1d", cyc); + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - always_comb begin - hit = 1; - unique case (addr[11:0]) - match_item0: $display("match_item0"); - match_item1: $display("match_item1"); - default: hit = 0; - endcase - end + always_comb begin + hit = 1; + unique case (addr[11:0]) + match_item0: $display("match_item0"); + match_item1: $display("match_item1"); + default: hit = 0; + endcase + end `ifdef NO_STOP_FAIL - always_comb begin - unique case (s) - "": ; - "0": ; - "2": ; - "4": ; - "6": ; - endcase - end - always_comb begin - priority case (s) - $sformatf("%1d", cyc - 1): ; - "0": ; - "6": ; - endcase - end + always_comb begin + unique case (s) + "": ; + "0": ; + "2": ; + "4": ; + "6": ; + endcase + end + always_comb begin + priority case (s) + $sformatf("%1d", cyc - 1): ; + "0": ; + "6": ; + endcase + end `endif endmodule diff --git a/test_regress/t/t_assign_expr.v b/test_regress/t/t_assign_expr.v index ff551bc81..98ecc2759 100644 --- a/test_regress/t/t_assign_expr.v +++ b/test_regress/t/t_assign_expr.v @@ -4,76 +4,94 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int a; - int b; - int i; + int a; + int b; + int i; - // verilator lint_off ASSIGNEQEXPR - initial begin - a = 10; - i = (a = 2); - `checkd(a, 2); `checkd(i, 2); + // verilator lint_off ASSIGNEQEXPR + initial begin + a = 10; + i = (a = 2); + `checkd(a, 2); + `checkd(i, 2); - a = 10; - i = (a += 2); - `checkd(a, 12); `checkd(i, 12); + a = 10; + i = (a += 2); + `checkd(a, 12); + `checkd(i, 12); - a = 10; - i = (a -= 2); - `checkd(a, 8); `checkd(i, 8); + a = 10; + i = (a -= 2); + `checkd(a, 8); + `checkd(i, 8); - a = 10; - i = (a *= 2); - `checkd(a, 20); `checkd(i, 20); + a = 10; + i = (a *= 2); + `checkd(a, 20); + `checkd(i, 20); - a = 10; - i = (a /= 2); - `checkd(a, 5); `checkd(i, 5); + a = 10; + i = (a /= 2); + `checkd(a, 5); + `checkd(i, 5); - a = 11; - i = (a %= 2); - `checkd(a, 1); `checkd(i, 1); + a = 11; + i = (a %= 2); + `checkd(a, 1); + `checkd(i, 1); - a = 10; - i = (a &= 2); - `checkd(a, 2); `checkd(i, 2); + a = 10; + i = (a &= 2); + `checkd(a, 2); + `checkd(i, 2); - a = 8; - i = (a |= 2); - `checkd(a, 10); `checkd(i, 10); + a = 8; + i = (a |= 2); + `checkd(a, 10); + `checkd(i, 10); - a = 10; - i = (a ^= 2); - `checkd(a, 8); `checkd(i, 8); + a = 10; + i = (a ^= 2); + `checkd(a, 8); + `checkd(i, 8); - a = 10; - i = (a <<= 2); - `checkd(a, 40); `checkd(i, 40); + a = 10; + i = (a <<= 2); + `checkd(a, 40); + `checkd(i, 40); - a = 10; - i = (a >>= 2); - `checkd(a, 2); `checkd(i, 2); + a = 10; + i = (a >>= 2); + `checkd(a, 2); + `checkd(i, 2); - a = 10; - i = (a >>>= 2); - `checkd(a, 2); `checkd(i, 2); + a = 10; + i = (a >>>= 2); + `checkd(a, 2); + `checkd(i, 2); - a = 10; - i = (a = (b = 5)); - `checkd(a, 5); `checkd(i, 5); `checkd(b, 5); + a = 10; + i = (a = (b = 5)); + `checkd(a, 5); + `checkd(i, 5); + `checkd(b, 5); - a = 10; - b = 6; - i = ((a += (b += 1) + 1)); - `checkd(a, 18); `checkd(i, 18); `checkd(b, 7); + a = 10; + b = 6; + i = ((a += (b += 1) + 1)); + `checkd(a, 18); + `checkd(i, 18); + `checkd(b, 7); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assign_inline.v b/test_regress/t/t_assign_inline.v index f378db28e..ad22baf4a 100644 --- a/test_regress/t/t_assign_inline.v +++ b/test_regress/t/t_assign_inline.v @@ -4,50 +4,48 @@ // SPDX-FileCopyrightText: 2015 Mike Thyer // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - int cycle=0; + int cycle = 0; - // verilator lint_off UNOPTFLAT - reg [7:0] a_r; - wire [7:0] a_w; - reg [7:0] b_r; - reg [7:0] c_d_r, c_q_r; + // verilator lint_off UNOPTFLAT + reg [7:0] a_r; + wire [7:0] a_w; + reg [7:0] b_r; + reg [7:0] c_d_r, c_q_r; - assign a_w = a_r; + assign a_w = a_r; - always @(*) begin - a_r = 0; - b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete" - a_r = c_q_r; - c_d_r = c_q_r; - end + always @(*) begin + a_r = 0; + b_r = a_w; // Substituting the a_w assignment to get b_r = 0 is wrong, as a_r is not "complete" + a_r = c_q_r; + c_d_r = c_q_r; + end - // stimulus + checks - always @(posedge clk) begin - cycle <= cycle+1; - if (cycle==0) begin - c_q_r <= 8'b0; - end - else begin - c_q_r <= c_d_r+1; + // stimulus + checks + always @(posedge clk) begin + cycle <= cycle + 1; + if (cycle == 0) begin + c_q_r <= 8'b0; + end + else begin + c_q_r <= c_d_r + 1; `ifdef TEST_VERBOSE - $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same + $display("[%0t] a_r=%0d, b_r=%0d", $time, a_r, b_r); // a_r and b_r should always be the same `endif - end - if (cycle >= 10) begin - if (b_r==9) begin - $write("*-* All Finished *-*\n"); - $finish; - end - else begin - $stop; - end - end - end + end + if (cycle >= 10) begin + if (b_r == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + else begin + $stop; + end + end + end endmodule diff --git a/test_regress/t/t_assign_slice_overflow.v b/test_regress/t/t_assign_slice_overflow.v index 64b6fca2c..ed1af2f4d 100644 --- a/test_regress/t/t_assign_slice_overflow.v +++ b/test_regress/t/t_assign_slice_overflow.v @@ -23,157 +23,158 @@ // SPDX-FileCopyrightText: 2021 David Turner // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - // Non-constant offsets - reg varoffset1; - reg [6:0] varoffset2; - reg [6:0] varoffset3; + integer cyc = 0; + // Non-constant offsets + reg varoffset1; + reg [6:0] varoffset2; + reg [6:0] varoffset3; - // Destinations for variable-offset assignments - reg [69:0] dstwide1; - reg [69:0] dstwide2; - reg [1:0] dstnarrow; + // Destinations for variable-offset assignments + reg [69:0] dstwide1; + reg [69:0] dstwide2; + reg [1:0] dstnarrow; - // Constant offsets - reg [6:0] constoffset; + // Constant offsets + reg [6:0] constoffset; - // Destinations for constant-offset assignments - reg [2:0] dst_cdata; - reg [11:0] dst_sdata; - reg [29:0] dst_idata; - reg [59:0] dst_qdata; - reg [69:0] dst_wdata1; // assign idata within word - reg [69:0] dst_wdata2; // assign idata crossing word boundary - reg [69:0] dst_wdata3; // assign idata corresponding to whole word - reg [69:0] dst_wdata4; // assign qdata - reg [69:0] dst_wdata5; // assign wdata corresponding to several whole words - reg [69:0] dst_wdata6; // assign wdata starting at word-offset - reg [69:0] dst_wdata7; // assign wdata unaligned + // Destinations for constant-offset assignments + reg [2:0] dst_cdata; + reg [11:0] dst_sdata; + reg [29:0] dst_idata; + reg [59:0] dst_qdata; + reg [69:0] dst_wdata1; // assign idata within word + reg [69:0] dst_wdata2; // assign idata crossing word boundary + reg [69:0] dst_wdata3; // assign idata corresponding to whole word + reg [69:0] dst_wdata4; // assign qdata + reg [69:0] dst_wdata5; // assign wdata corresponding to several whole words + reg [69:0] dst_wdata6; // assign wdata starting at word-offset + reg [69:0] dst_wdata7; // assign wdata unaligned - always @(*) begin - // Non-constant select offset, destination narrow - dstnarrow = 2'd0; - dstnarrow[varoffset1 +: 2'd2] = 2'd2; + always @(*) begin + // Non-constant select offset, destination narrow + dstnarrow = 2'd0; + dstnarrow[varoffset1+:2'd2] = 2'd2; - // Non-constant select offset, destination wide, width == 1 - dstwide1 = 70'd0; - dstwide1[varoffset2 +: 1'd1] = 1'd1; + // Non-constant select offset, destination wide, width == 1 + dstwide1 = 70'd0; + dstwide1[varoffset2+:1'd1] = 1'd1; - // Non-constant select offset, destination wide, width != 1 - dstwide2 = 70'd0; - dstwide2[varoffset3 +: 2'd2] = 2'd2; + // Non-constant select offset, destination wide, width != 1 + dstwide2 = 70'd0; + dstwide2[varoffset3+:2'd2] = 2'd2; - // Constant offset, IData into CData - constoffset = 7'd2; - dst_cdata = 3'd0; - dst_cdata[constoffset[0 +: 2] +: 3'd3] = 3'd6; + // Constant offset, IData into CData + constoffset = 7'd2; + dst_cdata = 3'd0; + dst_cdata[constoffset[0+:2]+:3'd3] = 3'd6; - // Constant offset, IData into SData - constoffset = 7'd11; - dst_sdata = 12'd0; - dst_sdata[constoffset[0 +: 4] +: 2'd2] = 2'd2; + // Constant offset, IData into SData + constoffset = 7'd11; + dst_sdata = 12'd0; + dst_sdata[constoffset[0+:4]+:2'd2] = 2'd2; - // Constant offset, IData into IData - constoffset = 7'd29; - dst_idata = 30'd0; - dst_idata[constoffset[0 +: 5] +: 2'd2] = 2'd2; + // Constant offset, IData into IData + constoffset = 7'd29; + dst_idata = 30'd0; + dst_idata[constoffset[0+:5]+:2'd2] = 2'd2; - // Constant offset, QData into QData - constoffset = 7'd59; - dst_qdata = 60'd0; - dst_qdata[constoffset[0 +: 6] +: 2'd2] = 2'd2; + // Constant offset, QData into QData + constoffset = 7'd59; + dst_qdata = 60'd0; + dst_qdata[constoffset[0+:6]+:2'd2] = 2'd2; - // Constant offset, IData into WData within word - constoffset = 7'd69; - dst_wdata1 = 70'd0; - dst_wdata1[constoffset +: 2'd2] = 2'd2; + // Constant offset, IData into WData within word + constoffset = 7'd69; + dst_wdata1 = 70'd0; + dst_wdata1[constoffset+:2'd2] = 2'd2; - // Constant offset, IData into WData crossing word boundary - constoffset = 7'd61; - dst_wdata2 = 70'd0; - dst_wdata2[constoffset +: 4'd10] = 10'd1 << 4'd9; + // Constant offset, IData into WData crossing word boundary + constoffset = 7'd61; + dst_wdata2 = 70'd0; + dst_wdata2[constoffset+:4'd10] = 10'd1 << 4'd9; - // Constant offset, IData into WData replacing a whole word - constoffset = 7'd64; - dst_wdata3 = 70'd0; - dst_wdata3[constoffset +: 6'd32] = 32'd1 << 3'd6; + // Constant offset, IData into WData replacing a whole word + constoffset = 7'd64; + dst_wdata3 = 70'd0; + dst_wdata3[constoffset+:6'd32] = 32'd1 << 3'd6; - // Constant offset, QData into WData - constoffset = 7'd31; - dst_wdata4 = 70'd0; - dst_wdata4[constoffset +: 7'd40] = 40'd1 << 7'd39; + // Constant offset, QData into WData + constoffset = 7'd31; + dst_wdata4 = 70'd0; + dst_wdata4[constoffset+:7'd40] = 40'd1 << 7'd39; - // Constant offset, WData into WData replacing whole words - constoffset = 7'd32; - dst_wdata5 = 70'd0; - dst_wdata5[constoffset +: 7'd64] = 64'd1 << 7'd38; + // Constant offset, WData into WData replacing whole words + constoffset = 7'd32; + dst_wdata5 = 70'd0; + dst_wdata5[constoffset+:7'd64] = 64'd1 << 7'd38; - // Constant offset, WData into WData offset word aligned - constoffset = 7'd32; - dst_wdata6 = 70'd0; - dst_wdata6[constoffset +: 7'd40] = 40'd1 << 7'd38; + // Constant offset, WData into WData offset word aligned + constoffset = 7'd32; + dst_wdata6 = 70'd0; + dst_wdata6[constoffset+:7'd40] = 40'd1 << 7'd38; - // Constant offset, WData into WData unaligned - constoffset = 7'd1; - dst_wdata7 = 70'd0; - dst_wdata7[constoffset +: 7'd70] = 70'd1 << 7'd69; - end + // Constant offset, WData into WData unaligned + constoffset = 7'd1; + dst_wdata7 = 70'd0; + dst_wdata7[constoffset+:7'd70] = 70'd1 << 7'd69; + end - // Test loop - always @ (posedge clk) begin - // State machine to avoid verilator constant-folding offset - if (cyc == 0) begin - // Initialisation - varoffset1 <= 1'd0; - varoffset2 <= 7'd0; - varoffset3 <= 7'd0; - end else if (cyc == 1) begin - // Variable offsets set here to avoid verilator constant folding - varoffset1 <= 1'd1; - varoffset2 <= 7'd70; - varoffset3 <= 7'd69; - end else if (cyc == 2) begin - // Check all destinations are 0 - $write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1); - $write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1); - $write("dstnarrow = %23d, downshifted = %23d\n", dstnarrow, dstnarrow >> 1); - $write("dst_cdata = %23d, downshifted = %23d\n", dst_cdata, dst_cdata >> 1); - $write("dst_sdata = %23d, downshifted = %23d\n", dst_sdata, dst_sdata >> 1); - $write("dst_idata = %23d, downshifted = %23d\n", dst_idata, dst_idata >> 1); - $write("dst_qdata = %23d, downshifted = %23d\n", dst_qdata, dst_qdata >> 1); - $write("dst_wdata1 = %23d, downshifted = %23d\n", dst_wdata1, dst_wdata1 >> 1); - $write("dst_wdata2 = %23d, downshifted = %23d\n", dst_wdata2, dst_wdata2 >> 1); - $write("dst_wdata3 = %23d, downshifted = %23d\n", dst_wdata3, dst_wdata3 >> 1); - $write("dst_wdata4 = %23d, downshifted = %23d\n", dst_wdata4, dst_wdata4 >> 1); - $write("dst_wdata5 = %23d, downshifted = %23d\n", dst_wdata5, dst_wdata5 >> 1); - $write("dst_wdata6 = %23d, downshifted = %23d\n", dst_wdata6, dst_wdata6 >> 1); - $write("dst_wdata7 = %23d, downshifted = %23d\n", dst_wdata7, dst_wdata7 >> 1); + // Test loop + always @(posedge clk) begin + // State machine to avoid verilator constant-folding offset + if (cyc == 0) begin + // Initialisation + varoffset1 <= 1'd0; + varoffset2 <= 7'd0; + varoffset3 <= 7'd0; + end + else if (cyc == 1) begin + // Variable offsets set here to avoid verilator constant folding + varoffset1 <= 1'd1; + varoffset2 <= 7'd70; + varoffset3 <= 7'd69; + end + else if (cyc == 2) begin + // Check all destinations are 0 + $write("dstwide1 = %23d, downshifted = %23d\n", dstwide1, dstwide1 >> 1); + $write("dstwide2 = %23d, downshifted = %23d\n", dstwide2, dstwide2 >> 1); + $write("dstnarrow = %23d, downshifted = %23d\n", dstnarrow, dstnarrow >> 1); + $write("dst_cdata = %23d, downshifted = %23d\n", dst_cdata, dst_cdata >> 1); + $write("dst_sdata = %23d, downshifted = %23d\n", dst_sdata, dst_sdata >> 1); + $write("dst_idata = %23d, downshifted = %23d\n", dst_idata, dst_idata >> 1); + $write("dst_qdata = %23d, downshifted = %23d\n", dst_qdata, dst_qdata >> 1); + $write("dst_wdata1 = %23d, downshifted = %23d\n", dst_wdata1, dst_wdata1 >> 1); + $write("dst_wdata2 = %23d, downshifted = %23d\n", dst_wdata2, dst_wdata2 >> 1); + $write("dst_wdata3 = %23d, downshifted = %23d\n", dst_wdata3, dst_wdata3 >> 1); + $write("dst_wdata4 = %23d, downshifted = %23d\n", dst_wdata4, dst_wdata4 >> 1); + $write("dst_wdata5 = %23d, downshifted = %23d\n", dst_wdata5, dst_wdata5 >> 1); + $write("dst_wdata6 = %23d, downshifted = %23d\n", dst_wdata6, dst_wdata6 >> 1); + $write("dst_wdata7 = %23d, downshifted = %23d\n", dst_wdata7, dst_wdata7 >> 1); - if (dstwide1 !== 70'd0 || (dstwide1 >> 1) !== 70'd0) $stop; - if (dstwide2 !== 70'd0 || (dstwide2 >> 1) !== 70'd0) $stop; - if (dstnarrow !== 2'd0 || (dstnarrow >> 1) !== 2'd0) $stop; - if (dst_cdata !== 3'd0 || (dst_cdata >> 1) !== 3'd0) $stop; - if (dst_sdata !== 12'd0 || (dst_sdata >> 1) !== 12'd0) $stop; - if (dst_idata !== 30'd0 || (dst_idata >> 1) !== 30'd0) $stop; - if (dst_qdata !== 60'd0 || (dst_qdata >> 1) !== 60'd0) $stop; - if (dst_wdata1 !== 70'd0 || (dst_wdata1 >> 1) !== 70'd0) $stop; - if (dst_wdata2 !== 70'd0 || (dst_wdata2 >> 1) !== 70'd0) $stop; - if (dst_wdata3 !== 70'd0 || (dst_wdata3 >> 1) !== 70'd0) $stop; - if (dst_wdata4 !== 70'd0 || (dst_wdata4 >> 1) !== 70'd0) $stop; - if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop; - if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop; - if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop; - end else begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (dstwide1 !== 70'd0 || (dstwide1 >> 1) !== 70'd0) $stop; + if (dstwide2 !== 70'd0 || (dstwide2 >> 1) !== 70'd0) $stop; + if (dstnarrow !== 2'd0 || (dstnarrow >> 1) !== 2'd0) $stop; + if (dst_cdata !== 3'd0 || (dst_cdata >> 1) !== 3'd0) $stop; + if (dst_sdata !== 12'd0 || (dst_sdata >> 1) !== 12'd0) $stop; + if (dst_idata !== 30'd0 || (dst_idata >> 1) !== 30'd0) $stop; + if (dst_qdata !== 60'd0 || (dst_qdata >> 1) !== 60'd0) $stop; + if (dst_wdata1 !== 70'd0 || (dst_wdata1 >> 1) !== 70'd0) $stop; + if (dst_wdata2 !== 70'd0 || (dst_wdata2 >> 1) !== 70'd0) $stop; + if (dst_wdata3 !== 70'd0 || (dst_wdata3 >> 1) !== 70'd0) $stop; + if (dst_wdata4 !== 70'd0 || (dst_wdata4 >> 1) !== 70'd0) $stop; + if (dst_wdata5 !== 70'd0 || (dst_wdata5 >> 1) !== 70'd0) $stop; + if (dst_wdata6 !== 70'd0 || (dst_wdata6 >> 1) !== 70'd0) $stop; + if (dst_wdata7 !== 70'd0 || (dst_wdata7 >> 1) !== 70'd0) $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end - cyc <= cyc + 1; - end + cyc <= cyc + 1; + end endmodule diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.out b/test_regress/t/t_assigndly_dynamic_notiming_bad.out index 687d05541..9712a069f 100644 --- a/test_regress/t/t_assigndly_dynamic_notiming_bad.out +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.out @@ -1,6 +1,6 @@ -%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:11: Delayed assignment in a non-inlined function/task requires --timing - : ... note: In instance '$unit::Cls' - 10 | qux <= '1; - | ^~ +%Error-NOTIMING: t/t_assigndly_dynamic_notiming_bad.v:10:9: Delayed assignment in a non-inlined function/task requires --timing + : ... note: In instance '$unit::Cls' + 10 | qux <= '1; + | ^~ ... For error description see https://verilator.org/warn/NOTIMING?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assigndly_dynamic_notiming_bad.v b/test_regress/t/t_assigndly_dynamic_notiming_bad.v index 818f9378f..a089f302b 100644 --- a/test_regress/t/t_assigndly_dynamic_notiming_bad.v +++ b/test_regress/t/t_assigndly_dynamic_notiming_bad.v @@ -5,19 +5,19 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - task bar; - static int qux; - qux <= '1; - // Use qux to prevent V3Dead optimizations - $display("qux = %d\n", qux); - endtask + task bar; + static int qux; + qux <= '1; + // Use qux to prevent V3Dead optimizations + $display("qux = %d\n", qux); + endtask endclass module t; - initial begin - Cls c; - c.bar(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + c.bar(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assigndly_task.v b/test_regress/t/t_assigndly_task.v index 6a7f4f63b..c8570b0ab 100644 --- a/test_regress/t/t_assigndly_task.v +++ b/test_regress/t/t_assigndly_task.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 module t ( - input clk, - input [7:0] d, - input [2:0] a, - output [7:0] q + input clk, + input [7:0] d, + input [2:0] a, + output [7:0] q ); always_ff @(posedge clk) tick(a); diff --git a/test_regress/t/t_assoc.v b/test_regress/t/t_assoc.v index 1f9d9b5a9..dd47f92a1 100644 --- a/test_regress/t/t_assoc.v +++ b/test_regress/t/t_assoc.v @@ -4,149 +4,196 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - integer i; + integer i; - always @ (posedge clk) begin - cyc <= cyc + 1; - begin - // Type - typedef bit [3:0] nibble_t; - typedef string dict_t [nibble_t]; - dict_t a; - string b [nibble_t]; - nibble_t k; - string v; + always @(posedge clk) begin + cyc <= cyc + 1; + begin + // Type + typedef bit [3:0] nibble_t; + typedef string dict_t[nibble_t]; + dict_t a; + string b[nibble_t]; + nibble_t k; + string v; - a[4'd3] = "fooed"; - a[4'd2] = "bared"; - i = a.num(); `checkh(i, 2); - i = a.size; `checkh(i, 2); // Also checks no parens - v = a[4'd3]; `checks(v, "fooed"); - v = a[4'd2]; `checks(v, "bared"); - i = a.exists(4'd0); `checkh(i, 0); - if (a.exists(4'd0)) $stop; // Check no width warning - i = a.exists(4'd2); `checkh(i, 1); - if (!a.exists(4'd2)) $stop; // Check no width warning - i = a.first(k); `checkh(i, 1); `checks(k, 4'd2); - i = a.next(k); `checkh(i, 1); `checks(k, 4'd3); - i = a.next(k); `checkh(i, 0); - i = a.last(k); `checkh(i, 1); `checks(k, 4'd3); - i = a.prev(k); `checkh(i, 1); `checks(k, 4'd2); - i = a.prev(k); `checkh(i, 0); - `checkp(a, "'{'h2:\"bared\", 'h3:\"fooed\"}"); + a[4'd3] = "fooed"; + a[4'd2] = "bared"; + i = a.num(); + `checkh(i, 2); + i = a.size; + `checkh(i, 2); // Also checks no parens + v = a[4'd3]; + `checks(v, "fooed"); + v = a[4'd2]; + `checks(v, "bared"); + i = a.exists(4'd0); + `checkh(i, 0); + if (a.exists(4'd0)) $stop; // Check no width warning + i = a.exists(4'd2); + `checkh(i, 1); + if (!a.exists(4'd2)) $stop; // Check no width warning + i = a.first(k); + `checkh(i, 1); + `checks(k, 4'd2); + i = a.next(k); + `checkh(i, 1); + `checks(k, 4'd3); + i = a.next(k); + `checkh(i, 0); + i = a.last(k); + `checkh(i, 1); + `checks(k, 4'd3); + i = a.prev(k); + `checkh(i, 1); + `checks(k, 4'd2); + i = a.prev(k); + `checkh(i, 0); + `checkp(a, "'{'h2:\"bared\", 'h3:\"fooed\"}"); - a.first(k); `checks(k, 4'd2); - a.next(k); `checks(k, 4'd3); - a.next(k); - a.last(k); `checks(k, 4'd3); - a.prev(k); `checks(k, 4'd2); + a.first(k); + `checks(k, 4'd2); + a.next(k); + `checks(k, 4'd3); + a.next(k); + a.last(k); + `checks(k, 4'd3); + a.prev(k); + `checks(k, 4'd2); - a.delete(4'd2); - i = a.size(); `checkh(i, 1); + a.delete(4'd2); + i = a.size(); + `checkh(i, 1); - b = a; // Copy assignment - i = b.size(); `checkh(i, 1); - end + b = a; // Copy assignment + i = b.size(); + `checkh(i, 1); + end - begin - // Strings - string a [string]; - string k; - string v; + begin + // Strings + string a[string]; + string k; + string v; - a["foo"] = "fooed"; - a["bar"] = "bared"; - i = a.num(); `checkh(i, 2); - i = a.size(); `checkh(i, 2); - v = a["foo"]; `checks(v, "fooed"); - v = a["bar"]; `checks(v, "bared"); - i = a.exists("baz"); `checkh(i, 0); - i = a.exists("bar"); `checkh(i, 1); - i = a.first(k); `checkh(i, 1); `checks(k, "bar"); - i = a.next(k); `checkh(i, 1); `checks(k, "foo"); - i = a.next(k); `checkh(i, 0); - i = a.last(k); `checkh(i, 1); `checks(k, "foo"); - i = a.prev(k); `checkh(i, 1); `checks(k, "bar"); - i = a.prev(k); `checkh(i, 0); - `checkp(a["foo"], "\"fooed\""); - `checkp(a, "'{\"bar\":\"bared\", \"foo\":\"fooed\"}"); + a["foo"] = "fooed"; + a["bar"] = "bared"; + i = a.num(); + `checkh(i, 2); + i = a.size(); + `checkh(i, 2); + v = a["foo"]; + `checks(v, "fooed"); + v = a["bar"]; + `checks(v, "bared"); + i = a.exists("baz"); + `checkh(i, 0); + i = a.exists("bar"); + `checkh(i, 1); + i = a.first(k); + `checkh(i, 1); + `checks(k, "bar"); + i = a.next(k); + `checkh(i, 1); + `checks(k, "foo"); + i = a.next(k); + `checkh(i, 0); + i = a.last(k); + `checkh(i, 1); + `checks(k, "foo"); + i = a.prev(k); + `checkh(i, 1); + `checks(k, "bar"); + i = a.prev(k); + `checkh(i, 0); + `checkp(a["foo"], "\"fooed\""); + `checkp(a, "'{\"bar\":\"bared\", \"foo\":\"fooed\"}"); - a.delete("bar"); - i = a.size(); `checkh(i, 1); - a.delete(); - i = a.size(); `checkh(i, 0); - i = a.first(k); `checkh(i, 0); - i = a.last(k); `checkh(i, 0); + a.delete("bar"); + i = a.size(); + `checkh(i, 1); + a.delete(); + i = a.size(); + `checkh(i, 0); + i = a.first(k); + `checkh(i, 0); + i = a.last(k); + `checkh(i, 0); - // Patterns & default - a = '{ "f": "fooed", "b": "bared", default: "defaulted" }; - i = a.size(); `checkh(i, 2); // Default doesn't count - v = a["f"]; `checks(v, "fooed"); - v = a["b"]; `checks(v, "bared"); - v = a["NEXISTS"]; `checks(v, "defaulted"); + // Patterns & default + a = '{"f": "fooed", "b": "bared", default: "defaulted"}; + i = a.size(); + `checkh(i, 2); // Default doesn't count + v = a["f"]; + `checks(v, "fooed"); + v = a["b"]; + `checks(v, "bared"); + v = a["NEXISTS"]; + `checks(v, "defaulted"); - a = '{}; - i = a.size(); `checkh(i, 0); - end + a = '{}; + i = a.size(); + `checkh(i, 0); + end - begin - // Wide-wides - need special array container classes, ick. - logic [91:2] a [ logic [65:1] ]; - int b [ bit [99:0] ]; - a[~65'hfe] = ~ 90'hfee; - `checkh(a[~65'hfe], ~ 90'hfee); - b[100'b1] = 1; - `checkh(b[100'b1], 1); - end + begin + // Wide-wides - need special array container classes, ick. + logic [91:2] a[logic [65:1]]; + int b[bit [99:0]]; + a[~65'hfe] = ~90'hfee; + `checkh(a[~65'hfe], ~90'hfee); + b[100'b1] = 1; + `checkh(b[100'b1], 1); + end - begin - int a [string]; - int sum; - sum = 0; - a["one"] = 1; - a["two"] = 2; - foreach (a[i]) sum += a[i]; - `checkh(sum, 1 + 2); - end + begin + int a[string]; + int sum; + sum = 0; + a["one"] = 1; + a["two"] = 2; + foreach (a[i]) sum += a[i]; + `checkh(sum, 1 + 2); + end - begin // Issue #5435 - int a; - int ok; - int dict [int]; + begin // Issue #5435 + int a; + int ok; + int dict[int]; - dict[3] = 'h13; - dict[4] = 'h14; - dict[5] = 'h15; + dict[3] = 'h13; + dict[4] = 'h14; + dict[5] = 'h15; - a = 4; - ok = dict.first(a); - if (a != 3) $stop; - if (ok != 1) $stop; - a = 4; - ok = dict.next(a); - if (a != 5) $stop; - if (ok != 1) $stop; - a = 4; - ok = dict.last(a); - if (a != 5) $stop; - if (ok != 1) $stop; - end + a = 4; + ok = dict.first(a); + if (a != 3) $stop; + if (ok != 1) $stop; + a = 4; + ok = dict.next(a); + if (a != 5) $stop; + if (ok != 1) $stop; + a = 4; + ok = dict.last(a); + if (a != 5) $stop; + if (ok != 1) $stop; + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assoc2.v b/test_regress/t/t_assoc2.v index 42deb93c1..5601e54df 100644 --- a/test_regress/t/t_assoc2.v +++ b/test_regress/t/t_assoc2.v @@ -4,45 +4,45 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - int imap[int]; + int imap[int]; - // associative array of an associative array - logic [31:0] a [logic [31:0]][logic [63:0]]; + // associative array of an associative array + logic [31:0] a[logic [31:0]][logic [63:0]]; - task static disp(); - int i = 60; - imap[i++] = 600; - imap[i++] = 601; - foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]); - endtask + task static disp(); + int i = 60; + imap[i++] = 600; + imap[i++] = 601; + foreach (imap[k]) $display("imap[%0d] = %0d", k, imap[k]); + endtask - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 1) begin - a[5][8] = 8; - a[5][9] = 9; - imap[10] = 100; - imap[11] = 101; - end - else if (cyc == 2) begin - `checkh(a[5][8], 8); - `checkh(a[5][9], 9); - disp(); - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 1) begin + a[5][8] = 8; + a[5][9] = 9; + imap[10] = 100; + imap[11] = 101; + end + else if (cyc == 2) begin + `checkh(a[5][8], 8); + `checkh(a[5][9], 9); + disp(); + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_assoc_compare.v b/test_regress/t/t_assoc_compare.v index ce4923359..d25036970 100644 --- a/test_regress/t/t_assoc_compare.v +++ b/test_regress/t/t_assoc_compare.v @@ -4,64 +4,66 @@ // SPDX-FileCopyrightText: 2023 Ilya Barkov // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define check_comp(lhs, rhs, op, exp) if ((exp) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (exp)); `stop; end +`define check_comp(lhs, rhs, op, expv) if ((expv) != ((lhs) op (rhs))) begin $write("%%Error: %s:%0d: op comparison shall return 'b%x\n", `__FILE__, `__LINE__, (expv)); `stop; end // Two checks because == and != may not be derived from each other `define check_eq(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b1) `check_comp(lhs, rhs, !=, 1'b0) `define check_ne(lhs, rhs) `check_comp(lhs, rhs, ==, 1'b0) `check_comp(lhs, rhs, !=, 1'b1) +// verilog_format: on class Cls; - int i; + int i; endclass module t; - initial begin - begin // simple case - int assoc1[int]; - int assoc2[int]; - // Empty are equal - `check_eq(assoc1, assoc2) - // Make different - assoc1[10] = 15; - assoc2[-1] = 365; - `check_ne(assoc1, assoc2) - // Make same - assoc1[-1] = 365; - assoc2[10] = 15; - `check_eq(assoc1, assoc2) - // Don't actually change - assoc1[-1] = 365; - `check_eq(assoc1, assoc2) - // Compare different sizes - assoc1[3] = 0; - `check_ne(assoc1, assoc2) - end - begin // check that a class as key is fine - int assoc1[Cls]; - int assoc2[Cls]; - automatic Cls a = new; - automatic Cls b = new; - int t; - assoc1[a] = 0; - `check_ne(assoc1, assoc2) - assoc2[a] = 0; - `check_eq(assoc1, assoc2) - assoc2.delete(a); - assoc2[b] = 0; - `check_ne(assoc1, assoc2) - end - begin // check that a class as value is fine - Cls assoc1[int]; - Cls assoc2[int]; - automatic Cls a = new; - automatic Cls b = new; - assoc1[1] = a; - assoc2[1] = b; - `check_ne(assoc1, assoc2) - assoc2[1] = a; - `check_eq(assoc1, assoc2) - end - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + begin // simple case + int assoc1[int]; + int assoc2[int]; + // Empty are equal + `check_eq(assoc1, assoc2) + // Make different + assoc1[10] = 15; + assoc2[-1] = 365; + `check_ne(assoc1, assoc2) + // Make same + assoc1[-1] = 365; + assoc2[10] = 15; + `check_eq(assoc1, assoc2) + // Don't actually change + assoc1[-1] = 365; + `check_eq(assoc1, assoc2) + // Compare different sizes + assoc1[3] = 0; + `check_ne(assoc1, assoc2) + end + begin // check that a class as key is fine + int assoc1[Cls]; + int assoc2[Cls]; + automatic Cls a = new; + automatic Cls b = new; + int t; + assoc1[a] = 0; + `check_ne(assoc1, assoc2) + assoc2[a] = 0; + `check_eq(assoc1, assoc2) + assoc2.delete(a); + assoc2[b] = 0; + `check_ne(assoc1, assoc2) + end + begin // check that a class as value is fine + Cls assoc1[int]; + Cls assoc2[int]; + automatic Cls a = new; + automatic Cls b = new; + assoc1[1] = a; + assoc2[1] = b; + `check_ne(assoc1, assoc2) + assoc2[1] = a; + `check_eq(assoc1, assoc2) + end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assoc_enum.v b/test_regress/t/t_assoc_enum.v index 79de64a4d..3ae1af9f8 100644 --- a/test_regress/t/t_assoc_enum.v +++ b/test_regress/t/t_assoc_enum.v @@ -11,25 +11,31 @@ // verilog_format: on class X; - typedef enum int { - INITIAL, RUNNING, SUSPENDED, COMPLETING, DONE - } state_t; + typedef enum int { + INITIAL, + RUNNING, + SUSPENDED, + COMPLETING, + DONE + } state_t; - static string state_names[state_t] = '{ - INITIAL: "INITIAL", - RUNNING: "RUNNING", - SUSPENDED: "SUSPENDED", - COMPLETING: "COMPLETING", - DONE: "DONE" - }; - protected state_t state; + static + string + state_names[state_t] = '{ + INITIAL: "INITIAL", + RUNNING: "RUNNING", + SUSPENDED: "SUSPENDED", + COMPLETING: "COMPLETING", + DONE: "DONE" + }; + protected state_t state; - function new(); - this.state = INITIAL; - `checks(state_names[this.state], "INITIAL"); - this.state = RUNNING; - `checks(state_names[this.state], "RUNNING"); - endfunction + function new(); + this.state = INITIAL; + `checks(state_names[this.state], "INITIAL"); + this.state = RUNNING; + `checks(state_names[this.state], "RUNNING"); + endfunction endclass diff --git a/test_regress/t/t_assoc_method.v b/test_regress/t/t_assoc_method.v index cadc9809b..82e4970a6 100644 --- a/test_regress/t/t_assoc_method.v +++ b/test_regress/t/t_assoc_method.v @@ -4,10 +4,11 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); - +// verilog_format: on module t; typedef struct {int x, y;} point; @@ -51,7 +52,7 @@ module t; points_q[1] = point'{2, 4}; points_q[5] = point'{1, 4}; - points_qv = points_q.unique(p) with (p.x); + points_qv = points_q.unique(p) with (p.x); `checkh(points_qv.size, 2); qi = points_q.unique_index (p) with (p.x + p.y); qi.sort; @@ -189,7 +190,7 @@ module t; i = qe.xor(); `checkh(i, 32'b0); - q = '{10: 1, 11: 2}; + q = '{10: 1, 11: 2}; qe = '{10: 1, 11: 2}; `checkh(q == qe, 1'b1); `checkh(q != qe, 1'b0); diff --git a/test_regress/t/t_assoc_method_bad.out b/test_regress/t/t_assoc_method_bad.out index 101bd8f61..6d4dc09c5 100644 --- a/test_regress/t/t_assoc_method_bad.out +++ b/test_regress/t/t_assoc_method_bad.out @@ -1,67 +1,67 @@ -%Error: t/t_assoc_method_bad.v:14:13: The 1 arguments passed to .num method does not match its requiring 0 arguments +%Error: t/t_assoc_method_bad.v:14:11: The 1 arguments passed to .num method does not match its requiring 0 arguments : ... note: In instance 't' - 14 | v = a.num("badarg"); - | ^~~ + 14 | v = a.num("badarg"); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_assoc_method_bad.v:15:13: The 1 arguments passed to .size method does not match its requiring 0 arguments +%Error: t/t_assoc_method_bad.v:15:11: The 1 arguments passed to .size method does not match its requiring 0 arguments : ... note: In instance 't' - 15 | v = a.size("badarg"); - | ^~~~ -%Error: t/t_assoc_method_bad.v:16:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments + 15 | v = a.size("badarg"); + | ^~~~ +%Error: t/t_assoc_method_bad.v:16:11: The 0 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' - 16 | v = a.exists(); - | ^~~~~~ -%Error: t/t_assoc_method_bad.v:17:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments + 16 | v = a.exists(); + | ^~~~~~ +%Error: t/t_assoc_method_bad.v:17:11: The 2 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' - 17 | v = a.exists(k, "bad2"); - | ^~~~~~ -%Error: t/t_assoc_method_bad.v:18:13: The 0 arguments passed to .first method does not match its requiring 1 arguments + 17 | v = a.exists(k, "bad2"); + | ^~~~~~ +%Error: t/t_assoc_method_bad.v:18:11: The 0 arguments passed to .first method does not match its requiring 1 arguments : ... note: In instance 't' - 18 | v = a.first(); - | ^~~~~ -%Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:13: Unsupported: Non-variable on LHS of built-in method 'first' + 18 | v = a.first(); + | ^~~~~ +%Error-UNSUPPORTED: t/t_assoc_method_bad.v:18:11: Unsupported: Non-variable on LHS of built-in method 'first' : ... note: In instance 't' - 18 | v = a.first(); - | ^~~~~ + 18 | v = a.first(); + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error: t/t_assoc_method_bad.v:19:13: The 2 arguments passed to .next method does not match its requiring 1 arguments +%Error: t/t_assoc_method_bad.v:19:11: The 2 arguments passed to .next method does not match its requiring 1 arguments : ... note: In instance 't' - 19 | v = a.next(k, "bad2"); - | ^~~~ -%Error: t/t_assoc_method_bad.v:20:13: The 0 arguments passed to .last method does not match its requiring 1 arguments + 19 | v = a.next(k, "bad2"); + | ^~~~ +%Error: t/t_assoc_method_bad.v:20:11: The 0 arguments passed to .last method does not match its requiring 1 arguments : ... note: In instance 't' - 20 | v = a.last(); - | ^~~~ -%Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:13: Unsupported: Non-variable on LHS of built-in method 'last' + 20 | v = a.last(); + | ^~~~ +%Error-UNSUPPORTED: t/t_assoc_method_bad.v:20:11: Unsupported: Non-variable on LHS of built-in method 'last' : ... note: In instance 't' - 20 | v = a.last(); - | ^~~~ -%Error: t/t_assoc_method_bad.v:21:13: The 2 arguments passed to .prev method does not match its requiring 1 arguments + 20 | v = a.last(); + | ^~~~ +%Error: t/t_assoc_method_bad.v:21:11: The 2 arguments passed to .prev method does not match its requiring 1 arguments : ... note: In instance 't' - 21 | v = a.prev(k, "bad2"); - | ^~~~ -%Error: t/t_assoc_method_bad.v:22:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments + 21 | v = a.prev(k, "bad2"); + | ^~~~ +%Error: t/t_assoc_method_bad.v:22:7: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments : ... note: In instance 't' - 22 | a.delete(k, "bad2"); - | ^~~~~~ -%Error: t/t_assoc_method_bad.v:24:9: Array method 'sort' not legal on associative arrays + 22 | a.delete(k, "bad2"); + | ^~~~~~ +%Error: t/t_assoc_method_bad.v:24:7: Array method 'sort' not legal on associative arrays : ... note: In instance 't' - 24 | a.sort; - | ^~~~ -%Error: t/t_assoc_method_bad.v:25:9: Array method 'rsort' not legal on associative arrays + 24 | a.sort; + | ^~~~ +%Error: t/t_assoc_method_bad.v:25:7: Array method 'rsort' not legal on associative arrays : ... note: In instance 't' - 25 | a.rsort; - | ^~~~~ -%Error: t/t_assoc_method_bad.v:26:9: Array method 'reverse' not legal on associative arrays + 25 | a.rsort; + | ^~~~~ +%Error: t/t_assoc_method_bad.v:26:7: Array method 'reverse' not legal on associative arrays : ... note: In instance 't' - 26 | a.reverse; - | ^~~~~~~ -%Error: t/t_assoc_method_bad.v:27:9: Array method 'shuffle' not legal on associative arrays + 26 | a.reverse; + | ^~~~~~~ +%Error: t/t_assoc_method_bad.v:27:7: Array method 'shuffle' not legal on associative arrays : ... note: In instance 't' - 27 | a.shuffle; - | ^~~~~~~ -%Error: t/t_assoc_method_bad.v:29:9: Unknown built-in associative array method 'bad_not_defined' + 27 | a.shuffle; + | ^~~~~~~ +%Error: t/t_assoc_method_bad.v:29:7: Unknown built-in associative array method 'bad_not_defined' : ... note: In instance 't' - 29 | a.bad_not_defined(); - | ^~~~~~~~~~~~~~~ + 29 | a.bad_not_defined(); + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assoc_method_bad.v b/test_regress/t/t_assoc_method_bad.v index a2dabc4ea..c118ec531 100644 --- a/test_regress/t/t_assoc_method_bad.v +++ b/test_regress/t/t_assoc_method_bad.v @@ -6,26 +6,26 @@ module t; - initial begin - string a [string]; - string k; - string v; + initial begin + string a[string]; + string k; + string v; - v = a.num("badarg"); - v = a.size("badarg"); - v = a.exists(); // Bad - v = a.exists(k, "bad2"); - v = a.first(); // Bad - v = a.next(k, "bad2"); // Bad - v = a.last(); // Bad - v = a.prev(k, "bad2"); // Bad - a.delete(k, "bad2"); + v = a.num("badarg"); + v = a.size("badarg"); + v = a.exists(); // Bad + v = a.exists(k, "bad2"); + v = a.first(); // Bad + v = a.next(k, "bad2"); // Bad + v = a.last(); // Bad + v = a.prev(k, "bad2"); // Bad + a.delete(k, "bad2"); - a.sort; // Not legal on assoc - a.rsort; // Not legal on assoc - a.reverse; // Not legal on assoc - a.shuffle; // Not legal on assoc + a.sort; // Not legal on assoc + a.rsort; // Not legal on assoc + a.reverse; // Not legal on assoc + a.shuffle; // Not legal on assoc - a.bad_not_defined(); - end + a.bad_not_defined(); + end endmodule diff --git a/test_regress/t/t_assoc_method_map.out b/test_regress/t/t_assoc_method_map.out index 61d553d8b..62dd71bbc 100644 --- a/test_regress/t/t_assoc_method_map.out +++ b/test_regress/t/t_assoc_method_map.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_assoc_method_map.v:17:15: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5) +%Error-UNSUPPORTED: t/t_assoc_method_map.v:19:13: Unsupported: Associative array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' - 17 | res = a.map(el) with (el == 2); - | ^~~ + 19 | res = a.map(el) with (el == 2); + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assoc_method_map.v b/test_regress/t/t_assoc_method_map.v index c01a19a30..829b0baaf 100644 --- a/test_regress/t/t_assoc_method_map.v +++ b/test_regress/t/t_assoc_method_map.v @@ -4,20 +4,22 @@ // SPDX-FileCopyrightText: 2024 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - initial begin - automatic int res[]; - automatic int a[int] = '{1: 100, 2: 200, 3: 300}; + initial begin + automatic int res[]; + automatic int a[int] = '{1: 100, 2: 200, 3: 300}; - // TODO results not known to be correct - res = a.map(el) with (el == 2); - `checkh(res.size, 3); - `checkh(res[0], 0); - `checkh(res[1], 1); - `checkh(res[2], 0); - end + // TODO results not known to be correct + res = a.map(el) with (el == 2); + `checkh(res.size, 3); + `checkh(res[0], 0); + `checkh(res[1], 1); + `checkh(res[2], 0); + end endmodule diff --git a/test_regress/t/t_assoc_ref_type.v b/test_regress/t/t_assoc_ref_type.v index 276f98893..3b2f83dce 100644 --- a/test_regress/t/t_assoc_ref_type.v +++ b/test_regress/t/t_assoc_ref_type.v @@ -5,87 +5,91 @@ // SPDX-License-Identifier: CC0-1.0 class Foo1; - int x = 1; - function int get_x; - return x; - endfunction + int x = 1; + function int get_x; + return x; + endfunction endclass class Foo2; - int x = 2; - function int get_x; - return x; - endfunction + int x = 2; + function int get_x; + return x; + endfunction endclass class Bar; - typedef Foo1 foo_t; - protected foo_t m_dict[int]; + typedef Foo1 foo_t; + protected foo_t m_dict[int]; - function void set(int key); - foo_t default_value = new; - m_dict[key] = default_value; - endfunction - function foo_t get(int key); - return m_dict[key]; - endfunction + function void set(int key); + foo_t default_value = new; + m_dict[key] = default_value; + endfunction + function foo_t get(int key); + return m_dict[key]; + endfunction endclass -class Baz #(type T=Foo1); +class Baz #( + type T = Foo1 +); protected T m_dict[int]; function void set(int key); - T default_value = new; - m_dict[key] = default_value; - endfunction - function T get(int key); - return m_dict[key]; - endfunction + T default_value = new; + m_dict[key] = default_value; + endfunction + function T get(int key); + return m_dict[key]; + endfunction endclass class WBase; endclass -class Wrapper#(type VAL_T=int); - VAL_T value; +class Wrapper #( + type VAL_T = int +); + VAL_T value; endclass class Bum; - typedef int map_t[string]; - map_t m_value; - function new(map_t value); - m_value = value; - endfunction + typedef int map_t[string]; + map_t m_value; + function new(map_t value); + m_value = value; + endfunction endclass module t; - typedef WBase wrap_map_t[string]; - typedef WBase wrap_queue_t[$]; + typedef WBase wrap_map_t[string]; + typedef WBase wrap_queue_t[$]; - localparam string str_key = "the_key"; + localparam string str_key = "the_key"; - initial begin - automatic Bar bar_i = new; - automatic Baz baz_1_i = new; - automatic Baz #(Foo2) baz_2_i = new; - automatic Bum bum_i; + initial begin + automatic Bar bar_i = new; + automatic Baz baz_1_i = new; + automatic Baz #(Foo2) baz_2_i = new; + automatic Bum bum_i; - automatic Wrapper#(wrap_map_t) wrap_map = new(); - automatic Wrapper#(wrap_queue_t) wrap_queue = new(); + automatic Wrapper #(wrap_map_t) wrap_map = new(); + automatic Wrapper #(wrap_queue_t) wrap_queue = new(); - bar_i.set(1); - baz_1_i.set(2); - baz_2_i.set(3); + bar_i.set(1); + baz_1_i.set(2); + baz_2_i.set(3); - if (bar_i.get(1).get_x() != 1) $stop; - if (baz_1_i.get(2).get_x() != 1) $stop; - if (baz_2_i.get(3).get_x() != 2) $stop; + if (bar_i.get(1).get_x() != 1) $stop; + if (baz_1_i.get(2).get_x() != 1) $stop; + if (baz_2_i.get(3).get_x() != 2) $stop; - bum_i = new('{str_key: 42}); - if (bum_i.m_value["the_key"] != 42) $stop; + bum_i = new('{str_key: 42}); + if (bum_i.m_value["the_key"] != 42) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assoc_wildcard.v b/test_regress/t/t_assoc_wildcard.v index 002ae3549..257b579da 100644 --- a/test_regress/t/t_assoc_wildcard.v +++ b/test_regress/t/t_assoc_wildcard.v @@ -4,51 +4,63 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; + integer cyc = 0; - integer i; + integer i; - always @ (posedge clk) begin - cyc <= cyc + 1; - begin - // Wildcard - typedef string dict_t [*]; - static string a [*] = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; - static dict_t b = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; - int k; - string v; + always @(posedge clk) begin + cyc <= cyc + 1; + begin + // Wildcard + typedef string dict_t [*]; + static string a [*] = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; + static dict_t b = '{default: "nope", "BBBBB": "fooing", 23'h434343: "baring"}; + int k; + string v; - v = b["CCC"]; `checks(v, "baring"); - v = b["BBBBB"]; `checks(v, "fooing"); + v = b["CCC"]; + `checks(v, "baring"); + v = b["BBBBB"]; + `checks(v, "fooing"); - v = a["CCC"]; `checks(v, "baring"); - v = a["BBBBB"]; `checks(v, "fooing"); + v = a["CCC"]; + `checks(v, "baring"); + v = a["BBBBB"]; + `checks(v, "fooing"); - a[32'd1234] = "fooed"; - a[4'd3] = "bared"; - a[79'h4141] = "bazed"; - i = a.num(); `checkh(i, 5); - i = a.size(); `checkh(i, 5); - v = a[39'd1234]; `checks(v, "fooed"); - v = a["AA"]; `checks(v, "bazed"); - v = a[4'd3]; `checks(v, "bared"); - i = a.exists("baz"); `checkh(i, 0); - i = a.exists(4'd3); `checkh(i, 1); - a.delete(4'd3); - i = a.size(); `checkh(i, 4); - end + a[32'd1234] = "fooed"; + a[4'd3] = "bared"; + a[79'h4141] = "bazed"; + i = a.num(); + `checkh(i, 5); + i = a.size(); + `checkh(i, 5); + v = a[39'd1234]; + `checks(v, "fooed"); + v = a["AA"]; + `checks(v, "bazed"); + v = a[4'd3]; + `checks(v, "bared"); + i = a.exists("baz"); + `checkh(i, 0); + i = a.exists(4'd3); + `checkh(i, 1); + a.delete(4'd3); + i = a.size(); + `checkh(i, 4); + end - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_assoc_wildcard_bad.out b/test_regress/t/t_assoc_wildcard_bad.out index a76182730..58322f10b 100644 --- a/test_regress/t/t_assoc_wildcard_bad.out +++ b/test_regress/t/t_assoc_wildcard_bad.out @@ -1,78 +1,78 @@ -%Error: t/t_assoc_wildcard_bad.v:23:13: The 1 arguments passed to .num method does not match its requiring 0 arguments +%Error: t/t_assoc_wildcard_bad.v:23:11: The 1 arguments passed to .num method does not match its requiring 0 arguments : ... note: In instance 't' - 23 | v = a.num("badarg"); - | ^~~ + 23 | v = a.num("badarg"); + | ^~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_assoc_wildcard_bad.v:24:13: The 1 arguments passed to .size method does not match its requiring 0 arguments +%Error: t/t_assoc_wildcard_bad.v:24:11: The 1 arguments passed to .size method does not match its requiring 0 arguments : ... note: In instance 't' - 24 | v = a.size("badarg"); - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:25:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments + 24 | v = a.size("badarg"); + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:25:11: The 0 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' - 25 | v = a.exists(); - | ^~~~~~ -%Error: t/t_assoc_wildcard_bad.v:26:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments + 25 | v = a.exists(); + | ^~~~~~ +%Error: t/t_assoc_wildcard_bad.v:26:11: The 2 arguments passed to .exists method does not match its requiring 1 arguments : ... note: In instance 't' - 26 | v = a.exists(k, "bad2"); - | ^~~~~~ -%Error: t/t_assoc_wildcard_bad.v:27:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments + 26 | v = a.exists(k, "bad2"); + | ^~~~~~ +%Error: t/t_assoc_wildcard_bad.v:27:7: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments : ... note: In instance 't' - 27 | a.delete(k, "bad2"); - | ^~~~~~ -%Error: t/t_assoc_wildcard_bad.v:29:9: Array method 'sort' not legal on associative arrays + 27 | a.delete(k, "bad2"); + | ^~~~~~ +%Error: t/t_assoc_wildcard_bad.v:29:7: Array method 'sort' not legal on associative arrays : ... note: In instance 't' - 29 | a.sort; - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:30:9: Array method 'rsort' not legal on associative arrays + 29 | a.sort; + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:30:7: Array method 'rsort' not legal on associative arrays : ... note: In instance 't' - 30 | a.rsort; - | ^~~~~ -%Error: t/t_assoc_wildcard_bad.v:31:9: Array method 'reverse' not legal on associative arrays + 30 | a.rsort; + | ^~~~~ +%Error: t/t_assoc_wildcard_bad.v:31:7: Array method 'reverse' not legal on associative arrays : ... note: In instance 't' - 31 | a.reverse; - | ^~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:32:9: Array method 'shuffle' not legal on associative arrays + 31 | a.reverse; + | ^~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:32:7: Array method 'shuffle' not legal on associative arrays : ... note: In instance 't' - 32 | a.shuffle; - | ^~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:34:9: Array method 'first' not legal on wildcard associative arrays + 32 | a.shuffle; + | ^~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:34:7: Array method 'first' not legal on wildcard associative arrays : ... note: In instance 't' - 34 | a.first; - | ^~~~~ -%Error: t/t_assoc_wildcard_bad.v:35:9: Array method 'last' not legal on wildcard associative arrays + 34 | a.first; + | ^~~~~ +%Error: t/t_assoc_wildcard_bad.v:35:7: Array method 'last' not legal on wildcard associative arrays : ... note: In instance 't' - 35 | a.last; - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:36:9: Array method 'next' not legal on wildcard associative arrays + 35 | a.last; + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:36:7: Array method 'next' not legal on wildcard associative arrays : ... note: In instance 't' - 36 | a.next; - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:37:9: Array method 'prev' not legal on wildcard associative arrays + 36 | a.next; + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:37:7: Array method 'prev' not legal on wildcard associative arrays : ... note: In instance 't' - 37 | a.prev; - | ^~~~ -%Error: t/t_assoc_wildcard_bad.v:38:9: Array method 'unique_index' not legal on wildcard associative arrays + 37 | a.prev; + | ^~~~ +%Error: t/t_assoc_wildcard_bad.v:38:7: Array method 'unique_index' not legal on wildcard associative arrays : ... note: In instance 't' - 38 | a.unique_index; - | ^~~~~~~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:39:9: Array method 'find_index' not legal on wildcard associative arrays + 38 | a.unique_index; + | ^~~~~~~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:39:7: Array method 'find_index' not legal on wildcard associative arrays : ... note: In instance 't' - 39 | a.find_index; - | ^~~~~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:40:9: Array method 'find_first_index' not legal on wildcard associative arrays + 39 | a.find_index; + | ^~~~~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:40:7: Array method 'find_first_index' not legal on wildcard associative arrays : ... note: In instance 't' - 40 | a.find_first_index; - | ^~~~~~~~~~~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:41:9: Array method 'find_last_index' not legal on wildcard associative arrays + 40 | a.find_first_index; + | ^~~~~~~~~~~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:41:7: Array method 'find_last_index' not legal on wildcard associative arrays : ... note: In instance 't' - 41 | a.find_last_index; - | ^~~~~~~~~~~~~~~ -%Error: t/t_assoc_wildcard_bad.v:43:8: Wildcard index must be integral (IEEE 1800-2023 7.8.1) + 41 | a.find_last_index; + | ^~~~~~~~~~~~~~~ +%Error: t/t_assoc_wildcard_bad.v:43:6: Wildcard index must be integral (IEEE 1800-2023 7.8.1) : ... note: In instance 't' - 43 | a[x] = "bad"; - | ^ -%Error: t/t_assoc_wildcard_bad.v:45:9: Unknown wildcard associative array method 'bad_not_defined' + 43 | a[x] = "bad"; + | ^ +%Error: t/t_assoc_wildcard_bad.v:45:7: Unknown wildcard associative array method 'bad_not_defined' : ... note: In instance 't' - 45 | a.bad_not_defined(); - | ^~~~~~~~~~~~~~~ + 45 | a.bad_not_defined(); + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assoc_wildcard_bad.v b/test_regress/t/t_assoc_wildcard_bad.v index f8e7c6f01..4ce772a39 100644 --- a/test_regress/t/t_assoc_wildcard_bad.v +++ b/test_regress/t/t_assoc_wildcard_bad.v @@ -7,41 +7,41 @@ typedef class Cls; class Cls; - integer imembera; - integer imemberb; + integer imembera; + integer imemberb; endclass : Cls module t; - initial begin - string a [*]; - string k; - string v; + initial begin + string a [*]; + string k; + string v; - Cls x; + Cls x; - v = a.num("badarg"); - v = a.size("badarg"); - v = a.exists(); // Bad - v = a.exists(k, "bad2"); - a.delete(k, "bad2"); + v = a.num("badarg"); + v = a.size("badarg"); + v = a.exists(); // Bad + v = a.exists(k, "bad2"); + a.delete(k, "bad2"); - a.sort; // Not legal on assoc - a.rsort; // Not legal on assoc - a.reverse; // Not legal on assoc - a.shuffle; // Not legal on assoc + a.sort; // Not legal on assoc + a.rsort; // Not legal on assoc + a.reverse; // Not legal on assoc + a.shuffle; // Not legal on assoc - a.first; // Not legal on wildcard - a.last; // Not legal on wildcard - a.next; // Not legal on wildcard - a.prev; // Not legal on wildcard - a.unique_index; // Not legal on wildcard - a.find_index; // Not legal on wildcard - a.find_first_index; // Not legal on wildcard - a.find_last_index; // Not legal on wildcard + a.first; // Not legal on wildcard + a.last; // Not legal on wildcard + a.next; // Not legal on wildcard + a.prev; // Not legal on wildcard + a.unique_index; // Not legal on wildcard + a.find_index; // Not legal on wildcard + a.find_first_index; // Not legal on wildcard + a.find_last_index; // Not legal on wildcard - a[x] = "bad"; + a[x] = "bad"; - a.bad_not_defined(); - end + a.bad_not_defined(); + end endmodule diff --git a/test_regress/t/t_assoc_wildcard_map.out b/test_regress/t/t_assoc_wildcard_map.out index 91dae9ed5..fadf53e84 100644 --- a/test_regress/t/t_assoc_wildcard_map.out +++ b/test_regress/t/t_assoc_wildcard_map.out @@ -1,6 +1,6 @@ -%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:15: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5) +%Error-UNSUPPORTED: t/t_assoc_wildcard_map.v:19:13: Unsupported: Wildcard array 'map' method (IEEE 1800-2023 7.12.5) : ... note: In instance 't' - 19 | res = a.map(el) with (el == 2); - | ^~~ + 19 | res = a.map(el) with (el == 2); + | ^~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_assoc_wildcard_map.v b/test_regress/t/t_assoc_wildcard_map.v index befe2d958..482e8a890 100644 --- a/test_regress/t/t_assoc_wildcard_map.v +++ b/test_regress/t/t_assoc_wildcard_map.v @@ -11,15 +11,15 @@ module t; - initial begin - automatic int res[]; - automatic int a [*] = '{1: 100, 2: 200, 3: 300}; + initial begin + automatic int res[]; + automatic int a [*] = '{1: 100, 2: 200, 3: 300}; - // TODO results not known to be correct - res = a.map(el) with (el == 2); - `checkh(res.size, 3); - `checkh(res[0], 0); - `checkh(res[1], 1); - `checkh(res[2], 0); - end + // TODO results not known to be correct + res = a.map(el) with (el == 2); + `checkh(res.size, 3); + `checkh(res[0], 0); + `checkh(res[1], 1); + `checkh(res[2], 0); + end endmodule diff --git a/test_regress/t/t_assoc_wildcard_method.v b/test_regress/t/t_assoc_wildcard_method.v index d9b784d2d..5c1e8ca6f 100644 --- a/test_regress/t/t_assoc_wildcard_method.v +++ b/test_regress/t/t_assoc_wildcard_method.v @@ -4,151 +4,153 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkp(gotv,expv_s) do begin string gotv_s; gotv_s = $sformatf("%p", gotv); if ((gotv_s) != (expv_s)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv_s), (expv_s)); `stop; end end while(0); +// verilog_format: on module t; - typedef struct { int x, y; } point; + typedef struct { int x, y; } point; - function automatic int vec_len_squared(point p); - return p.x * p.x + p.y * p.y; - endfunction + function automatic int vec_len_squared(point p); + return p.x * p.x + p.y * p.y; + endfunction - initial begin - int q[*]; - int qe [ * ]; // Empty - Note spaces around [*] for parsing coverage - automatic point points_q[*] = '{"a": point'{1, 2}, "b": point'{2, 4}, "c": point'{1, 4}}; - int qv[$]; // Value returns - int qi[$]; // Index returns - int i; - bit b; - string v; + initial begin + int q[*]; + int qe [ * ]; // Empty - Note spaces around [*] for parsing coverage + automatic point points_q[*] = '{"a": point'{1, 2}, "b": point'{2, 4}, "c": point'{1, 4}}; + int qv[$]; // Value returns + int qi[$]; // Index returns + int i; + bit b; + string v; - q = '{"a":1, "b":2, "c":2, "d":4, "e":3}; - `checkp(q, "'{\"a\":'h1, \"b\":'h2, \"c\":'h2, \"d\":'h4, \"e\":'h3}"); + q = '{"a":1, "b":2, "c":2, "d":4, "e":3}; + `checkp(q, "'{\"a\":'h1, \"b\":'h2, \"c\":'h2, \"d\":'h4, \"e\":'h3}"); - // NOT tested: with ... selectors + // NOT tested: with ... selectors - //q.sort; // Not legal on assoc - see t_assoc_meth_bad - //q.rsort; // Not legal on assoc - see t_assoc_meth_bad - //q.reverse; // Not legal on assoc - see t_assoc_meth_bad - //q.shuffle; // Not legal on assoc - see t_assoc_meth_bad + //q.sort; // Not legal on assoc - see t_assoc_meth_bad + //q.rsort; // Not legal on assoc - see t_assoc_meth_bad + //q.reverse; // Not legal on assoc - see t_assoc_meth_bad + //q.shuffle; // Not legal on assoc - see t_assoc_meth_bad - `checkp(qe, "'{}"); - qv = q.unique; - `checkp(qv, "'{'h1, 'h2, 'h4, 'h3}"); - qv = qe.unique; - `checkp(qv, "'{}"); + `checkp(qe, "'{}"); + qv = q.unique; + `checkp(qv, "'{'h1, 'h2, 'h4, 'h3}"); + qv = qe.unique; + `checkp(qv, "'{}"); - //q.unique_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad + //q.unique_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad - // These require an with clause or are illegal - qv = q.find with (item == 2); - `checkp(qv, "'{'h2, 'h2}"); - qv = q.find_first with (item == 2); - `checkp(qv, "'{'h2}"); - qv = q.find_last with (item == 2); - `checkp(qv, "'{'h2}"); + // These require an with clause or are illegal + qv = q.find with (item == 2); + `checkp(qv, "'{'h2, 'h2}"); + qv = q.find_first with (item == 2); + `checkp(qv, "'{'h2}"); + qv = q.find_last with (item == 2); + `checkp(qv, "'{'h2}"); - qv = q.find with (item == 20); - `checkp(qv, "'{}"); - qv = q.find_first with (item == 20); - `checkp(qv, "'{}"); - qv = q.find_last with (item == 20); - `checkp(qv, "'{}"); + qv = q.find with (item == 20); + `checkp(qv, "'{}"); + qv = q.find_first with (item == 20); + `checkp(qv, "'{}"); + qv = q.find_last with (item == 20); + `checkp(qv, "'{}"); - //q.find_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad - //q.find_first_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad - //q.find_last_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad + //q.find_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad + //q.find_first_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad + //q.find_last_index; // Not legal on wildcard assoc - see t_assoc_wildcard_bad - qv = q.min; - `checkp(qv, "'{'h1}"); - qv = q.max; - `checkp(qv, "'{'h4}"); + qv = q.min; + `checkp(qv, "'{'h1}"); + qv = q.max; + `checkp(qv, "'{'h4}"); - qv = qe.min; - `checkp(qv, "'{}"); - qv = qe.max; - `checkp(qv, "'{}"); + qv = qe.min; + `checkp(qv, "'{}"); + qv = qe.max; + `checkp(qv, "'{}"); - // Reduction methods + // Reduction methods - i = q.sum; - `checkh(i, 32'hc); - i = q.sum with (item + 1); - `checkh(i, 32'h11); - i = q.product; - `checkh(i, 32'h30); - i = q.product with (item + 1); - `checkh(i, 32'h168); + i = q.sum; + `checkh(i, 32'hc); + i = q.sum with (item + 1); + `checkh(i, 32'h11); + i = q.product; + `checkh(i, 32'h30); + i = q.product with (item + 1); + `checkh(i, 32'h168); - i = qe.sum; - `checkh(i, 32'h0); - i = qe.product; - `checkh(i, 32'h0); + i = qe.sum; + `checkh(i, 32'h0); + i = qe.product; + `checkh(i, 32'h0); - q = '{10:32'b1100, 11:32'b1010}; - i = q.and; - `checkh(i, 32'b1000); - i = q.and with (item + 1); - `checkh(i, 32'b1001); - i = q.or; - `checkh(i, 32'b1110); - i = q.or with (item + 1); - `checkh(i, 32'b1111); - i = q.xor; - `checkh(i, 32'b0110); - i = q.xor with (item + 1); - `checkh(i, 32'b0110); + q = '{10:32'b1100, 11:32'b1010}; + i = q.and; + `checkh(i, 32'b1000); + i = q.and with (item + 1); + `checkh(i, 32'b1001); + i = q.or; + `checkh(i, 32'b1110); + i = q.or with (item + 1); + `checkh(i, 32'b1111); + i = q.xor; + `checkh(i, 32'b0110); + i = q.xor with (item + 1); + `checkh(i, 32'b0110); - i = qe.and; - `checkh(i, 32'h0); - i = qe.and with (item + 1); - `checkh(i, 32'h0); - i = qe.or; - `checkh(i, 32'b0); - i = qe.or with (item + 1); - `checkh(i, 32'b0); - i = qe.xor; - `checkh(i, 32'b0); - i = qe.xor with (item + 1); - `checkh(i, 32'b0); + i = qe.and; + `checkh(i, 32'h0); + i = qe.and with (item + 1); + `checkh(i, 32'h0); + i = qe.or; + `checkh(i, 32'b0); + i = qe.or with (item + 1); + `checkh(i, 32'b0); + i = qe.xor; + `checkh(i, 32'b0); + i = qe.xor with (item + 1); + `checkh(i, 32'b0); - i = q.and(); - `checkh(i, 32'b1000); - i = q.and() with (item + 1); - `checkh(i, 32'b1001); - i = q.or(); - `checkh(i, 32'b1110); - i = q.or() with (item + 1); - `checkh(i, 32'b1111); - i = q.xor(); - `checkh(i, 32'b0110); - i = q.xor() with (item + 1); - `checkh(i, 32'b0110); + i = q.and(); + `checkh(i, 32'b1000); + i = q.and() with (item + 1); + `checkh(i, 32'b1001); + i = q.or(); + `checkh(i, 32'b1110); + i = q.or() with (item + 1); + `checkh(i, 32'b1111); + i = q.xor(); + `checkh(i, 32'b0110); + i = q.xor() with (item + 1); + `checkh(i, 32'b0110); - i = qe.and(); - `checkh(i, 32'b0); - i = qe.or(); - `checkh(i, 32'b0); - i = qe.xor(); - `checkh(i, 32'b0); + i = qe.and(); + `checkh(i, 32'b0); + i = qe.or(); + `checkh(i, 32'b0); + i = qe.xor(); + `checkh(i, 32'b0); - i = points_q.sum with (vec_len_squared(item)); - `checkh(i, 32'h2a); - i = points_q.product with (vec_len_squared(item)); - `checkh(i, 32'h6a4); - b = points_q.sum with (vec_len_squared(item) == 5); - `checkh(b, 1'b1); - b = points_q.sum with (vec_len_squared(item) == 0); - `checkh(b, 1'b0); - b = points_q.product with (vec_len_squared(item) inside {5, 17}); - `checkh(b, 1'b0); - b = points_q.sum with (vec_len_squared(item) inside {5, 17, 20}); - `checkh(b, 1'b1); + i = points_q.sum with (vec_len_squared(item)); + `checkh(i, 32'h2a); + i = points_q.product with (vec_len_squared(item)); + `checkh(i, 32'h6a4); + b = points_q.sum with (vec_len_squared(item) == 5); + `checkh(b, 1'b1); + b = points_q.sum with (vec_len_squared(item) == 0); + `checkh(b, 1'b0); + b = points_q.product with (vec_len_squared(item) inside {5, 17}); + `checkh(b, 1'b0); + b = points_q.sum with (vec_len_squared(item) inside {5, 17, 20}); + `checkh(b, 1'b1); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_attr_parenstar.v b/test_regress/t/t_attr_parenstar.v index 580a42da7..accecc67d 100644 --- a/test_regress/t/t_attr_parenstar.v +++ b/test_regress/t/t_attr_parenstar.v @@ -4,39 +4,38 @@ // SPDX-FileCopyrightText: 2011 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + // verilog_format: off + always @(*) begin + if (clk) begin end + end - always @(*) begin - if (clk) begin end - end + always @(* ) begin + if (clk) begin end + end - always @(* ) begin - if (clk) begin end - end + // Not legal in some simulators, legal in others +// always @(* /*cmt*/ ) begin +// if (clk) begin end +// end - // Not legal in some simulators, legal in others -// always @(* /*cmt*/ ) begin -// if (clk) begin end -// end + // Not legal in some simulators, legal in others +// always @(* // cmt +// ) begin +// if (clk) begin end +// end - // Not legal in some simulators, legal in others -// always @(* // cmt -// ) begin -// if (clk) begin end -// end + always @ (* + ) begin + if (clk) begin end + end + // verilog_format: on - always @ (* - ) begin - if (clk) begin end - end - - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_benchmark_mux4k.v b/test_regress/t/t_benchmark_mux4k.v index 0e0fe4ee9..74ca1423f 100644 --- a/test_regress/t/t_benchmark_mux4k.v +++ b/test_regress/t/t_benchmark_mux4k.v @@ -18,163 +18,171 @@ // Total of DATA_WIDTH*MUX2_SIZE*(MUX1_SIZE+1) instantiations of mux64 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [`DATA_WIDTH-1:0] datao; // From mux4096 of mux4096.v + // End of automatics - reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai; - reg [`ADDR_WIDTH-1:0] addr; + reg [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai; + reg [`ADDR_WIDTH-1:0] addr; - // Mux: takes in addr and datai and outputs datao - mux4096 mux4096 (/*AUTOINST*/ - // Outputs - .datao (datao[`DATA_WIDTH-1:0]), - // Inputs - .datai (datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), - .addr (addr[`ADDR_WIDTH-1:0])); + // Mux: takes in addr and datai and outputs datao + mux4096 mux4096 ( /*AUTOINST*/ + // Outputs + .datao(datao[`DATA_WIDTH-1:0]), + // Inputs + .datai(datai[`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0]), + .addr(addr[`ADDR_WIDTH-1:0]) + ); - // calculate what the answer should be from datai. This is bit - // tricky given the way datai gets sliced. datai is in bit - // planes where all the LSBs are contiguous and then the next bit. - reg [`DATA_WIDTH-1:0] datao_check; - integer j; - always @(datai or addr) begin - for(j=0;j<`DATA_WIDTH;j=j+1) begin - /* verilator lint_off WIDTH */ - datao_check[j] = datai >> ((`MUX1_SIZE*`MUX2_SIZE*j)+addr); - /* verilator lint_on WIDTH */ + // calculate what the answer should be from datai. This is bit + // tricky given the way datai gets sliced. datai is in bit + // planes where all the LSBs are contiguous and then the next bit. + reg [`DATA_WIDTH-1:0] datao_check; + integer j; + always @(datai or addr) begin + for (j = 0; j < `DATA_WIDTH; j = j + 1) begin + /* verilator lint_off WIDTH */ + datao_check[j] = datai >> ((`MUX1_SIZE * `MUX2_SIZE * j) + addr); + /* verilator lint_on WIDTH */ + end + end + + // Run the test loop. This just increments the address + integer i, result; + always @(posedge clk) begin + // initial the input data with random values + if (addr == 0) begin + result = 1; + datai = 0; + for (i = 0; i < `MUX1_SIZE * `MUX2_SIZE; i = i + 1) begin + /* verilator lint_off WIDTH */ + datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); + /* verilator lint_on WIDTH */ end - end + end - // Run the test loop. This just increments the address - integer i, result; - always @ (posedge clk) begin - // initial the input data with random values - if (addr == 0) begin - result = 1; - datai = 0; - for(i=0; i<`MUX1_SIZE*`MUX2_SIZE; i=i+1) begin - /* verilator lint_off WIDTH */ - datai = (datai << `DATA_WIDTH) | ($random & {`DATA_WIDTH{1'b1}}); - /* verilator lint_on WIDTH */ - end - end - - addr <= addr + 1; - if (datao_check != datao) begin - result = 0; - $stop; - end + addr <= addr + 1; + if (datao_check != datao) begin + result = 0; + $stop; + end `ifdef TEST_VERBOSE - $write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao); + $write("Addr=%d datao_check=%d datao=%d\n", addr, datao_check, datao); `endif - // only run the first 10 addresses for now - if (addr > 10) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + // only run the first 10 addresses for now + if (addr > 10) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module mux4096 - (input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai, - input [`ADDR_WIDTH-1:0] addr, - output [`DATA_WIDTH-1:0] datao - ); +module mux4096 ( + input [`DATA_WIDTH*`MUX1_SIZE*`MUX2_SIZE-1:0] datai, + input [`ADDR_WIDTH-1:0] addr, + output [`DATA_WIDTH-1:0] datao +); - // DATA_WIDTH instantiations of mux4096_1bit - mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] - (.addr(addr), + // DATA_WIDTH instantiations of mux4096_1bit + mux4096_1bit mux4096_1bit[`DATA_WIDTH-1:0] ( + .addr(addr), .datai(datai), .datao(datao) - ); + ); endmodule -module mux4096_1bit - (input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai, - input [`ADDR_WIDTH-1:0] addr, - output datao - ); +module mux4096_1bit ( + input [`MUX1_SIZE*`MUX2_SIZE-1:0] datai, + input [`ADDR_WIDTH-1:0] addr, + output datao +); - // address decoding - wire [3:0] A = (4'b1) << addr[1:0]; - wire [3:0] B = (4'b1) << addr[3:2]; - wire [3:0] C = (4'b1) << addr[5:4]; - wire [3:0] D = (4'b1) << addr[7:6]; - wire [3:0] E = (4'b1) << addr[9:8]; - wire [3:0] F = (4'b1) << addr[11:10]; + // address decoding + wire [3:0] A = (4'b1) << addr[1:0]; + wire [3:0] B = (4'b1) << addr[3:2]; + wire [3:0] C = (4'b1) << addr[5:4]; + wire [3:0] D = (4'b1) << addr[7:6]; + wire [3:0] E = (4'b1) << addr[9:8]; + wire [3:0] F = (4'b1) << addr[11:10]; - wire [`MUX2_SIZE-1:0] data0; + wire [`MUX2_SIZE-1:0] data0; - // DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64 - // first stage of 64:1 muxing - mux64 #(.MUX_SIZE(`MUX1_SIZE)) mux1[`MUX2_SIZE-1:0] - (.A(A), + // DATA_WIDTH*(MUX2_SIZE)*MUX1_SIZE instantiations of mux64 + // first stage of 64:1 muxing + mux64 #( + .MUX_SIZE(`MUX1_SIZE) + ) mux1[`MUX2_SIZE-1:0] ( + .A(A), .B(B), .C(C), .datai(datai), - .datao(data0)); + .datao(data0) + ); - // DATA_WIDTH*MUX2_SIZE instantiations of mux64 - // second stage of 64:1 muxing - mux64 #(.MUX_SIZE(`MUX2_SIZE)) mux2 - (.A(D), + // DATA_WIDTH*MUX2_SIZE instantiations of mux64 + // second stage of 64:1 muxing + mux64 #( + .MUX_SIZE(`MUX2_SIZE) + ) mux2 ( + .A(D), .B(E), .C(F), .datai(data0), - .datao(datao)); + .datao(datao) + ); endmodule -module mux64 - #(parameter MUX_SIZE=64) - (input [3:0] A, - input [3:0] B, - input [3:0] C, - input [MUX_SIZE-1:0] datai, - output datao - ); +module mux64 #( + parameter MUX_SIZE = 64 +) ( + input [3:0] A, + input [3:0] B, + input [3:0] C, + input [MUX_SIZE-1:0] datai, + output datao +); - wire [63:0] colSelA = { 16{ A[3:0] }}; - wire [63:0] colSelB = { 4{ {4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}}; - wire [63:0] colSelC = { {16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}}; + wire [63:0] colSelA = {16{A[3:0]}}; + wire [63:0] colSelB = {4{{4{B[3]}}, {4{B[2]}}, {4{B[1]}}, {4{B[0]}}}}; + wire [63:0] colSelC = {{16{C[3]}}, {16{C[2]}}, {16{C[1]}}, {16{C[0]}}}; - wire [MUX_SIZE-1:0] data_bus; + wire [MUX_SIZE-1:0] data_bus; - // Note each of these becomes a separate wire. - //.colSelA(colSelA[MUX_SIZE-1:0]), - //.colSelB(colSelB[MUX_SIZE-1:0]), - //.colSelC(colSelC[MUX_SIZE-1:0]), + // Note each of these becomes a separate wire. + //.colSelA(colSelA[MUX_SIZE-1:0]), + //.colSelB(colSelB[MUX_SIZE-1:0]), + //.colSelC(colSelC[MUX_SIZE-1:0]), - drv drv[MUX_SIZE-1:0] - (.colSelA(colSelA[MUX_SIZE-1:0]), + drv drv[MUX_SIZE-1:0] ( + .colSelA(colSelA[MUX_SIZE-1:0]), .colSelB(colSelB[MUX_SIZE-1:0]), .colSelC(colSelC[MUX_SIZE-1:0]), .datai(datai), .datao(data_bus) - ); + ); - assign datao = |data_bus; + assign datao = |data_bus; endmodule -module drv - (input colSelA, - input colSelB, - input colSelC, - input datai, - output datao - ); - assign datao = colSelC & colSelB & colSelA & datai; +module drv ( + input colSelA, + input colSelB, + input colSelC, + input datai, + output datao +); + assign datao = colSelC & colSelB & colSelA & datai; endmodule diff --git a/test_regress/t/t_bind.v b/test_regress/t/t_bind.v index a8ec4fe9e..8601775db 100644 --- a/test_regress/t/t_bind.v +++ b/test_regress/t/t_bind.v @@ -7,72 +7,77 @@ bit a_finished; bit b_finished; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; - wire [31:0] o; - wire si = 1'b0; +module t ( /*AUTOARG*/ + // Inputs + clk + ); + input clk; + wire [31:0] o; + wire si = 1'b0; - ExampInst i - (// Outputs - .o (o[31:0]), + ExampInst i ( // Outputs + .o(o[31:0]), // Inputs - .i (1'b0) - /*AUTOINST*/); + .i(1'b0) + /*AUTOINST*/); - Prog p (/*AUTOINST*/ - // Inputs - .si (si)); + Prog p ( /*AUTOINST*/ + // Inputs + .si (si)); - always @ (posedge clk) begin - if (!a_finished) $stop; - if (!b_finished) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (!a_finished) $stop; + if (!b_finished) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module InstModule ( - output logic [31:0] so, - input si - ); - assign so = {32{si}}; + output logic [31:0] so, + input si +); + assign so = {32{si}}; endmodule -program Prog (input si); - initial a_finished = 1'b1; +program Prog ( + input si +); + initial a_finished = 1'b1; endprogram -module ExampInst (o,i); - output logic [31:0] o; - input i; +module ExampInst ( + o, + i +); + output logic [31:0] o; + input i; - InstModule instName - (// Outputs - .so (o[31:0]), + InstModule instName ( // Outputs + .so(o[31:0]), // Inputs - .si (i) - /*AUTOINST*/); + .si(i) + /*AUTOINST*/); - //bind InstModule Prog instProg - // (.si(si)); + //bind InstModule Prog instProg + // (.si(si)); - // Note is based on context of caller - bind InstModule Prog instProg - (/*AUTOBIND*/ - .si (si)); + // Note is based on context of caller + bind InstModule Prog instProg ( /*AUTOBIND*/ + .si(si) + ); endmodule // Check bind at top level -bind InstModule Prog2 instProg2 - (/*AUTOBIND*/ - .si (si)); +bind InstModule Prog2 instProg2 ( /*AUTOBIND*/ + .si(si) +); // Check program declared after bind -program Prog2 (input si); - initial b_finished = 1'b1; +program Prog2 ( + input si +); + initial b_finished = 1'b1; endprogram diff --git a/test_regress/t/t_bind2.v b/test_regress/t/t_bind2.v index ebf19478c..7b400704f 100644 --- a/test_regress/t/t_bind2.v +++ b/test_regress/t/t_bind2.v @@ -6,14 +6,15 @@ // verilator lint_off WIDTH +// verilog_format: off `define stop $stop -`define checkh(gotv, expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t ( + input clk +); -module t ( /*AUTOARG*/ - // Inputs - clk - ); - input clk; reg [7:0] p1; reg [7:0] p2; reg [7:0] p3; diff --git a/test_regress/t/t_bind_nfound.v b/test_regress/t/t_bind_nfound.v index ba0e49bb5..46cb381de 100644 --- a/test_regress/t/t_bind_nfound.v +++ b/test_regress/t/t_bind_nfound.v @@ -9,19 +9,19 @@ endinterface module t; - sub sub(); + sub sub (); - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule module sub_ext; - bind sub_inst bound_if i_bound(); + bind sub_inst bound_if i_bound (); endmodule module sub; - sub_ext sub_ext(); + sub_ext sub_ext (); endmodule diff --git a/test_regress/t/t_bitsel_2d_slice.v b/test_regress/t/t_bitsel_2d_slice.v index 25ffbf47e..6387c9d31 100644 --- a/test_regress/t/t_bitsel_2d_slice.v +++ b/test_regress/t/t_bitsel_2d_slice.v @@ -4,26 +4,24 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - localparam int WIDTH = 8; - typedef logic [WIDTH-1:0] [15:0] two_dee_t; - typedef logic[$clog2(WIDTH)-1:0] index_t; + localparam int WIDTH = 8; + typedef logic [WIDTH-1:0][15:0] two_dee_t; + typedef logic [$clog2(WIDTH)-1:0] index_t; - two_dee_t the_two_dee; + two_dee_t the_two_dee; - initial begin - the_two_dee[index_t'(5)][7:0] = 8'hab; - the_two_dee[index_t'(5)][15:8] = 8'h12; - end + initial begin + the_two_dee[index_t'(5)][7:0] = 8'hab; + the_two_dee[index_t'(5)][15:8] = 8'h12; + end - always @ (posedge clk) begin - if (the_two_dee[5] != 16'h12ab) $stop(); - $write("*-* All Finished *-*\n"); - $finish; - end + always @(posedge clk) begin + if (the_two_dee[5] != 16'h12ab) $stop(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_concat.v b/test_regress/t/t_bitsel_concat.v index daff0b45e..a6c364b87 100644 --- a/test_regress/t/t_bitsel_concat.v +++ b/test_regress/t/t_bitsel_concat.v @@ -17,88 +17,88 @@ // Test IEEE 1800-2023 concat bit selects, function bit selects, method bit selects class Cls; - static function logic [15:0] valf1ed(); - return 16'hf1ed; - endfunction + static function logic [15:0] valf1ed(); + return 16'hf1ed; + endfunction endclass module t; - Cls c; + Cls c; - int q[$]; + int q[$]; - logic [7:0] aa; - logic [7:0] bb; - logic [7:0] s8; - logic s1; + logic [7:0] aa; + logic [7:0] bb; + logic [7:0] s8; + logic s1; - function logic [15:0] valf0ed(); - return 16'hf0ed; - endfunction + function logic [15:0] valf0ed(); + return 16'hf0ed; + endfunction - int i; - typedef int arr_t[1:0][3:0]; + int i; + typedef int arr_t[1:0][3:0]; - function arr_t valarr(); - return '{'{1,2,3,4}, '{5,6,7,8}}; - endfunction + function arr_t valarr(); + return '{'{1,2,3,4}, '{5,6,7,8}}; + endfunction - initial begin - aa = 8'haa; - bb = 8'hbb; + initial begin + aa = 8'haa; + bb = 8'hbb; - s1 = {aa,bb}[8]; - `checkh(s1, 1'b0); - s1 = {aa,bb}[9]; - `checkh(s1, 1'b1); - s8 = {aa,bb}[11:4]; - `checkh(s8, 8'hab); - s8 = {aa,bb}[4+:8]; - `checkh(s8, 8'hab); - s8 = {aa,bb}[11-:8]; - `checkh(s8, 8'hab); + s1 = {aa,bb}[8]; + `checkh(s1, 1'b0); + s1 = {aa,bb}[9]; + `checkh(s1, 1'b1); + s8 = {aa,bb}[11:4]; + `checkh(s8, 8'hab); + s8 = {aa,bb}[4+:8]; + `checkh(s8, 8'hab); + s8 = {aa,bb}[11-:8]; + `checkh(s8, 8'hab); - s1 = valf0ed()[4]; - `checkh(s1, 1'b0); - s1 = valf0ed()[5]; - `checkh(s1, 1'b1); - s8 = valf0ed()[11:4]; - `checkh(s8, 8'h0e); - s8 = valf0ed()[4+:8]; - `checkh(s8, 8'h0e); - s8 = valf0ed()[11-:8]; - `checkh(s8, 8'h0e); + s1 = valf0ed()[4]; + `checkh(s1, 1'b0); + s1 = valf0ed()[5]; + `checkh(s1, 1'b1); + s8 = valf0ed()[11:4]; + `checkh(s8, 8'h0e); + s8 = valf0ed()[4+:8]; + `checkh(s8, 8'h0e); + s8 = valf0ed()[11-:8]; + `checkh(s8, 8'h0e); - c = new; - s1 = c.valf1ed()[4]; - `checkh(s1, 1'b0); - s1 = c.valf1ed()[5]; - `checkh(s1, 1'b1); - s8 = c.valf1ed()[11:4]; - `checkh(s8, 8'h1e); - s8 = c.valf1ed()[4+:8]; - `checkh(s8, 8'h1e); - s8 = c.valf1ed()[11-:8]; - `checkh(s8, 8'h1e); + c = new; + s1 = c.valf1ed()[4]; + `checkh(s1, 1'b0); + s1 = c.valf1ed()[5]; + `checkh(s1, 1'b1); + s8 = c.valf1ed()[11:4]; + `checkh(s8, 8'h1e); + s8 = c.valf1ed()[4+:8]; + `checkh(s8, 8'h1e); + s8 = c.valf1ed()[11-:8]; + `checkh(s8, 8'h1e); - q.push_front(32'h10ef); - s1 = q.sum()[4]; - `checkh(s1, 1'b0); - s1 = q.sum()[5]; - `checkh(s1, 1'b1); - s8 = q.sum()[11:4]; - `checkh(s8, 8'h0e); - s8 = q.sum()[4+:8]; - `checkh(s8, 8'h0e); - s8 = q.sum()[11-:8]; - `checkh(s8, 8'h0e); + q.push_front(32'h10ef); + s1 = q.sum()[4]; + `checkh(s1, 1'b0); + s1 = q.sum()[5]; + `checkh(s1, 1'b1); + s8 = q.sum()[11:4]; + `checkh(s8, 8'h0e); + s8 = q.sum()[4+:8]; + `checkh(s8, 8'h0e); + s8 = q.sum()[11-:8]; + `checkh(s8, 8'h0e); - i = valarr()[1][2]; - $display(i); + i = valarr()[1][2]; + $display(i); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_const_bad.out b/test_regress/t/t_bitsel_const_bad.out index f4060503d..3e4b87786 100644 --- a/test_regress/t/t_bitsel_const_bad.out +++ b/test_regress/t/t_bitsel_const_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_bitsel_const_bad.v:16:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' +%Error: t/t_bitsel_const_bad.v:16:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... note: In instance 't' - 16 | assign a = b[0]; - | ^ + 16 | assign a = b[0]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_const_bad.v b/test_regress/t/t_bitsel_const_bad.v index 27316736f..368fd9c0a 100644 --- a/test_regress/t/t_bitsel_const_bad.v +++ b/test_regress/t/t_bitsel_const_bad.v @@ -8,11 +8,11 @@ module t; - // Note that if we declare "wire [0:0] b", this works just fine. - wire a; - wire b; + // Note that if we declare "wire [0:0] b", this works just fine. + wire a; + wire b; - assign b = 1'b0; - assign a = b[0]; // IEEE illegal can't extract scalar + assign b = 1'b0; + assign a = b[0]; // IEEE illegal can't extract scalar endmodule diff --git a/test_regress/t/t_bitsel_enum.v b/test_regress/t/t_bitsel_enum.v index edb81040e..58176bdb9 100644 --- a/test_regress/t/t_bitsel_enum.v +++ b/test_regress/t/t_bitsel_enum.v @@ -4,25 +4,22 @@ // SPDX-FileCopyrightText: 2015 Jonathon Donaldson // SPDX-License-Identifier: CC0-1.0 -module t_bitsel_enum - ( - output out0, - output out1 - ); +module t_bitsel_enum ( + output out0, + output out1 +); - localparam [6:0] CNST_VAL = 7'h22; + localparam [6:0] CNST_VAL = 7'h22; - enum logic [6:0] { - ENUM_VAL = 7'h33 - } MyEnum; + enum logic [6:0] {ENUM_VAL = 7'h33} MyEnum; - assign out0 = CNST_VAL[0]; - // Not supported by NC-verilog nor VCS, but other simulators do - assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works + assign out0 = CNST_VAL[0]; + // Not supported by NC-verilog nor VCS, but other simulators do + assign out1 = ENUM_VAL[0]; // named values of an enumeration should act like constants so this should work just like the line above works - initial begin - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_over32.v b/test_regress/t/t_bitsel_over32.v index c4311ca0b..44b16ad73 100644 --- a/test_regress/t/t_bitsel_over32.v +++ b/test_regress/t/t_bitsel_over32.v @@ -4,35 +4,38 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(aw_addr, orig_aw_size); +module t ( + aw_addr, + orig_aw_size +); - typedef logic [63:0] addr_t; - typedef logic [7:0][7:0] mst_data_t; + typedef logic [63:0] addr_t; + typedef logic [7:0][7:0] mst_data_t; - logic [127:0] slv_req_i_w_data; - input addr_t aw_addr; - mst_data_t w_data; - input logic [2:0] orig_aw_size; + logic [127:0] slv_req_i_w_data; + input addr_t aw_addr; + mst_data_t w_data; + input logic [2:0] orig_aw_size; - always_comb begin + always_comb begin - // verilator lint_off WIDTHEXPAND - automatic addr_t mst_port_offset = aw_addr[2:0]; - automatic addr_t slv_port_offset = aw_addr[3:0]; + // verilator lint_off WIDTHEXPAND + automatic addr_t mst_port_offset = aw_addr[2:0]; + automatic addr_t slv_port_offset = aw_addr[3:0]; - w_data = '0; + w_data = '0; - for (int b=0; b<16; b++) begin - if ((b >= slv_port_offset) && + for (int b = 0; b < 16; b++) begin + if ((b >= slv_port_offset) && (b - slv_port_offset < (1 << orig_aw_size)) && (b + mst_port_offset - slv_port_offset < 8)) begin - automatic addr_t index = b + mst_port_offset - slv_port_offset; + automatic addr_t index = b + mst_port_offset - slv_port_offset; - // verilator lint_on WIDTHEXPAND - // [#][7:0] = [ +: 8] - w_data[index] = slv_req_i_w_data[8*b +: 8]; + // verilator lint_on WIDTHEXPAND + // [#][7:0] = [ +: 8] + w_data[index] = slv_req_i_w_data[8*b+:8]; - end end - end + end + end endmodule diff --git a/test_regress/t/t_bitsel_slice.v b/test_regress/t/t_bitsel_slice.v index bf26d8a10..c5af87271 100644 --- a/test_regress/t/t_bitsel_slice.v +++ b/test_regress/t/t_bitsel_slice.v @@ -4,80 +4,78 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - logic [2:0] [1:0] in; - always @* in = crc[5:0]; + logic [2:0][1:0] in; + always @* in = crc[5:0]; - /*AUTOWIRE*/ - // Beginning of automatic wires (for undeclared instantiated-module outputs) - logic [1:0] [1:0] out; // From test of Test.v - // End of automatics + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [1:0] [1:0] out; // From test of Test.v + // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out/*[1:0][1:0]*/), - // Inputs - .clk (clk), - .in (in/*[2:0][1:0]*/)); + Test test ( /*AUTOINST*/ + // Outputs + .out (out/*[1:0][1:0]*/), + // Inputs + .clk (clk), + .in (in/*[2:0][1:0]*/)); - // Aggregate outputs into a single result vector - wire [63:0] result = {60'h0, out[1],out[0]}; + // Aggregate outputs into a single result vector + wire [63:0] result = {60'h0, out[1], out[0]}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= 64'h0; - end - else if (cyc<10) begin - sum <= 64'h0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'hdc21e42d85441511 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= 64'h0; + end + else if (cyc < 10) begin + sum <= 64'h0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'hdc21e42d85441511 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module Test (/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in - ); +module Test ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, in + ); - //bug717 + //bug717 - input clk; - input logic [2:0][1:0] in; + input clk; + input logic [2:0][1:0] in; - output logic [1:0][1:0] out; + output logic [1:0][1:0] out; - always @(posedge clk) begin - out <= in[2 -: 2]; - end + always @(posedge clk) begin + out <= in[2-:2]; + end endmodule diff --git a/test_regress/t/t_bitsel_struct.v b/test_regress/t/t_bitsel_struct.v index 03e271b77..bdeb1d689 100644 --- a/test_regress/t/t_bitsel_struct.v +++ b/test_regress/t/t_bitsel_struct.v @@ -11,19 +11,19 @@ module t; - typedef struct packed { - logic [1:0][15:0] channel; - logic others; - } buss_t; + typedef struct packed { + logic [1:0][15:0] channel; + logic others; + } buss_t; - buss_t b; - reg [7:0] a; + buss_t b; + reg [7:0] a; - initial begin - b = {16'h8765,16'h4321,1'b1}; - a = b.channel[0][8+:8]; - if (a != 8'h43) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + b = {16'h8765, 16'h4321, 1'b1}; + a = b.channel[0][8+:8]; + if (a != 8'h43) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_struct2.v b/test_regress/t/t_bitsel_struct2.v index 41b02b1ea..39cf0fdb4 100644 --- a/test_regress/t/t_bitsel_struct2.v +++ b/test_regress/t/t_bitsel_struct2.v @@ -4,43 +4,43 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkb(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='b%x exp='b%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - typedef struct packed { - logic [3:2] a; - logic [5:4][3:2] b; - } ab_t; - typedef ab_t [7:6] c_t; // array of structs - typedef struct packed { - c_t [17:16] d; - } e_t; + typedef struct packed { + logic [3:2] a; + logic [5:4][3:2] b; + } ab_t; + typedef ab_t [7:6] c_t; // array of structs + typedef struct packed {c_t [17:16] d;} e_t; - initial begin - e_t e; - `checkh($bits(ab_t),6); - `checkh($bits(c_t),12); - `checkh($bits(e_t),24); - `checkh($bits(e), 24); - `checkh($bits(e.d[17]),12); - `checkh($bits(e.d[16][6]),6); - `checkh($bits(e.d[16][6].b[5]),2); - `checkh($bits(e.d[16][6].b[5][2]), 1); - // - e = 24'b101101010111010110101010; - `checkb(e, 24'b101101010111010110101010); - e.d[17] = 12'b111110011011; - `checkb(e, 24'b111110011011010110101010); - e.d[16][6] = 6'b010101; - `checkb(e, 24'b111110011011010110010101); - e.d[16][6].b[5] = 2'b10; - `checkb(e, 24'b111110011011010110011001); - e.d[16][6].b[5][2] = 1'b1; - // - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + e_t e; + `checkh($bits(ab_t), 6); + `checkh($bits(c_t), 12); + `checkh($bits(e_t), 24); + `checkh($bits(e), 24); + `checkh($bits(e.d[17]), 12); + `checkh($bits(e.d[16][6]), 6); + `checkh($bits(e.d[16][6].b[5]), 2); + `checkh($bits(e.d[16][6].b[5][2]), 1); + // + e = 24'b101101010111010110101010; + `checkb(e, 24'b101101010111010110101010); + e.d[17] = 12'b111110011011; + `checkb(e, 24'b111110011011010110101010); + e.d[16][6] = 6'b010101; + `checkb(e, 24'b111110011011010110010101); + e.d[16][6].b[5] = 2'b10; + `checkb(e, 24'b111110011011010110011001); + e.d[16][6].b[5][2] = 1'b1; + // + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_struct3.v b/test_regress/t/t_bitsel_struct3.v index 3a63eb106..a54c0e47f 100644 --- a/test_regress/t/t_bitsel_struct3.v +++ b/test_regress/t/t_bitsel_struct3.v @@ -9,48 +9,50 @@ // SPDX-FileCopyrightText: 2013 Jie Xu // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - typedef struct packed { - logic [15:0] channel; - logic [15:0] others; - } buss_t; + typedef struct packed { + logic [15:0] channel; + logic [15:0] others; + } buss_t; - buss_t b; + buss_t b; - reg [7:0] a; - reg [7:0] c; - reg [7:0] d; + reg [7:0] a; + reg [7:0] c; + reg [7:0] d; - union packed { - logic [31:0] [7:0] idx; - struct packed { - logic [15:0] z, y, x; - logic [25:0] [7:0] r; - } nam; - } gpr; + union packed { + logic [31:0][7:0] idx; + struct packed { + logic [15:0] z, y, x; + logic [25:0][7:0] r; + } nam; + } gpr; - reg [14:0] gpr_a; + reg [14:0] gpr_a; - initial begin - b = {16'h8765,16'h4321}; - a = b[19:12]; // This works - c = b[8+:8]; // This fails - d = b[11-:8]; // This fails - `checkh(a, 8'h54); - `checkh(c, 8'h43); - `checkh(d, 8'h32); + initial begin + b = {16'h8765, 16'h4321}; + a = b[19:12]; // This works + c = b[8+:8]; // This fails + d = b[11-:8]; // This fails + `checkh(a, 8'h54); + `checkh(c, 8'h43); + `checkh(d, 8'h32); - gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345; - `checkh (gpr[255:255-14], 15'h091a); - gpr_a = gpr.nam.z[15:1]; - `checkh (gpr_a, 15'h091a); + gpr = 256'h12346789_abcdef12_3456789a_bcdef123_456789ab_cdef1234_56789abc_def12345; + `checkh(gpr[255:255-14], 15'h091a); + gpr_a = gpr.nam.z[15:1]; + `checkh(gpr_a, 15'h091a); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_bitsel_wire_array_bad.out b/test_regress/t/t_bitsel_wire_array_bad.out index 5fdddc94d..86dc766af 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.out +++ b/test_regress/t/t_bitsel_wire_array_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_bitsel_wire_array_bad.v:16:16: Illegal assignment of constant to unpacked array +%Error: t/t_bitsel_wire_array_bad.v:16:15: Illegal assignment of constant to unpacked array : ... note: In instance 't' - 16 | assign b = a[0]; - | ^ + 16 | assign b = a[0]; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_wire_array_bad.v b/test_regress/t/t_bitsel_wire_array_bad.v index f14a20c61..e2a630c14 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.v +++ b/test_regress/t/t_bitsel_wire_array_bad.v @@ -8,11 +8,11 @@ module t; - // a and b are arrays of length 1. - wire a[0:0]; // Array of nets - wire b[0:0]; + // a and b are arrays of length 1. + wire a[0:0]; // Array of nets + wire b[0:0]; - assign a = 1'b0; // Only net assignment allowed - assign b = a[0]; // Only net assignment allowed + assign a = 1'b0; // Only net assignment allowed + assign b = a[0]; // Only net assignment allowed endmodule diff --git a/test_regress/t/t_blocking.v b/test_regress/t/t_blocking.v index 9978352cd..6328b995d 100644 --- a/test_regress/t/t_blocking.v +++ b/test_regress/t/t_blocking.v @@ -4,93 +4,91 @@ // SPDX-FileCopyrightText: 2003 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; + integer _mode; + initial _mode = 0; + reg [7:0] a; + reg [7:0] b; + reg [7:0] c; - integer _mode; initial _mode=0; - reg [7:0] a; - reg [7:0] b; - reg [7:0] c; + reg [7:0] mode_d1r; + reg [7:0] mode_d2r; + reg [7:0] mode_d3r; - reg [7:0] mode_d1r; - reg [7:0] mode_d2r; - reg [7:0] mode_d3r; + // surefire lint_off ITENST + // surefire lint_off STMINI + // surefire lint_off NBAJAM - // surefire lint_off ITENST - // surefire lint_off STMINI - // surefire lint_off NBAJAM - - always @ (posedge clk) begin // filp-flops with asynchronous reset - if (0) begin - _mode <= 0; + always @(posedge clk) begin // filp-flops with asynchronous reset + if (0) begin + _mode <= 0; + end + else begin + _mode <= _mode + 1; + if (_mode == 0) begin + $write("[%0t] t_blocking: Running\n", $time); + a <= 8'd0; + b <= 8'd0; + c <= 8'd0; end - else begin - _mode <= _mode + 1; - if (_mode==0) begin - $write("[%0t] t_blocking: Running\n", $time); - a <= 8'd0; - b <= 8'd0; - c <= 8'd0; - end - else if (_mode==1) begin - if (a !== 8'd0) $stop; - if (b !== 8'd0) $stop; - if (c !== 8'd0) $stop; - a <= b; - b <= 8'd1; - c <= b; - if (a !== 8'd0) $stop; - if (b !== 8'd0) $stop; - if (c !== 8'd0) $stop; - end - else if (_mode==2) begin - if (a !== 8'd0) $stop; - if (b !== 8'd1) $stop; - if (c !== 8'd0) $stop; - a <= b; - b <= 8'd2; - c <= b; - if (a !== 8'd0) $stop; - if (b !== 8'd1) $stop; - if (c !== 8'd0) $stop; - end - else if (_mode==3) begin - if (a !== 8'd1) $stop; - if (b !== 8'd2) $stop; - if (c !== 8'd1) $stop; - end - else if (_mode==4) begin - if (mode_d3r != 8'd1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + else if (_mode == 1) begin + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd1; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd0) $stop; + if (c !== 8'd0) $stop; end - end + else if (_mode == 2) begin + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + a <= b; + b <= 8'd2; + c <= b; + if (a !== 8'd0) $stop; + if (b !== 8'd1) $stop; + if (c !== 8'd0) $stop; + end + else if (_mode == 3) begin + if (a !== 8'd1) $stop; + if (b !== 8'd2) $stop; + if (c !== 8'd1) $stop; + end + else if (_mode == 4) begin + if (mode_d3r != 8'd1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + end - always @ (posedge clk) begin - mode_d3r <= mode_d2r; - mode_d2r <= mode_d1r; - mode_d1r <= _mode[7:0]; - end + always @(posedge clk) begin + mode_d3r <= mode_d2r; + mode_d2r <= mode_d1r; + mode_d1r <= _mode[7:0]; + end - reg [14:10] bits; - // surefire lint_off SEQASS - always @ (posedge clk) begin - if (_mode==1) begin - bits[14:13] <= 2'b11; - bits[12] <= 1'b1; - end - if (_mode==2) begin - bits[11:10] <= 2'b10; - bits[13] <= 0; - end - if (_mode==3) begin - if (bits !== 5'b10110) $stop; - end - end + reg [14:10] bits; + // surefire lint_off SEQASS + always @(posedge clk) begin + if (_mode == 1) begin + bits[14:13] <= 2'b11; + bits[12] <= 1'b1; + end + if (_mode == 2) begin + bits[11:10] <= 2'b10; + bits[13] <= 0; + end + if (_mode == 3) begin + if (bits !== 5'b10110) $stop; + end + end endmodule diff --git a/test_regress/t/t_c_this.v b/test_regress/t/t_c_this.v index 50bd459f7..d5dcd8f0b 100644 --- a/test_regress/t/t_c_this.v +++ b/test_regress/t/t_c_this.v @@ -4,12 +4,14 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (clk); - input clk; - always @(posedge clk) begin - $c("const CData xthis = this->clk;"); - $c("const CData thisx = xthis;"); - $c("const CData xthisx = thisx;"); - $c("this->clk = xthisx;"); - end +module t ( + clk +); + input clk; + always @(posedge clk) begin + $c("const CData xthis = this->clk;"); + $c("const CData thisx = xthis;"); + $c("const CData xthisx = thisx;"); + $c("this->clk = xthisx;"); + end endmodule diff --git a/test_regress/t/t_case_genx_bad.out b/test_regress/t/t_case_genx_bad.out index 09c1b5392..e5a63f89d 100644 --- a/test_regress/t/t_case_genx_bad.out +++ b/test_regress/t/t_case_genx_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_case_genx_bad.v:14:9: Use of x/? constant in generate case statement, (no such thing as 'generate casez') +%Error: t/t_case_genx_bad.v:14:7: Use of x/? constant in generate case statement, (no such thing as 'generate casez') : ... note: In instance 't' - 14 | 32'b1xxx: initial begin end - | ^~~~~~~~ + 14 | 32'b1xxx: initial begin end + | ^~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_case_genx_bad.v b/test_regress/t/t_case_genx_bad.v index 7c5da4003..21ed53ecf 100644 --- a/test_regress/t/t_case_genx_bad.v +++ b/test_regress/t/t_case_genx_bad.v @@ -6,14 +6,14 @@ module t; - parameter P = 32'b1000; + parameter P = 32'b1000; - generate - case (P) - 32'b0: initial begin end - 32'b1xxx: initial begin end - default initial begin end // No ':' to cover parser - endcase - endgenerate + generate + case (P) + 32'b0: initial begin end + 32'b1xxx: initial begin end + default initial begin end // No ':' to cover parser + endcase + endgenerate endmodule diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v index 3bf1c5124..0325f18b0 100644 --- a/test_regress/t/t_cast.v +++ b/test_regress/t/t_cast.v @@ -5,136 +5,136 @@ // SPDX-License-Identifier: CC0-1.0 interface intf; - typedef logic [7:0] octet; - typedef octet [1:0] word; - octet [1:0] octets; - word [1:0] words; + typedef logic [7:0] octet; + typedef octet [1:0] word; + octet [1:0] octets; + word [1:0] words; endinterface module t; - typedef logic [3:0] mc_t; - typedef mc_t tocast_t; - typedef logic [2:0] [7:0] two_dee_t; + typedef logic [3:0] mc_t; + typedef mc_t tocast_t; + typedef logic [2:0] [7:0] two_dee_t; - typedef struct packed { - logic [15:0] data; - } packed_t; - typedef struct packed { - logic [31:0] data; - } packed2_t; + typedef struct packed { + logic [15:0] data; + } packed_t; + typedef struct packed { + logic [31:0] data; + } packed2_t; - typedef enum [15:0] { - ONE = 1 - } enum_t; + typedef enum [15:0] { + ONE = 1 + } enum_t; - typedef enum_t [3:0] enums_t; + typedef enum_t [3:0] enums_t; - packed_t pdata; - packed_t pdata_reg; - packed2_t pdata2_reg; - assign pdata.data = 16'h1234; - logic [7:0] logic8bit; - assign logic8bit = $bits(logic8bit)'(pdata >> 8); + packed_t pdata; + packed_t pdata_reg; + packed2_t pdata2_reg; + assign pdata.data = 16'h1234; + logic [7:0] logic8bit; + assign logic8bit = $bits(logic8bit)'(pdata >> 8); - mc_t o; - enum_t e; - enums_t es; + mc_t o; + enum_t e; + enums_t es; - intf the_intf(); + intf the_intf(); - logic [15:0] allones = 16'hffff; - parameter FOUR = 4; + logic [15:0] allones = 16'hffff; + parameter FOUR = 4; - localparam two_dee_t two_dee = two_dee_t'(32'habcdef); + localparam two_dee_t two_dee = two_dee_t'(32'habcdef); - // bug925 - localparam [6:0] RESULT = 7'((6*9+92)%96); + // bug925 + localparam [6:0] RESULT = 7'((6*9+92)%96); - logic signed [14:0] samp0 = 15'h0000; - logic signed [14:0] samp1 = 15'h0000; - logic signed [14:0] samp2 = 15'h6000; - logic signed [11:0] coeff0 = 12'h009; - logic signed [11:0] coeff1 = 12'h280; - logic signed [11:0] coeff2 = 12'h4C5; - logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11)); - // verilator lint_off WIDTH - logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11)); - // verilator lint_on WIDTH - logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector - (27'(coeff1 * samp1) >>> 11) + - (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings + logic signed [14:0] samp0 = 15'h0000; + logic signed [14:0] samp1 = 15'h0000; + logic signed [14:0] samp2 = 15'h6000; + logic signed [11:0] coeff0 = 12'h009; + logic signed [11:0] coeff1 = 12'h280; + logic signed [11:0] coeff2 = 12'h4C5; + logic signed [26:0] mida = ((27'(coeff2 * samp2) >>> 11)); + // verilator lint_off WIDTH + logic signed [26:0] midb = 15'((27'(coeff2 * samp2) >>> 11)); + // verilator lint_on WIDTH + logic signed [14:0] outa = 15'((27'(coeff0 * samp0) >>> 11) + // 27' size casting in order for intermediate result to not be truncated to the width of LHS vector + (27'(coeff1 * samp1) >>> 11) + + (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings - logic one = 1'b1; - logic [32:0] b33 = {32'(0), one}; - logic [31:0] b32 = {31'(0), one}; + logic one = 1'b1; + logic [32:0] b33 = {32'(0), one}; + logic [31:0] b32 = {31'(0), one}; - logic [31:0] thirty_two_bits; - two_dee_t two_dee_sig; + logic [31:0] thirty_two_bits; + two_dee_t two_dee_sig; - int i; - initial begin - if (logic8bit != 8'h12) $stop; - if (4'shf > 4'sh0) $stop; - if (signed'(4'hf) > 4'sh0) $stop; - if (4'hf < 4'h0) $stop; - if (unsigned'(4'shf) < 4'h0) $stop; - if (const'(4'shf) !== 4'shf) $stop; - if (4'(allones) !== 4'hf) $stop; - if (6'(allones) !== 6'h3f) $stop; - if ((4)'(allones) !== 4'hf) $stop; - if ((4+2)'(allones) !== 6'h3f) $stop; - if ((4-2)'(allones) !== 2'h3) $stop; - if ((FOUR+2)'(allones) !== 6'h3f) $stop; - if (50 !== RESULT) $stop; + int i; + initial begin + if (logic8bit != 8'h12) $stop; + if (4'shf > 4'sh0) $stop; + if (signed'(4'hf) > 4'sh0) $stop; + if (4'hf < 4'h0) $stop; + if (unsigned'(4'shf) < 4'h0) $stop; + if (const'(4'shf) !== 4'shf) $stop; + if (4'(allones) !== 4'hf) $stop; + if (6'(allones) !== 6'h3f) $stop; + if ((4)'(allones) !== 4'hf) $stop; + if ((4+2)'(allones) !== 6'h3f) $stop; + if ((4-2)'(allones) !== 2'h3) $stop; + if ((FOUR+2)'(allones) !== 6'h3f) $stop; + if (50 !== RESULT) $stop; - e = ONE; - if (e != 1) $stop; - if (e != ONE) $stop; - e = enum_t'(ONE); - if (e != ONE) $stop; - e = enum_t'(16'h1); - if (e != ONE) $stop; - pdata_reg.data = 1; - e = enum_t'(pdata_reg); - if (e != ONE) $stop; + e = ONE; + if (e != 1) $stop; + if (e != ONE) $stop; + e = enum_t'(ONE); + if (e != ONE) $stop; + e = enum_t'(16'h1); + if (e != ONE) $stop; + pdata_reg.data = 1; + e = enum_t'(pdata_reg); + if (e != ONE) $stop; - es = {ONE, ONE, ONE, ONE}; - for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; - es = enums_t'(64'h0001_0001_0001_0001); - for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; + es = {ONE, ONE, ONE, ONE}; + for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; + es = enums_t'(64'h0001_0001_0001_0001); + for (i = 0; i < 4; i++) if (es[i] != ONE) $stop; - o = tocast_t'(4'b1); - if (o != 4'b1) $stop; + o = tocast_t'(4'b1); + if (o != 4'b1) $stop; - the_intf.octets = 16'd1; - pdata_reg = packed_t'(the_intf.octets); - if (pdata_reg.data != 16'd1) $stop; + the_intf.octets = 16'd1; + pdata_reg = packed_t'(the_intf.octets); + if (pdata_reg.data != 16'd1) $stop; - the_intf.words = 32'd1; - pdata2_reg = packed2_t'(the_intf.words); - if (pdata2_reg.data != 32'd1) $stop; + the_intf.words = 32'd1; + pdata2_reg = packed2_t'(the_intf.words); + if (pdata2_reg.data != 32'd1) $stop; - if (15'h6cec != outa) $stop; - if (27'h7ffecec != mida) $stop; - if (27'h7ffecec != midb) $stop; + if (15'h6cec != outa) $stop; + if (27'h7ffecec != mida) $stop; + if (27'h7ffecec != midb) $stop; - if (b33 != 33'b1) $stop; - if (b32 != 32'b1) $stop; + if (b33 != 33'b1) $stop; + if (b32 != 32'b1) $stop; - if (two_dee[0] != 8'hef) $stop; - if (two_dee[1] != 8'hcd) $stop; - if (two_dee[2] != 8'hab) $stop; + if (two_dee[0] != 8'hef) $stop; + if (two_dee[1] != 8'hcd) $stop; + if (two_dee[2] != 8'hab) $stop; - thirty_two_bits = 32'h123456; - two_dee_sig = two_dee_t'(thirty_two_bits); + thirty_two_bits = 32'h123456; + two_dee_sig = two_dee_t'(thirty_two_bits); - if (two_dee_sig[0] != 8'h56) $stop; - if (two_dee_sig[1] != 8'h34) $stop; - if (two_dee_sig[2] != 8'h12) $stop; + if (two_dee_sig[0] != 8'h56) $stop; + if (two_dee_sig[1] != 8'h34) $stop; + if (two_dee_sig[2] != 8'h12) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_cast_param_type.v b/test_regress/t/t_cast_param_type.v index f68e63a4e..ca4814eaa 100644 --- a/test_regress/t/t_cast_param_type.v +++ b/test_regress/t/t_cast_param_type.v @@ -20,7 +20,7 @@ function automatic letters_t lfunc(int a); return letters_t'(1); endfunction -module t (); +module t; localparam FMT = lfunc(1); SubA suba0 (); diff --git a/test_regress/t/t_castdyn_castconst_bad.out b/test_regress/t/t_castdyn_castconst_bad.out index e479532a4..946a30ce3 100644 --- a/test_regress/t/t_castdyn_castconst_bad.out +++ b/test_regress/t/t_castdyn_castconst_bad.out @@ -1,17 +1,17 @@ -%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:20:11: $cast will always return one as 'int' is always castable from 'logic[31:0]' - : ... note: In instance 't' - : ... Suggest static cast - 20 | i = $cast(v, 1); - | ^~~~~ +%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:20:9: $cast will always return one as 'int' is always castable from 'logic[31:0]' + : ... note: In instance 't' + : ... Suggest static cast + 20 | i = $cast(v, 1); + | ^~~~~ ... For warning description see https://verilator.org/warn/CASTCONST?v=latest ... Use "/* verilator lint_off CASTCONST */" and lint_on around source to disable this message. -%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:21:11: $cast will always return one as 'class{}Base' is always castable from 'class{}Base' - : ... note: In instance 't' - : ... Suggest static cast - 21 | i = $cast(b, b); - | ^~~~~ -%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:22:11: $cast will always return zero as 'class{}Base' is not castable from 'class{}Other' - : ... note: In instance 't' - 22 | i = $cast(b, o); - | ^~~~~ +%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:21:9: $cast will always return one as 'class{}Base' is always castable from 'class{}Base' + : ... note: In instance 't' + : ... Suggest static cast + 21 | i = $cast(b, b); + | ^~~~~ +%Warning-CASTCONST: t/t_castdyn_castconst_bad.v:22:9: $cast will always return zero as 'class{}Base' is not castable from 'class{}Other' + : ... note: In instance 't' + 22 | i = $cast(b, o); + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_castdyn_castconst_bad.v b/test_regress/t/t_castdyn_castconst_bad.v index 76ec5e7f5..6b5154e95 100644 --- a/test_regress/t/t_castdyn_castconst_bad.v +++ b/test_regress/t/t_castdyn_castconst_bad.v @@ -8,20 +8,20 @@ class Base; endclass class Other; endclass -enum { ZERO } e; +enum {ZERO} e; module t; - int i; - int v; - Base b; - Other o; - initial begin - i = $cast(v, 1); // 1 - i = $cast(b, b); // 1 - i = $cast(b, o); // 0 - i = $cast(e, 0); // 1 - i = $cast(e, 10); // 0 - end + int i; + int v; + Base b; + Other o; + initial begin + i = $cast(v, 1); // 1 + i = $cast(b, b); // 1 + i = $cast(b, o); // 0 + i = $cast(e, 0); // 1 + i = $cast(e, 10); // 0 + end endmodule diff --git a/test_regress/t/t_castdyn_enum.v b/test_regress/t/t_castdyn_enum.v index 44b6bba5b..3c11e1539 100644 --- a/test_regress/t/t_castdyn_enum.v +++ b/test_regress/t/t_castdyn_enum.v @@ -4,65 +4,67 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -typedef enum {TEN=10, - ELEVEN=11, - SIXTEEN=16} enum_t; +typedef enum { + TEN = 10, + ELEVEN = 11, + SIXTEEN = 16 +} enum_t; -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - int i; - int i_const; - int cyc; - enum_t en; + int i; + int i_const; + int cyc; + enum_t en; - // Constant propagation tests - initial begin - en = SIXTEEN; - i_const = $cast(en, 1); - if (i_const != 0) $stop; - if (en != SIXTEEN) $stop; + // Constant propagation tests + initial begin + en = SIXTEEN; + i_const = $cast(en, 1); + if (i_const != 0) $stop; + if (en != SIXTEEN) $stop; - en = SIXTEEN; - i_const = $cast(en, 10); - if (i_const != 1) $stop; - if (en != TEN) $stop; - end + en = SIXTEEN; + i_const = $cast(en, 10); + if (i_const != 1) $stop; + if (en != TEN) $stop; + end - // Test loop - always @ (posedge clk) begin - i = $cast(en, cyc); + // Test loop + always @(posedge clk) begin + i = $cast(en, cyc); `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d i=%0d en=%0d\n", $time, cyc, i, en); + $write("[%0t] cyc==%0d i=%0d en=%0d\n", $time, cyc, i, en); `endif - cyc <= cyc + 1; - if (cyc == 10) begin - if (i != 1) $stop; - if (en != TEN) $stop; - end - else if (cyc == 11) begin - if (i != 1) $stop; - if (en != ELEVEN) $stop; - end - else if (cyc == 12) begin - if (i != 0) $stop; - if (en != ELEVEN) $stop; - end - else if (cyc == 16) begin - if (i != 1) $stop; - if (en != SIXTEEN) $stop; - end - else if (cyc == 17) begin - if (i != 0) $stop; - if (en != SIXTEEN) $stop; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc == 10) begin + if (i != 1) $stop; + if (en != TEN) $stop; + end + else if (cyc == 11) begin + if (i != 1) $stop; + if (en != ELEVEN) $stop; + end + else if (cyc == 12) begin + if (i != 0) $stop; + if (en != ELEVEN) $stop; + end + else if (cyc == 16) begin + if (i != 1) $stop; + if (en != SIXTEEN) $stop; + end + else if (cyc == 17) begin + if (i != 0) $stop; + if (en != SIXTEEN) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_castdyn_unsup_bad.out b/test_regress/t/t_castdyn_unsup_bad.out index 781b340eb..5bda83857 100644 --- a/test_regress/t/t_castdyn_unsup_bad.out +++ b/test_regress/t/t_castdyn_unsup_bad.out @@ -1,7 +1,7 @@ -%Error-UNSUPPORTED: t/t_castdyn_unsup_bad.v:13:7: Unsupported: $cast to 'string$[$]' from 'int$[string]' +%Error-UNSUPPORTED: t/t_castdyn_unsup_bad.v:13:5: Unsupported: $cast to 'string$[$]' from 'int$[string]' : ... note: In instance 't' : ... Suggest try static cast - 13 | $cast(q, aarray); - | ^~~~~ + 13 | $cast(q, aarray); + | ^~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_castdyn_unsup_bad.v b/test_regress/t/t_castdyn_unsup_bad.v index d36ae6406..f21d7b742 100644 --- a/test_regress/t/t_castdyn_unsup_bad.v +++ b/test_regress/t/t_castdyn_unsup_bad.v @@ -6,11 +6,11 @@ module t; - string q[$]; - int aarray[string]; + string q[$]; + int aarray[string]; - initial begin - $cast(q, aarray); - end + initial begin + $cast(q, aarray); + end endmodule diff --git a/test_regress/t/t_checker.v b/test_regress/t/t_checker.v index 099423cea..182fea31c 100644 --- a/test_regress/t/t_checker.v +++ b/test_regress/t/t_checker.v @@ -4,44 +4,42 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t( + input clk + ); - integer cyc = 0; + integer cyc = 0; - bit failure; - mutex check_bus(cyc, clk, failure); + bit failure; + mutex check_bus(cyc, clk, failure); - integer cyc_d1; - always @ (posedge clk) cyc_d1 <= cyc; + integer cyc_d1; + always @ (posedge clk) cyc_d1 <= cyc; - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d cyc_d1=0x%0x exp=%x failure=%x\n", - $time, cyc, cyc_d1, $onehot0(cyc), failure); + $write("[%0t] cyc==%0d cyc_d1=0x%0x exp=%x failure=%x\n", + $time, cyc, cyc_d1, $onehot0(cyc), failure); `endif - cyc <= cyc + 1; - if (cyc < 3) begin - end - else if (cyc < 90) begin - if (failure !== !$onehot0(cyc)) $stop; - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc < 3) begin + end + else if (cyc < 90) begin + if (failure !== !$onehot0(cyc)) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule checker mutex (input logic [31:0] sig, input bit clk, output bit failure); - logic [31:0] last_sig; - assert property (@(negedge clk) $onehot0(sig)) - failure = 1'b0; else failure = 1'b1; - assert property (@(negedge clk) sig == last_sig + 1); - always_ff @(posedge clk) last_sig <= sig; + logic [31:0] last_sig; + assert property (@(negedge clk) $onehot0(sig)) + failure = 1'b0; else failure = 1'b1; + assert property (@(negedge clk) sig == last_sig + 1); + always_ff @(posedge clk) last_sig <= sig; endchecker diff --git a/test_regress/t/t_checker_unsup.out b/test_regress/t/t_checker_unsup.out index 47f44ac75..3f8643ee3 100644 --- a/test_regress/t/t_checker_unsup.out +++ b/test_regress/t/t_checker_unsup.out @@ -1,20 +1,20 @@ -%Error-UNSUPPORTED: t/t_checker_unsup.v:31:12: Unsupported: 'checker' below unit-level - 31 | checker checker_in_module; - | ^~~~~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:29:11: Unsupported: 'checker' below unit-level + 29 | checker checker_in_module; + | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_checker_unsup.v:37:12: Unsupported: 'checker' below unit-level - 37 | checker checker_in_pkg; - | ^~~~~~~~~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:41:29: Unsupported: checker port variable default value - 41 | checker Chk(input defaulted = 1'b0); +%Error-UNSUPPORTED: t/t_checker_unsup.v:35:11: Unsupported: 'checker' below unit-level + 35 | checker checker_in_pkg; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:39:29: Unsupported: checker port variable default value + 39 | checker Chk(input defaulted = 1'b0); | ^ -%Error-UNSUPPORTED: t/t_checker_unsup.v:45:4: Unsupported: checker rand - 45 | rand bit randed; - | ^~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:67:4: Unsupported: default clocking identifier - 67 | default clocking clk; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:70:12: Unsupported: recursive 'checker' - 70 | checker ChkChk; - | ^~~~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:43:3: Unsupported: checker rand + 43 | rand bit randed; + | ^~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:65:3: Unsupported: default clocking identifier + 65 | default clocking clk; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:68:11: Unsupported: recursive 'checker' + 68 | checker ChkChk; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_checker_unsup.v b/test_regress/t/t_checker_unsup.v index 4926cd4ab..7f4e236b8 100644 --- a/test_regress/t/t_checker_unsup.v +++ b/test_regress/t/t_checker_unsup.v @@ -4,83 +4,81 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t( + input clk + ); - integer cyc = 0; + integer cyc = 0; - // Test loop - always @ (posedge clk) begin + // Test loop + always @ (posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d\n", $time, cyc); + $write("[%0t] cyc==%0d\n", $time, cyc); `endif - cyc <= cyc + 1; - if (cyc == 0) begin - end - else if (cyc == 99) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + if (cyc == 0) begin + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end - Chk check(clk, cyc); + Chk check(clk, cyc); - checker checker_in_module; - endchecker + checker checker_in_module; + endchecker endmodule package Pkg; - checker checker_in_pkg; - endchecker + checker checker_in_pkg; + endchecker endpackage checker Chk(input defaulted = 1'b0); - bit clk; - bit in; - bit rst; - rand bit randed; // TODO test this + bit clk; + bit in; + bit rst; + rand bit randed; // TODO test this - int counter = 0; + int counter = 0; - int ival; - final if (ival != 1234) $stop; - genvar g; - if (0) begin - initial ival = 1; - end - else begin - initial ival = 1234; - end + int ival; + final if (ival != 1234) $stop; + genvar g; + if (0) begin + initial ival = 1; + end + else begin + initial ival = 1234; + end - int ival2; - case (1) - 0: initial ival2 = 0; - default: initial ival2 = 12345; - endcase - final if (ival2 != 12345) $stop; + int ival2; + case (1) + 0: initial ival2 = 0; + default: initial ival2 = 12345; + endcase + final if (ival2 != 12345) $stop; - default clocking clk; // TODO test this - default disable iff rst; // TODO test this + default clocking clk; // TODO test this + default disable iff rst; // TODO test this - checker ChkChk; // TODO flag unsupported - endchecker + checker ChkChk; // TODO flag unsupported + endchecker - function automatic int f; // TODO test this - endfunction + function automatic int f; // TODO test this + endfunction - clocking cb1 @(posedge clk); // TODO test this - input in; - output out; - endclocking + clocking cb1 @(posedge clk); // TODO test this + input in; + output out; + endclocking - always_ff @(posedge clk) - counter <= counter + 1'b1; + always_ff @(posedge clk) + counter <= counter + 1'b1; - a1: assert property (@(posedge clk) counter == in); + a1: assert property (@(posedge clk) counter == in); endchecker diff --git a/test_regress/t/t_class1.v b/test_regress/t/t_class1.v index 1c4dc3736..d00b5cccb 100644 --- a/test_regress/t/t_class1.v +++ b/test_regress/t/t_class1.v @@ -7,32 +7,32 @@ typedef class Cls; class Cls; - int imembera; - int imemberb; + int imembera; + int imemberb; endclass : Cls module t; - typedef Cls Cls2; + typedef Cls Cls2; - initial begin - Cls c; - Cls2 c2; - if (c != null) $stop; - if (c) $stop; - if (c2) $stop; - $display("Display: null = \"%p\"", c); // null - c = new; - c2 = new; - if (c == null) $stop; - if (!c) $stop; - if (!c2) $stop; - $display("Display: newed = \"%p\"", c); // '{imembera:0, imemberb:0} - c.imembera = 10; - c.imemberb = 20; - $display("Display: set = \"%p\"", c); // '{imembera:10, imemberb:20} - if (c.imembera != 10) $stop; - if (c.imemberb != 20) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + Cls c; + Cls2 c2; + if (c != null) $stop; + if (c) $stop; + if (c2) $stop; + $display("Display: null = \"%p\"", c); // null + c = new; + c2 = new; + if (c == null) $stop; + if (!c) $stop; + if (!c2) $stop; + $display("Display: newed = \"%p\"", c); // '{imembera:0, imemberb:0} + c.imembera = 10; + c.imemberb = 20; + $display("Display: set = \"%p\"", c); // '{imembera:10, imemberb:20} + if (c.imembera != 10) $stop; + if (c.imemberb != 20) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class2.v b/test_regress/t/t_class2.v index d3bfc7962..5ef217e4a 100644 --- a/test_regress/t/t_class2.v +++ b/test_regress/t/t_class2.v @@ -5,41 +5,41 @@ // SPDX-License-Identifier: CC0-1.0 package Pkg; - typedef enum { ENUMP_VAL = 33 } enump_t; + typedef enum {ENUMP_VAL = 33} enump_t; endpackage module t; -class Cls; - int imembera; - int imemberb; - typedef enum { ENUM_VAL = 22 } enum_t; -endclass : Cls + class Cls; + int imembera; + int imemberb; + typedef enum {ENUM_VAL = 22} enum_t; + endclass : Cls - Cls c; - Cls d; + Cls c; + Cls d; - Cls::enum_t e; + Cls::enum_t e; - initial begin - // Alternate between two versions to make sure we don't - // constant propagate between them. - c = new; - d = new; - e = Cls::ENUM_VAL; - c.imembera = 10; - d.imembera = 11; - c.imemberb = 20; - d.imemberb = 21; - if (c.imembera != 10) $stop; - if (d.imembera != 11) $stop; - if (c.imemberb != 20) $stop; - if (d.imemberb != 21) $stop; - if (Pkg::ENUMP_VAL != 33) $stop; - if (Cls::ENUM_VAL != 22) $stop; - if (c.ENUM_VAL != 22) $stop; - if (e != Cls::ENUM_VAL) $stop; - if (e != 22) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // Alternate between two versions to make sure we don't + // constant propagate between them. + c = new; + d = new; + e = Cls::ENUM_VAL; + c.imembera = 10; + d.imembera = 11; + c.imemberb = 20; + d.imemberb = 21; + if (c.imembera != 10) $stop; + if (d.imembera != 11) $stop; + if (c.imemberb != 20) $stop; + if (d.imemberb != 21) $stop; + if (Pkg::ENUMP_VAL != 33) $stop; + if (Cls::ENUM_VAL != 22) $stop; + if (c.ENUM_VAL != 22) $stop; + if (e != Cls::ENUM_VAL) $stop; + if (e != 22) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_class_builtin_bad.out b/test_regress/t/t_class_builtin_bad.out index ebe06364a..60dc885a8 100644 --- a/test_regress/t/t_class_builtin_bad.out +++ b/test_regress/t/t_class_builtin_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_class_builtin_bad.v:8:17: The 'rand_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.8) +%Error: t/t_class_builtin_bad.v:8:16: The 'rand_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.8) : ... note: In instance 't' - 8 | function int rand_mode(bit onoff); - | ^~~~~~~~~ + 8 | function int rand_mode(bit onoff); + | ^~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_class_builtin_bad.v:11:17: The 'constraint_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.9) +%Error: t/t_class_builtin_bad.v:11:16: The 'constraint_mode' method is built-in and cannot be overridden (IEEE 1800-2023 18.9) : ... note: In instance 't' - 11 | function int constraint_mode(bit onoff); - | ^~~~~~~~~~~~~~~ + 11 | function int constraint_mode(bit onoff); + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_builtin_bad.v b/test_regress/t/t_class_builtin_bad.v index 5f3c42ade..e157f5b77 100644 --- a/test_regress/t/t_class_builtin_bad.v +++ b/test_regress/t/t_class_builtin_bad.v @@ -5,16 +5,16 @@ // SPDX-License-Identifier: CC0-1.0 class Cls; - function int rand_mode(bit onoff); - return 1; - endfunction - function int constraint_mode(bit onoff); - return 1; - endfunction + function int rand_mode(bit onoff); + return 1; + endfunction + function int constraint_mode(bit onoff); + return 1; + endfunction endclass module t; - initial begin - Cls c; - end + initial begin + Cls c; + end endmodule diff --git a/test_regress/t/t_class_eq.v b/test_regress/t/t_class_eq.v index be9814153..8a17f094b 100644 --- a/test_regress/t/t_class_eq.v +++ b/test_regress/t/t_class_eq.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; class A; int num; diff --git a/test_regress/t/t_class_extends_arg.v b/test_regress/t/t_class_extends_arg.v index 08f6323d2..784a66c7d 100644 --- a/test_regress/t/t_class_extends_arg.v +++ b/test_regress/t/t_class_extends_arg.v @@ -26,7 +26,7 @@ class Cls5Imp extends Base(5); // Implicit new endclass -module t (); +module t; Cls5Exp ce; Cls5Imp ci; diff --git a/test_regress/t/t_class_new_typed.v b/test_regress/t/t_class_new_typed.v index b870a8b59..76dedbf49 100644 --- a/test_regress/t/t_class_new_typed.v +++ b/test_regress/t/t_class_new_typed.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2025 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; class SuperCls; int s = 2; function new(int def = 3); diff --git a/test_regress/t/t_class_wide.v b/test_regress/t/t_class_wide.v index 271d7c1a3..22fe39756 100644 --- a/test_regress/t/t_class_wide.v +++ b/test_regress/t/t_class_wide.v @@ -12,7 +12,7 @@ class item; bit [`WIDTH-1:0] data; endclass -module t (); +module t; logic [`WIDTH-1:0] data; item item0 = new; diff --git a/test_regress/t/t_clocked_release_combo.v b/test_regress/t/t_clocked_release_combo.v index 0698ffbfd..0d5bcef73 100644 --- a/test_regress/t/t_clocked_release_combo.v +++ b/test_regress/t/t_clocked_release_combo.v @@ -5,10 +5,10 @@ // SPDX-License-Identifier: CC0-1.0 // verilator lint_off MULTIDRIVEN -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( /*AUTOARG*/ + // Inputs + clk +); input clk; logic [31:0] lhs1, lhs2, rhs; @@ -36,16 +36,16 @@ module t (/*AUTOARG*/ if (cyc == 0) cond <= 1; if (cyc == 3) cond <= 0; if (cyc > 1 && cyc < 4) begin - if (lhs1 != 'hdeadbeef) $stop; - if (lhs2 != 'hfeedface) $stop; + if (lhs1 != 'hdeadbeef) $stop; + if (lhs2 != 'hfeedface) $stop; end if (cyc > 4 && cyc < 8) begin - if (lhs1 != '1) $stop; - if (lhs2 != '1) $stop; + if (lhs1 != '1) $stop; + if (lhs2 != '1) $stop; end if (cyc >= 8) begin - $write("*-* All Finished *-*\n"); - $finish; + $write("*-* All Finished *-*\n"); + $finish; end end endmodule diff --git a/test_regress/t/t_clocker.v b/test_regress/t/t_clocker.v index e51d195e9..5816818c6 100644 --- a/test_regress/t/t_clocker.v +++ b/test_regress/t/t_clocker.v @@ -9,51 +9,51 @@ localparam ID_MSB = 1; -module t (/*AUTOARG*/ - // Inputs - clk, - res, - res8, - res16 - ); - input clk; - output reg res; - // When not inlining the below may trigger CLKDATA - output reg [7:0] res8; - output reg [15:0] res16; +module t ( /*AUTOARG*/ + // Inputs + clk, + res, + res8, + res16 +); + input clk; + output reg res; + // When not inlining the below may trigger CLKDATA + output reg [7:0] res8; + output reg [15:0] res16; - wire [7:0] clkSet; - wire clk_1; - wire [2:0] clk_3; - wire [3:0] clk_4; - wire clk_final; - reg [7:0] count; + wire [7:0] clkSet; + wire clk_1; + wire [2:0] clk_3; + wire [3:0] clk_4; + wire clk_final; + reg [7:0] count; - assign clkSet = {8{clk}}; - assign clk_4 = clkSet[7:4]; - assign clk_1 = clk_4[0];; + assign clkSet = {8{clk}}; + assign clk_4 = clkSet[7:4]; + assign clk_1 = clk_4[0]; + ; - // arraysel - assign clk_3 = {3{clk_1}}; - assign clk_final = clk_3[0]; + // arraysel + assign clk_3 = {3{clk_1}}; + assign clk_final = clk_3[0]; - assign res8 = {clk_3, 1'b0, clk_4}; - assign res16 = {count, clk_3, clk_1, clk_4}; + assign res8 = {clk_3, 1'b0, clk_4}; + assign res16 = {count, clk_3, clk_1, clk_4}; - initial - count = 0; + initial count = 0; - always @(posedge clk_final or negedge clk_final) begin - count = count + 1; - res <= clk_final; - if ( count == 8'hf) begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk_final or negedge clk_final) begin + count = count + 1; + res <= clk_final; + if (count == 8'hf) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_clocking_empty_block.v b/test_regress/t/t_clocking_empty_block.v index 76d371dcb..3bacba39b 100644 --- a/test_regress/t/t_clocking_empty_block.v +++ b/test_regress/t/t_clocking_empty_block.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Alex Mykyta // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; logic clk = 0; logic x; logic y; diff --git a/test_regress/t/t_comb_do_not_convert_to.v b/test_regress/t/t_comb_do_not_convert_to.v index 33b172315..b8250eb1c 100644 --- a/test_regress/t/t_comb_do_not_convert_to.v +++ b/test_regress/t/t_comb_do_not_convert_to.v @@ -13,45 +13,45 @@ module t ( output reg o_3, output reg o_4, output reg o_5 - ); +); - input clk; + input clk; - reg a = 0; - reg b = 0; + reg a = 0; + reg b = 0; - event e; + event e; - // We must not convert these blocks into combinational blocks + // We must not convert these blocks into combinational blocks - always @(i) begin - a <= ~a; - o_0 = i; - end + always @(i) begin + a <= ~a; + o_0 = i; + end - always @(i) begin - force b = 1; - o_1 = i; - end + always @(i) begin + force b = 1; + o_1 = i; + end - always @(i) begin - release b; - o_2 = i; - end + always @(i) begin + release b; + o_2 = i; + end - always @(i) begin - -> e; - o_3 = i; - end + always @(i) begin + ->e; + o_3 = i; + end - always @(i) begin - ->> e; - o_4 = i; - end + always @(i) begin + ->>e; + o_4 = i; + end - always @(i) begin - $display("Hello"); - o_5 = i; - end + always @(i) begin + $display("Hello"); + o_5 = i; + end endmodule diff --git a/test_regress/t/t_comb_input_0.v b/test_regress/t/t_comb_input_0.v index 8ed63208b..003785e9b 100644 --- a/test_regress/t/t_comb_input_0.v +++ b/test_regress/t/t_comb_input_0.v @@ -7,9 +7,9 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module top( - clk, - inc +module top ( + clk, + inc ); input clk; @@ -23,7 +23,7 @@ module top( always @(posedge clk) begin $display("cyc: %d sum: %d", cyc, sum); - if (sum != 2*cyc + 1) $stop; + if (sum != 2 * cyc + 1) $stop; cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_comb_input_1.v b/test_regress/t/t_comb_input_1.v index 98a81e175..54d30f01b 100644 --- a/test_regress/t/t_comb_input_1.v +++ b/test_regress/t/t_comb_input_1.v @@ -7,9 +7,9 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module top( - clk, - inc +module top ( + clk, + inc ); input clk; @@ -28,7 +28,7 @@ module top( always @(posedge clk) begin $display("cyc: %d sum: %d", cyc, sum); - if (sum != 2*cyc + 1) $stop; + if (sum != 2 * cyc + 1) $stop; cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_comb_input_2.v b/test_regress/t/t_comb_input_2.v index d2047021b..39d1acaef 100644 --- a/test_regress/t/t_comb_input_2.v +++ b/test_regress/t/t_comb_input_2.v @@ -14,9 +14,9 @@ `define IMPURE_ONE (|($random | $random)) `endif -module top( - clk, - inc +module top ( + clk, + inc ); input clk; @@ -37,7 +37,7 @@ module top( always @(posedge clk) begin $display("cyc: %d sum: %d", cyc, sum); - if (sum != 2*cyc + 1) $stop; + if (sum != 2 * cyc + 1) $stop; cyc <= cyc + 1; if (cyc == 100) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_comb_loop_through_unpacked_array.v b/test_regress/t/t_comb_loop_through_unpacked_array.v index d7992c98f..c88b1e5d3 100644 --- a/test_regress/t/t_comb_loop_through_unpacked_array.v +++ b/test_regress/t/t_comb_loop_through_unpacked_array.v @@ -6,14 +6,14 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module top( - input wire a, - input wire b, - output wire o +module top ( + input wire a, + input wire b, + output wire o ); - logic [255:0] array [1:0]; - logic [255:0] tmp [1:0]; + logic [255:0] array[1:0]; + logic [255:0] tmp[1:0]; // Nonsensical, but needs to compile. (In some real designs we can end up // with combinational loops via unpacked arrays) diff --git a/test_regress/t/t_compiler_include.v b/test_regress/t/t_compiler_include.v index 90437a0b3..58085ee32 100644 --- a/test_regress/t/t_compiler_include.v +++ b/test_regress/t/t_compiler_include.v @@ -6,6 +6,9 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (input logic[31:0] in, output logic[31:0] out); - assign out = in; +module t ( + input logic [31:0] in, + output logic [31:0] out +); + assign out = in; endmodule diff --git a/test_regress/t/t_compiler_include_dpi.v b/test_regress/t/t_compiler_include_dpi.v index 25f6dd00a..297cade39 100644 --- a/test_regress/t/t_compiler_include_dpi.v +++ b/test_regress/t/t_compiler_include_dpi.v @@ -7,25 +7,30 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; - int a = 123; - int b = 321; - int out; + int a = 123; + int b = 321; + int out; - import "DPI-C" function void dpii_add - (int a, int b, ref int out); - import "DPI-C" function int dpii_add_check - (int actual, int expected); + import "DPI-C" function void dpii_add( + int a, + int b, + ref int out + ); + import "DPI-C" function int dpii_add_check( + int actual, + int expected + ); - initial begin - dpii_add(a, b, out); - if (dpii_add_check(out, (a + b)) != 1) begin - $write("%%Error: Failure in DPI tests\n"); - $stop; - end - else begin - $write("*-* All Finished *-*\n"); - $finish; - end - end + initial begin + dpii_add(a, b, out); + if (dpii_add_check(out, (a + b)) != 1) begin + $write("%%Error: Failure in DPI tests\n"); + $stop; + end + else begin + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_concat_casts.v b/test_regress/t/t_concat_casts.v index 014348ad7..c90070bee 100644 --- a/test_regress/t/t_concat_casts.v +++ b/test_regress/t/t_concat_casts.v @@ -5,37 +5,39 @@ // SPDX-License-Identifier: CC0-1.0 package my_pkg; - typedef enum logic [1:0] { - SIG_0, SIG_1, SIG_2 - } sig_t; + typedef enum logic [1:0] { + SIG_0, + SIG_1, + SIG_2 + } sig_t; endpackage : my_pkg module t; - import my_pkg::*; + import my_pkg::*; - typedef logic [7:0] foo_t; - typedef logic [31:0] bar_t; + typedef logic [7:0] foo_t; + typedef logic [31:0] bar_t; - bar_t [1:0] the_bars; + bar_t [1:0] the_bars; - foo_t [0:0][1:0] the_foos; + foo_t [0:0][1:0] the_foos; - always_comb begin - the_bars = {32'd7, 32'd8}; - the_foos[0] = {foo_t'(the_bars[1]), foo_t'(the_bars[0])}; - end + always_comb begin + the_bars = {32'd7, 32'd8}; + the_foos[0] = {foo_t'(the_bars[1]), foo_t'(the_bars[0])}; + end - logic [6:0] data; - logic [2:0] opt; + logic [6:0] data; + logic [2:0] opt; - assign data = 7'b110_0101; - assign opt = {data[5], sig_t'(data[1:0])}; + assign data = 7'b110_0101; + assign opt = {data[5], sig_t'(data[1:0])}; - initial begin - if (the_foos != 'h0708) $stop(); - if (opt != 'b101) $stop(); - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (the_foos != 'h0708) $stop(); + if (opt != 'b101) $stop(); + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_concat_impure.v b/test_regress/t/t_concat_impure.v index 16499b370..3c28aabf1 100644 --- a/test_regress/t/t_concat_impure.v +++ b/test_regress/t/t_concat_impure.v @@ -7,21 +7,21 @@ int global_variable = 0; function int side_effect; - global_variable++; + global_variable++; return 1; endfunction module t; - reg [15:0] x; - reg [15:0] y; - initial begin - {x, y} = side_effect() + 2; + reg [15:0] x; + reg [15:0] y; + initial begin + {x, y} = side_effect() + 2; - if (y != 3) $stop; - if (x != 0) $stop; - if (global_variable != 1) $stop; + if (y != 3) $stop; + if (x != 0) $stop; + if (global_variable != 1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_concat_link_bad.out b/test_regress/t/t_concat_link_bad.out index a4fc82936..82f785bf5 100644 --- a/test_regress/t/t_concat_link_bad.out +++ b/test_regress/t/t_concat_link_bad.out @@ -1,25 +1,25 @@ -%Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting REPLICATE under a DOT in dotted expression - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ - t/t_concat_link_bad.v:13:34: ... Resolving this reference - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ +%Error: t/t_concat_link_bad.v:13:18: Syntax error: Not expecting REPLICATE under a DOT in dotted expression + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ + t/t_concat_link_bad.v:13:32: ... Resolving this reference + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_concat_link_bad.v:13:26: Syntax error: Not expecting CONCAT under a REPLICATE in dotted expression - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ - t/t_concat_link_bad.v:13:34: ... Resolving this reference - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ -%Error: t/t_concat_link_bad.v:13:20: Syntax error: Not expecting CONST under a REPLICATE in dotted expression - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ - t/t_concat_link_bad.v:13:34: ... Resolving this reference - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^ -%Warning-IMPLICIT: t/t_concat_link_bad.v:13:12: Signal definition not found, creating implicitly: 'bar_s' - 13 | assign bar_s = {foo_s, foo_s}.f1; - | ^~~~~ +%Error: t/t_concat_link_bad.v:13:24: Syntax error: Not expecting CONCAT under a REPLICATE in dotted expression + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ + t/t_concat_link_bad.v:13:32: ... Resolving this reference + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ +%Error: t/t_concat_link_bad.v:13:18: Syntax error: Not expecting CONST under a REPLICATE in dotted expression + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ + t/t_concat_link_bad.v:13:32: ... Resolving this reference + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ +%Warning-IMPLICIT: t/t_concat_link_bad.v:13:10: Signal definition not found, creating implicitly: 'bar_s' + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^~~~~ ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_concat_link_bad.v b/test_regress/t/t_concat_link_bad.v index 576f03b59..e05d338f0 100644 --- a/test_regress/t/t_concat_link_bad.v +++ b/test_regress/t/t_concat_link_bad.v @@ -6,10 +6,10 @@ module t; - typedef logic [3:0] foo_t; + typedef logic [3:0] foo_t; - foo_t foo_s; + foo_t foo_s; - assign bar_s = {foo_s, foo_s}.f1; + assign bar_s = {foo_s, foo_s}.f1; endmodule diff --git a/test_regress/t/t_concat_opt.v b/test_regress/t/t_concat_opt.v index 3f85fa53b..adfde02b3 100644 --- a/test_regress/t/t_concat_opt.v +++ b/test_regress/t/t_concat_opt.v @@ -6,66 +6,62 @@ // // The test was added together with the concat optimization. -module t (/*AUTOARG*/ - // Inputs - clk - ); +module t ( + input clk +); - input clk; - integer cyc; initial cyc=1; + integer cyc; + initial cyc = 1; - reg [31:0] in_a; - reg [31:0] in_b; - reg [31:0] in_c; - reg [31:0] in_d; - reg [31:0] in_e; - reg [15:0] in_f; - wire [31:0] in_g; + reg [31:0] in_a; + reg [31:0] in_b; + reg [31:0] in_c; + reg [31:0] in_d; + reg [31:0] in_e; + reg [15:0] in_f; + wire [31:0] in_g; - assign in_g = in_a << 4; + assign in_g = in_a << 4; - reg [31:0] out_x; - reg [31:0] out_y; - reg [31:0] out_z; - reg [31:0] out_o; - reg [31:0] out_p; - reg [31:0] out_q; + reg [31:0] out_x; + reg [31:0] out_y; + reg [31:0] out_z; + reg [31:0] out_o; + reg [31:0] out_p; + reg [31:0] out_q; - assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f}; - assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]}; - assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]}; - assign out_o = out_z | out_y; - assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]}; - assign out_q = {{in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]}}; + assign out_x = {in_a[31:16] & in_f, in_a[15:0] & in_f}; + assign out_y = {in_a[31:18] & in_b[31:18], in_a[17:0] & in_b[17:0]}; + assign out_z = {in_c[31:14] & in_d[31:14] & in_e[31:14], in_c[13:0] & in_d[13:0] & in_e[13:0]}; + assign out_o = out_z | out_y; + assign out_p = {in_a[31:16] & in_f | in_e[31:16], in_a[15:0] & in_f | in_e[15:0]}; + assign out_q = { + {in_a[31:25] ^ in_g[31:25], in_a[24:16] ^ in_g[24:16]}, + {in_a[15:5] ^ in_g[15:5], in_a[4:0] ^ in_g[4:0]} + }; - always @ (posedge clk) begin - if (cyc!=0) begin - cyc <= cyc + 1; - in_a <= cyc; - in_b <= cyc + 1; - in_c <= cyc + 3; - in_d <= cyc + 8; - in_e <= cyc; - in_f <= cyc[15:0]; + always @(posedge clk) begin + if (cyc != 0) begin + cyc <= cyc + 1; + in_a <= cyc; + in_b <= cyc + 1; + in_c <= cyc + 3; + in_d <= cyc + 8; + in_e <= cyc; + in_f <= cyc[15:0]; - if (out_x != (in_a & {2{in_f}})) - $stop; - if (out_y != (in_a&in_b)) - $stop; - if (out_z != (in_e&in_d&in_c)) - $stop; - if (out_o != (((in_a&in_b)|(in_c&in_e&in_d)))) - $stop; - if (out_p != (in_a & {2{in_f}} | in_e)) - $stop; - if (out_q != (in_a ^ in_g)) - $stop; + if (out_x != (in_a & {2{in_f}})) $stop; + if (out_y != (in_a & in_b)) $stop; + if (out_z != (in_e & in_d & in_c)) $stop; + if (out_o != (((in_a & in_b) | (in_c & in_e & in_d)))) $stop; + if (out_p != (in_a & {2{in_f}} | in_e)) $stop; + if (out_q != (in_a ^ in_g)) $stop; - if (cyc==100) begin - $write("*-* All Finished *-*\n"); - $finish; - end + if (cyc == 100) begin + $write("*-* All Finished *-*\n"); + $finish; end - end + end + end endmodule diff --git a/test_regress/t/t_concat_or.v b/test_regress/t/t_concat_or.v index 5fa2acd57..03017634d 100644 --- a/test_regress/t/t_concat_or.v +++ b/test_regress/t/t_concat_or.v @@ -4,69 +4,71 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Outputs - i299, - // Inputs - i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, i200, i201, i202, - i203, i204, i205, i182, i183, i184, i185, i186, i187, i188, i189, i206, i282, - i284, i286, i287, i289, i290, i294, i34, i288, i31, i296, i37, i38 - ); - input [3:0] i190; - input [3:0] i191; - input [3:0] i192; - input [3:0] i193; - input [3:0] i194; - input [3:0] i195; - input [3:0] i196; - input [3:0] i197; - input [3:0] i198; - input [3:0] i199; - input [3:0] i200; - input [3:0] i201; - input [3:0] i202; - input [3:0] i203; - input [3:0] i204; - input [3:0] i205; - input [3:0] i182; - input [3:0] i183; - input [3:0] i184; - input [3:0] i185; - input [3:0] i186; - input [3:0] i187; - input [3:0] i188; - input [3:0] i189; - input [3:0] i206; - input [3:0] i282; - input [3:0] i284; - input [3:0] i286; - input [3:0] i287; - input [3:0] i289; - input [3:0] i290; - input [3:0] i294; - input [3:0] i34; - input [3:0] i288; - input [3:0] i31; - input [3:0] i296; - input [3:0] i37; - input [3:0] i38; +// verilog_format: off - output [3:0] i299; - assign i299 = { i296[2:0] | i31[3:1] | i282[3:1] | i284[3:1] | i34[3:1] - | i286[3:1] | i287[3:1] | i37[3:1] | i38[3:1] - | i288[3:1] | i289[3:1] | i290[3:1] | i182[3:1] - | i183[3:1] | i184[3:1] | i185[3:1] | i186[3:1] - | i187[3:1] | i188[3:1] | i189[3:1] | i190[3:1] - | i191[3:1] | i192[3:1] | i193[3:1] | i194[3:1] - | i195[3:1] | i196[3:1] | i197[3:1] | i198[3:1] - | i199[3:1] | i200[3:1] | i201[3:1] | i202[3:1] - | i203[3:1] | i204[3:1] | i205[3:1] | i206[3:1] - , - i294[0] | i289[0] | i290[0] | i182[0] | i183[0] - | i184[0] | i185[0] | i186[0] | i187[0] | i188[0] - | i189[0] | i190[0] | i191[0] | i192[0] | i193[0] - | i194[0] | i195[0] | i196[0] | i197[0] | i198[0] - | i199[0] | i200[0] | i201[0] | i202[0] | i203[0] - | i204[0] | i205[0] | i206[0] }; +module t(/*AUTOARG*/ + // Outputs + i299, + // Inputs + i190, i191, i192, i193, i194, i195, i196, i197, i198, i199, i200, i201, i202, + i203, i204, i205, i182, i183, i184, i185, i186, i187, i188, i189, i206, i282, + i284, i286, i287, i289, i290, i294, i34, i288, i31, i296, i37, i38 + ); + input [3:0] i190; + input [3:0] i191; + input [3:0] i192; + input [3:0] i193; + input [3:0] i194; + input [3:0] i195; + input [3:0] i196; + input [3:0] i197; + input [3:0] i198; + input [3:0] i199; + input [3:0] i200; + input [3:0] i201; + input [3:0] i202; + input [3:0] i203; + input [3:0] i204; + input [3:0] i205; + input [3:0] i182; + input [3:0] i183; + input [3:0] i184; + input [3:0] i185; + input [3:0] i186; + input [3:0] i187; + input [3:0] i188; + input [3:0] i189; + input [3:0] i206; + input [3:0] i282; + input [3:0] i284; + input [3:0] i286; + input [3:0] i287; + input [3:0] i289; + input [3:0] i290; + input [3:0] i294; + input [3:0] i34; + input [3:0] i288; + input [3:0] i31; + input [3:0] i296; + input [3:0] i37; + input [3:0] i38; + + output [3:0] i299; + assign i299 = { i296[2:0] | i31[3:1] | i282[3:1] | i284[3:1] | i34[3:1] + | i286[3:1] | i287[3:1] | i37[3:1] | i38[3:1] + | i288[3:1] | i289[3:1] | i290[3:1] | i182[3:1] + | i183[3:1] | i184[3:1] | i185[3:1] | i186[3:1] + | i187[3:1] | i188[3:1] | i189[3:1] | i190[3:1] + | i191[3:1] | i192[3:1] | i193[3:1] | i194[3:1] + | i195[3:1] | i196[3:1] | i197[3:1] | i198[3:1] + | i199[3:1] | i200[3:1] | i201[3:1] | i202[3:1] + | i203[3:1] | i204[3:1] | i205[3:1] | i206[3:1] + , + i294[0] | i289[0] | i290[0] | i182[0] | i183[0] + | i184[0] | i185[0] | i186[0] | i187[0] | i188[0] + | i189[0] | i190[0] | i191[0] | i192[0] | i193[0] + | i194[0] | i195[0] | i196[0] | i197[0] | i198[0] + | i199[0] | i200[0] | i201[0] | i202[0] | i203[0] + | i204[0] | i205[0] | i206[0] }; endmodule diff --git a/test_regress/t/t_concat_sel.v b/test_regress/t/t_concat_sel.v index 295680318..7cca57d66 100644 --- a/test_regress/t/t_concat_sel.v +++ b/test_regress/t/t_concat_sel.v @@ -5,70 +5,70 @@ // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; + // Inputs + clk + ); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [3:0] a = crc[3:0]; - wire [3:0] b = crc[19:16]; + // Take CRC data and apply to testblock inputs + wire [3:0] a = crc[3:0]; + wire [3:0] b = crc[19:16]; - // TEST - wire [3:0] out1 = {a,b}[2 +: 4]; - wire [3:0] out2 = {a,b}[5 -: 4]; - wire [3:0] out3 = {a,b}[5 : 2]; - wire [0:0] out4 = {a,b}[2]; + // TEST + wire [3:0] out1 = {a,b}[2 +: 4]; + wire [3:0] out2 = {a,b}[5 -: 4]; + wire [3:0] out3 = {a,b}[5 : 2]; + wire [0:0] out4 = {a,b}[2]; - // Aggregate outputs into a single result vector - wire [63:0] result = {51'h0, out4, out3, out2, out1}; + // Aggregate outputs into a single result vector + wire [63:0] result = {51'h0, out4, out3, out2, out1}; - initial begin - if ({16'h1234}[0] != 1'b0) $stop; - if ({16'h1234}[2] != 1'b1) $stop; - if ({16'h1234}[11:4] != 8'h23) $stop; - if ({16'h1234}[4+:8] != 8'h23) $stop; - if ({16'h1234}[11-:8] != 8'h23) $stop; - if ({8'h12, 8'h34}[0] != 1'b0) $stop; - if ({8'h12, 8'h34}[2] != 1'b1) $stop; - if ({8'h12, 8'h34}[11:4] != 8'h23) $stop; - if ({8'h12, 8'h34}[4+:8] != 8'h23) $stop; - if ({8'h12, 8'h34}[11-:8] != 8'h23) $stop; + initial begin + if ({16'h1234}[0] != 1'b0) $stop; + if ({16'h1234}[2] != 1'b1) $stop; + if ({16'h1234}[11:4] != 8'h23) $stop; + if ({16'h1234}[4+:8] != 8'h23) $stop; + if ({16'h1234}[11-:8] != 8'h23) $stop; + if ({8'h12, 8'h34}[0] != 1'b0) $stop; + if ({8'h12, 8'h34}[2] != 1'b1) $stop; + if ({8'h12, 8'h34}[11:4] != 8'h23) $stop; + if ({8'h12, 8'h34}[4+:8] != 8'h23) $stop; + if ({8'h12, 8'h34}[11-:8] != 8'h23) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h4afe43fb79d7b71e + if (sum !== `EXPECTED_SUM) $stop; $write("*-* All Finished *-*\n"); $finish; - end - - // Test loop - always @ (posedge clk) begin -`ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); -`endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc==0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc<10) begin - sum <= '0; - end - else if (cyc<90) begin - end - else if (cyc==99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h4afe43fb79d7b71e - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + end + end endmodule diff --git a/test_regress/t/t_concat_string.v b/test_regress/t/t_concat_string.v index a8c36346e..b8666f582 100644 --- a/test_regress/t/t_concat_string.v +++ b/test_regress/t/t_concat_string.v @@ -7,25 +7,27 @@ typedef enum {efgh} en; module t; - initial begin - en e; - string s; + initial begin + en e; + string s; - s = {"a", "b"}; - if (s != "ab") $stop; + s = {"a", "b"}; + if (s != "ab") $stop; - e = efgh; - s = {"abcd", e.name(), "ijkl"}; - if (s != "abcdefghijkl") $stop; + e = efgh; + s = {"abcd", e.name(), "ijkl"}; + if (s != "abcdefghijkl") $stop; - // hang V3Width if complexity grows exponential (2**52 should suffice) - s = {"a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", - "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z", - "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", - "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z"}; - if (s != "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz") $stop; + // hang V3Width if complexity grows exponential (2**52 should suffice) + // verilog_format: off + s = {"a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", + "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z", + "a", "b", "c", "d", "e", "f", "g", "h", "i", "j", "k", "l", "m", + "n", "o", "p", "q", "r", "s", "t", "u", "v", "w", "x", "y", "z"}; + // verilog_format: on + if (s != "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_concat_unpack.v b/test_regress/t/t_concat_unpack.v index 41ff5f43c..54d10648b 100644 --- a/test_regress/t/t_concat_unpack.v +++ b/test_regress/t/t_concat_unpack.v @@ -4,33 +4,31 @@ // SPDX-FileCopyrightText: 2022 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( + input clk +); - wire [31:0] arr [0:7]; - assign arr[0:7] = { - {16'hffff, 16'h0000}, - {16'h0000, 16'h0000}, - {16'h0a0a, 16'h0000}, - {16'ha0a0, 16'h0000}, - {16'hffff, 16'h0000}, - {16'h0000, 16'h0000}, - {16'h0a0a, 16'h0000}, - {16'ha0a0, 16'h0000} - }; + wire [31:0] arr[0:7]; + assign arr[0:7] = { + {16'hffff, 16'h0000}, + {16'h0000, 16'h0000}, + {16'h0a0a, 16'h0000}, + {16'ha0a0, 16'h0000}, + {16'hffff, 16'h0000}, + {16'h0000, 16'h0000}, + {16'h0a0a, 16'h0000}, + {16'ha0a0, 16'h0000} + }; - int cyc = 0; + int cyc = 0; - always @(posedge clk) begin - cyc <= cyc + 1; - if (cyc == 9) begin - if (arr[0] !== 32'hffff0000) $stop; - if (arr[7] !== 32'ha0a00000) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 9) begin + if (arr[0] !== 32'hffff0000) $stop; + if (arr[7] !== 32'ha0a00000) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_const.v b/test_regress/t/t_const.v index e142ce051..4ae937699 100644 --- a/test_regress/t/t_const.v +++ b/test_regress/t/t_const.v @@ -6,17 +6,17 @@ module t; - initial begin - // verilator lint_off WIDTH - if (32'hxxxxxxxx !== 'hx) $stop; - if (32'hzzzzzzzz !== 'hz) $stop; - if (32'h???????? !== 'h?) $stop; - if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; - if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; - if (68'h?_????????_???????? !== 'd?) $stop; - // verilator lint_on WIDTH - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + // verilator lint_off WIDTH + if (32'hxxxxxxxx !== 'hx) $stop; + if (32'hzzzzzzzz !== 'hz) $stop; + if (32'h???????? !== 'h?) $stop; + if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + if (68'h?_????????_???????? !== 'd?) $stop; + // verilator lint_on WIDTH + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_const_bad.out b/test_regress/t/t_const_bad.out index 5ef1e1fd6..db77ac73a 100644 --- a/test_regress/t/t_const_bad.out +++ b/test_regress/t/t_const_bad.out @@ -1,15 +1,15 @@ -%Warning-WIDTHXZEXPAND: t/t_const_bad.v:13:39: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +%Warning-WIDTHXZEXPAND: t/t_const_bad.v:13:37: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx : ... note: In instance 't' - 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; - | ^~~ + 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + | ^~~ ... For warning description see https://verilator.org/warn/WIDTHXZEXPAND?v=latest ... Use "/* verilator lint_off WIDTHXZEXPAND */" and lint_on around source to disable this message. -%Warning-WIDTHXZEXPAND: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz +%Warning-WIDTHXZEXPAND: t/t_const_bad.v:14:37: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... note: In instance 't' - 14 | if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; - | ^~~ -%Warning-WIDTHXZEXPAND: t/t_const_bad.v:15:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz + 14 | if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + | ^~~ +%Warning-WIDTHXZEXPAND: t/t_const_bad.v:15:37: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... note: In instance 't' - 15 | if (68'h?_????????_???????? !== 'd?) $stop; - | ^~~ + 15 | if (68'h?_????????_???????? !== 'd?) $stop; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_bad.v b/test_regress/t/t_const_bad.v index 6d3edd361..ba87ae32f 100644 --- a/test_regress/t/t_const_bad.v +++ b/test_regress/t/t_const_bad.v @@ -6,15 +6,15 @@ module t; - initial begin - if (32'hxxxxxxxx !== 'hx) $stop; - if (32'hzzzzzzzz !== 'hz) $stop; - if (32'h???????? !== 'h?) $stop; - if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; - if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; - if (68'h?_????????_???????? !== 'd?) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (32'hxxxxxxxx !== 'hx) $stop; + if (32'hzzzzzzzz !== 'hz) $stop; + if (32'h???????? !== 'h?) $stop; + if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + if (68'h?_????????_???????? !== 'd?) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_const_bitoptree_bug3096.v b/test_regress/t/t_const_bitoptree_bug3096.v index 6d783a25e..51c125982 100644 --- a/test_regress/t/t_const_bitoptree_bug3096.v +++ b/test_regress/t/t_const_bitoptree_bug3096.v @@ -8,17 +8,17 @@ // From issue #3096 -module decoder( - input wire [31:0] instr_i, - // Making 'a' an output preserves it as a sub-expression and causes a missing clean - output wire a, - output wire illegal_instr_o - ); - /* verilator lint_off WIDTH */ - wire b = ! instr_i[12:5]; - wire c = ! instr_i[1:0]; - wire d = ! instr_i[15:13]; - /* verilator lint_on WIDTH */ - assign a = d ? b : 1'h1; - assign illegal_instr_o = c ? a : 1'h0; +module decoder ( + input wire [31:0] instr_i, + // Making 'a' an output preserves it as a sub-expression and causes a missing clean + output wire a, + output wire illegal_instr_o +); + /* verilator lint_off WIDTH */ + wire b = !instr_i[12:5]; + wire c = !instr_i[1:0]; + wire d = !instr_i[15:13]; + /* verilator lint_on WIDTH */ + assign a = d ? b : 1'h1; + assign illegal_instr_o = c ? a : 1'h0; endmodule diff --git a/test_regress/t/t_const_dec_mixed_bad.out b/test_regress/t/t_const_dec_mixed_bad.out index 8e07f25e2..5b452d6f8 100644 --- a/test_regress/t/t_const_dec_mixed_bad.out +++ b/test_regress/t/t_const_dec_mixed_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_const_dec_mixed_bad.v:9:30: Mixing X/Z/? with digits not legal in decimal constant: x_1 - 9 | parameter [200:0] MIXED = 32'dx_1; - | ^~~~~~~ +%Error: t/t_const_dec_mixed_bad.v:9:29: Mixing X/Z/? with digits not legal in decimal constant: x_1 + 9 | parameter [200:0] MIXED = 32'dx_1; + | ^~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. %Error: Exiting due to diff --git a/test_regress/t/t_const_dec_mixed_bad.v b/test_regress/t/t_const_dec_mixed_bad.v index 99ac432f4..2bd1fc8fa 100644 --- a/test_regress/t/t_const_dec_mixed_bad.v +++ b/test_regress/t/t_const_dec_mixed_bad.v @@ -6,6 +6,6 @@ module t; - parameter [200:0] MIXED = 32'dx_1; + parameter [200:0] MIXED = 32'dx_1; endmodule diff --git a/test_regress/t/t_const_hi.v b/test_regress/t/t_const_hi.v index 5843d2d18..14b5ab813 100644 --- a/test_regress/t/t_const_hi.v +++ b/test_regress/t/t_const_hi.v @@ -4,50 +4,47 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [1:0] reg_i; - reg [1049:0] pad0; - reg [1049:0] reg_o; - reg [1049:0] spad1; + integer cyc = 0; + reg [1:0] reg_i; + reg [1049:0] pad0; + reg [1049:0] reg_o; + reg [1049:0] spad1; - /*AUTOWIRE*/ + /*AUTOWIRE*/ - always_comb begin - if (reg_i[1] == 1'b1) - reg_o = {986'd0, 64'hffff0000ffff0000}; - else if (reg_i[0] == 1'b1) - reg_o = {64'hffff0000ffff0000, 986'd0}; - else - reg_o = 1050'd0; - end + always_comb begin + if (reg_i[1] == 1'b1) reg_o = {986'd0, 64'hffff0000ffff0000}; + else if (reg_i[0] == 1'b1) reg_o = {64'hffff0000ffff0000, 986'd0}; + else reg_o = 1050'd0; + end - // Test loop - always @ (posedge clk) begin - cyc <= cyc + 1; - if (cyc == 0) begin - reg_i <= 2'b00; - pad0 <= '1; - spad1 <= '1; - end - else if (cyc == 1) begin - reg_i <= 2'b01; - end - else if (cyc == 2) begin - if (reg_o != {64'hffff0000ffff0000, 986'd0}) $stop; - reg_i <= 2'b10; - end - else if (cyc == 99) begin - if (reg_o != {986'd0, 64'hffff0000ffff0000}) $stop; - if (pad0 != '1) $stop; - if (spad1 != '1) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + reg_i <= 2'b00; + pad0 <= '1; + spad1 <= '1; + end + else if (cyc == 1) begin + reg_i <= 2'b01; + end + else if (cyc == 2) begin + if (reg_o != {64'hffff0000ffff0000, 986'd0}) $stop; + reg_i <= 2'b10; + end + else if (cyc == 99) begin + if (reg_o != {986'd0, 64'hffff0000ffff0000}) $stop; + if (pad0 != '1) $stop; + if (spad1 != '1) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule diff --git a/test_regress/t/t_const_number_bad.out b/test_regress/t/t_const_number_bad.out index cfd7ea94e..795db19d0 100644 --- a/test_regress/t/t_const_number_bad.out +++ b/test_regress/t/t_const_number_bad.out @@ -1,26 +1,26 @@ -%Error: t/t_const_number_bad.v:9:29: Number is missing value digits: 32'd - 9 | parameter integer FOO2 = 32'd-6; - | ^~~~ +%Error: t/t_const_number_bad.v:9:28: Number is missing value digits: 32'd + 9 | parameter integer FOO2 = 32'd-6; + | ^~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_const_number_bad.v:10:29: Number is missing value digits: 32'd - 10 | parameter integer FOO3 = 32'd; - | ^~~~ -%Error: t/t_const_number_bad.v:11:29: Number is missing value digits: 32'h - 11 | parameter integer FOO4 = 32'h; - | ^~~~ -%Error: t/t_const_number_bad.v:13:29: Illegal character in binary constant: 2 - 13 | parameter integer FOO5 = 32'b2; - | ^~~~~ -%Error: t/t_const_number_bad.v:14:29: Illegal character in octal constant - 14 | parameter integer FOO6 = 32'o8; - | ^~~~~ -%Error: t/t_const_number_bad.v:17:33: Illegal character in binary constant: 4 - 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; - | ^~~~~~ -%Error: t/t_const_number_bad.v:17:33: Too many digits for 1 bit number: '1'b1?4' - 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; - | ^~~~~~ -%Error: t/t_const_number_bad.v:17:39: syntax error, unexpected INTEGER NUMBER, expecting ';' - 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; - | ^~~ +%Error: t/t_const_number_bad.v:10:28: Number is missing value digits: 32'd + 10 | parameter integer FOO3 = 32'd; + | ^~~~ +%Error: t/t_const_number_bad.v:11:28: Number is missing value digits: 32'h + 11 | parameter integer FOO4 = 32'h; + | ^~~~ +%Error: t/t_const_number_bad.v:13:28: Illegal character in binary constant: 2 + 13 | parameter integer FOO5 = 32'b2; + | ^~~~~ +%Error: t/t_const_number_bad.v:14:28: Illegal character in octal constant + 14 | parameter integer FOO6 = 32'o8; + | ^~~~~ +%Error: t/t_const_number_bad.v:17:32: Illegal character in binary constant: 4 + 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; + | ^~~~~~ +%Error: t/t_const_number_bad.v:17:32: Too many digits for 1 bit number: '1'b1?4' + 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; + | ^~~~~~ +%Error: t/t_const_number_bad.v:17:38: syntax error, unexpected INTEGER NUMBER, expecting ';' + 17 | parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_number_bad.v b/test_regress/t/t_const_number_bad.v index b10a58750..b0d41042f 100644 --- a/test_regress/t/t_const_number_bad.v +++ b/test_regress/t/t_const_number_bad.v @@ -6,14 +6,14 @@ module t; - parameter integer FOO2 = 32'd-6; // Minus doesn't go here - parameter integer FOO3 = 32'd; - parameter integer FOO4 = 32'h; + parameter integer FOO2 = 32'd-6; // Minus doesn't go here + parameter integer FOO3 = 32'd; + parameter integer FOO4 = 32'h; - parameter integer FOO5 = 32'b2; - parameter integer FOO6 = 32'o8; + parameter integer FOO5 = 32'b2; + parameter integer FOO6 = 32'o8; - // See bug2432, this is questionable, some simulators take this, others do not - parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; // bug2432 - intentionally no spaces near ? + // See bug2432, this is questionable, some simulators take this, others do not + parameter logic [3:0] FOO7 = 1'b1?4'hF:4'h1; // bug2432 - intentionally no spaces near ? endmodule diff --git a/test_regress/t/t_const_number_unsized.v b/test_regress/t/t_const_number_unsized.v index e3d32a420..4f351ecda 100644 --- a/test_regress/t/t_const_number_unsized.v +++ b/test_regress/t/t_const_number_unsized.v @@ -4,53 +4,56 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0h exp=%0h\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on module t; - int s; - logic [255:0] n; + int s; + logic [255:0] n; - initial begin - s = $bits('d123); - `checkd(s, 32); - s = $bits('h123); - `checkd(s, 32); - s = $bits('o123); - `checkd(s, 32); - s = $bits('b101); - `checkd(s, 32); + initial begin + s = $bits('d123); + `checkd(s, 32); + s = $bits('h123); + `checkd(s, 32); + s = $bits('o123); + `checkd(s, 32); + s = $bits('b101); + `checkd(s, 32); - // verilator lint_off WIDTHEXPAND + // verilator lint_off WIDTHEXPAND - // Used to warn "Too many digits for 32 bit number" - // ... As that number was unsized ('...) it is limited to 32 bits - // But other simulators don't warn, and language of (IEEE 1800-2023 5.7.1) - // has been updated to accepting this legal - n = 'd123456789123456789123456789; - s = $bits('d123456789123456789123456789); - `checkh(n, 256'h661efdf2e3b19f7c045f15); - `checkd(s, 87); + // Used to warn "Too many digits for 32 bit number" + // ... As that number was unsized ('...) it is limited to 32 bits + // But other simulators don't warn, and language of (IEEE 1800-2023 5.7.1) + // has been updated to accepting this legal + n = 'd123456789123456789123456789; + s = $bits('d123456789123456789123456789); + `checkh(n, 256'h661efdf2e3b19f7c045f15); + `checkd(s, 87); - n = 'h123456789123456789123456789; - s = $bits('h123456789123456789123456789); - `checkh(n, 256'h123456789123456789123456789); - `checkd(s, 108); + n = 'h123456789123456789123456789; + s = $bits('h123456789123456789123456789); + `checkh(n, 256'h123456789123456789123456789); + `checkd(s, 108); - //FIX octal digits in master test, if don't merge this - n = 'o123456777123456777123456777; - s = $bits('o123456777123456777123456777); - `checkh(n, 256'h53977fca72eff94e5dff); - `checkd(s, 81); + //FIX octal digits in master test, if don't merge this + n = 'o123456777123456777123456777; + s = $bits('o123456777123456777123456777); + `checkh(n, 256'h53977fca72eff94e5dff); + `checkd(s, 81); - n = 'b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010; - s = $bits('b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010); - `checkh(n, 256'haaaaaaaaaaaaaaaaaaaaaaa); - `checkd(s, 92); + n = 'b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010; + s = $bits('b10101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010 + ); + `checkh(n, 256'haaaaaaaaaaaaaaaaaaaaaaa); + `checkd(s, 92); - $write("*-* All Finished *-*\n"); - $finish; - end + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_const_number_v_bad.out b/test_regress/t/t_const_number_v_bad.out index b222a145f..cc3f8bd2c 100644 --- a/test_regress/t/t_const_number_v_bad.out +++ b/test_regress/t/t_const_number_v_bad.out @@ -1,21 +1,21 @@ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:11:25: Unbased unsized literals require IEEE 1800-2005 or later. - 11 | wire [127:0] FOO1 = '0; - | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:11:23: Unbased unsized literals require IEEE 1800-2005 or later. + 11 | wire [127:0] FOO1 = '0; + | ^~ ... For warning description see https://verilator.org/warn/NEWERSTD?v=latest ... Use "/* verilator lint_off NEWERSTD */" and lint_on around source to disable this message. -%Warning-NEWERSTD: t/t_const_number_v_bad.v:12:25: Unbased unsized literals require IEEE 1800-2005 or later. - 12 | wire [127:0] FOO2 = '1; - | ^~ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:13:25: Unbased unsized literals require IEEE 1800-2005 or later. - 13 | wire [127:0] FOO3 = 'x; - | ^~ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:14:25: Unbased unsized literals require IEEE 1800-2005 or later. - 14 | wire [127:0] FOO4 = 'X; - | ^~ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:15:25: Unbased unsized literals require IEEE 1800-2005 or later. - 15 | wire [127:0] FOO5 = 'z; - | ^~ -%Warning-NEWERSTD: t/t_const_number_v_bad.v:16:25: Unbased unsized literals require IEEE 1800-2005 or later. - 16 | wire [127:0] FOO6 = 'Z; - | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:12:23: Unbased unsized literals require IEEE 1800-2005 or later. + 12 | wire [127:0] FOO2 = '1; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:13:23: Unbased unsized literals require IEEE 1800-2005 or later. + 13 | wire [127:0] FOO3 = 'x; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:14:23: Unbased unsized literals require IEEE 1800-2005 or later. + 14 | wire [127:0] FOO4 = 'X; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:15:23: Unbased unsized literals require IEEE 1800-2005 or later. + 15 | wire [127:0] FOO5 = 'z; + | ^~ +%Warning-NEWERSTD: t/t_const_number_v_bad.v:16:23: Unbased unsized literals require IEEE 1800-2005 or later. + 16 | wire [127:0] FOO6 = 'Z; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_const_number_v_bad.v b/test_regress/t/t_const_number_v_bad.v index c9564cd70..f5ef1875a 100644 --- a/test_regress/t/t_const_number_v_bad.v +++ b/test_regress/t/t_const_number_v_bad.v @@ -6,13 +6,13 @@ module t; - // "unbased_unsized_literal" is SystemVerilog only - // Should fail with "NEWERSTD" - wire [127:0] FOO1 = '0; - wire [127:0] FOO2 = '1; - wire [127:0] FOO3 = 'x; - wire [127:0] FOO4 = 'X; - wire [127:0] FOO5 = 'z; - wire [127:0] FOO6 = 'Z; + // "unbased_unsized_literal" is SystemVerilog only + // Should fail with "NEWERSTD" + wire [127:0] FOO1 = '0; + wire [127:0] FOO2 = '1; + wire [127:0] FOO3 = 'x; + wire [127:0] FOO4 = 'X; + wire [127:0] FOO5 = 'z; + wire [127:0] FOO6 = 'Z; endmodule diff --git a/test_regress/t/t_const_op_red_scope.v b/test_regress/t/t_const_op_red_scope.v index 520bc2eb8..45991e723 100644 --- a/test_regress/t/t_const_op_red_scope.v +++ b/test_regress/t/t_const_op_red_scope.v @@ -4,114 +4,120 @@ // SPDX-FileCopyrightText: 2021 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t ( /*AUTOARG*/ + // Inputs + clk +); + input clk; - integer cyc = 0; - reg [63:0] crc; - reg [63:0] sum; + integer cyc = 0; + reg [63:0] crc; + reg [63:0] sum; - // Take CRC data and apply to testblock inputs - wire [7:0] in = crc[7:0]; + // Take CRC data and apply to testblock inputs + wire [7:0] in = crc[7:0]; - /*AUTOWIRE*/ + /*AUTOWIRE*/ - wire out0; - wire out1; - wire out2; - wire out3; - wire out4; - wire out5; - wire out6; - wire out7; + wire out0; + wire out1; + wire out2; + wire out3; + wire out4; + wire out5; + wire out6; + wire out7; - /*SelFlop AUTO_TEMPLATE(.n(@), + /*SelFlop AUTO_TEMPLATE(.n(@), .out(out@)); */ - SelFlop selflop0(/*AUTOINST*/ - // Outputs - .out (out0), // Templated - // Inputs - .clk (clk), - .in (in[7:0]), - .n (0)); // Templated - SelFlop selflop1(/*AUTOINST*/ - // Outputs - .out (out1), // Templated - // Inputs - .clk (clk), - .in (in[7:0]), - .n (1)); // Templated - SelFlop selflop2(/*AUTOINST*/ - // Outputs - .out (out2), // Templated - // Inputs - .clk (clk), - .in (in[7:0]), - .n (2)); // Templated - SelFlop selflop3(/*AUTOINST*/ - // Outputs - .out (out3), // Templated - // Inputs - .clk (clk), - .in (in[7:0]), - .n (3)); // Templated + SelFlop selflop0 ( /*AUTOINST*/ + // Outputs + .out(out0), // Templated + // Inputs + .clk(clk), + .in(in[7:0]), + .n(0) + ); // Templated + SelFlop selflop1 ( /*AUTOINST*/ + // Outputs + .out(out1), // Templated + // Inputs + .clk(clk), + .in(in[7:0]), + .n(1) + ); // Templated + SelFlop selflop2 ( /*AUTOINST*/ + // Outputs + .out(out2), // Templated + // Inputs + .clk(clk), + .in(in[7:0]), + .n(2) + ); // Templated + SelFlop selflop3 ( /*AUTOINST*/ + // Outputs + .out(out3), // Templated + // Inputs + .clk(clk), + .in(in[7:0]), + .n(3) + ); // Templated - // Aggregate outputs into a single result vector - wire outo = out0|out1|out2|out3; - wire outa = out0&out1&out2&out3; - wire outx = out0^out1^out2^out3; - wire [63:0] result = {61'h0, outo, outa, outx}; + // Aggregate outputs into a single result vector + wire outo = out0 | out1 | out2 | out3; + wire outa = out0 & out1 & out2 & out3; + wire outx = out0 ^ out1 ^ out2 ^ out3; + wire [63:0] result = {61'h0, outo, outa, outx}; - // Test loop - always @ (posedge clk) begin + // Test loop + always @(posedge clk) begin `ifdef TEST_VERBOSE - $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); + $write("[%0t] cyc==%0d crc=%x result=%x\n", $time, cyc, crc, result); `endif - cyc <= cyc + 1; - crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; - sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; - if (cyc == 0) begin - // Setup - crc <= 64'h5aef0c8d_d70a4497; - sum <= '0; - end - else if (cyc < 10) begin - sum <= '0; - end - else if (cyc < 90) begin - end - else if (cyc == 99) begin - $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); - if (crc !== 64'hc77bb9b3784ea091) $stop; - // What checksum will we end up with (above print should match) -`define EXPECTED_SUM 64'h118c5809c7856d78 - if (sum !== `EXPECTED_SUM) $stop; - $write("*-* All Finished *-*\n"); - $finish; - end - end + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]}; + sum <= result ^ {sum[62:0], sum[63] ^ sum[2] ^ sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) + `define EXPECTED_SUM 64'h118c5809c7856d78 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end endmodule -module SelFlop(/*AUTOARG*/ - // Outputs - out, - // Inputs - clk, in, n - ); +module SelFlop ( /*AUTOARG*/ + // Outputs + out, + // Inputs + clk, + in, + n +); - input clk; - input [7:0] in; - input [2:0] n; - output reg out; + input clk; + input [7:0] in; + input [2:0] n; + output reg out; - // verilator no_inline_module + // verilator no_inline_module - always @(posedge clk) begin - out <= in[n]; - end + always @(posedge clk) begin + out <= in[n]; + end endmodule diff --git a/test_regress/t/t_const_overflow_bad.out b/test_regress/t/t_const_overflow_bad.out index 1085a37de..db62260b2 100644 --- a/test_regress/t/t_const_overflow_bad.out +++ b/test_regress/t/t_const_overflow_bad.out @@ -1,17 +1,17 @@ -%Error: t/t_const_overflow_bad.v:9:34: Too many digits for 94 bit number: '94'd123456789012345678901234567890' - 9 | parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_const_overflow_bad.v:9:33: Too many digits for 94 bit number: '94'd123456789012345678901234567890' + 9 | parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance. -%Error: t/t_const_overflow_bad.v:11:31: Too many digits for 8 bit number: '8'habc' - 11 | parameter [200:0] SMALLH = 8'habc; - | ^~~~~~ -%Error: t/t_const_overflow_bad.v:12:31: Too many digits for 6 bit number: '6'o1234' - 12 | parameter [200:0] SMALLO = 6'o1234; - | ^~~~~~~ -%Error: t/t_const_overflow_bad.v:13:31: Too many digits for 3 bit number: '3'b1111' - 13 | parameter [200:0] SMALLB = 3'b1111; - | ^~~~~~~ -%Error: t/t_const_overflow_bad.v:19:35: Too many digits for 129 bit number: '129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d' - 19 | parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; - | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_const_overflow_bad.v:11:30: Too many digits for 8 bit number: '8'habc' + 11 | parameter [200:0] SMALLH = 8'habc; + | ^~~~~~ +%Error: t/t_const_overflow_bad.v:12:30: Too many digits for 6 bit number: '6'o1234' + 12 | parameter [200:0] SMALLO = 6'o1234; + | ^~~~~~~ +%Error: t/t_const_overflow_bad.v:13:30: Too many digits for 3 bit number: '3'b1111' + 13 | parameter [200:0] SMALLB = 3'b1111; + | ^~~~~~~ +%Error: t/t_const_overflow_bad.v:19:34: Too many digits for 129 bit number: '129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d' + 19 | parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_overflow_bad.v b/test_regress/t/t_const_overflow_bad.v index fd6301033..61b88ec86 100644 --- a/test_regress/t/t_const_overflow_bad.v +++ b/test_regress/t/t_const_overflow_bad.v @@ -6,16 +6,16 @@ module t; - parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; // One to many digits + parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; // One to many digits - parameter [200:0] SMALLH = 8'habc; // One to many digits - parameter [200:0] SMALLO = 6'o1234; // One to many digits - parameter [200:0] SMALLB = 3'b1111; // One to many digits + parameter [200:0] SMALLH = 8'habc; // One to many digits + parameter [200:0] SMALLO = 6'o1234; // One to many digits + parameter [200:0] SMALLB = 3'b1111; // One to many digits - // We'll allow this though; no reason to be cruel - parameter [200:0] OKH = 8'h000000001; + // We'll allow this though; no reason to be cruel + parameter [200:0] OKH = 8'h000000001; - // bug1380 - parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; + // bug1380 + parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; endmodule diff --git a/test_regress/t/t_const_sel_sel_extend.v b/test_regress/t/t_const_sel_sel_extend.v index 40304abc8..21a2ea115 100644 --- a/test_regress/t/t_const_sel_sel_extend.v +++ b/test_regress/t/t_const_sel_sel_extend.v @@ -4,19 +4,19 @@ // SPDX-FileCopyrightText: 2022 Geza Lore // SPDX-License-Identifier: CC0-1.0 -module t( - output wire res +module t ( + output wire res ); - function automatic logic foo(logic bar); - foo = '0; - endfunction + function automatic logic foo(logic bar); + foo = '0; + endfunction - logic a, b; - logic [0:0][1:0] array; + logic a, b; + logic [0:0][1:0] array; - assign b = 0; - assign a = foo(b); - assign res = array[a][a]; + assign b = 0; + assign a = foo(b); + assign res = array[a][a]; endmodule diff --git a/test_regress/t/t_const_slicesel.v b/test_regress/t/t_const_slicesel.v index d77eb2696..8bcc4424b 100644 --- a/test_regress/t/t_const_slicesel.v +++ b/test_regress/t/t_const_slicesel.v @@ -6,15 +6,15 @@ module t; -localparam int unsigned A2 [1:0] = '{5,6}; -localparam int unsigned A3 [2:0] = '{4,5,6}; + localparam int unsigned A2[1:0] = '{5, 6}; + localparam int unsigned A3[2:0] = '{4, 5, 6}; -// Matching sizes with slicesel are okay. -localparam int unsigned B22 [1:0] = A2[1:0]; -localparam int unsigned B33 [2:0] = A3[2:0]; + // Matching sizes with slicesel are okay. + localparam int unsigned B22[1:0] = A2[1:0]; + localparam int unsigned B33[2:0] = A3[2:0]; -// See issue #3186 -localparam int unsigned B32_B [1:0] = A3[1:0]; -localparam int unsigned B32_T [1:0] = A3[2:1]; + // See issue #3186 + localparam int unsigned B32_B[1:0] = A3[1:0]; + localparam int unsigned B32_T[1:0] = A3[2:1]; endmodule diff --git a/test_regress/t/t_const_string_func.v b/test_regress/t/t_const_string_func.v index 275f37078..732b7f372 100644 --- a/test_regress/t/t_const_string_func.v +++ b/test_regress/t/t_const_string_func.v @@ -4,20 +4,19 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; - function automatic string foo_func(); - foo_func = "FOO"; - foo_func = $sformatf("%sBAR", foo_func); - for (int i = 0; i < 4; i++) - foo_func = $sformatf("%s%0d", foo_func, i); - endfunction + function automatic string foo_func(); + foo_func = "FOO"; + foo_func = $sformatf("%sBAR", foo_func); + for (int i = 0; i < 4; i++) foo_func = $sformatf("%s%0d", foo_func, i); + endfunction - localparam string the_foo = foo_func(); + localparam string the_foo = foo_func(); - initial begin - if (the_foo != "FOOBAR0123") $stop; - $write("*-* All Finished *-*\n"); - $finish; - end + initial begin + if (the_foo != "FOOBAR0123") $stop; + $write("*-* All Finished *-*\n"); + $finish; + end endmodule diff --git a/test_regress/t/t_constraint_cls_arr_member.v b/test_regress/t/t_constraint_cls_arr_member.v index 87fac6d50..44bf40ee2 100644 --- a/test_regress/t/t_constraint_cls_arr_member.v +++ b/test_regress/t/t_constraint_cls_arr_member.v @@ -24,7 +24,7 @@ class container_a; rand item_t items[4]; constraint val_c { foreach (items[i]) { - items[i].value inside {[10:200]}; + items[i].value inside {[10 : 200]}; } } function new(); @@ -37,9 +37,7 @@ class container_b; rand item_t items[4]; constraint order_c { foreach (items[i]) { - if (i != 0) { - items[i].value > items[i-1].value; - } + if (i != 0) {items[i].value > items[i-1].value;} } } function new(); @@ -81,7 +79,7 @@ module t; for (int i = 1; i < 4; i++) begin if (cb.items[i].value <= cb.items[i-1].value) begin $write("%%Error: %s:%0d: ordering violated: items[%0d]=%0d <= items[%0d]=%0d\n", - `__FILE__, `__LINE__, i, cb.items[i].value, i-1, cb.items[i-1].value); + `__FILE__, `__LINE__, i, cb.items[i].value, i - 1, cb.items[i-1].value); `stop; end end @@ -92,7 +90,7 @@ module t; for (int i = 1; i < 4; i++) begin if (cc.items[i].value <= cc.items[i-1].value) begin $write("%%Error: %s:%0d: ordering violated: items[%0d]=%0d <= items[%0d]=%0d\n", - `__FILE__, `__LINE__, i, cc.items[i].value, i-1, cc.items[i-1].value); + `__FILE__, `__LINE__, i, cc.items[i].value, i - 1, cc.items[i-1].value); `stop; end end diff --git a/test_regress/t/t_cover_toggle_min.v b/test_regress/t/t_cover_toggle_min.v index be1abc641..c41c82dc4 100644 --- a/test_regress/t/t_cover_toggle_min.v +++ b/test_regress/t/t_cover_toggle_min.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2024 Antmicro // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t(); +module t; logic[1:0] a; logic[1:0] b; logic[1:0] c; diff --git a/test_regress/t/t_cover_trace_always.v b/test_regress/t/t_cover_trace_always.v index 89fe43625..74d4eaf13 100644 --- a/test_regress/t/t_cover_trace_always.v +++ b/test_regress/t/t_cover_trace_always.v @@ -14,7 +14,7 @@ module imply(input logic p, input logic q, output logic r); end endmodule -module t(); +module t; logic p; logic q; logic r; diff --git a/test_regress/t/t_covergroup_func_override_bad.v b/test_regress/t/t_covergroup_func_override_bad.v index ce1507536..2f758be96 100644 --- a/test_regress/t/t_covergroup_func_override_bad.v +++ b/test_regress/t/t_covergroup_func_override_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ -module t(); +module t; covergroup cg; function sample(); diff --git a/test_regress/t/t_covergroup_new_override_bad.v b/test_regress/t/t_covergroup_new_override_bad.v index 8a31bc11e..a38753936 100644 --- a/test_regress/t/t_covergroup_new_override_bad.v +++ b/test_regress/t/t_covergroup_new_override_bad.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 /* verilator lint_off COVERIGN */ -module t(); +module t; covergroup cg; function new(); diff --git a/test_regress/t/t_cuse_forward.v b/test_regress/t/t_cuse_forward.v index 98f1f4995..a94b8b584 100644 --- a/test_regress/t/t_cuse_forward.v +++ b/test_regress/t/t_cuse_forward.v @@ -7,17 +7,17 @@ class Baz; endclass -class Bar#(type T) extends T; +class Bar #( + type T +) extends T; endclass class Foo; - typedef struct { - int field; - } Zee; + typedef struct {int field;} Zee; task t1(); // Refer to Baz CLASSREFDTYPE node in implementation (via CLASSEXTENDS) - Bar#(Baz) b = new; + Bar #(Baz) b = new; endtask // Refer to the very same Baz CLASSREFDTYPE node again, this time within interface task t2(Bar#(Baz)::T b); @@ -29,7 +29,7 @@ class Moo; Foo::Zee z; endclass -module t(); +module t; initial begin // Use Moo in top module to add Moo to root, causing inclusion of Foo header into // root header. diff --git a/test_regress/t/t_dpi_binary.v b/test_regress/t/t_dpi_binary.v index 5f97ed49e..5349afbea 100644 --- a/test_regress/t/t_dpi_binary.v +++ b/test_regress/t/t_dpi_binary.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; initial begin // All Finished is in dpic_final diff --git a/test_regress/t/t_dpi_context.v b/test_regress/t/t_dpi_context.v index a23fa6abb..1b61b4b1e 100644 --- a/test_regress/t/t_dpi_context.v +++ b/test_regress/t/t_dpi_context.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; sub a (.inst(1)); sub b (.inst(2)); diff --git a/test_regress/t/t_dpi_display.v b/test_regress/t/t_dpi_display.v index 31bf4ad60..61caa63f7 100644 --- a/test_regress/t/t_dpi_display.v +++ b/test_regress/t/t_dpi_display.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; `ifndef VERILATOR `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." diff --git a/test_regress/t/t_dpi_display_bad.v b/test_regress/t/t_dpi_display_bad.v index 536da6df3..8e97f97f7 100644 --- a/test_regress/t/t_dpi_display_bad.v +++ b/test_regress/t/t_dpi_display_bad.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; `ifndef VERILATOR `error "Only Verilator supports PLI-ish DPI calls and sformat conversion." diff --git a/test_regress/t/t_dpi_dup_bad.v b/test_regress/t/t_dpi_dup_bad.v index 493613856..358f00094 100644 --- a/test_regress/t/t_dpi_dup_bad.v +++ b/test_regress/t/t_dpi_dup_bad.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; // Same name w/ different args import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); diff --git a/test_regress/t/t_dpi_import_mix_bad.v b/test_regress/t/t_dpi_import_mix_bad.v index bb6fa043f..f00216a6e 100644 --- a/test_regress/t/t_dpi_import_mix_bad.v +++ b/test_regress/t/t_dpi_import_mix_bad.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; import "DPI-C" function int foo (int i); export "DPI-C" function foo; // Bad mix diff --git a/test_regress/t/t_dpi_name_bad.v b/test_regress/t/t_dpi_name_bad.v index 32cd549d2..a1b4838d5 100644 --- a/test_regress/t/t_dpi_name_bad.v +++ b/test_regress/t/t_dpi_name_bad.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; import "DPI-C" function int \badly.named (int i); diff --git a/test_regress/t/t_dpi_string.v b/test_regress/t/t_dpi_string.v index 6c9c6dddc..eb723c6b1 100644 --- a/test_regress/t/t_dpi_string.v +++ b/test_regress/t/t_dpi_string.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; import "DPI-C" function int dpii_string(input string DSM_NAME); diff --git a/test_regress/t/t_dpi_sys.v b/test_regress/t/t_dpi_sys.v index 1b0ab5082..232b94e6c 100644 --- a/test_regress/t/t_dpi_sys.v +++ b/test_regress/t/t_dpi_sys.v @@ -10,7 +10,7 @@ import "DPI-C" dpii_sys_task = function void \$dpii_sys (int i); import "DPI-C" dpii_sys_func = function int \$dpii_func (int i); -module t (); +module t; `ifndef verilator `error "Only Verilator supports PLI-ish DPI calls." diff --git a/test_regress/t/t_enum_bad_value.v b/test_regress/t/t_enum_bad_value.v index a9d71a590..b6b40906c 100644 --- a/test_regress/t/t_enum_bad_value.v +++ b/test_regress/t/t_enum_bad_value.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; enum bit signed [3:0] {OK1 = -1} ok1_t; // As is signed, loss of 1 bits is ok per IEEE enum bit signed [3:0] {OK2 = 3} ok2_t; diff --git a/test_regress/t/t_enum_const_methods.v b/test_regress/t/t_enum_const_methods.v index 0e4ed8596..d67975577 100644 --- a/test_regress/t/t_enum_const_methods.v +++ b/test_regress/t/t_enum_const_methods.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2022 Todd Strader // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; typedef enum [1:0] {E0, E1, E2} enm_t; diff --git a/test_regress/t/t_enum_name2.v b/test_regress/t/t_enum_name2.v index e99bd993f..de05825a5 100644 --- a/test_regress/t/t_enum_name2.v +++ b/test_regress/t/t_enum_name2.v @@ -13,7 +13,7 @@ package our_pkg; } T_Opcode; endpackage : our_pkg -module t (); +module t; our our (); endmodule diff --git a/test_regress/t/t_event_control_assign.v b/test_regress/t/t_event_control_assign.v index 1142d7eec..4d97ab5ba 100644 --- a/test_regress/t/t_event_control_assign.v +++ b/test_regress/t/t_event_control_assign.v @@ -8,7 +8,7 @@ int evt_recv_cnt; int new_evt_recv_cnt; -module t(); +module t; class Foo; event evt1; diff --git a/test_regress/t/t_event_control_pass.v b/test_regress/t/t_event_control_pass.v index 1426a817e..703c30fa8 100644 --- a/test_regress/t/t_event_control_pass.v +++ b/test_regress/t/t_event_control_pass.v @@ -24,7 +24,7 @@ endclass bit got_event; -module t(); +module t; initial begin Bar bar; diff --git a/test_regress/t/t_event_control_star.v b/test_regress/t/t_event_control_star.v index 9b2579c8f..c82ba653a 100644 --- a/test_regress/t/t_event_control_star.v +++ b/test_regress/t/t_event_control_star.v @@ -6,7 +6,7 @@ // Based on ivtest's nested_impl_event1.v by Martin Whitaker. -module t(); +module t; reg a; reg b; diff --git a/test_regress/t/t_final.v b/test_regress/t/t_final.v index 1a3156f4c..610061f1f 100644 --- a/test_regress/t/t_final.v +++ b/test_regress/t/t_final.v @@ -16,7 +16,7 @@ module submodule (); final ; // Empty test endmodule -module t (); +module t; generate for (genvar i = 0; i < 100; i = i + 1) begin : module_set submodule u_submodule(); diff --git a/test_regress/t/t_flag_fi.v b/test_regress/t/t_flag_fi.v index 28de5623e..8bcb12bc1 100644 --- a/test_regress/t/t_flag_fi.v +++ b/test_regress/t/t_flag_fi.v @@ -6,7 +6,7 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -module t (); +module t; initial begin $c("myfunction();"); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_flag_ldflags.v b/test_regress/t/t_flag_ldflags.v index ee945cb7a..b3b4a9907 100644 --- a/test_regress/t/t_flag_ldflags.v +++ b/test_regress/t/t_flag_ldflags.v @@ -10,7 +10,7 @@ import "DPI-C" pure function void dpii_a_library(); import "DPI-C" pure function void dpii_c_library(); import "DPI-C" pure function void dpii_so_library(); -module t (); +module t; initial begin dpii_a_library(); // From .a file dpii_c_library(); // From .cpp file diff --git a/test_regress/t/t_fork_block_item_declaration.v b/test_regress/t/t_fork_block_item_declaration.v index 79f996d63..c48501c1d 100644 --- a/test_regress/t/t_fork_block_item_declaration.v +++ b/test_regress/t/t_fork_block_item_declaration.v @@ -21,7 +21,7 @@ class Foo; endtask endclass -module t(); +module t; initial begin automatic int desired_counts[10] = '{10{1}}; counts = '{10{0}}; diff --git a/test_regress/t/t_fork_initial.v b/test_regress/t/t_fork_initial.v index 8bf3bee57..e274d7fed 100644 --- a/test_regress/t/t_fork_initial.v +++ b/test_regress/t/t_fork_initial.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; initial fork reg i; i = 1'b1; diff --git a/test_regress/t/t_fork_join_none_any_nested.v b/test_regress/t/t_fork_join_none_any_nested.v index 6a0f99875..2a7e7ac6c 100644 --- a/test_regress/t/t_fork_join_none_any_nested.v +++ b/test_regress/t/t_fork_join_none_any_nested.v @@ -25,7 +25,7 @@ class Foo; endtask endclass -module t(); +module t; reg a, b, c; initial begin diff --git a/test_regress/t/t_fork_join_none_class_cap.v b/test_regress/t/t_fork_join_none_class_cap.v index 49cd26392..aae0d6d6b 100644 --- a/test_regress/t/t_fork_join_none_class_cap.v +++ b/test_regress/t/t_fork_join_none_class_cap.v @@ -40,7 +40,7 @@ class Foo; endtask endclass -module t(); +module t; initial begin Foo foo; foo = new; diff --git a/test_regress/t/t_fork_join_none_virtual.v b/test_regress/t/t_fork_join_none_virtual.v index 6a0df7c6a..d67d5efe5 100644 --- a/test_regress/t/t_fork_join_none_virtual.v +++ b/test_regress/t/t_fork_join_none_virtual.v @@ -44,7 +44,7 @@ class Subfoo extends Foo; virtual task do_something();#5;endtask endclass -module t(); +module t; initial begin Subfoo subfoo; Foo foo; diff --git a/test_regress/t/t_fork_output_arg.v b/test_regress/t/t_fork_output_arg.v index 7c80d81d7..892b049f6 100644 --- a/test_regress/t/t_fork_output_arg.v +++ b/test_regress/t/t_fork_output_arg.v @@ -20,7 +20,7 @@ task automatic test; if (o != 100) $stop; endtask -module t(); +module t; initial begin test(); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_func_automatic_clear.v b/test_regress/t/t_func_automatic_clear.v index 512f8c529..1e1f41928 100644 --- a/test_regress/t/t_func_automatic_clear.v +++ b/test_regress/t/t_func_automatic_clear.v @@ -13,7 +13,7 @@ // Bug5747: Make sure that a variable with automatic storage is freshly // allocated when entering the function. -module t(); +module t; function automatic int ts_queue(); static int qs[$]; qs.push_back(0); diff --git a/test_regress/t/t_func_complex.v b/test_regress/t/t_func_complex.v index 0489cf568..561717d29 100644 --- a/test_regress/t/t_func_complex.v +++ b/test_regress/t/t_func_complex.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; typedef integer q_t[$]; function void queue_set(ref q_t q); diff --git a/test_regress/t/t_func_real_param.v b/test_regress/t/t_func_real_param.v index 21a95626b..60dcd09c6 100644 --- a/test_regress/t/t_func_real_param.v +++ b/test_regress/t/t_func_real_param.v @@ -6,7 +6,7 @@ // bug475 -module t(); +module t; function real get_real_one; input ignored; diff --git a/test_regress/t/t_func_refio_bad.v b/test_regress/t/t_func_refio_bad.v index a8eef79b2..b81984b26 100644 --- a/test_regress/t/t_func_refio_bad.v +++ b/test_regress/t/t_func_refio_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2020 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; typedef integer q_t[$]; function void queue_set(ref q_t q); diff --git a/test_regress/t/t_func_v.v b/test_regress/t/t_func_v.v index b7ab4cfb2..3b8f45236 100644 --- a/test_regress/t/t_func_v.v +++ b/test_regress/t/t_func_v.v @@ -6,7 +6,7 @@ // See bug569 -module t(); +module t; `ifdef T_FUNC_V_NOINL // verilator no_inline_module `endif diff --git a/test_regress/t/t_fuzz_triand_bad.v b/test_regress/t/t_fuzz_triand_bad.v index 648e830f1..6b63e35a5 100644 --- a/test_regress/t/t_fuzz_triand_bad.v +++ b/test_regress/t/t_fuzz_triand_bad.v @@ -4,6 +4,6 @@ // SPDX-FileCopyrightText: 2019 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; tri g=g.and.g; endmodule diff --git a/test_regress/t/t_gate_opt.v b/test_regress/t/t_gate_opt.v index aacdc2fd0..bdc237edc 100644 --- a/test_regress/t/t_gate_opt.v +++ b/test_regress/t/t_gate_opt.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 // bug5101 -module t (); +module t; logic [1:0] in0, in1, out; logic sel; diff --git a/test_regress/t/t_iface_self_ref_typedef.v b/test_regress/t/t_iface_self_ref_typedef.v index 298f795a1..9ff06e25d 100644 --- a/test_regress/t/t_iface_self_ref_typedef.v +++ b/test_regress/t/t_iface_self_ref_typedef.v @@ -7,12 +7,14 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Self-referential typedef: typedef iface#(T) this_type inside interface iface -interface my_iface #(type T = logic); - typedef my_iface #(T) self_t; +interface my_iface #( + type T = logic +); + typedef my_iface#(T) self_t; T data; endinterface -module t (); +module t; my_iface #(logic [7:0]) if0 (); initial begin diff --git a/test_regress/t/t_iface_typedef_struct_member.v b/test_regress/t/t_iface_typedef_struct_member.v index 9c7fcb3c0..6a4d75a7b 100644 --- a/test_regress/t/t_iface_typedef_struct_member.v +++ b/test_regress/t/t_iface_typedef_struct_member.v @@ -28,7 +28,9 @@ endpackage // The struct-in-union pattern triggers MemberDType fixup (line 1056). // The $bits() usage in sub_mod forces widthing during V3Param, moving // template RefDTypes into the type table before the template dies. -interface types_if #(parameter cfg_pkg::cfg_t cfg = 0)(); +interface types_if #( + parameter cfg_pkg::cfg_t cfg = 0 +) (); typedef logic [$clog2(cfg.NumUnits)-1:0] idx_t; typedef struct packed { @@ -39,33 +41,35 @@ interface types_if #(parameter cfg_pkg::cfg_t cfg = 0)(); typedef struct packed { logic [3:0] cmd; union packed { - addr_t addr; // struct-in-union: MemberDType trigger + addr_t addr; // struct-in-union: MemberDType trigger logic [31:0] raw; } payload; } req_t; endinterface -module sub_mod #(parameter cfg_pkg::cfg_t cfg = 0)(); - types_if #(cfg) types(); - typedef types.idx_t idx_t; - typedef types.req_t req_t; +module sub_mod #( + parameter cfg_pkg::cfg_t cfg = 0 +) (); + types_if #(cfg) types (); + typedef types.idx_t idx_t; + typedef types.req_t req_t; typedef types.addr_t addr_t; localparam int ReqWidth = $bits(req_t); - idx_t s_idx; - req_t s_req; + idx_t s_idx; + req_t s_req; addr_t s_addr; endmodule module t; localparam cfg_pkg::cfg_t CFG = '{NumUnits: 5, LineSize: 32}; - types_if #(CFG) types(); + types_if #(CFG) types (); typedef types.req_t req_t; req_t top_req; - sub_mod #(.cfg(CFG)) sub(); + sub_mod #(.cfg(CFG)) sub (); initial begin #1; diff --git a/test_regress/t/t_iface_typedef_wrong_clone.v b/test_regress/t/t_iface_typedef_wrong_clone.v index 2b79650b3..ce2fbd552 100644 --- a/test_regress/t/t_iface_typedef_wrong_clone.v +++ b/test_regress/t/t_iface_typedef_wrong_clone.v @@ -26,7 +26,9 @@ typedef struct packed { } sc_cfg_t; // Inner types interface - parameterized with struct typedef -interface sc_types_if #(parameter sc_cfg_t cfg = 0)(); +interface sc_types_if #( + parameter sc_cfg_t cfg = 0 +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; @@ -37,25 +39,29 @@ interface sc_types_if #(parameter sc_cfg_t cfg = 0)(); endinterface // Cache interface - wraps types interface and re-exports typedefs -interface sc_if #(parameter sc_cfg_t cfg = 0)(); - sc_types_if #(cfg) sc_io(); +interface sc_if #( + parameter sc_cfg_t cfg = 0 +) (); + sc_types_if #(cfg) sc_io (); typedef sc_io.addr_t addr_t; typedef sc_io.data_t data_t; - typedef sc_io.pkt_t pkt_t; + typedef sc_io.pkt_t pkt_t; addr_t rq_addr_i; endinterface // Wrapper module that uses the cache interface -module sc_wrap #(parameter sc_cfg_t cfg = 0)(); - sc_if #(cfg) cache(); +module sc_wrap #( + parameter sc_cfg_t cfg = 0 +) (); + sc_if #(cfg) cache (); typedef cache.addr_t addr_t; - typedef cache.pkt_t pkt_t; + typedef cache.pkt_t pkt_t; addr_t local_addr; - pkt_t local_pkt; + pkt_t local_pkt; assign cache.rq_addr_i = local_addr; endmodule @@ -64,10 +70,10 @@ endmodule // This creates two clones of sc_if (and sc_types_if) with different params module t; localparam sc_cfg_t cfg_narrow = '{AddrBits: 16, DataBits: 32}; - localparam sc_cfg_t cfg_wide = '{AddrBits: 32, DataBits: 64}; + localparam sc_cfg_t cfg_wide = '{AddrBits: 32, DataBits: 64}; - sc_wrap #(.cfg(cfg_narrow)) narrow(); - sc_wrap #(.cfg(cfg_wide)) wide(); + sc_wrap #(.cfg(cfg_narrow)) narrow (); + sc_wrap #(.cfg(cfg_wide)) wide (); initial begin #1; diff --git a/test_regress/t/t_initial_delay_assign.v b/test_regress/t/t_initial_delay_assign.v index a5eaec7e6..5219cfb1d 100644 --- a/test_regress/t/t_initial_delay_assign.v +++ b/test_regress/t/t_initial_delay_assign.v @@ -23,7 +23,7 @@ end \ -module t (); +module t; reg foo1; wire bar1; initial foo1 = '0; diff --git a/test_regress/t/t_inside_nonint.v b/test_regress/t/t_inside_nonint.v index b37e7675a..eb9429883 100644 --- a/test_regress/t/t_inside_nonint.v +++ b/test_regress/t/t_inside_nonint.v @@ -16,7 +16,7 @@ function bit check_double(real d); return 1'b0; endfunction -module t(); +module t; initial begin if (!check_string("WO")) $stop; diff --git a/test_regress/t/t_interface_ar2a.v b/test_regress/t/t_interface_ar2a.v index e2102953b..8e2142d3f 100644 --- a/test_regress/t/t_interface_ar2a.v +++ b/test_regress/t/t_interface_ar2a.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2020 Thierry Tambe // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; ahb_slave_intf AHB_S[1](); diff --git a/test_regress/t/t_interface_ar2b.v b/test_regress/t/t_interface_ar2b.v index 6e8766ff9..f715e7a47 100644 --- a/test_regress/t/t_interface_ar2b.v +++ b/test_regress/t/t_interface_ar2b.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2020 Thierry Tambe // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; sub sub [1] (); diff --git a/test_regress/t/t_interface_array_nocolon.v b/test_regress/t/t_interface_array_nocolon.v index 5ef95ea2b..cce609d06 100644 --- a/test_regress/t/t_interface_array_nocolon.v +++ b/test_regress/t/t_interface_array_nocolon.v @@ -16,7 +16,7 @@ module foo_subm ); endmodule -module t (); +module t; localparam N = 3; diff --git a/test_regress/t/t_interface_array_nocolon_bad.v b/test_regress/t/t_interface_array_nocolon_bad.v index 79c6c570d..b88110bfe 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.v +++ b/test_regress/t/t_interface_array_nocolon_bad.v @@ -16,7 +16,7 @@ module foo_subm ); endmodule -module t (); +module t; localparam N = 3; diff --git a/test_regress/t/t_interface_gen10.v b/test_regress/t/t_interface_gen10.v index 0e00daee2..d3f31b60b 100644 --- a/test_regress/t/t_interface_gen10.v +++ b/test_regress/t/t_interface_gen10.v @@ -19,7 +19,7 @@ module t1(intf mod_intf); end endmodule -module t(); +module t; generate begin : TestIf intf #(.PARAM(1)) my_intf [0:0] (); diff --git a/test_regress/t/t_interface_gen11.v b/test_regress/t/t_interface_gen11.v index 6ae54e8da..0fc617cde 100644 --- a/test_regress/t/t_interface_gen11.v +++ b/test_regress/t/t_interface_gen11.v @@ -27,7 +27,7 @@ module t2(intf mod_intfs [1:0]); endgenerate endmodule -module t(); +module t; intf #(.PARAM(1)) my_intf [1:0] (); diff --git a/test_regress/t/t_interface_gen5.v b/test_regress/t/t_interface_gen5.v index db58f6764..ca54aaf56 100644 --- a/test_regress/t/t_interface_gen5.v +++ b/test_regress/t/t_interface_gen5.v @@ -19,7 +19,7 @@ module t1(intf mod_intf); end endmodule -module t(); +module t; generate begin : TestIf intf #(.PARAM(1)) my_intf (); diff --git a/test_regress/t/t_interface_gen6.v b/test_regress/t/t_interface_gen6.v index b3a9e5620..18858412d 100644 --- a/test_regress/t/t_interface_gen6.v +++ b/test_regress/t/t_interface_gen6.v @@ -12,7 +12,7 @@ interface intf logic val; endinterface -module t(); +module t; generate if (1) begin diff --git a/test_regress/t/t_interface_gen7.v b/test_regress/t/t_interface_gen7.v index fb457286e..a9dfb6e8a 100644 --- a/test_regress/t/t_interface_gen7.v +++ b/test_regress/t/t_interface_gen7.v @@ -21,7 +21,7 @@ module t1(intf mod_intf); end endmodule -module t(); +module t; intf #(.PARAM(1)) my_intf [1:0] (); diff --git a/test_regress/t/t_interface_gen8.v b/test_regress/t/t_interface_gen8.v index f3f464fbd..1de7133b9 100644 --- a/test_regress/t/t_interface_gen8.v +++ b/test_regress/t/t_interface_gen8.v @@ -19,7 +19,7 @@ module t1(intf mod_intf); end endmodule -module t(); +module t; //intf #(.PARAM(1)) my_intf [1:0] (); intf #(.PARAM(1)) my_intf (); diff --git a/test_regress/t/t_interface_gen9.v b/test_regress/t/t_interface_gen9.v index 4f8d6bd59..a329dba5f 100644 --- a/test_regress/t/t_interface_gen9.v +++ b/test_regress/t/t_interface_gen9.v @@ -12,7 +12,7 @@ module t1(input logic foo); end endmodule -module t(); +module t; logic [1:0] my_foo; diff --git a/test_regress/t/t_interface_localparam.v b/test_regress/t/t_interface_localparam.v index 5957fc49c..a753aa752 100644 --- a/test_regress/t/t_interface_localparam.v +++ b/test_regress/t/t_interface_localparam.v @@ -46,7 +46,7 @@ module Core( end endmodule -module t(); +module t; SimpleIntf intf(); diff --git a/test_regress/t/t_interface_mp_func.v b/test_regress/t/t_interface_mp_func.v index be8089001..fe12a85c8 100644 --- a/test_regress/t/t_interface_mp_func.v +++ b/test_regress/t/t_interface_mp_func.v @@ -18,7 +18,7 @@ interface pads_if(); endtask endinterface -module t(); +module t; pads_if padsif[1:0](); pads_if padsif_arr[1:0](); initial begin diff --git a/test_regress/t/t_interface_nested_struct_param.v b/test_regress/t/t_interface_nested_struct_param.v index a4932167b..76491f549 100644 --- a/test_regress/t/t_interface_nested_struct_param.v +++ b/test_regress/t/t_interface_nested_struct_param.v @@ -33,24 +33,24 @@ endpackage // Nested types interface: derives struct typedef from computed localparams interface types_if #( - parameter cfg_pkg::cfg_t cfg = '0 -)(); + parameter cfg_pkg::cfg_t cfg = '0 +) (); // Computed localparams - these use division and $clog2 of cfg fields. // With default cfg='0, these produce X/undefined values. - localparam int NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int NUM_LINES = cfg.Capacity / cfg.LineSize; localparam int LINES_PER_WAY = NUM_LINES / cfg.Associativity; - localparam int BLOCK_BITS = $clog2(cfg.LineSize); - localparam int ROW_BITS = $clog2(LINES_PER_WAY); - localparam int TAG_BITS = cfg.AddrBits - ROW_BITS - BLOCK_BITS; + localparam int BLOCK_BITS = $clog2(cfg.LineSize); + localparam int ROW_BITS = $clog2(LINES_PER_WAY); + localparam int TAG_BITS = cfg.AddrBits - ROW_BITS - BLOCK_BITS; typedef logic [TAG_BITS-1:0] tag_t; typedef logic [ROW_BITS-1:0] row_t; typedef logic [BLOCK_BITS-1:0] block_t; typedef struct packed { - logic vld; - tag_t tag; - row_t row; + logic vld; + tag_t tag; + row_t row; block_t block; } entry_t; endinterface @@ -58,28 +58,28 @@ endinterface // Wrapper interface: instantiates types_if as a nested cell // (mirrors simple_cache_if which instantiates simple_cache_types_if) interface wrapper_if #( - parameter cfg_pkg::cfg_t cfg = '0 -)(); - types_if #(cfg) types(); + parameter cfg_pkg::cfg_t cfg = '0 +) (); + types_if #(cfg) types (); - typedef types.tag_t tag_t; + typedef types.tag_t tag_t; - logic req_vld; - tag_t req_tag; + logic req_vld; + tag_t req_tag; endinterface // Sub-module parameterized by entry width // (mirrors flop_nr / sram_generic_1r1w parameterized by $bits(sc_tag_t)) module entry_store #( - parameter int ENTRY_WIDTH = 8, - parameter int DEPTH = 4 -)( - input logic clk, - input logic wr_en, - input logic [ENTRY_WIDTH-1:0] wr_data, - output logic [ENTRY_WIDTH-1:0] rd_data + parameter int ENTRY_WIDTH = 8, + parameter int DEPTH = 4 +) ( + input logic clk, + input logic wr_en, + input logic [ENTRY_WIDTH-1:0] wr_data, + output logic [ENTRY_WIDTH-1:0] rd_data ); - logic [ENTRY_WIDTH-1:0] mem [DEPTH]; + logic [ENTRY_WIDTH-1:0] mem[DEPTH]; always_ff @(posedge clk) begin if (wr_en) mem[0] <= wr_data; end @@ -91,14 +91,14 @@ endmodule // (mirrors simple_cache which receives simple_cache_if, instantiates // simple_cache_types_if, and uses types.sc_tag_t) module inner_mod #( - parameter cfg_pkg::cfg_t cfg = '0 -)( - input logic clk, - wrapper_if io + parameter cfg_pkg::cfg_t cfg = '0 +) ( + input logic clk, + wrapper_if io ); // Local instantiation of types_if - same cfg, so gets same clone // as the one inside wrapper_if via "De-parameterize to prev" - types_if #(cfg) types(); + types_if #(cfg) types (); typedef types.entry_t entry_t; typedef types.tag_t tag_t; @@ -106,37 +106,37 @@ module inner_mod #( entry_t wr_entry; entry_t rd_entry; - assign wr_entry.vld = io.req_vld; - assign wr_entry.tag = io.req_tag; - assign wr_entry.row = '0; + assign wr_entry.vld = io.req_vld; + assign wr_entry.tag = io.req_tag; + assign wr_entry.row = '0; assign wr_entry.block = '0; // Use $bits of the struct typedef as a value parameter to sub-module. // This is the critical pattern: $bits(entry_t) must resolve using the // clone's struct (correct width), not the template's (zero/X width). entry_store #( - .ENTRY_WIDTH($bits(entry_t)), - .DEPTH(8) + .ENTRY_WIDTH($bits(entry_t)), + .DEPTH(8) ) u_store ( - .clk(clk), - .wr_en(io.req_vld), - .wr_data(wr_entry), - .rd_data(rd_entry) + .clk(clk), + .wr_en(io.req_vld), + .wr_data(wr_entry), + .rd_data(rd_entry) ); endmodule // Outer wrapper module: instantiates wrapper_if and inner_mod // (mirrors mblit_simple_cache_wrap) module outer_mod #( - parameter cfg_pkg::cfg_t cfg = '0 -)( - input logic clk + parameter cfg_pkg::cfg_t cfg = '0 +) ( + input logic clk ); - wrapper_if #(cfg) wif(); + wrapper_if #(cfg) wif (); inner_mod #(cfg) u_inner ( - .clk(clk), - .io(wif) + .clk(clk), + .io(wif) ); endmodule @@ -155,10 +155,10 @@ module t; // TAG_BITS = 64 - 3 - 6 = 55 // entry_t = 1 + 55 + 3 + 6 = 65 bits localparam cfg_pkg::cfg_t MY_CFG = '{ - AddrBits: 64, - Capacity: 1024, - LineSize: 64, - Associativity: 2 + AddrBits: 64, + Capacity: 1024, + LineSize: 64, + Associativity: 2 }; outer_mod #(.cfg(MY_CFG)) u_outer (.clk(clk)); @@ -172,8 +172,7 @@ module t; if (cyc > 5) begin // Verify the struct round-trips correctly if (u_outer.u_inner.rd_entry.vld !== 1'b1 && cyc > 10) begin - $display("FAIL cyc=%0d: rd_entry.vld=%b expected 1", - cyc, u_outer.u_inner.rd_entry.vld); + $display("FAIL cyc=%0d: rd_entry.vld=%b expected 1", cyc, u_outer.u_inner.rd_entry.vld); $stop; end end diff --git a/test_regress/t/t_interface_param_another_bad.v b/test_regress/t/t_interface_param_another_bad.v index 25e66288e..fb3b9eb5a 100644 --- a/test_regress/t/t_interface_param_another_bad.v +++ b/test_regress/t/t_interface_param_another_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2017 Johan Bjork // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; simple_bus sb_intf (); simple_bus #(.PARAMETER(sb_intf.dummy)) simple (); initial begin diff --git a/test_regress/t/t_jumps_uninit_destructor_call.v b/test_regress/t/t_jumps_uninit_destructor_call.v index ddcdce134..717f660ff 100644 --- a/test_regress/t/t_jumps_uninit_destructor_call.v +++ b/test_regress/t/t_jumps_uninit_destructor_call.v @@ -26,14 +26,14 @@ class Foo; // without having it initialized first. endtask task automatic return_before_select(bit b, int idx); - if (b) return; // goto + if (b) return; // goto // This will create two temporary strings used to select from `arrb` and assign to it. arrb[arra[idx]] = #10 "yah!"; // jump here endtask endclass -module t(); +module t; initial begin Foo foo; foo = new; diff --git a/test_regress/t/t_lint_const_func_dpi_bad.v b/test_regress/t/t_lint_const_func_dpi_bad.v index 6647afd4b..538f63ad4 100644 --- a/test_regress/t/t_lint_const_func_dpi_bad.v +++ b/test_regress/t/t_lint_const_func_dpi_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2021 Donald Owen // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; import "DPI-C" function int dpiFunc(); localparam PARAM = dpiFunc(); endmodule diff --git a/test_regress/t/t_lint_const_func_gen_bad.v b/test_regress/t/t_lint_const_func_gen_bad.v index 95dd6abe0..12013395b 100644 --- a/test_regress/t/t_lint_const_func_gen_bad.v +++ b/test_regress/t/t_lint_const_func_gen_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2021 Donald Owen // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; if (1) begin: GenConstFunc // IEEE 1800-2023 13.4.3, constant functions shall not be declared inside a //generate block diff --git a/test_regress/t/t_lint_infinite_bad.v b/test_regress/t/t_lint_infinite_bad.v index 8e11c11f4..0b74bcef1 100644 --- a/test_regress/t/t_lint_infinite_bad.v +++ b/test_regress/t/t_lint_infinite_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2017 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; initial begin forever begin end diff --git a/test_regress/t/t_lint_once_bad.v b/test_regress/t/t_lint_once_bad.v index a148e5510..22ba2bd3f 100644 --- a/test_regress/t/t_lint_once_bad.v +++ b/test_regress/t/t_lint_once_bad.v @@ -7,7 +7,7 @@ // Check that we report warnings only once on parameterized modules // Also check that we don't suppress warnings on the same line -module t (); +module t; sub #(.A(1)) sub1(); sub #(.A(2)) sub2(); sub #(.A(3)) sub3(); diff --git a/test_regress/t/t_lint_only.v b/test_regress/t/t_lint_only.v index e0ab4d0df..1921847c3 100644 --- a/test_regress/t/t_lint_only.v +++ b/test_regress/t/t_lint_only.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2006 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; initial begin $stop; end diff --git a/test_regress/t/t_lint_repeat_bad.v b/test_regress/t/t_lint_repeat_bad.v index 747c3b6b0..5f9f79e86 100644 --- a/test_regress/t/t_lint_repeat_bad.v +++ b/test_regress/t/t_lint_repeat_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2012 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; sub #(.Z(0)) sub1 (); sub #(.Z(1)) sub2 (); diff --git a/test_regress/t/t_lint_restore_bad.v b/test_regress/t/t_lint_restore_bad.v index 8566a9650..dadf0e143 100644 --- a/test_regress/t/t_lint_restore_bad.v +++ b/test_regress/t/t_lint_restore_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; reg [3:0] four; reg [4:0] five; diff --git a/test_regress/t/t_lint_restore_prag_bad.v b/test_regress/t/t_lint_restore_prag_bad.v index 71a05c912..c66468779 100644 --- a/test_regress/t/t_lint_restore_prag_bad.v +++ b/test_regress/t/t_lint_restore_prag_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2007 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; // No matching save // verilator lint_restore diff --git a/test_regress/t/t_lint_subout_bad.v b/test_regress/t/t_lint_subout_bad.v index 52f2da80a..df2d7ec7c 100644 --- a/test_regress/t/t_lint_subout_bad.v +++ b/test_regress/t/t_lint_subout_bad.v @@ -6,7 +6,7 @@ // verilator lint_off UNDRIVEN -module t(); +module t; wire sig; sub sub0(.out(33'b0)); sub sub1(.out({32'b0, sig})); diff --git a/test_regress/t/t_lint_width.v b/test_regress/t/t_lint_width.v index ff2c55d58..707f06911 100644 --- a/test_regress/t/t_lint_width.v +++ b/test_regress/t/t_lint_width.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2010 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; // This isn't a width violation, as +/- 1'b1 is a common idiom // that's fairly harmless diff --git a/test_regress/t/t_lint_width_bad.v b/test_regress/t/t_lint_width_bad.v index 9c004f754..b2c4db6c6 100644 --- a/test_regress/t/t_lint_width_bad.v +++ b/test_regress/t/t_lint_width_bad.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2009 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; // See also t_math_width diff --git a/test_regress/t/t_lparam_assign_iface_const.v b/test_regress/t/t_lparam_assign_iface_const.v index 9237520e4..140051d89 100644 --- a/test_regress/t/t_lparam_assign_iface_const.v +++ b/test_regress/t/t_lparam_assign_iface_const.v @@ -5,32 +5,31 @@ // SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 typedef struct { - int BAR_INT; - bit BAR_BIT; - byte BAR_ARRAY [0:3]; + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY[0:3]; } foo_t; -interface intf - #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}) - (); +interface intf #( + parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}} +) (); endinterface -module sub (intf the_intf_port [4]); - localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; +module sub ( + intf the_intf_port[4] +); + localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; initial begin #1; - if (intf_foo_bar_int != 4) $stop; + if (intf_foo_bar_int != 4) $stop; end endmodule -module t (); - intf the_intf [4] (); +module t; + intf the_intf[4] (); - sub - the_sub ( - .the_intf_port (the_intf) - ); + sub the_sub (.the_intf_port(the_intf)); initial begin #2; diff --git a/test_regress/t/t_lparam_assign_iface_typedef_bad.v b/test_regress/t/t_lparam_assign_iface_typedef_bad.v index 2a030945b..806f6f2a2 100644 --- a/test_regress/t/t_lparam_assign_iface_typedef_bad.v +++ b/test_regress/t/t_lparam_assign_iface_typedef_bad.v @@ -8,20 +8,20 @@ // Correct syntax is: localparam type p0_rq_t = if0.rq_t; interface x_if #( - parameter int p_awidth = 4, - parameter int p_dwidth = 7 -)(); + parameter int p_awidth = 4, + parameter int p_dwidth = 7 +) (); typedef struct packed { logic [p_awidth-1:0] addr; logic [p_dwidth-1:0] data; } rq_t; endinterface -module t(); +module t; x_if #( - .p_awidth(16), - .p_dwidth(8) - ) if0(); + .p_awidth(16), + .p_dwidth(8) + ) if0 (); localparam p0_rq_t = if0.rq_t; // Bad: missing 'type' keyword diff --git a/test_regress/t/t_lparam_dep_iface0.v b/test_regress/t/t_lparam_dep_iface0.v index 54abb8d2e..842ec3e84 100644 --- a/test_regress/t/t_lparam_dep_iface0.v +++ b/test_regress/t/t_lparam_dep_iface0.v @@ -12,18 +12,20 @@ // verilog_format: on typedef struct { - int BAR_INT; - bit BAR_BIT; - byte BAR_ARRAY [0:3]; + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY[0:3]; } foo_t; -interface intf - #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}) - (); +interface intf #( + parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}} +) (); endinterface -module sub (intf single_intf_port); - localparam byte single_foo_bar_byte = single_intf_port.FOO.BAR_ARRAY[3]; +module sub ( + intf single_intf_port +); + localparam byte single_foo_bar_byte = single_intf_port.FOO.BAR_ARRAY[3]; initial begin #1; @@ -31,13 +33,10 @@ module sub (intf single_intf_port); end endmodule -module t (); +module t; intf single_intf (); - sub - the_sub ( - .single_intf_port(single_intf) - ); + sub the_sub (.single_intf_port(single_intf)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface1.v b/test_regress/t/t_lparam_dep_iface1.v index c9029fc01..43d9254b6 100644 --- a/test_regress/t/t_lparam_dep_iface1.v +++ b/test_regress/t/t_lparam_dep_iface1.v @@ -12,18 +12,20 @@ // verilog_format: on typedef struct { - int BAR_INT; - bit BAR_BIT; - byte BAR_ARRAY [0:3]; + int BAR_INT; + bit BAR_BIT; + byte BAR_ARRAY[0:3]; } foo_t; -interface intf - #(parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}}) - (); +interface intf #( + parameter foo_t FOO = '{4, 1'b1, '{8'd1, 8'd2, 8'd4, 8'd8}} +) (); endinterface -module sub (intf the_intf_port [4]); - localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; +module sub ( + intf the_intf_port[4] +); + localparam int intf_foo_bar_int = the_intf_port[0].FOO.BAR_INT; initial begin #1; @@ -31,13 +33,10 @@ module sub (intf the_intf_port [4]); end endmodule -module t (); - intf the_intf [4] (); +module t; + intf the_intf[4] (); - sub - the_sub ( - .the_intf_port (the_intf) - ); + sub the_sub (.the_intf_port(the_intf)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface10.v b/test_regress/t/t_lparam_dep_iface10.v index 0e34e4793..7fbfb5672 100644 --- a/test_regress/t/t_lparam_dep_iface10.v +++ b/test_regress/t/t_lparam_dep_iface10.v @@ -19,24 +19,26 @@ package scp; endpackage interface a_if #( - parameter a_p = 0 -)(); + parameter a_p = 0 +) (); localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP_MUL = cfg.ABits * cfg.BBits; localparam int LP_ADD = cfg.ABits + cfg.BBits; - a_if #(LP_MUL) types_mul(); - a_if #(LP_ADD) types_add(); + a_if #(LP_MUL) types_mul (); + a_if #(LP_ADD) types_add (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.types_mul.a_t a_mul_t; @@ -52,17 +54,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface11.v b/test_regress/t/t_lparam_dep_iface11.v index 6ed0ccd3c..eee64ae45 100644 --- a/test_regress/t/t_lparam_dep_iface11.v +++ b/test_regress/t/t_lparam_dep_iface11.v @@ -19,33 +19,35 @@ package scp; endpackage interface a_if #( - parameter a_p = 0 -)(); + parameter a_p = 0 +) (); localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface interface b_if #( - parameter b_p = 0 -)(); + parameter b_p = 0 +) (); localparam int LP0 = b_p + 3; typedef logic [LP0-1:0] b_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_inst(); - b_if #(LP0) b_inst(); + a_if #(LP0) a_inst (); + b_if #(LP0) b_inst (); typedef a_inst.a_t a_t; typedef b_inst.b_t b_t; endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -61,17 +63,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface12.v b/test_regress/t/t_lparam_dep_iface12.v index e462e4cca..d8f8421e1 100644 --- a/test_regress/t/t_lparam_dep_iface12.v +++ b/test_regress/t/t_lparam_dep_iface12.v @@ -20,40 +20,42 @@ endpackage // Level 4: innermost interface interface d_if #( - parameter d_p = 0 -)(); + parameter d_p = 0 +) (); localparam int LP0 = d_p + 1; typedef logic [LP0-1:0] d_t; endinterface // Level 3 interface c_if #( - parameter c_p = 0 -)(); + parameter c_p = 0 +) (); localparam int LP0 = c_p * 2; - d_if #(LP0) d_inst(); + d_if #(LP0) d_inst (); typedef d_inst.d_t c_t; endinterface // Level 2 interface b_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - c_if #(LP0) c_inst(); + c_if #(LP0) c_inst (); typedef c_inst.c_t b_t; endinterface // Level 1: outermost interface interface a_if #( - parameter scp::cfg_t cfg = 0 -)(); - b_if #(cfg) b_inst(); + parameter scp::cfg_t cfg = 0 +) (); + b_if #(cfg) b_inst (); typedef b_inst.b_t a_t; endinterface -module m #(parameter scp::cfg_t cfg=0) ( - a_if io +module m #( + parameter scp::cfg_t cfg = 0 +) ( + a_if io ); typedef io.a_t a_t; @@ -69,17 +71,12 @@ module m #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t cfg = '{ABits : 2, BBits : 3}; a_if #(cfg) a_io (); - m #(cfg) m_inst( - .io(a_io) - ); + m #(cfg) m_inst (.io(a_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface13.v b/test_regress/t/t_lparam_dep_iface13.v index 4feff82f7..1b5ac1d7f 100644 --- a/test_regress/t/t_lparam_dep_iface13.v +++ b/test_regress/t/t_lparam_dep_iface13.v @@ -29,37 +29,39 @@ package sc; endpackage interface simple_cache_types_if #( - parameter sc::cfg_t cfg = 0 -)(); + parameter sc::cfg_t cfg = 0 +) (); - localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; - localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; - localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); - localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); - localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; - localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; - localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; + localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; endinterface interface simple_cache_if #( - parameter sc::cfg_t cfg = 0 -)(); - simple_cache_types_if #(cfg) types(); + parameter sc::cfg_t cfg = 0 +) (); + simple_cache_types_if #(cfg) types (); endinterface -module simple_cache #(parameter sc::cfg_t cfg=0) ( - simple_cache_if io +module simple_cache #( + parameter sc::cfg_t cfg = 0 +) ( + simple_cache_if io ); localparam num_rld_beats = cfg.LineSize / cfg.RefillWidth; localparam num_arrays = cfg.FgWidth / cfg.RefillWidth; - localparam dat_array_width = cfg.RefillWidth*8; - localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; - localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; - localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; - localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; + localparam dat_array_width = cfg.RefillWidth * 8; + localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; + localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; + localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; initial begin #1; @@ -75,28 +77,26 @@ module simple_cache #(parameter sc::cfg_t cfg=0) ( endmodule -module t(); +module t; localparam sc::cfg_t sc_cfg = '{ - CmdTagBits : $clog2(6), - Associativity : 2, - Capacity : 1024, - LineSize : 64, - StateBits : 2, - AddrBits : 64, - MissQSize : 2, + CmdTagBits : $clog2(6), + Associativity : 2, + Capacity : 1024, + LineSize : 64, + StateBits : 2, + AddrBits : 64, + MissQSize : 2, - FgWidth : 16, - RefillWidth : 8 + FgWidth : 16, + RefillWidth : 8 }; simple_cache_if #(sc_cfg) sc_io (); - simple_cache #(sc_cfg) simple_cache( - .io(sc_io) - ); + simple_cache #(sc_cfg) simple_cache (.io(sc_io)); - localparam int SC_DROWS_PER_LINE = sc_io.types.SC_DROWS_PER_LINE; + localparam int SC_DROWS_PER_LINE = sc_io.types.SC_DROWS_PER_LINE; initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface14.v b/test_regress/t/t_lparam_dep_iface14.v index 04ac60423..c14a92a87 100644 --- a/test_regress/t/t_lparam_dep_iface14.v +++ b/test_regress/t/t_lparam_dep_iface14.v @@ -15,18 +15,22 @@ // verilog_format: on typedef struct packed { - int unsigned ABits; - int unsigned BBits; + int unsigned ABits; + int unsigned BBits; } scp_cfg_t; -interface a_if #(parameter a_p = 0)(); +interface a_if #( + parameter a_p = 0 +) (); localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface -interface sct_if #(parameter scp_cfg_t cfg = 0)(); +interface sct_if #( + parameter scp_cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; // Captured typedef from nested interface endinterface @@ -34,39 +38,43 @@ interface intf #( parameter type data_t = bit, parameter int arr[2][4] ) (); - data_t data; - logic [$bits(data)-1:0] other_data; + data_t data; + logic [$bits(data)-1:0] other_data; endinterface module sub #( parameter int width, parameter int arr[2][4] ) (); - typedef struct packed { - logic [3:3] [0:0] [width-1:0] field; - } user_type_t; + typedef struct packed {logic [3:3][0:0][width-1:0] field;} user_type_t; - // This has a PIN that assigns data_t - intf #( - .data_t(user_type_t), - .arr(arr) - ) the_intf (); + // This has a PIN that assigns data_t + intf #( + .data_t(user_type_t), + .arr(arr) + ) the_intf (); - logic [width-1:0] signal; + logic [width-1:0] signal; - always_comb begin - the_intf.data.field = signal; - the_intf.other_data = signal; - end + always_comb begin + the_intf.data.field = signal; + the_intf.other_data = signal; + end endmodule -module t (); +module t; localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3}; sct_if #(sc_cfg) types (); - sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); - sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); + sub #( + .width(8), + .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub8 (); + sub #( + .width(16), + .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub16 (); typedef types.a_if0.a_t a_t; typedef types.a_t a2_t; @@ -75,7 +83,7 @@ module t (); #1; `checkd(12, $bits(a_t)); `checkd(12, $bits(a2_t)); - `checkd(8, $bits(sub8.the_intf.data)); + `checkd(8, $bits(sub8.the_intf.data)); `checkd(16, $bits(sub16.the_intf.data)); #1; diff --git a/test_regress/t/t_lparam_dep_iface15.v b/test_regress/t/t_lparam_dep_iface15.v index 2af8515ac..c48ac66fb 100644 --- a/test_regress/t/t_lparam_dep_iface15.v +++ b/test_regress/t/t_lparam_dep_iface15.v @@ -19,41 +19,45 @@ typedef struct packed { int unsigned BBits; } scp_cfg_t; -interface a_if #(parameter a_p = 0)(); +interface a_if #( + parameter a_p = 0 +) (); localparam int LP0 = a_p; typedef logic [LP0-1:0] a_t; endinterface -interface sct_if #(parameter scp_cfg_t cfg = 0)(); +interface sct_if #( + parameter scp_cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; endinterface -interface sc_if #(parameter scp_cfg_t cfg = 0)(); - sct_if #(cfg) types(); +interface sc_if #( + parameter scp_cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); typedef types.a_t a_t; endinterface interface intf #( - parameter type data_t = bit, - parameter int arr[2][4] + parameter type data_t = bit, + parameter int arr[2][4] ) (); data_t data; logic [$bits(data)-1:0] other_data; endinterface module sub #( - parameter int width, - parameter int arr[2][4] + parameter int width, + parameter int arr[2][4] ) (); - typedef struct packed { - logic [3:3] [0:0] [width-1:0] field; - } user_type_t; + typedef struct packed {logic [3:3][0:0][width-1:0] field;} user_type_t; intf #( - .data_t(user_type_t), - .arr(arr) + .data_t(user_type_t), + .arr(arr) ) the_intf (); logic [width-1:0] signal; @@ -64,8 +68,10 @@ module sub #( end endmodule -module sc #(parameter scp_cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp_cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -75,14 +81,20 @@ module sc #(parameter scp_cfg_t cfg=0) ( end endmodule -module t (); +module t; localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3}; sc_if #(sc_cfg) sc_io (); sc #(sc_cfg) sc_inst (.io(sc_io)); - sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); - sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 (); + sub #( + .width(8), + .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub8 (); + sub #( + .width(16), + .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub16 (); typedef sc_io.types.a_if0.a_t inner_t; typedef sc_io.types.a_t mid_t; diff --git a/test_regress/t/t_lparam_dep_iface16.v b/test_regress/t/t_lparam_dep_iface16.v index 1a68ec3e2..4e04f1c00 100644 --- a/test_regress/t/t_lparam_dep_iface16.v +++ b/test_regress/t/t_lparam_dep_iface16.v @@ -18,37 +18,41 @@ typedef struct packed { int unsigned BBits; } scp_cfg_t; -interface a_if #(parameter a_p = 0)(); +interface a_if #( + parameter a_p = 0 +) (); localparam int LP0 = a_p; typedef logic [LP0-1:0] a_t; endinterface -interface sct_if #(parameter scp_cfg_t cfg = 0)(); +interface sct_if #( + parameter scp_cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; endinterface -interface sc_if #(parameter scp_cfg_t cfg = 0)(); - sct_if #(cfg) types(); +interface sc_if #( + parameter scp_cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); typedef types.a_t a_t; endinterface interface intf #( - parameter type data_t = bit, - parameter int arr[2][4] + parameter type data_t = bit, + parameter int arr[2][4] ) (); data_t data; logic [$bits(data)-1:0] other_data; endinterface module sub #( - parameter int width, - parameter int arr[2][4] + parameter int width, + parameter int arr[2][4] ) (); - typedef struct packed { - logic [3:3] [0:0] [width-1:0] field; - } user_type_t; + typedef struct packed {logic [3:3][0:0][width-1:0] field;} user_type_t; intf #( .data_t(user_type_t), @@ -58,13 +62,15 @@ module sub #( logic [width-1:0] signal; always_comb begin - the_intf.data.field = signal; - the_intf.other_data = signal; + the_intf.data.field = signal; + the_intf.other_data = signal; end endmodule -module sc #(parameter scp_cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp_cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -74,13 +80,18 @@ module sc #(parameter scp_cfg_t cfg=0) ( end endmodule -module t (input clk); +module t ( + input clk +); localparam scp_cfg_t sc_cfg = '{ABits: 2, BBits: 3}; sc_if #(sc_cfg) sc_io (); sc #(sc_cfg) sc_inst (.io(sc_io)); - sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 (); + sub #( + .width(8), + .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}}) + ) sub8 (); typedef sc_io.types.a_if0.a_t inner_t; typedef sc_io.types.a_t mid_t; diff --git a/test_regress/t/t_lparam_dep_iface2.v b/test_regress/t/t_lparam_dep_iface2.v index afa27b5f2..6189846a0 100644 --- a/test_regress/t/t_lparam_dep_iface2.v +++ b/test_regress/t/t_lparam_dep_iface2.v @@ -25,7 +25,9 @@ package p2; } cfg_t; endpackage -interface types_if #(parameter p1::cfg_t cfg=0)(); +interface types_if #( + parameter p1::cfg_t cfg = 0 +) (); localparam int ABits = cfg.ABits; localparam int BBits = cfg.BBits; @@ -35,7 +37,9 @@ interface types_if #(parameter p1::cfg_t cfg=0)(); } a_t; endinterface -interface io_if #(parameter p1::cfg_t cfg=0)(); +interface io_if #( + parameter p1::cfg_t cfg = 0 +) (); localparam int ABits = cfg.ABits; localparam int BBits = cfg.BBits; @@ -44,8 +48,8 @@ interface io_if #(parameter p1::cfg_t cfg=0)(); typedef types.a_t a_t; endinterface -module modA( - io_if io +module modA ( + io_if io ); localparam int ABits = io.types.ABits; @@ -62,24 +66,16 @@ module modA( endmodule -module t (); - localparam p2::cfg_t mcfg = '{ - CBits : 8, - DBits : 16 - }; +module t; + localparam p2::cfg_t mcfg = '{CBits : 8, DBits : 16}; - localparam p1::cfg_t cfg = '{ - ABits : mcfg.CBits, - BBits : mcfg.CBits + mcfg.DBits - }; + localparam p1::cfg_t cfg = '{ABits : mcfg.CBits, BBits : mcfg.CBits + mcfg.DBits}; io_if #(cfg) modA_io (); typedef modA_io.types.a_t a_t; - modA modA_inst ( - .io(modA_io) - ); + modA modA_inst (.io(modA_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface3.v b/test_regress/t/t_lparam_dep_iface3.v index 5675fc8c1..cd4a2f573 100644 --- a/test_regress/t/t_lparam_dep_iface3.v +++ b/test_regress/t/t_lparam_dep_iface3.v @@ -29,16 +29,16 @@ package sc; endpackage interface simple_cache_types_if #( - parameter sc::cfg_t cfg = 0 -)(); + parameter sc::cfg_t cfg = 0 +) (); - localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; - localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; - localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); - localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); - localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; - localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; - localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_DROWS_PER_LINE = cfg.LineSize / cfg.FgWidth; + localparam int SC_NUM_DROWS = SC_NUM_LINES * SC_DROWS_PER_LINE; typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.Associativity-1:0] assoc_oh_t; @@ -73,9 +73,9 @@ interface simple_cache_types_if #( endinterface interface simple_cache_if #( - parameter sc::cfg_t cfg = 0 -)(); - simple_cache_types_if #(cfg) types(); + parameter sc::cfg_t cfg = 0 +) (); + simple_cache_types_if #(cfg) types (); typedef types.cmd_tag_t cmd_tag_t; typedef types.addr_t addr_t; @@ -83,8 +83,10 @@ interface simple_cache_if #( endinterface -module simple_cache #(parameter sc::cfg_t cfg=0) ( - simple_cache_if io +module simple_cache #( + parameter sc::cfg_t cfg = 0 +) ( + simple_cache_if io ); typedef io.types.addr_t addr_t; @@ -99,11 +101,11 @@ module simple_cache #(parameter sc::cfg_t cfg=0) ( localparam num_rld_beats = cfg.LineSize / cfg.RefillWidth; localparam num_arrays = cfg.FgWidth / cfg.RefillWidth; - localparam dat_array_width = cfg.RefillWidth*8; - localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; - localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; - localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; - localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; + localparam dat_array_width = cfg.RefillWidth * 8; + localparam int SC_DROWS_PER_LINE = io.types.SC_DROWS_PER_LINE; + localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; + localparam int SC_LINES_PER_WAY = io.types.SC_LINES_PER_WAY; + localparam int SC_NUM_DROWS = io.types.SC_NUM_DROWS; initial begin #1; @@ -119,26 +121,24 @@ module simple_cache #(parameter sc::cfg_t cfg=0) ( endmodule -module t(); +module t; localparam sc::cfg_t sc_cfg = '{ - CmdTagBits : $clog2(6), - Associativity : 2, - Capacity : 1024, - LineSize : 64, - StateBits : 2, - AddrBits : 64, - MissQSize : 2, + CmdTagBits : $clog2(6), + Associativity : 2, + Capacity : 1024, + LineSize : 64, + StateBits : 2, + AddrBits : 64, + MissQSize : 2, - FgWidth : 16, - RefillWidth : 8 + FgWidth : 16, + RefillWidth : 8 }; simple_cache_if #(sc_cfg) sc_io (); - simple_cache #(sc_cfg) simple_cache( - .io(sc_io) - ); + simple_cache #(sc_cfg) simple_cache (.io(sc_io)); //localparam int SC_DROWS_PER_LINE = sc_io.types.SC_DROWS_PER_LINE; //localparam int SC_NUM_LINES = sc_io.types.SC_NUM_LINES; diff --git a/test_regress/t/t_lparam_dep_iface4.v b/test_regress/t/t_lparam_dep_iface4.v index d81eab7c0..f31de4c9c 100644 --- a/test_regress/t/t_lparam_dep_iface4.v +++ b/test_regress/t/t_lparam_dep_iface4.v @@ -19,10 +19,10 @@ package scp; endpackage interface sct_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); - localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; typedef logic [(cfg.Capacity / cfg.LineSize)-1:0] sc_num_lines_t; @@ -31,17 +31,19 @@ interface sct_if #( endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); - sct_if #(cfg) types(); + parameter scp::cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); - localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; + localparam int SC_NUM_LINES = io.types.SC_NUM_LINES; typedef io.types.sc_num_lines_t sc_num_lines_t; typedef io.types.sc_num_lines_2_t sc_num_lines_2_t; @@ -57,18 +59,13 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); +module t; - localparam scp::cfg_t sc_cfg = '{ - Capacity : 1024, - LineSize : 64 - }; + localparam scp::cfg_t sc_cfg = '{Capacity : 1024, LineSize : 64}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) simple_cache( - .io(sc_io) - ); + sc #(sc_cfg) simple_cache (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface5.v b/test_regress/t/t_lparam_dep_iface5.v index cb0c654d9..7fdb47e79 100644 --- a/test_regress/t/t_lparam_dep_iface5.v +++ b/test_regress/t/t_lparam_dep_iface5.v @@ -21,29 +21,31 @@ package scp; endpackage interface sct_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); // this is intentional as I want all the dependencies to be resolved - localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; - localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; - localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); - localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); - localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; + localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; + localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; + localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); + localparam int SC_ROW_BITS = $clog2(SC_LINES_PER_WAY); + localparam int SC_TAG_BITS = cfg.AddrBits - SC_ROW_BITS - SC_BLOCK_BITS; typedef logic [SC_TAG_BITS-1:0] tag_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); - sct_if #(cfg) types(); + parameter scp::cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); - sct_if #(cfg) types(); + sct_if #(cfg) types (); typedef io.types.tag_t tag_t; typedef types.tag_t tag2_t; @@ -55,21 +57,19 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); +module t; localparam scp::cfg_t sc_cfg = '{ - Associativity : 2, - Capacity : 1024, - LineSize : 64, - AddrBits : 64 + Associativity : 2, + Capacity : 1024, + LineSize : 64, + AddrBits : 64 }; sc_if #(sc_cfg) sc_io (); typedef sc_io.types.tag_t tag_t; - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface6.v b/test_regress/t/t_lparam_dep_iface6.v index e19b8a6a4..fb6cd6375 100644 --- a/test_regress/t/t_lparam_dep_iface6.v +++ b/test_regress/t/t_lparam_dep_iface6.v @@ -19,32 +19,34 @@ package scp; endpackage interface a_if #( - parameter a_p = 0 -)(); - localparam int LP0 = a_p; + parameter a_p = 0 +) (); + localparam int LP0 = a_p; typedef logic [LP0-1:0] a_t; endinterface interface sct_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); // this is intentional as I want all the dependencies to be resolved - localparam int LP0 = cfg.ABits * cfg.BBits; + localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); - sct_if #(cfg) types(); + parameter scp::cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); typedef types.a_t a_t; endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -56,17 +58,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface7.v b/test_regress/t/t_lparam_dep_iface7.v index 133d8a802..e045e9de5 100644 --- a/test_regress/t/t_lparam_dep_iface7.v +++ b/test_regress/t/t_lparam_dep_iface7.v @@ -19,22 +19,24 @@ package scp; endpackage interface a_if #( - parameter a_p = 0 -)(); - localparam int LP0 = a_p * 2; + parameter a_p = 0 +) (); + localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); - localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) types(); + localparam int LP0 = cfg.ABits * cfg.BBits; + a_if #(LP0) types (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.types.a_t a_t; @@ -46,17 +48,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface8.v b/test_regress/t/t_lparam_dep_iface8.v index 3d8c325c0..cb9c0223f 100644 --- a/test_regress/t/t_lparam_dep_iface8.v +++ b/test_regress/t/t_lparam_dep_iface8.v @@ -20,31 +20,33 @@ endpackage // Level 3: innermost interface interface a_if #( - parameter a_p = 0 -)(); + parameter a_p = 0 +) (); localparam int LP0 = a_p * 2; typedef logic [LP0-1:0] a_t; endinterface // Level 2: middle interface interface sct_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) a_if0(); + a_if #(LP0) a_if0 (); typedef a_if0.a_t a_t; endinterface // Level 1: outermost interface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); - sct_if #(cfg) types(); + parameter scp::cfg_t cfg = 0 +) (); + sct_if #(cfg) types (); typedef types.a_t a_t; endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.a_t a_t; @@ -56,17 +58,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_lparam_dep_iface9.v b/test_regress/t/t_lparam_dep_iface9.v index 0e994e057..3c04fb769 100644 --- a/test_regress/t/t_lparam_dep_iface9.v +++ b/test_regress/t/t_lparam_dep_iface9.v @@ -20,23 +20,25 @@ endpackage // Interface with chained localparam dependencies interface a_if #( - parameter a_p = 0 -)(); - localparam int LP0 = a_p * 2; // LP0 = a_p * 2 - localparam int LP1 = LP0 + 1; // LP1 = LP0 + 1 - localparam int LP2 = LP1 * LP0; // LP2 = LP1 * LP0 + parameter a_p = 0 +) (); + localparam int LP0 = a_p * 2; // LP0 = a_p * 2 + localparam int LP1 = LP0 + 1; // LP1 = LP0 + 1 + localparam int LP2 = LP1 * LP0; // LP2 = LP1 * LP0 typedef logic [LP2-1:0] a_t; endinterface interface sc_if #( - parameter scp::cfg_t cfg = 0 -)(); + parameter scp::cfg_t cfg = 0 +) (); localparam int LP0 = cfg.ABits * cfg.BBits; - a_if #(LP0) types(); + a_if #(LP0) types (); endinterface -module sc #(parameter scp::cfg_t cfg=0) ( - sc_if io +module sc #( + parameter scp::cfg_t cfg = 0 +) ( + sc_if io ); typedef io.types.a_t a_t; @@ -49,17 +51,12 @@ module sc #(parameter scp::cfg_t cfg=0) ( end endmodule -module t(); - localparam scp::cfg_t sc_cfg = '{ - ABits : 2, - BBits : 3 - }; +module t; + localparam scp::cfg_t sc_cfg = '{ABits : 2, BBits : 3}; sc_if #(sc_cfg) sc_io (); - sc #(sc_cfg) sc( - .io(sc_io) - ); + sc #(sc_cfg) sc (.io(sc_io)); initial begin #2; diff --git a/test_regress/t/t_mailbox_concurrent.v b/test_regress/t/t_mailbox_concurrent.v index a719cfaf5..308c91877 100644 --- a/test_regress/t/t_mailbox_concurrent.v +++ b/test_regress/t/t_mailbox_concurrent.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2024 Liam Braun // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; mailbox #(int) m; task automatic test_get; diff --git a/test_regress/t/t_math_width.v b/test_regress/t/t_math_width.v index d53ae51eb..603cdc21a 100644 --- a/test_regress/t/t_math_width.v +++ b/test_regress/t/t_math_width.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2014 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; // See also t_lint_width diff --git a/test_regress/t/t_mod_interface_clocking_bad.v b/test_regress/t/t_mod_interface_clocking_bad.v index e64550fa7..a56f1ed5a 100644 --- a/test_regress/t/t_mod_interface_clocking_bad.v +++ b/test_regress/t/t_mod_interface_clocking_bad.v @@ -27,7 +27,7 @@ module sub ( endmodule -module t (); +module t; logic clk = 0; mem_if m_if (clk); diff --git a/test_regress/t/t_mod_longname.v b/test_regress/t/t_mod_longname.v index 8ba6c653f..7d6d0d0da 100644 --- a/test_regress/t/t_mod_longname.v +++ b/test_regress/t/t_mod_longname.v @@ -10,7 +10,7 @@ `define LONG_NAME_SUB sublongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie `define LONG_NAME_VAR varlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie -module t (); +module t; initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_name_collision.v b/test_regress/t/t_name_collision.v index 4f232e0b3..d2191f1bd 100644 --- a/test_regress/t/t_name_collision.v +++ b/test_regress/t/t_name_collision.v @@ -9,7 +9,7 @@ module HasNameParam (); endmodule -module t (); +module t; HasNameParam a(); initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_opt_merge_cond_relaxed.v b/test_regress/t/t_opt_merge_cond_relaxed.v index c48e0f5e9..d84a24008 100644 --- a/test_regress/t/t_opt_merge_cond_relaxed.v +++ b/test_regress/t/t_opt_merge_cond_relaxed.v @@ -4,8 +4,10 @@ // SPDX-FileCopyrightText: 2026 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 +// verilog_format: off `define stop $stop -`define check(got ,exp) do if ((got) !== (exp)) begin $write("%%Error: %s:%0d: cyc=%0d got='h%x exp='h%x\n", `__FILE__,`__LINE__, cyc, (got), (exp)); `stop; end while(0) +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d (%s !== %s)\n", `__FILE__,`__LINE__, (gotv), (expv), `"gotv`", `"expv`"); `stop; end while(0); +// verilog_format: on module t; @@ -26,19 +28,19 @@ module t; dpiWr = value; endfunction export "DPI-C" function setDpi; - import "DPI-C" context function void setViaDpi(int value); // calls setDpi(value) + import "DPI-C" context function void setViaDpi(int value); // calls setDpi(value) int dpiRd = 0; function automatic int getDpi(); return dpiRd; endfunction export "DPI-C" function getDpi; - import "DPI-C" context function int getViaDpi(); // calls getDpi() + import "DPI-C" context function int getViaDpi(); // calls getDpi() int tmp; int cnt = 0; - int pub /* verilator public_flat_rd */ = 0; + int pub /* verilator public_flat_rd */ = 0; always @(posedge clk) begin @@ -60,7 +62,7 @@ module t; if (cyc[1:0] == 2'd2) setViaDpi(cyc + 16); ++cnt; if (cyc[1:0] == 2'd2) setViaDpi(cyc + 32); - `check(dpiWr, cyc % 4 == 2 ? cyc + 32 : 13); + `checkd(dpiWr, cyc % 4 == 2 ? cyc + 32 : 13); // DPI call, but no public state involved. dpiRd = 24; @@ -74,7 +76,7 @@ module t; tmp = getViaDpi(); tmp += 20; end - `check(tmp, cyc % 4 == 1 ? 44 : 10); + `checkd(tmp, cyc % 4 == 1 ? 44 : 10); //--------------------------- // NOT Mergeable @@ -82,36 +84,36 @@ module t; // DPI call, possible implicit state chagne. tmp = dpiWr; if (dpiWr[1:0] == 2'd2) setViaDpi(dpiWr & ~32'b11); - if (dpiWr[1:0] == 2'd2) setViaDpi(dpiWr + 10); // Won't execute - `check(dpiWr, cyc % 4 == 2 ? (tmp & ~32'b11) : 13); + if (dpiWr[1:0] == 2'd2) setViaDpi(dpiWr + 10); // Won't execute + `checkd(dpiWr, cyc % 4 == 2 ? (tmp & ~32'b11) : 13); // DPI call, possible implicit state acces. dpiWr = 14; if (cyc[1:0] == 2'd3) setViaDpi(cyc + 32); ++pub; if (cyc[1:0] == 2'd3) setViaDpi(cyc + 64); - `check(dpiWr, cyc % 4 == 3 ? cyc + 64 : 14); + `checkd(dpiWr, cyc % 4 == 3 ? cyc + 64 : 14); // DPI call, possible implicit state change. dpiWr = 11; - tmp = cyc + $c(0); // Prevent repalcing with 'cyc' + tmp = cyc + $c(0); // Prevent repalcing with 'cyc' if (tmp % 3 == 0) begin - setViaDpi(3); - tmp = dpiWr + 2; + setViaDpi(3); + tmp = dpiWr + 2; end - if (tmp % 3 == 0) setViaDpi(4); // Won't execute - `check(dpiWr, cyc % 3 == 0 ? 3 : 11); + if (tmp % 3 == 0) setViaDpi(4); // Won't execute + `checkd(dpiWr, cyc % 3 == 0 ? 3 : 11); dpiWr = 3; // DPI call, possible implicit state change. - tmp = cyc + $c(0); // Prevent repalcing with 'cyc' + tmp = cyc + $c(0); // Prevent repalcing with 'cyc' if (tmp % 2 == 0) begin - setViaDpi(6); - if (cyc[2]) tmp = dpiWr + 1; + setViaDpi(6); + if (cyc[2]) tmp = dpiWr + 1; end - if (tmp % 2 == 0) setViaDpi(4); // Sometime executes - `check(tmp, cyc % 2 == 0 ? (cyc[2] ? 7 : cyc) : cyc); - `check(dpiWr, cyc % 2 == 0 ? (cyc[2] ? 6 : 4) : 3); + if (tmp % 2 == 0) setViaDpi(4); // Sometime executes + `checkd(tmp, cyc % 2 == 0 ? (cyc[2] ? 7 : cyc) : cyc); + `checkd(dpiWr, cyc % 2 == 0 ? (cyc[2] ? 6 : 4) : 3); // DPI call, possible implicit state read. dpiRd = 2; @@ -122,8 +124,8 @@ module t; if (cyc[1:0] == 2'd1) begin dpiRd = 3; end - `check(tmp, cyc % 4 == 1 ? 100 : 2); - `check(dpiRd, cyc % 4 == 1 ? 3 : 2); + `checkd(tmp, cyc % 4 == 1 ? 100 : 2); + `checkd(dpiRd, cyc % 4 == 1 ? 3 : 2); //--------------------------- // Dispaly so not eliminated diff --git a/test_regress/t/t_package_abs.v b/test_regress/t/t_package_abs.v index 5ea79a8e3..a265e1861 100644 --- a/test_regress/t/t_package_abs.v +++ b/test_regress/t/t_package_abs.v @@ -15,7 +15,7 @@ package functions; endfunction endpackage -module t (); +module t; import functions::*; localparam P = 1; generate diff --git a/test_regress/t/t_package_ddecl.v b/test_regress/t/t_package_ddecl.v index 03cedbe40..ad24d2901 100644 --- a/test_regress/t/t_package_ddecl.v +++ b/test_regress/t/t_package_ddecl.v @@ -14,7 +14,7 @@ package functions; endtask endpackage -module t (); +module t; // synthesis translate off import functions::*; // synthesis translate on diff --git a/test_regress/t/t_param_default_override.v b/test_regress/t/t_param_default_override.v index 65caaa4d4..c70582101 100644 --- a/test_regress/t/t_param_default_override.v +++ b/test_regress/t/t_param_default_override.v @@ -42,7 +42,7 @@ module m8 #(parameter int N = 4) endmodule -module t (); +module t; reg [5:0] i0, i1, i2, i3; reg [1:0] S; wire [5:0] Y; diff --git a/test_regress/t/t_param_pattern2.v b/test_regress/t/t_param_pattern2.v index 64211085b..1245de47c 100644 --- a/test_regress/t/t_param_pattern2.v +++ b/test_regress/t/t_param_pattern2.v @@ -10,7 +10,7 @@ module dut assign x = P[2]; endmodule -module t(); +module t; int o; dut #(.P('{1, 2, 3, 4, 5})) u_dut(.x(o)); diff --git a/test_regress/t/t_param_real.v b/test_regress/t/t_param_real.v index 0190587e5..543e317d7 100644 --- a/test_regress/t/t_param_real.v +++ b/test_regress/t/t_param_real.v @@ -14,7 +14,7 @@ module mod #( end endmodule -module t(); +module t; mod #(.HZ(123.45)) mod1(); mod #(.HZ(24.45)) mod2(); diff --git a/test_regress/t/t_param_real2.v b/test_regress/t/t_param_real2.v index ecdca0549..03f225549 100644 --- a/test_regress/t/t_param_real2.v +++ b/test_regress/t/t_param_real2.v @@ -9,7 +9,7 @@ module foo endmodule -module t(); +module t; genvar m, r; generate diff --git a/test_regress/t/t_param_type_cmp.v b/test_regress/t/t_param_type_cmp.v index 547986c89..99ce7ad7b 100644 --- a/test_regress/t/t_param_type_cmp.v +++ b/test_regress/t/t_param_type_cmp.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2004 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; logic [2:0] a; logic [2:0] b; diff --git a/test_regress/t/t_param_type_from_iface_struct.v b/test_regress/t/t_param_type_from_iface_struct.v index 9628c9748..65331477a 100644 --- a/test_regress/t/t_param_type_from_iface_struct.v +++ b/test_regress/t/t_param_type_from_iface_struct.v @@ -26,32 +26,36 @@ package cfg_pkg; endpackage // Parameterized inner interface with struct typedefs -interface inner_if #(parameter cfg_pkg::cfg_t cfg = '0); +interface inner_if #( + parameter cfg_pkg::cfg_t cfg = '0 +); typedef struct packed { - logic [cfg.IdBits-1:0] id; + logic [cfg.IdBits-1:0] id; logic [cfg.DataBits-1:0] data; } req_t; typedef struct packed { - logic [cfg.IdBits-1:0] id; - logic [1:0] resp; + logic [cfg.IdBits-1:0] id; + logic [1:0] resp; } resp_t; - req_t req; + req_t req; resp_t resp; endinterface // Outer interface containing a nested inner_if -interface outer_if #(parameter cfg_pkg::cfg_t cfg = '0); - inner_if #(cfg) inner(); +interface outer_if #( + parameter cfg_pkg::cfg_t cfg = '0 +); + inner_if #(cfg) inner (); endinterface // Module with type parameters (consumer of struct typedefs) module typed_mod #( - parameter type req_t = logic, - parameter type resp_t = logic -)( - input logic clk + parameter type req_t = logic, + parameter type resp_t = logic +) ( + input logic clk ); - req_t r; + req_t r; resp_t s; assign r = '0; assign s = '0; @@ -59,30 +63,42 @@ endmodule // Wrapper: takes outer_if ports, typedefs through two-level nesting, // passes as type parameters to typed_mod -module wrap_mod #(parameter int NUM = 1)( - input logic clk, - outer_if ports [NUM] +module wrap_mod #( + parameter int NUM = 1 +) ( + input logic clk, + outer_if ports[NUM] ); - typedef ports[0].inner.req_t local_req_t; + typedef ports[0].inner.req_t local_req_t; typedef ports[0].inner.resp_t local_resp_t; - typed_mod #(.req_t(local_req_t), .resp_t(local_resp_t)) u_sub(.clk(clk)); + typed_mod #( + .req_t(local_req_t), + .resp_t(local_resp_t) + ) u_sub ( + .clk(clk) + ); endmodule -module t(); +module t; logic clk = 0; localparam cfg_pkg::cfg_t CFG_A = '{IdBits: 4, DataBits: 32}; localparam cfg_pkg::cfg_t CFG_B = '{IdBits: 8, DataBits: 64}; // Force inner_if to be cloned with different configs first - inner_if #(CFG_A) early_a(); - inner_if #(CFG_B) early_b(); + inner_if #(CFG_A) early_a (); + inner_if #(CFG_B) early_b (); assign early_a.req = '0; assign early_a.resp = '0; assign early_b.req = '0; assign early_b.resp = '0; - outer_if #(CFG_A) io [2] (); - wrap_mod #(.NUM(2)) u_wrap(.clk(clk), .ports(io)); + outer_if #(CFG_A) io[2] (); + wrap_mod #( + .NUM(2) + ) u_wrap ( + .clk(clk), + .ports(io) + ); initial begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_param_up_bad.v b/test_regress/t/t_param_up_bad.v index b0632a1dc..92bf6d5e9 100644 --- a/test_regress/t/t_param_up_bad.v +++ b/test_regress/t/t_param_up_bad.v @@ -26,7 +26,7 @@ module parent child c (); endmodule -module t (); +module t; // The parameter must be anything other than the default parent #( 1 ) p (); endmodule diff --git a/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v index c1eda693e..1f83bb8d6 100644 --- a/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v +++ b/test_regress/t/t_paramgraph_ascrange_prelim_cfg.v @@ -12,30 +12,30 @@ // verilog_format: on package axis; - typedef struct packed { - int unsigned DataWidth; - } cfg_t; + typedef struct packed {int unsigned DataWidth;} cfg_t; endpackage -interface axis_if #(parameter axis::cfg_t cfg = '0)(); +interface axis_if #( + parameter axis::cfg_t cfg = '0 +) (); typedef logic [cfg.DataWidth-1:0] tdata_t; endinterface module axis_chan #( - parameter axis::cfg_t chan_cfg = '0 + parameter axis::cfg_t chan_cfg = '0 ) (); - axis_if #(chan_cfg) axis_channel_io(); + axis_if #(chan_cfg) axis_channel_io (); typedef axis_channel_io.tdata_t data_t; localparam int kWidth = $bits(data_t); initial begin #1; - `checkd(kWidth,32); + `checkd(kWidth, 32); end endmodule module t; localparam axis::cfg_t axis_chan_cfg = '{DataWidth: 32}; - axis_chan #(.chan_cfg(axis_chan_cfg)) u_chan(); + axis_chan #(.chan_cfg(axis_chan_cfg)) u_chan (); initial begin #2; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_paramgraph_bisect1.v b/test_regress/t/t_paramgraph_bisect1.v index 4de603c87..c97351006 100644 --- a/test_regress/t/t_paramgraph_bisect1.v +++ b/test_regress/t/t_paramgraph_bisect1.v @@ -17,7 +17,7 @@ package rial; -// Configuration structure + // Configuration structure typedef struct packed { // CCA Parameters int unsigned NumDd; @@ -29,16 +29,18 @@ endpackage package cb; typedef struct packed { - int unsigned XdatSize; // raw packet data size + int unsigned XdatSize; // raw packet data size } cfg_t; endpackage -interface ccia_types_if #(parameter rial::cfg_t cfg=0)(); +interface ccia_types_if #( + parameter rial::cfg_t cfg = 0 +) (); // 'base' types typedef logic [$clog2(cfg.DDNumStuff)-1:0] wave_index_t; -// types for tb + // types for tb typedef struct packed { logic [3:0] e_cmd; logic en; @@ -48,39 +50,31 @@ interface ccia_types_if #(parameter rial::cfg_t cfg=0)(); logic [64-(4+1+1+$clog2(cfg.DDNumStuff)+12)-1:0] pad0; } tl_reg_cmd_t; - typedef struct packed { - logic [63:0] raw; - } tl_addr_cmd_t; + typedef struct packed {logic [63:0] raw;} tl_addr_cmd_t; typedef union packed { tl_reg_cmd_t rcmd; tl_addr_cmd_t acmd; } tl_data_fld_t; - typedef union packed { - tl_data_fld_t [cfg.DDNumStuffThreads-1:0] d_a; - } cmd_data_t; + typedef union packed {tl_data_fld_t [cfg.DDNumStuffThreads-1:0] d_a;} cmd_data_t; - typedef struct packed { - cmd_data_t d; - } cmd_beat_t; + typedef struct packed {cmd_data_t d;} cmd_beat_t; endinterface module rial_top #( - parameter rial::cfg_t aer_cfg=0 -)(); + parameter rial::cfg_t aer_cfg = 0 +) (); -// for the types - ccia_types_if #(aer_cfg) ccia_types(); + // for the types + ccia_types_if #(aer_cfg) ccia_types (); -// genvars and locally defined types + // genvars and locally defined types typedef ccia_types.cmd_beat_t cmd_beat_t; // CB and RBUS - localparam cb::cfg_t cb_cfg = '{ - XdatSize:$bits(cmd_beat_t) - }; + localparam cb::cfg_t cb_cfg = '{XdatSize: $bits(cmd_beat_t)}; initial begin #1; @@ -93,19 +87,18 @@ module rial_top #( endmodule // SOC Top w/IO and SOC configuration -module rial_wrap(); +module rial_wrap (); parameter rial::cfg_t aer_cfg = '{ - NumDd : 3, - // CC Parameters - DDNumStuff : 4, - DDNumStuffThreads : 8 + NumDd : 3, + // CC Parameters + DDNumStuff : + 4, + DDNumStuffThreads : 8 }; -// DUT - rial_top #( - .aer_cfg(aer_cfg) - ) rial_top(); + // DUT + rial_top #(.aer_cfg(aer_cfg)) rial_top (); initial begin #2; diff --git a/test_regress/t/t_paramgraph_bits_corruption.v b/test_regress/t/t_paramgraph_bits_corruption.v index e5a34d207..f31d3da79 100644 --- a/test_regress/t/t_paramgraph_bits_corruption.v +++ b/test_regress/t/t_paramgraph_bits_corruption.v @@ -35,7 +35,7 @@ package TestPkg; logic [31:0] field14; logic [31:0] field15; logic [31:0] field16; - logic [12:0] field17; // 525 bits total (16*32 + 13) + logic [12:0] field17; // 525 bits total (16*32 + 13) } cmd_beat_t; typedef struct packed { @@ -50,10 +50,10 @@ package TestPkg; // where the pattern literal gets a 128-bit constant instead of proper 32-bit assignment // Note: cmd_beat_t is referenced directly, not through a localparam type alias localparam cfg_t cb_cfg = '{ - Rids : 32'h1, - Pids : 32'h2, - Fnum : 32'h3, - XdatSize : $bits(cmd_beat_t) // Should be 525, but gets corrupted + Rids : 32'h1, + Pids : 32'h2, + Fnum : 32'h3, + XdatSize : $bits(cmd_beat_t) // Should be 525, but gets corrupted }; endpackage diff --git a/test_regress/t/t_paramgraph_bits_iface_typedef.v b/test_regress/t/t_paramgraph_bits_iface_typedef.v index 81cb7e258..12a236295 100644 --- a/test_regress/t/t_paramgraph_bits_iface_typedef.v +++ b/test_regress/t/t_paramgraph_bits_iface_typedef.v @@ -11,7 +11,7 @@ // Interface with a packed struct typedef interface axis_if #( - parameter int DataWidth = 8 + parameter int DataWidth = 8 ); typedef struct packed { logic [DataWidth-1:0] data; @@ -22,27 +22,27 @@ interface axis_if #( logic tvalid; logic tready; - modport initiator (output tdata, tvalid, input tready); - modport target (input tdata, tvalid, output tready); + modport initiator(output tdata, tvalid, input tready); + modport target(input tdata, tvalid, output tready); endinterface // Simple buffer module that takes a width parameter module skid_buffer #( - parameter int p_width = 8 + parameter int p_width = 8 ) ( - input logic clk, - input logic [p_width-1:0] data_i, - output logic [p_width-1:0] data_o + input logic clk, + input logic [p_width-1:0] data_i, + output logic [p_width-1:0] data_o ); always_ff @(posedge clk) data_o <= data_i; endmodule // Module that uses $bits() of an interface typedef as a parameter module axis_upsizer #( - parameter int p_has_skid = 1 + parameter int p_has_skid = 1 ) ( - input logic clk, - axis_if.initiator op_io + input logic clk, + axis_if.initiator op_io ); // Typedef from interface port typedef op_io.pkt_t op_pkt_t; @@ -50,15 +50,17 @@ module axis_upsizer #( op_pkt_t op_pkt_int; generate - if (p_has_skid>0) begin : gen_skid + if (p_has_skid > 0) begin : gen_skid op_pkt_t skid_src_pkt; // This is the problematic line - $bits(op_pkt_t) used as parameter // The PARAMTYPEDTYPE for op_pkt_t has REQUIREDTYPE that needs resolution - skid_buffer #(.p_width($bits(op_pkt_t))) skid ( - .clk(clk), - .data_i(op_pkt_int), - .data_o(skid_src_pkt) + skid_buffer #( + .p_width($bits(op_pkt_t)) + ) skid ( + .clk(clk), + .data_i(op_pkt_int), + .data_o(skid_src_pkt) ); end endgenerate @@ -67,11 +69,13 @@ endmodule module top; logic clk; - axis_if #(.DataWidth(32)) op_if(); + axis_if #(.DataWidth(32)) op_if (); - axis_upsizer #(.p_has_skid(1)) u_upsizer ( - .clk(clk), - .op_io(op_if.initiator) + axis_upsizer #( + .p_has_skid(1) + ) u_upsizer ( + .clk(clk), + .op_io(op_if.initiator) ); initial begin diff --git a/test_regress/t/t_paramgraph_cloned_refdtype.v b/test_regress/t/t_paramgraph_cloned_refdtype.v index 92700abdc..7b5d37f98 100644 --- a/test_regress/t/t_paramgraph_cloned_refdtype.v +++ b/test_regress/t/t_paramgraph_cloned_refdtype.v @@ -14,7 +14,10 @@ // // A registry class that returns its own type -class uvm_object_registry #(type T = int, string Tname = ""); +class uvm_object_registry #( + type T = int, + string Tname = "" +); typedef uvm_object_registry#(T, Tname) this_type; static function this_type get(); @@ -26,7 +29,9 @@ endclass // A pool class that has a nested type_id typedef pointing to the registry // The key pattern: type_id is a typedef to uvm_object_registry parameterized with THIS class -class uvm_object_string_pool #(type T = int); +class uvm_object_string_pool #( + type T = int +); typedef uvm_object_string_pool#(T) this_type; typedef uvm_object_registry#(uvm_object_string_pool#(T)) type_id; @@ -49,10 +54,14 @@ class uvm_object_string_pool #(type T = int); endclass // Simple wrapper classes to create different specializations -class uvm_queue #(type T = int); +class uvm_queue #( + type T = int +); endclass -class uvm_event #(type T = int); +class uvm_event #( + type T = int +); endclass // Create two different specializations of uvm_object_string_pool @@ -66,8 +75,8 @@ module t; // Before the fix, both would incorrectly return the same registry type // After the fix, each returns its own correctly-specialized registry - uvm_object_registry#(uvm_object_string_pool#(uvm_event#(int))) event_reg; - uvm_object_registry#(uvm_object_string_pool#(uvm_queue#(string))) queue_reg; + uvm_object_registry #(uvm_object_string_pool #(uvm_event #(int))) event_reg; + uvm_object_registry #(uvm_object_string_pool #(uvm_queue #(string))) queue_reg; event_reg = uvm_event_pool::get_type(); queue_reg = uvm_queue_pool::get_type(); diff --git a/test_regress/t/t_paramgraph_comined_iface.v b/test_regress/t/t_paramgraph_comined_iface.v index 8f844903e..c3590707b 100644 --- a/test_regress/t/t_paramgraph_comined_iface.v +++ b/test_regress/t/t_paramgraph_comined_iface.v @@ -26,7 +26,9 @@ typedef struct packed { } axi_cfg_t; // INNERMOST: Parameterized interface with typedefs -interface axi4_if #(parameter axi_cfg_t cfg = 0)(); +interface axi4_if #( + parameter axi_cfg_t cfg = 0 +) (); localparam int unsigned AddrBits = cfg.AddrBits * 2; localparam int unsigned DataBits = cfg.DataBits * 2; localparam int unsigned IdBits = cfg.IdBits * 2; @@ -36,22 +38,24 @@ interface axi4_if #(parameter axi_cfg_t cfg = 0)(); typedef logic [IdBits-1:0] id_t; typedef struct packed { - id_t id; - addr_t addr; + id_t id; + addr_t addr; } ar_chan_t; typedef struct packed { - id_t id; - data_t data; + id_t id; + data_t data; } r_chan_t; ar_chan_t ar; - r_chan_t r; + r_chan_t r; endinterface // MIDDLE: Interface that wraps axi4_if and re-exports its typedefs -interface tlb_io_if #(parameter axi_cfg_t axi_cfg = 0)(); - axi4_if #(.cfg(axi_cfg)) axi_tlb_io(); +interface tlb_io_if #( + parameter axi_cfg_t axi_cfg = 0 +) (); + axi4_if #(.cfg(axi_cfg)) axi_tlb_io (); // Re-export typedefs from nested interface typedef axi_tlb_io.r_chan_t r_chan_t; @@ -61,12 +65,12 @@ endinterface // OUTER: Interface with TWO SIBLING tlb_io_if instances with DIFFERENT params // This is the BLENDED pattern: sibling cells + nested chains interface cca_io_if #( - parameter axi_cfg_t axi_cfg_a = 0, - parameter axi_cfg_t axi_cfg_b = 0 -)(); + parameter axi_cfg_t axi_cfg_a = 0, + parameter axi_cfg_t axi_cfg_b = 0 +) (); // SIBLING CELLS - same interface type, DIFFERENT params - tlb_io_if #(.axi_cfg(axi_cfg_a)) tlb_io_a(); - tlb_io_if #(.axi_cfg(axi_cfg_b)) tlb_io_b(); + tlb_io_if #(.axi_cfg(axi_cfg_a)) tlb_io_a (); + tlb_io_if #(.axi_cfg(axi_cfg_b)) tlb_io_b (); // Re-export from each sibling (these should be DIFFERENT types) typedef tlb_io_a.r_chan_t r_chan_a_t; @@ -76,7 +80,7 @@ endinterface // MODULE: Accesses typedefs from BOTH sibling nested chains via interface port // This is the CRITICAL test - must distinguish between tlb_io_a and tlb_io_b module cca_xbar ( - cca_io_if cca_io + cca_io_if cca_io ); // Access typedefs through SIBLING nested interface chains // These MUST resolve to DIFFERENT types based on the different params @@ -105,12 +109,15 @@ module cca_xbar ( endmodule // TOP MODULE -module t(); +module t; localparam axi_cfg_t cfg_a = '{AddrBits: 32, DataBits: 64, IdBits: 4}; localparam axi_cfg_t cfg_b = '{AddrBits: 40, DataBits: 128, IdBits: 8}; - cca_io_if #(.axi_cfg_a(cfg_a), .axi_cfg_b(cfg_b)) cca_io(); - cca_xbar xbar(.cca_io(cca_io)); + cca_io_if #( + .axi_cfg_a(cfg_a), + .axi_cfg_b(cfg_b) + ) cca_io (); + cca_xbar xbar (.cca_io(cca_io)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_array_ports.v b/test_regress/t/t_paramgraph_iface_array_ports.v index be8b6d9bf..db9239cc6 100644 --- a/test_regress/t/t_paramgraph_iface_array_ports.v +++ b/test_regress/t/t_paramgraph_iface_array_ports.v @@ -22,7 +22,9 @@ package axi_pkg; } cfg_t; endpackage -interface axi4_if #(parameter axi_pkg::cfg_t cfg = '0)(); +interface axi4_if #( + parameter axi_pkg::cfg_t cfg = '0 +) (); typedef logic [cfg.IdBits-1:0] id_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.UserBits-1:0] user_t; @@ -34,16 +36,20 @@ interface axi4_if #(parameter axi_pkg::cfg_t cfg = '0)(); } req_t; endinterface -module sink #(parameter int N = 1)(axi4_if tgt_ports [N-1:0]); +module sink #( + parameter int N = 1 +) ( + axi4_if tgt_ports[N-1:0] +); localparam type req_t = tgt_ports[0].req_t; req_t rq; endmodule module top; - localparam axi_pkg::cfg_t cfg = '{IdBits:4, DataBits:32, UserBits:2}; - axi4_if #(.cfg(cfg)) tgt_ports [1:0](); + localparam axi_pkg::cfg_t cfg = '{IdBits: 4, DataBits: 32, UserBits: 2}; + axi4_if #(.cfg(cfg)) tgt_ports[1:0] (); - sink #(.N(2)) u_sink(.tgt_ports(tgt_ports)); + sink #(.N(2)) u_sink (.tgt_ports(tgt_ports)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_cfg_zero.v b/test_regress/t/t_paramgraph_iface_cfg_zero.v index 5efae55e5..dc14f75f9 100644 --- a/test_regress/t/t_paramgraph_iface_cfg_zero.v +++ b/test_regress/t/t_paramgraph_iface_cfg_zero.v @@ -22,12 +22,16 @@ package aerial; } cfg_t; endpackage -interface aicc_types_if #(parameter aerial::cfg_t cfg = '0)(); +interface aicc_types_if #( + parameter aerial::cfg_t cfg = '0 +) (); typedef logic [$clog2(cfg.NumCc)-1:0] cc_index_t; typedef logic [$clog2(cfg.CCNumIds)-1:0] trans_id_t; endinterface -module child(aicc_types_if types); +module child ( + aicc_types_if types +); localparam type cc_index_t = types.cc_index_t; localparam type trans_id_t = types.trans_id_t; cc_index_t cc_idx; @@ -35,9 +39,9 @@ module child(aicc_types_if types); endmodule module top; - localparam aerial::cfg_t aer_cfg = '{NumCc:4, CCNumWaves:2, CCNumIds:8}; - aicc_types_if #(.cfg(aer_cfg)) types(); - child u_child(.types(types)); + localparam aerial::cfg_t aer_cfg = '{NumCc: 4, CCNumWaves: 2, CCNumIds: 8}; + aicc_types_if #(.cfg(aer_cfg)) types (); + child u_child (.types(types)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_deadmod.v b/test_regress/t/t_paramgraph_iface_deadmod.v index e09cb446a..a84770bfb 100644 --- a/test_regress/t/t_paramgraph_iface_deadmod.v +++ b/test_regress/t/t_paramgraph_iface_deadmod.v @@ -18,7 +18,9 @@ package axi4; } cfg_t; endpackage -interface axi4_if #(parameter axi4::cfg_t cfg = '0)(); +interface axi4_if #( + parameter axi4::cfg_t cfg = '0 +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.DataBits/8-1:0] strb_t; @@ -32,8 +34,8 @@ interface axi4_if #(parameter axi4::cfg_t cfg = '0)(); } aw_chan_t; endinterface -module dead_mod( - axi4_if axi_io +module dead_mod ( + axi4_if axi_io ); typedef axi_io.addr_t addr_t; typedef axi_io.data_t data_t; @@ -45,14 +47,14 @@ module dead_mod( endmodule module dead_top; - localparam axi4::cfg_t cfg = '{IdBits:4, AddrBits:32, DataBits:64, UserBits:2}; - axi4_if #(.cfg(cfg)) axi_io(); + localparam axi4::cfg_t cfg = '{IdBits: 4, AddrBits: 32, DataBits: 64, UserBits: 2}; + axi4_if #(.cfg(cfg)) axi_io (); - dead_mod u_dead(.axi_io(axi_io)); + dead_mod u_dead (.axi_io(axi_io)); endmodule module top; - dead_top dead_top(); + dead_top dead_top (); initial begin #1; $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_paramgraph_iface_dependency1.v b/test_regress/t/t_paramgraph_iface_dependency1.v index a1dcc8e6e..f6980edc2 100644 --- a/test_regress/t/t_paramgraph_iface_dependency1.v +++ b/test_regress/t/t_paramgraph_iface_dependency1.v @@ -11,20 +11,18 @@ // verilog_format: on package a_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface depgraph_if #(a_pkg::cfg_t cfg=0)(); +interface depgraph_if #( + a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; - typedef struct packed { - byte_t a; - } pair_t; + typedef struct packed {byte_t a;} pair_t; endinterface -module a_mod( - depgraph_if ifc +module a_mod ( + depgraph_if ifc ); typedef ifc.pair_t pair_t; @@ -32,20 +30,16 @@ module a_mod( initial begin #1; - `checkd($bits(pair_t),8); + `checkd($bits(pair_t), 8); `checkd(p_a, 8); end endmodule -module t(); - localparam a_pkg::cfg_t cfg = '{ - a: 8 - }; +module t; + localparam a_pkg::cfg_t cfg = '{a: 8}; - depgraph_if #(cfg) ifc(); - a_mod #() a_mod_0( - .ifc(ifc) - ); + depgraph_if #(cfg) ifc (); + a_mod #() a_mod_0 (.ifc(ifc)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_dependency2.v b/test_regress/t/t_paramgraph_iface_dependency2.v index 5f8160bbc..442eabaaa 100644 --- a/test_regress/t/t_paramgraph_iface_dependency2.v +++ b/test_regress/t/t_paramgraph_iface_dependency2.v @@ -11,18 +11,16 @@ // verilog_format: on package a_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage package b_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface depgraph_if #(a_pkg::cfg_t cfg=0)(); +interface depgraph_if #( + a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; typedef logic [cfg.a*2-1:0] half_t; typedef struct packed { @@ -35,18 +33,14 @@ interface depgraph_if #(a_pkg::cfg_t cfg=0)(); } pair_u_t; endinterface -module t(); - localparam a_pkg::cfg_t cfg = '{ - a: 8 - }; +module t; + localparam a_pkg::cfg_t cfg = '{a: 8}; - depgraph_if #(cfg) ifc(); + depgraph_if #(cfg) ifc (); typedef ifc.pair_u_t pair_u_t; - localparam b_pkg::cfg_t cfg_b = '{ - a:$bits(pair_u_t) - }; + localparam b_pkg::cfg_t cfg_b = '{a: $bits(pair_u_t)}; initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_dependency3.v b/test_regress/t/t_paramgraph_iface_dependency3.v index 266e56b95..6064d179c 100644 --- a/test_regress/t/t_paramgraph_iface_dependency3.v +++ b/test_regress/t/t_paramgraph_iface_dependency3.v @@ -11,18 +11,16 @@ // verilog_format: on package a_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage package b_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface depgraph_if #(a_pkg::cfg_t cfg=0)(); +interface depgraph_if #( + a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; typedef logic [cfg.a*2-1:0] half_t; typedef struct packed { @@ -31,8 +29,8 @@ interface depgraph_if #(a_pkg::cfg_t cfg=0)(); } pair_t; endinterface -module a_mod( - depgraph_if ifc +module a_mod ( + depgraph_if ifc ); typedef ifc.pair_t pair_t; typedef ifc.half_t half_t; @@ -42,28 +40,22 @@ module a_mod( initial begin #1; - `checkd($bits(pair_t),24); + `checkd($bits(pair_t), 24); `checkd(p_a, 24); `checkd(p_b, 16); end endmodule -module t(); - localparam a_pkg::cfg_t cfg = '{ - a: 8 - }; +module t; + localparam a_pkg::cfg_t cfg = '{a: 8}; - depgraph_if #(cfg) ifc(); + depgraph_if #(cfg) ifc (); typedef ifc.byte_t byte_t; - a_mod #() a_mod_0( - .ifc(ifc) - ); + a_mod #() a_mod_0 (.ifc(ifc)); - localparam b_pkg::cfg_t cfg_b = '{ - a:$bits(byte_t) - }; + localparam b_pkg::cfg_t cfg_b = '{a: $bits(byte_t)}; initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_param_from_port.v b/test_regress/t/t_paramgraph_iface_param_from_port.v index a6f664b38..c5728ca6d 100644 --- a/test_regress/t/t_paramgraph_iface_param_from_port.v +++ b/test_regress/t/t_paramgraph_iface_param_from_port.v @@ -20,19 +20,27 @@ package cfg_pkg; } cfg_t; endpackage -interface types_if #(parameter cfg_pkg::cfg_t cfg = '0)(); +interface types_if #( + parameter cfg_pkg::cfg_t cfg = '0 +) (); typedef logic [cfg.DataWidth-1:0] data_t; typedef logic [cfg.IdWidth-1:0] id_t; endinterface -interface bus_if #(parameter cfg_pkg::cfg_t cfg = '0)(); - types_if #(cfg) types(); +interface bus_if #( + parameter cfg_pkg::cfg_t cfg = '0 +) (); + types_if #(cfg) types (); typedef types.data_t data_t; typedef types.id_t id_t; endinterface -module child(bus_if io, output int data_w, output int id_w); - types_if #(io.cfg) port_types(); +module child ( + bus_if io, + output int data_w, + output int id_w +); + types_if #(io.cfg) port_types (); typedef port_types.data_t p_data_t; typedef port_types.id_t p_id_t; assign data_w = $bits(p_data_t); @@ -40,19 +48,27 @@ module child(bus_if io, output int data_w, output int id_w); endmodule module top; - localparam cfg_pkg::cfg_t cfg0 = '{DataWidth:32, IdWidth:4}; - localparam cfg_pkg::cfg_t cfg1 = '{DataWidth:64, IdWidth:6}; + localparam cfg_pkg::cfg_t cfg0 = '{DataWidth: 32, IdWidth: 4}; + localparam cfg_pkg::cfg_t cfg1 = '{DataWidth: 64, IdWidth: 6}; - bus_if #(cfg0) bus0(); - bus_if #(cfg1) bus1(); + bus_if #(cfg0) bus0 (); + bus_if #(cfg1) bus1 (); int data_w0; int id_w0; int data_w1; int id_w1; - child u0(.io(bus0), .data_w(data_w0), .id_w(id_w0)); - child u1(.io(bus1), .data_w(data_w1), .id_w(id_w1)); + child u0 ( + .io(bus0), + .data_w(data_w0), + .id_w(id_w0) + ); + child u1 ( + .io(bus1), + .data_w(data_w1), + .id_w(id_w1) + ); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_pin.v b/test_regress/t/t_paramgraph_iface_pin.v index 7d1c3d6ab..94d4fe2ed 100644 --- a/test_regress/t/t_paramgraph_iface_pin.v +++ b/test_regress/t/t_paramgraph_iface_pin.v @@ -11,12 +11,12 @@ // verilog_format: on package a_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface depgraph_if #(a_pkg::cfg_t cfg=0)(); +interface depgraph_if #( + a_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; typedef logic [2*cfg.a-1:0] half_t; typedef struct packed { @@ -25,8 +25,8 @@ interface depgraph_if #(a_pkg::cfg_t cfg=0)(); } pair_t; endinterface -module a_mod( - depgraph_if ifc +module a_mod ( + depgraph_if ifc ); typedef ifc.byte_t byte_t; typedef ifc.pair_t pair_t; @@ -39,20 +39,16 @@ module a_mod( initial begin #1; `checkd($bits(byte_t), 8); - `checkd($bits(pair_t),24); + `checkd($bits(pair_t), 24); `checkd($bits(flat), 24); end endmodule -module t(); - localparam a_pkg::cfg_t cfg = '{ - a:8 - }; +module t; + localparam a_pkg::cfg_t cfg = '{a: 8}; - depgraph_if #(cfg) ifc(); - a_mod #() a_mod_0( - .ifc(ifc) - ); + depgraph_if #(cfg) ifc (); + a_mod #() a_mod_0 (.ifc(ifc)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_iface_port_typedef.v b/test_regress/t/t_paramgraph_iface_port_typedef.v index 99d9050e8..34f1567f4 100644 --- a/test_regress/t/t_paramgraph_iface_port_typedef.v +++ b/test_regress/t/t_paramgraph_iface_port_typedef.v @@ -15,33 +15,42 @@ // verilog_format: on package acme_pkg; - typedef struct packed { - int DataBits; - } cfg_t; + typedef struct packed {int DataBits;} cfg_t; endpackage -interface acme_if #(parameter acme_pkg::cfg_t cfg = '0)(); +interface acme_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); typedef logic [cfg.DataBits-1:0] data_t; endinterface -module child(acme_if io, output int width_o); +module child ( + acme_if io, + output int width_o +); typedef io.data_t data_t; data_t payload; assign width_o = $bits(data_t); endmodule module top; - localparam acme_pkg::cfg_t cfg0 = '{DataBits:32}; - localparam acme_pkg::cfg_t cfg1 = '{DataBits:64}; + localparam acme_pkg::cfg_t cfg0 = '{DataBits: 32}; + localparam acme_pkg::cfg_t cfg1 = '{DataBits: 64}; - acme_if #(cfg0) io0(); - acme_if #(cfg1) io1(); + acme_if #(cfg0) io0 (); + acme_if #(cfg1) io1 (); int width0; int width1; - child u0(.io(io0), .width_o(width0)); - child u1(.io(io1), .width_o(width1)); + child u0 ( + .io(io0), + .width_o(width0) + ); + child u1 ( + .io(io1), + .width_o(width1) + ); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch.v b/test_regress/t/t_paramgraph_iface_template_mismatch.v index 92e39e58a..6c3ef397c 100644 --- a/test_regress/t/t_paramgraph_iface_template_mismatch.v +++ b/test_regress/t/t_paramgraph_iface_template_mismatch.v @@ -22,15 +22,17 @@ package axi4l; } cfg_t; endpackage -interface axi4l_if #(parameter axi4l::cfg_t cfg = '0)(); +interface axi4l_if #( + parameter axi4l::cfg_t cfg = '0 +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.DataBits/8-1:0] strb_t; typedef logic [cfg.UserBits-1:0] user_t; endinterface -module ccom_to_axi( - axi4l_if axil_tgt_io +module ccom_to_axi ( + axi4l_if axil_tgt_io ); typedef axil_tgt_io.addr_t addr_t; typedef axil_tgt_io.data_t data_t; @@ -41,21 +43,23 @@ module ccom_to_axi( strb_t strb_q; endmodule -module dummy_consumer(axi4l_if axil_io); +module dummy_consumer ( + axi4l_if axil_io +); typedef axil_io.data_t data_t; data_t sink; endmodule module top; - localparam axi4l::cfg_t cfg = '{AddrBits:32, DataBits:64, UserBits:2}; + localparam axi4l::cfg_t cfg = '{AddrBits: 32, DataBits: 64, UserBits: 2}; // Live specialized instance used elsewhere. - axi4l_if #(.cfg(cfg)) axil_live(); - dummy_consumer u_consume(.axil_io(axil_live)); + axi4l_if #(.cfg(cfg)) axil_live (); + dummy_consumer u_consume (.axil_io(axil_live)); // Template/default instance used in ccom_to_axi. - axi4l_if #(cfg) axil_tgt_io(); - ccom_to_axi u_ccom_to_axi(.axil_tgt_io(axil_tgt_io)); + axi4l_if #(cfg) axil_tgt_io (); + ccom_to_axi u_ccom_to_axi (.axil_tgt_io(axil_tgt_io)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch2.v b/test_regress/t/t_paramgraph_iface_template_mismatch2.v index 394354d4a..8b7f08fe1 100644 --- a/test_regress/t/t_paramgraph_iface_template_mismatch2.v +++ b/test_regress/t/t_paramgraph_iface_template_mismatch2.v @@ -22,15 +22,17 @@ package axi4l; } cfg_t; endpackage -interface axi4l_if #(parameter axi4l::cfg_t cfg = '{AddrBits:4, DataBits:16, UserBits:1})(); +interface axi4l_if #( + parameter axi4l::cfg_t cfg = '{AddrBits: 4, DataBits: 16, UserBits: 1} +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.DataBits/8-1:0] strb_t; typedef logic [cfg.UserBits-1:0] user_t; endinterface -module ccom_to_axi( - axi4l_if axil_tgt_io +module ccom_to_axi ( + axi4l_if axil_tgt_io ); typedef axil_tgt_io.addr_t addr_t; typedef axil_tgt_io.data_t data_t; @@ -41,21 +43,23 @@ module ccom_to_axi( strb_t strb_q; endmodule -module dummy_consumer(axi4l_if axil_io); +module dummy_consumer ( + axi4l_if axil_io +); typedef axil_io.data_t data_t; data_t sink; endmodule module top; - localparam axi4l::cfg_t cfg = '{AddrBits:32, DataBits:64, UserBits:2}; + localparam axi4l::cfg_t cfg = '{AddrBits: 32, DataBits: 64, UserBits: 2}; // Live specialized instance used elsewhere. - axi4l_if #(.cfg(cfg)) axil_live(); - dummy_consumer u_consume(.axil_io(axil_live)); + axi4l_if #(.cfg(cfg)) axil_live (); + dummy_consumer u_consume (.axil_io(axil_live)); // Template/default instance used in ccom_to_axi. - axi4l_if #(cfg) axil_tgt_io(); - ccom_to_axi u_ccom_to_axi(.axil_tgt_io(axil_tgt_io)); + axi4l_if #(cfg) axil_tgt_io (); + ccom_to_axi u_ccom_to_axi (.axil_tgt_io(axil_tgt_io)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_template_mismatch3.v b/test_regress/t/t_paramgraph_iface_template_mismatch3.v index 2ab9ca006..44fd55937 100644 --- a/test_regress/t/t_paramgraph_iface_template_mismatch3.v +++ b/test_regress/t/t_paramgraph_iface_template_mismatch3.v @@ -15,40 +15,42 @@ // verilog_format: on package axi4l; - typedef struct packed { - int DataBits; - } cfg_t; + typedef struct packed {int DataBits;} cfg_t; endpackage -interface axi4l_if #(parameter axi4l::cfg_t cfg = '0)(); +interface axi4l_if #( + parameter axi4l::cfg_t cfg = '0 +) (); typedef logic [cfg.DataBits-1:0] data_t; endinterface -module ccom_to_axi( - axi4l_if axil_tgt_io +module ccom_to_axi ( + axi4l_if axil_tgt_io ); typedef axil_tgt_io.data_t data_t; data_t data_q; endmodule -module dummy_consumer(axi4l_if axil_io); +module dummy_consumer ( + axi4l_if axil_io +); typedef axil_io.data_t data_t; data_t sink; endmodule module top; localparam axi4l::cfg_t cfg = '{ - DataBits:64//, + DataBits: 64 //, }; // Live specialized instance used elsewhere. - axi4l_if #(.cfg(cfg)) axil_live(); - dummy_consumer u_consume(.axil_io(axil_live)); + axi4l_if #(.cfg(cfg)) axil_live (); + dummy_consumer u_consume (.axil_io(axil_live)); // Template/default instance used in ccom_to_axi. - axi4l_if #(cfg) axil_tgt_io(); - ccom_to_axi u_ccom_to_axi(.axil_tgt_io(axil_tgt_io)); + axi4l_if #(cfg) axil_tgt_io (); + ccom_to_axi u_ccom_to_axi (.axil_tgt_io(axil_tgt_io)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_iface_template_nested.v b/test_regress/t/t_paramgraph_iface_template_nested.v index ea2c99090..eca496bc9 100644 --- a/test_regress/t/t_paramgraph_iface_template_nested.v +++ b/test_regress/t/t_paramgraph_iface_template_nested.v @@ -15,52 +15,56 @@ // verilog_format: on package acme_pkg; - typedef struct packed { - int DataBits; - } cfg_t; + typedef struct packed {int DataBits;} cfg_t; endpackage -interface acme_types_if #(parameter acme_pkg::cfg_t cfg = '0)(); +interface acme_types_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); typedef logic [cfg.DataBits-1:0] data_t; endinterface -interface acme_tb_if #(parameter acme_pkg::cfg_t cfg = '0)(); - acme_types_if #(cfg) acme_types(); +interface acme_tb_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); + acme_types_if #(cfg) acme_types (); typedef acme_types.data_t data_t; data_t payload; endinterface -interface acme_if #(parameter acme_pkg::cfg_t cfg = '0)(); - acme_tb_if #(cfg) rq_tb_io_i(); - acme_types_if #(cfg) acme_types(); +interface acme_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); + acme_tb_if #(cfg) rq_tb_io_i (); + acme_types_if #(cfg) acme_types (); typedef acme_types.data_t data_t; data_t passthru; endinterface -interface acme_wrap_if #(parameter acme_pkg::cfg_t cfg = '0)(); - acme_if #(cfg) acme_io(); +interface acme_wrap_if #( + parameter acme_pkg::cfg_t cfg = '0 +) (); + acme_if #(cfg) acme_io (); typedef acme_io.data_t data_t; data_t leaf; endinterface -module consumer(acme_wrap_if wrap_io); +module consumer ( + acme_wrap_if wrap_io +); typedef wrap_io.data_t data_t; data_t sink; endmodule module top; - localparam acme_pkg::cfg_t cfg0 = '{ - DataBits:64 - }; - localparam acme_pkg::cfg_t cfg1 = '{ - DataBits:128 - }; + localparam acme_pkg::cfg_t cfg0 = '{DataBits: 64}; + localparam acme_pkg::cfg_t cfg1 = '{DataBits: 128}; - acme_wrap_if #(cfg0) wrap0(); - acme_wrap_if #(cfg1) wrap1(); + acme_wrap_if #(cfg0) wrap0 (); + acme_wrap_if #(cfg1) wrap1 (); - consumer u_consume0(.wrap_io(wrap0)); - consumer u_consume1(.wrap_io(wrap1)); + consumer u_consume0 (.wrap_io(wrap0)); + consumer u_consume1 (.wrap_io(wrap1)); initial begin #1; diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v index 3ca551d2b..e9c5a2207 100644 --- a/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_chain.v @@ -14,7 +14,7 @@ interface depgraph_if; endinterface module t_paramgraph_member_refdtype_iface_chain; - depgraph_if ifc(); + depgraph_if ifc (); typedef ifc.byte_t byte_t; typedef byte_t byte_t2; diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v index f38a8a755..71c037c2c 100644 --- a/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_struct.v @@ -19,7 +19,7 @@ interface depgraph_if; endinterface module t_paramgraph_member_refdtype_iface_struct; - depgraph_if ifc(); + depgraph_if ifc (); typedef ifc.byte_t byte_t; typedef ifc.pair_t pair_t; diff --git a/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v index dfd79a819..4e375c90b 100644 --- a/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v +++ b/test_regress/t/t_paramgraph_member_refdtype_iface_typedef.v @@ -15,7 +15,7 @@ interface depgraph_if; endinterface module t_paramgraph_member_refdtype_iface_typedef; - depgraph_if ifc(); + depgraph_if ifc (); typedef ifc.byte_t byte_t; typedef struct packed { diff --git a/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v index 8297b7179..4b291cba9 100644 --- a/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v +++ b/test_regress/t/t_paramgraph_member_refdtype_pkg_iface.v @@ -11,12 +11,12 @@ // verilog_format: on package paramgraph_pkg; - typedef struct packed { - int unsigned a; - } cfg_t; + typedef struct packed {int unsigned a;} cfg_t; endpackage -interface paramgraph_if #(paramgraph_pkg::cfg_t cfg=0)(); +interface paramgraph_if #( + paramgraph_pkg::cfg_t cfg = 0 +) (); typedef logic [cfg.a-1:0] byte_t; typedef struct packed { byte_t a; @@ -25,11 +25,9 @@ interface paramgraph_if #(paramgraph_pkg::cfg_t cfg=0)(); endinterface module t_paramgraph_member_refdtype_pkg_iface; - localparam paramgraph_pkg::cfg_t cfg = '{ - a: 8 - }; + localparam paramgraph_pkg::cfg_t cfg = '{a: 8}; - paramgraph_if #(cfg) ifc(); + paramgraph_if #(cfg) ifc (); typedef ifc.byte_t byte_t; typedef ifc.pair_t pair_t; diff --git a/test_regress/t/t_paramgraph_minimal_sibling.v b/test_regress/t/t_paramgraph_minimal_sibling.v index e3d8cd042..87df13b20 100644 --- a/test_regress/t/t_paramgraph_minimal_sibling.v +++ b/test_regress/t/t_paramgraph_minimal_sibling.v @@ -12,19 +12,25 @@ // `define stop $stop -`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define checkd(gotv, + expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); // Parameterized interface with a typedef that depends on the parameter -interface a_if #(parameter int WIDTH = 8)(); - localparam LP_WIDTH = WIDTH*2; +interface a_if #( + parameter int WIDTH = 8 +) (); + localparam LP_WIDTH = WIDTH * 2; typedef logic [LP_WIDTH-1:0] data_t; data_t data; endinterface // Wrapper interface with TWO SIBLING instances of a_if with DIFFERENT widths -interface wrapper_if #(parameter int WIDTH_A = 8, parameter int WIDTH_B = 16)(); - a_if #(.WIDTH(WIDTH_A)) a_inst(); - a_if #(.WIDTH(WIDTH_B)) b_inst(); +interface wrapper_if #( + parameter int WIDTH_A = 8, + parameter int WIDTH_B = 16 +) (); + a_if #(.WIDTH(WIDTH_A)) a_inst (); + a_if #(.WIDTH(WIDTH_B)) b_inst (); // Re-export typedefs from each sibling typedef a_inst.data_t a_data_t; @@ -33,7 +39,7 @@ endinterface // Module that accesses typedefs from BOTH siblings via interface port module consumer ( - wrapper_if wif + wrapper_if wif ); // These MUST resolve to DIFFERENT types typedef wif.a_inst.data_t local_a_t; // Should be 10 bits @@ -50,9 +56,12 @@ module consumer ( endmodule // Top module -module t(); - wrapper_if #(.WIDTH_A(10), .WIDTH_B(20)) wif(); - consumer c(.wif(wif)); +module t; + wrapper_if #( + .WIDTH_A(10), + .WIDTH_B(20) + ) wif (); + consumer c (.wif(wif)); initial begin #2; diff --git a/test_regress/t/t_paramgraph_nested_iface_typedef.v b/test_regress/t/t_paramgraph_nested_iface_typedef.v index 77cf1ca1b..afe12a800 100644 --- a/test_regress/t/t_paramgraph_nested_iface_typedef.v +++ b/test_regress/t/t_paramgraph_nested_iface_typedef.v @@ -24,7 +24,9 @@ typedef struct packed { } axi_cfg_t; // Innermost interface - like axi4_if.sv in the real design -interface axi4_if #(parameter axi_cfg_t cfg = '{32, 64, 4, 0})(); +interface axi4_if #( + parameter axi_cfg_t cfg = '{32, 64, 4, 0} +) (); typedef logic [cfg.AddrBits-1:0] addr_t; typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.IdBits-1:0] id_t; @@ -33,25 +35,27 @@ interface axi4_if #(parameter axi_cfg_t cfg = '{32, 64, 4, 0})(); // AXI channel typedef typedef struct packed { - id_t id; - addr_t addr; + id_t id; + addr_t addr; logic [7:0] len; } ar_chan_t; typedef struct packed { - id_t id; - data_t data; + id_t id; + data_t data; logic [1:0] resp; - logic last; + logic last; } r_chan_t; ar_chan_t ar; - r_chan_t r; + r_chan_t r; endinterface // Middle interface - wraps the AXI interface -interface tlb_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); - axi4_if #(.cfg(axi_cfg)) axi_tlb_io(); +interface tlb_io_if #( + parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0} +) (); + axi4_if #(.cfg(axi_cfg)) axi_tlb_io (); // Capture typedef from nested interface typedef axi_tlb_io.r_chan_t r_chan_t; @@ -59,8 +63,10 @@ interface tlb_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); endinterface // Outer interface - contains the middle interface -interface cca_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); - tlb_io_if #(.axi_cfg(axi_cfg)) tlb_io(); +interface cca_io_if #( + parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0} +) (); + tlb_io_if #(.axi_cfg(axi_cfg)) tlb_io (); // Capture typedef from doubly-nested interface typedef tlb_io.r_chan_t r_chan_t; @@ -68,8 +74,10 @@ interface cca_io_if #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})(); endinterface // Module that uses the doubly-nested typedef - this is where the error occurred -module cca_xbar #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})( - cca_io_if cca_io +module cca_xbar #( + parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0} +) ( + cca_io_if cca_io ); // This line was causing "Internal Error: Unlinked" before the fix // because cca_io.tlb_io.r_chan_t references a typedef from a nested interface @@ -92,17 +100,17 @@ module cca_xbar #(parameter axi_cfg_t axi_cfg = '{32, 64, 4, 0})( end endmodule -module t(); +module t; localparam axi_cfg_t cfg1 = '{AddrBits: 32, DataBits: 64, IdBits: 4, UserBits: 2}; localparam axi_cfg_t cfg2 = '{AddrBits: 40, DataBits: 128, IdBits: 8, UserBits: 4}; // Instantiate outer interface - cca_io_if #(.axi_cfg(cfg1)) cca_io1(); - cca_io_if #(.axi_cfg(cfg2)) cca_io2(); + cca_io_if #(.axi_cfg(cfg1)) cca_io1 (); + cca_io_if #(.axi_cfg(cfg2)) cca_io2 (); // Instantiate modules that use doubly-nested typedefs - cca_xbar #(.axi_cfg(cfg1)) xbar1(.cca_io(cca_io1)); - cca_xbar #(.axi_cfg(cfg2)) xbar2(.cca_io(cca_io2)); + cca_xbar #(.axi_cfg(cfg1)) xbar1 (.cca_io(cca_io1)); + cca_xbar #(.axi_cfg(cfg2)) xbar2 (.cca_io(cca_io2)); // Also test direct typedef access in top module typedef cca_io1.tlb_io.r_chan_t top_r_chan_t; diff --git a/test_regress/t/t_paramgraph_param_not_const.v b/test_regress/t/t_paramgraph_param_not_const.v index 51569f711..83cd922bb 100644 --- a/test_regress/t/t_paramgraph_param_not_const.v +++ b/test_regress/t/t_paramgraph_param_not_const.v @@ -32,7 +32,9 @@ package a_pkg; } cfg_t; endpackage -interface other_types_if #(parameter a_pkg::cfg_t cfg=0)(); +interface other_types_if #( + parameter a_pkg::cfg_t cfg = 0 +) (); // Create a struct that results in 525 bits typedef struct packed { logic [cfg.p_a-1:0] field1; @@ -42,7 +44,9 @@ interface other_types_if #(parameter a_pkg::cfg_t cfg=0)(); endinterface // Simple interface that takes a parameter -interface simple_if #(parameter cb::cfg_t cfg=0)(); +interface simple_if #( + parameter cb::cfg_t cfg = 0 +) (); logic [cfg.Rids-1:0] rids; logic [cfg.Pids-1:0] pids; logic [cfg.Fnum-1:0] fnum; @@ -50,25 +54,22 @@ interface simple_if #(parameter cb::cfg_t cfg=0)(); endinterface module TestMod; - localparam a_pkg::cfg_t ot_cfg = '{ - p_a : 8, - p_b : 4 - }; + localparam a_pkg::cfg_t ot_cfg = '{p_a : 8, p_b : 4}; - other_types_if #(ot_cfg) other_types(); + other_types_if #(ot_cfg) other_types (); typedef other_types.cmd_beat_t cmd_beat_t; // This pattern assignment should work correctly localparam cb::cfg_t cb_cfg = '{ - Rids : 32'h1, - Pids : 32'h2, - Fnum : 32'h3, - XdatSize : $bits(cmd_beat_t) + Rids : 32'h1, + Pids : 32'h2, + Fnum : 32'h3, + XdatSize : $bits(cmd_beat_t) }; // This should trigger the error - cb_cfg is not recognized as constant - simple_if#(cb_cfg) cb_vc0_io(); + simple_if #(cb_cfg) cb_vc0_io (); initial begin `checkd(cb_cfg.XdatSize, 12); diff --git a/test_regress/t/t_paramgraph_paramtype_default.v b/test_regress/t/t_paramgraph_paramtype_default.v index 8e4bf9ec5..bb4842e49 100644 --- a/test_regress/t/t_paramgraph_paramtype_default.v +++ b/test_regress/t/t_paramgraph_paramtype_default.v @@ -12,17 +12,20 @@ // // Simple type flop - parameterized by type T with default = logic -module tflop #(parameter type T = logic) ( - input logic clk, - input logic reset, - input T reset_strap_i, - output T q_o, - input T d_i +module tflop #( + parameter type T = logic +) ( + input logic clk, + input logic reset, + input T reset_strap_i, + output T q_o, + input T d_i ); always_ff @(posedge clk) begin if (reset) begin q_o <= reset_strap_i; - end else begin + end + else begin q_o <= d_i; end end @@ -30,19 +33,19 @@ endmodule // Module that uses tflop with DEFAULT type parameter (T = logic) module user_mod ( - input logic clk, - input logic reset + input logic clk, + input logic reset ); logic d_in, d_out; // Use tflop with default type parameter T = logic // This should NOT create a specialized clone - it reuses the template tflop vld_reg ( - .clk(clk), - .reset(reset), - .reset_strap_i(1'b0), - .q_o(d_out), - .d_i(d_in) + .clk(clk), + .reset(reset), + .reset_strap_i(1'b0), + .q_o(d_out), + .d_i(d_in) ); initial begin @@ -58,7 +61,10 @@ module t; logic clk = 0; logic reset = 1; - user_mod uut (.clk(clk), .reset(reset)); + user_mod uut ( + .clk(clk), + .reset(reset) + ); initial begin #5 reset = 0; diff --git a/test_regress/t/t_paramgraph_refdtype_iface.v b/test_regress/t/t_paramgraph_refdtype_iface.v index 0577c5b43..753988a41 100644 --- a/test_regress/t/t_paramgraph_refdtype_iface.v +++ b/test_regress/t/t_paramgraph_refdtype_iface.v @@ -19,7 +19,7 @@ interface depgraph_if; endinterface module depgraph_top; - depgraph_if ifc(); + depgraph_if ifc (); typedef ifc.nibble_t nibble_t; diff --git a/test_regress/t/t_paramgraph_refdtype_unlinked.v b/test_regress/t/t_paramgraph_refdtype_unlinked.v index b490eaa41..2056b5a01 100644 --- a/test_regress/t/t_paramgraph_refdtype_unlinked.v +++ b/test_regress/t/t_paramgraph_refdtype_unlinked.v @@ -18,7 +18,9 @@ package Include; typedef logic [11:0] mbox_addr_t; endpackage -interface mbox_if #(parameter int WIDTH = 0); +interface mbox_if #( + parameter int WIDTH = 0 +); typedef Include::mbox_addr_t mbox_addr_t; typedef struct packed { @@ -27,8 +29,10 @@ interface mbox_if #(parameter int WIDTH = 0); } RFTag; endinterface -module mbox #(parameter int WIDTH = 0); - mbox_if #(WIDTH) if_inst(); +module mbox #( + parameter int WIDTH = 0 +); + mbox_if #(WIDTH) if_inst (); // This should reproduce the REFDTYPE UNLINKED error // Using a type cast of an interface typedef in a parameter @@ -42,5 +46,5 @@ module mbox #(parameter int WIDTH = 0); endmodule module top; - mbox #(.WIDTH(14)) u_mbox(); + mbox #(.WIDTH(14)) u_mbox (); endmodule diff --git a/test_regress/t/t_paramgraph_selbit_dtype.v b/test_regress/t/t_paramgraph_selbit_dtype.v index 971a172ea..d47b5606f 100644 --- a/test_regress/t/t_paramgraph_selbit_dtype.v +++ b/test_regress/t/t_paramgraph_selbit_dtype.v @@ -12,13 +12,13 @@ // Spill register with type parameter (simplified from spill_register_flushable) module spill_register #( - parameter type T = logic + parameter type T = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic sel_i, - input T data_i, - output T data_o + input logic clk_i, + input logic rst_ni, + input logic sel_i, + input T data_i, + output T data_o ); // Two registers of type T T a_data_q; @@ -26,15 +26,16 @@ module spill_register #( logic b_full_q; always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - a_data_q <= '0; - b_data_q <= '0; - b_full_q <= 1'b0; - end else begin - a_data_q <= data_i; - b_data_q <= a_data_q; - b_full_q <= sel_i; - end + if (!rst_ni) begin + a_data_q <= '0; + b_data_q <= '0; + b_full_q <= 1'b0; + end + else begin + a_data_q <= data_i; + b_data_q <= a_data_q; + b_full_q <= sel_i; + end end // This is the problematic line - ternary expression with type parameter variables @@ -44,41 +45,45 @@ endmodule // Wrapper module that passes type parameter through (like spill_register_flushable wrapper) module spill_wrapper #( - parameter type T = logic + parameter type T = logic ) ( - input logic clk_i, - input logic rst_ni, - input logic sel_i, - input T data_i, - output T data_o + input logic clk_i, + input logic rst_ni, + input logic sel_i, + input T data_i, + output T data_o ); // Instantiate spill_register with the same type parameter - spill_register #(.T(T)) i_spill ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .sel_i(sel_i), - .data_i(data_i), - .data_o(data_o) + spill_register #( + .T(T) + ) i_spill ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .sel_i(sel_i), + .data_i(data_i), + .data_o(data_o) ); endmodule // Another level of nesting (like axi_demux) module demux #( - parameter type T = logic + parameter type T = logic ) ( - input logic clk_i, - input logic rst_ni + input logic clk_i, + input logic rst_ni ); logic sel; T data_in; T data_out; - spill_wrapper #(.T(T)) i_spill_wrapper ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .sel_i(sel), - .data_i(data_in), - .data_o(data_out) + spill_wrapper #( + .T(T) + ) i_spill_wrapper ( + .clk_i(clk_i), + .rst_ni(rst_ni), + .sel_i(sel), + .data_i(data_in), + .data_o(data_out) ); endmodule @@ -87,9 +92,11 @@ module top; logic rst_n; // Instantiate with default T (logic) - demux #(.T(logic)) u_demux ( - .clk_i(clk), - .rst_ni(rst_n) + demux #( + .T(logic) + ) u_demux ( + .clk_i(clk), + .rst_ni(rst_n) ); initial begin diff --git a/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v b/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v index 8e9d7d6a3..bb44797d9 100644 --- a/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v +++ b/test_regress/t/t_paramgraph_simple_cache_localparam_cfg.v @@ -27,8 +27,8 @@ package cache_pkg; endpackage interface cache_types_if #( - parameter cache_pkg::cfg_t cfg = '0 -)(); + parameter cache_pkg::cfg_t cfg = '0 +) (); localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); @@ -41,14 +41,18 @@ interface cache_types_if #( endinterface interface cache_if #( - parameter cache_pkg::cfg_t cfg = '0 -)(); - cache_types_if #(cfg) types(); + parameter cache_pkg::cfg_t cfg = '0 +) (); + cache_types_if #(cfg) types (); typedef types.tag_t tag_t; typedef types.drow_addr_t drow_addr_t; endinterface -module cache_leaf(cache_if io, output int tag_bits_o, output int drow_bits_o); +module cache_leaf ( + cache_if io, + output int tag_bits_o, + output int drow_bits_o +); typedef io.tag_t tag_t; typedef io.drow_addr_t drow_addr_t; assign tag_bits_o = $bits(tag_t); @@ -56,31 +60,48 @@ module cache_leaf(cache_if io, output int tag_bits_o, output int drow_bits_o); endmodule module cache_wrap #( - parameter cache_pkg::cfg_t cfg = '0 -)(output int tag_bits_o, output int drow_bits_o); + parameter cache_pkg::cfg_t cfg = '0 +) ( + output int tag_bits_o, + output int drow_bits_o +); localparam cache_pkg::cfg_t sc_cfg = '{ - CmdTagBits : $clog2(cfg.Capacity), - Associativity : cfg.Associativity, - Capacity : cfg.Capacity, - LineSize : cfg.LineSize, - AddrBits : cfg.AddrBits, - FgWidth : cfg.FgWidth, - MissQSize : cfg.MissQSize + CmdTagBits : $clog2(cfg.Capacity), + Associativity : cfg.Associativity, + Capacity : cfg.Capacity, + LineSize : cfg.LineSize, + AddrBits : cfg.AddrBits, + FgWidth : cfg.FgWidth, + MissQSize : cfg.MissQSize }; - cache_if #(sc_cfg) sc_io(); + cache_if #(sc_cfg) sc_io (); - cache_leaf u_leaf(.io(sc_io), .tag_bits_o(tag_bits_o), .drow_bits_o(drow_bits_o)); + cache_leaf u_leaf ( + .io(sc_io), + .tag_bits_o(tag_bits_o), + .drow_bits_o(drow_bits_o) + ); endmodule module top; localparam cache_pkg::cfg_t cfg0 = '{ - Capacity:1024, LineSize:64, Associativity:4, AddrBits:32, - FgWidth:32, MissQSize:8, CmdTagBits:0 + Capacity: 1024, + LineSize: 64, + Associativity: 4, + AddrBits: 32, + FgWidth: 32, + MissQSize: 8, + CmdTagBits: 0 }; localparam cache_pkg::cfg_t cfg1 = '{ - Capacity:2048, LineSize:32, Associativity:2, AddrBits:36, - FgWidth:16, MissQSize:16, CmdTagBits:0 + Capacity: 2048, + LineSize: 32, + Associativity: 2, + AddrBits: 36, + FgWidth: 16, + MissQSize: 16, + CmdTagBits: 0 }; int tag_bits0; @@ -88,8 +109,14 @@ module top; int tag_bits1; int drow_bits1; - cache_wrap #(cfg0) wrap0(.tag_bits_o(tag_bits0), .drow_bits_o(drow_bits0)); - cache_wrap #(cfg1) wrap1(.tag_bits_o(tag_bits1), .drow_bits_o(drow_bits1)); + cache_wrap #(cfg0) wrap0 ( + .tag_bits_o(tag_bits0), + .drow_bits_o(drow_bits0) + ); + cache_wrap #(cfg1) wrap1 ( + .tag_bits_o(tag_bits1), + .drow_bits_o(drow_bits1) + ); initial begin #1; diff --git a/test_regress/t/t_paramgraph_simple_cache_types_if.v b/test_regress/t/t_paramgraph_simple_cache_types_if.v index 7dff2292f..2370f4256 100644 --- a/test_regress/t/t_paramgraph_simple_cache_types_if.v +++ b/test_regress/t/t_paramgraph_simple_cache_types_if.v @@ -28,8 +28,8 @@ package sc_pkg; endpackage interface simple_cache_types_if #( - parameter sc_pkg::cfg_t cfg = '0 -)(); + parameter sc_pkg::cfg_t cfg = '0 +) (); localparam int SC_NUM_LINES = cfg.Capacity / cfg.LineSize; localparam int SC_LINES_PER_WAY = SC_NUM_LINES / cfg.Associativity; localparam int SC_BLOCK_BITS = $clog2(cfg.LineSize); @@ -57,7 +57,12 @@ interface simple_cache_types_if #( } sc_tag_addr_t; endinterface -module child(simple_cache_types_if types, output int tag_bits_o, output int tag_addr_bits_o, output int drow_bits_o); +module child ( + simple_cache_types_if types, + output int tag_bits_o, + output int tag_addr_bits_o, + output int drow_bits_o +); typedef types.tag_t tag_t; typedef types.sc_tag_addr_t sc_tag_addr_t; typedef types.drow_addr_t drow_addr_t; @@ -68,16 +73,28 @@ endmodule module top; localparam sc_pkg::cfg_t cfg0 = '{ - Capacity:1024, LineSize:64, Associativity:4, AddrBits:32, - FgWidth:32, StateBits:2, CmdTagBits:5, MissQSize:8 + Capacity: 1024, + LineSize: 64, + Associativity: 4, + AddrBits: 32, + FgWidth: 32, + StateBits: 2, + CmdTagBits: 5, + MissQSize: 8 }; localparam sc_pkg::cfg_t cfg1 = '{ - Capacity:2048, LineSize:32, Associativity:2, AddrBits:36, - FgWidth:16, StateBits:3, CmdTagBits:7, MissQSize:16 + Capacity: 2048, + LineSize: 32, + Associativity: 2, + AddrBits: 36, + FgWidth: 16, + StateBits: 3, + CmdTagBits: 7, + MissQSize: 16 }; - simple_cache_types_if #(cfg0) types0(); - simple_cache_types_if #(cfg1) types1(); + simple_cache_types_if #(cfg0) types0 (); + simple_cache_types_if #(cfg1) types1 (); int tag_bits0; int tag_addr_bits0; @@ -86,10 +103,18 @@ module top; int tag_addr_bits1; int drow_bits1; - child u0(.types(types0), .tag_bits_o(tag_bits0), .tag_addr_bits_o(tag_addr_bits0), - .drow_bits_o(drow_bits0)); - child u1(.types(types1), .tag_bits_o(tag_bits1), .tag_addr_bits_o(tag_addr_bits1), - .drow_bits_o(drow_bits1)); + child u0 ( + .types(types0), + .tag_bits_o(tag_bits0), + .tag_addr_bits_o(tag_addr_bits0), + .drow_bits_o(drow_bits0) + ); + child u1 ( + .types(types1), + .tag_bits_o(tag_bits1), + .tag_addr_bits_o(tag_addr_bits1), + .drow_bits_o(drow_bits1) + ); initial begin #1; diff --git a/test_regress/t/t_pp_lib.v b/test_regress/t/t_pp_lib.v index ff79fa89d..c21188b58 100644 --- a/test_regress/t/t_pp_lib.v +++ b/test_regress/t/t_pp_lib.v @@ -5,7 +5,7 @@ // SPDX-License-Identifier: CC0-1.0 `include "t_pp_lib_inc.vh" -module t(); +module t; wire [`WIDTH-1:0] a; library_cell n1(a); endmodule diff --git a/test_regress/t/t_preproc_str_undef.v b/test_regress/t/t_preproc_str_undef.v index ef072b9b2..5910ed3cb 100644 --- a/test_regress/t/t_preproc_str_undef.v +++ b/test_regress/t/t_preproc_str_undef.v @@ -12,7 +12,7 @@ `define name3(p) ```p``_SUFFIX `define stringify(text) `"text`" -module t(); +module t; initial begin // Another simulator gives: // `PREFIX_my_suffix diff --git a/test_regress/t/t_process_propagation.v b/test_regress/t/t_process_propagation.v index 169649f36..256456a14 100644 --- a/test_regress/t/t_process_propagation.v +++ b/test_regress/t/t_process_propagation.v @@ -33,7 +33,7 @@ class Bar extends Foo; endtask endclass -module t(); +module t; initial begin process p; Foo foo; diff --git a/test_regress/t/t_process_task.v b/test_regress/t/t_process_task.v index 9e7d41ad3..1ba02cf41 100644 --- a/test_regress/t/t_process_task.v +++ b/test_regress/t/t_process_task.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; std::process proc; logic clk = 0; logic b = 0; diff --git a/test_regress/t/t_public_clk.v b/test_regress/t/t_public_clk.v index bef8056e0..cd40d635f 100644 --- a/test_regress/t/t_public_clk.v +++ b/test_regress/t/t_public_clk.v @@ -12,7 +12,7 @@ `define IMPURE_ONE (|($random | $random)) `endif -module t (); +module t; logic clk /* verilator public_flat_rw */; int count; diff --git a/test_regress/t/t_queue_insert_at_end.v b/test_regress/t/t_queue_insert_at_end.v index 9e21d4264..d65582b92 100644 --- a/test_regress/t/t_queue_insert_at_end.v +++ b/test_regress/t/t_queue_insert_at_end.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Antmicro Ltd // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; initial begin int queue[$]; diff --git a/test_regress/t/t_randomize_std_static.v b/test_regress/t/t_randomize_std_static.v index 7d56ac592..5077fa4cf 100644 --- a/test_regress/t/t_randomize_std_static.v +++ b/test_regress/t/t_randomize_std_static.v @@ -34,9 +34,7 @@ module t; static function instr_name_t get_rand_instr(); instr_name_t name; int ok; - ok = std::randomize(name) with { - name inside {allowed_instrs}; - }; + ok = std::randomize(name) with {name inside {allowed_instrs};}; `checkd(ok, 1); return name; endfunction @@ -49,8 +47,9 @@ module t; repeat (20) begin result = instr_base::get_rand_instr(); - `checkd(result == INSTR_ADD || result == INSTR_SUB - || result == INSTR_MUL || result == INSTR_AND, 1); + `checkd( + result == INSTR_ADD || result == INSTR_SUB || result == INSTR_MUL || result == INSTR_AND, + 1); end $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_real_param.v b/test_regress/t/t_real_param.v index 8927b2436..0f86b3b3b 100644 --- a/test_regress/t/t_real_param.v +++ b/test_regress/t/t_real_param.v @@ -9,7 +9,7 @@ module foo (); endmodule -module t(); +module t; genvar m, r; generate for (m = 10; m <= 20; m+=10) begin : gen_m diff --git a/test_regress/t/t_recursive_typedef_bad.v b/test_regress/t/t_recursive_typedef_bad.v index 35811eedc..4b9f08023 100644 --- a/test_regress/t/t_recursive_typedef_bad.v +++ b/test_regress/t/t_recursive_typedef_bad.v @@ -18,7 +18,7 @@ module circ #( assign bo = ai; endmodule -module t (); +module t; logic [7:0] x, y; circ u_circ ( .ai(x), diff --git a/test_regress/t/t_select_bound3.v b/test_regress/t/t_select_bound3.v index 6cb8f05ad..8793aaa29 100644 --- a/test_regress/t/t_select_bound3.v +++ b/test_regress/t/t_select_bound3.v @@ -10,7 +10,7 @@ class cls; int m_field; endclass -module t(); +module t; cls inst[2]; initial begin diff --git a/test_regress/t/t_selrange_iface_type_param.v b/test_regress/t/t_selrange_iface_type_param.v index b9fd18340..a65dcb05b 100644 --- a/test_regress/t/t_selrange_iface_type_param.v +++ b/test_regress/t/t_selrange_iface_type_param.v @@ -30,13 +30,15 @@ package cfg_pkg; endpackage // Parameterized interface (like axi4_if) -interface my_if #(parameter cfg_pkg::cfg_t cfg = 0); - typedef logic [cfg.IdBits-1:0] id_t; - typedef logic [cfg.DataBits-1:0] data_t; +interface my_if #( + parameter cfg_pkg::cfg_t cfg = 0 +); + typedef logic [cfg.IdBits-1:0] id_t; + typedef logic [cfg.DataBits-1:0] data_t; typedef logic [cfg.DataBits/8-1:0] strb_t; typedef struct packed { - id_t id; + id_t id; data_t data; logic [7:0] len; logic [2:0] size; @@ -46,16 +48,16 @@ interface my_if #(parameter cfg_pkg::cfg_t cfg = 0); typedef struct packed { data_t data; strb_t strb; - logic last; + logic last; } w_chan_t; typedef struct packed { - id_t id; + id_t id; logic [1:0] resp; } b_chan_t; typedef struct packed { - id_t id; + id_t id; data_t data; logic [7:0] len; logic [2:0] size; @@ -63,33 +65,33 @@ interface my_if #(parameter cfg_pkg::cfg_t cfg = 0); } ar_chan_t; typedef struct packed { - id_t id; - data_t data; + id_t id; + data_t data; logic [1:0] resp; - logic last; + logic last; } r_chan_t; typedef struct packed { aw_chan_t aw; - logic aw_valid; - w_chan_t w; - logic w_valid; - logic b_ready; + logic aw_valid; + w_chan_t w; + logic w_valid; + logic b_ready; ar_chan_t ar; - logic ar_valid; - logic r_ready; + logic ar_valid; + logic r_ready; } req_t; typedef struct packed { - logic aw_ready; - logic w_ready; - b_chan_t b; - logic b_valid; - r_chan_t r; - logic r_valid; + logic aw_ready; + logic w_ready; + b_chan_t b; + logic b_valid; + r_chan_t r; + logic r_valid; } resp_t; - req_t req; + req_t req; resp_t resp; modport target(input req, output resp); @@ -100,17 +102,17 @@ endinterface // Leaf: axi_demux_simple skeleton //====================================================================== module axi_demux_simple #( - parameter int unsigned AxiIdWidth = 32'd0, - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic, - parameter int unsigned AxiLookBits = 32'd3 -)( - input logic clk_i, - input logic rst_ni, - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, - output logic [AxiLookBits-1:0] id_out, - output int unsigned req_bits_out + parameter int unsigned AxiIdWidth = 32'd0, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter int unsigned AxiLookBits = 32'd3 +) ( + input logic clk_i, + input logic rst_ni, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + output logic [AxiLookBits-1:0] id_out, + output int unsigned req_bits_out ); // Extract ID from nested struct - triggers SELRANGE if axi_req_t // is from wrong interface clone (id field narrower than AxiLookBits) @@ -124,37 +126,37 @@ endmodule // axi_demux skeleton //====================================================================== module axi_demux #( - parameter int unsigned AxiIdWidth = 32'd0, - parameter type aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type r_chan_t = logic, - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic, - parameter int unsigned NoMstPorts = 32'd0, - parameter int unsigned MaxTrans = 32'd8, - parameter int unsigned AxiLookBits = 32'd3 -)( - input logic clk_i, - input logic rst_ni, - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, - output logic [AxiLookBits-1:0] id_out, - output int unsigned req_bits_out + parameter int unsigned AxiIdWidth = 32'd0, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic, + parameter int unsigned NoMstPorts = 32'd0, + parameter int unsigned MaxTrans = 32'd8, + parameter int unsigned AxiLookBits = 32'd3 +) ( + input logic clk_i, + input logic rst_ni, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + output logic [AxiLookBits-1:0] id_out, + output int unsigned req_bits_out ); axi_demux_simple #( - .AxiIdWidth ( AxiIdWidth ), - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), - .AxiLookBits ( AxiLookBits ) + .AxiIdWidth(AxiIdWidth), + .axi_req_t(axi_req_t), + .axi_resp_t(axi_resp_t), + .AxiLookBits(AxiLookBits) ) i_demux_simple ( - .clk_i, - .rst_ni, - .slv_req_i, - .slv_resp_o, - .id_out, - .req_bits_out + .clk_i, + .rst_ni, + .slv_req_i, + .slv_resp_o, + .id_out, + .req_bits_out ); endmodule @@ -162,56 +164,77 @@ endmodule // axi_burst_splitter skeleton //====================================================================== module axi_burst_splitter #( - parameter int unsigned AddrWidth = 32'd0, - parameter int unsigned DataWidth = 32'd0, - parameter int unsigned IdWidth = 32'd0, - parameter int unsigned UserWidth = 32'd0, - parameter type axi_req_t = logic, - parameter type axi_resp_t = logic -)( - input logic clk_i, - input logic rst_ni, - input axi_req_t slv_req_i, - output axi_resp_t slv_resp_o, - output logic [IdWidth-1:0] id_out + parameter int unsigned AddrWidth = 32'd0, + parameter int unsigned DataWidth = 32'd0, + parameter int unsigned IdWidth = 32'd0, + parameter int unsigned UserWidth = 32'd0, + parameter type axi_req_t = logic, + parameter type axi_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input axi_req_t slv_req_i, + output axi_resp_t slv_resp_o, + output logic [IdWidth-1:0] id_out ); - typedef logic [AddrWidth-1:0] addr_t; - typedef logic [DataWidth-1:0] data_t; - typedef logic [IdWidth-1:0] id_t; + typedef logic [AddrWidth-1:0] addr_t; + typedef logic [DataWidth-1:0] data_t; + typedef logic [IdWidth-1:0] id_t; typedef logic [DataWidth/8-1:0] strb_t; - typedef logic [UserWidth-1:0] user_t; + typedef logic [UserWidth-1:0] user_t; typedef struct packed { - id_t id; + id_t id; addr_t addr; logic [7:0] len; logic [2:0] size; logic [1:0] burst; } local_aw_chan_t; - typedef struct packed { data_t data; strb_t strb; logic last; } local_w_chan_t; - typedef struct packed { id_t id; logic [1:0] resp; } local_b_chan_t; - typedef struct packed { id_t id; addr_t addr; logic [7:0] len; logic [2:0] size; logic [1:0] burst; } local_ar_chan_t; - typedef struct packed { id_t id; data_t data; logic [1:0] resp; logic last; } local_r_chan_t; + typedef struct packed { + data_t data; + strb_t strb; + logic last; + } local_w_chan_t; + typedef struct packed { + id_t id; + logic [1:0] resp; + } local_b_chan_t; + typedef struct packed { + id_t id; + addr_t addr; + logic [7:0] len; + logic [2:0] size; + logic [1:0] burst; + } local_ar_chan_t; + typedef struct packed { + id_t id; + data_t data; + logic [1:0] resp; + logic last; + } local_r_chan_t; int unsigned req_bits_out; axi_demux #( - .AxiIdWidth ( IdWidth ), - .aw_chan_t ( local_aw_chan_t ), - .w_chan_t ( local_w_chan_t ), - .b_chan_t ( local_b_chan_t ), - .ar_chan_t ( local_ar_chan_t ), - .r_chan_t ( local_r_chan_t ), - .axi_req_t ( axi_req_t ), - .axi_resp_t ( axi_resp_t ), - .NoMstPorts ( 2 ), - .MaxTrans ( 4 ), - .AxiLookBits ( IdWidth ) + .AxiIdWidth(IdWidth), + .aw_chan_t(local_aw_chan_t), + .w_chan_t(local_w_chan_t), + .b_chan_t(local_b_chan_t), + .ar_chan_t(local_ar_chan_t), + .r_chan_t(local_r_chan_t), + .axi_req_t(axi_req_t), + .axi_resp_t(axi_resp_t), + .NoMstPorts(2), + .MaxTrans(4), + .AxiLookBits(IdWidth) ) i_demux ( - .clk_i, .rst_ni, - .slv_req_i, .slv_resp_o, .id_out, - .req_bits_out + .clk_i, + .rst_ni, + .slv_req_i, + .slv_resp_o, + .id_out, + .req_bits_out ); endmodule @@ -219,28 +242,28 @@ endmodule // axi_dw_upsizer skeleton //====================================================================== module axi_dw_upsizer #( - parameter int unsigned AxiIdWidth = 1, - parameter int unsigned AxiAddrWidth = 1, - parameter type aw_chan_t = logic, - parameter type mst_w_chan_t = logic, - parameter type slv_w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type mst_r_chan_t = logic, - parameter type slv_r_chan_t = logic, - parameter type axi_mst_req_t = logic, - parameter type axi_mst_resp_t = logic, - parameter type axi_slv_req_t = logic, - parameter type axi_slv_resp_t = logic -)( - input logic clk_i, - input logic rst_ni, - input axi_slv_req_t slv_req_i, - output axi_slv_resp_t slv_resp_o, - output axi_mst_req_t mst_req_o, - input axi_mst_resp_t mst_resp_i + parameter int unsigned AxiIdWidth = 1, + parameter int unsigned AxiAddrWidth = 1, + parameter type aw_chan_t = logic, + parameter type mst_w_chan_t = logic, + parameter type slv_w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type mst_r_chan_t = logic, + parameter type slv_r_chan_t = logic, + parameter type axi_mst_req_t = logic, + parameter type axi_mst_resp_t = logic, + parameter type axi_slv_req_t = logic, + parameter type axi_slv_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input axi_slv_req_t slv_req_i, + output axi_slv_resp_t slv_resp_o, + output axi_mst_req_t mst_req_o, + input axi_mst_resp_t mst_resp_i ); - axi_mst_req_t mst_req; + axi_mst_req_t mst_req; axi_mst_resp_t mst_resp; logic [AxiIdWidth-1:0] id_out; int unsigned req_bits_out; @@ -250,23 +273,24 @@ module axi_dw_upsizer #( assign mst_req_o = mst_req; axi_demux #( - .AxiIdWidth ( AxiIdWidth ), - .aw_chan_t ( aw_chan_t ), - .w_chan_t ( mst_w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .r_chan_t ( mst_r_chan_t ), - .axi_req_t ( axi_mst_req_t ), - .axi_resp_t ( axi_mst_resp_t ), - .NoMstPorts ( 2 ), - .MaxTrans ( 4 ), - .AxiLookBits ( AxiIdWidth ) + .AxiIdWidth(AxiIdWidth), + .aw_chan_t(aw_chan_t), + .w_chan_t(mst_w_chan_t), + .b_chan_t(b_chan_t), + .ar_chan_t(ar_chan_t), + .r_chan_t(mst_r_chan_t), + .axi_req_t(axi_mst_req_t), + .axi_resp_t(axi_mst_resp_t), + .NoMstPorts(2), + .MaxTrans(4), + .AxiLookBits(AxiIdWidth) ) i_axi_demux ( - .clk_i, .rst_ni, - .slv_req_i ( mst_req ), - .slv_resp_o ( mst_resp ), - .id_out, - .req_bits_out + .clk_i, + .rst_ni, + .slv_req_i(mst_req), + .slv_resp_o(mst_resp), + .id_out, + .req_bits_out ); endmodule @@ -274,53 +298,56 @@ endmodule // axi_dw_converter skeleton - generate if for upsize //====================================================================== module axi_dw_converter #( - parameter int unsigned AxiSlvPortDataWidth = 8, - parameter int unsigned AxiMstPortDataWidth = 8, - parameter int unsigned AxiAddrWidth = 1, - parameter int unsigned AxiIdWidth = 1, - parameter type aw_chan_t = logic, - parameter type mst_w_chan_t = logic, - parameter type slv_w_chan_t = logic, - parameter type b_chan_t = logic, - parameter type ar_chan_t = logic, - parameter type mst_r_chan_t = logic, - parameter type slv_r_chan_t = logic, - parameter type axi_mst_req_t = logic, - parameter type axi_mst_resp_t = logic, - parameter type axi_slv_req_t = logic, - parameter type axi_slv_resp_t = logic -)( - input logic clk_i, - input logic rst_ni, - input axi_slv_req_t slv_req_i, - output axi_slv_resp_t slv_resp_o, - output axi_mst_req_t mst_req_o, - input axi_mst_resp_t mst_resp_i + parameter int unsigned AxiSlvPortDataWidth = 8, + parameter int unsigned AxiMstPortDataWidth = 8, + parameter int unsigned AxiAddrWidth = 1, + parameter int unsigned AxiIdWidth = 1, + parameter type aw_chan_t = logic, + parameter type mst_w_chan_t = logic, + parameter type slv_w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type mst_r_chan_t = logic, + parameter type slv_r_chan_t = logic, + parameter type axi_mst_req_t = logic, + parameter type axi_mst_resp_t = logic, + parameter type axi_slv_req_t = logic, + parameter type axi_slv_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input axi_slv_req_t slv_req_i, + output axi_slv_resp_t slv_resp_o, + output axi_mst_req_t mst_req_o, + input axi_mst_resp_t mst_resp_i ); if (AxiMstPortDataWidth == AxiSlvPortDataWidth) begin : gen_no_dw_conversion - assign mst_req_o = slv_req_i; + assign mst_req_o = slv_req_i; assign slv_resp_o = mst_resp_i; end if (AxiMstPortDataWidth > AxiSlvPortDataWidth) begin : gen_dw_upsize axi_dw_upsizer #( - .AxiAddrWidth ( AxiAddrWidth ), - .AxiIdWidth ( AxiIdWidth ), - .aw_chan_t ( aw_chan_t ), - .mst_w_chan_t ( mst_w_chan_t ), - .slv_w_chan_t ( slv_w_chan_t ), - .b_chan_t ( b_chan_t ), - .ar_chan_t ( ar_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ), - .slv_r_chan_t ( slv_r_chan_t ), - .axi_mst_req_t ( axi_mst_req_t ), - .axi_mst_resp_t ( axi_mst_resp_t ), - .axi_slv_req_t ( axi_slv_req_t ), - .axi_slv_resp_t ( axi_slv_resp_t ) + .AxiAddrWidth(AxiAddrWidth), + .AxiIdWidth(AxiIdWidth), + .aw_chan_t(aw_chan_t), + .mst_w_chan_t(mst_w_chan_t), + .slv_w_chan_t(slv_w_chan_t), + .b_chan_t(b_chan_t), + .ar_chan_t(ar_chan_t), + .mst_r_chan_t(mst_r_chan_t), + .slv_r_chan_t(slv_r_chan_t), + .axi_mst_req_t(axi_mst_req_t), + .axi_mst_resp_t(axi_mst_resp_t), + .axi_slv_req_t(axi_slv_req_t), + .axi_slv_resp_t(axi_slv_resp_t) ) i_axi_dw_upsizer ( - .clk_i, .rst_ni, - .slv_req_i, .slv_resp_o, - .mst_req_o, .mst_resp_i + .clk_i, + .rst_ni, + .slv_req_i, + .slv_resp_o, + .mst_req_o, + .mst_resp_i ); end @@ -328,7 +355,8 @@ module axi_dw_converter #( int unsigned mst_req_bits; if (AxiMstPortDataWidth > AxiSlvPortDataWidth) begin : gen_bits_up assign mst_req_bits = gen_dw_upsize.i_axi_dw_upsizer.req_bits_out; - end else begin : gen_bits_eq + end + else begin : gen_bits_eq assign mst_req_bits = 0; end endmodule @@ -337,29 +365,32 @@ endmodule // axi_to_axi_lite skeleton //====================================================================== module axi_to_axi_lite #( - parameter int unsigned AxiAddrWidth = 32'd0, - parameter int unsigned AxiDataWidth = 32'd0, - parameter int unsigned AxiIdWidth = 32'd0, - parameter int unsigned AxiUserWidth = 32'd0, - parameter type full_req_t = logic, - parameter type full_resp_t = logic -)( - input logic clk_i, - input logic rst_ni, - input full_req_t slv_req_i, - output full_resp_t slv_resp_o, - output logic [AxiIdWidth-1:0] id_out + parameter int unsigned AxiAddrWidth = 32'd0, + parameter int unsigned AxiDataWidth = 32'd0, + parameter int unsigned AxiIdWidth = 32'd0, + parameter int unsigned AxiUserWidth = 32'd0, + parameter type full_req_t = logic, + parameter type full_resp_t = logic +) ( + input logic clk_i, + input logic rst_ni, + input full_req_t slv_req_i, + output full_resp_t slv_resp_o, + output logic [AxiIdWidth-1:0] id_out ); axi_burst_splitter #( - .AddrWidth ( AxiAddrWidth ), - .DataWidth ( AxiDataWidth ), - .IdWidth ( AxiIdWidth ), - .UserWidth ( AxiUserWidth ), - .axi_req_t ( full_req_t ), - .axi_resp_t ( full_resp_t ) + .AddrWidth(AxiAddrWidth), + .DataWidth(AxiDataWidth), + .IdWidth(AxiIdWidth), + .UserWidth(AxiUserWidth), + .axi_req_t(full_req_t), + .axi_resp_t(full_resp_t) ) i_axi_burst_splitter ( - .clk_i, .rst_ni, - .slv_req_i, .slv_resp_o, .id_out + .clk_i, + .rst_ni, + .slv_req_i, + .slv_resp_o, + .id_out ); int unsigned req_bits_out; @@ -369,12 +400,13 @@ endmodule //====================================================================== // axi_to_axi_lite_wrap - non-parameterized wrapper (#()) with iface port //====================================================================== -module axi_to_axi_lite_wrap #()( - input logic clk_i, - input logic rst_ni, - my_if.target axi_tgt_io +module axi_to_axi_lite_wrap #( +) ( + input logic clk_i, + input logic rst_ni, + my_if.target axi_tgt_io ); - typedef axi_tgt_io.req_t tgt_req_t; + typedef axi_tgt_io.req_t tgt_req_t; typedef axi_tgt_io.resp_t tgt_resp_t; tgt_req_t tgt_req; @@ -386,17 +418,18 @@ module axi_to_axi_lite_wrap #()( int unsigned req_bits_out; axi_to_axi_lite #( - .AxiAddrWidth ( 32 ), - .AxiDataWidth ( axi_tgt_io.cfg.DataBits ), - .AxiIdWidth ( axi_tgt_io.cfg.IdBits ), - .AxiUserWidth ( 1 ), - .full_req_t ( tgt_req_t ), - .full_resp_t ( tgt_resp_t ) + .AxiAddrWidth(32), + .AxiDataWidth(axi_tgt_io.cfg.DataBits), + .AxiIdWidth(axi_tgt_io.cfg.IdBits), + .AxiUserWidth(1), + .full_req_t(tgt_req_t), + .full_resp_t(tgt_resp_t) ) axi_to_axi_lite ( - .clk_i, .rst_ni, - .slv_req_i ( tgt_req ), - .slv_resp_o ( tgt_resp ), - .id_out ( id_result ) + .clk_i, + .rst_ni, + .slv_req_i(tgt_req), + .slv_resp_o(tgt_resp), + .id_out(id_result) ); assign req_bits_out = axi_to_axi_lite.req_bits_out; @@ -405,25 +438,26 @@ endmodule //====================================================================== // axi_dw_converter_wrap - non-parameterized wrapper with TWO iface ports //====================================================================== -module axi_dw_converter_wrap #()( - input logic clk_i, - input logic rst_ni, - my_if.target tgt_io, - my_if.initiator mst_io +module axi_dw_converter_wrap #( +) ( + input logic clk_i, + input logic rst_ni, + my_if.target tgt_io, + my_if.initiator mst_io ); - typedef tgt_io.aw_chan_t tgt_aw_chan_t; - typedef tgt_io.w_chan_t tgt_w_chan_t; - typedef tgt_io.b_chan_t tgt_b_chan_t; - typedef tgt_io.ar_chan_t tgt_ar_chan_t; - typedef tgt_io.r_chan_t tgt_r_chan_t; + typedef tgt_io.aw_chan_t tgt_aw_chan_t; + typedef tgt_io.w_chan_t tgt_w_chan_t; + typedef tgt_io.b_chan_t tgt_b_chan_t; + typedef tgt_io.ar_chan_t tgt_ar_chan_t; + typedef tgt_io.r_chan_t tgt_r_chan_t; - typedef mst_io.w_chan_t mst_w_chan_t; - typedef mst_io.r_chan_t mst_r_chan_t; + typedef mst_io.w_chan_t mst_w_chan_t; + typedef mst_io.r_chan_t mst_r_chan_t; - typedef tgt_io.req_t tgt_req_t; - typedef tgt_io.resp_t tgt_resp_t; - typedef mst_io.req_t mst_req_t; - typedef mst_io.resp_t mst_resp_t; + typedef tgt_io.req_t tgt_req_t; + typedef tgt_io.resp_t tgt_resp_t; + typedef mst_io.req_t mst_req_t; + typedef mst_io.resp_t mst_resp_t; tgt_req_t tgt_req; tgt_resp_t tgt_resp; @@ -436,27 +470,28 @@ module axi_dw_converter_wrap #()( assign mst_resp = mst_io.resp; axi_dw_converter #( - .AxiSlvPortDataWidth ( tgt_io.cfg.DataBits ), - .AxiMstPortDataWidth ( mst_io.cfg.DataBits ), - .AxiAddrWidth ( 32 ), - .AxiIdWidth ( tgt_io.cfg.IdBits ), - .aw_chan_t ( tgt_aw_chan_t ), - .mst_w_chan_t ( mst_w_chan_t ), - .slv_w_chan_t ( tgt_w_chan_t ), - .b_chan_t ( tgt_b_chan_t ), - .ar_chan_t ( tgt_ar_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ), - .slv_r_chan_t ( tgt_r_chan_t ), - .axi_mst_req_t ( mst_req_t ), - .axi_mst_resp_t ( mst_resp_t ), - .axi_slv_req_t ( tgt_req_t ), - .axi_slv_resp_t ( tgt_resp_t ) + .AxiSlvPortDataWidth(tgt_io.cfg.DataBits), + .AxiMstPortDataWidth(mst_io.cfg.DataBits), + .AxiAddrWidth(32), + .AxiIdWidth(tgt_io.cfg.IdBits), + .aw_chan_t(tgt_aw_chan_t), + .mst_w_chan_t(mst_w_chan_t), + .slv_w_chan_t(tgt_w_chan_t), + .b_chan_t(tgt_b_chan_t), + .ar_chan_t(tgt_ar_chan_t), + .mst_r_chan_t(mst_r_chan_t), + .slv_r_chan_t(tgt_r_chan_t), + .axi_mst_req_t(mst_req_t), + .axi_mst_resp_t(mst_resp_t), + .axi_slv_req_t(tgt_req_t), + .axi_slv_resp_t(tgt_resp_t) ) dw_converter ( - .clk_i, .rst_ni, - .slv_req_i ( tgt_req ), - .slv_resp_o ( tgt_resp ), - .mst_req_o ( mst_req ), - .mst_resp_i ( mst_resp ) + .clk_i, + .rst_ni, + .slv_req_i(tgt_req), + .slv_resp_o(tgt_resp), + .mst_req_o(mst_req), + .mst_resp_i(mst_resp) ); // Expose $bits from the mst-side leaf (through dw_converter -> upsizer -> demux) @@ -484,20 +519,23 @@ module t; // Config B: wide ID (8 bits), data 64 bits localparam cfg_pkg::cfg_t CFG_B = '{IdBits: 8, DataBits: 64}; - my_if #(.cfg(CFG_A_SLV)) bus_a_slv(); - my_if #(.cfg(CFG_A_MST)) bus_a_mst(); - my_if #(.cfg(CFG_B)) bus_b(); + my_if #(.cfg(CFG_A_SLV)) bus_a_slv (); + my_if #(.cfg(CFG_A_MST)) bus_a_mst (); + my_if #(.cfg(CFG_B)) bus_b (); // Path A: dw_converter_wrap (narrow ID, upsize 64->128) axi_dw_converter_wrap #() u_dw_conv_wrap ( - .clk_i(clk), .rst_ni(rst_n), - .tgt_io(bus_a_slv), .mst_io(bus_a_mst) + .clk_i(clk), + .rst_ni(rst_n), + .tgt_io(bus_a_slv), + .mst_io(bus_a_mst) ); // Path B: axi_to_axi_lite_wrap (wide ID) axi_to_axi_lite_wrap #() u_axi_to_lite_wrap ( - .clk_i(clk), .rst_ni(rst_n), - .axi_tgt_io(bus_b) + .clk_i(clk), + .rst_ni(rst_n), + .axi_tgt_io(bus_b) ); //====================================================================== @@ -524,11 +562,12 @@ module t; localparam int unsigned EXP_REQ_BITS_A_SLV = 236; localparam int unsigned EXP_REQ_BITS_A_MST = 436; - localparam int unsigned EXP_REQ_BITS_B = 248; + localparam int unsigned EXP_REQ_BITS_B = 248; // verilator lint_off STMTDLY initial begin - clk = 0; rst_n = 1; + clk = 0; + rst_n = 1; // Drive path A: narrow ID bus_a_slv.req = '0; @@ -583,8 +622,7 @@ module t; // axi_to_axi_lite_wrap -> ... -> axi_demux_simple extracts aw.id[0+:8] //------------------------------------------------------------------ if (u_axi_to_lite_wrap.id_result !== 8'hAB) begin - $display("%%Error: axi_to_lite id_result=%0h expected=AB", - u_axi_to_lite_wrap.id_result); + $display("%%Error: axi_to_lite id_result=%0h expected=AB", u_axi_to_lite_wrap.id_result); $stop; end diff --git a/test_regress/t/t_semaphore_concurrent.v b/test_regress/t/t_semaphore_concurrent.v index 58186867e..56342859c 100644 --- a/test_regress/t/t_semaphore_concurrent.v +++ b/test_regress/t/t_semaphore_concurrent.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2024 Liam Braun // SPDX-License-Identifier: CC0-1.0 -module t(); +module t; semaphore s; // Stand-in for a task that should only be run by one thread at a time diff --git a/test_regress/t/t_split_var_1_bad.v b/test_regress/t/t_split_var_1_bad.v index b448b7a21..3e494d990 100644 --- a/test_regress/t/t_split_var_1_bad.v +++ b/test_regress/t/t_split_var_1_bad.v @@ -12,7 +12,7 @@ interface ifs; logic [7:0] should_show_warning_ifs1 [1:0] /* verilator split_var */; endinterface -module t(); +module t; // The following variables can not be splitted. will see warnings. real should_show_warning0 /*verilator split_var*/; string should_show_warning1 /*verilator split_var*/; diff --git a/test_regress/t/t_static_function_in_class_noparen.v b/test_regress/t/t_static_function_in_class_noparen.v index 654751306..502278131 100644 --- a/test_regress/t/t_static_function_in_class_noparen.v +++ b/test_regress/t/t_static_function_in_class_noparen.v @@ -16,7 +16,7 @@ class Foo; endfunction endclass -module t(); +module t; initial begin int v; diff --git a/test_regress/t/t_std_process_self.v b/test_regress/t/t_std_process_self.v index 9627bbaff..489a794dd 100644 --- a/test_regress/t/t_std_process_self.v +++ b/test_regress/t/t_std_process_self.v @@ -15,7 +15,7 @@ class Foo; endtask endclass -module t(); +module t; initial begin Foo::do_something(); $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_struct_genfor.v b/test_regress/t/t_struct_genfor.v index c6415abac..5026862e0 100644 --- a/test_regress/t/t_struct_genfor.v +++ b/test_regress/t/t_struct_genfor.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2013 Wilson Snyder // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; for (genvar g = 0; g < 2; ++g) begin : genfor typedef struct packed { diff --git a/test_regress/t/t_structu_wide.v b/test_regress/t/t_structu_wide.v index 61dca1ad7..061bc2360 100644 --- a/test_regress/t/t_structu_wide.v +++ b/test_regress/t/t_structu_wide.v @@ -8,7 +8,7 @@ `define WIDE_WIDTH 128 `endif -module t (); +module t; typedef struct { bit [`WIDE_WIDTH-1:0] data; } wide_t; diff --git a/test_regress/t/t_sys_readmem_eof.v b/test_regress/t/t_sys_readmem_eof.v index dac29b83d..0a6b604a1 100644 --- a/test_regress/t/t_sys_readmem_eof.v +++ b/test_regress/t/t_sys_readmem_eof.v @@ -8,7 +8,7 @@ `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); `define STRINGIFY(x) `"x`" -module t(); +module t; reg [7:0] rom [4]; initial begin $readmemh({`STRINGIFY(`TEST_OBJ_DIR), "/dat.mem"}, rom); diff --git a/test_regress/t/t_timing_dynscope.v b/test_regress/t/t_timing_dynscope.v index cc03503ea..8a8d75fe2 100644 --- a/test_regress/t/t_timing_dynscope.v +++ b/test_regress/t/t_timing_dynscope.v @@ -25,7 +25,7 @@ class Foo; endtask endclass -module t(); +module t; initial begin int desired_counts[10]; counts = '{10{0}}; diff --git a/test_regress/t/t_timing_split.v b/test_regress/t/t_timing_split.v index cd33fa6af..0850ce7c8 100644 --- a/test_regress/t/t_timing_split.v +++ b/test_regress/t/t_timing_split.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2023 Jomit626 // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; logic clk = 0; logic data = 0; diff --git a/test_regress/t/t_trace_split_cfuncs.v b/test_regress/t/t_trace_split_cfuncs.v index be695fa88..a4adac3ac 100644 --- a/test_regress/t/t_trace_split_cfuncs.v +++ b/test_regress/t/t_trace_split_cfuncs.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2022 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; initial begin $dumpfile("dump.vcd"); diff --git a/test_regress/t/t_trace_split_cfuncs_dpi_export.v b/test_regress/t/t_trace_split_cfuncs_dpi_export.v index 2951f36e1..6bd0d4ca5 100644 --- a/test_regress/t/t_trace_split_cfuncs_dpi_export.v +++ b/test_regress/t/t_trace_split_cfuncs_dpi_export.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2022 Varun Koyyalagunta // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; function automatic void func(); endfunction diff --git a/test_regress/t/t_type_param.v b/test_regress/t/t_type_param.v index ed22d9d21..89e2b51d0 100644 --- a/test_regress/t/t_type_param.v +++ b/test_regress/t/t_type_param.v @@ -25,7 +25,7 @@ module foo_wrapper endmodule -module t(); +module t; logic [7:0] qux1; int bar_size1; diff --git a/test_regress/t/t_udp_nonsequential_x.v b/test_regress/t/t_udp_nonsequential_x.v index d415442c3..a598cc533 100644 --- a/test_regress/t/t_udp_nonsequential_x.v +++ b/test_regress/t/t_udp_nonsequential_x.v @@ -4,7 +4,7 @@ // SPDX-FileCopyrightText: 2025 Michael Bikovitsky // SPDX-License-Identifier: CC0-1.0 -module t (); +module t; wire true1; not1 a(true1, '0); diff --git a/test_regress/t/t_var_extern_method_lifetime.v b/test_regress/t/t_var_extern_method_lifetime.v index 1b1feb3d9..efbe410fe 100644 --- a/test_regress/t/t_var_extern_method_lifetime.v +++ b/test_regress/t/t_var_extern_method_lifetime.v @@ -20,7 +20,7 @@ task automatic Foo::add_in_fork_delayed(int delay, Foo arg); join_none endtask -module t(); +module t; initial begin Foo foo1, foo2; foo1 = new(1); diff --git a/test_regress/t/t_var_in_fork.v b/test_regress/t/t_var_in_fork.v index 8406377a9..2146249f7 100644 --- a/test_regress/t/t_var_in_fork.v +++ b/test_regress/t/t_var_in_fork.v @@ -6,7 +6,7 @@ int static_var; -module t(); +module t; event evt; task send_event(); ->evt; diff --git a/test_regress/t/t_x_rand_scoped_is_random.v b/test_regress/t/t_x_rand_scoped_is_random.v index e3b4ce968..e6b6fa690 100644 --- a/test_regress/t/t_x_rand_scoped_is_random.v +++ b/test_regress/t/t_x_rand_scoped_is_random.v @@ -6,7 +6,7 @@ `define STRINGIFY(x) `"x`" -module t (); +module t; reg a0 = 'x; reg a1 = 'x; reg a2 = 'x; From f232449252713ea9c28482ef5b298e6068923370 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 3 Mar 2026 07:21:39 -0500 Subject: [PATCH 037/340] Commentary: Changes update --- Changes | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Changes b/Changes index 0b16e32a8..86fd3d1b2 100644 --- a/Changes +++ b/Changes @@ -14,6 +14,7 @@ Verilator 5.047 devel **Other:** * Support soft constraint solving (#7124) (#7166). [Yilou Wang] +* Support constraints on fixed-size array of class object members (#7170) (#7183). [Yilou Wang] * Add VPI callback support to --main (#7145). * Add V3LiftExpr pass to lower impure expressions and calls (#7141) (#7164). [Geza Lore, Testorrent USA, Inc.] * Improve assignment-compatibility type check (#2843) (#5666) (#7052). [Pawel Kojma, Antmicro Ltd.] @@ -21,6 +22,7 @@ Verilator 5.047 devel * Optimize function call return value temporaries (#7152). [Geza Lore, Testorrent USA, Inc.] * Optimize conditional merging across some impure statements (#7159). [Geza Lore, Testorrent USA, Inc.] * Fix lambda coroutines (#6106) (#7135). [Nick Brereton] +* Fix interface localparam dependencies and arbitrary nesting (#6936) (#7128). [em2machine] * Fix errant integer promotion (#7012). [Todd Strader] * Fix scheduling non-determinism (#7120) (#7162) (#7165). [Geza Lore, Testorrent USA, Inc.] * Fix parameters inside std::randomize `with` clause (#7140). [Kamil Danecki, Antmicro Ltd.] From 5f3d47573640080682dd5a2a915fbb605babfc88 Mon Sep 17 00:00:00 2001 From: em2machine <92717390+em2machine@users.noreply.github.com> Date: Tue, 3 Mar 2026 11:13:32 -0500 Subject: [PATCH 038/340] Internals: Minor coverage improvement as followup to (#7128 followup) (#7184) --- src/V3LinkDot.cpp | 3 ++- src/V3LinkDotIfaceCapture.cpp | 49 +++++++++++++++++++++-------------- 2 files changed, 32 insertions(+), 20 deletions(-) diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index a482a04f5..14f0be075 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -5582,7 +5582,8 @@ class LinkDotResolveVisitor final : public VNVisitor { // typedef is first linked. if (V3LinkDotIfaceCapture::enabled()) { if (AstRefDType* const resolvedRefp = VN_CAST(resolvedDTypep, RefDType)) { - if (VL_UNCOVERABLE(VN_IS(resolvedRefp->user2p(), Cell))) { + if (VL_UNCOVERABLE( + VN_IS(resolvedRefp->user2p(), Cell))) { // LCOV_EXCL_LINE resolvedRefp->v3fatalSrc( // LCOV_EXCL_LINE "typeofp resolved RefDType has Cell in user2p;" " expected to be captured already"); diff --git a/src/V3LinkDotIfaceCapture.cpp b/src/V3LinkDotIfaceCapture.cpp index 24e98721b..dde304e2b 100644 --- a/src/V3LinkDotIfaceCapture.cpp +++ b/src/V3LinkDotIfaceCapture.cpp @@ -139,41 +139,52 @@ string resolveOwnerName(const string& hint, AstNode* nodep) { } // namespace AstTypedef* V3LinkDotIfaceCapture::findTypedefInModule(AstNodeModule* modp, const string& name) { + AstTypedef* resultp = nullptr; const StmtNameMap& cache = getOrBuild(modp); const auto it = cache.m_byName.find(name); - if (it == cache.m_byName.end()) return nullptr; - for (AstNode* nodep : it->second) { - if (AstTypedef* const tdp = VN_CAST(nodep, Typedef)) return tdp; + if (!(it == cache.m_byName.end())) { + for (AstNode* nodep : it->second) { + if (AstTypedef* const tdp = VN_CAST(nodep, Typedef)) { + resultp = tdp; + break; + } + } } - // Cache has entry for this name but no Typedef - unexpected. - v3fatalSrc("findTypedefInModule: name '" << name << "' found in " << modp->prettyNameQ() - << " but no Typedef node"); - return nullptr; // LCOV_EXCL_LINE + return resultp; } AstNodeDType* V3LinkDotIfaceCapture::findDTypeInModule(AstNodeModule* modp, const string& name, VNType type) { + + AstNodeDType* resultp = nullptr; const StmtNameMap& cache = getOrBuild(modp); const auto it = cache.m_byName.find(name); - if (it == cache.m_byName.end()) return nullptr; - for (AstNode* nodep : it->second) { - if (AstNodeDType* const dtp = VN_CAST(nodep, NodeDType)) { - if (dtp->type() == type) return dtp; + if (!(it == cache.m_byName.end())) { + for (AstNode* nodep : it->second) { + if (AstNodeDType* const dtp = VN_CAST(nodep, NodeDType)) { + if (dtp->type() == type) { + resultp = dtp; + break; + } + } } } - // Cache has entry for this name but no matching DType - unexpected. - v3fatalSrc("findDTypeInModule: name '" << name << "' found in " << modp->prettyNameQ() - << " but no matching DType"); - return nullptr; // LCOV_EXCL_LINE + return resultp; } AstParamTypeDType* V3LinkDotIfaceCapture::findParamTypeInModule(AstNodeModule* modp, const string& name) { + + AstParamTypeDType* resultp = nullptr; const StmtNameMap& cache = getOrBuild(modp); const auto it = cache.m_byName.find(name); - if (it == cache.m_byName.end()) return nullptr; - for (AstNode* nodep : it->second) { - if (AstParamTypeDType* const ptdp = VN_CAST(nodep, ParamTypeDType)) return ptdp; + if (!(it == cache.m_byName.end())) { + for (AstNode* nodep : it->second) { + if (AstParamTypeDType* const ptdp = VN_CAST(nodep, ParamTypeDType)) { + resultp = ptdp; + break; + } + } } - return nullptr; + return resultp; } AstNodeDType* V3LinkDotIfaceCapture::findDTypeByPrettyName(AstNodeModule* modp, From 3bc73cc7683a927374f0f72be4185e41f9e1cfed Mon Sep 17 00:00:00 2001 From: Yilou Wang Date: Tue, 3 Mar 2026 17:23:14 +0100 Subject: [PATCH 039/340] Support constraint imperfect distributions (#6811) (#7168) --- include/verilated_random.cpp | 8 + include/verilated_random.h | 1 + src/V3AstAttr.h | 2 + src/V3AstNodeExpr.h | 2 +- src/V3Randomize.cpp | 216 +++++++++++++++++++++ src/V3Width.cpp | 19 +- test_regress/t/t_constraint_dist_weight.py | 21 ++ test_regress/t/t_constraint_dist_weight.v | 129 ++++++++++++ test_regress/t/t_randomize.out | 7 - test_regress/t/t_randomize.py | 9 +- test_regress/t/t_randomize.v | 4 +- 11 files changed, 405 insertions(+), 13 deletions(-) create mode 100755 test_regress/t/t_constraint_dist_weight.py create mode 100644 test_regress/t/t_constraint_dist_weight.v delete mode 100644 test_regress/t/t_randomize.out diff --git a/include/verilated_random.cpp b/include/verilated_random.cpp index 4ed746e86..f800b2ea8 100644 --- a/include/verilated_random.cpp +++ b/include/verilated_random.cpp @@ -746,6 +746,14 @@ void VlRandomizer::soft(std::string&& constraint, const char* /*filename*/, uint m_softConstraints.emplace_back(std::move(constraint)); } +void VlRandomizer::disable_soft(const std::string& varName) { + // IEEE 1800-2017 18.5.13: Remove all soft constraints referencing the variable + m_softConstraints.erase( + std::remove_if(m_softConstraints.begin(), m_softConstraints.end(), + [&](const std::string& c) { return c.find(varName) != std::string::npos; }), + m_softConstraints.end()); +} + void VlRandomizer::clearConstraints() { m_constraints.clear(); m_constraints_line.clear(); diff --git a/include/verilated_random.h b/include/verilated_random.h index 993778b55..010a52a9f 100644 --- a/include/verilated_random.h +++ b/include/verilated_random.h @@ -596,6 +596,7 @@ public: const char* source = ""); void soft(std::string&& constraint, const char* filename = "", uint32_t linenum = 0, const char* source = ""); + void disable_soft(const std::string& varName); void clearConstraints(); void clearAll(); // Clear both constraints and variables void markRandc(const char* name); // Mark variable as randc for cyclic tracking diff --git a/src/V3AstAttr.h b/src/V3AstAttr.h index bfe9ba1fb..bf5ba0ae6 100644 --- a/src/V3AstAttr.h +++ b/src/V3AstAttr.h @@ -814,6 +814,7 @@ public: RANDOMIZER_BASIC_STD_RANDOMIZATION, RANDOMIZER_CLEARCONSTRAINTS, RANDOMIZER_CLEARALL, + RANDOMIZER_DISABLE_SOFT, RANDOMIZER_HARD, RANDOMIZER_SOFT, RANDOMIZER_UNIQUE, @@ -951,6 +952,7 @@ inline std::ostream& operator<<(std::ostream& os, const VCMethod& rhs) { {RANDOMIZER_BASIC_STD_RANDOMIZATION, "basicStdRandomization", false}, \ {RANDOMIZER_CLEARCONSTRAINTS, "clearConstraints", false}, \ {RANDOMIZER_CLEARALL, "clearAll", false}, \ + {RANDOMIZER_DISABLE_SOFT, "disable_soft", false}, \ {RANDOMIZER_HARD, "hard", false}, \ {RANDOMIZER_SOFT, "soft", false}, \ {RANDOMIZER_UNIQUE, "rand_unique", false}, \ diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h index 34b0bf105..664d7946b 100644 --- a/src/V3AstNodeExpr.h +++ b/src/V3AstNodeExpr.h @@ -1268,7 +1268,7 @@ class AstDist final : public AstNodeExpr { // @astgen op2 := itemsp : List[AstDistItem] public: AstDist(FileLine* fl, AstNodeExpr* exprp, AstDistItem* itemsp) - : ASTGEN_SUPER_Inside(fl) { + : ASTGEN_SUPER_Dist(fl) { this->exprp(exprp); addItemsp(itemsp); dtypeSetBit(); diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 57c257796..5300a31ac 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -1785,6 +1785,7 @@ class ConstraintExprVisitor final : public VNVisitor { newp = new AstLogIf{fl, new AstNot{fl, nodep->condp()->unlinkFrBack()}, elsep}; } if (newp) { + newp->dtypeSetBit(); // Result is boolean (prevents bare-var != 0 wrapping) newp->user1(true); // Assume result-dependent nodep->replaceWith(new AstConstraintExpr{fl, newp}); } else { @@ -1963,6 +1964,45 @@ class ConstraintExprVisitor final : public VNVisitor { } void visit(AstConstraintExpr* nodep) override { + // IEEE 1800-2017 18.5.13: "disable soft" removes all soft constraints + // referencing the specified variable. Pass the variable name directly + // instead of going through SMT lowering. + if (nodep->isDisableSoft()) { + // Extract variable name from expression (VarRef or MemberSel) + std::string varName; + if (const AstNodeVarRef* const vrefp = VN_CAST(nodep->exprp(), NodeVarRef)) { + varName = vrefp->name(); + } else if (const AstMemberSel* const mselp = VN_CAST(nodep->exprp(), MemberSel)) { + varName = mselp->name(); + } else { + nodep->v3fatalSrc("Unexpected expression type in disable soft"); + return; + } + AstCMethodHard* const callp = new AstCMethodHard{ + nodep->fileline(), + new AstVarRef{nodep->fileline(), VN_AS(m_genp->user2p(), NodeModule), m_genp, + VAccess::READWRITE}, + VCMethod::RANDOMIZER_DISABLE_SOFT, + new AstConst{nodep->fileline(), AstConst::String{}, varName}}; + callp->dtypeSetVoid(); + nodep->replaceWith(callp->makeStmt()); + VL_DO_DANGLING(nodep->deleteTree(), nodep); + return; + } + // IEEE 1800-2017 18.5.1: A bare expression used as a constraint is + // implicitly treated as "expr != 0" when wider than 1 bit. + // Must wrap before iterateChildren, which converts to SMT format. + { + AstNodeExpr* const exprp = nodep->exprp(); + if (exprp->width() > 1) { + FileLine* const fl = exprp->fileline(); + V3Number numZero{fl, exprp->width(), 0}; + AstNodeExpr* const neqp + = new AstNeq{fl, exprp->unlinkFrBack(), new AstConst{fl, numZero}}; + neqp->user1(true); // Mark as rand-dependent for SMT path + nodep->exprp(neqp); + } + } iterateChildren(nodep); if (m_wantSingle) { nodep->replaceWith(nodep->exprp()->unlinkFrBack()); @@ -2506,6 +2546,7 @@ class RandomizeVisitor final : public VNVisitor { AstDynArrayDType* m_dynarrayDtp = nullptr; // Dynamic array type (for rand mode) size_t m_enumValueTabCount = 0; // Number of tables with enum values created int m_randCaseNum = 0; // Randcase number within a module for var naming + int m_distNum = 0; // Dist bucket variable counter within a module for var naming std::map m_randcDtypes; // RandC data type deduplication AstConstraint* m_constraintp = nullptr; // Current constraint std::set m_writtenVars; // Track write_var calls per class to avoid duplicates @@ -3551,6 +3592,178 @@ class RandomizeVisitor final : public VNVisitor { } } + // Replace AstDist with weighted bucket selection via AstConstraintIf chain. + // Supports both constant and variable weight expressions. + void lowerDistConstraints(AstTask* taskp, AstNode* constrItemsp) { + for (AstNode *nextip, *itemp = constrItemsp; itemp; itemp = nextip) { + nextip = itemp->nextp(); + AstConstraintExpr* const constrExprp = VN_CAST(itemp, ConstraintExpr); + if (!constrExprp) continue; + AstDist* const distp = VN_CAST(constrExprp->exprp(), Dist); + if (!distp) continue; + + FileLine* const fl = distp->fileline(); + + struct BucketInfo final { + AstNodeExpr* rangep; + AstNodeExpr* weightExprp; // Effective weight as AST expression + }; + std::vector buckets; + + for (AstDistItem* ditemp = distp->itemsp(); ditemp; + ditemp = VN_AS(ditemp->nextp(), DistItem)) { + // Skip compile-time zero weights + if (const AstConst* const constp = VN_CAST(ditemp->weightp(), Const)) { + if (constp->toUQuad() == 0) continue; + } + + // Clone and extend weight to 64-bit + AstNodeExpr* weightExprp + = new AstExtend{fl, ditemp->weightp()->cloneTreePure(false), 64}; + + // := is per-value weight; for ranges multiply by range size + if (!ditemp->isWhole()) { + if (const AstInsideRange* const irp = VN_CAST(ditemp->rangep(), InsideRange)) { + const AstConst* const lop = VN_CAST(irp->lhsp(), Const); + const AstConst* const hip = VN_CAST(irp->rhsp(), Const); + AstNodeExpr* rangeSizep; + if (lop && hip) { + const uint64_t rangeSize = hip->toUQuad() - lop->toUQuad() + 1; + rangeSizep = new AstConst{fl, AstConst::Unsized64{}, rangeSize}; + } else { + // Variable range bounds: (hi - lo + 1) at runtime + rangeSizep = new AstAdd{ + fl, new AstConst{fl, AstConst::Unsized64{}, 1}, + new AstSub{ + fl, new AstExtend{fl, irp->rhsp()->cloneTreePure(false), 64}, + new AstExtend{fl, irp->lhsp()->cloneTreePure(false), 64}}}; + rangeSizep->dtypeSetUInt64(); + } + weightExprp = new AstMul{fl, weightExprp, rangeSizep}; + weightExprp->dtypeSetUInt64(); + } + } + + buckets.push_back({ditemp->rangep(), weightExprp}); + } + + if (buckets.empty()) { + // All weights are zero: dist is vacuously true (unconstrained) + AstConstraintExpr* const truep + = new AstConstraintExpr{fl, new AstConst{fl, AstConst::BitTrue{}}}; + constrExprp->replaceWith(truep); + VL_DO_DANGLING(pushDeletep(constrExprp), constrExprp); + continue; + } + + // Build totalWeight expression: w[0] + w[1] + ... + w[N-1] + AstNodeExpr* totalWeightExprp = nullptr; + for (auto& bucket : buckets) { + if (!totalWeightExprp) { + totalWeightExprp = bucket.weightExprp->cloneTreePure(false); + } else { + totalWeightExprp = new AstAdd{fl, totalWeightExprp, + bucket.weightExprp->cloneTreePure(false)}; + totalWeightExprp->dtypeSetUInt64(); + } + } + + // Store totalWeight in temp var (evaluated once, used twice) + const int distId = m_distNum++; + const std::string totalName = "__Vdist_total" + cvtToStr(distId); + AstVar* const totalVarp + = new AstVar{fl, VVarType::BLOCKTEMP, totalName, taskp->findUInt64DType()}; + totalVarp->noSubst(true); + totalVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); + totalVarp->funcLocal(true); + totalVarp->isInternal(true); + taskp->addStmtsp(totalVarp); + taskp->addStmtsp( + new AstAssign{fl, new AstVarRef{fl, totalVarp, VAccess::WRITE}, totalWeightExprp}); + + // bucketVar = (rand64() % totalWeight) + 1 + const std::string bucketName = "__Vdist_bucket" + cvtToStr(distId); + AstVar* const bucketVarp + = new AstVar{fl, VVarType::BLOCKTEMP, bucketName, taskp->findUInt64DType()}; + bucketVarp->noSubst(true); + bucketVarp->lifetime(VLifetime::AUTOMATIC_EXPLICIT); + bucketVarp->funcLocal(true); + bucketVarp->isInternal(true); + taskp->addStmtsp(bucketVarp); + + AstNodeExpr* randp = new AstRand{fl, nullptr, false}; + randp->dtypeSetUInt64(); + taskp->addStmtsp(new AstAssign{ + fl, new AstVarRef{fl, bucketVarp, VAccess::WRITE}, + new AstAdd{ + fl, new AstConst{fl, AstConst::Unsized64{}, 1}, + new AstModDiv{fl, randp, new AstVarRef{fl, totalVarp, VAccess::READ}}}}); + + // Build cumulative sum expressions forward: cumSum[i] = w[0]+...+w[i] + std::vector cumSums; + AstNodeExpr* runningSump = nullptr; + for (size_t i = 0; i < buckets.size(); ++i) { + if (!runningSump) { + runningSump = buckets[i].weightExprp->cloneTreePure(false); + } else { + runningSump = new AstAdd{fl, runningSump, + buckets[i].weightExprp->cloneTreePure(false)}; + runningSump->dtypeSetUInt64(); + } + cumSums.push_back(runningSump->cloneTreePure(true)); + } + + // Build ConstraintIf chain backward (last bucket is unconditional default) + AstNode* chainp = nullptr; + for (int i = static_cast(buckets.size()) - 1; i >= 0; --i) { + AstNodeExpr* constraintExprp; + if (const AstInsideRange* const irp = VN_CAST(buckets[i].rangep, InsideRange)) { + AstNodeExpr* const exprCopy1p = distp->exprp()->cloneTreePure(false); + exprCopy1p->user1(true); + AstNodeExpr* const exprCopy2p = distp->exprp()->cloneTreePure(false); + exprCopy2p->user1(true); + AstGte* const gtep + = new AstGte{fl, exprCopy1p, irp->lhsp()->cloneTreePure(false)}; + gtep->user1(true); + AstLte* const ltep + = new AstLte{fl, exprCopy2p, irp->rhsp()->cloneTreePure(false)}; + ltep->user1(true); + constraintExprp = new AstLogAnd{fl, gtep, ltep}; + constraintExprp->user1(true); + } else { + AstNodeExpr* const exprCopyp = distp->exprp()->cloneTreePure(false); + exprCopyp->user1(true); + constraintExprp + = new AstEq{fl, exprCopyp, buckets[i].rangep->cloneTreePure(false)}; + constraintExprp->user1(true); + } + + AstConstraintExpr* const thenp = new AstConstraintExpr{fl, constraintExprp}; + + if (!chainp) { + chainp = thenp; + } else { + AstNodeExpr* const condp + = new AstLte{fl, new AstVarRef{fl, bucketVarp, VAccess::READ}, cumSums[i]}; + chainp = new AstConstraintIf{fl, condp, thenp, chainp}; + } + } + + if (chainp) { + constrExprp->replaceWith(chainp); + VL_DO_DANGLING(pushDeletep(constrExprp), constrExprp); + } + + // Clean up nodes used only as clone templates (never inserted into tree) + for (auto& bucket : buckets) { + VL_DO_DANGLING(pushDeletep(bucket.weightExprp), bucket.weightExprp); + } + VL_DO_DANGLING(pushDeletep(runningSump), runningSump); + // Last cumSum is unused (last bucket is unconditional default) + pushDeletep(cumSums.back()); + } + } + // VISITORS void visit(AstNodeModule* nodep) override { VL_RESTORER(m_modp); @@ -3567,8 +3780,10 @@ class RandomizeVisitor final : public VNVisitor { void visit(AstClass* nodep) override { VL_RESTORER(m_modp); VL_RESTORER(m_randCaseNum); + VL_RESTORER(m_distNum); m_modp = nodep; m_randCaseNum = 0; + m_distNum = 0; m_writtenVars.clear(); // Each class has its own set of written variables iterateChildren(nodep); @@ -3616,6 +3831,7 @@ class RandomizeVisitor final : public VNVisitor { } if (constrp->itemsp()) expandUniqueElementList(constrp->itemsp()); + if (constrp->itemsp()) lowerDistConstraints(taskp, constrp->itemsp()); ConstraintExprVisitor{classp, m_memberMap, constrp->itemsp(), nullptr, genp, randModeVarp, m_writtenVars}; if (constrp->itemsp()) { diff --git a/src/V3Width.cpp b/src/V3Width.cpp index c96dcc561..06415443a 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -3126,7 +3126,7 @@ class WidthVisitor final : public VNVisitor { } void visit(AstDist* nodep) override { // x dist {a :/ p, b :/ q} --> (p > 0 && x == a) || (q > 0 && x == b) - nodep->v3warn(CONSTRAINTIGN, "Constraint expression ignored (imperfect distribution)"); + // (only outside constraints; inside constraints V3Randomize handles weighted selection) userIterateAndNext(nodep->exprp(), WidthVP{CONTEXT_DET, PRELIM}.p()); for (AstNode *nextip, *itemp = nodep->itemsp(); itemp; itemp = nextip) { nextip = itemp->nextp(); // iterate may cause the node to get replaced @@ -3163,6 +3163,23 @@ class WidthVisitor final : public VNVisitor { if (!VN_IS(itemp, InsideRange)) iterateCheck(nodep, "Dist Item", itemp, CONTEXT_DET, FINAL, subDTypep, EXTEND_EXP); } + + // Inside a constraint, V3Randomize handles dist lowering with proper weights, + // but only for simple scalar/range items. Container-type items (queues, arrays) + // must be lowered here via insideItem() which knows how to expand them. + if (m_constraintp) { + bool canLower = true; + for (AstDistItem* ditemp = nodep->itemsp(); ditemp; + ditemp = VN_AS(ditemp->nextp(), DistItem)) { + if (!VN_IS(ditemp->rangep(), Const) && !VN_IS(ditemp->rangep(), InsideRange)) { + canLower = false; + break; + } + } + if (canLower) return; + } + + // Outside constraint: lower to inside (ignores weights) AstNodeExpr* newp = nullptr; for (AstDistItem* itemp = nodep->itemsp(); itemp; itemp = VN_AS(itemp->nextp(), DistItem)) { diff --git a/test_regress/t/t_constraint_dist_weight.py b/test_regress/t/t_constraint_dist_weight.py new file mode 100755 index 000000000..db1adb3f9 --- /dev/null +++ b/test_regress/t/t_constraint_dist_weight.py @@ -0,0 +1,21 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of either the GNU Lesser General Public License Version 3 +# or the Perl Artistic License Version 2.0. +# SPDX-FileCopyrightText: 2026 Wilson Snyder +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_constraint_dist_weight.v b/test_regress/t/t_constraint_dist_weight.v new file mode 100644 index 000000000..8312d6650 --- /dev/null +++ b/test_regress/t/t_constraint_dist_weight.v @@ -0,0 +1,129 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain. +// SPDX-FileCopyrightText: 2026 PlanV GmbH +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +`define check_range(gotv,minv,maxv) do if ((gotv) < (minv) || (gotv) > (maxv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d-%0d\n", `__FILE__,`__LINE__, (gotv), (minv), (maxv)); `stop; end while(0); +// verilog_format: on + +class DistScalar; + rand bit [7:0] x; + constraint c { x dist { 8'd0 := 1, 8'd255 := 3 }; } +endclass + +class DistRange; + rand bit [7:0] x; + constraint c { x dist { [8'd0:8'd9] :/ 1, [8'd10:8'd19] :/ 3 }; } +endclass + +class DistZeroWeight; + rand bit [7:0] x; + constraint c { x dist { 8'd0 := 0, 8'd1 := 1, 8'd2 := 1 }; } +endclass + +class DistAllZeroWeight; + rand bit [7:0] x; + constraint c { x dist { 8'd0 := 0, 8'd1 := 0, 8'd2 := 0 }; } +endclass + +class DistVarWeight; + rand bit [7:0] x; + int w1, w2; + constraint c { x dist { 8'd0 := w1, 8'd255 := w2 }; } +endclass + +class DistVarWeightRange; + rand bit [7:0] x; + int w1, w2; + constraint c { x dist { [8'd0:8'd9] :/ w1, [8'd10:8'd19] :/ w2 }; } +endclass + +module t; + initial begin + DistScalar sc; + DistRange rg; + DistZeroWeight zw; + DistAllZeroWeight azw; + DistVarWeight vw; + DistVarWeightRange vwr; + int count_high; + int count_range_high; + int total; + + total = 2000; + + // := scalar weights: expect ~75% for value 255 + sc = new; + count_high = 0; + repeat (total) begin + `checkd(sc.randomize(), 1); + if (sc.x == 8'd255) count_high++; + else `checkd(sc.x, 0); + end + `check_range(count_high, total * 60 / 100, total * 90 / 100); + + // :/ range weights: expect ~75% in [10:19] + rg = new; + count_range_high = 0; + repeat (total) begin + `checkd(rg.randomize(), 1); + if (rg.x >= 8'd10 && rg.x <= 8'd19) count_range_high++; + else if (rg.x > 8'd9) begin + $write("%%Error: x=%0d outside valid range [0:19]\n", rg.x); + `stop; + end + end + `check_range(count_range_high, total * 60 / 100, total * 90 / 100); + + // Zero weight: value 0 must never appear + zw = new; + repeat (total) begin + `checkd(zw.randomize(), 1); + if (zw.x == 8'd0) begin + $write("%%Error: zero-weight value 0 was selected\n"); + `stop; + end + `check_range(zw.x, 1, 2); + end + + // All-zero weights: dist constraint is effectively unconstrained, randomize succeeds + azw = new; + repeat (20) begin + `checkd(azw.randomize(), 1); + end + + // Variable := scalar weights: w1=1, w2=3 => expect ~75% for value 255 + vw = new; + vw.w1 = 1; + vw.w2 = 3; + count_high = 0; + repeat (total) begin + `checkd(vw.randomize(), 1); + if (vw.x == 8'd255) count_high++; + else `checkd(vw.x, 0); + end + `check_range(count_high, total * 60 / 100, total * 90 / 100); + + // Variable :/ range weights: w1=1, w2=3 => expect ~75% in [10:19] + vwr = new; + vwr.w1 = 1; + vwr.w2 = 3; + count_range_high = 0; + repeat (total) begin + `checkd(vwr.randomize(), 1); + if (vwr.x >= 8'd10 && vwr.x <= 8'd19) count_range_high++; + else if (vwr.x > 8'd9) begin + $write("%%Error: x=%0d outside valid range [0:19]\n", vwr.x); + `stop; + end + end + `check_range(count_range_high, total * 60 / 100, total * 90 / 100); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_randomize.out b/test_regress/t/t_randomize.out deleted file mode 100644 index 1e9892a78..000000000 --- a/test_regress/t/t_randomize.out +++ /dev/null @@ -1,7 +0,0 @@ -%Warning-CONSTRAINTIGN: t/t_randomize.v:22:14: Constraint expression ignored (imperfect distribution) - : ... note: In instance 't' - 22 | length dist { [0:1], [2:5] :/ 2, 6 := 6, 7 := 10, 1}; - | ^~~~ - ... For warning description see https://verilator.org/warn/CONSTRAINTIGN?v=latest - ... Use "/* verilator lint_off CONSTRAINTIGN */" and lint_on around source to disable this message. -%Error: Exiting due to diff --git a/test_regress/t/t_randomize.py b/test_regress/t/t_randomize.py index 3160d0589..ab048b5e8 100755 --- a/test_regress/t/t_randomize.py +++ b/test_regress/t/t_randomize.py @@ -9,8 +9,13 @@ import vltest_bootstrap -test.scenarios('vlt') +test.scenarios('simulator') -test.lint(fails=True, expect_filename=test.golden_filename) +if not test.have_solver: + test.skip("No constraint solver installed") + +test.compile() + +test.execute() test.passes() diff --git a/test_regress/t/t_randomize.v b/test_regress/t/t_randomize.v index 2c613ac94..0a0231de6 100644 --- a/test_regress/t/t_randomize.v +++ b/test_regress/t/t_randomize.v @@ -11,7 +11,7 @@ class Packet; rand bit if_4; rand bit iff_5_6; - /*rand*/ int array[2]; // 2,4,6 // TODO: add rand when supported + rand int array[2]; // 2,4,6 constraint empty {} @@ -58,7 +58,7 @@ module t; automatic int v; automatic bit if_4 = '0; - // TODO not testing constrained values + p = new; v = p.randomize(); if (v != 1) $stop; v = p.randomize() with {}; From 7cf539cf05eb7ed2d150f01a899a05471eb8f502 Mon Sep 17 00:00:00 2001 From: jalcim Date: Wed, 4 Mar 2026 11:46:07 +0000 Subject: [PATCH 040/340] Add --func-recursion-depth CLI option (#7175) (#7179) --- bin/verilator | 1 + docs/guide/exe_verilator.rst | 8 ++++++++ src/V3Options.cpp | 1 + src/V3Options.h | 2 ++ src/V3Simulate.h | 6 +++--- test_regress/t/t_func_recurse_depth.py | 18 ++++++++++++++++++ test_regress/t/t_func_recurse_depth.v | 24 ++++++++++++++++++++++++ 7 files changed, 57 insertions(+), 3 deletions(-) create mode 100755 test_regress/t/t_func_recurse_depth.py create mode 100644 test_regress/t/t_func_recurse_depth.v diff --git a/bin/verilator b/bin/verilator index ab07e6201..03ae90424 100755 --- a/bin/verilator +++ b/bin/verilator @@ -390,6 +390,7 @@ detailed descriptions of these arguments. -f Parse arguments from a file -FI Force include of a file --flatten Force inlining of all modules, tasks and functions + --func-recursion-depth Maximum recursive constant function depth --future0