From c1d4d7af10a9183e1a655e08a00388a071b50573 Mon Sep 17 00:00:00 2001 From: Ryszard Rozak Date: Fri, 9 Jan 2026 15:23:33 +0100 Subject: [PATCH] Extract case with forcing struct to separate test Signed-off-by: Ryszard Rozak --- test_regress/t/t_force_unpacked_struct.py | 18 ++++++ test_regress/t/t_force_unpacked_struct.v | 69 +++++++++++++++++++++++ test_regress/t/t_force_unpacked_unsup.out | 3 - test_regress/t/t_force_unpacked_unsup.v | 11 ---- 4 files changed, 87 insertions(+), 14 deletions(-) create mode 100755 test_regress/t/t_force_unpacked_struct.py create mode 100644 test_regress/t/t_force_unpacked_struct.v diff --git a/test_regress/t/t_force_unpacked_struct.py b/test_regress/t/t_force_unpacked_struct.py new file mode 100755 index 000000000..d4f986441 --- /dev/null +++ b/test_regress/t/t_force_unpacked_struct.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile() + +test.execute() + +test.passes() diff --git a/test_regress/t/t_force_unpacked_struct.v b/test_regress/t/t_force_unpacked_struct.v new file mode 100644 index 000000000..6200f1812 --- /dev/null +++ b/test_regress/t/t_force_unpacked_struct.v @@ -0,0 +1,69 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2026 by Antmicro. +// SPDX-License-Identifier: CC0-1.0 + +// verilog_format: off +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) +`define checkr(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); +// verilog_format: on + +module t ( + input clk +); + + integer cyc = 0; + + typedef struct {int x;} struct_t; + + struct_t s_array[3]; + struct_t my_struct; + + // Test loop + always @(posedge clk) begin + cyc <= cyc + 1; + if (cyc == 0) begin + s_array[1].x <= 1; + my_struct.x <= 1; + end + else if (cyc == 1) begin + `checkh(s_array[1].x, 1); + `checkh(my_struct.x, 1); + end + else if (cyc == 2) begin + force s_array[1].x = 0; + force my_struct.x = 0; + end + else if (cyc == 3) begin + `checkh(s_array[1].x, 0); + s_array[1].x <= 1; + `checkh(my_struct.x, 0); + my_struct.x <= 1; + end + else if (cyc == 4) begin + `checkh(s_array[1].x, 0); + `checkh(my_struct.x, 0); + end + else if (cyc == 5) begin + release s_array[1].x; + release my_struct.x; + end + else if (cyc == 6) begin + `checkh(s_array[1].x, 0); + s_array[1].x <= 1; + `checkh(my_struct.x, 0); + my_struct.x <= 1; + end + else if (cyc == 7) begin + `checkh(s_array[1].x, 1); + `checkh(my_struct.x, 1); + end + else if (cyc == 8) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule diff --git a/test_regress/t/t_force_unpacked_unsup.out b/test_regress/t/t_force_unpacked_unsup.out index a770c9520..b8ef50971 100644 --- a/test_regress/t/t_force_unpacked_unsup.out +++ b/test_regress/t/t_force_unpacked_unsup.out @@ -11,7 +11,4 @@ %Error-UNSUPPORTED: t/t_force_unpacked_unsup.v:21:12: Unsupported: Force of unpacked array variable with elements of complex data type 21 | struct_t s_array[3000]; | ^~~~~~~ -%Error-UNSUPPORTED: t/t_force_unpacked_unsup.v:24:12: Unsupported: Force of unpacked struct / union variable - 24 | struct_t my_struct; - | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_force_unpacked_unsup.v b/test_regress/t/t_force_unpacked_unsup.v index 63ef45b67..b3f0bc456 100644 --- a/test_regress/t/t_force_unpacked_unsup.v +++ b/test_regress/t/t_force_unpacked_unsup.v @@ -21,7 +21,6 @@ module t ( struct_t s_array[3000]; bit big_array[40][40][40]; real r_array[2]; - struct_t my_struct; // Test loop always @(posedge clk) begin @@ -30,19 +29,16 @@ module t ( r_array[0] <= 1; big_array[1][2][3] <= 1; s_array[1].x <= 1; - my_struct.x <= 1; end else if (cyc == 1) begin `checkr(r_array[0], 1); `checkr(big_array[1][2][3], 1); `checkh(s_array[1].x, 1); - `checkh(my_struct.x, 1); end else if (cyc == 2) begin force r_array[0] = 0; force big_array[1][2][3] = 0; force s_array[1].x = 0; - force my_struct.x = 0; end else if (cyc == 3) begin `checkr(r_array[0], 0); @@ -51,20 +47,16 @@ module t ( big_array[1][2][3] <= 1; `checkh(s_array[1].x, 0); s_array[1].x <= 1; - `checkh(my_struct.x, 0); - my_struct.x <= 1; end else if (cyc == 4) begin `checkr(r_array[0], 0); `checkr(big_array[1][2][3], 0); `checkh(s_array[1].x, 0); - `checkh(my_struct.x, 0); end else if (cyc == 5) begin release r_array[0]; release big_array[1][2][3]; release s_array[1].x; - release my_struct.x; end else if (cyc == 6) begin `checkr(r_array[0], 0); @@ -73,14 +65,11 @@ module t ( big_array[1][2][3] <= 1; `checkh(s_array[1].x, 0); s_array[1].x <= 1; - `checkh(my_struct.x, 0); - my_struct.x <= 1; end else if (cyc == 7) begin `checkr(r_array[0], 1); `checkr(big_array[1][2][3], 1); `checkh(s_array[1].x, 1); - `checkh(my_struct.x, 1); end else if (cyc == 8) begin $write("*-* All Finished *-*\n");