From c1d1b333ac77e9f5a2b8817eaa73a9aad3360d4e Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Thu, 23 Apr 2026 00:50:12 -0400
Subject: [PATCH] With -Wpendantic allow circular assigns

---
 src/V3Const.cpp                        |  4 +++-
 test_regress/t/t_dist_warn_coverage.py |  2 --
 test_regress/t/t_lint_wireloop.py      | 18 ++++++++++++++++++
 test_regress/t/t_lint_wireloop.v       | 11 +++++++++++
 test_regress/t/t_lint_wireloop_bad.out |  5 +++++
 test_regress/t/t_lint_wireloop_bad.py  | 17 +++++++++++++++++
 6 files changed, 54 insertions(+), 3 deletions(-)
 create mode 100755 test_regress/t/t_lint_wireloop.py
 create mode 100644 test_regress/t/t_lint_wireloop.v
 create mode 100644 test_regress/t/t_lint_wireloop_bad.out
 create mode 100755 test_regress/t/t_lint_wireloop_bad.py

diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index fad388b35..e8abc71dd 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -2229,7 +2229,9 @@ class ConstVisitor final : public VNVisitor {
             && !VN_IS(nodep, AssignDly)) {
             // X = X.  Quite pointless, though X <= X may override another earlier assignment
             if (VN_IS(nodep, AssignW)) {
-                nodep->v3error("Wire inputs its own output, creating circular logic (wire x=x)");
+                if (!v3Global.opt.pedantic())
+                    nodep->v3error(
+                        "Wire inputs its own output, creating circular logic (wire x=x)");
                 return false;  // Don't delete the assign, or V3Gate will freak out
             } else {
                 VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
diff --git a/test_regress/t/t_dist_warn_coverage.py b/test_regress/t/t_dist_warn_coverage.py
index ea7e24054..8d4a15dc8 100755
--- a/test_regress/t/t_dist_warn_coverage.py
+++ b/test_regress/t/t_dist_warn_coverage.py
@@ -134,7 +134,6 @@ for s in [
         'Unsupported: Size-changing cast on non-basic data type',
         'Unsupported: Slice of non-constant bounds',
         'Unsupported: Stream operation on a variable of a type',
-        'Unsupported: Unclocked assertion',
         'Unsupported: Using --protect-ids with public function',
         'Unsupported: Verilog 1995 gate primitive:',
         'Unsupported: [] dimensions',
@@ -153,7 +152,6 @@ for s in [
         'Unsupported: super',
         'Unsupported: with[] stream expression',
         'expected non-complex non-double',
-        'is not an unpacked array, but is in an unpacked array context',
         'loading other than unpacked-array variable',
         'loading other than unpacked/associative-array variable',
 ]:
diff --git a/test_regress/t/t_lint_wireloop.py b/test_regress/t/t_lint_wireloop.py
new file mode 100755
index 000000000..31f0b97e4
--- /dev/null
+++ b/test_regress/t/t_lint_wireloop.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator_st')
+
+test.compile(verilator_flags2=['--binary --Wpedantic'])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_lint_wireloop.v b/test_regress/t/t_lint_wireloop.v
new file mode 100644
index 000000000..3765d2023
--- /dev/null
+++ b/test_regress/t/t_lint_wireloop.v
@@ -0,0 +1,11 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Wilson Snyder
+// SPDX-License-Identifier: CC0-1.0
+
+module t;
+  wire w;
+  assign w = w;
+  initial $finish;
+endmodule
diff --git a/test_regress/t/t_lint_wireloop_bad.out b/test_regress/t/t_lint_wireloop_bad.out
new file mode 100644
index 000000000..e92a86d09
--- /dev/null
+++ b/test_regress/t/t_lint_wireloop_bad.out
@@ -0,0 +1,5 @@
+%Error: t/t_lint_wireloop.v:9:12: Wire inputs its own output, creating circular logic (wire x=x)
+    9 |   assign w = w;
+      |            ^
+        ... See the manual at https://verilator.org/verilator_doc.html?v=latest for more assistance.
+%Error: Exiting due to
diff --git a/test_regress/t/t_lint_wireloop_bad.py b/test_regress/t/t_lint_wireloop_bad.py
new file mode 100755
index 000000000..856ce0c92
--- /dev/null
+++ b/test_regress/t/t_lint_wireloop_bad.py
@@ -0,0 +1,17 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2024 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+test.top_filename = "t/t_lint_wireloop.v"
+
+test.lint(fails=True, expect_filename=test.golden_filename)
+
+test.passes()