diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 2f85156be..641e57355 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -2889,9 +2889,9 @@ class LinkDotResolveVisitor final : public VNVisitor {
             VSymEnt* const foundp = m_pinSymp->findIdFlat(nodep->name());
             const char* const whatp = nodep->param() ? "parameter" : "pin";
             if (!foundp) {
-                if (nodep->name() == "__paramNumber1" && m_cellp
-                    && VN_IS(m_cellp->modp(), Primitive)) {
-                    // Primitive parameter is really a delay we can just ignore
+                if (m_cellp && VN_IS(m_cellp->modp(), Primitive)
+                    && (nodep->name() == "__paramNumber1" || nodep->name() == "__paramNumber2")) {
+                    // Primitive parameter is really a delay2 we can just ignore
                     VL_DO_DANGLING(pushDeletep(nodep->unlinkFrBack()), nodep);
                     return;
                 } else {
diff --git a/test_regress/t/t_udp_delay.py b/test_regress/t/t_udp_delay.py
new file mode 100755
index 000000000..055e14291
--- /dev/null
+++ b/test_regress/t/t_udp_delay.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('linter')
+
+test.compile()
+
+test.passes()
diff --git a/test_regress/t/t_udp_delay.v b/test_regress/t/t_udp_delay.v
new file mode 100644
index 000000000..238a514ab
--- /dev/null
+++ b/test_regress/t/t_udp_delay.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+primitive not_u(out, in);
+  output out;
+  input in;
+  table
+    0 : 1;
+    1 : 0;
+  endtable
+endprimitive
+
+module t (out, in);
+  input in;
+  output wire out;
+  real v = 0.34;
+  not_u #(1.145, v) dut_u (out, in);
+endmodule