diff --git a/.travis.yml b/.travis.yml index dd59d6f58..b0623c38c 100644 --- a/.travis.yml +++ b/.travis.yml @@ -1,8 +1,10 @@ # DESCRIPTION: Travis-CI config # -# Copyright 2003-2019 by Todd Strader. Verilator is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 version: ~> 1.0 diff --git a/Changes b/Changes index a83afa729..719aa2d10 100644 --- a/Changes +++ b/Changes @@ -3,6 +3,35 @@ Revision history for Verilator The contributors that suggested a given feature are shown in []. Thanks! +* Verilator 4.032 2020-04-04 + +*** Add column numbers to errors and warnings. + +*** Add GCC 9-style line number prefix when showing source text for errors. + +*** Add setting VM_PARALLEL_BUILDS=1 when using --output-split, #2185. + +*** Change --quiet-exit to also suppress 'Exiting due to N errors'. + +**** Suppress REALCVT for whole real numbers. + +**** Support split_var in vlt files, #2219. [Marco Widmer] + +**** Fix parameter type redeclaring a type, #2195. [hdzhangdoc] + +**** Fix VCD open with empty filename, #2198. [Julius Baxter] + +**** Fix packages as enum base types, #2202. [Driss Hafdi] + +**** Fix duplicate typedefs in generate for, #2205. [hdzhangdoc] + +**** Fix MinW portability, #2114. [Sean Cross] + +**** Fix assertions with unique case inside, #2199. [hdzhangdoc] + +**** Fix implicit conversion of floats to wide integers. + + * Verilator 4.030 2020-03-08 ** Add split_var metacomment to assist UNOPTFLAT fixes, #2066. [Yutetsu TAKATSUKASA] @@ -3538,10 +3567,11 @@ of input ports exists for tracing. This uses outline mode in Emacs. See C-h m [M-x describe-mode]. -Copyright 2001-2020 by Wilson Snyder. This program is free software; you +Copyright 2001-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 Local variables: mode: outline diff --git a/MANIFEST.SKIP b/MANIFEST.SKIP index c0d696663..97f2a9fa3 100644 --- a/MANIFEST.SKIP +++ b/MANIFEST.SKIP @@ -28,7 +28,7 @@ /obj_vcs/ /obj_vlt/ /obj_vltmt/ -/INCA_libs/ +INCA_libs/ /cov_work/ /logs/ ^Makefile$ @@ -37,6 +37,7 @@ bin/verilator_bin.* bin/verilator_coverage_bin.* docs/.*\.html$ docs/Makefile$ +docs/clang-format.txt$ docs/doxygen-doc/.* examples/xml_py/copied/ examples/xml_py/graph.* diff --git a/Makefile.in b/Makefile.in index 6f7441743..f9d9bffad 100644 --- a/Makefile.in +++ b/Makefile.in @@ -7,15 +7,11 @@ # #***************************************************************************** # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# Verilator is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ # diff --git a/bin/verilator b/bin/verilator index b321db9e7..68c42e97e 100755 --- a/bin/verilator +++ b/bin/verilator @@ -5,11 +5,7 @@ # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### @@ -1083,8 +1079,8 @@ and the remaining files can be compiled on parallel machines. Using design --output-split 20000 resulted in splitting into approximately one-minute-compile chunks. -Typically when using this, make with VM_PARALLEL_BUILDS=1, and use -I. +Typically when using this, make with VM_PARALLEL_BUILDS=1 (set for you if +using the default makefiles), and use I. =item --output-split-cfuncs I @@ -1273,7 +1269,8 @@ detailed description. =item --quiet-exit -When exiting due to an error, do not display the "Command Failed" message. +When exiting due to an error, do not display the "Exiting due to Errors" +nor "Command Failed" messages. =item --relative-includes @@ -2855,7 +2852,7 @@ and range of line numbers (or all lines if omitted). For tracing_off, cells below any module in the files/ranges specified will also not be traced. -=item clock_enable -module "" -signal "" +=item clock_enable -module "" -var "" Indicate the signal is used to gate a clock, and the user takes responsibility for insuring there are no races related to it. @@ -2863,13 +2860,13 @@ for insuring there are no races related to it. Same as /*verilator clock_enable*/, see L for more information and an example. -=item clocker -module "" [-task ""] -signal "" +=item clocker -module "" [-task ""] -var "" -=item clocker -module "" [-function ""] -signal "" +=item clocker -module "" [-function ""] -var "" -=item no_clocker -module "" [-task ""] -signal "" +=item no_clocker -module "" [-task ""] -var "" -=item no_clocker -module "" [-function ""] -signal "" +=item no_clocker -module "" [-function ""] -var "" Indicate the signal is used as clock or not. This information is used by Verilator to mark the signal as clocker and propagate the clocker attribute @@ -2911,9 +2908,9 @@ routines will replace the __DOT__ with the period. Same as /*verilator inline_module*/, see L for more information. -=item isolate_assignments -module "" [-task ""] -signal "" +=item isolate_assignments -module "" [-task ""] -var "" -=item isolate_assignments -module "" [-function ""] -signal "" +=item isolate_assignments -module "" [-function ""] -var "" =item isolate_assignments -module "" -function "" @@ -2948,9 +2945,9 @@ outside the task itself. Same as /*verilator no_inline_task*/, see L for more information. -=item sc_bv -module "" [-task ""] -signal "" +=item sc_bv -module "" [-task ""] -var "" -=item sc_bv -module "" [-function ""] -signal "" +=item sc_bv -module "" [-function ""] -var "" Sets the port to be of sc_bv> type, instead of bool, vluint32_t or vluint64_t. This may be useful if the port width is parameterized and @@ -2962,9 +2959,9 @@ significantly. Same as /*verilator sc_bv*/, see L for more information. -=item sformat [-module ""] [-task ""] -signal "" +=item sformat [-module ""] [-task ""] -var "" -=item sformat [-module ""] [-function ""] -signal "" +=item sformat [-module ""] [-function ""] -var "" Final input of a function or task "input string" to indicate the function or task should pass all remaining arguments through @@ -2974,6 +2971,17 @@ behavior. See the test_regress/t/t_dpi_display.v file for an example. Same as /*verilator sformat*/, see L for more information. +=item split_var [-module ""] [-task ""] -var "" + +=item split_var [-module ""] [-function ""] -var "" + +Break the variable into multiple pieces typically to resolve UNOPTFLAT +performance issues. Typically the variables to attach this to are +recommeded by Verilator itself, see UNOPTFLAT. + +Same as /*verilator split_var*/, see L for more +information. + =back @@ -3487,6 +3495,9 @@ requested but cannot occur a SPLITVAR warning is issued. Splitting large arrays may slow donw the Verilation speed, so use this only on variables that require it. +Same as C in configuration files, see L +for more information. + =item /*verilator tag */ Attached after a variable or structure member to indicate opaque (to @@ -3914,7 +3925,24 @@ checking across the designs, and prevents other users from compiling your code without knowing the magic set of disables needed to successfully compile your design. -List of all warnings: +=head2 Error and Warning Format + +Warnings and errors printed by Verilator always match this regular +expression: + + %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.* + +Errors and warning start with a percent sign (historical heritage from +Digital Equipment Corporation). Some errors or warning have a code +attached, with meanings described below. Some errors also have a filename, +line number and optional column number (starting at column 1 to match GCC). + +Following an the error message, Verilator will typically show the user's +source code corresponding to the error, prefixed by the line number and a " +| ". Following this is typically an arrow and ~ pointing at the error on +the source line directly above. + +=head2 List of all warnings =over 4 @@ -5359,15 +5387,15 @@ remain anonymous. The latest version is available from L. -Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you can +Copyright 2003-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify the Verilator internals under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. All Verilog and C++/SystemC code quoted within this documentation file are -released into the Public Domain. Many example files and test files are -likewise released into the Public Domain as described in the files -themselves. +released as Creative Commons Public Domain (CC0). Many example files and +test files are likewise released under CC0 into effectively the Public +Domain as described in the files themselves. =head1 SEE ALSO diff --git a/bin/verilator_coverage b/bin/verilator_coverage index 13701b660..37b931c29 100755 --- a/bin/verilator_coverage +++ b/bin/verilator_coverage @@ -6,11 +6,6 @@ # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# ###################################################################### require 5.006_001; @@ -269,10 +264,12 @@ Specifies a module search directory. The latest version is available from L. -Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify the Verilator internals under the terms of -either the GNU Lesser General Public License Version 3 or the Perl Artistic -License Version 2.0. +Copyright 2003-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify the Verilator internals under the terms +of either the GNU Lesser General Public License Version 3 or the Perl +Artistic License Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/bin/verilator_difftree b/bin/verilator_difftree index a7aab372b..4fefebdd6 100755 --- a/bin/verilator_difftree +++ b/bin/verilator_difftree @@ -233,9 +233,12 @@ Do not show differences in line numbering. The latest version is available from L. -Copyright 2005-2020 by Wilson Snyder. This package is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2005-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 574d01567..ddd7f2434 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -538,9 +538,12 @@ verilator_gantt.vcd. The latest version is available from L. -Copyright 2018-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2018-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/bin/verilator_includer b/bin/verilator_includer index 83e05f2ed..182d2f7d7 100755 --- a/bin/verilator_includer +++ b/bin/verilator_includer @@ -1,9 +1,11 @@ #!/usr/bin/env perl # DESCRIPTION: Print include statements for each ARGV # -# Copyright 2003-2020 by Wilson Snyder. This package is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### require 5.005; diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index 85523163d..f69a5124b 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -228,9 +228,12 @@ Displays this message and program version and exits. The latest version is available from L. -Copyright 2007-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2007-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/ci/build_vcddiff.sh b/ci/build_vcddiff.sh index 9a0e8b6da..f4eca15fd 100755 --- a/ci/build_vcddiff.sh +++ b/ci/build_vcddiff.sh @@ -1,10 +1,11 @@ #!/bin/bash # DESCRIPTION: Verilator: Build script for vcddiff # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 set -e # NB: it would be better to add this via a PPA diff --git a/ci/build_verilator.sh b/ci/build_verilator.sh index cd1d7d558..3ae363bf7 100755 --- a/ci/build_verilator.sh +++ b/ci/build_verilator.sh @@ -1,10 +1,11 @@ #!/bin/bash # DESCRIPTION: Verilator: Travis CI build script # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # # This script builds and caches the Verilator binaries for Travis CI # (and possibly other CI platforms). The Verilator CI system uses this diff --git a/ci/docker/buildenv/Dockerfile b/ci/docker/buildenv/Dockerfile index e634b300d..7243d30d2 100644 --- a/ci/docker/buildenv/Dockerfile +++ b/ci/docker/buildenv/Dockerfile @@ -1,9 +1,10 @@ # DESCRIPTION: Dockerfile for env to build and fully test Verilator # -# Copyright 2020 by Stefan Wallentowitz. This program is free -# software; you can redistribute it and/or modify it under the terms -# of either the GNU Lesser General Public License Version 3 or the -# Perl Artistic License Version 2.0. +# Copyright 2020 by Stefan Wallentowitz. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 FROM ubuntu:18.04 diff --git a/ci/docker/buildenv/README.adoc b/ci/docker/buildenv/README.adoc index edb3e2b5a..c4747c890 100644 --- a/ci/docker/buildenv/README.adoc +++ b/ci/docker/buildenv/README.adoc @@ -1,7 +1,7 @@ -= Verilator Build Environment += Verilator Docker Build Environment -This container is set up to compile and test a Verilator build based -on the following parameters: +This Verilator Build container is set up to compile and test a Verilator +build. It uses the following parameters: * Source repository (default: https://github.com/verilator/verilator) * Source revision (default: master) @@ -10,7 +10,7 @@ on the following parameters: The container is published as `verilator/verilator-buildenv` on https://hub.docker.com/repository/docker/verilator/verilator-buildenv[docker hub]. -To run the basic build of current master: +To run the basic build using the current Verilator master: docker run -ti verilator/verilator-buildenv @@ -18,7 +18,7 @@ To also run tests: docker run -ti verilator/verilator-buildenv test -Change the compiler: +To change the compiler: docker run -ti -e CC=gcc-4.8 -e CXX=g++-4.8 verilator/verilator-buildenv test @@ -29,22 +29,21 @@ To run those too: docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` -e CC=gcc-4.8 -e CXX=g++-4.8 --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test .... -You may want to avoid pushing your changes to a remote repository and -instead use a local working copy. You can mount the local working copy -path as a volume and use this as repo. Be careful, that it can only -use committed changes, so you may want to use a work-in-progress -commit or so. To build the current HEAD from top of a repository: +Rather then building using a remote git repository you may prefer to use a +working copy on the local filesystem. Mount the local working copy path as +a volume and use that in place of git. When doing this be careful to have +all changes committed to the local git area. To build the current HEAD from +top of a repository: .... docker run -ti -v ${PWD}:/tmp/repo -e REPO=/tmp/repo -e REV=`git rev-parse --short HEAD` --cap-add=SYS_PTRACE --security-opt seccomp=unconfined verilator/verilator-buildenv test .... -== Under the Hood +== Rebuilding -To rebuild the image, simply run: +To rebuild the Verilator-buildenv docker image, run: docker build . -It will build SystemC in all supported compiler variants to reduce the -impact on testing cycles. A build script will be the entrypoint to the -container that will perform a standard build and test procedure. +This will also build SystemC under all supported compiler variants to +reduce the SystemC testing time. diff --git a/ci/docker/buildenv/build-systemc.sh b/ci/docker/buildenv/build-systemc.sh index ee4630977..0500e8ff3 100755 --- a/ci/docker/buildenv/build-systemc.sh +++ b/ci/docker/buildenv/build-systemc.sh @@ -1,10 +1,11 @@ #!/bin/bash -e # DESCRIPTION: Build SystemC in Ubuntu 18.04 with different g++/gcc # -# Copyright 2020 by Stefan Wallentowitz. This program is free -# software; you can redistribute it and/or modify it under the terms -# of either the GNU Lesser General Public License Version 3 or the -# Perl Artistic License Version 2.0. +# Copyright 2020 by Stefan Wallentowitz. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 build_variant () { version=$($1 --version | grep gcc | awk '{print $4}') diff --git a/ci/docker/buildenv/build.sh b/ci/docker/buildenv/build.sh index e79f69f91..f48c1c80b 100755 --- a/ci/docker/buildenv/build.sh +++ b/ci/docker/buildenv/build.sh @@ -1,10 +1,11 @@ #!/bin/bash -e # DESCRIPTION: Build Verilator (inside container) # -# Copyright 2020 by Stefan Wallentowitz. This program is free -# software; you can redistribute it and/or modify it under the terms -# of either the GNU Lesser General Public License Version 3 or the -# Perl Artistic License Version 2.0. +# Copyright 2020 by Stefan Wallentowitz. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 : "${REPO:=https://github.com/verilator/verilator}" : "${REV:=master}" diff --git a/ci/docker/run/Dockerfile b/ci/docker/run/Dockerfile index 7f7995009..315123203 100644 --- a/ci/docker/run/Dockerfile +++ b/ci/docker/run/Dockerfile @@ -1,9 +1,10 @@ # DESCRIPTION: Dockerfile for image to run Verilator inside # -# Copyright 2020 by Stefan Wallentowitz. This program is free -# software; you can redistribute it and/or modify it under the terms -# of either the GNU Lesser General Public License Version 3 or the -# Perl Artistic License Version 2.0. +# Copyright 2020 by Stefan Wallentowitz. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 FROM ubuntu:18.04 diff --git a/ci/docker/run/README.adoc b/ci/docker/run/README.adoc index 82793b878..84321ac06 100644 --- a/ci/docker/run/README.adoc +++ b/ci/docker/run/README.adoc @@ -1,49 +1,59 @@ -= Docker Container as Verilator executable += Verilator Executable Docker Container -This allows you to run Verilator easily as a docker image, e.g.: +The Verilator Executable Docker Container allows you to run Verilator +easily as a docker image, e.g.: docker run -ti verilator/verilator:latest --version -This is in particular useful to compare against older version or to -check when an issue was introduced. +This will install the container, run the latest Verilator and print +Verilator's version. -You will need to give it access to your files as a volume and fix the -user rights: +Containers are automatically built for all released versions, so you may +easily compare results across versions, e.g.: + + docker run -ti verilator/verilator:4.030 --version + +Verilator needs to read and write files on the local system. To simplify +this process, use the `verilator-docker` convenience script. This script +takes the version number, and all remaining arguments are passed through to +Verilator. e.g.: + + ./verilator-docker 4.030 --version + +or + + ./verilator-docker 4.030 --cc test.v + +If you prefer not to use `verilator-docker` you must give the container +access to your files as a volume with appropriate user rights. For example +to Verilate test.v: .... docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:latest --cc test.v .... -The caveat is that it can only access files below the current -directory then, a workaround is to adopt the volume and set -`-workdir`. +This method can only access files below the current directory. An +alternative is setup the volume `-workdir`. -There is a convenience script in this folder that wraps around the -docker calls: - - $ verilator-docker 3.922 --version - Verilator 3.922 2018-03-17 rev UNKNOWN_REV - -Finally, you can also work in the container by setting the entrypoint +You can also work in the container by setting the entrypoint (don't forget to mount a volume if you want your work persistent): docker run -ti --entrypoint /bin/bash verilator/verilator:latest -The other files in this folder all for building the containers and to -store in them. You could use it to build Verilator at a specific +You can also use the container to build Verilator at a specific commit: docker build --build-arg SOURCE_COMMIT= . == Internals -The Dockerfile is pretty straight-forward, it builds Verilator and -removes the tree after that to reduce the image size. It sets a -wrapper script (`verilator-wrap.sh`) as entrypoint. This script calls -Verilator but also copies the verilated runtime files to the `obj_dir` -or the `-Mdir` respectively. This allows the user to build the C++ -output with the matching runtime files. The wrapper patches the -generated Makefile accordingly. +The Dockerfile builds Verilator and removes the tree when completed to +reduce the image size. The entrypoint is set as a wrapper script +(`verilator-wrap.sh`). That script 1. calls Verilator, and 2. copies the +Verilated runtime files to the `obj_dir` or the `-Mdir` respectively. This +allows the user to have the files to they may later build the C++ output +with the matching runtime files. The wrapper also patches the Verilated +Makefile accordingly. There is also a hook defined that is run by docker hub via automated builds. diff --git a/ci/docker/run/hooks/build b/ci/docker/run/hooks/build index 5a6d609d5..6d2290cae 100644 --- a/ci/docker/run/hooks/build +++ b/ci/docker/run/hooks/build @@ -1,9 +1,10 @@ #!/bin/bash # DESCRIPTION: Docker hub hook to pass SOURCE_COMMIT # -# Copyright 2020 by Stefan Wallentowitz. This program is free -# software; you can redistribute it and/or modify it under the terms -# of either the GNU Lesser General Public License Version 3 or the -# Perl Artistic License Version 2.0.FROM ubuntu:18.04 +# Copyright 2020 by Stefan Wallentowitz. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 docker build --build-arg SOURCE_COMMIT=${SOURCE_COMMIT} -f $DOCKERFILE_PATH -t $IMAGE_NAME . diff --git a/ci/docker/run/hooks/post_push b/ci/docker/run/hooks/post_push index 8a12ed478..256e85008 100755 --- a/ci/docker/run/hooks/post_push +++ b/ci/docker/run/hooks/post_push @@ -1,10 +1,11 @@ #!/bin/bash # DESCRIPTION: Docker hub hook to tag the latest release (stable) # -# Copyright 2020 by Stefan Wallentowitz. This program is free -# software; you can redistribute it and/or modify it under the terms -# of either the GNU Lesser General Public License Version 3 or the -# Perl Artistic License Version 2.0.FROM ubuntu:18.04 +# Copyright 2020 by Stefan Wallentowitz. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 if [ "$SOURCE_BRANCH"="stable" ]; then docker tag $IMAGE_NAME $DOCKER_REPO:latest diff --git a/ci/docker/run/verilator-docker b/ci/docker/run/verilator-docker index ceb47df9f..9648c2903 100755 --- a/ci/docker/run/verilator-docker +++ b/ci/docker/run/verilator-docker @@ -1,10 +1,11 @@ #!/bin/bash # DESCRIPTION: Wrap a verilator call to run a docker container # -# Copyright 2020 by Stefan Wallentowitz. This program is free -# software; you can redistribute it and/or modify it under the terms -# of either the GNU Lesser General Public License Version 3 or the -# Perl Artistic License Version 2.0. +# Copyright 2020 by Stefan Wallentowitz. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 docker pull verilator/verilator:$1 >/dev/null docker run -ti -v ${PWD}:/work --user $(id -u):$(id -g) verilator/verilator:$1 "${@:2}" diff --git a/ci/docker/run/verilator-wrap.sh b/ci/docker/run/verilator-wrap.sh index 69de6e768..aa7a3be60 100755 --- a/ci/docker/run/verilator-wrap.sh +++ b/ci/docker/run/verilator-wrap.sh @@ -1,13 +1,18 @@ -#!/bin/bash -e +#!/bin/bash # DESCRIPTION: Wrap a Verilator call and copy vlt includes # (inside docker container) # -# Copyright 2020 by Stefan Wallentowitz. This program is free -# software; you can redistribute it and/or modify it under the terms -# of either the GNU Lesser General Public License Version 3 or the -# Perl Artistic License Version 2.0. +# Copyright 2020 by Stefan Wallentowitz. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 perl /usr/local/bin/verilator "$@" +status=$? +if [ $status -ne 0 ]; then + exit $status +fi # Check if user set an obj_dir obj_dir=$(echo " $@" | grep -oP '\s--Mdir\s*\K\S+') diff --git a/ci/test.sh b/ci/test.sh index 361a198d7..fbac24b6c 100755 --- a/ci/test.sh +++ b/ci/test.sh @@ -1,10 +1,12 @@ #!/bin/bash # DESCRIPTION: Verilator: Travis CI test script # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + set -e export DRIVER_FLAGS='-j 0 --quiet --rerun' diff --git a/configure.ac b/configure.ac index c3d87cbd1..23ec1a6e1 100644 --- a/configure.ac +++ b/configure.ac @@ -1,12 +1,13 @@ # DESCRIPTION: Process this file with autoconf to produce a configure script. # -# Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser +# Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you +# can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[4.030 2020-03-08], +AC_INIT([Verilator],[4.032 2020-04-04], [https://verilator.org], [verilator],[https://verilator.org]) # When releasing, also update header of Changes file @@ -301,7 +302,6 @@ AC_SUBST(CFG_CXXFLAGS_WEXTRA) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Qunused-arguments) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-faligned-new) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-unused-parameter) -_MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-undefined-bool-conversion) _MY_CXX_CHECK_OPT(CFG_CXXFLAGS_SRC,-Wno-shadow) AC_SUBST(CFG_CXXFLAGS_SRC) @@ -369,8 +369,13 @@ AC_SUBST(CFG_LDFLAGS_SRC) # The pthread library is required by tcmalloc, so add it if it exists. If it # does not, the tcmalloc check below will fail anyway, and linking against # pthreads is harmless otherwise. +CFG_LIBS="$LIBS $CFG_LIBS" _MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpthread) +# Check libraries for MingW +_MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lbcrypt) +_MY_LDLIBS_CHECK_OPT(CFG_LIBS, -lpsapi) + # Check if tcmalloc is available based on --enable-tcmalloc _MY_LDLIBS_CHECK_IFELSE( $LTCMALLOC, diff --git a/docs/CONTRIBUTING.adoc b/docs/CONTRIBUTING.adoc index 2770d8136..e205d80b0 100644 --- a/docs/CONTRIBUTING.adoc +++ b/docs/CONTRIBUTING.adoc @@ -50,13 +50,13 @@ contributions flow more efficiently. link:CONTRIBUTORS[docs/CONTRIBUTORS] and you are agreeing all future contributions are also certified. -** We occasionally accept contributions where people do not want their - name published. Please email us; you must still certify your - contribution using email. +** We occasionally accept contributions where people do not want their name + published. Please email us; you must still privately certify your + contribution. -* Your test contributions are generally considered released into the public - domain, unless you request otherwise or put a GNU/Artistic license on - your test file. +* Your test contributions are generally considered released into the + Creative Commons Public Domain (CC0), unless you request otherwise or put + a GNU/Artistic license on your file. * Most important is we get your patch. If you'd like to clean up indentation and related issues ahead of our feedback, that is diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 8c6c42276..0060aa607 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -8,6 +8,7 @@ all. Ahmed El-Mahmoudy Alex Chadwick Chris Randall +David Stanford Driss Hafdi Eric Rippey Garrett Smith @@ -23,6 +24,8 @@ Kevin Kiningham Kuba Ober Lukasz Dalek Maarten De Braekeleer +Maciej Sobkowski +Marco Widmer Matthew Ballance Mike Popoloski Patrick Stewart @@ -30,6 +33,7 @@ Peter Monsson Philipp Wagner Pieter Kapsenberg Richard Myers +Sean Cross Sebastien Van Cauwenberghe Stefan Wallentowitz Tobias Rosenkranz @@ -38,4 +42,3 @@ Todd Strader Wilson Snyder Yutetsu TAKATSUKASA Yves Mathieu -David Stanford diff --git a/docs/Makefile.in b/docs/Makefile.in index a2aa53a0c..3f68f1ebb 100644 --- a/docs/Makefile.in +++ b/docs/Makefile.in @@ -7,15 +7,11 @@ # #***************************************************************************** # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# Verilator is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ # diff --git a/docs/TODO b/docs/TODO index 72b7c13a1..357a15b28 100644 --- a/docs/TODO +++ b/docs/TODO @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 * Language support: ** Fix ordering of each bit separately in a signal (mips) @@ -22,17 +23,10 @@ ** Assertions ** Tristate support -* Configure/Make/Install -** Distribute with flex/bison already expanded? - Flex library not needed. Probably too difficult to be worth it. - * Testing: -** Capture all inputs into global "rerun it" file ** Code to make wrapper that sets signals, so can do comparison checks ** New random program generator ** Better graph viewer with search and zoom -** Port and test against opencores.org code -** // verilator debug in code so can see only tree affecting those nodes * Usability: ** Detect and pre-remove most UNOPTFLATs diff --git a/docs/clang-format.txt b/docs/clang-format.txt new file mode 100644 index 000000000..3a1876b64 --- /dev/null +++ b/docs/clang-format.txt @@ -0,0 +1,159 @@ +clang-format is used to standardize the indentation of the internal C++ +code. + +For the most part clang-format changes provide good consistency, the two +main exceptions being the indentation of preprocessor directives, and +tables of statements. + +Reformatting is generally performed only before other large changes are to +be made to a file. The following files are not yet clang-format clean: + +clang-format -i include/verilated.h +clang-format -i include/verilated_dpi.h +clang-format -i include/verilated_fst_c.h +clang-format -i include/verilated_heavy.h +clang-format -i include/verilated_imp.h +clang-format -i include/verilated_save.h +clang-format -i include/verilated_sym_props.h +clang-format -i include/verilated_unordered_set_map.h +clang-format -i include/verilated_vcd_c.h +clang-format -i include/verilatedos.h + +clang-format -i include/verilated.cpp +clang-format -i include/verilated_cov.cpp +clang-format -i include/verilated_dpi.cpp +clang-format -i include/verilated_fst_c.cpp +clang-format -i include/verilated_save.cpp +clang-format -i include/verilated_threads.cpp +clang-format -i include/verilated_vcd_c.cpp +clang-format -i include/verilated_vpi.cpp + +clang-format -i src/V3Ast.h +clang-format -i src/V3AstNodes.h +clang-format -i src/V3EmitCBase.h +clang-format -i src/V3Error.h +clang-format -i src/V3File.h +clang-format -i src/V3FileLine.h +clang-format -i src/V3Global.h +clang-format -i src/V3Graph.h +clang-format -i src/V3GraphDfa.h +clang-format -i src/V3GraphStream.h +clang-format -i src/V3Hashed.h +clang-format -i src/V3LanguageWords.h +clang-format -i src/V3LinkDot.h +clang-format -i src/V3List.h +clang-format -i src/V3Number.h +clang-format -i src/V3Options.h +clang-format -i src/V3OrderGraph.h +clang-format -i src/V3Os.h +clang-format -i src/V3ParseImp.h +clang-format -i src/V3ParseSym.h +clang-format -i src/V3Partition.h +clang-format -i src/V3PartitionGraph.h +clang-format -i src/V3PreLex.h +clang-format -i src/V3PreProc.h +clang-format -i src/V3Scoreboard.h +clang-format -i src/V3SenTree.h +clang-format -i src/V3Simulate.h +clang-format -i src/V3Stats.h +clang-format -i src/V3String.h +clang-format -i src/V3SymTable.h +clang-format -i src/V3TSP.h +clang-format -i src/V3Task.h +clang-format -i src/V3WidthCommit.h + +clang-format -i src/V3Active.cpp +clang-format -i src/V3ActiveTop.cpp +clang-format -i src/V3Assert.cpp +clang-format -i src/V3AssertPre.cpp +clang-format -i src/V3Ast.cpp +clang-format -i src/V3AstNodes.cpp +clang-format -i src/V3Begin.cpp +clang-format -i src/V3Branch.cpp +clang-format -i src/V3Broken.cpp +clang-format -i src/V3CCtors.cpp +clang-format -i src/V3Case.cpp +clang-format -i src/V3Cast.cpp +clang-format -i src/V3Cdc.cpp +clang-format -i src/V3Changed.cpp +clang-format -i src/V3Clean.cpp +clang-format -i src/V3Clock.cpp +clang-format -i src/V3Combine.cpp +clang-format -i src/V3Const.cpp +clang-format -i src/V3Coverage.cpp +clang-format -i src/V3CoverageJoin.cpp +clang-format -i src/V3Dead.cpp +clang-format -i src/V3Delayed.cpp +clang-format -i src/V3Depth.cpp +clang-format -i src/V3DepthBlock.cpp +clang-format -i src/V3EmitC.cpp +clang-format -i src/V3EmitCInlines.cpp +clang-format -i src/V3EmitCMake.cpp +clang-format -i src/V3EmitCSyms.cpp +clang-format -i src/V3EmitMk.cpp +clang-format -i src/V3EmitV.cpp +clang-format -i src/V3EmitXml.cpp +clang-format -i src/V3Error.cpp +clang-format -i src/V3Expand.cpp +clang-format -i src/V3File.cpp +clang-format -i src/V3FileLine.cpp +clang-format -i src/V3Gate.cpp +clang-format -i src/V3GenClk.cpp +clang-format -i src/V3Graph.cpp +clang-format -i src/V3GraphAcyc.cpp +clang-format -i src/V3GraphAlg.cpp +clang-format -i src/V3GraphDfa.cpp +clang-format -i src/V3GraphPathChecker.cpp +clang-format -i src/V3GraphTest.cpp +clang-format -i src/V3Hashed.cpp +clang-format -i src/V3Inline.cpp +clang-format -i src/V3Inst.cpp +clang-format -i src/V3InstrCount.cpp +clang-format -i src/V3Life.cpp +clang-format -i src/V3LifePost.cpp +clang-format -i src/V3LinkCells.cpp +clang-format -i src/V3LinkDot.cpp +clang-format -i src/V3LinkJump.cpp +clang-format -i src/V3LinkLValue.cpp +clang-format -i src/V3LinkLevel.cpp +clang-format -i src/V3LinkParse.cpp +clang-format -i src/V3LinkResolve.cpp +clang-format -i src/V3Localize.cpp +clang-format -i src/V3Name.cpp +clang-format -i src/V3Number.cpp +clang-format -i src/V3Number_test.cpp +clang-format -i src/V3Options.cpp +clang-format -i src/V3Order.cpp +clang-format -i src/V3Os.cpp +clang-format -i src/V3Param.cpp +clang-format -i src/V3ParseGrammar.cpp +clang-format -i src/V3ParseImp.cpp +clang-format -i src/V3ParseLex.cpp +clang-format -i src/V3Partition.cpp +clang-format -i src/V3PreProc.cpp +clang-format -i src/V3PreShell.cpp +clang-format -i src/V3Premit.cpp +clang-format -i src/V3ProtectLib.cpp +clang-format -i src/V3Reloop.cpp +clang-format -i src/V3Scope.cpp +clang-format -i src/V3Scoreboard.cpp +clang-format -i src/V3Slice.cpp +clang-format -i src/V3Split.cpp +clang-format -i src/V3SplitAs.cpp +clang-format -i src/V3SplitVar.cpp +clang-format -i src/V3Stats.cpp +clang-format -i src/V3StatsReport.cpp +clang-format -i src/V3String.cpp +clang-format -i src/V3Subst.cpp +clang-format -i src/V3TSP.cpp +clang-format -i src/V3Table.cpp +clang-format -i src/V3Task.cpp +clang-format -i src/V3Trace.cpp +clang-format -i src/V3TraceDecl.cpp +clang-format -i src/V3Tristate.cpp +clang-format -i src/V3Undriven.cpp +clang-format -i src/V3Unknown.cpp +clang-format -i src/V3Unroll.cpp +clang-format -i src/V3Width.cpp +clang-format -i src/V3WidthSel.cpp +clang-format -i src/Verilator.cpp diff --git a/docs/install.adoc b/docs/install.adoc index 09a74c516..8add7f3c1 100644 --- a/docs/install.adoc +++ b/docs/install.adoc @@ -303,3 +303,4 @@ or https://verilator.org/verilator_doc.pdf[Verilator manual (PDF)]. Copyright 2008-2020 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/docs/internals.adoc b/docs/internals.adoc index 55d5e407a..eec37389c 100644 --- a/docs/internals.adoc +++ b/docs/internals.adoc @@ -998,3 +998,4 @@ list in `src/Makefile_obj.in` and reconfigure. Copyright 2008-2020 by Wilson Snyder. Verilator is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/docs/xml.adoc b/docs/xml.adoc index a501095d8..3dabedc02 100644 --- a/docs/xml.adoc +++ b/docs/xml.adoc @@ -63,3 +63,10 @@ each describing the contents of that module, and a single ``... `` element which lists all used types used within the modules. Each type has a numeric `id` attribute that is referred to by elements in the `` elements using the `dtype_id` attribute. + +== Distribution + +Copyright 2020-2020 by Wilson Snyder. Verilator is free software; you can +redistribute it and/or modify it under the terms of either the GNU Lesser +General Public License Version 3 or the Perl Artistic License Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/examples/cmake_hello_c/CMakeLists.txt b/examples/cmake_hello_c/CMakeLists.txt index 82c4707ff..e657d627b 100644 --- a/examples/cmake_hello_c/CMakeLists.txt +++ b/examples/cmake_hello_c/CMakeLists.txt @@ -5,10 +5,11 @@ # This is an example cmake script to build a verilog to systemc project # using cmake and verilator. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/cmake_hello_c/Makefile b/examples/cmake_hello_c/Makefile index 769c4896f..2e3120f65 100644 --- a/examples/cmake_hello_c/Makefile +++ b/examples/cmake_hello_c/Makefile @@ -6,10 +6,11 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/cmake_hello_sc/CMakeLists.txt b/examples/cmake_hello_sc/CMakeLists.txt index 7ee97f3da..7d89c83bc 100644 --- a/examples/cmake_hello_sc/CMakeLists.txt +++ b/examples/cmake_hello_sc/CMakeLists.txt @@ -5,10 +5,11 @@ # This is an example cmake script to build a verilog to SystemC project # using CMake and Verilator. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/cmake_hello_sc/Makefile b/examples/cmake_hello_sc/Makefile index 5d652762a..b63fe2d4b 100644 --- a/examples/cmake_hello_sc/Makefile +++ b/examples/cmake_hello_sc/Makefile @@ -6,10 +6,11 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/cmake_protect_lib/CMakeLists.txt b/examples/cmake_protect_lib/CMakeLists.txt index d08888b93..0605b8089 100644 --- a/examples/cmake_protect_lib/CMakeLists.txt +++ b/examples/cmake_protect_lib/CMakeLists.txt @@ -5,10 +5,11 @@ # This is an example cmake script to build a verilog to systemc project # using cmake and verilator. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/cmake_protect_lib/Makefile b/examples/cmake_protect_lib/Makefile index 95132f76c..2e08b2a9a 100644 --- a/examples/cmake_protect_lib/Makefile +++ b/examples/cmake_protect_lib/Makefile @@ -6,10 +6,11 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/cmake_tracing_c/CMakeLists.txt b/examples/cmake_tracing_c/CMakeLists.txt index d26932609..ecfd8f4ed 100644 --- a/examples/cmake_tracing_c/CMakeLists.txt +++ b/examples/cmake_tracing_c/CMakeLists.txt @@ -5,10 +5,11 @@ # This is an example cmake script to build a verilog to systemc project # using cmake and verilator. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/cmake_tracing_c/Makefile b/examples/cmake_tracing_c/Makefile index ef7f45ddf..fe61cc730 100644 --- a/examples/cmake_tracing_c/Makefile +++ b/examples/cmake_tracing_c/Makefile @@ -6,10 +6,11 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/cmake_tracing_sc/CMakeLists.txt b/examples/cmake_tracing_sc/CMakeLists.txt index 20a55c06e..bb81dd3d0 100644 --- a/examples/cmake_tracing_sc/CMakeLists.txt +++ b/examples/cmake_tracing_sc/CMakeLists.txt @@ -5,10 +5,11 @@ # This is an example cmake script to build a verilog to SystemC project # using CMake and Verilator. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/cmake_tracing_sc/Makefile b/examples/cmake_tracing_sc/Makefile index 6f3aad9e6..6332ed2d5 100644 --- a/examples/cmake_tracing_sc/Makefile +++ b/examples/cmake_tracing_sc/Makefile @@ -6,10 +6,11 @@ # This makefile is here for testing the examples and should # generally not be added to a CMake project. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/make_hello_c/Makefile b/examples/make_hello_c/Makefile index 40939fb59..940c0bf25 100644 --- a/examples/make_hello_c/Makefile +++ b/examples/make_hello_c/Makefile @@ -5,10 +5,11 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### # Check for sanity to avoid later confusion diff --git a/examples/make_hello_c/sim_main.cpp b/examples/make_hello_c/sim_main.cpp index 08709e155..fd5003027 100644 --- a/examples/make_hello_c/sim_main.cpp +++ b/examples/make_hello_c/sim_main.cpp @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //====================================================================== // Include common routines diff --git a/examples/make_hello_c/top.v b/examples/make_hello_c/top.v index b1116025d..803566f1a 100644 --- a/examples/make_hello_c/top.v +++ b/examples/make_hello_c/top.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // See also the EXAMPLE section in the verilator manpage/document. module top; diff --git a/examples/make_hello_sc/Makefile b/examples/make_hello_sc/Makefile index 30506c69d..dc074b90e 100644 --- a/examples/make_hello_sc/Makefile +++ b/examples/make_hello_sc/Makefile @@ -5,10 +5,11 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### # Check for sanity to avoid later confusion diff --git a/examples/make_hello_sc/sc_main.cpp b/examples/make_hello_sc/sc_main.cpp index 30ec5fdb7..12848e35b 100644 --- a/examples/make_hello_sc/sc_main.cpp +++ b/examples/make_hello_sc/sc_main.cpp @@ -1,8 +1,9 @@ // -*- SystemC -*- // DESCRIPTION: Verilator Example: Top level main for invoking SystemC model // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //====================================================================== // SystemC global header diff --git a/examples/make_hello_sc/top.v b/examples/make_hello_sc/top.v index b1116025d..803566f1a 100644 --- a/examples/make_hello_sc/top.v +++ b/examples/make_hello_sc/top.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // See also the EXAMPLE section in the verilator manpage/document. module top; diff --git a/examples/make_protect_lib/Makefile b/examples/make_protect_lib/Makefile index b2e33a283..34f1a58dc 100644 --- a/examples/make_protect_lib/Makefile +++ b/examples/make_protect_lib/Makefile @@ -5,10 +5,11 @@ # This calls the object directory makefiles. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### # Check for sanity to avoid later confusion diff --git a/examples/make_protect_lib/secret_impl.v b/examples/make_protect_lib/secret_impl.v index a72344960..fd8557af1 100644 --- a/examples/make_protect_lib/secret_impl.v +++ b/examples/make_protect_lib/secret_impl.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: --protect-lib example secret module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 // This module will be used as libsecret.a or libsecret.so without // exposing the source. diff --git a/examples/make_protect_lib/sim_main.cpp b/examples/make_protect_lib/sim_main.cpp index b457fc1ae..3244f0a69 100644 --- a/examples/make_protect_lib/sim_main.cpp +++ b/examples/make_protect_lib/sim_main.cpp @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: --protect-lib example module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 //====================================================================== // See examples/tracing_c for notes on tracing diff --git a/examples/make_protect_lib/top.v b/examples/make_protect_lib/top.v index 76410e2c7..16a0e2740 100644 --- a/examples/make_protect_lib/top.v +++ b/examples/make_protect_lib/top.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: --protect-lib example module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Todd Strader. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 // See also the EXAMPLE section in the verilator manpage/document. module top (input clk); diff --git a/examples/make_tracing_c/Makefile b/examples/make_tracing_c/Makefile index a6acdc445..ba4b30bc3 100644 --- a/examples/make_tracing_c/Makefile +++ b/examples/make_tracing_c/Makefile @@ -5,10 +5,11 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### # Check for sanity to avoid later confusion diff --git a/examples/make_tracing_c/Makefile_obj b/examples/make_tracing_c/Makefile_obj index 6d07eb427..bbea9d940 100644 --- a/examples/make_tracing_c/Makefile_obj +++ b/examples/make_tracing_c/Makefile_obj @@ -5,10 +5,11 @@ # # This is executed in the object directory, and called by ../Makefile # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ####################################################################### diff --git a/examples/make_tracing_c/sim_main.cpp b/examples/make_tracing_c/sim_main.cpp index 527ff105b..6ff878731 100644 --- a/examples/make_tracing_c/sim_main.cpp +++ b/examples/make_tracing_c/sim_main.cpp @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //====================================================================== // Include common routines diff --git a/examples/make_tracing_c/sub.v b/examples/make_tracing_c/sub.v index 553d85921..47975db0c 100644 --- a/examples/make_tracing_c/sub.v +++ b/examples/make_tracing_c/sub.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // ====================================================================== module sub diff --git a/examples/make_tracing_c/top.v b/examples/make_tracing_c/top.v index ac537c68f..a11027546 100644 --- a/examples/make_tracing_c/top.v +++ b/examples/make_tracing_c/top.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // ====================================================================== // This is intended to be a complex example of several features, please also diff --git a/examples/make_tracing_sc/Makefile b/examples/make_tracing_sc/Makefile index ded101604..4b91f5ddc 100644 --- a/examples/make_tracing_sc/Makefile +++ b/examples/make_tracing_sc/Makefile @@ -5,10 +5,11 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### # Check for sanity to avoid later confusion diff --git a/examples/make_tracing_sc/Makefile_obj b/examples/make_tracing_sc/Makefile_obj index 03ffe389b..c997e2788 100644 --- a/examples/make_tracing_sc/Makefile_obj +++ b/examples/make_tracing_sc/Makefile_obj @@ -5,10 +5,11 @@ # # This is executed in the object directory, and called by ../Makefile # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ####################################################################### diff --git a/examples/make_tracing_sc/sc_main.cpp b/examples/make_tracing_sc/sc_main.cpp index 381d321bf..31145a17f 100644 --- a/examples/make_tracing_sc/sc_main.cpp +++ b/examples/make_tracing_sc/sc_main.cpp @@ -1,8 +1,9 @@ // -*- SystemC -*- // DESCRIPTION: Verilator Example: Top level main for invoking SystemC model // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //====================================================================== // SystemC global header diff --git a/examples/make_tracing_sc/sub.v b/examples/make_tracing_sc/sub.v index 6d0e64e8f..75529a924 100644 --- a/examples/make_tracing_sc/sub.v +++ b/examples/make_tracing_sc/sub.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // ====================================================================== module sub diff --git a/examples/make_tracing_sc/top.v b/examples/make_tracing_sc/top.v index beae05605..534acb8e1 100644 --- a/examples/make_tracing_sc/top.v +++ b/examples/make_tracing_sc/top.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // ====================================================================== // This is intended to be a complex example of several features, please also diff --git a/examples/xml_py/Makefile b/examples/xml_py/Makefile index e05a6f00d..c76871650 100644 --- a/examples/xml_py/Makefile +++ b/examples/xml_py/Makefile @@ -2,10 +2,11 @@ # # DESCRIPTION: Verilator Example: XML tests # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/examples/xml_py/sub.v b/examples/xml_py/sub.v index 5faf89f92..ba2eed35c 100644 --- a/examples/xml_py/sub.v +++ b/examples/xml_py/sub.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // ====================================================================== module sub diff --git a/examples/xml_py/top.v b/examples/xml_py/top.v index de7a98645..405bf46c5 100644 --- a/examples/xml_py/top.v +++ b/examples/xml_py/top.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog example module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // ====================================================================== module top diff --git a/examples/xml_py/vl_file_copy b/examples/xml_py/vl_file_copy index fa5d99308..0a5125c2a 100755 --- a/examples/xml_py/vl_file_copy +++ b/examples/xml_py/vl_file_copy @@ -84,8 +84,10 @@ Example usage: -v Verilog library -y Directory to search for modules -This file ONLY is placed into the Public Domain, for any use, without -warranty, 2019 by Wilson Snyder.""" +This file ONLY is placed under the Creative Commons Public Domain, for +any use, without warranty, 2019 by Wilson Snyder. +SPDX-License-Identifier: CC0-1.0 +""" ) parser.add_argument('-debug', '--debug', action='store_const', const=9, diff --git a/examples/xml_py/vl_hier_graph b/examples/xml_py/vl_hier_graph index 8273167fc..038518614 100755 --- a/examples/xml_py/vl_hier_graph +++ b/examples/xml_py/vl_hier_graph @@ -108,8 +108,10 @@ Example usage: -v Verilog library -y Directory to search for modules -This file ONLY is placed into the Public Domain, for any use, without -warranty, 2019 by Wilson Snyder.""" +This file ONLY is placed under the Creative Commons Public Domain, for +any use, without warranty, 2019 by Wilson Snyder. +SPDX-License-Identifier: CC0-1.0 +""" ) parser.add_argument('-debug', '--debug', action='store_const', const=9, diff --git a/include/gtkwave/fastlz.c b/include/gtkwave/fastlz.c index 50bf56a46..b52a799b9 100644 --- a/include/gtkwave/fastlz.c +++ b/include/gtkwave/fastlz.c @@ -22,6 +22,8 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + SPDX-License-Identifier: MIT */ #include "fastlz.h" diff --git a/include/gtkwave/fastlz.h b/include/gtkwave/fastlz.h index 8b4eac2e8..1ce44a32a 100644 --- a/include/gtkwave/fastlz.h +++ b/include/gtkwave/fastlz.h @@ -22,6 +22,8 @@ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + + SPDX-License-Identifier: MIT */ #ifndef FASTLZ_H diff --git a/include/gtkwave/fstapi.c b/include/gtkwave/fstapi.c index 720116ba8..8540587bb 100644 --- a/include/gtkwave/fstapi.c +++ b/include/gtkwave/fstapi.c @@ -18,6 +18,8 @@ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. + * + * SPDX-License-Identifier: MIT */ /* @@ -1024,7 +1026,9 @@ if(!xc->curval_mem) static void fstDestroyMmaps(struct fstWriterContext *xc, int is_closing) { +#if !defined __CYGWIN__ && !defined __MINGW32__ (void)is_closing; +#endif fstMunmap(xc->valpos_mem, xc->maxhandle * 4 * sizeof(uint32_t)); xc->valpos_mem = NULL; diff --git a/include/gtkwave/fstapi.h b/include/gtkwave/fstapi.h index bbc82c278..e347449ce 100644 --- a/include/gtkwave/fstapi.h +++ b/include/gtkwave/fstapi.h @@ -18,6 +18,8 @@ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. + * + * SPDX-License-Identifier: MIT */ #ifndef FST_API_H diff --git a/include/gtkwave/lz4.c b/include/gtkwave/lz4.c index 00fbcfca1..55dc1a835 100644 --- a/include/gtkwave/lz4.c +++ b/include/gtkwave/lz4.c @@ -27,6 +27,8 @@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + SPDX-License-Identifier: BSD-2-Clause + You can contact the author at : - LZ4 source repository : https://github.com/Cyan4973/lz4 - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c diff --git a/include/gtkwave/lz4.h b/include/gtkwave/lz4.h index 3e7400225..bd5245ea5 100644 --- a/include/gtkwave/lz4.h +++ b/include/gtkwave/lz4.h @@ -28,6 +28,8 @@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + SPDX-License-Identifier: BSD-2-Clause + You can contact the author at : - LZ4 source repository : https://github.com/Cyan4973/lz4 - LZ4 public forum : https://groups.google.com/forum/#!forum/lz4c diff --git a/include/gtkwave/wavealloca.h b/include/gtkwave/wavealloca.h index 8c064fe03..8fa7d8090 100644 --- a/include/gtkwave/wavealloca.h +++ b/include/gtkwave/wavealloca.h @@ -18,6 +18,8 @@ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. + * + * SPDX-License-Identifier: MIT */ #ifndef WAVE_ALLOCA_H diff --git a/include/verilated.cpp b/include/verilated.cpp index c242b5ab5..373082276 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -3,13 +3,9 @@ // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// @@ -888,7 +884,7 @@ static inline int _vl_vsss_peek(FILE* fp, int& floc, WDataInP fromp, } static inline void _vl_vsss_skipspace(FILE* fp, int& floc, WDataInP fromp, const std::string& fstr) VL_MT_SAFE { - while (1) { + while (true) { int c = _vl_vsss_peek(fp, floc, fromp, fstr); if (c==EOF || !isspace(c)) return; _vl_vsss_advance(fp, floc); @@ -898,7 +894,7 @@ static inline void _vl_vsss_read(FILE* fp, int& floc, WDataInP fromp, const std: char* tmpp, const char* acceptp) VL_MT_SAFE { // Read into tmp, consisting of characters from acceptp list char* cp = tmpp; - while (1) { + while (true) { int c = _vl_vsss_peek(fp, floc, fromp, fstr); if (c==EOF || isspace(c)) break; if (acceptp // String - allow anything @@ -1344,7 +1340,7 @@ IData VL_FREAD_I(int width, int array_lsb, int array_size, // Read the data // We process a character at a time, as then we don't need to deal // with changing buffer sizes dynamically, etc. - while (1) { + while (true) { int c = fgetc(fp); if (VL_UNLIKELY(c == EOF)) break; // Shift value in @@ -1672,7 +1668,7 @@ bool VlReadMem::get(QData& addrr, std::string& valuer) { // Read the data // We process a character at a time, as then we don't need to deal // with changing buffer sizes dynamically, etc. - while (1) { + while (true) { int c = fgetc(m_fp); if (VL_UNLIKELY(c == EOF)) break; // printf("%d: Got '%c' Addr%lx IN%d IgE%d IgC%d\n", @@ -1857,7 +1853,7 @@ void VL_READMEM_N(bool hex, // Hex format, else binary VlReadMem rmem(hex, bits, filename, start, end); if (VL_UNLIKELY(!rmem.isOpen())) return; - while (1) { + while (true) { QData addr; std::string value; if (rmem.get(addr /*ref*/, value/*ref*/)) { @@ -2187,9 +2183,7 @@ void VerilatedImp::commandArgsAddGuts(int argc, const char** argv) VL_REQUIRES(s void VerilatedImp::commandArgVl(const std::string& arg) { if (0 == strncmp(arg.c_str(), "+verilator+", strlen("+verilator+"))) { std::string value; - if (0) { - } - else if (arg == "+verilator+debug") { + if (arg == "+verilator+debug") { Verilated::debug(4); } else if (commandArgVlValue(arg, "+verilator+debugi+", value/*ref*/)) { diff --git a/include/verilated.h b/include/verilated.h index 90aa9ff53..2aed894a1 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -3,13 +3,9 @@ // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// @@ -320,7 +316,7 @@ private: public: // But internals only - called from VerilatedModule's VerilatedScope(); ~VerilatedScope(); - void configure(VerilatedSyms* symsp, const char* prefixp, const char* suffix, + void configure(VerilatedSyms* symsp, const char* prefixp, const char* suffixp, const char* identifier, const Type type) VL_MT_UNSAFE; void exportInsert(int finalize, const char* namep, void* cb) VL_MT_UNSAFE; void varInsert(int finalize, const char* namep, void* datap, @@ -699,13 +695,12 @@ static inline QData VL_CVT_Q_D(double lhs) VL_PURE { union { double d; QData q; } u; u.d=lhs; return u.q; } /// Return double from QData (numeric) static inline double VL_ITOR_D_I(IData lhs) VL_PURE { - return static_cast(static_cast(lhs)); } + return static_cast(static_cast(lhs)); +} /// Return QData from double (numeric) -static inline IData VL_RTOI_I_D(double lhs) VL_PURE { - return static_cast(VL_TRUNC(lhs)); } -/// Return QData from double (numeric) -static inline IData VL_RTOIROUND_I_D(double lhs) VL_PURE { - return static_cast(VL_ROUND(lhs)); } +static inline IData VL_RTOI_I_D(double lhs) VL_PURE { + return static_cast(VL_TRUNC(lhs)); +} // Sign extend such that if MSB set, we get ffff_ffff, else 0s // (Requires clean input) @@ -1324,6 +1319,14 @@ static inline WDataOutP VL_NEGATE_W(int words, WDataOutP owp, WDataInP lwp) VL_M } return owp; } +static void VL_NEGATE_INPLACE_W(int words, WDataOutP owp_lwp) VL_MT_SAFE { + EData carry = 1; + for (int i = 0; i < words; ++i) { + EData word = ~owp_lwp[i] + carry; + carry = (word < ~owp_lwp[i]); + owp_lwp[i] = word; + } +} // EMIT_RULE: VL_MUL: oclean=dirty; lclean==clean; rclean==clean; // EMIT_RULE: VL_DIV: oclean=dirty; lclean==clean; rclean==clean; @@ -1650,18 +1653,22 @@ static inline void _VL_INSERT_WW(int, WDataOutP owp, WDataInP lwp, int hbit, int int oword = lword+i; EData d = lwp[i] << loffset; EData od = (owp[oword] & ~linsmask) | (d & linsmask); - if (oword == hword) + if (oword == hword) { owp[oword] = (owp[oword] & ~hinsmask) | (od & hinsmask); - else owp[oword] = od; + } else { + owp[oword] = od; + } } { // Upper word int oword = lword+i+1; if (oword <= hword) { EData d = lwp[i] >> nbitsonright; EData od = (d & ~linsmask) | (owp[oword] & linsmask); - if (oword == hword) + if (oword == hword) { owp[oword] = (owp[oword] & ~hinsmask) | (od & hinsmask); - else owp[oword] = od; + } else { + owp[oword] = od; + } } } } @@ -2240,6 +2247,49 @@ static inline WDataOutP VL_SEL_WWII(int obits, int lbits, int, int, return owp; } +//====================================================================== +// Math needing insert/select + +/// Return QData from double (numeric) +// EMIT_RULE: VL_RTOIROUND_Q_D: oclean=dirty; lclean==clean/real +static inline QData VL_RTOIROUND_Q_D(int bits, double lhs) VL_PURE { + // IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa + // This does not need to support subnormals as they are sub-integral + lhs = VL_ROUND(lhs); + if (lhs == 0.0) return 0; + QData q = VL_CVT_Q_D(lhs); + int lsb = static_cast((q >> VL_ULL(52)) & VL_MASK_Q(11)) - 1023 - 52; + vluint64_t mantissa = (q & VL_MASK_Q(52)) | (VL_ULL(1) << 52); + vluint64_t out = 0; + if (lsb < 0) { + out = mantissa >> -lsb; + } else if (lsb < 64) { + out = mantissa << lsb; + } + if (lhs < 0) out = -out; + return out; +} +static inline IData VL_RTOIROUND_I_D(int bits, double lhs) VL_PURE { + return static_cast(VL_RTOIROUND_Q_D(bits, lhs)); +} +static inline WDataOutP VL_RTOIROUND_W_D(int obits, WDataOutP owp, double lhs) VL_PURE { + // IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa + // This does not need to support subnormals as they are sub-integral + lhs = VL_ROUND(lhs); + VL_ZERO_W(obits, owp); + if (lhs == 0.0) return owp; + QData q = VL_CVT_Q_D(lhs); + int lsb = static_cast((q >> VL_ULL(52)) & VL_MASK_Q(11)) - 1023 - 52; + vluint64_t mantissa = (q & VL_MASK_Q(52)) | (VL_ULL(1) << 52); + if (lsb < 0) { + VL_SET_WQ(owp, mantissa >> -lsb); + } else if (lsb < obits) { + _VL_INSERT_WQ(obits, owp, mantissa, lsb + 52, lsb); + } + if (lhs < 0) VL_NEGATE_INPLACE_W(VL_WORDS_I(obits), owp); + return owp; +} + //====================================================================== // Range assignments diff --git a/include/verilated.mk.in b/include/verilated.mk.in index b00b58272..0a5254610 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -2,9 +2,11 @@ ###################################################################### # DESCRIPTION: Makefile commands for all verilated target files # -# Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### PERL = @PERL@ diff --git a/include/verilated.v b/include/verilated.v index ad51dcd99..4353c02cf 100644 --- a/include/verilated.v +++ b/include/verilated.v @@ -6,13 +6,9 @@ // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// This is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= // diff --git a/include/verilated_config.h.in b/include/verilated_config.h.in index afc8d191c..cb5175559 100644 --- a/include/verilated_config.h.in +++ b/include/verilated_config.h.in @@ -3,13 +3,9 @@ // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index cfa129a0c..24f83dd8f 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// @@ -77,7 +74,7 @@ public: virtual void zero() const VL_OVERRIDE { *m_countp = 0; } // CONSTRUCTORS // cppcheck-suppress noExplicitConstructor - VerilatedCoverItemSpec(T* countp) : m_countp(countp) { *m_countp = 0; } + explicit VerilatedCoverItemSpec(T* countp) : m_countp(countp) { *m_countp = 0; } virtual ~VerilatedCoverItemSpec() VL_OVERRIDE {} }; diff --git a/include/verilated_cov.h b/include/verilated_cov.h index aff3e8c33..5aa11a2d7 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// @@ -32,9 +29,15 @@ /// Conditionally compile coverage code #ifdef VM_COVERAGE -# define VL_IF_COVER(stmts) do { stmts ; } while(0) +# define VL_IF_COVER(stmts) \ + do { \ + stmts; \ + } while (false) #else -# define VL_IF_COVER(stmts) do { if(0) { stmts ; } } while(0) +# define VL_IF_COVER(stmts) \ + do { \ + if (false) { stmts; } \ + } while (false) #endif //============================================================================= @@ -65,10 +68,10 @@ /// VL_COVER_INSERT(&m_cases[i], "comment", "Coverage Case", "i", cvtToNumStr(i)); /// } -#define VL_COVER_INSERT(countp,args...) \ +#define VL_COVER_INSERT(countp,...) \ VL_IF_COVER(VerilatedCov::_inserti(countp); \ VerilatedCov::_insertf(__FILE__, __LINE__); \ - VerilatedCov::_insertp("hier", name(), args)) + VerilatedCov::_insertp("hier", name(), __VA_ARGS__)) //============================================================================= /// Convert VL_COVER_INSERT value arguments to strings diff --git a/include/verilated_cov_key.h b/include/verilated_cov_key.h index 4fda5dda9..fdb0600e2 100644 --- a/include/verilated_cov_key.h +++ b/include/verilated_cov_key.h @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp index a9da6866c..7b4678ea1 100644 --- a/include/verilated_dpi.cpp +++ b/include/verilated_dpi.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// @@ -46,8 +42,8 @@ VL_FATAL_MT(__FILE__, __LINE__, "", \ (std::string("%%Error: Unsupported DPI function: ")+VL_FUNC).c_str()) -#define _VL_SVDPI_WARN(message...) \ - VL_PRINTF_MT(message) +#define _VL_SVDPI_WARN(...) \ + VL_PRINTF_MT(__VA_ARGS__) // Function requires a "context" in the import declaration #define _VL_SVDPI_CONTEXT_WARN() \ diff --git a/include/verilated_dpi.h b/include/verilated_dpi.h index 4edffc32b..26ff6f02b 100644 --- a/include/verilated_dpi.h +++ b/include/verilated_dpi.h @@ -3,13 +3,9 @@ // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index 926a19384..7b816fd75 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 9f2f6c9d6..1ce99df69 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index 432c847d4..774450707 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -3,13 +3,9 @@ // // Copyright 2010-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// @@ -37,10 +33,10 @@ //=================================================================== // String formatters (required by below containers) -extern std::string VL_TO_STRING(CData obj); -extern std::string VL_TO_STRING(SData obj); -extern std::string VL_TO_STRING(IData obj); -extern std::string VL_TO_STRING(QData obj); +extern std::string VL_TO_STRING(CData lhs); +extern std::string VL_TO_STRING(SData lhs); +extern std::string VL_TO_STRING(IData lhs); +extern std::string VL_TO_STRING(QData lhs); inline std::string VL_TO_STRING(const std::string& obj) { return "\"" + obj + "\""; } extern std::string VL_TO_STRING_W(int words, WDataInP obj); @@ -162,7 +158,7 @@ public: int next(T_Key& indexr) const { typename Map::const_iterator it = m_map.find(indexr); if (VL_UNLIKELY(it == m_map.end())) return 0; - it++; + ++it; if (VL_UNLIKELY(it == m_map.end())) return 0; indexr = it->first; return 1; @@ -221,7 +217,7 @@ void VL_READMEM_N(bool hex, int bits, const std::string& filename, VlAssocArray& obj, QData start, QData end) VL_MT_SAFE { VlReadMem rmem(hex, bits, filename, start, end); if (VL_UNLIKELY(!rmem.isOpen())) return; - while (1) { + while (true) { QData addr; std::string data; if (rmem.get(addr /*ref*/, data /*ref*/)) { diff --git a/include/verilated_imp.h b/include/verilated_imp.h index 0d55c4c36..ac580ec1a 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -3,13 +3,9 @@ // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp index 965ab24e8..18b668e98 100644 --- a/include/verilated_save.cpp +++ b/include/verilated_save.cpp @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// @@ -187,7 +184,7 @@ void VerilatedSave::flush() VL_MT_UNSAFE_ONE { m_assertOne.check(); if (VL_UNLIKELY(!isOpen())) return; vluint8_t* wp = m_bufp; - while (1) { + while (true) { ssize_t remaining = (m_cp - wp); if (remaining==0) break; errno = 0; @@ -216,7 +213,7 @@ void VerilatedRestore::fill() VL_MT_UNSAFE_ONE { m_endp = m_bufp + (m_endp - m_cp); m_cp = m_bufp; // Reset buffer // Read into buffer starting at m_endp - while (1) { + while (true) { ssize_t remaining = (m_bufp+bufferSize() - m_endp); if (remaining==0) break; errno = 0; diff --git a/include/verilated_save.h b/include/verilated_save.h index e755b77b0..94497fbde 100644 --- a/include/verilated_save.h +++ b/include/verilated_save.h @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2012-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2000-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// diff --git a/include/verilated_sc.h b/include/verilated_sc.h index a9e8dc42d..b250d224b 100644 --- a/include/verilated_sc.h +++ b/include/verilated_sc.h @@ -3,13 +3,9 @@ // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// diff --git a/include/verilated_sym_props.h b/include/verilated_sym_props.h index 373002660..845e40f1b 100644 --- a/include/verilated_sym_props.h +++ b/include/verilated_sym_props.h @@ -3,13 +3,9 @@ // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// diff --git a/include/verilated_syms.h b/include/verilated_syms.h index 4b3ffe028..e364a18cf 100644 --- a/include/verilated_syms.h +++ b/include/verilated_syms.h @@ -3,13 +3,9 @@ // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// diff --git a/include/verilated_threads.cpp b/include/verilated_threads.cpp index 1c5fda43b..7568e1585 100644 --- a/include/verilated_threads.cpp +++ b/include/verilated_threads.cpp @@ -1,16 +1,11 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED -// -// Copyright 2012-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2012-2020 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// @@ -41,7 +36,8 @@ VlMTaskVertex::VlMTaskVertex(vluint32_t upstreamDepCount) // VlWorkerThread VlWorkerThread::VlWorkerThread(VlThreadPool* poolp, bool profiling) - : m_ready_size(0) + : m_waiting(false) + , m_ready_size(0) , m_poolp(poolp) , m_profiling(profiling) , m_exiting(false) @@ -63,7 +59,7 @@ void VlWorkerThread::workerLoop() { ExecRec work; work.m_fnp = NULL; - while (1) { + while (true) { if (VL_LIKELY(!work.m_fnp)) { dequeWork(&work); } @@ -173,12 +169,12 @@ void VlThreadPool::profileDump(const char* filenamep, vluint64_t ticksElapsed) { VlMTaskVertex::yields()); vluint32_t thread_id = 0; - for (ProfileSet::iterator pit = m_allProfiles.begin(); + for (ProfileSet::const_iterator pit = m_allProfiles.begin(); pit != m_allProfiles.end(); ++pit) { ++thread_id; bool printing = false; // False while in warmup phase - for (ProfileTrace::iterator eit = (*pit)->begin(); + for (ProfileTrace::const_iterator eit = (*pit)->begin(); eit != (*pit)->end(); ++eit) { switch (eit->m_type) { case VlProfileRec::TYPE_BARRIER: diff --git a/include/verilated_threads.h b/include/verilated_threads.h index ae02e5df6..39cab0a11 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2012-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2012-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// diff --git a/include/verilated_unordered_set_map.h b/include/verilated_unordered_set_map.h index 6c185462d..9800b39a1 100644 --- a/include/verilated_unordered_set_map.h +++ b/include/verilated_unordered_set_map.h @@ -7,15 +7,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -151,7 +147,7 @@ public: return (!this->operator==(other)); } void advanceUntilValid() { - while (1) { + while (true) { if (m_bit != m_setp->m_bucketsp[m_bucketIdx].end()) { // Valid iterator in this bucket; we're done. return; diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index 49f4d69f9..bf344ecc9 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// @@ -159,10 +156,10 @@ VerilatedVcd::VerilatedVcd(VerilatedVcdFile* filep) void VerilatedVcd::open(const char* filename) { m_assertOne.check(); - if (isOpen() || !filename || !*filename) return; + if (isOpen()) return; // Set member variables - m_filename = filename; + m_filename = filename; // "" is ok, as someone may overload open VerilatedVcdSingleton::pushVcd(this); // SPDIFF_OFF @@ -367,7 +364,7 @@ void VerilatedVcd::bufferFlush() VL_MT_UNSAFE_ONE { m_assertOne.check(); if (VL_UNLIKELY(!isOpen())) return; char* wp = m_wrBufp; - while (1) { + while (true) { ssize_t remaining = (m_writep - wp); if (remaining==0) break; errno = 0; diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index f0a5bcb9f..7051b07d1 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// diff --git a/include/verilated_vcd_sc.cpp b/include/verilated_vcd_sc.cpp index 7fc772648..ef3013d29 100644 --- a/include/verilated_vcd_sc.cpp +++ b/include/verilated_vcd_sc.cpp @@ -3,14 +3,11 @@ // // THIS MODULE IS PUBLICLY LICENSED // -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// diff --git a/include/verilated_vcd_sc.h b/include/verilated_vcd_sc.h index 48c961c8d..030f8820a 100644 --- a/include/verilated_vcd_sc.h +++ b/include/verilated_vcd_sc.h @@ -1,16 +1,11 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED -// -// Copyright 2001-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -// -// This is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. +// Copyright 2001-2020 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //============================================================================= /// diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index d22c1c807..2a6f727df 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// @@ -80,21 +76,22 @@ public: if (VL_UNCOVERABLE(size>chunk)) VL_FATAL_MT(__FILE__, __LINE__, "", "increase chunk"); if (VL_LIKELY(t_freeHead)) { vluint8_t* newp = t_freeHead; - t_freeHead = *((vluint8_t**)newp); + t_freeHead = *(reinterpret_cast(newp)); return newp+8; } // +8: 8 bytes for next vluint8_t* newp = reinterpret_cast(::operator new(chunk+8)); return newp+8; } - inline static void operator delete(void* obj, size_t size) VL_MT_SAFE { - vluint8_t* oldp = ((vluint8_t*)obj)-8; - *((void**)oldp) = t_freeHead; + inline static void operator delete(void* obj, size_t /*size*/)VL_MT_SAFE { + vluint8_t* oldp = (static_cast(obj)) - 8; + *(reinterpret_cast(oldp)) = t_freeHead; t_freeHead = oldp; } // MEMBERS static inline VerilatedVpio* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } inline vpiHandle castVpiHandle() { return reinterpret_cast(this); } // ACCESSORS virtual const char* name() const { return ""; } @@ -121,7 +118,8 @@ public: } virtual ~VerilatedVpioCb() {} static inline VerilatedVpioCb* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } virtual vluint32_t type() const { return vpiCallback; } vluint32_t reason() const { return m_cbData.reason; } VerilatedPliCb cb_rtnp() const { return m_cbData.cb_rtn; } @@ -135,7 +133,8 @@ public: explicit VerilatedVpioConst(vlsint32_t num) : m_num(num) {} virtual ~VerilatedVpioConst() {} static inline VerilatedVpioConst* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } virtual vluint32_t type() const { return vpiUndefined; } vlsint32_t num() const { return m_num; } }; @@ -147,7 +146,8 @@ public: explicit VerilatedVpioRange(const VerilatedRange* range) : m_range(range), m_iteration(0) {} virtual ~VerilatedVpioRange() {} static inline VerilatedVpioRange* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } virtual vluint32_t type() const { return vpiRange; } virtual vluint32_t size() const { return m_range->elements(); } virtual const VerilatedRange* rangep() const { return m_range; } @@ -171,7 +171,8 @@ public: : m_scopep(scopep) {} virtual ~VerilatedVpioScope() {} static inline VerilatedVpioScope* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } virtual vluint32_t type() const { return vpiScope; } const VerilatedScope* scopep() const { return m_scopep; } virtual const char* name() const { return m_scopep->name(); } @@ -206,7 +207,8 @@ public: if (m_prevDatap) { delete [] m_prevDatap; m_prevDatap = NULL; } } static inline VerilatedVpioVar* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } const VerilatedVar* varp() const { return m_varp; } const VerilatedScope* scopep() const { return m_scopep; } vluint32_t mask() const { return m_mask.u32; } @@ -240,11 +242,12 @@ public: vlsint32_t index, int offset) : VerilatedVpioVar(varp, scopep) { m_index = index; - m_varDatap = ((vluint8_t*)varp->datap()) + entSize()*offset; + m_varDatap = (static_cast(varp->datap())) + entSize() * offset; } virtual ~VerilatedVpioMemoryWord() {} static inline VerilatedVpioMemoryWord* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } virtual vluint32_t type() const { return vpiMemoryWord; } virtual vluint32_t size() const { return varp()->packed().elements(); } virtual const VerilatedRange* rangep() const { return &(varp()->packed()); } @@ -265,7 +268,8 @@ public: : m_scopep(scopep), m_started(false) { } virtual ~VerilatedVpioVarIter() {} static inline VerilatedVpioVarIter* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } virtual vluint32_t type() const { return vpiIterator; } virtual vpiHandle dovpi_scan() { if (VL_LIKELY(m_scopep->varsp())) { @@ -295,7 +299,8 @@ public: m_done(false) { } virtual ~VerilatedVpioMemoryWordIter() {} static inline VerilatedVpioMemoryWordIter* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } virtual vluint32_t type() const { return vpiIterator; } void iterationInc() { if (!(m_done = (m_iteration == m_varp->unpacked().left()))) { @@ -322,7 +327,8 @@ public: m_name = m_scopep->identifier(); } static inline VerilatedVpioModule* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*)h); } + return dynamic_cast(reinterpret_cast(h)); + } virtual vluint32_t type() const { return vpiModule; } virtual const char* name() const { return m_name; } virtual const char* fullname() const { return m_fullname; } @@ -337,7 +343,8 @@ public: } virtual ~VerilatedVpioModuleIter() {} static inline VerilatedVpioModuleIter* castp(vpiHandle h) { - return dynamic_cast((VerilatedVpio*) h); } + return dynamic_cast(reinterpret_cast(h)); + } virtual vluint32_t type() const { return vpiIterator; } virtual vpiHandle dovpi_scan() { if (m_it == m_vec->end()) { @@ -465,7 +472,7 @@ public: varop->fullname(), *((CData*)newDatap), *((CData*)prevDatap), newDatap, prevDatap);); - if (memcmp(prevDatap, newDatap, varop->entSize())) { + if (memcmp(prevDatap, newDatap, varop->entSize()) != 0) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_callback %p %s v[0]=%d\n", vop, varop->fullname(), *((CData*)newDatap));); update.insert(varop); @@ -509,7 +516,7 @@ public: VerilatedVpiError() : m_flag(false) { m_buff[0] = '\0'; - m_errorInfo.product = (PLI_BYTE8*)Verilated::productName(); + m_errorInfo.product = const_cast(Verilated::productName()); } ~VerilatedVpiError() {} static void selfTest() VL_MT_UNSAFE_ONE; @@ -518,7 +525,7 @@ public: m_errorInfo.level = level; return this; } - void setMessage(std::string file, PLI_INT32 line, const char* message, ...) { + void setMessage(const std::string& file, PLI_INT32 line, const char* message, ...) { // message cannot be a const string& as va_start cannot use a reference static VL_THREAD_LOCAL std::string filehold; va_list args; @@ -527,7 +534,7 @@ public: va_end(args); m_errorInfo.state = vpiPLI; filehold = file; - setError((PLI_BYTE8*)m_buff, NULL, (PLI_BYTE8*)filehold.c_str(), line); + setError((PLI_BYTE8*)m_buff, NULL, const_cast(filehold.c_str()), line); } p_vpi_error_info getError() { if (m_flag) return &m_errorInfo; @@ -570,6 +577,10 @@ bool VerilatedVpi::callCbs(vluint32_t reason) VL_MT_UNSAFE_ONE { return VerilatedVpiImp::callCbs(reason); } +QData VerilatedVpi::cbNextDeadline() VL_MT_UNSAFE_ONE { + return VerilatedVpiImp::cbNextDeadline(); +} + //====================================================================== // VerilatedVpiImp implementation @@ -1024,14 +1035,13 @@ PLI_INT32 vpi_remove_cb(vpiHandle object) { return 1; } -void vpi_get_cb_info(vpiHandle object, p_cb_data cb_data_p) { - _VL_VPI_UNIMP(); return; +void vpi_get_cb_info(vpiHandle /*object*/, p_cb_data /*cb_data_p*/) { _VL_VPI_UNIMP(); } +vpiHandle vpi_register_systf(p_vpi_systf_data /*systf_data_p*/) { + _VL_VPI_UNIMP(); + return 0; } -vpiHandle vpi_register_systf(p_vpi_systf_data systf_data_p) { - _VL_VPI_UNIMP(); return 0; -} -void vpi_get_systf_info(vpiHandle object, p_vpi_systf_data systf_data_p) { - _VL_VPI_UNIMP(); return; +void vpi_get_systf_info(vpiHandle /*object*/, p_vpi_systf_data /*systf_data_p*/) { + _VL_VPI_UNIMP(); } // for obtaining handles @@ -1047,7 +1057,7 @@ vpiHandle vpi_handle_by_name(PLI_BYTE8* namep, vpiHandle scope) { std::string scopeAndName = namep; if (voScopep) { scopeAndName = std::string(voScopep->fullname()) + "." + namep; - namep = (PLI_BYTE8*)scopeAndName.c_str(); + namep = const_cast(scopeAndName.c_str()); } { // This doesn't yet follow the hierarchy in the proper way @@ -1067,7 +1077,7 @@ vpiHandle vpi_handle_by_name(PLI_BYTE8* namep, vpiHandle scope) { scopename = std::string(namep, dotp-namep); } - if (scopename.find(".") == std::string::npos) { + if (scopename.find('.') == std::string::npos) { // This is a toplevel, hence search in our TOP ports first. scopep = Verilated::scopeFind("TOP"); if (scopep) { @@ -1150,8 +1160,10 @@ vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { } } -vpiHandle vpi_handle_multi(PLI_INT32 type, vpiHandle refHandle1, vpiHandle refHandle2, ... ) { - _VL_VPI_UNIMP(); return 0; +vpiHandle vpi_handle_multi(PLI_INT32 /*type*/, vpiHandle /*refHandle1*/, vpiHandle /*refHandle2*/, + ...) { + _VL_VPI_UNIMP(); + return 0; } vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) { @@ -1194,7 +1206,7 @@ vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) { VerilatedVpioModule* vop = VerilatedVpioModule::castp(object); const VerilatedHierarchyMap* map = VerilatedImp::hierarchyMap(); const VerilatedScope *mod = vop ? vop->scopep() : NULL; - VerilatedHierarchyMap::const_iterator it = map->find((VerilatedScope*) mod); + VerilatedHierarchyMap::const_iterator it = map->find(const_cast(mod)); if (it == map->end()) return 0; return ((new VerilatedVpioModuleIter(it->second))->castVpiHandle()); } @@ -1256,7 +1268,7 @@ PLI_INT32 vpi_get(PLI_INT32 property, vpiHandle object) { } } -PLI_INT64 vpi_get64(PLI_INT32 property, vpiHandle object) { +PLI_INT64 vpi_get64(PLI_INT32 /*property*/, vpiHandle /*object*/) { _VL_VPI_UNIMP(); return 0; } @@ -1269,16 +1281,16 @@ PLI_BYTE8 *vpi_get_str(PLI_INT32 property, vpiHandle object) { if (VL_UNLIKELY(!vop)) return NULL; switch (property) { case vpiName: { - return (PLI_BYTE8*)vop->name(); + return const_cast(vop->name()); } case vpiFullName: { - return (PLI_BYTE8*)vop->fullname(); + return const_cast(vop->fullname()); } case vpiDefName: { - return (PLI_BYTE8*)vop->defname(); + return const_cast(vop->defname()); } case vpiType: { - return (PLI_BYTE8*) VerilatedVpiError::strFromVpiObjType(vop->type()); + return const_cast(VerilatedVpiError::strFromVpiObjType(vop->type())); } default: _VL_VPI_WARNING(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", @@ -1289,14 +1301,8 @@ PLI_BYTE8 *vpi_get_str(PLI_INT32 property, vpiHandle object) { // delay processing -void vpi_get_delays(vpiHandle object, p_vpi_delay delay_p) { - _VL_VPI_UNIMP(); - return; -} -void vpi_put_delays(vpiHandle object, p_vpi_delay delay_p) { - _VL_VPI_UNIMP(); - return; -} +void vpi_get_delays(vpiHandle /*object*/, p_vpi_delay /*delay_p*/) { _VL_VPI_UNIMP(); } +void vpi_put_delays(vpiHandle /*object*/, p_vpi_delay /*delay_p*/) { _VL_VPI_UNIMP(); } // value processing @@ -1582,8 +1588,8 @@ void vpi_get_value(vpiHandle object, p_vpi_value value_p) { VL_FUNC, VerilatedVpiError::strFromVpiVal(value_p->format)); } -vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p, - p_vpi_time time_p, PLI_INT32 flags) { +vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p, p_vpi_time /*time_p*/, + PLI_INT32 /*flags*/) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: vpi_put_value %p %p\n", object, value_p);); VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); @@ -1876,19 +1882,18 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value value_p, return NULL; } -void vpi_get_value_array(vpiHandle object, p_vpi_arrayvalue arrayvalue_p, - PLI_INT32 *index_p, PLI_UINT32 num) { - _VL_VPI_UNIMP(); return; +void vpi_get_value_array(vpiHandle /*object*/, p_vpi_arrayvalue /*arrayvalue_p*/, + PLI_INT32* /*index_p*/, PLI_UINT32 /*num*/) { + _VL_VPI_UNIMP(); } -void vpi_put_value_array(vpiHandle object, p_vpi_arrayvalue arrayvalue_p, - PLI_INT32 *index_p, PLI_UINT32 num) { - _VL_VPI_UNIMP(); return; +void vpi_put_value_array(vpiHandle /*object*/, p_vpi_arrayvalue /*arrayvalue_p*/, + PLI_INT32* /*index_p*/, PLI_UINT32 /*num*/) { + _VL_VPI_UNIMP(); } - // time processing -void vpi_get_time(vpiHandle object, p_vpi_time time_p) { +void vpi_get_time(vpiHandle /*object*/, p_vpi_time time_p) { VerilatedVpiImp::assertOneCheck(); // cppcheck-suppress nullPointer if (VL_UNLIKELY(!time_p)) { @@ -1905,7 +1910,6 @@ void vpi_get_time(vpiHandle object, p_vpi_time time_p) { } _VL_VPI_ERROR(__FILE__, __LINE__, "%s: Unsupported type (%d)", VL_FUNC, time_p->type); - return; } // I/O routines @@ -1919,11 +1923,13 @@ PLI_UINT32 vpi_mcd_open(PLI_BYTE8 *filenamep) { PLI_UINT32 vpi_mcd_close(PLI_UINT32 mcd) { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); - VL_FCLOSE_I(mcd); return 0; + VL_FCLOSE_I(mcd); + return 0; } -PLI_BYTE8 *vpi_mcd_name(PLI_UINT32 mcd) { - _VL_VPI_UNIMP(); return 0; +PLI_BYTE8* vpi_mcd_name(PLI_UINT32 /*mcd*/) { + _VL_VPI_UNIMP(); + return 0; } PLI_INT32 vpi_mcd_printf(PLI_UINT32 mcd, PLI_BYTE8 *formatp, ...) { @@ -1980,8 +1986,9 @@ PLI_INT32 vpi_mcd_flush(PLI_UINT32 mcd) { // utility routines -PLI_INT32 vpi_compare_objects(vpiHandle object1, vpiHandle object2) { - _VL_VPI_UNIMP(); return 0; +PLI_INT32 vpi_compare_objects(vpiHandle /*object1*/, vpiHandle /*object2*/) { + _VL_VPI_UNIMP(); + return 0; } PLI_INT32 vpi_chk_error(p_vpi_error_info error_info_p) { // executing vpi_chk_error does not reset error @@ -2016,25 +2023,29 @@ PLI_INT32 vpi_get_vlog_info(p_vpi_vlog_info vlog_info_p) VL_MT_SAFE { VerilatedVpiImp::assertOneCheck(); _VL_VPI_ERROR_RESET(); vlog_info_p->argc = Verilated::getCommandArgs()->argc; - vlog_info_p->argv = (PLI_BYTE8**)Verilated::getCommandArgs()->argv; - vlog_info_p->product = (PLI_BYTE8*)Verilated::productName(); - vlog_info_p->version = (PLI_BYTE8*)Verilated::productVersion(); + vlog_info_p->argv = const_cast(Verilated::getCommandArgs()->argv); + vlog_info_p->product = const_cast(Verilated::productName()); + vlog_info_p->version = const_cast(Verilated::productVersion()); return 1; } // routines added with 1364-2001 -PLI_INT32 vpi_get_data(PLI_INT32 id, PLI_BYTE8 *dataLoc, PLI_INT32 numOfBytes) { - _VL_VPI_UNIMP(); return 0; +PLI_INT32 vpi_get_data(PLI_INT32 /*id*/, PLI_BYTE8* /*dataLoc*/, PLI_INT32 /*numOfBytes*/) { + _VL_VPI_UNIMP(); + return 0; } -PLI_INT32 vpi_put_data(PLI_INT32 id, PLI_BYTE8 *dataLoc, PLI_INT32 numOfBytes) { - _VL_VPI_UNIMP(); return 0; +PLI_INT32 vpi_put_data(PLI_INT32 /*id*/, PLI_BYTE8* /*dataLoc*/, PLI_INT32 /*numOfBytes*/) { + _VL_VPI_UNIMP(); + return 0; } -void *vpi_get_userdata(vpiHandle obj) { - _VL_VPI_UNIMP(); return 0; +void* vpi_get_userdata(vpiHandle /*obj*/) { + _VL_VPI_UNIMP(); + return 0; } -PLI_INT32 vpi_put_userdata(vpiHandle obj, void *userdata) { - _VL_VPI_UNIMP(); return 0; +PLI_INT32 vpi_put_userdata(vpiHandle /*obj*/, void* /*userdata*/) { + _VL_VPI_UNIMP(); + return 0; } PLI_INT32 vpi_control(PLI_INT32 operation, ...) { @@ -2056,6 +2067,8 @@ PLI_INT32 vpi_control(PLI_INT32 operation, ...) { return 0; } -vpiHandle vpi_handle_by_multi_index(vpiHandle obj, PLI_INT32 num_index, PLI_INT32 *index_array) { - _VL_VPI_UNIMP(); return 0; +vpiHandle vpi_handle_by_multi_index(vpiHandle /*obj*/, PLI_INT32 /*num_index*/, + PLI_INT32* /*index_array*/) { + _VL_VPI_UNIMP(); + return 0; } diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h index 0715cd18f..dea1bb9e0 100644 --- a/include/verilated_vpi.h +++ b/include/verilated_vpi.h @@ -3,13 +3,9 @@ // // Copyright 2009-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //========================================================================= /// @@ -48,6 +44,9 @@ public: /// Call callbacks of arbitrary types /// Users can call this from their application code static bool callCbs(vluint32_t reason) VL_MT_UNSAFE_ONE; + /// Returns time of the next registered VPI callback, or + /// ~(0) if none are registered + static QData cbNextDeadline() VL_MT_UNSAFE_ONE; /// Self test, for internal use only static void selfTest() VL_MT_UNSAFE_ONE; }; diff --git a/include/verilatedos.h b/include/verilatedos.h index cc3bdd3b3..4bbfa0fe3 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -3,13 +3,9 @@ // // Copyright 2003-2020 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* /// @@ -157,15 +153,32 @@ # define VL_DANGLING(var) #else ///< After e.g. delete, set variable to NULL to indicate must not use later -# define VL_DANGLING(var) do { (var) = NULL; } while(0) +# define VL_DANGLING(var) \ + do { \ + (var) = NULL; \ + } while (false) #endif ///< Perform an e.g. delete, then set variable to NULL to indicate must not use later. ///< Unlike VL_DO_CLEAR the setting of the variable is only for debug reasons. -#define VL_DO_DANGLING(stmt, var) do { do { stmt; } while(0); VL_DANGLING(var); } while(0) +#define VL_DO_DANGLING(stmt, var) \ + do { \ + do { \ + stmt; \ + } while (false); \ + VL_DANGLING(var); \ + } while (false) ///< Perform an e.g. delete, then set variable to NULL as a requirement -#define VL_DO_CLEAR(stmt, stmt2) do { do { stmt; } while(0); do { stmt2; } while(0); } while(0) +#define VL_DO_CLEAR(stmt, stmt2) \ + do { \ + do { \ + stmt; \ + } while (false); \ + do { \ + stmt2; \ + } while (false); \ + } while (false) //========================================================================= // C++-2011 @@ -236,7 +249,9 @@ # include // ssize_t typedef unsigned char uint8_t; ///< 8-bit unsigned type (backward compatibility) typedef unsigned short int uint16_t; ///< 16-bit unsigned type (backward compatibility) +typedef char vlsint8_t; ///< 8-bit signed type typedef unsigned char vluint8_t; ///< 8-bit unsigned type +typedef short int vlsint16_t; ///< 16-bit signed type typedef unsigned short int vluint16_t; ///< 16-bit unsigned type # if defined(__uint32_t_defined) || defined(___int32_t_defined) // Newer Cygwin uint32_t in stdint.h as an unsigned int typedef int32_t vlsint32_t; ///< 32-bit signed type @@ -259,7 +274,9 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type typedef unsigned __int8 uint8_t; ///< 8-bit unsigned type (backward compatibility) typedef unsigned __int16 uint16_t; ///< 16-bit unsigned type (backward compatibility) typedef unsigned __int32 uint32_t; ///< 32-bit unsigned type (backward compatibility) +typedef signed __int8 vlsint8_t; ///< 8-bit signed type typedef unsigned __int8 vluint8_t; ///< 8-bit unsigned type +typedef signed __int16 vlsint16_t; ///< 16-bit signed type typedef unsigned __int16 vluint16_t; ///< 16-bit unsigned type typedef signed __int32 vlsint32_t; ///< 32-bit signed type typedef unsigned __int32 vluint32_t; ///< 32-bit unsigned type @@ -280,10 +297,12 @@ typedef signed __int32 ssize_t; ///< signed size_t; returned fro # include // Linux and most flavors # include // __WORDSIZE # include // ssize_t -typedef uint8_t vluint8_t; ///< 32-bit unsigned type -typedef uint16_t vluint16_t; ///< 32-bit unsigned type +typedef char vlsint8_t; ///< 8-bit signed type +typedef uint8_t vluint8_t; ///< 8-bit unsigned type +typedef short vlsint16_t; ///< 16-bit signed type +typedef uint16_t vluint16_t; ///< 16-bit unsigned type typedef int vlsint32_t; ///< 32-bit signed type -typedef uint32_t vluint32_t; ///< 32-bit signed type +typedef uint32_t vluint32_t; ///< 32-bit unsigned type # if defined(__WORDSIZE) && (__WORDSIZE == 64) typedef long vlsint64_t; ///< 64-bit signed type typedef unsigned long vluint64_t; ///< 64-bit unsigned type diff --git a/nodist/bisondiff b/nodist/bisondiff index 71120ee22..f925c15a2 100755 --- a/nodist/bisondiff +++ b/nodist/bisondiff @@ -1,15 +1,11 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2007-2020 by Wilson Snyder. This package is free software; you +# Copyright 2007-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/nodist/bisonreader b/nodist/bisonreader index 0ada7c788..561dd77be 100755 --- a/nodist/bisonreader +++ b/nodist/bisonreader @@ -1,15 +1,11 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2007-2020 by Wilson Snyder. This package is free software; you +# Copyright 2007-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/nodist/code_coverage b/nodist/code_coverage index 8a2b2b2c8..9659bedbd 100755 --- a/nodist/code_coverage +++ b/nodist/code_coverage @@ -243,11 +243,13 @@ Runs a specific stage (see the script). =head1 DISTRIBUTION -Copyright 2019-2020 by Wilson Snyder. This package is free software; you +Copyright 2019-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + =head1 AUTHORS Wilson Snyder diff --git a/nodist/code_coverage.dat b/nodist/code_coverage.dat index b9046cba6..898b65cf7 100644 --- a/nodist/code_coverage.dat +++ b/nodist/code_coverage.dat @@ -1,10 +1,11 @@ # -*- Perl -*- # DESCRIPTION: Verilator: Internal C++ code lcov control file # -# Copyright 2019-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 source_globs("src/*.cpp", "src/*.h", diff --git a/nodist/dot_importer b/nodist/dot_importer index a63c2831c..d44d02f61 100755 --- a/nodist/dot_importer +++ b/nodist/dot_importer @@ -143,9 +143,12 @@ Displays this message and program version and exits. =head1 DISTRIBUTION -Copyright 2005-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2005-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/nodist/dot_pruner b/nodist/dot_pruner index 9022b017f..aad378e5a 100755 --- a/nodist/dot_pruner +++ b/nodist/dot_pruner @@ -184,9 +184,12 @@ Displays this message and program version and exits. =head1 DISTRIBUTION -Copyright 2005-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2005-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/nodist/flexdiff b/nodist/flexdiff index 963c8fdf8..1969cf482 100755 --- a/nodist/flexdiff +++ b/nodist/flexdiff @@ -1,15 +1,11 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2007-2020 by Wilson Snyder. This package is free software; you +# Copyright 2007-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/nodist/fuzzer/actual_fail b/nodist/fuzzer/actual_fail index e69493dd2..e8d860fae 100755 --- a/nodist/fuzzer/actual_fail +++ b/nodist/fuzzer/actual_fail @@ -2,9 +2,10 @@ ###################################################################### # DESCRIPTION: Fuzzer result checker # -# Copyright 2019-2019 by Eric Rippey. This package is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser +# Copyright 2019-2019 by Eric Rippey. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # This script is designed to rerun examples to see whether they have diff --git a/nodist/fuzzer/all b/nodist/fuzzer/all index 247ecf5a0..8382a7245 100755 --- a/nodist/fuzzer/all +++ b/nodist/fuzzer/all @@ -2,9 +2,11 @@ ###################################################################### # DESCRIPTION: Fuzzer one-line setup & run # -# Copyright 2019-2019 by Eric Rippey. This package is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# Copyright 2019-2019 by Eric Rippey. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # Run all steps needed to configure and start fuzzer diff --git a/nodist/fuzzer/generate_dictionary b/nodist/fuzzer/generate_dictionary index e69ff0a77..f7196b2e3 100755 --- a/nodist/fuzzer/generate_dictionary +++ b/nodist/fuzzer/generate_dictionary @@ -2,9 +2,10 @@ ###################################################################### # DESCRIPTION: Fuzzer dictionary generator # -# Copyright 2019-2019 by Eric Rippey. This package is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser +# Copyright 2019-2019 by Eric Rippey. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU Lesser # General Public License Version 3 or the Perl Artistic License Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # Attempts to pull a list of keywords out of the Flex input diff --git a/nodist/fuzzer/run b/nodist/fuzzer/run index 7cc324d41..216a2249e 100755 --- a/nodist/fuzzer/run +++ b/nodist/fuzzer/run @@ -2,9 +2,11 @@ ###################################################################### # DESCRIPTION: Fuzzer run script # -# Copyright 2019-2019 by Eric Rippey. This package is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# Copyright 2019-2019 by Eric Rippey. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # Actually do the fuzzing. Note that this will not terminate in any reasonable diff --git a/nodist/fuzzer/setup_root b/nodist/fuzzer/setup_root index 2db484a9a..5fed7ac64 100755 --- a/nodist/fuzzer/setup_root +++ b/nodist/fuzzer/setup_root @@ -2,9 +2,11 @@ ###################################################################### # DESCRIPTION: Fuzzer setup to be run as root # -# Copyright 2019-2019 by Eric Rippey. This package is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# Copyright 2019-2019 by Eric Rippey. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # This is the portion of the fuzzer setup that must be run as root. diff --git a/nodist/fuzzer/setup_user b/nodist/fuzzer/setup_user index 407b0f152..918f03fcf 100755 --- a/nodist/fuzzer/setup_user +++ b/nodist/fuzzer/setup_user @@ -2,9 +2,11 @@ ###################################################################### # DESCRIPTION: Fuzzer setup to be run as a normal user # -# Copyright 2019-2019 by Eric Rippey. This package is free software; you can -# redistribute it and/or modify it under the terms of either the GNU Lesser -# General Public License Version 3 or the Perl Artistic License Version 2.0. +# Copyright 2019-2019 by Eric Rippey. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 ###################################################################### # This is the portion of the setup for fuzzing that does not require root access. diff --git a/nodist/fuzzer/wrapper.cpp b/nodist/fuzzer/wrapper.cpp index 25ea4b028..34995ad2e 100644 --- a/nodist/fuzzer/wrapper.cpp +++ b/nodist/fuzzer/wrapper.cpp @@ -2,10 +2,11 @@ //************************************************************************* // DESCRIPTION: Verilator fuzzing wrapper for verilator_bin // -// Copyright 2019 by Eric Rippey. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2019 by Eric Rippey. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include diff --git a/nodist/git_untabify b/nodist/git_untabify index fc355b00b..68bbbac04 100755 --- a/nodist/git_untabify +++ b/nodist/git_untabify @@ -236,9 +236,12 @@ Displays program version and exits. =head1 DISTRIBUTION -Copyright 2005-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2005-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/nodist/install_test b/nodist/install_test index 4b4025219..edc59f8c8 100755 --- a/nodist/install_test +++ b/nodist/install_test @@ -190,11 +190,13 @@ Runs a specific test stage (see the script). =head1 DISTRIBUTION -Copyright 2009-2020 by Wilson Snyder. This package is free software; you +Copyright 2009-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + =head1 AUTHORS Wilson Snyder diff --git a/nodist/invoke_atsim b/nodist/invoke_atsim index 41490042c..d7dd44268 100755 --- a/nodist/invoke_atsim +++ b/nodist/invoke_atsim @@ -28,11 +28,13 @@ invoke_atsim - Invoke tool under "modules" command =head1 DISTRIBUTION -Copyright 2005-2020 by Wilson Snyder. This package is free software; you +Copyright 2005-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + =head1 AUTHORS Wilson Snyder diff --git a/nodist/invoke_iccr b/nodist/invoke_iccr index 580dc7a72..883b9ad9a 100755 --- a/nodist/invoke_iccr +++ b/nodist/invoke_iccr @@ -28,11 +28,13 @@ invoke_iccr - Invoke tool under "modules" command =head1 DISTRIBUTION -Copyright 2007-2020 by Wilson Snyder. This package is free software; you +Copyright 2007-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + =head1 AUTHORS Wilson Snyder diff --git a/nodist/invoke_ncverilog b/nodist/invoke_ncverilog index ef2809c71..08eb51889 100755 --- a/nodist/invoke_ncverilog +++ b/nodist/invoke_ncverilog @@ -28,11 +28,13 @@ invoke_ncverilog - Invoke tool under "modules" command =head1 DISTRIBUTION -Copyright 2005-2020 by Wilson Snyder. This package is free software; you +Copyright 2005-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + =head1 AUTHORS Wilson Snyder diff --git a/nodist/invoke_vcs b/nodist/invoke_vcs index ceeaf25af..1e708e9ad 100755 --- a/nodist/invoke_vcs +++ b/nodist/invoke_vcs @@ -28,11 +28,13 @@ invoke_vcs - Invoke tool under "modules" command =head1 DISTRIBUTION -Copyright 2005-2020 by Wilson Snyder. This package is free software; you +Copyright 2005-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + =head1 AUTHORS Wilson Snyder diff --git a/nodist/vtree_importer b/nodist/vtree_importer index 652c114bd..2a2d2c497 100755 --- a/nodist/vtree_importer +++ b/nodist/vtree_importer @@ -331,9 +331,12 @@ Displays this message and program version and exits. =head1 DISTRIBUTION -Copyright 2005-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2005-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/src/.gdbinit b/src/.gdbinit index 9bed7ea0c..17532d0d2 100644 --- a/src/.gdbinit +++ b/src/.gdbinit @@ -1,9 +1,10 @@ # DESCRIPTION: Verilator: GDB startup file with useful defines # -# Copyright 2012-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2012-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 define pn call $arg0->dumpGdb() diff --git a/src/Makefile.in b/src/Makefile.in index ff0c685a2..4bf742008 100644 --- a/src/Makefile.in +++ b/src/Makefile.in @@ -7,15 +7,11 @@ # #***************************************************************************** # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# Verilator is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ diff --git a/src/Makefile_obj.in b/src/Makefile_obj.in index 4f677b61c..af74d9e8d 100644 --- a/src/Makefile_obj.in +++ b/src/Makefile_obj.in @@ -7,15 +7,11 @@ # #***************************************************************************** # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# Verilator is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ diff --git a/src/V3Active.cpp b/src/V3Active.cpp index a41f48650..bb15e55c1 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Active's Transformations: @@ -83,16 +79,12 @@ private: // Simplify sensitivity list VL_DO_DANGLING(V3Const::constifyExpensiveEdit(nodep), nodep); } - // Empty visitors, speed things up - virtual void visit(AstNodeStmt* nodep) VL_OVERRIDE { } //-------------------- - // Default - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); - } - // METHODS + virtual void visit(AstNodeStmt*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: + // METHODS AstScope* scopep() { return m_scopep; } AstActive* getCActive(FileLine* fl) { if (!m_cActivep) { @@ -210,9 +202,8 @@ private: } } //-------------------- - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS ActiveDlyVisitor(AstNode* nodep, CheckType check) { @@ -415,19 +406,17 @@ private: } } - // Empty visitors, speed things up - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE {} - virtual void visit(AstVarScope* nodep) VL_OVERRIDE {} //-------------------- - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstVarScope*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS - explicit ActiveVisitor(AstNetlist* nodep) { - m_scopeFinalp = NULL; - m_itemCombo = false; - m_itemSequent = false; + explicit ActiveVisitor(AstNetlist* nodep) + : m_scopeFinalp(NULL) + , m_itemCombo(false) + , m_itemSequent(false) { iterate(nodep); } virtual ~ActiveVisitor() {} diff --git a/src/V3Active.h b/src/V3Active.h index 070232665..cc0629e0b 100644 --- a/src/V3Active.h +++ b/src/V3Active.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ActiveTop.cpp b/src/V3ActiveTop.cpp index 924680335..43552c170 100644 --- a/src/V3ActiveTop.cpp +++ b/src/V3ActiveTop.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Active's Transformations: @@ -131,17 +127,15 @@ private: virtual void visit(AstFinal* nodep) VL_OVERRIDE { // LCOV_EXCL_LINE nodep->v3fatalSrc("Node should have been deleted"); } - // Empty visitors, speed things up - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE {} - virtual void visit(AstVarScope* nodep) VL_OVERRIDE {} //-------------------- - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstVarScope*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS - explicit ActiveTopVisitor(AstNetlist* nodep) { - m_topscopep = NULL; + explicit ActiveTopVisitor(AstNetlist* nodep) + : m_topscopep(NULL) { iterate(nodep); } virtual ~ActiveTopVisitor() {} diff --git a/src/V3ActiveTop.h b/src/V3ActiveTop.h index 9b4628de5..27a7b18d1 100644 --- a/src/V3ActiveTop.h +++ b/src/V3ActiveTop.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp index ffd983921..023450b9c 100644 --- a/src/V3Assert.cpp +++ b/src/V3Assert.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -258,12 +254,15 @@ private: // Not parallel, but harmlessly so. } else { AstNode* propp = NULL; - for (AstCaseItem* itemp = nodep->itemsp(); - itemp; itemp=VN_CAST(itemp->nextp(), CaseItem)) { - for (AstNode* icondp = itemp->condsp(); - icondp!=NULL; icondp=icondp->nextp()) { + for (AstCaseItem* itemp = nodep->itemsp(); itemp; + itemp = VN_CAST(itemp->nextp(), CaseItem)) { + for (AstNode* icondp = itemp->condsp(); icondp; icondp = icondp->nextp()) { AstNode* onep; - if (nodep->casex() || nodep->casez() || nodep->caseInside()) { + if (AstInsideRange* rcondp = VN_CAST(icondp, InsideRange)) { + onep = rcondp->newAndFromInside(nodep->exprp(), + rcondp->lhsp()->cloneTree(true), + rcondp->rhsp()->cloneTree(true)); + } else if (nodep->casex() || nodep->casez() || nodep->caseInside()) { onep = AstEqWild::newTyped(itemp->fileline(), nodep->exprp()->cloneTree(false), icondp->cloneTree(false)); @@ -381,9 +380,8 @@ private: m_beginp = lastp; } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit AssertVisitor(AstNetlist* nodep) { diff --git a/src/V3Assert.h b/src/V3Assert.h index fa8f144c7..d72625aba 100644 --- a/src/V3Assert.h +++ b/src/V3Assert.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3AssertPre.cpp b/src/V3AssertPre.cpp index 2dc09f85f..aec7c4761 100644 --- a/src/V3AssertPre.cpp +++ b/src/V3AssertPre.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // Pre steps: @@ -137,9 +133,7 @@ private: // Reset defaults m_seniDefaultp = NULL; } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3AssertPre.h b/src/V3AssertPre.h index 93e414fe6..41eceb57c 100644 --- a/src/V3AssertPre.h +++ b/src/V3AssertPre.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Ast.cpp b/src/V3Ast.cpp index 6235efc1e..42ac68911 100644 --- a/src/V3Ast.cpp +++ b/src/V3Ast.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -1208,7 +1204,7 @@ AstNodeDType* AstNode::findLogicDType(int width, int widthMin, AstNumeric numeri return v3Global.rootp()->typeTablep() ->findLogicBitDType(fileline(), AstBasicDTypeKwd::LOGIC, width, widthMin, numeric); } -AstNodeDType* AstNode::findLogicRangeDType(VNumRange range, int widthMin, +AstNodeDType* AstNode::findLogicRangeDType(const VNumRange& range, int widthMin, AstNumeric numeric) const { return v3Global.rootp()->typeTablep() ->findLogicBitDType(fileline(), AstBasicDTypeKwd::LOGIC, range, widthMin, numeric); diff --git a/src/V3Ast.h b/src/V3Ast.h index 851c4c898..edc5ca021 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -54,13 +50,13 @@ typedef std::set MTaskIdSet; // Set of mtaskIds for Var sorting #define BROKEN_RTN(test) \ do { \ if (VL_UNCOVERABLE(test)) return #test; \ - } while (0) + } while (false) // For broken() function, return error string if a base of this class has a match #define BROKEN_BASE_RTN(test) \ do { \ const char* reasonp = (test); \ if (VL_UNCOVERABLE(reasonp)) return reasonp; \ - } while (0) + } while (false) // (V)erilator (N)ode is: True if AstNode is of a a given AstType #define VN_IS(nodep,nodetypename) (AstNode::privateIs(nodep)) @@ -1563,7 +1559,8 @@ public: AstNodeDType* findVoidDType() const; AstNodeDType* findBitDType(int width, int widthMin, AstNumeric numeric) const; AstNodeDType* findLogicDType(int width, int widthMin, AstNumeric numeric) const; - AstNodeDType* findLogicRangeDType(VNumRange range, int widthMin, AstNumeric numeric) const; + AstNodeDType* findLogicRangeDType(const VNumRange& range, int widthMin, + AstNumeric numeric) const; AstNodeDType* findBasicDType(AstBasicDTypeKwd kwd) const; AstBasicDType* findInsertSameDType(AstBasicDType* nodep); @@ -1697,6 +1694,7 @@ public: // METHODS virtual bool hasDType() const { return true; } virtual string emitVerilog() = 0; /// Format string for verilog writing; see V3EmitV + // For documentation on emitC format see EmitCStmts::emitOpName virtual string emitC() = 0; virtual string emitSimpleOperator() { return ""; } virtual bool cleanOut() const = 0; // True if output has extra upper bits zero diff --git a/src/V3AstConstOnly.h b/src/V3AstConstOnly.h index ae31294ed..7278ecfbe 100644 --- a/src/V3AstConstOnly.h +++ b/src/V3AstConstOnly.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 9f57d2ba3..64df9f9df 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -197,6 +193,15 @@ AstExecGraph::~AstExecGraph() { VL_DO_DANGLING(delete m_depGraphp, m_depGraphp); } +AstNode* AstInsideRange::newAndFromInside(AstNode* exprp, AstNode* lhsp, AstNode* rhsp) { + AstNode* ap = new AstGte(fileline(), exprp->cloneTree(true), lhsp); + AstNode* bp = new AstLte(fileline(), exprp->cloneTree(true), rhsp); + ap->fileline()->modifyWarnOff(V3ErrorCode::UNSIGNED, true); + bp->fileline()->modifyWarnOff(V3ErrorCode::CMPCONST, true); + AstNode* newp = new AstAnd(fileline(), ap, bp); + return newp; +} + bool AstVar::isSigPublic() const { return (m_sigPublic || (v3Global.opt.allPublic() && !isTemp() && !isGenVar())); } diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index c060added..6a23d8435 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -3902,6 +3898,8 @@ public: virtual string emitVerilog() { return "[%l:%r]"; } virtual string emitC() { V3ERROR_NA; return ""; } virtual bool cleanOut() const { return false; } // NA + // Create AstAnd(AstGte(...), AstLte(...)) + AstNode* newAndFromInside(AstNode* exprp, AstNode* lhsp, AstNode* rhsp); }; class AstInitItem : public AstNode { @@ -4587,16 +4585,19 @@ public: virtual int instrCount() const { return instrCountDouble(); } }; class AstRToIRoundS : public AstNodeUniop { + // Convert real to integer, with arbitrary sized output (not just "integer" format) public: AstRToIRoundS(FileLine* fl, AstNode* lhsp) - : ASTGEN_SUPER(fl, lhsp) { dtypeSetSigned32(); } + : ASTGEN_SUPER(fl, lhsp) { + dtypeSetSigned32(); + } ASTNODE_NODE_FUNCS(RToIRoundS) virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opRToIRoundS(lhs); } virtual string emitVerilog() { return "%f$rtoi_rounded(%l)"; } - virtual string emitC() { return "VL_RTOIROUND_I_D(%li)"; } + virtual string emitC() { return "VL_RTOIROUND_%nq_D(%nw, %P, %li)"; } virtual bool cleanOut() const { return false; } - virtual bool cleanLhs() const { return false; } // Eliminated before matters - virtual bool sizeMattersLhs() const { return false; } // Eliminated before matters + virtual bool cleanLhs() const { return false; } + virtual bool sizeMattersLhs() const { return false; } virtual int instrCount() const { return instrCountDouble(); } }; class AstIToRD : public AstNodeUniop { diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp index 77650f7a4..80cd56fe8 100644 --- a/src/V3Begin.cpp +++ b/src/V3Begin.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Begin's Transformations: @@ -171,6 +167,18 @@ private: else m_modp->addStmtp(nodep); } } + virtual void visit(AstTypedef* nodep) VL_OVERRIDE { + if (m_unnamedScope != "") { + // Rename it + nodep->name(m_unnamedScope + "__DOT__" + nodep->name()); + m_statep->userMarkChanged(nodep); + // Move to module + nodep->unlinkFrBack(); + // Begins under funcs just move into the func + if (m_ftaskp) m_ftaskp->addStmtsp(nodep); + else m_modp->addStmtp(nodep); + } + } virtual void visit(AstCell* nodep) VL_OVERRIDE { UINFO(8," CELL "<fileline(), AstConst::LogicFalse()); } else if (AstInsideRange* irangep = VN_CAST(icondp, InsideRange)) { // Similar logic in V3Width::visit(AstInside) - AstNode* ap = AstGte::newTyped(itemp->fileline(), - cexprp->cloneTree(false), - irangep->lhsp()->unlinkFrBack()); - AstNode* bp = AstLte::newTyped(itemp->fileline(), - cexprp->cloneTree(false), - irangep->rhsp()->unlinkFrBack()); - ap->fileline()->modifyWarnOff(V3ErrorCode::UNSIGNED, true); - bp->fileline()->modifyWarnOff(V3ErrorCode::CMPCONST, true); - condp = new AstAnd(itemp->fileline(), ap, bp); + condp = irangep->newAndFromInside(cexprp, irangep->lhsp()->unlinkFrBack(), + irangep->rhsp()->unlinkFrBack()); } else if (iconstp && iconstp->num().isFourState() && (nodep->casex() || nodep->casez() || nodep->caseInside())) { V3Number nummask (itemp, iconstp->width()); @@ -475,10 +463,7 @@ private: } } //-------------------- - // Default: Just iterate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Case.h b/src/V3Case.h index ace56e8d5..1e4d916b6 100644 --- a/src/V3Case.h +++ b/src/V3Case.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Cast.cpp b/src/V3Cast.cpp index 533faa24d..4d7ee95f8 100644 --- a/src/V3Cast.cpp +++ b/src/V3Cast.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Cast's Transformations: @@ -161,13 +157,10 @@ private: } // NOPs - virtual void visit(AstVar* nodep) VL_OVERRIDE {} + virtual void visit(AstVar*) VL_OVERRIDE {} //-------------------- - // Default: Just iterate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Cast.h b/src/V3Cast.h index 0b9cd167f..d18fc641b 100644 --- a/src/V3Cast.h +++ b/src/V3Cast.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp index 0ffa208c5..0fc002f27 100644 --- a/src/V3Cdc.cpp +++ b/src/V3Cdc.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Cdc's Transformations: @@ -506,7 +502,7 @@ private: for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp=itp->verticesNextp()) { if (CdcVarVertex* vvertexp = dynamic_cast(itp)) { AstVar* varp = vvertexp->varScp()->varp(); - if (1) { // varp->isPrimaryIO() + { string what = "wire"; if (varp->isPrimaryIO()) what = varp->direction().prettyName(); @@ -696,7 +692,7 @@ private: } // Math that shouldn't cause us to clear hazard - virtual void visit(AstConst* nodep) VL_OVERRIDE { } + virtual void visit(AstConst*) VL_OVERRIDE {} virtual void visit(AstReplicate* nodep) VL_OVERRIDE { iterateChildren(nodep); } @@ -716,10 +712,10 @@ private: } // Ignores - virtual void visit(AstInitial* nodep) VL_OVERRIDE { } - virtual void visit(AstTraceInc* nodep) VL_OVERRIDE { } - virtual void visit(AstCoverToggle* nodep) VL_OVERRIDE { } - virtual void visit(AstNodeDType* nodep) VL_OVERRIDE { } + virtual void visit(AstInitial*) VL_OVERRIDE {} + virtual void visit(AstTraceInc*) VL_OVERRIDE {} + virtual void visit(AstCoverToggle*) VL_OVERRIDE {} + virtual void visit(AstNodeDType*) VL_OVERRIDE {} //-------------------- // Default @@ -727,9 +723,7 @@ private: setNodeHazard(nodep); iterateChildren(nodep); } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -756,11 +750,11 @@ public: iterate(nodep); analyze(); - if (debug()>=1) edgeReport(); // Not useful to users at the moment - if (0) { - *m_ofp<<"\nDBG-test-dumper\n"; + if (debug() >= 1) edgeReport(); // Not useful to users at the moment + if (false) { + *m_ofp << "\nDBG-test-dumper\n"; V3EmitV::verilogPrefixedTree(nodep, *m_ofp, "DBG ", 40, NULL, true); - *m_ofp<varp()) nodep->varp()->user4(1); } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit ConstVarMarkVisitor(AstNode* nodep) { @@ -71,9 +66,8 @@ private: virtual void visit(AstVarRef* nodep) VL_OVERRIDE { if (nodep->varp() && nodep->varp()->user4()) m_found = true; } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit ConstVarFindVisitor(AstNode* nodep) { @@ -596,15 +590,12 @@ private: bool rad = ifMergeAdjacent(lp->rhsp(), rp->rhsp()); if (lad && rad) return true; // {a[] & b[]&c[], a[] & b[]&c[]} - else if (lad && concatMergeable(lp->rhsp(), rp->rhsp())) return true; + if (lad && concatMergeable(lp->rhsp(), rp->rhsp())) return true; // {a[]&b[] & c[], a[]&b[] & c[]} - else if (rad && concatMergeable(lp->lhsp(), rp->lhsp())) return true; - else { - // {(a[]&b[])&(c[]&d[]), (a[]&b[])&(c[]&d[])} - if (concatMergeable(lp->lhsp(), rp->lhsp()) - && concatMergeable(lp->rhsp(), rp->rhsp())) - return true; - } + if (rad && concatMergeable(lp->lhsp(), rp->lhsp())) return true; + // {(a[]&b[])&(c[]&d[]), (a[]&b[])&(c[]&d[])} + if (concatMergeable(lp->lhsp(), rp->lhsp()) + && concatMergeable(lp->rhsp(), rp->rhsp())) return true; return false; } @@ -1374,7 +1365,7 @@ private: } // Special cases - virtual void visit(AstConst* nodep) VL_OVERRIDE {} // Already constant + virtual void visit(AstConst*) VL_OVERRIDE {} // Already constant virtual void visit(AstCell* nodep) VL_OVERRIDE { if (m_params) { @@ -2162,7 +2153,7 @@ private: // These are converted by V3Param. Don't constify as we don't want the // from() VARREF to disappear, if any. // If output of a presel didn't get consted, chances are V3Param didn't visit properly - virtual void visit(AstNodePreSel* nodep) VL_OVERRIDE {} + virtual void visit(AstNodePreSel*) VL_OVERRIDE {} // Ignored, can eliminate early virtual void visit(AstSysIgnore* nodep) VL_OVERRIDE { diff --git a/src/V3Const.h b/src/V3Const.h index 803fc0f0d..a7a45aca6 100644 --- a/src/V3Const.h +++ b/src/V3Const.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index c1f8ef3e7..69f8288c8 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // COVERAGE TRANSFORMATIONS: @@ -403,7 +399,6 @@ private: // VISITORS - BOTH virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate if (m_checkBlock) { iterateChildren(nodep); m_checkBlock = true; // Reset as a child may have cleared it diff --git a/src/V3Coverage.h b/src/V3Coverage.h index 311bd4b7d..b24b25ee8 100644 --- a/src/V3Coverage.h +++ b/src/V3Coverage.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3CoverageJoin.cpp b/src/V3CoverageJoin.cpp index 1cbf77c1e..f721b4eeb 100644 --- a/src/V3CoverageJoin.cpp +++ b/src/V3CoverageJoin.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // COVERAGEJOIN TRANSFORMATIONS: @@ -72,7 +68,7 @@ private: // Want to choose a base node, and keep finding duplicates that are identical. // This prevents making chains where a->b, then c->d, then b->c, as we'll // find a->b, a->c, a->d directly. - while (1) { + while (true) { V3Hashed::iterator dupit = hashed.findDuplicate(nodep->origp()); if (dupit == hashed.end()) break; // @@ -113,10 +109,8 @@ private: iterateChildren(nodep); } //-------------------- - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE {} // Accelerate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3CoverageJoin.h b/src/V3CoverageJoin.h index a9ee2a82c..1983db564 100644 --- a/src/V3CoverageJoin.h +++ b/src/V3CoverageJoin.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Dead.cpp b/src/V3Dead.cpp index a98ff7bfb..2f9fcf83c 100644 --- a/src/V3Dead.cpp +++ b/src/V3Dead.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // DEAD TRANSFORMATIONS: @@ -62,10 +58,9 @@ private: nodep->modp()->user1Inc(-1); } //----- - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE {} // Accelerate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit DeadModVisitor(AstNodeModule* nodep) { diff --git a/src/V3Dead.h b/src/V3Dead.h index e670b31d5..6ef94b8d6 100644 --- a/src/V3Dead.h +++ b/src/V3Dead.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index 75ac8f17c..575ba1ab4 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Delayed's Transformations: @@ -455,10 +451,7 @@ private: } //-------------------- - // Default: Just iterate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Delayed.h b/src/V3Delayed.h index 9d7bc8f45..cdacae1ff 100644 --- a/src/V3Delayed.h +++ b/src/V3Delayed.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp index e04a62393..8763ca6b8 100644 --- a/src/V3Depth.cpp +++ b/src/V3Depth.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Depth's Transformations: @@ -154,10 +150,8 @@ private: //-------------------- // Default: Just iterate - virtual void visit(AstVar* nodep) VL_OVERRIDE {} // Don't hit varrefs under vars - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstVar*) VL_OVERRIDE {} // Don't hit varrefs under vars + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Depth.h b/src/V3Depth.h index 75c673d2b..6527afab8 100644 --- a/src/V3Depth.h +++ b/src/V3Depth.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3DepthBlock.cpp b/src/V3DepthBlock.cpp index 6ddb7e774..2abd25e6c 100644 --- a/src/V3DepthBlock.cpp +++ b/src/V3DepthBlock.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3DepthBlock's Transformations: @@ -117,13 +113,10 @@ private: } } - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate //-------------------- - // Default: Just iterate - virtual void visit(AstVar* nodep) VL_OVERRIDE {} // Don't hit varrefs under vars - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstVar*) VL_OVERRIDE {} // Don't hit varrefs under vars + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3DepthBlock.h b/src/V3DepthBlock.h index 745763dc3..2ba04b280 100644 --- a/src/V3DepthBlock.h +++ b/src/V3DepthBlock.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp index 4f0ca0aad..393254244 100644 --- a/src/V3Descope.cpp +++ b/src/V3Descope.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // DESCOPE TRANSFORMATIONS: diff --git a/src/V3Descope.h b/src/V3Descope.h index 2589898ef..f808a5a8d 100644 --- a/src/V3Descope.h +++ b/src/V3Descope.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 5196060b4..71c70f214 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitC.h b/src/V3EmitC.h index 718f6070e..0bd5ec642 100644 --- a/src/V3EmitC.h +++ b/src/V3EmitC.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCBase.h b/src/V3EmitCBase.h index 19da8a1fd..d0c9d76f8 100644 --- a/src/V3EmitCBase.h +++ b/src/V3EmitCBase.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCInlines.cpp b/src/V3EmitCInlines.cpp index 5d60724af..d3fa0084c 100644 --- a/src/V3EmitCInlines.cpp +++ b/src/V3EmitCInlines.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -100,12 +96,9 @@ class EmitCInlines : EmitCBaseVisitor { iterateChildren(nodep); } - // Default - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } //--------------------------------------- - // ACCESSORS + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: explicit EmitCInlines(AstNetlist* nodep) { iterate(nodep); diff --git a/src/V3EmitCMake.cpp b/src/V3EmitCMake.cpp index 2de114211..2eed8feb8 100644 --- a/src/V3EmitCMake.cpp +++ b/src/V3EmitCMake.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -74,12 +70,11 @@ class CMakeEmitter { cmake_set_raw(of, name, raw_value, cache_type, docstring); } - //Swap all backslashes for forward slashes, because of Windows + // Swap all backslashes for forward slashes, because of Windows static string deslash(const string& s) { std::string res = s; for (string::iterator it = res.begin(); it != res.end(); ++it) { - if (*it == '\\') - *it = '/'; + if (*it == '\\') *it = '/'; } return res; } diff --git a/src/V3EmitCMake.h b/src/V3EmitCMake.h index 6c309450d..9cfe9275a 100644 --- a/src/V3EmitCMake.h +++ b/src/V3EmitCMake.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 69dbc8ad4..ee532ba1d 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -145,7 +141,7 @@ class EmitCSyms : EmitCBaseVisitor { string scopeDecodeIdentifier(const string& scpname) { string out = scpname; // Remove hierarchy - string::size_type pos = out.rfind("."); + string::size_type pos = out.rfind('.'); if (pos != std::string::npos) out.erase(0, pos + 1); // Decode all escaped characters while ((pos = out.find("__0")) != string::npos) { @@ -167,10 +163,8 @@ class EmitCSyms : EmitCBaseVisitor { } string::size_type pos = scp.rfind("__DOT__"); if (pos == string::npos) { - pos = scp.rfind("."); - if (pos == string::npos) { - break; - } + pos = scp.rfind('.'); + if (pos == string::npos) break; } scp.resize(pos); } @@ -232,10 +226,8 @@ class EmitCSyms : EmitCBaseVisitor { string above = name; while (!above.empty()) { - string::size_type pos = above.rfind("."); - if (pos == string::npos) { - break; - } + string::size_type pos = above.rfind('.'); + if (pos == string::npos) break; above.resize(pos); if (m_vpiScopeHierarchy.find(above) != m_vpiScopeHierarchy.end()) { m_vpiScopeHierarchy[above].push_back(name); @@ -345,18 +337,14 @@ class EmitCSyms : EmitCBaseVisitor { iterateChildren(nodep); m_funcp = NULL; } - // NOPs - virtual void visit(AstConst*) VL_OVERRIDE {} - // Default - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + //--------------------------------------- - // ACCESSORS + virtual void visit(AstConst*) VL_OVERRIDE {} + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: - explicit EmitCSyms(AstNetlist* nodep, bool dpiHdrOnly): - m_dpiHdrOnly(dpiHdrOnly) - { + explicit EmitCSyms(AstNetlist* nodep, bool dpiHdrOnly) + : m_dpiHdrOnly(dpiHdrOnly) { m_funcp = NULL; m_modp = NULL; m_coverBins = 0; @@ -675,8 +663,8 @@ void EmitCSyms::emitSymImp() { string name = it->second.m_prettyName; if (it->first == "TOP") continue; name = name.replace(0, 4, ""); // Remove the "TOP." - if ((name.find(".") == string::npos) && (it->second.m_type == "SCOPE_MODULE")) { - puts("__Vhier.add(0, &"+protect("__Vscope_"+it->second.m_symName)+");\n"); + if ((name.find('.') == string::npos) && (it->second.m_type == "SCOPE_MODULE")) { + puts("__Vhier.add(0, &" + protect("__Vscope_" + it->second.m_symName) + ");\n"); } } diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index c8a83ce2a..9efdad47f 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -51,6 +47,9 @@ public: of.puts("\n### Switches...\n"); of.puts("# Coverage output mode? 0/1 (from --coverage)\n"); of.puts("VM_COVERAGE = "); of.puts(v3Global.opt.coverage()?"1":"0"); of.puts("\n"); + of.puts("# Parallel builds? 0/1 (from --output-split)\n"); + of.puts("VM_PARALLEL_BUILDS = "); + of.puts(v3Global.opt.outputSplit() ? "1" : "0"); of.puts("\n"); of.puts("# Threaded output mode? 0/1/N threads (from --threads)\n"); of.puts("VM_THREADS = "); of.puts(cvtToStr(v3Global.opt.threads())); of.puts("\n"); of.puts("# Tracing output mode? 0/1 (from --trace)\n"); diff --git a/src/V3EmitMk.h b/src/V3EmitMk.h index eb7c0d4da..809e65173 100644 --- a/src/V3EmitMk.h +++ b/src/V3EmitMk.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3EmitV.cpp b/src/V3EmitV.cpp index afa57b8cf..7cd2a7be6 100644 --- a/src/V3EmitV.cpp +++ b/src/V3EmitV.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -744,7 +740,7 @@ public: void V3EmitV::emitv() { UINFO(2,__FUNCTION__<<": "<= as would otherwise recurse - v3fatal("Exiting due to too many errors encountered; --error-limit="<= (level))) { cout << stmsg; } } #ifdef VL_DEBUG -# define UDEBUGONLY(stmts) {stmts} +# define UDEBUGONLY(stmts) \ + { stmts } #else -# define UDEBUGONLY(stmts) {if (0) {stmts}} +# define UDEBUGONLY(stmts) \ + { if (false) { stmts } } #endif // Assertion without object, generally UOBJASSERT preferred #define UASSERT(condition,stmsg) \ - do { if (VL_UNCOVERABLE(!(condition))) { v3fatalSrc(stmsg); }} while(0) + do { if (VL_UNCOVERABLE(!(condition))) { v3fatalSrc(stmsg); }} while (false) // Assertion with object #define UASSERT_OBJ(condition,obj,stmsg) \ - do { if (VL_UNCOVERABLE(!(condition))) { (obj)->v3fatalSrc(stmsg); }} while(0) + do { if (VL_UNCOVERABLE(!(condition))) { (obj)->v3fatalSrc(stmsg); }} while (false) // For use in V3Ast static functions only #define UASSERT_STATIC(condition,stmsg) \ do { if (VL_UNCOVERABLE(!(condition))) { \ std::cerr<<"Internal Error: "<<__FILE__<<":"< will work to control UINFOs in diff --git a/src/V3Expand.cpp b/src/V3Expand.cpp index 0510e6087..5fe34563f 100644 --- a/src/V3Expand.cpp +++ b/src/V3Expand.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Expand's Transformations: @@ -954,11 +950,8 @@ private: } //-------------------- - // Default: Just iterate virtual void visit(AstVar*) VL_OVERRIDE {} // Don't hit varrefs under vars - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Expand.h b/src/V3Expand.h index 2a28294d7..f0eb83608 100644 --- a/src/V3Expand.h +++ b/src/V3Expand.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3File.cpp b/src/V3File.cpp index 5347268b3..8a0ae3e08 100644 --- a/src/V3File.cpp +++ b/src/V3File.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -1028,10 +1024,10 @@ public: string out; string::size_type start = 0; // space, ., -> - while (1) { + while (true) { // When C++11, use find_if and lambda string::size_type pos = string::npos; - string separator = ""; + string separator; trySep(old, start, " ", pos/*ref*/, separator/*ref*/); trySep(old, start, ".", pos/*ref*/, separator/*ref*/); trySep(old, start, "->", pos/*ref*/, separator/*ref*/); diff --git a/src/V3File.h b/src/V3File.h index d974058b5..c5cb7fe2f 100644 --- a/src/V3File.h +++ b/src/V3File.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp index 7dad8ea66..60984003b 100644 --- a/src/V3FileLine.cpp +++ b/src/V3FileLine.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -103,8 +99,8 @@ void VFileContent::pushText(const string& text) { // Insert line-by-line string::size_type line_start = 0; - while (1) { - string::size_type line_end = leftover.find("\n", line_start); + while (true) { + string::size_type line_end = leftover.find('\n', line_start); if (line_end != string::npos) { string oneline (leftover, line_start, line_end-line_start+1); m_lines.push_back(oneline); // Keeps newline @@ -288,7 +284,7 @@ string FileLine::asciiLineCol() const { } string FileLine::ascii() const { // For most errors especially in the parser the lastLineno is more accurate than firstLineno - return filename()+":"+cvtToStr(lastLineno()); + return filename() + ":" + cvtToStr(lastLineno()) + ":" + cvtToStr(firstColumn()); } std::ostream& operator<<(std::ostream& os, FileLine* fileline) { os <ascii()<<": "< | " + return "\n%Error: internal tracking of file contents failed"; + } else { + return ""; + } } return m_contentp->getLine(m_contentLineno); } @@ -393,19 +393,22 @@ string FileLine::prettySource() const { string FileLine::warnContext(bool secondary) const { V3Error::errorContexted(true); if (!v3Global.opt.context()) return ""; - string out = ""; - if (firstLineno()==lastLineno() && firstColumn()) { + string out; + if (firstLineno() == lastLineno() && firstColumn()) { string sourceLine = prettySource(); // Don't show super-long lines as can fill screen and unlikely to help user - if (!sourceLine.empty() - && sourceLine.length() < SHOW_SOURCE_MAX_LENGTH - && sourceLine.length() >= (size_t)(lastColumn()-1)) { - out += sourceLine+"\n"; - out += string((firstColumn()-1), ' ')+'^'; + if (!sourceLine.empty() && sourceLine.length() < SHOW_SOURCE_MAX_LENGTH + && sourceLine.length() >= static_cast(lastColumn() - 1)) { + string linestr = cvtToStr(firstLineno()); + while (linestr.size() < 5) + linestr = ' ' + linestr; + out += linestr + " | " + sourceLine + "\n"; + out += std::string(linestr.size(), ' ') + " | "; + out += string((firstColumn() - 1), ' ') + '^'; // Can't use UASSERT_OBJ used in warnings already inside the error end handler if (lastColumn() > firstColumn()) { // Note lastColumn() can be <= firstColumn() in some weird preproc expansions - out += string((lastColumn()-firstColumn()-1), '~'); + out += string((lastColumn() - firstColumn() - 1), '~'); } out += "\n"; } @@ -413,8 +416,8 @@ string FileLine::warnContext(bool secondary) const { if (!secondary) { // Avoid printing long paths on informational part of error for (FileLine* parentFl = parent(); parentFl; parentFl = parentFl->parent()) { if (parentFl->filenameIsGlobal()) break; - out += parentFl->warnOther()+"... note: In file included from " - +parentFl->filebasename()+"\n"; + out += parentFl->warnOther() + "... note: In file included from " + + parentFl->filebasename() + "\n"; } } return out; @@ -448,7 +451,7 @@ void FileLine::deleteAllRemaining() { // FileLines are allocated, but never nicely freed, as it's much faster // that way. Unfortunately this makes our leak checking a big mess, so // only when leak checking we'll track them all and cleanup. - while (1) { + while (true) { FileLineCheckSet::iterator it = fileLineLeakChecks.begin(); if (it==fileLineLeakChecks.end()) break; delete *it; diff --git a/src/V3FileLine.h b/src/V3FileLine.h index dc9643d26..09953ef14 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp index 7ecacc26a..117145039 100644 --- a/src/V3Gate.cpp +++ b/src/V3Gate.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Gate's Transformations: @@ -219,17 +215,13 @@ private: if (m_lhsVarRef) clearSimple(">1 lhs varRefs"); m_lhsVarRef = nodep; } else { - if (m_rhsVarRefs.size()>1) { + if (m_rhsVarRefs.size() > 1) { AstNodeVarRef* lastRefp = m_rhsVarRefs.back(); - if (0) { // Disable the multiple-input optimization - clearSimple(">1 rhs varRefs"); - } else { - if (m_buffersOnly) clearSimple(">1 rhs varRefs"); - if (!nodep->varScopep()->varp()->gateMultiInputOptimizable() - // We didn't check multiInput on the first varref, so check it here - || !lastRefp->varScopep()->varp()->gateMultiInputOptimizable()) { - clearSimple("!gateMultiInputOptimizable"); - } + if (m_buffersOnly) clearSimple(">1 rhs varRefs"); + if (!nodep->varScopep()->varp()->gateMultiInputOptimizable() + // We didn't check multiInput on the first varref, so check it here + || !lastRefp->varScopep()->varp()->gateMultiInputOptimizable()) { + clearSimple("!gateMultiInputOptimizable"); } } m_rhsVarRefs.push_back(nodep); @@ -257,7 +249,6 @@ private: } } //-------------------- - // Default virtual void visit(AstNode* nodep) VL_OVERRIDE { // *** Special iterator if (!m_isSimple) return; // Fastpath @@ -272,6 +263,7 @@ private: } else iterateChildren(nodep); } + public: // CONSTRUCTORS GateOkVisitor(AstNode* nodep, bool buffersOnly, bool dedupe) { @@ -531,7 +523,6 @@ private: } //-------------------- - // Default virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); if (nodep->isOutputter() && m_logicVertexp) m_logicVertexp->setConsumed("outputter"); @@ -569,7 +560,7 @@ void GateVisitor::optimizeSignals(bool allowMultiIn) { && !vvertexp->varScp()->varp()->valuep() && !vvertexp->varScp()->varp()->isSigPublic()) { UINFO(4, "No drivers "<varScp()<deleteTree(), nodep); } } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS virtual ~GateElimVisitor() {} @@ -1448,10 +1438,8 @@ private: iterate(nodep->lhsp()); } //-------------------- - // Default - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS GateConcatVisitor() { @@ -1632,11 +1620,9 @@ private: } } // Speedups - virtual void visit(AstVar* nodep) VL_OVERRIDE {} - virtual void visit(AstActive* nodep) VL_OVERRIDE {} - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstVar*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstActive*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Gate.h b/src/V3Gate.h index c57144139..4248ce6f8 100644 --- a/src/V3Gate.h +++ b/src/V3Gate.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GenClk.cpp b/src/V3GenClk.cpp index eda3e027c..8d7d53614 100644 --- a/src/V3GenClk.cpp +++ b/src/V3GenClk.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // GENCLK TRANSFORMATIONS: @@ -121,9 +117,8 @@ private: } //----- - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS GenClkRenameVisitor(AstTopScope* nodep, AstNodeModule* topModp) { @@ -220,9 +215,8 @@ private: //----- virtual void visit(AstVar*) VL_OVERRIDE {} // Don't want varrefs under it - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit GenClkReadVisitor(AstNetlist* nodep) diff --git a/src/V3GenClk.h b/src/V3GenClk.h index d25b1be25..38d4c7ec6 100644 --- a/src/V3GenClk.h +++ b/src/V3GenClk.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Global.cpp b/src/V3Global.cpp index 62a53f233..226eb6915 100644 --- a/src/V3Global.cpp +++ b/src/V3Global.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Global.h b/src/V3Global.h index da20b88cd..d97c20274 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Graph.cpp b/src/V3Graph.cpp index 5233e4b6d..108acd9ca 100644 --- a/src/V3Graph.cpp +++ b/src/V3Graph.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -350,7 +346,7 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) const { // Print vertices int n = 0; string subgr; - for (SubgraphMmap::iterator it = subgraphs.begin(); it!=subgraphs.end(); ++it) { + for (SubgraphMmap::const_iterator it = subgraphs.begin(); it != subgraphs.end(); ++it) { string vertexSubgraph = it->first; V3GraphVertex* vertexp = it->second; numMap[vertexp] = n; diff --git a/src/V3Graph.h b/src/V3Graph.h index 14c757494..7249c97a0 100644 --- a/src/V3Graph.h +++ b/src/V3Graph.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphAcyc.cpp b/src/V3GraphAcyc.cpp index a36709075..55d00294a 100644 --- a/src/V3GraphAcyc.cpp +++ b/src/V3GraphAcyc.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphAlg.cpp b/src/V3GraphAlg.cpp index aad179fe0..9120f8f98 100644 --- a/src/V3GraphAlg.cpp +++ b/src/V3GraphAlg.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphAlg.h b/src/V3GraphAlg.h index 78aeeda31..073c48c98 100644 --- a/src/V3GraphAlg.h +++ b/src/V3GraphAlg.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -38,7 +34,8 @@ protected: V3EdgeFuncP m_edgeFuncp; // Function that says we follow this edge // CONSTRUCTORS GraphAlg(T_Graph* graphp, V3EdgeFuncP edgeFuncp) - : m_graphp(graphp), m_edgeFuncp(edgeFuncp) {} + : m_graphp(graphp) + , m_edgeFuncp(edgeFuncp) {} ~GraphAlg() {} // METHODS inline bool followEdge(V3GraphEdge* edgep) { diff --git a/src/V3GraphDfa.cpp b/src/V3GraphDfa.cpp index 81af99039..3804c3272 100644 --- a/src/V3GraphDfa.cpp +++ b/src/V3GraphDfa.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphDfa.h b/src/V3GraphDfa.h index 193279631..0edf4bb5b 100644 --- a/src/V3GraphDfa.h +++ b/src/V3GraphDfa.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphPathChecker.cpp b/src/V3GraphPathChecker.cpp index e510e4b30..409c8737f 100644 --- a/src/V3GraphPathChecker.cpp +++ b/src/V3GraphPathChecker.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphPathChecker.h b/src/V3GraphPathChecker.h index 7b6024eee..2f6675460 100644 --- a/src/V3GraphPathChecker.h +++ b/src/V3GraphPathChecker.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -40,7 +36,7 @@ class GraphPathChecker : GraphAlg { // through the same node twice while searching for a path. vluint64_t m_generation; - public: +public: // CONSTRUCTORS explicit GraphPathChecker(const V3Graph* graphp, V3EdgeFuncP edgeFuncp = V3GraphEdge::followAlwaysTrue); @@ -54,9 +50,8 @@ class GraphPathChecker : GraphAlg { // removed. Detect such an edge. bool isTransitiveEdge(const V3GraphEdge* edgep); - private: - bool pathExistsInternal(const V3GraphVertex* ap, - const V3GraphVertex* bp, +private: + bool pathExistsInternal(const V3GraphVertex* ap, const V3GraphVertex* bp, unsigned* costp = NULL); void initHalfCriticalPaths(GraphWay way, bool checkOnly); void incGeneration() { ++m_generation; } diff --git a/src/V3GraphStream.h b/src/V3GraphStream.h index b949b0418..bf5f4d02b 100644 --- a/src/V3GraphStream.h +++ b/src/V3GraphStream.h @@ -7,15 +7,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3GraphTest.cpp b/src/V3GraphTest.cpp index cd1e2e3fb..3a6d3fcd3 100644 --- a/src/V3GraphTest.cpp +++ b/src/V3GraphTest.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Hashed.cpp b/src/V3Hashed.cpp index ad22028eb..887118e18 100644 --- a/src/V3Hashed.cpp +++ b/src/V3Hashed.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Hashed's Transformations: @@ -87,23 +83,23 @@ private: } //-------------------- - // Default: Just iterate virtual void visit(AstVar*) VL_OVERRIDE {} virtual void visit(AstTypedef*) VL_OVERRIDE {} virtual void visit(AstParamTypeDType*) VL_OVERRIDE {} virtual void visit(AstNode* nodep) VL_OVERRIDE { + // Hash not just iterate nodeHashIterate(nodep); } public: // CONSTRUCTORS - explicit HashedVisitor(AstNode* nodep) { - m_cacheInUser4 = true; + explicit HashedVisitor(AstNode* nodep) + : m_cacheInUser4(true) { nodeHashIterate(nodep); - //UINFO(9," stmthash "<(nodep)); } V3Hash finalHash() const { return m_lowerHash; } diff --git a/src/V3Hashed.h b/src/V3Hashed.h index 063d0a09a..0915c7385 100644 --- a/src/V3Hashed.h +++ b/src/V3Hashed.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index 364b3ec77..382d75263 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Inline's Transformations: @@ -58,19 +54,21 @@ private: // AstNodeModule::user2() // CIL_*. Allowed to automatically inline module // AstNodeModule::user3() // int. Number of cells referencing this module // AstNodeModule::user4() // int. Statements in module - AstUser2InUse m_inuser2; - AstUser3InUse m_inuser3; - AstUser4InUse m_inuser4; + AstUser2InUse m_inuser2; + AstUser3InUse m_inuser3; + AstUser4InUse m_inuser4; // For the user2 field: - enum {CIL_NOTHARD=0, // Inline not supported - CIL_NOTSOFT, // Don't inline unless user overrides - CIL_MAYBE, // Might inline - CIL_USER}; // Pragma suggests inlining + enum { + CIL_NOTHARD = 0, // Inline not supported + CIL_NOTSOFT, // Don't inline unless user overrides + CIL_MAYBE, // Might inline + CIL_USER + }; // Pragma suggests inlining // STATE - AstNodeModule* m_modp; // Current module - VDouble0 m_statUnsup; // Statistic tracking + AstNodeModule* m_modp; // Current module + VDouble0 m_statUnsup; // Statistic tracking typedef std::vector ModVec; ModVec m_allMods; // All modules, in top-down order. @@ -87,13 +85,13 @@ private: void cantInline(const char* reason, bool hard) { if (hard) { if (m_modp->user2() != CIL_NOTHARD) { - UINFO(4," No inline hard: "<user2(CIL_NOTHARD); ++m_statUnsup; } } else { if (m_modp->user2() == CIL_MAYBE) { - UINFO(4," No inline soft: "<user2(CIL_NOTSOFT); } } @@ -123,7 +121,7 @@ private: } virtual void visit(AstPragma* nodep) VL_OVERRIDE { if (nodep->pragType() == AstPragmaType::INLINE_MODULE) { - //UINFO(0,"PRAG MARK "<v3error("Inline pragma not under a module"); // LCOV_EXCL_LINE } else if (m_modp->user2() == CIL_MAYBE @@ -172,7 +170,7 @@ private: // Iterate through all modules in bottom-up order. // Make a final inlining decision for each. - for (ModVec::reverse_iterator it=m_allMods.rbegin(); it!=m_allMods.rend(); ++it) { + for (ModVec::reverse_iterator it = m_allMods.rbegin(); it != m_allMods.rend(); ++it) { AstNodeModule* modp = *it; // If we're going to inline some modules into this one, @@ -195,19 +193,18 @@ private: // If a mod*#refs is < this # nodes, can inline it bool doit = ((allowed == CIL_USER) || ((allowed == CIL_MAYBE) - && (refs==1 + && (refs == 1 || statements < INLINE_MODS_SMALLER || v3Global.opt.inlineMult() < 1 - || refs*statements < v3Global.opt.inlineMult()))); + || refs * statements < v3Global.opt.inlineMult()))); // Packages aren't really "under" anything so they confuse this algorithm if (VN_IS(modp, Package)) doit = false; - UINFO(4, " Inline="<user1(doit); } } //-------------------- - // Default: Just iterate virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); if (m_modp) { @@ -247,12 +244,10 @@ private: virtual void visit(AstCell* nodep) VL_OVERRIDE { nodep->user4p(nodep->clonep()); } - // Accelerate - virtual void visit(AstNodeStmt* nodep) VL_OVERRIDE {} - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE {} - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + //-------------------- + virtual void visit(AstNodeStmt*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -274,9 +269,9 @@ private: // See InlineVisitor // STATE - StringSet m_renamedInterfaces; // Name of renamed interface variables - AstNodeModule* m_modp; // Current module - AstCell* m_cellp; // Cell being cloned + StringSet m_renamedInterfaces; // Name of renamed interface variables + AstNodeModule* m_modp; // Current module + AstCell* m_cellp; // Cell being cloned // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -289,7 +284,7 @@ private: // Rename string name = m_cellp->name() + "__DOT__" + nodep->name(); nodep->name(name); - UINFO(6, " Inline "<user2p()) { // Make an assignment, so we'll trace it properly // user2p is either a const or a var. - AstConst* exprconstp = VN_CAST(nodep->user2p(), Const); + AstConst* exprconstp = VN_CAST(nodep->user2p(), Const); AstVarRef* exprvarrefp = VN_CAST(nodep->user2p(), VarRef); - UINFO(8,"connectto: "<user2p()<user2p() << endl); UASSERT_OBJ(exprconstp || exprvarrefp, nodep, "Unknown interconnect type; pinReconnectSimple should have cleared up"); if (exprconstp) { @@ -320,7 +315,7 @@ private: // Public variable at the lower module end - we need to make sure we propagate // the logic changes up and down; if we aliased, we might // remove the change detection on the output variable. - UINFO(9,"public pin assign: "<isNonOutput(), nodep, "Outputs only - inputs use AssignAlias"); m_modp->addStmtp( new AstAssignW(nodep->fileline(), @@ -330,7 +325,7 @@ private: // Public variable at this end and it is an unpacked array. We need to assign // instead of aliased, because otherwise it will pass V3Slice and invalid // code will be emitted. - UINFO(9,"assign to public and unpacked: "<addStmtp( new AstAssignW(nodep->fileline(), new AstVarRef(nodep->fileline(), exprvarrefp->varp(), true), @@ -342,8 +337,8 @@ private: new AstVarRef(nodep->fileline(), exprvarrefp->varp(), false))); AstNode* nodebp = exprvarrefp->varp(); - nodep ->fileline()->modifyStateInherit(nodebp->fileline()); - nodebp->fileline()->modifyStateInherit(nodep ->fileline()); + nodep->fileline()->modifyStateInherit(nodebp->fileline()); + nodebp->fileline()->modifyStateInherit(nodep->fileline()); } else { // Do to inlining child's variable now within the same // module, so a AstVarRef not AstVarXRef below @@ -353,8 +348,8 @@ private: new AstVarRef(nodep->fileline(), exprvarrefp->varp(), false))); AstNode* nodebp = exprvarrefp->varp(); - nodep ->fileline()->modifyStateInherit(nodebp->fileline()); - nodebp->fileline()->modifyStateInherit(nodep ->fileline()); + nodep->fileline()->modifyStateInherit(nodebp->fileline()); + nodebp->fileline()->modifyStateInherit(nodep->fileline()); } } // Iterate won't hit AstIfaceRefDType directly as it is no longer underneath the module @@ -383,8 +378,8 @@ private: string name = m_cellp->name() + "__DOT__" + nodep->name(); if (!nodep->isFuncLocal()) nodep->inlineAttrReset(name); if (!m_cellp->isTrace()) nodep->trace(false); - if (debug()>=9) { nodep->dumpTree(cout, "varchanged:"); } - if (debug()>=9 && nodep->valuep()) { nodep->valuep()->dumpTree(cout, "varchangei:"); } + if (debug() >= 9) { nodep->dumpTree(cout, "varchanged:"); } + if (debug() >= 9 && nodep->valuep()) { nodep->valuep()->dumpTree(cout, "varchangei:"); } iterateChildren(nodep); } virtual void visit(AstNodeFTask* nodep) VL_OVERRIDE { @@ -401,17 +396,15 @@ private: if (nodep->varp()->user2p() // It's being converted to an alias. && !nodep->varp()->user3() && !VN_IS(nodep->backp(), AssignAlias)) { // Don't constant propagate aliases (we just made) - AstConst* exprconstp = VN_CAST(nodep->varp()->user2p(), Const); + AstConst* exprconstp = VN_CAST(nodep->varp()->user2p(), Const); AstVarRef* exprvarrefp = VN_CAST(nodep->varp()->user2p(), VarRef); if (exprconstp) { nodep->replaceWith(exprconstp->cloneTree(true)); VL_DO_DANGLING(nodep->deleteTree(), nodep); return; - } - else if (exprvarrefp) { - nodep->varp( exprvarrefp->varp() ); - } - else { + } else if (exprvarrefp) { + nodep->varp(exprvarrefp->varp()); + } else { nodep->v3fatalSrc("Null connection?"); } } @@ -429,7 +422,7 @@ private: } // If foo.bar, and foo is an interface, then need to search again for foo string::size_type pos = tryname.rfind('.'); - if (pos == string::npos || pos==0) { + if (pos == string::npos || pos == 0) { break; } else { tryname = tryname.substr(0, pos); @@ -444,12 +437,12 @@ private: if (m_renamedInterfaces.count(nodep->dotted())) { nodep->dotted(m_cellp->name() + "__DOT__" + nodep->dotted()); } - UINFO(8," "<scopeAttrp(); if (afterp) afterp->unlinkFrBackWithNext(); - nodep->scopeAttrp(new AstText(nodep->fileline(), string("__DOT__")+m_cellp->name())); + nodep->scopeAttrp(new AstText(nodep->fileline(), string("__DOT__") + m_cellp->name())); if (afterp) nodep->scopeAttrp(afterp); afterp = nodep->scopeEntrp(); if (afterp) afterp->unlinkFrBackWithNext(); - nodep->scopeEntrp(new AstText(nodep->fileline(), string("__DOT__")+m_cellp->name())); + nodep->scopeEntrp(new AstText(nodep->fileline(), string("__DOT__") + m_cellp->name())); if (afterp) nodep->scopeEntrp(afterp); iterateChildren(nodep); } @@ -470,9 +463,7 @@ private: nodep->hier(VString::dot(m_cellp->prettyName(), ".", nodep->hier())); iterateChildren(nodep); } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -494,21 +485,21 @@ private: // AstIfaceRefDType::user5p() // Whether the cell pointed to by this // // AstIfaceRefDType has been inlined // Input: - // AstNodeModule::user1p() // bool. True to inline this module (from InlineMarkVisitor) + // AstNodeModule::user1p() // bool. True to inline this module (from InlineMarkVisitor) // Cleared each cell // AstVar::user2p() // AstVarRef*/AstConst* Points to signal this // // is a direct connect to // AstVar::user3() // bool Don't alias the user2, keep it as signal // AstCell::user4 // AstCell* of the created clone - AstUser2InUse m_inuser2; - AstUser3InUse m_inuser3; - AstUser4InUse m_inuser4; - AstUser5InUse m_inuser5; + AstUser2InUse m_inuser2; + AstUser3InUse m_inuser3; + AstUser4InUse m_inuser4; + AstUser5InUse m_inuser5; // STATE - AstNodeModule* m_modp; // Current module - VDouble0 m_statCells; // Statistic tracking + AstNodeModule* m_modp; // Current module + VDouble0 m_statCells; // Statistic tracking // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -536,36 +527,36 @@ private: } virtual void visit(AstCell* nodep) VL_OVERRIDE { if (nodep->modp()->user1()) { // Marked with inline request - UINFO(5," Inline CELL "<pinsp(); pinp; pinp=VN_CAST(pinp->nextp(), Pin)) { + for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_CAST(pinp->nextp(), Pin)) { if (!pinp->exprp()) continue; V3Inst::pinReconnectSimple(pinp, nodep, false); } // Clone original module - if (debug()>=9) { nodep->dumpTree(cout, "inlcell:"); } - //if (debug()>=9) { nodep->modp()->dumpTree(cout,"oldmod:"); } + if (debug() >= 9) { nodep->dumpTree(cout, "inlcell:"); } + // if (debug()>=9) { nodep->modp()->dumpTree(cout,"oldmod:"); } AstNodeModule* newmodp = nodep->modp()->cloneTree(false); - if (debug()>=9) { newmodp->dumpTree(cout, "newmod:"); } + if (debug() >= 9) { newmodp->dumpTree(cout, "newmod:"); } // Clear var markings and find cell cross references AstNode::user2ClearTree(); AstNode::user4ClearTree(); { InlineCollectVisitor(nodep->modp()); } // {} to destroy visitor immediately // Create data for dotted variable resolution - AstCellInline* inlinep = new AstCellInline(nodep->fileline(), - nodep->name(), nodep->modp()->origName()); + AstCellInline* inlinep + = new AstCellInline(nodep->fileline(), nodep->name(), nodep->modp()->origName()); m_modp->addInlinesp(inlinep); // Must be parsed before any AstCells // Create assignments to the pins - for (AstPin* pinp = nodep->pinsp(); pinp; pinp=VN_CAST(pinp->nextp(), Pin)) { + for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_CAST(pinp->nextp(), Pin)) { if (!pinp->exprp()) continue; - UINFO(6," Pin change from "<modVarp()<modVarp() << endl); // Make new signal; even though we'll optimize the interconnect, we // need an alias to trace correctly. If tracing is disabled, we'll // delete it in later optimizations. @@ -587,20 +578,20 @@ private: // One to one interconnect won't make a temporary variable. // This prevents creating a lot of extra wires for clock signals. // It will become a tracing alias. - UINFO(6,"One-to-one "<user2p(connectRefp); // Public output inside the cell must go via an assign rather // than alias. Else the public logic will set the alias, losing // the value to be propagated up (InOnly isn't a problem as the // AssignAlias will create the assignment for us) pinNewVarp->user3(pinNewVarp->isSigUserRWPublic() - && pinNewVarp->direction()==VDirection::OUTPUT); + && pinNewVarp->direction() == VDirection::OUTPUT); } // Cleanup var names, etc, to not conflict { InlineRelinkVisitor(newmodp, m_modp, nodep); } // Move statements to top module - if (debug()>=9) { newmodp->dumpTree(cout, "fixmod:"); } + if (debug() >= 9) { newmodp->dumpTree(cout, "fixmod:"); } AstNode* stmtsp = newmodp->stmtsp(); if (stmtsp) stmtsp->unlinkFrBackWithNext(); if (stmtsp) m_modp->addStmtp(stmtsp); @@ -608,16 +599,14 @@ private: VL_DO_DANGLING(newmodp->deleteTree(), newmodp); // Clear any leftover ports, etc nodep->unlinkFrBack(); VL_DO_DANGLING(pushDeletep(nodep), nodep); - if (debug()>=9) { m_modp->dumpTree(cout, "donemod:"); } + if (debug() >= 9) { m_modp->dumpTree(cout, "donemod:"); } } } //-------------------- - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE {} // Accelerate - virtual void visit(AstNodeStmt* nodep) VL_OVERRIDE {} // Accelerate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNodeStmt*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -646,16 +635,10 @@ private: VL_DEBUG_FUNC; // Declare debug() // VISITORS - virtual void visit(AstNetlist* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } - + virtual void visit(AstNetlist* nodep) VL_OVERRIDE { iterateChildren(nodep); } virtual void visit(AstModule* nodep) VL_OVERRIDE { - if (nodep->isTop()) { - iterateChildren(nodep); - } + if (nodep->isTop()) { iterateChildren(nodep); } } - virtual void visit(AstCell* nodep) VL_OVERRIDE { string oldScope = m_scope; if (m_scope.empty()) { @@ -666,7 +649,7 @@ private: if (AstModule* modp = VN_CAST(nodep->modp(), Module)) { // Pass Cell pointers down to the next module - for (AstPin* pinp = nodep->pinsp(); pinp; pinp=VN_CAST(pinp->nextp(), Pin)) { + for (AstPin* pinp = nodep->pinsp(); pinp; pinp = VN_CAST(pinp->nextp(), Pin)) { AstVar* varp = pinp->modVarp(); AstVarRef* varrefp = VN_CAST(pinp->exprp(), VarRef); if (!varrefp) continue; @@ -691,7 +674,6 @@ private: m_scope = oldScope; } - virtual void visit(AstAssignVarScope* nodep) VL_OVERRIDE { // Reference AstVarRef* reflp = VN_CAST(nodep->lhsp(), VarRef); @@ -716,49 +698,37 @@ private: alias += varlp->name(); cellp->addIntfRefp(new AstIntfRef(varlp->fileline(), alias)); } - //-------------------- virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate virtual void visit(AstNodeStmt*) VL_OVERRIDE {} // Accelerate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS - explicit InlineIntfRefVisitor(AstNode* nodep) { - iterate(nodep); - } - virtual ~InlineIntfRefVisitor() { - } + explicit InlineIntfRefVisitor(AstNode* nodep) { iterate(nodep); } + virtual ~InlineIntfRefVisitor() {} }; //###################################################################### // Inline class functions void V3Inline::inlineAll(AstNetlist* nodep) { - UINFO(2,__FUNCTION__<<": "<modulesp(); modp; modp=nextmodp) { + for (AstNodeModule* modp = v3Global.rootp()->modulesp(); modp; modp = nextmodp) { nextmodp = VN_CAST(modp->nextp(), NodeModule); if (modp->user1()) { // Was inlined VL_DO_DANGLING(modp->unlinkFrBack()->deleteTree(), modp); } } - { - InlineIntfRefVisitor crvisitor (nodep); - } + { InlineIntfRefVisitor crvisitor(nodep); } V3Global::dumpCheckGlobalTree("inline", 0, v3Global.opt.dumpTreeLevel(__FILE__) >= 3); } diff --git a/src/V3Inline.h b/src/V3Inline.h index 2258c39f0..a45cfbe1a 100644 --- a/src/V3Inline.h +++ b/src/V3Inline.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index e12aa53a7..e3895e611 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Inst's Transformations: @@ -129,10 +125,8 @@ private: virtual void visit(AstAlways*) VL_OVERRIDE {} //-------------------- - // Default: Just iterate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit InstVisitor(AstNetlist* nodep) { @@ -162,12 +156,9 @@ private: } iterateChildren(nodep); } - // Save some time - virtual void visit(AstNodeMath*) VL_OVERRIDE {} - // Default: Just iterate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // METHODS void insert(AstVar* nodep) { @@ -446,13 +437,10 @@ private: } } - // Save some time - virtual void visit(AstNodeMath*) VL_OVERRIDE {} //-------------------- - // Default: Just iterate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit InstDeVisitor(AstNetlist* nodep) { diff --git a/src/V3Inst.h b/src/V3Inst.h index 38858b072..3617180e9 100644 --- a/src/V3Inst.h +++ b/src/V3Inst.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3InstrCount.cpp b/src/V3InstrCount.cpp index 94c54c3d7..5c2e46edb 100644 --- a/src/V3InstrCount.cpp +++ b/src/V3InstrCount.cpp @@ -7,15 +7,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3InstrCount.h b/src/V3InstrCount.h index 47ffed11a..8f3bcf1b8 100644 --- a/src/V3InstrCount.h +++ b/src/V3InstrCount.h @@ -7,15 +7,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LangCode.h b/src/V3LangCode.h index c66d4b76d..59861dafa 100644 --- a/src/V3LangCode.h +++ b/src/V3LangCode.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LanguageWords.h b/src/V3LanguageWords.h index 2319ecfe8..17416dab4 100644 --- a/src/V3LanguageWords.h +++ b/src/V3LanguageWords.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -46,7 +42,7 @@ class V3LanguageWords { static const_iterator begin() { return s().s_kwdMap.begin(); } static const_iterator end() { return s().s_kwdMap.end(); } static string isKeyword(const string& kwd) { - KeywordMap::iterator it = s().s_kwdMap.find(kwd); + KeywordMap::const_iterator it = s().s_kwdMap.find(kwd); if (it == s().s_kwdMap.end()) return ""; return it->second; } diff --git a/src/V3Life.cpp b/src/V3Life.cpp index e02164178..08f674015 100644 --- a/src/V3Life.cpp +++ b/src/V3Life.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // LIFE TRANSFORMATIONS: @@ -438,9 +434,7 @@ private: } virtual void visit(AstVar*) VL_OVERRIDE {} // Don't want varrefs under it - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -493,9 +487,8 @@ private: virtual void visit(AstVar*) VL_OVERRIDE {} // Accelerate virtual void visit(AstNodeStmt*) VL_OVERRIDE {} // Accelerate virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS LifeTopVisitor(AstNetlist* nodep, LifeState* statep) { diff --git a/src/V3Life.h b/src/V3Life.h index 24823ee83..44a44f020 100644 --- a/src/V3Life.h +++ b/src/V3Life.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LifePost.cpp b/src/V3LifePost.cpp index 96c6bb8a6..b50adc9e2 100644 --- a/src/V3LifePost.cpp +++ b/src/V3LifePost.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // LIFE TRANSFORMATIONS: @@ -91,9 +87,8 @@ private: iterateChildren(nodep); } virtual void visit(AstVar*) VL_OVERRIDE {} // Don't want varrefs under it - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit LifePostElimVisitor(AstTopScope* nodep) @@ -346,9 +341,8 @@ private: } //----- virtual void visit(AstVar*) VL_OVERRIDE {} // Don't want varrefs under it - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit LifePostDlyVisitor(AstNetlist* nodep) diff --git a/src/V3LifePost.h b/src/V3LifePost.h index 4a04e4213..1aa9fae02 100644 --- a/src/V3LifePost.h +++ b/src/V3LifePost.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkCells.cpp b/src/V3LinkCells.cpp index 8e4ea4b29..009b3f005 100644 --- a/src/V3LinkCells.cpp +++ b/src/V3LinkCells.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // NO EDITS: Don't replace or delete nodes, as the parser symbol table @@ -450,11 +446,8 @@ private: // Accelerate the recursion // Must do statements to support Generates, math though... - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE {} - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } // METHODS void readModNames() { diff --git a/src/V3LinkCells.h b/src/V3LinkCells.h index 42738fe65..b79b94a01 100644 --- a/src/V3LinkCells.h +++ b/src/V3LinkCells.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index ccc9aa8d3..70ea00511 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // LinkDot TRANSFORMATIONS: @@ -505,7 +501,7 @@ public: it!=m_scopeAliasMap[samn].end(); ++it) { VSymEnt* lhsp = it->first; VSymEnt* srcp = lhsp; - while (1) { // Follow chain of aliases up to highest level non-alias + while (true) { // Follow chain of aliases up to highest level non-alias ScopeAliasMap::iterator it2 = m_scopeAliasMap[samn].find(srcp); if (it2 != m_scopeAliasMap[samn].end()) { srcp = it2->second; continue; } else break; @@ -757,7 +753,7 @@ class LinkDotFindVisitor : public AstNVisitor { m_curSymp = m_modSymp = NULL; } } - virtual void visit(AstTypeTable* nodep) VL_OVERRIDE {} + virtual void visit(AstTypeTable*) VL_OVERRIDE {} virtual void visit(AstNodeModule* nodep) VL_OVERRIDE { // Called on top module from Netlist, other modules from the cell creating them, // and packages @@ -1093,6 +1089,12 @@ class LinkDotFindVisitor : public AstNVisitor { iterateChildren(nodep); m_statep->insertSym(m_curSymp, nodep->name(), nodep, m_packagep); } + virtual void visit(AstTypedefFwd* nodep) VL_OVERRIDE { + UASSERT_OBJ(m_curSymp, nodep, "Typedef not under module/package/$unit"); + iterateChildren(nodep); + // No need to insert, only the real typedef matters, but need to track for errors + nodep->user1p(m_curSymp); + } virtual void visit(AstParamTypeDType* nodep) VL_OVERRIDE { UASSERT_OBJ(m_curSymp, nodep, "Parameter type not under module/package/$unit"); iterateChildren(nodep); @@ -1178,10 +1180,7 @@ class LinkDotFindVisitor : public AstNVisitor { // No longer needed, but can't delete until any multi-instantiated modules are expanded } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -1242,7 +1241,7 @@ private: } // VISITs - virtual void visit(AstTypeTable* nodep) VL_OVERRIDE {} + virtual void visit(AstTypeTable*) VL_OVERRIDE {} virtual void visit(AstNodeModule* nodep) VL_OVERRIDE { UINFO(5," "<dead() || !nodep->user4()) { @@ -1343,11 +1342,22 @@ private: // We're done with implicit gates VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); + virtual void visit(AstTypedefFwd* nodep) VL_OVERRIDE { + VSymEnt* foundp = m_statep->getNodeSym(nodep)->findIdFallback(nodep->name()); + if (!foundp && v3Global.opt.pedantic()) { + // We only check it was ever really defined in pedantic mode, as it + // might have been in a header file referring to a module we never + // needed so there are false positives + nodep->v3error( + "Forward typedef unused or does not resolve to a data type (IEEE 1800-2017 6.18): " + << nodep->prettyNameQ()); + } + // We only needed the forward declaration in order to parse correctly. + VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS LinkDotParamVisitor(AstNetlist* rootp, LinkDotState* statep) { @@ -1493,10 +1503,7 @@ class LinkDotScopeVisitor : public AstNVisitor { virtual void visit(AstCell*) VL_OVERRIDE {} virtual void visit(AstVar*) VL_OVERRIDE {} virtual void visit(AstNodeMath*) VL_OVERRIDE {} - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -1581,10 +1588,7 @@ class LinkDotIfaceVisitor : public AstNVisitor { nodep->unlinkFrBack(); VL_DO_DANGLING(pushDeletep(nodep), nodep); } } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -1762,7 +1766,7 @@ private: // Recurse..., backward as must do packages before using packages iterateChildrenBackwards(nodep); } - virtual void visit(AstTypeTable* nodep) VL_OVERRIDE {} + virtual void visit(AstTypeTable*) VL_OVERRIDE {} virtual void visit(AstNodeModule* nodep) VL_OVERRIDE { if (nodep->dead()) return; checkNoDot(nodep); @@ -2563,10 +2567,10 @@ private: } virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate checkNoDot(nodep); iterateChildren(nodep); } + public: // CONSTRUCTORS LinkDotResolveVisitor(AstNetlist* rootp, LinkDotState* statep) { diff --git a/src/V3LinkDot.h b/src/V3LinkDot.h index 3a2721d41..2df4ac3b9 100644 --- a/src/V3LinkDot.h +++ b/src/V3LinkDot.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp index 6420415aa..50244c0b5 100644 --- a/src/V3LinkJump.cpp +++ b/src/V3LinkJump.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3LinkJump's Transformations: @@ -247,11 +243,9 @@ private: virtual void visit(AstVarRef* nodep) VL_OVERRIDE { if (m_loopInc && nodep->varp()) nodep->varp()->usedLoopIdx(true); } + virtual void visit(AstConst*) VL_OVERRIDE {} + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } - virtual void visit(AstConst* nodep) VL_OVERRIDE {} - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } public: // CONSTRUCTORS explicit LinkJumpVisitor(AstNetlist* nodep) { diff --git a/src/V3LinkJump.h b/src/V3LinkJump.h index fe923aff3..fba121e9c 100644 --- a/src/V3LinkJump.h +++ b/src/V3LinkJump.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkLValue.cpp b/src/V3LinkLValue.cpp index e8f178ac8..c4318b8cb 100644 --- a/src/V3LinkLValue.cpp +++ b/src/V3LinkLValue.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // LinkLValue TRANSFORMATIONS: @@ -270,10 +266,7 @@ private: } } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3LinkLValue.h b/src/V3LinkLValue.h index d2d62bdb1..101e06514 100644 --- a/src/V3LinkLValue.h +++ b/src/V3LinkLValue.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index abdfa423a..e51172c6e 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // LINKTOP TRANSFORMATIONS: @@ -55,11 +51,9 @@ void V3LinkLevel::modSortByLevel() { ModVec mods; // Modules ModVec tops; // Top level modules - for (AstNodeModule* nodep = v3Global.rootp()->modulesp(); - nodep; nodep=VN_CAST(nodep->nextp(), NodeModule)) { - if (nodep->level()<=2) { - tops.push_back(nodep); - } + for (AstNodeModule* nodep = v3Global.rootp()->modulesp(); nodep; + nodep = VN_CAST(nodep->nextp(), NodeModule)) { + if (nodep->level() <= 2) tops.push_back(nodep); mods.push_back(nodep); } if (tops.size() >= 2) { @@ -69,7 +63,7 @@ void V3LinkLevel::modSortByLevel() { <warnMore() <<"... Suggest see manual; fix the duplicates, or use --top-module to select top." <warnMore()<<"... Top module "<prettyNameQ()<warnContextSecondary(); diff --git a/src/V3LinkLevel.h b/src/V3LinkLevel.h index 64b9b3bd8..f17861e6e 100644 --- a/src/V3LinkLevel.h +++ b/src/V3LinkLevel.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -33,6 +29,7 @@ class V3LinkLevel { private: static void wrapTopCell(AstNetlist* rootp); static void wrapTopPackages(AstNetlist* rootp); + public: static void modSortByLevel(); static void wrapTop(AstNetlist* rootp); diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 55c79ddd0..ce6b45d52 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // LinkParse TRANSFORMATIONS: @@ -386,13 +382,6 @@ private: VL_DO_DANGLING(nodep->deleteTree(), nodep); } - virtual void visit(AstTypedefFwd* nodep) VL_OVERRIDE { - // We only needed the forward declaration in order to parse correctly. - // We won't even check it was ever really defined, as it might have been in a header - // file referring to a module we never needed - VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); - } - virtual void visit(AstForeach* nodep) VL_OVERRIDE { // FOREACH(array,loopvars,body) // -> BEGIN(declare vars, loopa=lowest; WHILE(loopa<=highest, ... body)) diff --git a/src/V3LinkParse.h b/src/V3LinkParse.h index 8bf81e799..10425842c 100644 --- a/src/V3LinkParse.h +++ b/src/V3LinkParse.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index 3180646af..44fa612d3 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // LinkResolve TRANSFORMATIONS: @@ -457,10 +453,7 @@ private: iterateChildren(nodep); } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -506,13 +499,9 @@ private: if (nodep->modp()->modPublic()) m_modp->modPublic(true); //** No iteration for speed } - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE { - // Speedup - } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit LinkBotupVisitor(AstNetlist* rootp) { diff --git a/src/V3LinkResolve.h b/src/V3LinkResolve.h index 68dd138c5..f33ff91d7 100644 --- a/src/V3LinkResolve.h +++ b/src/V3LinkResolve.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3List.h b/src/V3List.h index f78d306a7..755fc7426 100644 --- a/src/V3List.h +++ b/src/V3List.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -72,8 +68,8 @@ public: ~V3ListEnt() { #ifdef VL_DEBUG // Load bogus pointers so we can catch deletion bugs - m_nextp = (T)1; - m_prevp = (T)1; + m_nextp = reinterpret_cast(1); + m_prevp = reinterpret_cast(1); #endif } T nextp() const { return m_nextp; } diff --git a/src/V3Localize.cpp b/src/V3Localize.cpp index f5ce6e1d3..25667dc9e 100644 --- a/src/V3Localize.cpp +++ b/src/V3Localize.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // LOCALIZE TRANSFORMATIONS: @@ -84,9 +80,8 @@ private: nodep->hierThis(true); } } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit LocalizeDehierVisitor(AstNetlist* nodep) { @@ -224,9 +219,8 @@ private: } // No iterate; Don't want varrefs under it } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit LocalizeVisitor(AstNetlist* nodep) { diff --git a/src/V3Localize.h b/src/V3Localize.h index 22417e619..8fdf5fe5c 100644 --- a/src/V3Localize.h +++ b/src/V3Localize.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Name.cpp b/src/V3Name.cpp index 1992d1b06..c995fbfb9 100644 --- a/src/V3Name.cpp +++ b/src/V3Name.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Name's Transformations: @@ -134,9 +130,8 @@ private: } //-------------------- - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit NameVisitor(AstNetlist* nodep) { diff --git a/src/V3Name.h b/src/V3Name.h index 6f86ed00c..e998b5eb7 100644 --- a/src/V3Name.h +++ b/src/V3Name.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Number.cpp b/src/V3Number.cpp index b5900bc51..ca092ef53 100644 --- a/src/V3Number.cpp +++ b/src/V3Number.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -1642,7 +1638,7 @@ V3Number& V3Number::opMul(const V3Number& lhs, const V3Number& rhs) { vluint64_t mul = static_cast(lhs.m_value[lword]) * static_cast(rhs.m_value[rword]); for (int qword=lword+rword; qwordwords(); qword++) { - mul += (vluint64_t)(m_value[qword]); + mul += static_cast(m_value[qword]); m_value[qword] = (mul & VL_ULL(0xffffffff)); mul = (mul >> VL_ULL(32)) & VL_ULL(0xffffffff); } @@ -2059,8 +2055,28 @@ V3Number& V3Number::opRToIRoundS(const V3Number& lhs) { NUM_ASSERT_OP_ARGS1(lhs); NUM_ASSERT_DOUBLE_ARGS1(lhs); double v = VL_ROUND(lhs.toDouble()); - vlsint32_t i = static_cast(v); // C converts from double to vlsint32 - return setLongS(i); + setZero(); + union { double d; vluint64_t q; } u; + u.d = v; if (u.d == 0.0) {} + + int exp = static_cast((u.q >> VL_ULL(52)) & VL_MASK_Q(11)) - 1023; + int lsb = exp - 52; + vluint64_t mantissa = (u.q & VL_MASK_Q(52)) | (VL_ULL(1) << 52); + if (v != 0) { + // IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa + // This does not need to support subnormals as they are sub-integral + for (int bit = 0; bit <= 52; ++bit) { + if (mantissa & (VL_ULL(1) << bit)) { + int outbit = bit + lsb; + if (outbit >= 0) setBit(outbit, 1); + } + } + if (v < 0) { + V3Number noSign = *this; + opNegate(noSign); + } + } + return *this; } V3Number& V3Number::opRealToBits(const V3Number& lhs) { NUM_ASSERT_OP_ARGS1(lhs); diff --git a/src/V3Number.h b/src/V3Number.h index a53e886ca..5c1645842 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -26,10 +22,19 @@ #include "V3Error.h" +#include +#include #include //============================================================================ +// Return if two numbers within Epsilon of each other +inline bool v3EpsilonEqual(double a, double b) { + return fabs(a - b) <= (std::numeric_limits::epsilon() * std::max(1.0, std::max(a, b))); +} + +//============================================================================ + class AstNode; class V3Number { diff --git a/src/V3Number_test.cpp b/src/V3Number_test.cpp index e7faf7059..f4a5638e7 100644 --- a/src/V3Number_test.cpp +++ b/src/V3Number_test.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 724fc37e4..ebfc8a94b 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -100,6 +96,24 @@ public: ~V3OptionsImp() {} }; +//###################################################################### +// V3LangCode class functions + +V3LangCode::V3LangCode(const char* textp) { + // Return code for given string, or ERROR, which is a bad code + for (int codei = V3LangCode::L_ERROR; codei < V3LangCode::_ENUM_END; ++codei) { + V3LangCode code = V3LangCode(codei); + if (0 == VL_STRCASECMP(textp, code.ascii())) { + m_e = code; + return; + } + } + m_e = V3LangCode::L_ERROR; +} + +//###################################################################### +// V3Options class functions + void V3Options::addIncDirUser(const string& incdir) { m_impp->addIncDirUser(incdir); } @@ -229,7 +243,7 @@ void V3Options::addArg(const string& arg) { string V3Options::allArgsString() { string out; - for (std::list::iterator it=m_impp->m_allArgs.begin(); + for (std::list::const_iterator it = m_impp->m_allArgs.begin(); it != m_impp->m_allArgs.end(); ++it) { if (out != "") out += " "; out += *it; @@ -237,20 +251,6 @@ string V3Options::allArgsString() { return out; } -//###################################################################### -// V3LangCode class functions - -V3LangCode::V3LangCode(const char* textp) { - // Return code for given string, or ERROR, which is a bad code - for (int codei=V3LangCode::L_ERROR; codei(_e)) {} operator en() const { return m_e; } @@ -180,6 +177,7 @@ class V3Options { bool m_protectIds; // main switch: --protect-ids bool m_public; // main switch: --public bool m_publicFlatRW; // main switch: --public-flat-rw + bool m_quietExit; // main switch: --quiet-exit bool m_relativeCFuncs; // main switch: --relative-cfuncs bool m_relativeIncludes; // main switch: --relative-includes bool m_reportUnoptflat; // main switch: --report-unoptflat @@ -283,7 +281,7 @@ class V3Options { void showVersion(bool verbose); void coverage(bool flag) { m_coverageLine = m_coverageToggle = m_coverageUser = flag; } bool onoff(const char* sw, const char* arg, bool& flag); - bool onoffb(const char* sw, const char* arg, VOptionBool& flag); + bool onoffb(const char* sw, const char* arg, VOptionBool& flagr); bool suffixed(const string& sw, const char* arg); string parseFileArg(const string& optdir, const string& relfilename); bool parseLangExt(const char* swp, const char* langswp, const V3LangCode& lc); @@ -373,6 +371,7 @@ class V3Options { bool lintOnly() const { return m_lintOnly; } bool ignc() const { return m_ignc; } bool inhibitSim() const { return m_inhibitSim; } + bool quietExit() const { return m_quietExit; } bool relativeCFuncs() const { return m_relativeCFuncs; } bool reportUnoptflat() const { return m_reportUnoptflat; } bool vpi() const { return m_vpi; } diff --git a/src/V3Order.cpp b/src/V3Order.cpp index 1644f14c8..65f859012 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Order's Transformations: @@ -366,9 +362,7 @@ private: iterateChildren(nodep); m_inClocked = false; } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -403,15 +397,14 @@ private: } iterateChildren(nodep->rhsp()); } - virtual void visit(AstVarRef* nodep) VL_OVERRIDE { + virtual void visit(AstVarRef*) VL_OVERRIDE { // Previous versions checked attrClocker() here, but this breaks // the updated t_clocker VCD test. // If reenable this visitor note AstNodeMath short circuit below } - virtual void visit(AstNodeMath* nodep) VL_OVERRIDE {} // Accelerate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNodeMath*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit OrderClkAssVisitor(AstNode* nodep) { @@ -1254,10 +1247,8 @@ private: // on the next evaluation loop. } //-------------------- - // Default - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS OrderVisitor() { diff --git a/src/V3Order.h b/src/V3Order.h index 9f7151453..92be224f0 100644 --- a/src/V3Order.h +++ b/src/V3Order.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3OrderGraph.h b/src/V3OrderGraph.h index c4e6280b7..ebd1b5e16 100644 --- a/src/V3OrderGraph.h +++ b/src/V3OrderGraph.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // OrderGraph Class Hierarchy: diff --git a/src/V3Os.cpp b/src/V3Os.cpp index 88f5f8370..06b7ede3d 100644 --- a/src/V3Os.cpp +++ b/src/V3Os.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -47,7 +43,7 @@ #include #if defined(_WIN32) || defined(__MINGW32__) -# include // LONG for bcrypt.h on MINGW +# include // LONG for bcrypt.h on MINGW # include // BCryptGenRandom # include # include // mkdir diff --git a/src/V3Os.h b/src/V3Os.h index 08221cb3f..d1b2b4436 100644 --- a/src/V3Os.h +++ b/src/V3Os.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 9b551167c..9c5a745c0 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // PARAM TRANSFORMATIONS: @@ -549,10 +545,7 @@ private: VL_DO_DANGLING(nodep->deleteTree(), nodep); } - // Default: Just iterate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Param.h b/src/V3Param.h index 817f76f30..a2354de03 100644 --- a/src/V3Param.h +++ b/src/V3Param.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Parse.h b/src/V3Parse.h index 767649185..47bb0206e 100644 --- a/src/V3Parse.h +++ b/src/V3Parse.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -40,6 +36,7 @@ private: // CONSTRUCTORS VL_UNCOPYABLE(V3Parse); + public: // We must allow reading multiple files into one parser V3Parse(AstNetlist* rootp, VInFilter* filterp, V3ParseSym* symp); diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp index b02b727cb..a0426103a 100644 --- a/src/V3ParseGrammar.cpp +++ b/src/V3ParseGrammar.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ParseImp.cpp b/src/V3ParseImp.cpp index 969f22a5f..ca502f9b3 100644 --- a/src/V3ParseImp.cpp +++ b/src/V3ParseImp.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // Overview of files involved in parsing diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index 3b4225014..f6560326e 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2009-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2009-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ParseLex.cpp b/src/V3ParseLex.cpp index 019e87fdb..c59a7283e 100644 --- a/src/V3ParseLex.cpp +++ b/src/V3ParseLex.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ParseSym.h b/src/V3ParseSym.h index 3a820b145..fda4f4411 100644 --- a/src/V3ParseSym.h +++ b/src/V3ParseSym.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2009-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2009-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index b8ae1f469..04a063f31 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -730,7 +726,7 @@ public: lit != mtaskp->vertexListp()->end(); ++lit) { const OrderLogicVertex* logicp = (*lit)->logicp(); if (!logicp) continue; - if (0) { + if (false) { // Show nodes only *osp<<"> "; logicp->nodep()->dumpTree(*osp); } else { @@ -1195,7 +1191,7 @@ public: doRescore(); // Set initial scores in scoreboard - while (1) { + while (true) { // This is the best edge to merge, with the lowest // score (shortest local critical path) MergeCandidate* mergeCanp = const_cast(m_sb.bestp()); @@ -1783,9 +1779,7 @@ private: m_tracingCall = true; iterate(nodep->funcp()); } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Partition.h b/src/V3Partition.h index dfa737b0b..b5a78a756 100644 --- a/src/V3Partition.h +++ b/src/V3Partition.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -88,10 +84,8 @@ public: PartPtrIdMap() : m_nextId(0) {} // METHODS vluint64_t findId(const void* ptrp) const { - PtrMap::iterator it = m_id.find(ptrp); - if (it != m_id.end()) { - return it->second; - } + PtrMap::const_iterator it = m_id.find(ptrp); + if (it != m_id.end()) return it->second; m_id[ptrp] = m_nextId; return m_nextId++; } diff --git a/src/V3PartitionGraph.h b/src/V3PartitionGraph.h index 97450e5a9..6aeb6e411 100644 --- a/src/V3PartitionGraph.h +++ b/src/V3PartitionGraph.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PreLex.h b/src/V3PreLex.h index 3b7de5b61..6e51c46a5 100644 --- a/src/V3PreLex.h +++ b/src/V3PreLex.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2000-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the -// GNU Lesser General Public License Version 3 or the Perl Artistic License +// Copyright 2000-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // This header provides the interface between the lex proper V3PreLex.l/.cpp @@ -198,8 +194,13 @@ class V3PreLex { void curFilelinep(FileLine* fl) { curStreamp()->m_curFilelinep = fl; } void appendDefValue(const char* textp, size_t len) { m_defValue.append(textp, len); } void lineDirective(const char* textp); - void linenoInc() { if (curStreamp()->m_ignNewlines) curStreamp()->m_ignNewlines--; - else curFilelinep()->linenoInc(); } + void linenoInc() { + if (curStreamp()->m_ignNewlines) { + curStreamp()->m_ignNewlines--; + } else { + curFilelinep()->linenoInc(); + } + } void warnBackslashSpace(); // Called by V3PreProc.cpp to inform lexer void pushStateDefArg(int level); diff --git a/src/V3PreLex.l b/src/V3PreLex.l index 851f1e7d7..c75bf8844 100644 --- a/src/V3PreLex.l +++ b/src/V3PreLex.l @@ -10,15 +10,11 @@ * ************************************************************************** * - * Copyright 2003-2020 by Wilson Snyder. This program is free software; - * you can redistribute it and/or modify it under the terms of either the + * Copyright 2003-2020 by Wilson Snyder. This program is free software; you + * can redistribute it and/or modify it under the terms of either the * GNU Lesser General Public License Version 3 or the Perl Artistic License * Version 2.0. - * - * Verilator is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 * ************************************************************************** * Do not use Flex in C++ mode. It has bugs with yyunput() which result in diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index 102ca4cef..3328363e4 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2000-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the -// GNU Lesser General Public License Version 3 or the Perl Artistic License +// Copyright 2000-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -865,7 +861,7 @@ void V3PreProcImp::candidateDefines(VSpellCheck* spellerp) { int V3PreProcImp::getRawToken() { // Get a token from the file, whatever it may be. - while (1) { + while (true) { next_tok: if (m_lineAdd) { m_lineAdd--; @@ -946,7 +942,7 @@ void V3PreProcImp::debugToken(int tok, const char* cmtp) { int V3PreProcImp::getStateToken() { // Return the next state-determined token - while (1) { + while (true) { next_tok: if (isEof()) return VP_EOF; int tok = getRawToken(); diff --git a/src/V3PreProc.h b/src/V3PreProc.h index 9e09dfe93..ae03e7d16 100644 --- a/src/V3PreProc.h +++ b/src/V3PreProc.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2000-2020 by Wilson Snyder. This program is free software; -// you can redistribute it and/or modify it under the terms of either the -// GNU Lesser General Public License Version 3 or the Perl Artistic License +// Copyright 2000-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// This program is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PreShell.cpp b/src/V3PreShell.cpp index 54acd7acc..c0c7fd05c 100644 --- a/src/V3PreShell.cpp +++ b/src/V3PreShell.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3PreShell.h b/src/V3PreShell.h index 332083844..ec8a7678a 100644 --- a/src/V3PreShell.h +++ b/src/V3PreShell.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp index 50d1b010c..ec613e954 100644 --- a/src/V3Premit.cpp +++ b/src/V3Premit.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Premit's Transformations: @@ -73,9 +69,7 @@ private: } } } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS @@ -363,7 +357,8 @@ private: checkNode(nodep); } virtual void visit(AstConst* nodep) VL_OVERRIDE { - iterateChildren(nodep); checkNode(nodep); + iterateChildren(nodep); + checkNode(nodep); } virtual void visit(AstNodeCond* nodep) VL_OVERRIDE { iterateChildren(nodep); @@ -411,10 +406,8 @@ private: //-------------------- // Default: Just iterate - virtual void visit(AstVar* nodep) VL_OVERRIDE {} // Don't hit varrefs under vars - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstVar*) VL_OVERRIDE {} // Don't hit varrefs under vars + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Premit.h b/src/V3Premit.h index cd9c44052..b7a5e302d 100644 --- a/src/V3Premit.h +++ b/src/V3Premit.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp index 6e64d7563..ecb49ff4b 100644 --- a/src/V3ProtectLib.cpp +++ b/src/V3ProtectLib.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2019 by Todd Strader. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -367,7 +363,7 @@ class ProtectVisitor : public AstNVisitor { } } - virtual void visit(AstNode* nodep) VL_OVERRIDE { } + virtual void visit(AstNode*) VL_OVERRIDE {} string cInputConnection(AstVar* varp) { string frstmt; diff --git a/src/V3ProtectLib.h b/src/V3ProtectLib.h index 8ffaac46e..879305054 100644 --- a/src/V3ProtectLib.h +++ b/src/V3ProtectLib.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2019 by Todd Strader. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp index 602299d03..0654a7dae 100644 --- a/src/V3Reloop.cpp +++ b/src/V3Reloop.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Reloop's Transformations: @@ -226,12 +222,9 @@ private: UINFO(9, "Start merge i="<initsp()); - while (1) { + while (true) { UINFO(5, " FOR-ITER "<condp()); if (!optimizable()) break; @@ -884,7 +880,7 @@ private: iterateChildren(nodep); } else if (optimizable()) { int loops = 0; - while (1) { + while (true) { UINFO(5, " WHILE-ITER "<precondsp()); if (jumpingOver(nodep)) break; diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp index 7e7feddf6..87fab6817 100644 --- a/src/V3Slice.cpp +++ b/src/V3Slice.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // Slice TRANSFORMATIONS: @@ -229,10 +225,7 @@ class SliceVisitor : public AstNVisitor { expandBiOp(nodep); } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - // Default: Just iterate - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Slice.h b/src/V3Slice.h index 5ceaf2ceb..1ac23ac24 100644 --- a/src/V3Slice.h +++ b/src/V3Slice.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Split.cpp b/src/V3Split.cpp index f7eedfee3..cbfba4dee 100644 --- a/src/V3Split.cpp +++ b/src/V3Split.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Split implements two separate transformations: @@ -829,12 +825,11 @@ public: } } virtual ~RemovePlaceholdersVisitor() {} - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } virtual void visit(AstSplitPlaceholder* nodep) VL_OVERRIDE { m_removeSet.insert(nodep); } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + private: VL_UNCOPYABLE(RemovePlaceholdersVisitor); }; diff --git a/src/V3Split.h b/src/V3Split.h index 066d062b5..a60268cee 100644 --- a/src/V3Split.h +++ b/src/V3Split.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3SplitAs.cpp b/src/V3SplitAs.cpp index bc37cb0fa..0a4b76736 100644 --- a/src/V3SplitAs.cpp +++ b/src/V3SplitAs.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3SplitAs's Transformations: @@ -61,9 +57,8 @@ private: m_splitVscp = nodep->varScopep(); } } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit SplitAsFindVisitor(AstAlways* nodep) { @@ -121,9 +116,8 @@ private: m_keepStmt = oldKeep || m_keepStmt; UINFO(9," upKeep="< m_refs; - virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } virtual void visit(AstNodeModule* nodep) VL_OVERRIDE { UASSERT_OBJ(m_modp == NULL, m_modp, "Nested module declration"); if (!VN_IS(nodep, Module)) { @@ -1067,6 +1062,8 @@ class SplitPackedVarVisitor : public AstNVisitor, public SplitVarImpl { iterateChildren(nodep); } } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + // Extract necessary bit range from a newly created variable to meet ref static AstNode* extractBits(const PackedVarRefEntry& ref, const SplitNewVar& var, bool lvalue) { diff --git a/src/V3SplitVar.h b/src/V3SplitVar.h index 61a9e8db2..f9c1c64ab 100644 --- a/src/V3SplitVar.h +++ b/src/V3SplitVar.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Stats.cpp b/src/V3Stats.cpp index 6fd76e710..819b1236c 100644 --- a/src/V3Stats.cpp +++ b/src/V3Stats.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Stats.h b/src/V3Stats.h index 5bf2f7626..23f6c90ec 100644 --- a/src/V3Stats.h +++ b/src/V3Stats.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp index a40fd5727..3f28b025b 100644 --- a/src/V3StatsReport.cpp +++ b/src/V3StatsReport.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2005-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2005-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -140,12 +136,12 @@ class StatsReport { // Header os<<" Stat "<second; if (lastName != repp->name()) { lastName = repp->name(); diff --git a/src/V3String.cpp b/src/V3String.cpp index ea6a9ed2b..63f3f1f1b 100644 --- a/src/V3String.cpp +++ b/src/V3String.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -79,7 +75,7 @@ bool VString::wildmatch(const string& s, const string& p) { } bool VString::isWildcard(const string &p) { - return ((p.find("*") != string::npos) || (p.find("?") != string::npos)); + return ((p.find('*') != string::npos) || (p.find('?') != string::npos)); } string VString::dot(const string& a, const string& dot, const string& b) { @@ -148,8 +144,8 @@ static inline uint32_t shaRotr32(uint32_t lhs, uint32_t rhs) { return lhs >> rhs | lhs << (32 - rhs); } -static inline void sha256Block(uint32_t* h, uint32_t* chunk) VL_ATTR_ALWINLINE; -static inline void sha256Block(uint32_t* h, uint32_t* chunk) { +static inline void sha256Block(uint32_t* h, const uint32_t* chunk) VL_ATTR_ALWINLINE; +static inline void sha256Block(uint32_t* h, const uint32_t* chunk) { uint32_t ah[8]; const uint32_t* p = chunk; @@ -420,7 +416,7 @@ VSpellCheck::EditDistance VSpellCheck::cutoffDistance(size_t goal_len, size_t ca size_t max_length = std::max(goal_len, candidate_len); size_t min_length = std::min(goal_len, candidate_len); if (max_length <= 1) return 0; - if (max_length - min_length <= 1) return std::max(max_length / 3, (size_t)1); + if (max_length - min_length <= 1) return std::max(max_length / 3, static_cast(1)); return (max_length + 2) / 3; } diff --git a/src/V3String.h b/src/V3String.h index 889038777..d986bc04b 100644 --- a/src/V3String.h +++ b/src/V3String.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Subst.cpp b/src/V3Subst.cpp index a63bd64d5..6c4eee97b 100644 --- a/src/V3Subst.cpp +++ b/src/V3Subst.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2004-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2004-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Subst's Transformations: @@ -206,10 +202,9 @@ private: } } } - virtual void visit(AstConst* nodep) VL_OVERRIDE {} // Accelerate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstConst*) VL_OVERRIDE {} // Accelerate + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS SubstUseVisitor(AstNode* nodep, int origStep) { @@ -366,8 +361,8 @@ private: } } } - virtual void visit(AstVar* nodep) VL_OVERRIDE {} - virtual void visit(AstConst* nodep) VL_OVERRIDE {} + virtual void visit(AstVar*) VL_OVERRIDE {} + virtual void visit(AstConst*) VL_OVERRIDE {} virtual void visit(AstNode* nodep) VL_OVERRIDE { m_ops++; if (!nodep->isSubstOptimizable()) { diff --git a/src/V3Subst.h b/src/V3Subst.h index 573e65ccd..fbc3e5708 100644 --- a/src/V3Subst.h +++ b/src/V3Subst.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3SymTable.h b/src/V3SymTable.h index b0a504caa..58573d406 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index 8a9d2751b..2bf83be6c 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -11,14 +11,11 @@ // //************************************************************************* // -// This program is free software; you can redistribute it and/or modify -// it under the terms of either the GNU Lesser General Public License -// Version 3 or the Perl Artistic License Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -689,7 +686,7 @@ void V3TSP::selfTestString() { expect.push_back("3"); if (VL_UNCOVERABLE(expect != result)) { - for (std::vector::iterator it = result.begin(); it != result.end(); ++it) { + for (std::vector::const_iterator it = result.begin(); it != result.end(); ++it) { cout<<*it<<" "; } cout< m_flags; // Used/Driven on each subbit + AstVar* m_varp; // Variable this tracks + std::vector m_wholeFlags; // Used/Driven on whole vector + std::vector m_bitFlags; // Used/Driven on each subbit enum { FLAG_USED = 0, FLAG_DRIVEN = 1, FLAGS_PER_BIT = 2 }; @@ -58,31 +53,35 @@ public: explicit UndrivenVarEntry(AstVar* varp) { // Construction for when a var is used UINFO(9, "create "<width()*FLAGS_PER_BIT); - for (int i=0; iwidth()*FLAGS_PER_BIT; i++) { - m_flags[i] = false; + m_wholeFlags.resize(FLAGS_PER_BIT); + for (int i = 0; i < FLAGS_PER_BIT; i++) { + m_wholeFlags[i] = false; + } + m_bitFlags.resize(varp->width() * FLAGS_PER_BIT); + for (int i = 0; i < varp->width() * FLAGS_PER_BIT; i++) { + m_bitFlags[i] = false; } } ~UndrivenVarEntry() {} private: // METHODS - inline bool bitNumOk(int bit) const { return bit>=0 - && (bit*FLAGS_PER_BIT < static_cast(m_flags.size())); } - inline bool usedFlag(int bit) const { - return m_usedWhole || m_flags[bit*FLAGS_PER_BIT + FLAG_USED]; } - inline bool drivenFlag(int bit) const { - return m_drivenWhole || m_flags[bit*FLAGS_PER_BIT + FLAG_DRIVEN]; } + bool bitNumOk(int bit) const { + return bit >= 0 && (bit * FLAGS_PER_BIT < static_cast(m_bitFlags.size())); + } + bool usedFlag(int bit) const { + return m_wholeFlags[FLAG_USED] || m_bitFlags[bit * FLAGS_PER_BIT + FLAG_USED]; + } + bool drivenFlag(int bit) const { + return m_wholeFlags[FLAG_DRIVEN] || m_bitFlags[bit * FLAGS_PER_BIT + FLAG_DRIVEN]; + } enum BitNamesWhich { BN_UNUSED, BN_UNDRIVEN, BN_BOTH }; string bitNames(BitNamesWhich which) { string bits; bool prev = false; int msb = 0; // bit==-1 loops below; we do one extra iteration so end with prev=false - for (int bit=(m_flags.size()/FLAGS_PER_BIT)-1; bit >= -1; --bit) { + for (int bit=(m_bitFlags.size()/FLAGS_PER_BIT)-1; bit >= -1; --bit) { if (bit>=0 && ((which == BN_UNUSED && !usedFlag(bit) && drivenFlag(bit)) || (which == BN_UNDRIVEN && usedFlag(bit) && !drivenFlag(bit)) @@ -109,38 +108,39 @@ private: public: void usedWhole() { UINFO(9, "set u[*] "<name()<name()<name()<name()<isParam() && !nodep->isGenVar()) { bool allU = true; bool allD = true; - bool anyU = m_usedWhole; - bool anyD = m_drivenWhole; + bool anyU = m_wholeFlags[FLAG_USED]; + bool anyD = m_wholeFlags[FLAG_DRIVEN]; bool anyUnotD = false; bool anyDnotU = false; bool anynotDU = false; - for (unsigned bit=0; bitisIfaceRef()) { // For interface top level we don't do any tracking @@ -229,18 +229,18 @@ private: // NODE STATE // Netlist: // AstVar::user1p -> UndrivenVar* for usage var, 0=not set yet - AstUser1InUse m_inuser1; + AstUser1InUse m_inuser1; // Each always: // AstNode::user2p -> UndrivenVar* for usage var, 0=not set yet - AstUser2InUse m_inuser2; + AstUser2InUse m_inuser2; // STATE std::vector m_entryps[3]; // Nodes to delete when we are finished - bool m_inBBox; // In black box; mark as driven+used - bool m_inContAssign; // In continuous assignment - bool m_inProcAssign; // In procedural assignment - AstNodeFTask* m_taskp; // Current task - AstAlways* m_alwaysCombp; // Current always if combo, otherwise NULL + bool m_inBBox; // In black box; mark as driven+used + bool m_inContAssign; // In continuous assignment + bool m_inProcAssign; // In procedural assignment + AstNodeFTask* m_taskp; // Current task + AstAlways* m_alwaysCombp; // Current always if combo, otherwise NULL // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -414,20 +414,19 @@ private: } // Until we support tables, primitives will have undriven and unused I/Os - virtual void visit(AstPrimitive* nodep) VL_OVERRIDE {} + virtual void visit(AstPrimitive*) VL_OVERRIDE {} // Coverage artifacts etc shouldn't count as a sink - virtual void visit(AstCoverDecl* nodep) VL_OVERRIDE {} - virtual void visit(AstCoverInc* nodep) VL_OVERRIDE {} - virtual void visit(AstCoverToggle* nodep) VL_OVERRIDE {} - virtual void visit(AstTraceDecl* nodep) VL_OVERRIDE {} - virtual void visit(AstTraceInc* nodep) VL_OVERRIDE {} + virtual void visit(AstCoverDecl*) VL_OVERRIDE {} + virtual void visit(AstCoverInc*) VL_OVERRIDE {} + virtual void visit(AstCoverToggle*) VL_OVERRIDE {} + virtual void visit(AstTraceDecl*) VL_OVERRIDE {} + virtual void visit(AstTraceInc*) VL_OVERRIDE {} // iterate virtual void visit(AstConst* nodep) VL_OVERRIDE {} - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS explicit UndrivenVisitor(AstNetlist* nodep) { @@ -443,7 +442,7 @@ public: it != m_entryps[1].end(); ++it) { (*it)->reportViolations(); } - for (int usr=1; usr<3; ++usr) { + for (int usr = 1; usr < 3; ++usr) { for (std::vector::iterator it = m_entryps[usr].begin(); it != m_entryps[usr].end(); ++it) { delete (*it); diff --git a/src/V3Undriven.h b/src/V3Undriven.h index e3b198aaa..4475ab053 100644 --- a/src/V3Undriven.h +++ b/src/V3Undriven.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index fb299cb0f..cfc998c2f 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Unknown's Transformations: @@ -456,10 +452,7 @@ private: } } //-------------------- - // Default: Just iterate - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } public: // CONSTRUCTORS diff --git a/src/V3Unknown.h b/src/V3Unknown.h index 9d2b965c4..db784a95a 100644 --- a/src/V3Unknown.h +++ b/src/V3Unknown.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp index 73e8c5dd6..d09c42540 100644 --- a/src/V3Unroll.cpp +++ b/src/V3Unroll.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3Unroll's Transformations: @@ -244,7 +240,7 @@ private: if (!simulateTree(initp->rhsp(), NULL, initp, loopValue)) { return false; } - while (1) { + while (true) { V3Number res = V3Number(initp); if (!simulateTree(condp, &loopValue, NULL, res)) { return false; @@ -304,7 +300,7 @@ private: ++m_statLoops; if (stmtsp) { int times = 0; - while (1) { + while (true) { UINFO(8," Looping "<prelim()) { // First stage evaluation + iterateCheckReal(nodep, "LHS", nodep->lhsp(), BOTH); + } + if (!nodep->dtypep()->widthSized()) nodep->v3fatalSrc("RToIRoundS should be presized"); + } // Widths: Output integer unsigned, input real - virtual void visit(AstRealToBits* nodep) VL_OVERRIDE { visit_Ou64_Lr(nodep); } + virtual void visit(AstRealToBits* nodep) VL_OVERRIDE { visit_Ou64_Lr(nodep); } // Output integer, input string virtual void visit(AstLenN* nodep) VL_OVERRIDE { visit_Os32_string(nodep); } @@ -1703,15 +1705,8 @@ private: AstNode* inewp; if (AstInsideRange* irangep = VN_CAST(itemp, InsideRange)) { // Similar logic in V3Case - AstNode* ap = new AstGte(itemp->fileline(), - nodep->exprp()->cloneTree(true), - irangep->lhsp()->unlinkFrBack()); - AstNode* bp = new AstLte(itemp->fileline(), - nodep->exprp()->cloneTree(true), - irangep->rhsp()->unlinkFrBack()); - ap->fileline()->modifyWarnOff(V3ErrorCode::UNSIGNED, true); - bp->fileline()->modifyWarnOff(V3ErrorCode::CMPCONST, true); - inewp = new AstAnd(itemp->fileline(), ap, bp); + inewp = irangep->newAndFromInside(nodep->exprp(), irangep->lhsp()->unlinkFrBack(), + irangep->rhsp()->unlinkFrBack()); } else { inewp = new AstEqWild(itemp->fileline(), nodep->exprp()->cloneTree(true), @@ -2503,7 +2498,7 @@ private: << VN_CAST(patp->keyp(), Text)->text()); } } - } while(0); + } while (false); // Next if (memp) memp = VN_CAST(memp->nextp(), MemberDType); if (patp) patp = VN_CAST(patp->nextp(), PatMember); @@ -2848,10 +2843,17 @@ private: case 'm': break; // %m - auto insert "name" case 'l': break; // %m - auto insert "library" case 'd': { // Convert decimal to either 'd' or '#' - if (argp && argp->isSigned()) { // Convert it - ch = '~'; + if (argp) { + AstNode* nextp = argp->nextp(); + if (argp->isDouble()) { + spliceCvtS(argp, true, 64); + ch = '~'; + } + else if (argp->isSigned()) { // Convert it + ch = '~'; + } + argp = nextp; } - if (argp) argp = argp->nextp(); break; } case 'p': { // Pattern @@ -2900,6 +2902,17 @@ private: if (argp) argp = argp->nextp(); break; } + case 'f': // FALLTHRU + case 'g': { + if (argp) { + AstNode* nextp = argp->nextp(); + if (!argp->isDouble()) { + iterateCheckReal(nodep, "Display argument", argp, BOTH); + } + argp = nextp; + } + break; + } case '?': { // Unspecified by user, guess if (argp && argp->isDouble()) { ch = 'g'; @@ -3379,7 +3392,7 @@ private: // AstPattern requires assignments to pass datatype on PRELIM VL_DO_DANGLING(userIterate(pinp, WidthVP(portp->dtypep(), PRELIM).p()), pinp); } - } while (0); + } while (false); // Stage 2 { V3TaskConnects tconnects = V3Task::taskConnects(nodep, nodep->taskp()->stmtsp()); @@ -4191,7 +4204,7 @@ private: underp = spliceCvtD(underp); underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, FINAL).p()); } else if (!expDTypep->isDouble() && underp->isDouble()) { - underp = spliceCvtS(underp, true); // Round RHS + underp = spliceCvtS(underp, true, expDTypep->width()); // Round RHS underp = userIterateSubtreeReturnEdits(underp, WidthVP(SELF, FINAL).p()); } else if (expDTypep->isString() && !underp->dtypep()->isString()) { underp = spliceCvtString(underp); @@ -4320,7 +4333,7 @@ private: if (nodep && nodep->isDouble()) { nodep->v3error("Expected integral (non-" << nodep->dtypep()->prettyDTypeName() << ") input to " << nodep->backp()->prettyTypeName()); - nodep = spliceCvtS(nodep, true); + nodep = spliceCvtS(nodep, true, 32); } return nodep; } @@ -4339,16 +4352,27 @@ private: return nodep; } } - AstNode* spliceCvtS(AstNode* nodep, bool warnOn) { + AstNode* spliceCvtS(AstNode* nodep, bool warnOn, int width) { // IEEE-2012 11.8.1: Signed: Type coercion creates signed // 11.8.2: Argument to convert is self-determined if (nodep && nodep->dtypep()->skipRefp()->isDouble()) { - UINFO(6," spliceCvtS: "<unlinkFrBack(&linker); + if (AstConst* constp = VN_CAST(nodep, Const)) { + // We convert to/from vlsint32 rather than use floor() as want to make sure is + // representable in integer's number of bits + if (constp->isDouble() + && v3EpsilonEqual(constp->num().toDouble(), + static_cast( + static_cast(constp->num().toDouble())))) { + warnOn = false; + } + } if (warnOn) nodep->v3warn(REALCVT, "Implicit conversion of real to integer"); AstNode* newp = new AstRToIRoundS(nodep->fileline(), nodep); linker.relink(newp); + newp->dtypeSetBitSized(width, AstNumeric::SIGNED); return newp; } else { return nodep; diff --git a/src/V3Width.h b/src/V3Width.h index 2fcd76764..5ba10dc80 100644 --- a/src/V3Width.h +++ b/src/V3Width.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/V3WidthCommit.h b/src/V3WidthCommit.h index 853c0cb78..7f4617b9d 100644 --- a/src/V3WidthCommit.h +++ b/src/V3WidthCommit.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -38,6 +34,14 @@ class WidthRemoveVisitor : public AstNVisitor { private: + // METHODS + void replaceWithSignedVersion(AstNode* nodep, AstNode* newp) { + UINFO(6, " Replace " << nodep << " w/ " << newp << endl); + nodep->replaceWith(newp); + newp->dtypeFrom(nodep); + VL_DO_DANGLING(pushDeletep(nodep), nodep); + } + // VISITORS virtual void visit(AstSigned* nodep) VL_OVERRIDE { VL_DO_DANGLING(replaceWithSignedVersion(nodep, nodep->lhsp()->unlinkFrBack()), nodep); @@ -45,15 +49,8 @@ private: virtual void visit(AstUnsigned* nodep) VL_OVERRIDE { VL_DO_DANGLING(replaceWithSignedVersion(nodep, nodep->lhsp()->unlinkFrBack()), nodep); } - virtual void visit(AstNode* nodep) VL_OVERRIDE { - iterateChildren(nodep); - } - void replaceWithSignedVersion(AstNode* nodep, AstNode* newp) { - UINFO(6," Replace "<replaceWith(newp); - newp->dtypeFrom(nodep); - VL_DO_DANGLING(pushDeletep(nodep), nodep); - } + virtual void visit(AstNode* nodep) VL_OVERRIDE { iterateChildren(nodep); } + public: // CONSTRUCTORS WidthRemoveVisitor() {} diff --git a/src/V3WidthSel.cpp b/src/V3WidthSel.cpp index d2ddff0bc..61facc612 100644 --- a/src/V3WidthSel.cpp +++ b/src/V3WidthSel.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // V3WidthSel's Transformations: diff --git a/src/Verilator.cpp b/src/Verilator.cpp index bf74ef44d..7b773f820 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/VlcBucket.h b/src/VlcBucket.h index 10881eb75..31b922b27 100644 --- a/src/VlcBucket.h +++ b/src/VlcBucket.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -37,17 +33,22 @@ private: vluint64_t m_bucketsCovered; ///< Num buckets with sufficient coverage private: - static inline vluint64_t covBit(vluint64_t point) { return 1ULL<<(point & 63); } + static inline vluint64_t covBit(vluint64_t point) { return 1ULL << (point & 63); } inline vluint64_t allocSize() const { return sizeof(vluint64_t) * m_dataSize / 64; } void allocate(vluint64_t point) { vluint64_t oldsize = m_dataSize; - if (m_dataSize= sufficient()) { - //UINFO(9," addData "< NameMap; // Sorted by name (ordered) + typedef std::map NameMap; // Sorted by name (ordered) NameMap m_nameMap; //< Name to point-number std::vector m_points; //< List of all points vluint64_t m_numPoints; //< Total unique points @@ -114,33 +110,28 @@ public: public: // CONSTRUCTORS - VlcPoints() { - m_numPoints = 0; - } + VlcPoints() : m_numPoints(0) {} ~VlcPoints() {} // METHODS void dump() { - UINFO(2,"dumpPoints...\n"); + UINFO(2, "dumpPoints...\n"); VlcPoint::dumpHeader(); - for (VlcPoints::ByName::iterator it=begin(); it!=end(); ++it) { + for (VlcPoints::ByName::const_iterator it = begin(); it != end(); ++it) { const VlcPoint& point = pointNumber(it->second); point.dump(); } } - VlcPoint& pointNumber(vluint64_t num) { - return m_points[num]; - } + VlcPoint& pointNumber(vluint64_t num) { return m_points[num]; } vluint64_t findAddPoint(const string& name, vluint64_t count) { vluint64_t pointnum; - NameMap::iterator iter = m_nameMap.find(name); + NameMap::const_iterator iter = m_nameMap.find(name); if (iter != m_nameMap.end()) { pointnum = iter->second; m_points[pointnum].countInc(count); - } - else { + } else { pointnum = m_numPoints++; - VlcPoint point (name, pointnum); + VlcPoint point(name, pointnum); point.countInc(count); m_points.push_back(point); m_nameMap.insert(make_pair(point.name(), point.pointNum())); diff --git a/src/VlcSource.h b/src/VlcSource.h index 447f448be..ea9f3ed2b 100644 --- a/src/VlcSource.h +++ b/src/VlcSource.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/VlcTest.h b/src/VlcTest.h index 3411f97e6..0b38ce9e8 100644 --- a/src/VlcTest.h +++ b/src/VlcTest.h @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -71,19 +67,20 @@ public: // METHODS static void dumpHeader() { - cout<<"Tests:\n"; - //cout<<" Testrun, Computrons,"; // Currently not loaded - cout<<" Covered, Rank, RankPts, Filename"< ByName; + private: // MEMBERS ByName m_tests; //< List of all tests @@ -109,16 +107,16 @@ public: // CONSTRUCTORS VlcTests() {} ~VlcTests() { - for (VlcTests::ByName::iterator it=begin(); it!=end(); ++it) { - VL_DO_CLEAR(delete *it, *it=NULL); + for (VlcTests::ByName::iterator it = begin(); it != end(); ++it) { + VL_DO_CLEAR(delete *it, *it = NULL); } } // METHODS void dump(bool bucketsToo) { - UINFO(2,"dumpTests...\n"); + UINFO(2, "dumpTests...\n"); VlcTest::dumpHeader(); - for (VlcTests::ByName::iterator it=begin(); it!=end(); ++it) { + for (VlcTests::ByName::const_iterator it = begin(); it != end(); ++it) { (*it)->dump(bucketsToo); } } diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp index d18c9a56d..0e08d299f 100644 --- a/src/VlcTop.cpp +++ b/src/VlcTop.cpp @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -30,11 +26,11 @@ //###################################################################### void VlcTop::readCoverage(const string& filename, bool nonfatal) { - UINFO(2,"readCoverage "<second); - os <<"C '"<computrons() != rhsp->computrons()) { return lhsp->computrons() < rhsp->computrons(); } @@ -93,12 +89,12 @@ struct CmpComputrons { }; void VlcTop::rank() { - UINFO(2,"rank...\n"); + UINFO(2, "rank...\n"); vluint64_t nextrank = 1; // Sort by computrons, so fast tests get selected first std::vector bytime; - for (VlcTests::ByName::iterator it=m_tests.begin(); it!=m_tests.end(); ++it) { + for (VlcTests::ByName::const_iterator it = m_tests.begin(); it != m_tests.end(); ++it) { VlcTest* testp = *it; if (testp->bucketsCovered()) { // else no points, so can't help us bytime.push_back(*it); @@ -107,21 +103,21 @@ void VlcTop::rank() { sort(bytime.begin(), bytime.end(), CmpComputrons()); // Sort the vector VlcBuckets remaining; - for (VlcPoints::ByName::iterator it=m_points.begin(); it!=m_points.end(); ++it) { + for (VlcPoints::ByName::const_iterator it = m_points.begin(); it != m_points.end(); ++it) { VlcPoint* pointp = &points().pointNumber(it->second); // If any tests hit this point, then we'll need to cover it. - if (pointp->testsCovering()) { remaining.addData(pointp->pointNum(), 1); } + if (pointp->testsCovering()) remaining.addData(pointp->pointNum(), 1); } // Additional Greedy algorithm // O(n^2) Ouch. Probably the thing to do is randomize the order of data // then hierarchically solve a small subset of tests, and take resulting // solution and move up to larger subset of tests. (Aka quick sort.) - while (1) { - if (debug()) { UINFO(9,"Left on iter"<::iterator it=bytime.begin(); it!=bytime.end(); ++it) { + for (std::vector::iterator it = bytime.begin(); it != bytime.end(); ++it) { VlcTest* testp = *it; if (!testp->rank()) { vluint64_t remain = testp->buckets().dataPopCount(remaining); @@ -145,17 +141,17 @@ void VlcTop::rank() { void VlcTop::annotateCalc() { // Calculate per-line information into filedata structure - for (VlcPoints::ByName::iterator it=m_points.begin(); it!=m_points.end(); ++it) { + for (VlcPoints::ByName::const_iterator it = m_points.begin(); it != m_points.end(); ++it) { const VlcPoint& point = m_points.pointNumber(it->second); string filename = point.filename(); int lineno = point.lineno(); - if (!filename.empty() && lineno!=0) { + if (!filename.empty() && lineno != 0) { int column = point.column(); VlcSource& source = sources().findNewSource(filename); string threshStr = point.thresh(); unsigned thresh = (!threshStr.empty()) ? atoi(threshStr.c_str()) : opt.annotateMin(); bool ok = (point.count() >= thresh); - UINFO(9, "AnnoCalc count "<second; - //UINFO(1,"Source "<second; - for (VlcSource::ColumnMap::iterator cit=cmap.begin(); cit!=cmap.end(); ++cit) { + for (VlcSource::ColumnMap::iterator cit = cmap.begin(); cit != cmap.end(); ++cit) { VlcSourceCount& col = cit->second; - //UINFO(0,"Source "<second; if (!source.needed()) continue; string filename = source.name(); - string outfilename = dirname+"/"+V3Os::filenameNonDir(filename); + string outfilename = dirname + "/" + V3Os::filenameNonDir(filename); - UINFO(1,"annotateOutputFile "< "< " << outfilename << endl); std::ifstream is(filename.c_str()); if (!is) { - v3error("Can't read "<second; - for (VlcSource::ColumnMap::iterator cit=cmap.begin(); cit!=cmap.end(); ++cit) { + for (VlcSource::ColumnMap::iterator cit = cmap.begin(); cit != cmap.end(); ++cit) { VlcSourceCount& col = cit->second; - //UINFO(0,"Source "< free Verilog EDA software tool suite. The latest version is available from CPAN and from L. -Copyright 2008-2020 by Wilson Snyder. This package is free software; you +Copyright 2008-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/src/config_build.h.in b/src/config_build.h.in index ab0c895ea..f06671416 100644 --- a/src/config_build.h.in +++ b/src/config_build.h.in @@ -8,15 +8,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/src/config_rev.pl b/src/config_rev.pl index cee6695f0..b1de61379 100755 --- a/src/config_rev.pl +++ b/src/config_rev.pl @@ -1,15 +1,11 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2005-2020 by Wilson Snyder. Verilator is free software; you +# Copyright 2005-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### # DESCRIPTION: Query's subversion to get version number diff --git a/src/cppcheck_filtered b/src/cppcheck_filtered index 1f962ea58..461c042da 100755 --- a/src/cppcheck_filtered +++ b/src/cppcheck_filtered @@ -223,14 +223,11 @@ This is part of the L free Verilog EDA software tool suite. The latest version is available from CPAN and from L. -Copyright 2014-2020 by Wilson Snyder. This package is free software; you +Copyright 2014-2020 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/src/flexfix b/src/flexfix index ac916d9a6..85c8abb72 100755 --- a/src/flexfix +++ b/src/flexfix @@ -1,15 +1,11 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2002-2020 by Wilson Snyder. Verilator is free software; you +# Copyright 2002-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### # DESCRIPTION: Edits flex output to get around various broken flex issues. diff --git a/src/pod2latexfix b/src/pod2latexfix index 149e311de..8e3b4e9d9 100755 --- a/src/pod2latexfix +++ b/src/pod2latexfix @@ -1,15 +1,11 @@ #!/usr/bin/env perl ###################################################################### # -# Copyright 2002-2020 by Wilson Snyder. Verilator is free software; you +# Copyright 2002-2020 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### # DESCRIPTION: Edits pod2latex output diff --git a/src/verilog.l b/src/verilog.l index 2ebd3694e..2674ff260 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -6,15 +6,11 @@ * ************************************************************************** * - * Copyright 2003-2020 by Wilson Snyder. Verilator is free software; - * you can redistribute it and/or modify it under the terms of either the + * Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you + * can redistribute it and/or modify it under the terms of either the * GNU Lesser General Public License Version 3 or the Perl Artistic License * Version 2.0. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 * *************************************************************************/ @@ -155,6 +151,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5} "public_module" { FL; return yVLT_PUBLIC_MODULE; } "sc_bv" { FL; return yVLT_SC_BV; } "sformat" { FL; return yVLT_SFORMAT; } + "split_var" { FL; return yVLT_SPLIT_VAR; } "tracing_off" { FL; return yVLT_TRACING_OFF; } "tracing_on" { FL; return yVLT_TRACING_ON; } diff --git a/src/verilog.y b/src/verilog.y index c7ba7f6b0..75a34552b 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -6,15 +6,11 @@ // //************************************************************************* // -// Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2003-2020 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* // Original code here by Paul Wasson and Duane Galbi @@ -295,6 +291,7 @@ class AstSenTree; %token yVLT_PUBLIC_MODULE "public_module" %token yVLT_SC_BV "sc_bv" %token yVLT_SFORMAT "sformat" +%token yVLT_SPLIT_VAR "split_var" %token yVLT_TRACING_OFF "tracing_off" %token yVLT_TRACING_ON "tracing_on" @@ -1014,6 +1011,7 @@ paramPortDeclOrArgList: // IEEE: list_of_param_assignments + { parameter_ paramPortDeclOrArg: // IEEE: param_assignment + parameter_port_declaration // // We combine the two as we can't tell which follows a comma parameter_port_declarationFrontE param_assignment { $$ = $2; } + | parameter_port_declarationTypeFrontE type_assignment { $$ = $2; } ; portsStarE: // IEEE: .* + list_of_ports + list_of_port_declarations + empty @@ -1346,6 +1344,7 @@ local_parameter_declaration: // IEEE: local_parameter_declaration // // See notes in parameter_declaration // // Front must execute first so VARDTYPE is ready before list of vars local_parameter_declarationFront list_of_param_assignments { $$ = $2; } + | local_parameter_declarationTypeFront list_of_type_assignments { $$ = $2; } ; parameter_declaration: // IEEE: parameter_declaration @@ -1354,21 +1353,30 @@ parameter_declaration: // IEEE: parameter_declaration // // we use list_of_param_assignments because for port handling // // it already must accept types, so simpler to have code only one place // // Front must execute first so VARDTYPE is ready before list of vars - parameter_declarationFront list_of_param_assignments { $$ = $2; } + parameter_declarationFront list_of_param_assignments { $$ = $2; } + | parameter_declarationTypeFront list_of_type_assignments { $$ = $2; } ; local_parameter_declarationFront: // IEEE: local_parameter_declaration w/o assignment // // Front must execute first so VARDTYPE is ready before list of vars varLParamReset implicit_typeE { /*VARRESET-in-varLParam*/ VARDTYPE($2); } | varLParamReset data_type { /*VARRESET-in-varLParam*/ VARDTYPE($2); } - | varLParamReset yTYPE { /*VARRESET-in-varLParam*/ VARDTYPE(new AstParseTypeDType($2)); } + ; + +local_parameter_declarationTypeFront: // IEEE: local_parameter_declaration w/o assignment + // // Front must execute first so VARDTYPE is ready before list of vars + varLParamReset yTYPE { /*VARRESET-in-varLParam*/ VARDTYPE(new AstParseTypeDType($2)); } ; parameter_declarationFront: // IEEE: parameter_declaration w/o assignment // // Front must execute first so VARDTYPE is ready before list of vars varGParamReset implicit_typeE { /*VARRESET-in-varGParam*/ VARDTYPE($2); } | varGParamReset data_type { /*VARRESET-in-varGParam*/ VARDTYPE($2); } - | varGParamReset yTYPE { /*VARRESET-in-varGParam*/ VARDTYPE(new AstParseTypeDType($2)); } + ; + +parameter_declarationTypeFront: // IEEE: parameter_declaration w/o assignment + // // Front must execute first so VARDTYPE is ready before list of vars + varGParamReset yTYPE { /*VARRESET-in-varGParam*/ VARDTYPE(new AstParseTypeDType($2)); } ; parameter_port_declarationFrontE: // IEEE: parameter_port_declaration w/o assignment @@ -1377,12 +1385,18 @@ parameter_port_declarationFrontE: // IEEE: parameter_port_declaration w/o assign // // Front must execute first so VARDTYPE is ready before list of vars varGParamReset implicit_typeE { /*VARRESET-in-varGParam*/ VARDTYPE($2); } | varGParamReset data_type { /*VARRESET-in-varGParam*/ VARDTYPE($2); } - | varGParamReset yTYPE { /*VARRESET-in-varGParam*/ VARDTYPE(new AstParseTypeDType($2)); } | varLParamReset implicit_typeE { /*VARRESET-in-varLParam*/ VARDTYPE($2); } | varLParamReset data_type { /*VARRESET-in-varLParam*/ VARDTYPE($2); } - | varLParamReset yTYPE { /*VARRESET-in-varLParam*/ VARDTYPE(new AstParseTypeDType($2)); } | implicit_typeE { /*VARRESET-in-varGParam*/ VARDTYPE($1); } | data_type { /*VARRESET-in-varGParam*/ VARDTYPE($1); } + ; + +parameter_port_declarationTypeFrontE: // IEEE: parameter_port_declaration w/o assignment + // // IEEE: parameter_declaration (minus assignment) + // // IEEE: local_parameter_declaration (minus assignment) + // // Front must execute first so VARDTYPE is ready before list of vars + varGParamReset yTYPE { /*VARRESET-in-varGParam*/ VARDTYPE(new AstParseTypeDType($2)); } + | varLParamReset yTYPE { /*VARRESET-in-varLParam*/ VARDTYPE(new AstParseTypeDType($2)); } | yTYPE { /*VARRESET-in-varGParam*/ VARDTYPE(new AstParseTypeDType($1)); } ; @@ -1651,6 +1665,7 @@ member_decl_assignment: // Derived from IEEE: variable_decl_assignment } | id variable_dimensionListE '=' variable_declExpr { $4->v3error("Unsupported: Initial values in struct/union members."); + // But still need error if packed according to IEEE 7.2.2 $$ = NULL; } | idSVKwd { $$ = NULL; } // @@ -1775,7 +1790,12 @@ enum_base_typeE: // IEEE: enum_base_type | integer_vector_type signingE rangeListE { $1->setSignedState($2); $$ = GRAMMARP->addRange($1,$3,true); } // // below can be idAny or yaID__aTYPE // // IEEE requires a type, though no shift conflict if idAny - | idAny rangeListE { $$ = GRAMMARP->createArray(new AstRefDType($1, *$1), $2, true); } + // // IEEE: type_identifier [ packed_dimension ] + // // however other simulators allow [ class_scope | package_scope ] type_identifier + | idAny rangeListE + { $$ = GRAMMARP->createArray(new AstRefDType($1, *$1), $2, true); } + | package_scopeIdFollows idRefDType rangeListE + { $2->packagep($1); $$ = GRAMMARP->createArray($2, $3, true); } ; enum_nameList: @@ -2352,8 +2372,7 @@ packed_dimension: // ==IEEE: packed_dimension param_assignment: // ==IEEE: param_assignment // // IEEE: constant_param_expression // // constant_param_expression: '$' is in expr - // // note exptOrDataType being a data_type is only for yPARAMETER yTYPE - id/*new-parameter*/ variable_dimensionListE sigAttrListE '=' exprOrDataType + id/*new-parameter*/ variable_dimensionListE sigAttrListE '=' expr /**/ { $$ = VARDONEA($1,*$1, $2, $3); $$->valuep($5); } | id/*new-parameter*/ variable_dimensionListE sigAttrListE /**/ { $$ = VARDONEA($1,*$1, $2, $3); @@ -2366,6 +2385,17 @@ list_of_param_assignments: // ==IEEE: list_of_param_assignments | list_of_param_assignments ',' param_assignment { $$ = $1; $1->addNext($3); } ; +type_assignment: // ==IEEE: type_assignment + // // note exptOrDataType being a data_type is only for yPARAMETER yTYPE + idAny/*new-parameter*/ sigAttrListE '=' data_type + /**/ { $$ = VARDONEA($1,*$1, NULL, $2); $$->valuep($4); } + ; + +list_of_type_assignments: // ==IEEE: list_of_type_assignments + type_assignment { $$ = $1; } + | list_of_type_assignments ',' type_assignment { $$ = $1; $1->addNext($3); } + ; + list_of_defparam_assignments: //== IEEE: list_of_defparam_assignments defparam_assignment { $$ = $1; } | list_of_defparam_assignments ',' defparam_assignment { $$ = $1->addNext($3); } @@ -5795,6 +5825,7 @@ vltVarAttrFront: | yVLT_PUBLIC_FLAT_RW { $$ = AstAttrType::VAR_PUBLIC_FLAT_RW; v3Global.dpi(true); } | yVLT_SC_BV { $$ = AstAttrType::VAR_SC_BV; } | yVLT_SFORMAT { $$ = AstAttrType::VAR_SFORMAT; } + | yVLT_SPLIT_VAR { $$ = AstAttrType::VAR_SPLIT_VAR; } ; //********************************************************************** diff --git a/src/vlcovgen b/src/vlcovgen index 135f80293..c99d9aa88 100755 --- a/src/vlcovgen +++ b/src/vlcovgen @@ -150,14 +150,12 @@ Displays this message and program version and exits. =head1 DISTRIBUTION -Copyright 2002-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2002-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/test_regress/CMakeLists.txt b/test_regress/CMakeLists.txt index e4492d064..e07568e89 100644 --- a/test_regress/CMakeLists.txt +++ b/test_regress/CMakeLists.txt @@ -4,10 +4,11 @@ # # This CMake file is meant to be consumed by regression tests. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/test_regress/Makefile b/test_regress/Makefile index e105ee9af..6f36732e7 100644 --- a/test_regress/Makefile +++ b/test_regress/Makefile @@ -5,10 +5,11 @@ # This calls the object directory makefile. That allows the objects to # be placed in the "current directory" which simplifies the Makefile. # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #****************************************************************************/ diff --git a/test_regress/Makefile_obj b/test_regress/Makefile_obj index 02d911e7b..1678e3afb 100644 --- a/test_regress/Makefile_obj +++ b/test_regress/Makefile_obj @@ -5,10 +5,11 @@ # # This is executed in the object directory, and called by ../Makefile # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # #***************************************************************************** diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 1d967ba8c..db3f488e5 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -277,7 +277,7 @@ sub _calc_hashset { local $/; unpack("%32W*", $t); }; - if ($set == ($checksum % $nsets)) { + if (($set % $nsets) == ($checksum % $nsets)) { push @new, $t; } } @@ -2691,9 +2691,12 @@ Command to use to invoke XSim xvlog The latest version is available from L. -Copyright 2003-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2003-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/test_regress/t/TestSimulator.h b/test_regress/t/TestSimulator.h index 0e933df92..6a6803774 100644 --- a/test_regress/t/TestSimulator.h +++ b/test_regress/t/TestSimulator.h @@ -3,13 +3,9 @@ // // Copyright 2013-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/TestVpi.h b/test_regress/t/TestVpi.h index 6d4f4b1f1..843d65c4c 100644 --- a/test_regress/t/TestVpi.h +++ b/test_regress/t/TestVpi.h @@ -3,13 +3,9 @@ // // Copyright 2013-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/bootstrap.pl b/test_regress/t/bootstrap.pl index 418e56d58..9672e2299 100755 --- a/test_regress/t/bootstrap.pl +++ b/test_regress/t/bootstrap.pl @@ -1,10 +1,11 @@ #!/usr/bin/env perl # DESCRIPTION: Verilator: Verilog Test driver bootstrapper # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This is exec'ed by every test that is run standalone (called from the # shell as ./t_test_name.pl) diff --git a/test_regress/t/t_EXAMPLE.pl b/test_regress/t/t_EXAMPLE.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_EXAMPLE.pl +++ b/test_regress/t/t_EXAMPLE.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v index 83fde058a..befacfb1a 100644 --- a/test_regress/t/t_EXAMPLE.v +++ b/test_regress/t/t_EXAMPLE.v @@ -12,10 +12,11 @@ // **If you do not wish for your code to be released to the public // please note it here, otherwise:** // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by ____YOUR_NAME_HERE____. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 ____YOUR_NAME_HERE____. +// SPDX-License-Identifier: CC0-1.0 -module t (/*AUTOARG*/ +module t(/*AUTOARG*/ // Inputs clk ); @@ -33,12 +34,12 @@ module t (/*AUTOARG*/ wire [31:0] out; // From test of Test.v // End of automatics - Test test (/*AUTOINST*/ - // Outputs - .out (out[31:0]), - // Inputs - .clk (clk), - .in (in[31:0])); + Test test(/*AUTOINST*/ + // Outputs + .out (out[31:0]), + // Inputs + .clk (clk), + .in (in[31:0])); // Aggregate outputs into a single result vector wire [63:0] result = {32'h0, out}; @@ -51,17 +52,17 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; - if (cyc==0) begin + if (cyc == 0) begin // Setup crc <= 64'h5aef0c8d_d70a4497; sum <= '0; end - else if (cyc<10) begin + else if (cyc < 10) begin sum <= '0; end - else if (cyc<90) begin + else if (cyc < 90) begin end - else if (cyc==99) begin + else if (cyc == 99) begin $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); if (crc !== 64'hc77bb9b3784ea091) $stop; // What checksum will we end up with (above print should match) @@ -74,7 +75,7 @@ module t (/*AUTOARG*/ endmodule -module Test (/*AUTOARG*/ +module Test(/*AUTOARG*/ // Outputs out, // Inputs diff --git a/test_regress/t/t_a1_first_cc.pl b/test_regress/t/t_a1_first_cc.pl index 3ec02ecfd..08bcb4345 100755 --- a/test_regress/t/t_a1_first_cc.pl +++ b/test_regress/t/t_a1_first_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # show-config: This test runs the very first time we've executed Verilator # after building so we make sure to run with --gdbbt, so if it dumps we'll diff --git a/test_regress/t/t_a1_first_cc.v b/test_regress/t/t_a1_first_cc.v index d90fb7797..e541f39d9 100644 --- a/test_regress/t/t_a1_first_cc.v +++ b/test_regress/t/t_a1_first_cc.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_a2_first_sc.pl b/test_regress/t/t_a2_first_sc.pl index 72415320a..208b206ea 100755 --- a/test_regress/t/t_a2_first_sc.pl +++ b/test_regress/t/t_a2_first_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test runs the very first time we've executed Verilator --sc # after building so we make sure to run with --gdbbt, so if it dumps we'll diff --git a/test_regress/t/t_a3_selftest.pl b/test_regress/t/t_a3_selftest.pl index 284eb878a..8f89936ed 100755 --- a/test_regress/t/t_a3_selftest.pl +++ b/test_regress/t/t_a3_selftest.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_a4_examples.pl b/test_regress/t/t_a4_examples.pl index 070484da8..09c6958ca 100755 --- a/test_regress/t/t_a4_examples.pl +++ b/test_regress/t/t_a4_examples.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_altera_lpm_abs.pl b/test_regress/t/t_altera_lpm_abs.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_abs.pl +++ b/test_regress/t/t_altera_lpm_abs.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_add_sub.pl b/test_regress/t/t_altera_lpm_add_sub.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_add_sub.pl +++ b/test_regress/t/t_altera_lpm_add_sub.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_and.pl b/test_regress/t/t_altera_lpm_and.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_and.pl +++ b/test_regress/t/t_altera_lpm_and.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_bustri.pl b/test_regress/t/t_altera_lpm_bustri.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_bustri.pl +++ b/test_regress/t/t_altera_lpm_bustri.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_clshift.pl b/test_regress/t/t_altera_lpm_clshift.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_clshift.pl +++ b/test_regress/t/t_altera_lpm_clshift.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_compare.pl b/test_regress/t/t_altera_lpm_compare.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_compare.pl +++ b/test_regress/t/t_altera_lpm_compare.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_constant.pl b/test_regress/t/t_altera_lpm_constant.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_constant.pl +++ b/test_regress/t/t_altera_lpm_constant.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_counter.pl b/test_regress/t/t_altera_lpm_counter.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_counter.pl +++ b/test_regress/t/t_altera_lpm_counter.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_decode.pl b/test_regress/t/t_altera_lpm_decode.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_decode.pl +++ b/test_regress/t/t_altera_lpm_decode.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_divide.pl b/test_regress/t/t_altera_lpm_divide.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_divide.pl +++ b/test_regress/t/t_altera_lpm_divide.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_ff.pl b/test_regress/t/t_altera_lpm_ff.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_ff.pl +++ b/test_regress/t/t_altera_lpm_ff.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_fifo.pl b/test_regress/t/t_altera_lpm_fifo.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_fifo.pl +++ b/test_regress/t/t_altera_lpm_fifo.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_fifo_dc.pl b/test_regress/t/t_altera_lpm_fifo_dc.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_fifo_dc.pl +++ b/test_regress/t/t_altera_lpm_fifo_dc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_inv.pl b/test_regress/t/t_altera_lpm_inv.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_inv.pl +++ b/test_regress/t/t_altera_lpm_inv.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_latch.pl b/test_regress/t/t_altera_lpm_latch.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_latch.pl +++ b/test_regress/t/t_altera_lpm_latch.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_mult.pl b/test_regress/t/t_altera_lpm_mult.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_mult.pl +++ b/test_regress/t/t_altera_lpm_mult.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_mux.pl b/test_regress/t/t_altera_lpm_mux.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_mux.pl +++ b/test_regress/t/t_altera_lpm_mux.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_or.pl b/test_regress/t/t_altera_lpm_or.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_or.pl +++ b/test_regress/t/t_altera_lpm_or.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_ram_dp.pl b/test_regress/t/t_altera_lpm_ram_dp.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_ram_dp.pl +++ b/test_regress/t/t_altera_lpm_ram_dp.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_ram_dq.pl b/test_regress/t/t_altera_lpm_ram_dq.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_ram_dq.pl +++ b/test_regress/t/t_altera_lpm_ram_dq.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_ram_io.pl b/test_regress/t/t_altera_lpm_ram_io.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_ram_io.pl +++ b/test_regress/t/t_altera_lpm_ram_io.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_rom.pl b/test_regress/t/t_altera_lpm_rom.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_rom.pl +++ b/test_regress/t/t_altera_lpm_rom.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_shiftreg.pl b/test_regress/t/t_altera_lpm_shiftreg.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_shiftreg.pl +++ b/test_regress/t/t_altera_lpm_shiftreg.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_altera_lpm_xor.pl b/test_regress/t/t_altera_lpm_xor.pl index 20782a400..65defb5b2 100755 --- a/test_regress/t/t_altera_lpm_xor.pl +++ b/test_regress/t/t_altera_lpm_xor.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_alw_combdly.pl b/test_regress/t/t_alw_combdly.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_alw_combdly.pl +++ b/test_regress/t/t_alw_combdly.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_alw_combdly.v b/test_regress/t/t_alw_combdly.v index b17127d6e..38cdc0694 100644 --- a/test_regress/t/t_alw_combdly.v +++ b/test_regress/t/t_alw_combdly.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_alw_dly.pl b/test_regress/t/t_alw_dly.pl index a83c168ba..8dff4ed0c 100755 --- a/test_regress/t/t_alw_dly.pl +++ b/test_regress/t/t_alw_dly.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_alw_dly.v b/test_regress/t/t_alw_dly.v index 781a6706c..0cc82e2e6 100644 --- a/test_regress/t/t_alw_dly.v +++ b/test_regress/t/t_alw_dly.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_alw_noreorder.pl b/test_regress/t/t_alw_noreorder.pl index 58ff89bc9..140987464 100755 --- a/test_regress/t/t_alw_noreorder.pl +++ b/test_regress/t/t_alw_noreorder.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_alw_nosplit.pl b/test_regress/t/t_alw_nosplit.pl index a9edeead4..269e7d577 100755 --- a/test_regress/t/t_alw_nosplit.pl +++ b/test_regress/t/t_alw_nosplit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_alw_nosplit.v b/test_regress/t/t_alw_nosplit.v index 4d1db199e..53a29461e 100644 --- a/test_regress/t/t_alw_nosplit.v +++ b/test_regress/t/t_alw_nosplit.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_alw_reorder.pl b/test_regress/t/t_alw_reorder.pl index bedc40be3..9dc659d01 100755 --- a/test_regress/t/t_alw_reorder.pl +++ b/test_regress/t/t_alw_reorder.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_alw_reorder.v b/test_regress/t/t_alw_reorder.v index 7433bfbe7..2501945fe 100644 --- a/test_regress/t/t_alw_reorder.v +++ b/test_regress/t/t_alw_reorder.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_alw_split.pl b/test_regress/t/t_alw_split.pl index b0117e349..c1e43c8d2 100755 --- a/test_regress/t/t_alw_split.pl +++ b/test_regress/t/t_alw_split.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_alw_split.v b/test_regress/t/t_alw_split.v index f852753ec..8d5419ac1 100644 --- a/test_regress/t/t_alw_split.v +++ b/test_regress/t/t_alw_split.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_alw_split_cond.pl b/test_regress/t/t_alw_split_cond.pl index 5c448de7c..d1bf185c9 100755 --- a/test_regress/t/t_alw_split_cond.pl +++ b/test_regress/t/t_alw_split_cond.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_alw_split_cond.v b/test_regress/t/t_alw_split_cond.v index 11361438c..e1af8f173 100644 --- a/test_regress/t/t_alw_split_cond.v +++ b/test_regress/t/t_alw_split_cond.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug1604 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_alw_split_rst.pl b/test_regress/t/t_alw_split_rst.pl index 9f75a887f..4ef955903 100755 --- a/test_regress/t/t_alw_split_rst.pl +++ b/test_regress/t/t_alw_split_rst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_alw_split_rst.v b/test_regress/t/t_alw_split_rst.v index 9d2c3fb4f..b0f411f53 100644 --- a/test_regress/t/t_alw_split_rst.v +++ b/test_regress/t/t_alw_split_rst.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_alw_splitord.pl b/test_regress/t/t_alw_splitord.pl index a9ab8f248..e4e7ec5d6 100755 --- a/test_regress/t/t_alw_splitord.pl +++ b/test_regress/t/t_alw_splitord.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_alw_splitord.v b/test_regress/t/t_alw_splitord.v index f3136899f..b6529f97c 100644 --- a/test_regress/t/t_alw_splitord.v +++ b/test_regress/t/t_alw_splitord.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_array_backw_index_bad.out b/test_regress/t/t_array_backw_index_bad.out index 5ecdd8245..65c2aee38 100644 --- a/test_regress/t/t_array_backw_index_bad.out +++ b/test_regress/t/t_array_backw_index_bad.out @@ -1,21 +1,21 @@ -%Error: t/t_array_backw_index_bad.v:13: Slice selection '[1:3]' has backward indexing versus data type's '[3:0]' - : ... In instance t - array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; - ^ -%Error: t/t_array_backw_index_bad.v:14: Slice selection '[3:1]' has backward indexing versus data type's '[0:3]' - : ... In instance t - larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; - ^ -%Error: t/t_array_backw_index_bad.v:16: Slice selection index '[4:3]' outside data type's '[3:0]' - : ... In instance t - array_assign[4:3] = '{32'd4, 32'd3}; - ^ -%Error: t/t_array_backw_index_bad.v:17: Slice selection index '[1:-1]' outside data type's '[3:0]' - : ... In instance t - array_assign[1:-1] = '{32'd4, 32'd3}; - ^ -%Error: t/t_array_backw_index_bad.v:17: Assignment pattern missed initializing elements: -1 - : ... In instance t - array_assign[1:-1] = '{32'd4, 32'd3}; - ^~ +%Error: t/t_array_backw_index_bad.v:14:19: Slice selection '[1:3]' has backward indexing versus data type's '[3:0]' + : ... In instance t + 14 | array_assign[1:3] = '{32'd4, 32'd3, 32'd2}; + | ^ +%Error: t/t_array_backw_index_bad.v:15:20: Slice selection '[3:1]' has backward indexing versus data type's '[0:3]' + : ... In instance t + 15 | larray_assign[3:1] = '{32'd4, 32'd3, 32'd2}; + | ^ +%Error: t/t_array_backw_index_bad.v:17:19: Slice selection index '[4:3]' outside data type's '[3:0]' + : ... In instance t + 17 | array_assign[4:3] = '{32'd4, 32'd3}; + | ^ +%Error: t/t_array_backw_index_bad.v:18:19: Slice selection index '[1:-1]' outside data type's '[3:0]' + : ... In instance t + 18 | array_assign[1:-1] = '{32'd4, 32'd3}; + | ^ +%Error: t/t_array_backw_index_bad.v:18:28: Assignment pattern missed initializing elements: -1 + : ... In instance t + 18 | array_assign[1:-1] = '{32'd4, 32'd3}; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_array_backw_index_bad.pl b/test_regress/t/t_array_backw_index_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_array_backw_index_bad.pl +++ b/test_regress/t/t_array_backw_index_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_backw_index_bad.v b/test_regress/t/t_array_backw_index_bad.v index 626830448..b76aceba1 100644 --- a/test_regress/t/t_array_backw_index_bad.v +++ b/test_regress/t/t_array_backw_index_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_array_compare.pl b/test_regress/t/t_array_compare.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_array_compare.pl +++ b/test_regress/t/t_array_compare.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_compare.v b/test_regress/t/t_array_compare.v index d94464815..116bbf1d1 100644 --- a/test_regress/t/t_array_compare.v +++ b/test_regress/t/t_array_compare.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Andrew Bardsley. +// SPDX-License-Identifier: CC0-1.0 // bug1071 diff --git a/test_regress/t/t_array_interface.pl b/test_regress/t/t_array_interface.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_array_interface.pl +++ b/test_regress/t/t_array_interface.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_interface.v b/test_regress/t/t_array_interface.v index 3d8eaa78c..73ed3ecac 100644 --- a/test_regress/t/t_array_interface.v +++ b/test_regress/t/t_array_interface.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 interface intf; logic logic_in_intf; diff --git a/test_regress/t/t_array_interface_noinl.pl b/test_regress/t/t_array_interface_noinl.pl index 1fa90dabe..0fdd2e40a 100755 --- a/test_regress/t/t_array_interface_noinl.pl +++ b/test_regress/t/t_array_interface_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_list_bad.out b/test_regress/t/t_array_list_bad.out index fae4a64b4..45f539258 100644 --- a/test_regress/t/t_array_list_bad.out +++ b/test_regress/t/t_array_list_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_array_list_bad.v:37: Assignment pattern missed initializing elements: MEMBERDTYPE 't3' - : ... In instance t - test_out <= '{'0, '0}; - ^~ -%Warning-WIDTH: t/t_array_list_bad.v:37: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. - : ... In instance t - test_out <= '{'0, '0}; - ^~ +%Error: t/t_array_list_bad.v:38:25: Assignment pattern missed initializing elements: MEMBERDTYPE 't3' + : ... In instance t + 38 | test_out <= '{'0, '0}; + | ^~ +%Warning-WIDTH: t/t_array_list_bad.v:38:22: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS's CONCAT generates 2 bits. + : ... In instance t + 38 | test_out <= '{'0, '0}; + | ^~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_array_list_bad.pl b/test_regress/t/t_array_list_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_array_list_bad.pl +++ b/test_regress/t/t_array_list_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_array_list_bad.v b/test_regress/t/t_array_list_bad.v index 50f2f0004..b50e8531b 100644 --- a/test_regress/t/t_array_list_bad.v +++ b/test_regress/t/t_array_list_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 package pkg; typedef struct packed { diff --git a/test_regress/t/t_array_mda.pl b/test_regress/t/t_array_mda.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_array_mda.pl +++ b/test_regress/t/t_array_mda.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_mda.v b/test_regress/t/t_array_mda.v index 648c9b3c6..2c4cd8350 100644 --- a/test_regress/t/t_array_mda.v +++ b/test_regress/t/t_array_mda.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_array_packed_sysfunct.pl b/test_regress/t/t_array_packed_sysfunct.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_array_packed_sysfunct.pl +++ b/test_regress/t/t_array_packed_sysfunct.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_packed_sysfunct.v b/test_regress/t/t_array_packed_sysfunct.v index 03934588c..fbbdec136 100644 --- a/test_regress/t/t_array_packed_sysfunct.v +++ b/test_regress/t/t_array_packed_sysfunct.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_array_packed_write_read.pl b/test_regress/t/t_array_packed_write_read.pl index 7c51fd4da..f9888b6ba 100755 --- a/test_regress/t/t_array_packed_write_read.pl +++ b/test_regress/t/t_array_packed_write_read.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug446"); diff --git a/test_regress/t/t_array_packed_write_read.v b/test_regress/t/t_array_packed_write_read.v index 5d6907886..99aae9117 100644 --- a/test_regress/t/t_array_packed_write_read.v +++ b/test_regress/t/t_array_packed_write_read.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_array_pattern_2d.pl b/test_regress/t/t_array_pattern_2d.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_array_pattern_2d.pl +++ b/test_regress/t/t_array_pattern_2d.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_pattern_2d.v b/test_regress/t/t_array_pattern_2d.v index 797c9d485..dba37eef2 100644 --- a/test_regress/t/t_array_pattern_2d.v +++ b/test_regress/t/t_array_pattern_2d.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 //bug991 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_array_pattern_bad.out b/test_regress/t/t_array_pattern_bad.out index 450acd2c7..957b1715e 100644 --- a/test_regress/t/t_array_pattern_bad.out +++ b/test_regress/t/t_array_pattern_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_array_pattern_bad.v:23: Assignment pattern key 'valids' not found as member - : ... In instance t - valids: '1}; - ^~~~~~ +%Error: t/t_array_pattern_bad.v:24:18: Assignment pattern key 'valids' not found as member + : ... In instance t + 24 | valids: '1}; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_array_pattern_bad.pl b/test_regress/t/t_array_pattern_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_array_pattern_bad.pl +++ b/test_regress/t/t_array_pattern_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_pattern_bad.v b/test_regress/t/t_array_pattern_bad.v index 563de8ccd..6e00d149b 100644 --- a/test_regress/t/t_array_pattern_bad.v +++ b/test_regress/t/t_array_pattern_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug1364 diff --git a/test_regress/t/t_array_pattern_packed.pl b/test_regress/t/t_array_pattern_packed.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_array_pattern_packed.pl +++ b/test_regress/t/t_array_pattern_packed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_pattern_packed.v b/test_regress/t/t_array_pattern_packed.v index 768f64d46..8023dae9f 100644 --- a/test_regress/t/t_array_pattern_packed.v +++ b/test_regress/t/t_array_pattern_packed.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_array_pattern_unpacked.pl b/test_regress/t/t_array_pattern_unpacked.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_array_pattern_unpacked.pl +++ b/test_regress/t/t_array_pattern_unpacked.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_pattern_unpacked.v b/test_regress/t/t_array_pattern_unpacked.v index 903c8eaae..aaf1db6c4 100644 --- a/test_regress/t/t_array_pattern_unpacked.v +++ b/test_regress/t/t_array_pattern_unpacked.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_array_query.pl b/test_regress/t/t_array_query.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_array_query.pl +++ b/test_regress/t/t_array_query.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_query.v b/test_regress/t/t_array_query.v index 741787c6f..5f824d520 100644 --- a/test_regress/t/t_array_query.v +++ b/test_regress/t/t_array_query.v @@ -5,6 +5,7 @@ // // This file ONLY is placed into the Public Domain, for any use, without // warranty. +// SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Jeremy Bennett, Embecosm. diff --git a/test_regress/t/t_array_rev.pl b/test_regress/t/t_array_rev.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_array_rev.pl +++ b/test_regress/t/t_array_rev.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_rev.v b/test_regress/t/t_array_rev.v index f9b4a9402..b46935b34 100644 --- a/test_regress/t/t_array_rev.v +++ b/test_regress/t/t_array_rev.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Geoff Barrett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_array_type_methods.pl b/test_regress/t/t_array_type_methods.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_array_type_methods.pl +++ b/test_regress/t/t_array_type_methods.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_type_methods.v b/test_regress/t/t_array_type_methods.v index 0af06c8ee..48429bdd9 100644 --- a/test_regress/t/t_array_type_methods.v +++ b/test_regress/t/t_array_type_methods.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_array_unpacked_public.pl b/test_regress/t/t_array_unpacked_public.pl index 1bb1cc973..cc9e72798 100755 --- a/test_regress/t/t_array_unpacked_public.pl +++ b/test_regress/t/t_array_unpacked_public.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_array_unpacked_public.v b/test_regress/t/t_array_unpacked_public.v index a54ea36e2..fecfba51e 100644 --- a/test_regress/t/t_array_unpacked_public.v +++ b/test_regress/t/t_array_unpacked_public.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Stefan Wallentowitz +// without warranty, 2020 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 module t(); logic din [0:15]; diff --git a/test_regress/t/t_arraysel_wide.pl b/test_regress/t/t_arraysel_wide.pl index 5c448de7c..d1bf185c9 100755 --- a/test_regress/t/t_arraysel_wide.pl +++ b/test_regress/t/t_arraysel_wide.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_arraysel_wide.v b/test_regress/t/t_arraysel_wide.v index f00f68a00..943216e4e 100644 --- a/test_regress/t/t_arraysel_wide.v +++ b/test_regress/t/t_arraysel_wide.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_assert_basic.pl b/test_regress/t/t_assert_basic.pl index f97a8c4aa..4c0a46a1c 100755 --- a/test_regress/t/t_assert_basic.pl +++ b/test_regress/t/t_assert_basic.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_basic.v b/test_regress/t/t_assert_basic.v index 3de503741..0d718015d 100644 --- a/test_regress/t/t_assert_basic.v +++ b/test_regress/t/t_assert_basic.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assert_basic_cover.pl b/test_regress/t/t_assert_basic_cover.pl index a92304bcf..edbd8eae1 100755 --- a/test_regress/t/t_assert_basic_cover.pl +++ b/test_regress/t/t_assert_basic_cover.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_basic_fail.pl b/test_regress/t/t_assert_basic_fail.pl index 18621d701..20b8a4bb5 100755 --- a/test_regress/t/t_assert_basic_fail.pl +++ b/test_regress/t/t_assert_basic_fail.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_basic_off.pl b/test_regress/t/t_assert_basic_off.pl index 4945cc73c..ce432c44f 100755 --- a/test_regress/t/t_assert_basic_off.pl +++ b/test_regress/t/t_assert_basic_off.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_casez.pl b/test_regress/t/t_assert_casez.pl index be109d263..0d28d8ef2 100755 --- a/test_regress/t/t_assert_casez.pl +++ b/test_regress/t/t_assert_casez.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_casez.v b/test_regress/t/t_assert_casez.v index 760b628de..359fc4ef2 100644 --- a/test_regress/t/t_assert_casez.v +++ b/test_regress/t/t_assert_casez.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_assert_comp.pl b/test_regress/t/t_assert_comp.pl index f97a8c4aa..4c0a46a1c 100755 --- a/test_regress/t/t_assert_comp.pl +++ b/test_regress/t/t_assert_comp.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_comp.v b/test_regress/t/t_assert_comp.v index d51f679b6..50fe0168b 100644 --- a/test_regress/t/t_assert_comp.v +++ b/test_regress/t/t_assert_comp.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_assert_comp_bad.out b/test_regress/t/t_assert_comp_bad.out index a3d3be7a7..9906f8e57 100644 --- a/test_regress/t/t_assert_comp_bad.out +++ b/test_regress/t/t_assert_comp_bad.out @@ -1,18 +1,18 @@ --Info: t/t_assert_comp_bad.v:9: User compile-time info - : ... In instance t - $info("User compile-time info"); - ^~~~~ -%Warning-USERWARN: t/t_assert_comp_bad.v:10: User compile-time warning - : ... In instance t - $warning("User compile-time warning"); - ^~~~~~~~ +-Info: t/t_assert_comp_bad.v:10:7: User compile-time info + : ... In instance t + 10 | $info("User compile-time info"); + | ^~~~~ +%Warning-USERWARN: t/t_assert_comp_bad.v:11:7: User compile-time warning + : ... In instance t + 11 | $warning("User compile-time warning"); + | ^~~~~~~~ ... Use "/* verilator lint_off USERWARN */" and lint_on around source to disable this message. -%Warning-USERWARN: t/t_assert_comp_bad.v:11: 1 - : ... In instance t - $warning(1); - ^~~~~~~~ -%Warning-USERERROR: t/t_assert_comp_bad.v:12: User compile-time error - : ... In instance t - $error("User compile-time error"); - ^~~~~~ +%Warning-USERWARN: t/t_assert_comp_bad.v:12:7: 1 + : ... In instance t + 12 | $warning(1); + | ^~~~~~~~ +%Warning-USERERROR: t/t_assert_comp_bad.v:13:7: User compile-time error + : ... In instance t + 13 | $error("User compile-time error"); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_comp_bad.pl b/test_regress/t/t_assert_comp_bad.pl index 27ed6fc92..3ec9bc8ca 100755 --- a/test_regress/t/t_assert_comp_bad.pl +++ b/test_regress/t/t_assert_comp_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_comp_bad.v b/test_regress/t/t_assert_comp_bad.v index 028175bec..6f4146fdc 100644 --- a/test_regress/t/t_assert_comp_bad.v +++ b/test_regress/t/t_assert_comp_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_assert_cover.pl b/test_regress/t/t_assert_cover.pl index 929ab0cc1..27417ed8a 100755 --- a/test_regress/t/t_assert_cover.pl +++ b/test_regress/t/t_assert_cover.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_cover.v b/test_regress/t/t_assert_cover.v index f40e3193e..dd90d552e 100644 --- a/test_regress/t/t_assert_cover.v +++ b/test_regress/t/t_assert_cover.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assert_cover_off.pl b/test_regress/t/t_assert_cover_off.pl index 5b0c97c27..d0720ac25 100755 --- a/test_regress/t/t_assert_cover_off.pl +++ b/test_regress/t/t_assert_cover_off.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_disable_iff.pl b/test_regress/t/t_assert_disable_iff.pl index 90b4e1666..8b6c4232e 100644 --- a/test_regress/t/t_assert_disable_iff.pl +++ b/test_regress/t/t_assert_disable_iff.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_disable_iff.v b/test_regress/t/t_assert_disable_iff.v index 7e07d0184..de74764dc 100644 --- a/test_regress/t/t_assert_disable_iff.v +++ b/test_regress/t/t_assert_disable_iff.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Peter Monsson. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assert_disabled.pl b/test_regress/t/t_assert_disabled.pl index ce40c03ef..0fd1a2ed2 100755 --- a/test_regress/t/t_assert_disabled.pl +++ b/test_regress/t/t_assert_disabled.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_dup_bad.out b/test_regress/t/t_assert_dup_bad.out index 366bdec58..8357b40ac 100644 --- a/test_regress/t/t_assert_dup_bad.out +++ b/test_regress/t/t_assert_dup_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_assert_dup_bad.v:16: Duplicate declaration of block: 'covlabel' - covlabel: - ^~~~~~~~ - t/t_assert_dup_bad.v:14: ... Location of original declaration - covlabel: - ^~~~~~~~ +%Error: t/t_assert_dup_bad.v:17:4: Duplicate declaration of block: 'covlabel' + 17 | covlabel: + | ^~~~~~~~ + t/t_assert_dup_bad.v:15:4: ... Location of original declaration + 15 | covlabel: + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_dup_bad.pl b/test_regress/t/t_assert_dup_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_assert_dup_bad.pl +++ b/test_regress/t/t_assert_dup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_assert_dup_bad.v b/test_regress/t/t_assert_dup_bad.v index 6edaa221c..aef62c7f4 100644 --- a/test_regress/t/t_assert_dup_bad.v +++ b/test_regress/t/t_assert_dup_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assert_elab.pl b/test_regress/t/t_assert_elab.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_assert_elab.pl +++ b/test_regress/t/t_assert_elab.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_elab.v b/test_regress/t/t_assert_elab.v index 98283bbab..15b21a53d 100644 --- a/test_regress/t/t_assert_elab.v +++ b/test_regress/t/t_assert_elab.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 module t; localparam str = "string"; diff --git a/test_regress/t/t_assert_elab_bad.pl b/test_regress/t/t_assert_elab_bad.pl index 60f651b06..e4646c599 100755 --- a/test_regress/t/t_assert_elab_bad.pl +++ b/test_regress/t/t_assert_elab_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_enabled_bad.pl b/test_regress/t/t_assert_enabled_bad.pl index e97edee06..f9b49a910 100755 --- a/test_regress/t/t_assert_enabled_bad.pl +++ b/test_regress/t/t_assert_enabled_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_enabled_off.pl b/test_regress/t/t_assert_enabled_off.pl index 68476d21b..332a16068 100755 --- a/test_regress/t/t_assert_enabled_off.pl +++ b/test_regress/t/t_assert_enabled_off.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_assert_enabled_on_bad.pl b/test_regress/t/t_assert_enabled_on_bad.pl index b93de98fc..34d22352e 100755 --- a/test_regress/t/t_assert_enabled_on_bad.pl +++ b/test_regress/t/t_assert_enabled_on_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_assert_implication.pl b/test_regress/t/t_assert_implication.pl index fd994540c..fcfd1a86d 100755 --- a/test_regress/t/t_assert_implication.pl +++ b/test_regress/t/t_assert_implication.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_implication.v b/test_regress/t/t_assert_implication.v index 686d65643..9f2f96f91 100644 --- a/test_regress/t/t_assert_implication.v +++ b/test_regress/t/t_assert_implication.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Peter Monsson. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assert_implication_bad.pl b/test_regress/t/t_assert_implication_bad.pl index eb6f2f7e3..3fd3170f3 100755 --- a/test_regress/t/t_assert_implication_bad.pl +++ b/test_regress/t/t_assert_implication_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_inside_cond.pl b/test_regress/t/t_assert_inside_cond.pl new file mode 100755 index 000000000..90950ed85 --- /dev/null +++ b/test_regress/t/t_assert_inside_cond.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND"], + ); + +execute( + ); + +ok(1); +1; diff --git a/test_regress/t/t_assert_inside_cond.v b/test_regress/t/t_assert_inside_cond.v new file mode 100644 index 000000000..6f12ec6d7 --- /dev/null +++ b/test_regress/t/t_assert_inside_cond.v @@ -0,0 +1,46 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Outputs + hit, + // Inputs + clk + ); + + input clk; + output logic hit; + + logic [31:0] addr; + int cyc; + + initial addr = 32'h380; + + always @ (posedge clk) begin + cyc <= cyc + 1; +`ifdef T_ASSERT_INSIDE_COND + addr <= 32'h380; +`elsif T_ASSERT_INSIDE_COND_BAD + addr <= 32'h389; +`else + `error "Bad test define" +`endif + if (cyc == 9) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + + always_comb begin + hit = 0; + unique case (addr[11:0]) inside + [12'h380 : 12'h388]: begin + hit = 1; + end + endcase + end + +endmodule diff --git a/test_regress/t/t_assert_inside_cond_bad.out b/test_regress/t/t_assert_inside_cond_bad.out new file mode 100644 index 000000000..5defe9702 --- /dev/null +++ b/test_regress/t/t_assert_inside_cond_bad.out @@ -0,0 +1,3 @@ +[10] %Error: t_assert_inside_cond.v:39: Assertion failed in top.t: synthesis parallel_case, but multiple matches found +%Error: t/t_assert_inside_cond.v:39: Verilog $stop +Aborting... diff --git a/test_regress/t/t_assert_inside_cond_bad.pl b/test_regress/t/t_assert_inside_cond_bad.pl new file mode 100755 index 000000000..d715dbf2e --- /dev/null +++ b/test_regress/t/t_assert_inside_cond_bad.pl @@ -0,0 +1,25 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_assert_inside_cond.v"); + +compile( + verilator_flags2 => ["-x-assign 0 --assert +define+T_ASSERT_INSIDE_COND_BAD"], + ); + +execute( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_assert_on.v b/test_regress/t/t_assert_on.v index c6ae564e6..55704fa6b 100644 --- a/test_regress/t/t_assert_on.v +++ b/test_regress/t/t_assert_on.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assert_property.pl b/test_regress/t/t_assert_property.pl index fd994540c..fcfd1a86d 100755 --- a/test_regress/t/t_assert_property.pl +++ b/test_regress/t/t_assert_property.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_property.v b/test_regress/t/t_assert_property.v index 32f225a1d..797a48b52 100644 --- a/test_regress/t/t_assert_property.v +++ b/test_regress/t/t_assert_property.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assert_property_fail_1.pl b/test_regress/t/t_assert_property_fail_1.pl index 78b3d4d95..8637b2865 100755 --- a/test_regress/t/t_assert_property_fail_1.pl +++ b/test_regress/t/t_assert_property_fail_1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_property_fail_2.pl b/test_regress/t/t_assert_property_fail_2.pl index 1a4446161..c640ba27a 100755 --- a/test_regress/t/t_assert_property_fail_2.pl +++ b/test_regress/t/t_assert_property_fail_2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_question.pl b/test_regress/t/t_assert_question.pl index be109d263..0d28d8ef2 100755 --- a/test_regress/t/t_assert_question.pl +++ b/test_regress/t/t_assert_question.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_question.v b/test_regress/t/t_assert_question.v index c72584535..8c6f4fe81 100644 --- a/test_regress/t/t_assert_question.v +++ b/test_regress/t/t_assert_question.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_assert_synth.pl b/test_regress/t/t_assert_synth.pl index f97a8c4aa..4c0a46a1c 100755 --- a/test_regress/t/t_assert_synth.pl +++ b/test_regress/t/t_assert_synth.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_synth.v b/test_regress/t/t_assert_synth.v index 4e090850b..2a8f27e2b 100644 --- a/test_regress/t/t_assert_synth.v +++ b/test_regress/t/t_assert_synth.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assert_synth_full.out b/test_regress/t/t_assert_synth_full.out new file mode 100644 index 000000000..cf081f789 --- /dev/null +++ b/test_regress/t/t_assert_synth_full.out @@ -0,0 +1,3 @@ +[40] %Error: t_assert_synth.v:31: Assertion failed in top.t: synthesis full_case, but non-match found +%Error: t/t_assert_synth.v:31: Verilog $stop +Aborting... diff --git a/test_regress/t/t_assert_synth_full.pl b/test_regress/t/t_assert_synth_full.pl index eb9239199..9cbec7d08 100755 --- a/test_regress/t/t_assert_synth_full.pl +++ b/test_regress/t/t_assert_synth_full.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -20,8 +21,7 @@ compile( execute( check_finished => 0, fails => $Self->{vlt_all}, - expect => -'%Error: t_assert_synth.v:30: Assertion failed in top.t: synthesis full_case' + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_assert_synth_full.vlt b/test_regress/t/t_assert_synth_full.vlt index e2615f828..ab46a1251 100644 --- a/test_regress/t/t_assert_synth_full.vlt +++ b/test_regress/t/t_assert_synth_full.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_assert_synth_full_vlt.out b/test_regress/t/t_assert_synth_full_vlt.out index ad5ebd09f..72ae3003f 100644 --- a/test_regress/t/t_assert_synth_full_vlt.out +++ b/test_regress/t/t_assert_synth_full_vlt.out @@ -1,3 +1,3 @@ -[40] %Error: t_assert_synth.v:32: Assertion failed in top.t: synthesis full_case, but non-match found -%Error: t/t_assert_synth.v:32: Verilog $stop +[40] %Error: t_assert_synth.v:40: Assertion failed in top.t: synthesis full_case, but non-match found +%Error: t/t_assert_synth.v:40: Verilog $stop Aborting... diff --git a/test_regress/t/t_assert_synth_full_vlt.pl b/test_regress/t/t_assert_synth_full_vlt.pl index eb2eb54ae..ad39b7dc0 100755 --- a/test_regress/t/t_assert_synth_full_vlt.pl +++ b/test_regress/t/t_assert_synth_full_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_synth_off.pl b/test_regress/t/t_assert_synth_off.pl index 173ff7ad5..c75ee9028 100755 --- a/test_regress/t/t_assert_synth_off.pl +++ b/test_regress/t/t_assert_synth_off.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assert_synth_parallel.out b/test_regress/t/t_assert_synth_parallel.out new file mode 100644 index 000000000..6bf8c8773 --- /dev/null +++ b/test_regress/t/t_assert_synth_parallel.out @@ -0,0 +1,3 @@ +[40] %Error: t_assert_synth.v:50: Assertion failed in top.t: synthesis parallel_case, but multiple matches found +%Error: t/t_assert_synth.v:50: Verilog $stop +Aborting... diff --git a/test_regress/t/t_assert_synth_parallel.pl b/test_regress/t/t_assert_synth_parallel.pl index 628288ac8..df87d5e21 100755 --- a/test_regress/t/t_assert_synth_parallel.pl +++ b/test_regress/t/t_assert_synth_parallel.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -20,8 +21,7 @@ compile( execute( check_finished => 0, fails => $Self->{vlt_all}, - expect => -'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case' + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_assert_synth_parallel.vlt b/test_regress/t/t_assert_synth_parallel.vlt index d25ddaf06..c2ddfb908 100644 --- a/test_regress/t/t_assert_synth_parallel.vlt +++ b/test_regress/t/t_assert_synth_parallel.vlt @@ -2,7 +2,8 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config -parallel_case -file "t/t_assert_synth.v" -lines 54 +parallel_case -file "t/t_assert_synth.v" -lines 55 diff --git a/test_regress/t/t_assert_synth_parallel_vlt.out b/test_regress/t/t_assert_synth_parallel_vlt.out new file mode 100644 index 000000000..f0adb9c21 --- /dev/null +++ b/test_regress/t/t_assert_synth_parallel_vlt.out @@ -0,0 +1,3 @@ +[40] %Error: t_assert_synth.v:55: Assertion failed in top.t: synthesis parallel_case, but multiple matches found +%Error: t/t_assert_synth.v:55: Verilog $stop +Aborting... diff --git a/test_regress/t/t_assert_synth_parallel_vlt.pl b/test_regress/t/t_assert_synth_parallel_vlt.pl index c9cd46167..16ede2a0e 100755 --- a/test_regress/t/t_assert_synth_parallel_vlt.pl +++ b/test_regress/t/t_assert_synth_parallel_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -20,8 +21,7 @@ compile( execute( check_finished => 0, fails => $Self->{vlt_all}, - expect => -'%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case' + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_assign_inline.pl b/test_regress/t/t_assign_inline.pl index 4a4b40f3b..5e67daa36 100755 --- a/test_regress/t/t_assign_inline.pl +++ b/test_regress/t/t_assign_inline.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assign_inline.v b/test_regress/t/t_assign_inline.v index 5d29871a9..1b7033e80 100644 --- a/test_regress/t/t_assign_inline.v +++ b/test_regress/t/t_assign_inline.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Mike Thyer. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_assoc.pl b/test_regress/t/t_assoc.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_assoc.pl +++ b/test_regress/t/t_assoc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_assoc.v b/test_regress/t/t_assoc.v index cf3293d0c..8740c3679 100644 --- a/test_regress/t/t_assoc.v +++ b/test_regress/t/t_assoc.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_assoc_meth_bad.out b/test_regress/t/t_assoc_meth_bad.out index 26cbe65dd..6b3d75789 100644 --- a/test_regress/t/t_assoc_meth_bad.out +++ b/test_regress/t/t_assoc_meth_bad.out @@ -1,37 +1,37 @@ -%Error: t/t_assoc_meth_bad.v:13: The 1 arguments passed to .num method does not match its requiring 0 arguments - : ... In instance t - v = a.num("badarg"); - ^~~ -%Error: t/t_assoc_meth_bad.v:14: The 1 arguments passed to .size method does not match its requiring 0 arguments - : ... In instance t - v = a.size("badarg"); - ^~~~ -%Error: t/t_assoc_meth_bad.v:15: The 0 arguments passed to .exists method does not match its requiring 1 arguments - : ... In instance t - v = a.exists(); - ^~~~~~ -%Error: t/t_assoc_meth_bad.v:16: The 2 arguments passed to .exists method does not match its requiring 1 arguments - : ... In instance t - v = a.exists(k, "bad2"); - ^~~~~~ -%Error: t/t_assoc_meth_bad.v:17: The 0 arguments passed to .first method does not match its requiring 1 arguments - : ... In instance t - v = a.first(); - ^~~~~ -%Error: t/t_assoc_meth_bad.v:18: The 2 arguments passed to .next method does not match its requiring 1 arguments - : ... In instance t - v = a.next(k, "bad2"); - ^~~~ -%Error: t/t_assoc_meth_bad.v:19: The 0 arguments passed to .last method does not match its requiring 1 arguments - : ... In instance t - v = a.last(); - ^~~~ -%Error: t/t_assoc_meth_bad.v:20: The 2 arguments passed to .prev method does not match its requiring 1 arguments - : ... In instance t - v = a.prev(k, "bad2"); - ^~~~ -%Error: t/t_assoc_meth_bad.v:21: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments - : ... In instance t - a.delete(k, "bad2"); - ^~~~~~ +%Error: t/t_assoc_meth_bad.v:14:13: The 1 arguments passed to .num method does not match its requiring 0 arguments + : ... In instance t + 14 | v = a.num("badarg"); + | ^~~ +%Error: t/t_assoc_meth_bad.v:15:13: The 1 arguments passed to .size method does not match its requiring 0 arguments + : ... In instance t + 15 | v = a.size("badarg"); + | ^~~~ +%Error: t/t_assoc_meth_bad.v:16:13: The 0 arguments passed to .exists method does not match its requiring 1 arguments + : ... In instance t + 16 | v = a.exists(); + | ^~~~~~ +%Error: t/t_assoc_meth_bad.v:17:13: The 2 arguments passed to .exists method does not match its requiring 1 arguments + : ... In instance t + 17 | v = a.exists(k, "bad2"); + | ^~~~~~ +%Error: t/t_assoc_meth_bad.v:18:13: The 0 arguments passed to .first method does not match its requiring 1 arguments + : ... In instance t + 18 | v = a.first(); + | ^~~~~ +%Error: t/t_assoc_meth_bad.v:19:13: The 2 arguments passed to .next method does not match its requiring 1 arguments + : ... In instance t + 19 | v = a.next(k, "bad2"); + | ^~~~ +%Error: t/t_assoc_meth_bad.v:20:13: The 0 arguments passed to .last method does not match its requiring 1 arguments + : ... In instance t + 20 | v = a.last(); + | ^~~~ +%Error: t/t_assoc_meth_bad.v:21:13: The 2 arguments passed to .prev method does not match its requiring 1 arguments + : ... In instance t + 21 | v = a.prev(k, "bad2"); + | ^~~~ +%Error: t/t_assoc_meth_bad.v:22:9: The 2 arguments passed to .delete method does not match its requiring 0 to 1 arguments + : ... In instance t + 22 | a.delete(k, "bad2"); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assoc_meth_bad.pl b/test_regress/t/t_assoc_meth_bad.pl index 49151b6cd..2365c113e 100755 --- a/test_regress/t/t_assoc_meth_bad.pl +++ b/test_regress/t/t_assoc_meth_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_assoc_meth_bad.v b/test_regress/t/t_assoc_meth_bad.v index e935fb7d3..7174b7844 100644 --- a/test_regress/t/t_assoc_meth_bad.v +++ b/test_regress/t/t_assoc_meth_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_assoc_pattern_unsup.out b/test_regress/t/t_assoc_pattern_unsup.out index 51f4430cd..6df0d8f82 100644 --- a/test_regress/t/t_assoc_pattern_unsup.out +++ b/test_regress/t/t_assoc_pattern_unsup.out @@ -1,5 +1,5 @@ -%Error: t/t_assoc_pattern_unsup.v:18: Unsupported: Assignment pattern applies against non struct/union data type: 'string[string]' - : ... In instance t - a = '{ "f": "fooed", "b": "bared", default: "defaulted" }; - ^~ +%Error: t/t_assoc_pattern_unsup.v:19:11: Unsupported: Assignment pattern applies against non struct/union data type: 'string[string]' + : ... In instance t + 19 | a = '{ "f": "fooed", "b": "bared", default: "defaulted" }; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_assoc_pattern_unsup.pl b/test_regress/t/t_assoc_pattern_unsup.pl index 49151b6cd..2365c113e 100755 --- a/test_regress/t/t_assoc_pattern_unsup.pl +++ b/test_regress/t/t_assoc_pattern_unsup.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_assoc_pattern_unsup.v b/test_regress/t/t_assoc_pattern_unsup.v index 5010d550a..e2f896a0f 100644 --- a/test_regress/t/t_assoc_pattern_unsup.v +++ b/test_regress/t/t_assoc_pattern_unsup.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_assoc_wildcard_unsup.pl b/test_regress/t/t_assoc_wildcard_unsup.pl index 49151b6cd..2365c113e 100755 --- a/test_regress/t/t_assoc_wildcard_unsup.pl +++ b/test_regress/t/t_assoc_wildcard_unsup.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_assoc_wildcard_unsup.v b/test_regress/t/t_assoc_wildcard_unsup.v index e4ddb0697..d29a50bf8 100644 --- a/test_regress/t/t_assoc_wildcard_unsup.v +++ b/test_regress/t/t_assoc_wildcard_unsup.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_attr_parenstar.pl b/test_regress/t/t_attr_parenstar.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_attr_parenstar.pl +++ b/test_regress/t/t_attr_parenstar.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_attr_parenstar.v b/test_regress/t/t_attr_parenstar.v index 9b68ff475..d96199a74 100644 --- a/test_regress/t/t_attr_parenstar.v +++ b/test_regress/t/t_attr_parenstar.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_bench_mux4k.pl b/test_regress/t/t_bench_mux4k.pl index 2e5f4af6e..be3b43873 100755 --- a/test_regress/t/t_bench_mux4k.pl +++ b/test_regress/t/t_bench_mux4k.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bench_mux4k.v b/test_regress/t/t_bench_mux4k.v index 2280e1364..10be1c273 100644 --- a/test_regress/t/t_bench_mux4k.v +++ b/test_regress/t/t_bench_mux4k.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 // // This implements a 4096:1 mux via two stages of 64:1 muxing. diff --git a/test_regress/t/t_bench_mux4k_onecpu.pl b/test_regress/t/t_bench_mux4k_onecpu.pl index 2e075dc69..c56ecd683 100755 --- a/test_regress/t/t_bench_mux4k_onecpu.pl +++ b/test_regress/t/t_bench_mux4k_onecpu.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bind.pl b/test_regress/t/t_bind.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_bind.pl +++ b/test_regress/t/t_bind.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bind.v b/test_regress/t/t_bind.v index 5576b3d2d..33b2abaaf 100644 --- a/test_regress/t/t_bind.v +++ b/test_regress/t/t_bind.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 bit a_finished; bit b_finished; diff --git a/test_regress/t/t_bind2.pl b/test_regress/t/t_bind2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_bind2.pl +++ b/test_regress/t/t_bind2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bind2.v b/test_regress/t/t_bind2.v index b9cc73220..fd97a54d7 100644 --- a/test_regress/t/t_bind2.v +++ b/test_regress/t/t_bind2.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Ed Lander. +// SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH diff --git a/test_regress/t/t_bitsel_const_bad.out b/test_regress/t/t_bitsel_const_bad.out index 1bcbf6c61..767882eeb 100644 --- a/test_regress/t/t_bitsel_const_bad.out +++ b/test_regress/t/t_bitsel_const_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_bitsel_const_bad.v:20: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... In instance t - assign a = b[0]; - ^ +%Error: t/t_bitsel_const_bad.v:21:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... In instance t + 21 | assign a = b[0]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_const_bad.pl b/test_regress/t/t_bitsel_const_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_bitsel_const_bad.pl +++ b/test_regress/t/t_bitsel_const_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_bitsel_const_bad.v b/test_regress/t/t_bitsel_const_bad.v index 918ba6ffe..53aa133e4 100644 --- a/test_regress/t/t_bitsel_const_bad.v +++ b/test_regress/t/t_bitsel_const_bad.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_bitsel_enum.pl b/test_regress/t/t_bitsel_enum.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_bitsel_enum.pl +++ b/test_regress/t/t_bitsel_enum.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bitsel_enum.v b/test_regress/t/t_bitsel_enum.v index 4e316df2a..b23b72142 100644 --- a/test_regress/t/t_bitsel_enum.v +++ b/test_regress/t/t_bitsel_enum.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Jonathon Donaldson. +// SPDX-License-Identifier: CC0-1.0 module t_bitsel_enum ( diff --git a/test_regress/t/t_bitsel_slice.pl b/test_regress/t/t_bitsel_slice.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_bitsel_slice.pl +++ b/test_regress/t/t_bitsel_slice.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bitsel_slice.v b/test_regress/t/t_bitsel_slice.v index 304ec4a9b..f943829c2 100644 --- a/test_regress/t/t_bitsel_slice.v +++ b/test_regress/t/t_bitsel_slice.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_bitsel_struct.pl b/test_regress/t/t_bitsel_struct.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_bitsel_struct.pl +++ b/test_regress/t/t_bitsel_struct.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bitsel_struct.v b/test_regress/t/t_bitsel_struct.v index f8920d9ca..80fb3f837 100644 --- a/test_regress/t/t_bitsel_struct.v +++ b/test_regress/t/t_bitsel_struct.v @@ -7,6 +7,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_bitsel_struct2.pl b/test_regress/t/t_bitsel_struct2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_bitsel_struct2.pl +++ b/test_regress/t/t_bitsel_struct2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bitsel_struct2.v b/test_regress/t/t_bitsel_struct2.v index f399711c4..e53d8c6bf 100644 --- a/test_regress/t/t_bitsel_struct2.v +++ b/test_regress/t/t_bitsel_struct2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_bitsel_struct3.pl b/test_regress/t/t_bitsel_struct3.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_bitsel_struct3.pl +++ b/test_regress/t/t_bitsel_struct3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bitsel_struct3.v b/test_regress/t/t_bitsel_struct3.v index 444b29da5..5edb5d0a8 100644 --- a/test_regress/t/t_bitsel_struct3.v +++ b/test_regress/t/t_bitsel_struct3.v @@ -7,6 +7,7 @@ // // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2013 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_bitsel_wire_array_bad.out b/test_regress/t/t_bitsel_wire_array_bad.out index 54c16baa4..d256eef7d 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.out +++ b/test_regress/t/t_bitsel_wire_array_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_bitsel_wire_array_bad.v:20: Illegal assignment of constant to unpacked array - : ... In instance t - assign b = a[0]; - ^ +%Error: t/t_bitsel_wire_array_bad.v:21:16: Illegal assignment of constant to unpacked array + : ... In instance t + 21 | assign b = a[0]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_bitsel_wire_array_bad.pl b/test_regress/t/t_bitsel_wire_array_bad.pl index c40b6592b..c6036e2f3 100755 --- a/test_regress/t/t_bitsel_wire_array_bad.pl +++ b/test_regress/t/t_bitsel_wire_array_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_bitsel_wire_array_bad.v b/test_regress/t/t_bitsel_wire_array_bad.v index 90c050162..729b272f9 100644 --- a/test_regress/t/t_bitsel_wire_array_bad.v +++ b/test_regress/t/t_bitsel_wire_array_bad.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_blocking.pl b/test_regress/t/t_blocking.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_blocking.pl +++ b/test_regress/t/t_blocking.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_blocking.v b/test_regress/t/t_blocking.v index f2df6a672..fa6ec64de 100644 --- a/test_regress/t/t_blocking.v +++ b/test_regress/t/t_blocking.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_bug3180.pl b/test_regress/t/t_bug3180.pl index 5fb3165c1..53a8b0126 100755 --- a/test_regress/t/t_bug3180.pl +++ b/test_regress/t/t_bug3180.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_bug3180.v b/test_regress/t/t_bug3180.v index e5a2561d9..85651289b 100644 --- a/test_regress/t/t_bug3180.v +++ b/test_regress/t/t_bug3180.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_case_66bits.pl b/test_regress/t/t_case_66bits.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_66bits.pl +++ b/test_regress/t/t_case_66bits.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_66bits.v b/test_regress/t/t_case_66bits.v index e138e316d..95333a83b 100644 --- a/test_regress/t/t_case_66bits.v +++ b/test_regress/t/t_case_66bits.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_auto1.pl b/test_regress/t/t_case_auto1.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_auto1.pl +++ b/test_regress/t/t_case_auto1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_auto1.v b/test_regress/t/t_case_auto1.v index 32ea1d424..6d82878b6 100644 --- a/test_regress/t/t_case_auto1.v +++ b/test_regress/t/t_case_auto1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_deep.pl b/test_regress/t/t_case_deep.pl index 803dca735..d6841bed0 100755 --- a/test_regress/t/t_case_deep.pl +++ b/test_regress/t/t_case_deep.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_deep.v b/test_regress/t/t_case_deep.v index 3e4f9d5af..1883d5af8 100644 --- a/test_regress/t/t_case_deep.v +++ b/test_regress/t/t_case_deep.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_default_bad.out b/test_regress/t/t_case_default_bad.out index 50f7838f4..49b92c1ea 100644 --- a/test_regress/t/t_case_default_bad.out +++ b/test_regress/t/t_case_default_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_case_default_bad.v:15: Multiple default statements in case statement. - default: $stop; - ^~~~~~~ +%Error: t/t_case_default_bad.v:16:9: Multiple default statements in case statement. + 16 | default: $stop; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_case_default_bad.pl b/test_regress/t/t_case_default_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_case_default_bad.pl +++ b/test_regress/t/t_case_default_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_case_default_bad.v b/test_regress/t/t_case_default_bad.v index 882d24ca0..4099e2d6b 100644 --- a/test_regress/t/t_case_default_bad.v +++ b/test_regress/t/t_case_default_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_dupitems.pl b/test_regress/t/t_case_dupitems.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_dupitems.pl +++ b/test_regress/t/t_case_dupitems.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_dupitems.v b/test_regress/t/t_case_dupitems.v index c389a7ea4..8f38669e8 100644 --- a/test_regress/t/t_case_dupitems.v +++ b/test_regress/t/t_case_dupitems.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_genx_bad.out b/test_regress/t/t_case_genx_bad.out index b449bd71f..abdb81e62 100644 --- a/test_regress/t/t_case_genx_bad.out +++ b/test_regress/t/t_case_genx_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_case_genx_bad.v:13: Use of x/? constant in generate case statement, (no such thing as 'generate casez') - : ... In instance t - 32'b1xxx: initial begin end - ^~~~~~~~ +%Error: t/t_case_genx_bad.v:14:9: Use of x/? constant in generate case statement, (no such thing as 'generate casez') + : ... In instance t + 14 | 32'b1xxx: initial begin end + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_case_genx_bad.pl b/test_regress/t/t_case_genx_bad.pl index 518625206..f3dd1d2a1 100755 --- a/test_regress/t/t_case_genx_bad.pl +++ b/test_regress/t/t_case_genx_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_case_genx_bad.v b/test_regress/t/t_case_genx_bad.v index b09bea3e4..ef8e6f47b 100644 --- a/test_regress/t/t_case_genx_bad.v +++ b/test_regress/t/t_case_genx_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_case_group.pl b/test_regress/t/t_case_group.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_group.pl +++ b/test_regress/t/t_case_group.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_group.v b/test_regress/t/t_case_group.v index 32cb99ed2..0c7f1e625 100644 --- a/test_regress/t/t_case_group.v +++ b/test_regress/t/t_case_group.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_case_huge.pl b/test_regress/t/t_case_huge.pl index 14ce67913..423f9f2c3 100755 --- a/test_regress/t/t_case_huge.pl +++ b/test_regress/t/t_case_huge.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_huge.v b/test_regress/t/t_case_huge.v index 4eeaee866..cff27ca14 100644 --- a/test_regress/t/t_case_huge.v +++ b/test_regress/t/t_case_huge.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_huge_prof.pl b/test_regress/t/t_case_huge_prof.pl index 01b754c58..d12633181 100755 --- a/test_regress/t/t_case_huge_prof.pl +++ b/test_regress/t/t_case_huge_prof.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_case_huge_sub.v b/test_regress/t/t_case_huge_sub.v index c0118f1c2..c40ed7f32 100644 --- a/test_regress/t/t_case_huge_sub.v +++ b/test_regress/t/t_case_huge_sub.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_case_huge_sub2.v b/test_regress/t/t_case_huge_sub2.v index 53e2ab113..d753dff22 100644 --- a/test_regress/t/t_case_huge_sub2.v +++ b/test_regress/t/t_case_huge_sub2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub2 (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_case_huge_sub3.v b/test_regress/t/t_case_huge_sub3.v index 746344f3d..8174c9100 100644 --- a/test_regress/t/t_case_huge_sub3.v +++ b/test_regress/t/t_case_huge_sub3.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub3 (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_case_huge_sub4.v b/test_regress/t/t_case_huge_sub4.v index 831995502..b4eb77d28 100644 --- a/test_regress/t/t_case_huge_sub4.v +++ b/test_regress/t/t_case_huge_sub4.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_case_huge_sub4 (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_case_inside.pl b/test_regress/t/t_case_inside.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_inside.pl +++ b/test_regress/t/t_case_inside.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_inside.v b/test_regress/t/t_case_inside.v index 20aac26aa..59879dd2e 100644 --- a/test_regress/t/t_case_inside.v +++ b/test_regress/t/t_case_inside.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_itemwidth.pl b/test_regress/t/t_case_itemwidth.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_itemwidth.pl +++ b/test_regress/t/t_case_itemwidth.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_itemwidth.v b/test_regress/t/t_case_itemwidth.v index 4828f2386..67385ac9a 100644 --- a/test_regress/t/t_case_itemwidth.v +++ b/test_regress/t/t_case_itemwidth.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_nest.pl b/test_regress/t/t_case_nest.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_nest.pl +++ b/test_regress/t/t_case_nest.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_nest.v b/test_regress/t/t_case_nest.v index cb51c3321..8ba5b85d8 100644 --- a/test_regress/t/t_case_nest.v +++ b/test_regress/t/t_case_nest.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_onehot.pl b/test_regress/t/t_case_onehot.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_onehot.pl +++ b/test_regress/t/t_case_onehot.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_onehot.v b/test_regress/t/t_case_onehot.v index ca3dfff3c..2f71d68e9 100644 --- a/test_regress/t/t_case_onehot.v +++ b/test_regress/t/t_case_onehot.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_orig.pl b/test_regress/t/t_case_orig.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_orig.pl +++ b/test_regress/t/t_case_orig.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_orig.v b/test_regress/t/t_case_orig.v index 4acd3097c..eb40b783b 100644 --- a/test_regress/t/t_case_orig.v +++ b/test_regress/t/t_case_orig.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_reducer.pl b/test_regress/t/t_case_reducer.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_reducer.pl +++ b/test_regress/t/t_case_reducer.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_reducer.v b/test_regress/t/t_case_reducer.v index 306786154..44e0a11bc 100644 --- a/test_regress/t/t_case_reducer.v +++ b/test_regress/t/t_case_reducer.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_string.pl b/test_regress/t/t_case_string.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_string.pl +++ b/test_regress/t/t_case_string.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_string.v b/test_regress/t/t_case_string.v index c7fbde92b..a91a9a09d 100644 --- a/test_regress/t/t_case_string.v +++ b/test_regress/t/t_case_string.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_wild.pl b/test_regress/t/t_case_wild.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_case_wild.pl +++ b/test_regress/t/t_case_wild.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_wild.v b/test_regress/t/t_case_wild.v index 5264c38eb..c6daa0688 100644 --- a/test_regress/t/t_case_wild.v +++ b/test_regress/t/t_case_wild.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_write1.pl b/test_regress/t/t_case_write1.pl index 646a4254b..f108b9a2c 100755 --- a/test_regress/t/t_case_write1.pl +++ b/test_regress/t/t_case_write1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_write1.v b/test_regress/t/t_case_write1.v index c0d1123bc..7c3c8edf7 100644 --- a/test_regress/t/t_case_write1.v +++ b/test_regress/t/t_case_write1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "verilated.v" diff --git a/test_regress/t/t_case_write1_tasks.v b/test_regress/t/t_case_write1_tasks.v index 0c4844254..9a1a46669 100644 --- a/test_regress/t/t_case_write1_tasks.v +++ b/test_regress/t/t_case_write1_tasks.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "verilated.v" diff --git a/test_regress/t/t_case_write2.pl b/test_regress/t/t_case_write2.pl index 646a4254b..f108b9a2c 100755 --- a/test_regress/t/t_case_write2.pl +++ b/test_regress/t/t_case_write2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_write2.v b/test_regress/t/t_case_write2.v index 3110fc3a2..98d50c2b5 100644 --- a/test_regress/t/t_case_write2.v +++ b/test_regress/t/t_case_write2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "verilated.v" diff --git a/test_regress/t/t_case_write2_tasks.v b/test_regress/t/t_case_write2_tasks.v index 9790eaad3..eb0298ae1 100644 --- a/test_regress/t/t_case_write2_tasks.v +++ b/test_regress/t/t_case_write2_tasks.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "verilated.v" diff --git a/test_regress/t/t_case_x.pl b/test_regress/t/t_case_x.pl index 53262ac3e..d67e81f2e 100755 --- a/test_regress/t/t_case_x.pl +++ b/test_regress/t/t_case_x.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_case_x.v b/test_regress/t/t_case_x.v index 205261273..ac2ef544c 100644 --- a/test_regress/t/t_case_x.v +++ b/test_regress/t/t_case_x.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_case_x_bad.out b/test_regress/t/t_case_x_bad.out index 29c09348a..db1e485fa 100644 --- a/test_regress/t/t_case_x_bad.out +++ b/test_regress/t/t_case_x_bad.out @@ -1,8 +1,8 @@ -%Warning-CASEX: t/t_case_x_bad.v:13: Suggest casez (with ?'s) in place of casex (with X's) - casex (value) - ^~~~~ +%Warning-CASEX: t/t_case_x_bad.v:14:7: Suggest casez (with ?'s) in place of casex (with X's) + 14 | casex (value) + | ^~~~~ ... Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message. -%Warning-CASEWITHX: t/t_case_x_bad.v:18: Use of x/? constant in case statement, (perhaps intended casex/casez) - 4'b1xxx: $stop; - ^~~~~~~ +%Warning-CASEWITHX: t/t_case_x_bad.v:19:9: Use of x/? constant in case statement, (perhaps intended casex/casez) + 19 | 4'b1xxx: $stop; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_case_x_bad.pl b/test_regress/t/t_case_x_bad.pl index 518625206..f3dd1d2a1 100755 --- a/test_regress/t/t_case_x_bad.pl +++ b/test_regress/t/t_case_x_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_case_x_bad.v b/test_regress/t/t_case_x_bad.v index b2662f7c7..f42265cc7 100644 --- a/test_regress/t/t_case_x_bad.v +++ b/test_regress/t/t_case_x_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_case_zx_bad.out b/test_regress/t/t_case_zx_bad.out index 81af2999e..ca591019c 100644 --- a/test_regress/t/t_case_zx_bad.out +++ b/test_regress/t/t_case_zx_bad.out @@ -1,5 +1,5 @@ -%Warning-CASEWITHX: t/t_case_zx_bad.v:15: Use of x constant in casez statement, (perhaps intended ?/z in constant) - 4'b1xxx: $stop; - ^~~~~~~ +%Warning-CASEWITHX: t/t_case_zx_bad.v:16:9: Use of x constant in casez statement, (perhaps intended ?/z in constant) + 16 | 4'b1xxx: $stop; + | ^~~~~~~ ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_case_zx_bad.pl b/test_regress/t/t_case_zx_bad.pl index 518625206..f3dd1d2a1 100755 --- a/test_regress/t/t_case_zx_bad.pl +++ b/test_regress/t/t_case_zx_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_case_zx_bad.v b/test_regress/t/t_case_zx_bad.v index 1ba42561b..a99363d78 100644 --- a/test_regress/t/t_case_zx_bad.v +++ b/test_regress/t/t_case_zx_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_cast.pl b/test_regress/t/t_cast.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_cast.pl +++ b/test_regress/t/t_cast.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v index b17a103ec..51ea9b240 100644 --- a/test_regress/t/t_cast.v +++ b/test_regress/t/t_cast.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_cdc_async_bad.out b/test_regress/t/t_cdc_async_bad.out index 68ee9cdf6..030217948 100644 --- a/test_regress/t/t_cdc_async_bad.out +++ b/test_regress/t/t_cdc_async_bad.out @@ -1,12 +1,12 @@ -%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:27: Logic in path that feeds async reset, via signal: 't.rst2_bad_n' - wire rst2_bad_n = rst0_n | rst1_n; - ^ +%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:28:21: Logic in path that feeds async reset, via signal: 't.rst2_bad_n' + 28 | wire rst2_bad_n = rst0_n | rst1_n; + | ^ ... Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message. %Warning-CDCRSTLOGIC: See details in obj_vlt/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt -%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:52: Logic in path that feeds async reset, via signal: 't.rst6a_bad_n' - wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); - ^ -%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53: Logic in path that feeds async reset, via signal: 't.rst6b_bad_n' - wire rst6b_bad_n = rst6_bad_n ^ $c1("1"); - ^ +%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53:21: Logic in path that feeds async reset, via signal: 't.rst6a_bad_n' + 53 | wire rst6a_bad_n = rst6_bad_n ^ $c1("0"); + | ^ +%Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:54:21: Logic in path that feeds async reset, via signal: 't.rst6b_bad_n' + 54 | wire rst6b_bad_n = rst6_bad_n ^ $c1("1"); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_cdc_async_bad.pl b/test_regress/t/t_cdc_async_bad.pl index f32bced18..86f83c981 100755 --- a/test_regress/t/t_cdc_async_bad.pl +++ b/test_regress/t/t_cdc_async_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_cdc_async_bad.v b/test_regress/t/t_cdc_async_bad.v index 679ffa81f..5a9dd3c9a 100644 --- a/test_regress/t/t_cdc_async_bad.v +++ b/test_regress/t/t_cdc_async_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_cellarray.pl b/test_regress/t/t_cellarray.pl index 090119722..f4e5d2f0a 100755 --- a/test_regress/t/t_cellarray.pl +++ b/test_regress/t/t_cellarray.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_cellarray.v b/test_regress/t/t_cellarray.v index 6789ec737..c7c6e32b9 100644 --- a/test_regress/t/t_cellarray.v +++ b/test_regress/t/t_cellarray.v @@ -2,7 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. -// +// SPDX-License-Identifier: CC0-1.0 // change these two parameters to see the speed differences `define DATA_WIDTH 8 diff --git a/test_regress/t/t_chg_first.pl b/test_regress/t/t_chg_first.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_chg_first.pl +++ b/test_regress/t/t_chg_first.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_chg_first.v b/test_regress/t/t_chg_first.v index c80ec339f..77015defd 100644 --- a/test_regress/t/t_chg_first.v +++ b/test_regress/t/t_chg_first.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_class_unsup_bad.out b/test_regress/t/t_class_unsup_bad.out index db3c6788c..1bc20487b 100644 --- a/test_regress/t/t_class_unsup_bad.out +++ b/test_regress/t/t_class_unsup_bad.out @@ -1,28 +1,28 @@ -%Error: t/t_class_unsup_bad.v:6: Unsupported: virtual interface -virtual interface vi_t vi; -^~~~~~~ -%Error: t/t_class_unsup_bad.v:7: Unsupported: virtual data type -virtual vi_t vi2; -^~~~~~~ -%Error: t/t_class_unsup_bad.v:12: Unsupported: classes -class C #(parameter P=1); -^~~~~ -%Error: t/t_class_unsup_bad.v:13: Unsupported: class parameters - localparam LOCPAR = 10; - ^ -%Error: t/t_class_unsup_bad.v:24: Unsupported: virtual class member qualifier - virtual function void func_virtual; endfunction - ^~~~~~~ -%Error: t/t_class_unsup_bad.v:25: Unsupported: pure virtual class method - pure virtual function void func_pure_virtual; endfunction - ^~~~ -%Error: t/t_class_unsup_bad.v:25: syntax error, unexpected endfunction - pure virtual function void func_pure_virtual; endfunction - ^~~~~~~~~~~ -%Error: t/t_class_unsup_bad.v:31: Unsupported: virtual classes -virtual class VC; -^~~~~~~ -%Error: t/t_class_unsup_bad.v:31: Unsupported: classes -virtual class VC; - ^~~~~ +%Error: t/t_class_unsup_bad.v:7:1: Unsupported: virtual interface + 7 | virtual interface vi_t vi; + | ^~~~~~~ +%Error: t/t_class_unsup_bad.v:8:1: Unsupported: virtual data type + 8 | virtual vi_t vi2; + | ^~~~~~~ +%Error: t/t_class_unsup_bad.v:13:1: Unsupported: classes + 13 | class C #(parameter P=1); + | ^~~~~ +%Error: t/t_class_unsup_bad.v:14:26: Unsupported: class parameters + 14 | localparam LOCPAR = 10; + | ^ +%Error: t/t_class_unsup_bad.v:25:4: Unsupported: virtual class member qualifier + 25 | virtual function void func_virtual; endfunction + | ^~~~~~~ +%Error: t/t_class_unsup_bad.v:26:4: Unsupported: pure virtual class method + 26 | pure virtual function void func_pure_virtual; endfunction + | ^~~~ +%Error: t/t_class_unsup_bad.v:26:50: syntax error, unexpected endfunction + 26 | pure virtual function void func_pure_virtual; endfunction + | ^~~~~~~~~~~ +%Error: t/t_class_unsup_bad.v:32:1: Unsupported: virtual classes + 32 | virtual class VC; + | ^~~~~~~ +%Error: t/t_class_unsup_bad.v:32:9: Unsupported: classes + 32 | virtual class VC; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_class_unsup_bad.pl b/test_regress/t/t_class_unsup_bad.pl index 49151b6cd..2365c113e 100755 --- a/test_regress/t/t_class_unsup_bad.pl +++ b/test_regress/t/t_class_unsup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_class_unsup_bad.v b/test_regress/t/t_class_unsup_bad.v index e509c5aa0..79546e2a7 100644 --- a/test_regress/t/t_class_unsup_bad.v +++ b/test_regress/t/t_class_unsup_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 virtual interface vi_t vi; virtual vi_t vi2; diff --git a/test_regress/t/t_clk_2in.cpp b/test_regress/t/t_clk_2in.cpp index 60d9c866e..a102ec98a 100644 --- a/test_regress/t/t_clk_2in.cpp +++ b/test_regress/t/t_clk_2in.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_clk_2in.pl b/test_regress/t/t_clk_2in.pl index 9189ff808..1ed3b6e8b 100755 --- a/test_regress/t/t_clk_2in.pl +++ b/test_regress/t/t_clk_2in.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_2in.v b/test_regress/t/t_clk_2in.v index 6298c7eaa..25bd369ae 100644 --- a/test_regress/t/t_clk_2in.v +++ b/test_regress/t/t_clk_2in.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `ifndef VERILATOR module t; diff --git a/test_regress/t/t_clk_2in_vec.pl b/test_regress/t/t_clk_2in_vec.pl index e39511b25..efc390c54 100755 --- a/test_regress/t/t_clk_2in_vec.pl +++ b/test_regress/t/t_clk_2in_vec.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_concat.pl b/test_regress/t/t_clk_concat.pl index fd7224cbf..2f675ed7b 100755 --- a/test_regress/t/t_clk_concat.pl +++ b/test_regress/t/t_clk_concat.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_concat.v b/test_regress/t/t_clk_concat.v index afb1d26b1..6ece8b5a3 100644 --- a/test_regress/t/t_clk_concat.v +++ b/test_regress/t/t_clk_concat.v @@ -2,7 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. -// +// SPDX-License-Identifier: CC0-1.0 module some_module ( input wrclk diff --git a/test_regress/t/t_clk_concat.vlt b/test_regress/t/t_clk_concat.vlt index c6af77881..f50d457be 100644 --- a/test_regress/t/t_clk_concat.vlt +++ b/test_regress/t/t_clk_concat.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_clk_concat2.pl b/test_regress/t/t_clk_concat2.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_clk_concat2.pl +++ b/test_regress/t/t_clk_concat2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_concat2.v b/test_regress/t/t_clk_concat2.v index 746b55ddb..5c0654268 100644 --- a/test_regress/t/t_clk_concat2.v +++ b/test_regress/t/t_clk_concat2.v @@ -2,7 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. -// +// SPDX-License-Identifier: CC0-1.0 module some_module ( input wrclk diff --git a/test_regress/t/t_clk_concat3.pl b/test_regress/t/t_clk_concat3.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_clk_concat3.pl +++ b/test_regress/t/t_clk_concat3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_concat3.v b/test_regress/t/t_clk_concat3.v index 37c164890..16d07f895 100644 --- a/test_regress/t/t_clk_concat3.v +++ b/test_regress/t/t_clk_concat3.v @@ -2,7 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. -// +// SPDX-License-Identifier: CC0-1.0 /* verilator lint_off LITENDIAN */ module some_module ( diff --git a/test_regress/t/t_clk_concat4.pl b/test_regress/t/t_clk_concat4.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_clk_concat4.pl +++ b/test_regress/t/t_clk_concat4.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_concat4.v b/test_regress/t/t_clk_concat4.v index ace301afd..9d811a406 100644 --- a/test_regress/t/t_clk_concat4.v +++ b/test_regress/t/t_clk_concat4.v @@ -2,7 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. -// +// SPDX-License-Identifier: CC0-1.0 module some_module ( input wrclk diff --git a/test_regress/t/t_clk_concat5.pl b/test_regress/t/t_clk_concat5.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_clk_concat5.pl +++ b/test_regress/t/t_clk_concat5.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_concat5.v b/test_regress/t/t_clk_concat5.v index 1c126e3b1..c6d4af8ae 100644 --- a/test_regress/t/t_clk_concat5.v +++ b/test_regress/t/t_clk_concat5.v @@ -2,7 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. -// +// SPDX-License-Identifier: CC0-1.0 module some_module ( input [3:0] i_clks diff --git a/test_regress/t/t_clk_concat6.pl b/test_regress/t/t_clk_concat6.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_clk_concat6.pl +++ b/test_regress/t/t_clk_concat6.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_concat6.v b/test_regress/t/t_clk_concat6.v index 49acb3d6f..61e1a07a8 100644 --- a/test_regress/t/t_clk_concat6.v +++ b/test_regress/t/t_clk_concat6.v @@ -2,7 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. -// +// SPDX-License-Identifier: CC0-1.0 module some_module ( input [3:0] i_clks diff --git a/test_regress/t/t_clk_concat_vlt.pl b/test_regress/t/t_clk_concat_vlt.pl index 8c882f901..815b1b4a4 100755 --- a/test_regress/t/t_clk_concat_vlt.pl +++ b/test_regress/t/t_clk_concat_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_condflop.pl b/test_regress/t/t_clk_condflop.pl index 48b77b922..bd78435f2 100755 --- a/test_regress/t/t_clk_condflop.pl +++ b/test_regress/t/t_clk_condflop.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_condflop.v b/test_regress/t/t_clk_condflop.v index 5554ecb07..7cc4e1b69 100644 --- a/test_regress/t/t_clk_condflop.v +++ b/test_regress/t/t_clk_condflop.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_clk_condflop_nord.pl b/test_regress/t/t_clk_condflop_nord.pl index 7835b7a30..09fdf4760 100755 --- a/test_regress/t/t_clk_condflop_nord.pl +++ b/test_regress/t/t_clk_condflop_nord.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_condflop_nord.v b/test_regress/t/t_clk_condflop_nord.v index 5554ecb07..7cc4e1b69 100644 --- a/test_regress/t/t_clk_condflop_nord.v +++ b/test_regress/t/t_clk_condflop_nord.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_clk_dpulse.pl b/test_regress/t/t_clk_dpulse.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_clk_dpulse.pl +++ b/test_regress/t/t_clk_dpulse.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_dpulse.v b/test_regress/t/t_clk_dpulse.v index 1fa080c76..0c7877790 100644 --- a/test_regress/t/t_clk_dpulse.v +++ b/test_regress/t/t_clk_dpulse.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_clk_dsp.pl b/test_regress/t/t_clk_dsp.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_clk_dsp.pl +++ b/test_regress/t/t_clk_dsp.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_dsp.v b/test_regress/t/t_clk_dsp.v index 991b9754e..9572c35e6 100644 --- a/test_regress/t/t_clk_dsp.v +++ b/test_regress/t/t_clk_dsp.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_clk_first.pl b/test_regress/t/t_clk_first.pl index 91433482b..89850c37d 100755 --- a/test_regress/t/t_clk_first.pl +++ b/test_regress/t/t_clk_first.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_first.v b/test_regress/t/t_clk_first.v index 52cf01582..84b6f050b 100644 --- a/test_regress/t/t_clk_first.v +++ b/test_regress/t/t_clk_first.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_clk_first_bad.out b/test_regress/t/t_clk_first_bad.out index 2e9e41bf1..a640ff6c4 100644 --- a/test_regress/t/t_clk_first_bad.out +++ b/test_regress/t/t_clk_first_bad.out @@ -1,5 +1,5 @@ -%Warning-DEPRECATED: t/t_clk_first_deprecated.v:11: sc_clock is deprecated and will be removed - input clk /*verilator sc_clock*/ ; - ^~~~~~~~~~~~~~~~~~~~~~ +%Warning-DEPRECATED: t/t_clk_first_deprecated.v:12:14: sc_clock is deprecated and will be removed + 12 | input clk /*verilator sc_clock*/ ; + | ^~~~~~~~~~~~~~~~~~~~~~ ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_clk_first_bad.pl b/test_regress/t/t_clk_first_bad.pl index 3f7b54038..823cd4300 100755 --- a/test_regress/t/t_clk_first_bad.pl +++ b/test_regress/t/t_clk_first_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_clk_first_deprecated.pl b/test_regress/t/t_clk_first_deprecated.pl index 01d7bf8d0..4d96fac7d 100755 --- a/test_regress/t/t_clk_first_deprecated.pl +++ b/test_regress/t/t_clk_first_deprecated.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_clk_first_deprecated.v b/test_regress/t/t_clk_first_deprecated.v index 5c5f5ce12..5bf460c19 100644 --- a/test_regress/t/t_clk_first_deprecated.v +++ b/test_regress/t/t_clk_first_deprecated.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_clk_gater.pl b/test_regress/t/t_clk_gater.pl index 5884aa99e..5bba9e07e 100755 --- a/test_regress/t/t_clk_gater.pl +++ b/test_regress/t/t_clk_gater.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_gater.v b/test_regress/t/t_clk_gater.v index 4a8bdfe88..b676228ae 100644 --- a/test_regress/t/t_clk_gater.v +++ b/test_regress/t/t_clk_gater.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_clk_gen.pl b/test_regress/t/t_clk_gen.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_clk_gen.pl +++ b/test_regress/t/t_clk_gen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_gen.v b/test_regress/t/t_clk_gen.v index 8042d287f..9a07b7150 100644 --- a/test_regress/t/t_clk_gen.v +++ b/test_regress/t/t_clk_gen.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_clk_inp_init.cpp b/test_regress/t/t_clk_inp_init.cpp index 90e64a755..08fdd1118 100644 --- a/test_regress/t/t_clk_inp_init.cpp +++ b/test_regress/t/t_clk_inp_init.cpp @@ -1,3 +1,7 @@ +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + // Test defines // Generated header #include "Vt_clk_inp_init.h" diff --git a/test_regress/t/t_clk_inp_init.pl b/test_regress/t/t_clk_inp_init.pl index a752bc243..b2191a176 100755 --- a/test_regress/t/t_clk_inp_init.pl +++ b/test_regress/t/t_clk_inp_init.pl @@ -6,6 +6,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # can redistribute it and/or modify it under the terms of either the # GNU Lesser General Public License Version 3 or the Perl Artistic # License Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_inp_init.v b/test_regress/t/t_clk_inp_init.v index d9f7b9726..e9399c661 100644 --- a/test_regress/t/t_clk_inp_init.v +++ b/test_regress/t/t_clk_inp_init.v @@ -5,7 +5,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Rupert Swarbrick (Argon Design). - +// SPDX-License-Identifier: CC0-1.0 // bug1327 // This models some device under test with an asynchronous reset pin diff --git a/test_regress/t/t_clk_latch.pl b/test_regress/t/t_clk_latch.pl index 1bb3331e9..a8a66f6ba 100755 --- a/test_regress/t/t_clk_latch.pl +++ b/test_regress/t/t_clk_latch.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_latch.v b/test_regress/t/t_clk_latch.v index 18ec5fe72..7fc4e96ea 100644 --- a/test_regress/t/t_clk_latch.v +++ b/test_regress/t/t_clk_latch.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_clk_latch_edgestyle.pl b/test_regress/t/t_clk_latch_edgestyle.pl index e80218e13..ad463440f 100755 --- a/test_regress/t/t_clk_latch_edgestyle.pl +++ b/test_regress/t/t_clk_latch_edgestyle.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_latchgate.pl b/test_regress/t/t_clk_latchgate.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_clk_latchgate.pl +++ b/test_regress/t/t_clk_latchgate.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_latchgate.v b/test_regress/t/t_clk_latchgate.v index 1e3503ff5..bf43d7c06 100644 --- a/test_regress/t/t_clk_latchgate.v +++ b/test_regress/t/t_clk_latchgate.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // // -------------------------------------------------------- // Bug Description: diff --git a/test_regress/t/t_clk_powerdn.pl b/test_regress/t/t_clk_powerdn.pl index 48b77b922..bd78435f2 100755 --- a/test_regress/t/t_clk_powerdn.pl +++ b/test_regress/t/t_clk_powerdn.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_powerdn.v b/test_regress/t/t_clk_powerdn.v index 039bcb093..55173b573 100644 --- a/test_regress/t/t_clk_powerdn.v +++ b/test_regress/t/t_clk_powerdn.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_clk_scope_bad.out b/test_regress/t/t_clk_scope_bad.out index 8475842e0..bec10941c 100644 --- a/test_regress/t/t_clk_scope_bad.out +++ b/test_regress/t/t_clk_scope_bad.out @@ -1,6 +1,6 @@ -%Warning-CLKDATA: t/t_clk_scope_bad.v:35: Clock used as data (on rhs of assignment) in sequential block 'clk' - : ... In instance t.p2 - q <= d; - ^ +%Warning-CLKDATA: t/t_clk_scope_bad.v:36:12: Clock used as data (on rhs of assignment) in sequential block 'clk' + : ... In instance t.p2 + 36 | q <= d; + | ^ ... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_clk_scope_bad.pl b/test_regress/t/t_clk_scope_bad.pl index 518625206..f3dd1d2a1 100755 --- a/test_regress/t/t_clk_scope_bad.pl +++ b/test_regress/t/t_clk_scope_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_clk_scope_bad.v b/test_regress/t/t_clk_scope_bad.v index 0812d497a..08b480ee5 100644 --- a/test_regress/t/t_clk_scope_bad.v +++ b/test_regress/t/t_clk_scope_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_clk_vecgen1.pl b/test_regress/t/t_clk_vecgen1.pl index 2605f221a..90908ae96 100755 --- a/test_regress/t/t_clk_vecgen1.pl +++ b/test_regress/t/t_clk_vecgen1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_vecgen1.v b/test_regress/t/t_clk_vecgen1.v index 089fee0da..fd4cd4bad 100644 --- a/test_regress/t/t_clk_vecgen1.v +++ b/test_regress/t/t_clk_vecgen1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_clk_vecgen2.pl b/test_regress/t/t_clk_vecgen2.pl index fce42e49d..920605c09 100755 --- a/test_regress/t/t_clk_vecgen2.pl +++ b/test_regress/t/t_clk_vecgen2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clk_vecgen3.pl b/test_regress/t/t_clk_vecgen3.pl index 4cb74b187..ee3dda24e 100755 --- a/test_regress/t/t_clk_vecgen3.pl +++ b/test_regress/t/t_clk_vecgen3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clocker.pl b/test_regress/t/t_clocker.pl index cb64dcc32..6a31da87a 100755 --- a/test_regress/t/t_clocker.pl +++ b/test_regress/t/t_clocker.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_clocker.v b/test_regress/t/t_clocker.v index a29c1ff0b..7a4bdca32 100644 --- a/test_regress/t/t_clocker.v +++ b/test_regress/t/t_clocker.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; diff --git a/test_regress/t/t_concat_large.pl b/test_regress/t/t_concat_large.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_concat_large.pl +++ b/test_regress/t/t_concat_large.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_concat_large.v b/test_regress/t/t_concat_large.v index 5e52ce2af..e01f9992d 100644 --- a/test_regress/t/t_concat_large.v +++ b/test_regress/t/t_concat_large.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_concat_large_bad.out b/test_regress/t/t_concat_large_bad.out index da21041ac..a4afc3552 100644 --- a/test_regress/t/t_concat_large_bad.out +++ b/test_regress/t/t_concat_large_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:8: More than a 8k bit replication is probably wrong: 32768 - : ... In instance t - wire [32767:0] a = {32768{1'b1}}; - ^ +%Warning-WIDTHCONCAT: t/t_concat_large_bad.v:9:29: More than a 8k bit replication is probably wrong: 32768 + : ... In instance t + 9 | wire [32767:0] a = {32768{1'b1}}; + | ^ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_concat_large_bad.pl b/test_regress/t/t_concat_large_bad.pl index b27cd2241..fad9da3fe 100755 --- a/test_regress/t/t_concat_large_bad.pl +++ b/test_regress/t/t_concat_large_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_concat_large_bad.v b/test_regress/t/t_concat_large_bad.v index 7f966fa32..05f19cbcd 100644 --- a/test_regress/t/t_concat_large_bad.v +++ b/test_regress/t/t_concat_large_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_concat_link_bad.out b/test_regress/t/t_concat_link_bad.out index 8324eb8cc..6760aa004 100644 --- a/test_regress/t/t_concat_link_bad.out +++ b/test_regress/t/t_concat_link_bad.out @@ -1,14 +1,14 @@ -%Error: t/t_concat_link_bad.v:24: Syntax Error: Not expecting REPLICATE under a DOT in dotted expression - assign bar_s = {foo_s, foo_s}.f1; - ^ -%Error: t/t_concat_link_bad.v:24: Syntax Error: Not expecting CONCAT under a REPLICATE in dotted expression - assign bar_s = {foo_s, foo_s}.f1; - ^ -%Error: t/t_concat_link_bad.v:24: Syntax Error: Not expecting CONST under a REPLICATE in dotted expression - assign bar_s = {foo_s, foo_s}.f1; - ^ -%Warning-IMPLICIT: t/t_concat_link_bad.v:24: Signal definition not found, creating implicitly: 'bar_s' - assign bar_s = {foo_s, foo_s}.f1; - ^~~~~ +%Error: t/t_concat_link_bad.v:13:20: Syntax Error: Not expecting REPLICATE under a DOT in dotted expression + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ +%Error: t/t_concat_link_bad.v:13:26: Syntax Error: Not expecting CONCAT under a REPLICATE in dotted expression + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ +%Error: t/t_concat_link_bad.v:13:20: Syntax Error: Not expecting CONST under a REPLICATE in dotted expression + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^ +%Warning-IMPLICIT: t/t_concat_link_bad.v:13:12: Signal definition not found, creating implicitly: 'bar_s' + 13 | assign bar_s = {foo_s, foo_s}.f1; + | ^~~~~ ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_concat_link_bad.pl b/test_regress/t/t_concat_link_bad.pl index 4689d6999..e2ea28d29 100755 --- a/test_regress/t/t_concat_link_bad.pl +++ b/test_regress/t/t_concat_link_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_concat_link_bad.v b/test_regress/t/t_concat_link_bad.v index c038f38e3..8b0d87ab7 100644 --- a/test_regress/t/t_concat_link_bad.v +++ b/test_regress/t/t_concat_link_bad.v @@ -1,19 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Use this file as a template for submitting bugs, etc. -// This module takes a single clock input, and should either -// $write("*-* All Finished *-*\n"); -// $finish; -// on success, or $stop. -// -// The code as shown applies a random vector to the Test -// module, then calculates a CRC on the Test module's outputs. -// -// **If you do not wish for your code to be released to the public -// please note it here, otherwise:** -// // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by ____YOUR_NAME_HERE____. +// without warranty, 2019. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_concat_opt.pl b/test_regress/t/t_concat_opt.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_concat_opt.pl +++ b/test_regress/t/t_concat_opt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_concat_opt.v b/test_regress/t/t_concat_opt.v index 3eed6fafe..ae3014280 100644 --- a/test_regress/t/t_concat_opt.v +++ b/test_regress/t/t_concat_opt.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2004 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 // // The test was added together with the concat optimization. diff --git a/test_regress/t/t_const.pl b/test_regress/t/t_const.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_const.pl +++ b/test_regress/t/t_const.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_const.v b/test_regress/t/t_const.v index 22a5c0b25..43fa122f7 100644 --- a/test_regress/t/t_const.v +++ b/test_regress/t/t_const.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); diff --git a/test_regress/t/t_const_bad.out b/test_regress/t/t_const_bad.out index 3ad667c4e..6594d207b 100644 --- a/test_regress/t/t_const_bad.out +++ b/test_regress/t/t_const_bad.out @@ -1,14 +1,14 @@ -%Warning-WIDTH: t/t_const_bad.v:12: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx - : ... In instance t - if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; - ^~~ +%Warning-WIDTH: t/t_const_bad.v:13:39: Unsized constant being X/Z extended to 68 bits: ?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + : ... In instance t + 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; + | ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_const_bad.v:13: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz - : ... In instance t - if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; - ^~~ -%Warning-WIDTH: t/t_const_bad.v:14: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz - : ... In instance t - if (68'h?_????????_???????? !== 'd?) $stop; - ^~~ +%Warning-WIDTH: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz + : ... In instance t + 14 | if (68'hz_zzzzzzzz_zzzzzzzz !== 'dZ) $stop; + | ^~~ +%Warning-WIDTH: t/t_const_bad.v:15:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz + : ... In instance t + 15 | if (68'h?_????????_???????? !== 'd?) $stop; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_bad.pl b/test_regress/t/t_const_bad.pl index b27cd2241..fad9da3fe 100755 --- a/test_regress/t/t_const_bad.pl +++ b/test_regress/t/t_const_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_const_bad.v b/test_regress/t/t_const_bad.v index 66513d66d..c1edeaf2c 100644 --- a/test_regress/t/t_const_bad.v +++ b/test_regress/t/t_const_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); diff --git a/test_regress/t/t_const_dec_mixed_bad.out b/test_regress/t/t_const_dec_mixed_bad.out index e7f12a4f9..eac803545 100644 --- a/test_regress/t/t_const_dec_mixed_bad.out +++ b/test_regress/t/t_const_dec_mixed_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_const_dec_mixed_bad.v:8: Mixing X/Z/? with digits not legal in decimal constant: x_1 - parameter [200:0] MIXED = 32'dx_1; - ^~~~~~~ +%Error: t/t_const_dec_mixed_bad.v:9:30: Mixing X/Z/? with digits not legal in decimal constant: x_1 + 9 | parameter [200:0] MIXED = 32'dx_1; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_dec_mixed_bad.pl b/test_regress/t/t_const_dec_mixed_bad.pl index 518625206..f3dd1d2a1 100755 --- a/test_regress/t/t_const_dec_mixed_bad.pl +++ b/test_regress/t/t_const_dec_mixed_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_const_dec_mixed_bad.v b/test_regress/t/t_const_dec_mixed_bad.v index 5fc3d0317..d9a6d4780 100644 --- a/test_regress/t/t_const_dec_mixed_bad.v +++ b/test_regress/t/t_const_dec_mixed_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_const_overflow_bad.out b/test_regress/t/t_const_overflow_bad.out index 81de441e9..641cd071d 100644 --- a/test_regress/t/t_const_overflow_bad.out +++ b/test_regress/t/t_const_overflow_bad.out @@ -1,16 +1,16 @@ -%Error: t/t_const_overflow_bad.v:8: Too many digits for 94 bit number: 94'd123456789012345678901234567890 - parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; - ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_const_overflow_bad.v:10: Too many digits for 8 bit number: 8'habc - parameter [200:0] SMALLH = 8'habc; - ^~~~~~ -%Error: t/t_const_overflow_bad.v:11: Too many digits for 6 bit number: 6'o1234 - parameter [200:0] SMALLO = 6'o1234; - ^~~~~~~ -%Error: t/t_const_overflow_bad.v:12: Too many digits for 3 bit number: 3'b1111 - parameter [200:0] SMALLB = 3'b1111; - ^~~~~~~ -%Error: t/t_const_overflow_bad.v:18: Too many digits for 129 bit number: 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d - parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; - ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_const_overflow_bad.v:9:34: Too many digits for 94 bit number: 94'd123456789012345678901234567890 + 9 | parameter [200:0] TOO_SMALL = 94'd123456789012345678901234567890; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_const_overflow_bad.v:11:31: Too many digits for 8 bit number: 8'habc + 11 | parameter [200:0] SMALLH = 8'habc; + | ^~~~~~ +%Error: t/t_const_overflow_bad.v:12:31: Too many digits for 6 bit number: 6'o1234 + 12 | parameter [200:0] SMALLO = 6'o1234; + | ^~~~~~~ +%Error: t/t_const_overflow_bad.v:13:31: Too many digits for 3 bit number: 3'b1111 + 13 | parameter [200:0] SMALLB = 3'b1111; + | ^~~~~~~ +%Error: t/t_const_overflow_bad.v:19:35: Too many digits for 129 bit number: 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d + 19 | parameter [128:0] ALSO_SMALL = 129'hdeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00ddeadbeefc001f00d; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_const_overflow_bad.pl b/test_regress/t/t_const_overflow_bad.pl index 518625206..f3dd1d2a1 100755 --- a/test_regress/t/t_const_overflow_bad.pl +++ b/test_regress/t/t_const_overflow_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_const_overflow_bad.v b/test_regress/t/t_const_overflow_bad.v index 2cb28a8a1..0217fa4f2 100644 --- a/test_regress/t/t_const_overflow_bad.v +++ b/test_regress/t/t_const_overflow_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_cover_line.out b/test_regress/t/t_cover_line.out index 3071c13a7..567dd70ca 100644 --- a/test_regress/t/t_cover_line.out +++ b/test_regress/t/t_cover_line.out @@ -1,8 +1,9 @@ // verilator_coverage annotation // DESCRIPTION: Verilator: Verilog Test module // - // This file ONLY is placed into the Public Domain, for any use, - // without warranty, 2008 by Wilson Snyder. + // This file ONLY is placed under the Creative Commons Public Domain, for + // any use, without warranty, 2008 by Wilson Snyder. + // SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_cover_line.v b/test_regress/t/t_cover_line.v index 9c633a5dd..887c02c14 100644 --- a/test_regress/t/t_cover_line.v +++ b/test_regress/t/t_cover_line.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_cover_line.vlt b/test_regress/t/t_cover_line.vlt index 2018150fb..898f27d9c 100644 --- a/test_regress/t/t_cover_line.vlt +++ b/test_regress/t/t_cover_line.vlt @@ -2,8 +2,9 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config -coverage_block_off -file "t/t_cover_line.v" -lines 82 +coverage_block_off -file "t/t_cover_line.v" -lines 83 coverage_block_off -module "beta" -block "block" diff --git a/test_regress/t/t_cover_line_cc.pl b/test_regress/t/t_cover_line_cc.pl index 560dc831d..a583cabb2 100755 --- a/test_regress/t/t_cover_line_cc.pl +++ b/test_regress/t/t_cover_line_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_cover_line_cc_vlt.pl b/test_regress/t/t_cover_line_cc_vlt.pl index c2201d7b4..0d9234f4a 100755 --- a/test_regress/t/t_cover_line_cc_vlt.pl +++ b/test_regress/t/t_cover_line_cc_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_cover_line_sc.pl b/test_regress/t/t_cover_line_sc.pl index fbe062a41..e22105fb5 100755 --- a/test_regress/t/t_cover_line_sc.pl +++ b/test_regress/t/t_cover_line_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_cover_line_trace.out b/test_regress/t/t_cover_line_trace.out index e1fbd2120..67983b6bd 100644 --- a/test_regress/t/t_cover_line_trace.out +++ b/test_regress/t/t_cover_line_trace.out @@ -1,5 +1,5 @@ $version Generated by VerilatedVcd $end -$date Sun Dec 29 13:11:10 2019 +$date Thu Mar 19 18:37:02 2020 $end $timescale 1ns $end @@ -10,42 +10,42 @@ $timescale 1ns $end $var wire 32 + cyc [31:0] $end $var wire 8 3 cyc_copy [7:0] $end $var wire 1 # toggle $end - $var wire 32 S vlCoverageLineTrace_t_cover_line__44_if [31:0] $end - $var wire 32 ; vlCoverageLineTrace_t_cover_line__47_if [31:0] $end - $var wire 32 C vlCoverageLineTrace_t_cover_line__50_elsif [31:0] $end - $var wire 32 K vlCoverageLineTrace_t_cover_line__57_elsif [31:0] $end + $var wire 32 S vlCoverageLineTrace_t_cover_line__45_if [31:0] $end + $var wire 32 ; vlCoverageLineTrace_t_cover_line__48_if [31:0] $end + $var wire 32 C vlCoverageLineTrace_t_cover_line__51_elsif [31:0] $end + $var wire 32 K vlCoverageLineTrace_t_cover_line__58_elsif [31:0] $end $scope module a1 $end $var wire 1 5! clk $end $var wire 1 # toggle $end - $var wire 32 [ vlCoverageLineTrace_t_cover_line__78_if [31:0] $end + $var wire 32 [ vlCoverageLineTrace_t_cover_line__79_if [31:0] $end $upscope $end $scope module a2 $end $var wire 1 5! clk $end $var wire 1 # toggle $end - $var wire 32 c vlCoverageLineTrace_t_cover_line__78_if [31:0] $end + $var wire 32 c vlCoverageLineTrace_t_cover_line__79_if [31:0] $end $upscope $end $scope module b1 $end $var wire 1 5! clk $end $var wire 1 # toggle $end - $var wire 32 =! vlCoverageLineTrace_t_cover_line__103_if [31:0] $end - $var wire 32 s vlCoverageLineTrace_t_cover_line__107_if [31:0] $end + $var wire 32 =! vlCoverageLineTrace_t_cover_line__104_if [31:0] $end + $var wire 32 s vlCoverageLineTrace_t_cover_line__108_if [31:0] $end $upscope $end $scope module b2 $end $var wire 1 5! clk $end $var wire 1 # toggle $end - $var wire 32 E! vlCoverageLineTrace_t_cover_line__103_if [31:0] $end - $var wire 32 { vlCoverageLineTrace_t_cover_line__107_if [31:0] $end + $var wire 32 E! vlCoverageLineTrace_t_cover_line__104_if [31:0] $end + $var wire 32 { vlCoverageLineTrace_t_cover_line__108_if [31:0] $end $upscope $end $scope module o1 $end $var wire 1 5! clk $end $var wire 1 # toggle $end - $var wire 32 k vlCoverageLineTrace_t_cover_line__166_if [31:0] $end + $var wire 32 k vlCoverageLineTrace_t_cover_line__167_if [31:0] $end $upscope $end $scope module t1 $end $var wire 1 5! clk $end $var wire 1 # toggle $end - $var wire 32 %! vlCoverageLineTrace_t_cover_line__138_if [31:0] $end - $var wire 32 -! vlCoverageLineTrace_t_cover_line__141_if [31:0] $end + $var wire 32 %! vlCoverageLineTrace_t_cover_line__139_if [31:0] $end + $var wire 32 -! vlCoverageLineTrace_t_cover_line__142_if [31:0] $end $upscope $end $upscope $end $upscope $end diff --git a/test_regress/t/t_cover_line_trace.pl b/test_regress/t/t_cover_line_trace.pl index 0b6b4e958..06b2e755b 100755 --- a/test_regress/t/t_cover_line_trace.pl +++ b/test_regress/t/t_cover_line_trace.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_cover_sva_notflat.pl b/test_regress/t/t_cover_sva_notflat.pl index f929e7b9f..25cb59609 100755 --- a/test_regress/t/t_cover_sva_notflat.pl +++ b/test_regress/t/t_cover_sva_notflat.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_cover_sva_notflat.v b/test_regress/t/t_cover_sva_notflat.v index 59f920723..cc55c400e 100644 --- a/test_regress/t/t_cover_sva_notflat.v +++ b/test_regress/t/t_cover_sva_notflat.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_cover_sva_trace.pl b/test_regress/t/t_cover_sva_trace.pl index 6a50d7191..9125fabc2 100755 --- a/test_regress/t/t_cover_sva_trace.pl +++ b/test_regress/t/t_cover_sva_trace.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_cover_toggle.pl b/test_regress/t/t_cover_toggle.pl index db0a9e832..2bbb41827 100755 --- a/test_regress/t/t_cover_toggle.pl +++ b/test_regress/t/t_cover_toggle.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_cover_toggle.v b/test_regress/t/t_cover_toggle.v index e1979e639..e069a3382 100644 --- a/test_regress/t/t_cover_toggle.v +++ b/test_regress/t/t_cover_toggle.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_crazy_sel.pl b/test_regress/t/t_crazy_sel.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_crazy_sel.pl +++ b/test_regress/t/t_crazy_sel.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_crazy_sel.v b/test_regress/t/t_crazy_sel.v index 985978c31..a39637524 100644 --- a/test_regress/t/t_crazy_sel.v +++ b/test_regress/t/t_crazy_sel.v @@ -3,6 +3,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; diff --git a/test_regress/t/t_debug_fatalsrc_bad.pl b/test_regress/t/t_debug_fatalsrc_bad.pl index 3aaa74e5a..9acad386f 100755 --- a/test_regress/t/t_debug_fatalsrc_bad.pl +++ b/test_regress/t/t_debug_fatalsrc_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_debug_fatalsrc_bt_bad.pl b/test_regress/t/t_debug_fatalsrc_bt_bad.pl index 41ed2c8af..9a9d2071b 100755 --- a/test_regress/t/t_debug_fatalsrc_bt_bad.pl +++ b/test_regress/t/t_debug_fatalsrc_bt_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB"); diff --git a/test_regress/t/t_debug_sigsegv_bad.pl b/test_regress/t/t_debug_sigsegv_bad.pl index 04deb7b58..691631fe4 100755 --- a/test_regress/t/t_debug_sigsegv_bad.pl +++ b/test_regress/t/t_debug_sigsegv_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB"); diff --git a/test_regress/t/t_debug_sigsegv_bt_bad.pl b/test_regress/t/t_debug_sigsegv_bt_bad.pl index f12a27ece..65557c355 100755 --- a/test_regress/t/t_debug_sigsegv_bt_bad.pl +++ b/test_regress/t/t_debug_sigsegv_bt_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB"); diff --git a/test_regress/t/t_dedupe_clk_gate.pl b/test_regress/t/t_dedupe_clk_gate.pl index 85b870fb2..ecacecec3 100755 --- a/test_regress/t/t_dedupe_clk_gate.pl +++ b/test_regress/t/t_dedupe_clk_gate.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -16,7 +17,7 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); file_grep($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 4); } diff --git a/test_regress/t/t_dedupe_clk_gate.v b/test_regress/t/t_dedupe_clk_gate.v index 75196346a..1cfcec315 100644 --- a/test_regress/t/t_dedupe_clk_gate.v +++ b/test_regress/t/t_dedupe_clk_gate.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Varun Koyyalagunta, Centaur Technology. diff --git a/test_regress/t/t_dedupe_seq_logic.pl b/test_regress/t/t_dedupe_seq_logic.pl index 0a9c0f040..0601df48c 100755 --- a/test_regress/t/t_dedupe_seq_logic.pl +++ b/test_regress/t/t_dedupe_seq_logic.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dedupe_seq_logic.v b/test_regress/t/t_dedupe_seq_logic.v index 82025b924..e9a03f3f8 100644 --- a/test_regress/t/t_dedupe_seq_logic.v +++ b/test_regress/t/t_dedupe_seq_logic.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by Varun Koyyalagunta, Centaur Technology. // diff --git a/test_regress/t/t_delay.pl b/test_regress/t/t_delay.pl index c56a826e8..6111d84c6 100755 --- a/test_regress/t/t_delay.pl +++ b/test_regress/t/t_delay.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_delay.v b/test_regress/t/t_delay.v index 3b41e419c..2c1d2d9c6 100644 --- a/test_regress/t/t_delay.v +++ b/test_regress/t/t_delay.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_delay_stmtdly_bad.out b/test_regress/t/t_delay_stmtdly_bad.out index 12cd1077f..5e1f99423 100644 --- a/test_regress/t/t_delay_stmtdly_bad.out +++ b/test_regress/t/t_delay_stmtdly_bad.out @@ -1,14 +1,14 @@ -%Warning-ASSIGNDLY: t/t_delay.v:19: Unsupported: Ignoring delay on this assignment/primitive. - assign #(1.2000000000000000) dly1 = dly0 + 32'h1; - ^ +%Warning-ASSIGNDLY: t/t_delay.v:20:11: Unsupported: Ignoring delay on this assignment/primitive. + 20 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1; + | ^ ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message. -%Warning-ASSIGNDLY: t/t_delay.v:24: Unsupported: Ignoring delay on this assignment/primitive. - dly0 <= #0 32'h11; - ^ -%Warning-ASSIGNDLY: t/t_delay.v:27: Unsupported: Ignoring delay on this assignment/primitive. - dly0 <= #0.12 dly0 + 32'h12; - ^ -%Warning-STMTDLY: t/t_delay.v:33: Unsupported: Ignoring delay on this delayed statement. - #100 $finish; - ^ +%Warning-ASSIGNDLY: t/t_delay.v:25:18: Unsupported: Ignoring delay on this assignment/primitive. + 25 | dly0 <= #0 32'h11; + | ^ +%Warning-ASSIGNDLY: t/t_delay.v:28:18: Unsupported: Ignoring delay on this assignment/primitive. + 28 | dly0 <= #0.12 dly0 + 32'h12; + | ^ +%Warning-STMTDLY: t/t_delay.v:34:10: Unsupported: Ignoring delay on this delayed statement. + 34 | #100 $finish; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_delay_stmtdly_bad.pl b/test_regress/t/t_delay_stmtdly_bad.pl index 3de95217c..1d17ceca2 100755 --- a/test_regress/t/t_delay_stmtdly_bad.pl +++ b/test_regress/t/t_delay_stmtdly_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_detectarray_1.pl b/test_regress/t/t_detectarray_1.pl index 97d65733b..178edc13d 100755 --- a/test_regress/t/t_detectarray_1.pl +++ b/test_regress/t/t_detectarray_1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_detectarray_1.v b/test_regress/t/t_detectarray_1.v index 73834ea89..15f72f77c 100644 --- a/test_regress/t/t_detectarray_1.v +++ b/test_regress/t/t_detectarray_1.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; diff --git a/test_regress/t/t_detectarray_2.pl b/test_regress/t/t_detectarray_2.pl index 97d65733b..178edc13d 100755 --- a/test_regress/t/t_detectarray_2.pl +++ b/test_regress/t/t_detectarray_2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_detectarray_2.v b/test_regress/t/t_detectarray_2.v index 77eb06189..f6da72827 100644 --- a/test_regress/t/t_detectarray_2.v +++ b/test_regress/t/t_detectarray_2.v @@ -6,6 +6,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; diff --git a/test_regress/t/t_detectarray_3.pl b/test_regress/t/t_detectarray_3.pl index 4fd888569..dbb7b20c5 100755 --- a/test_regress/t/t_detectarray_3.pl +++ b/test_regress/t/t_detectarray_3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_detectarray_3.v b/test_regress/t/t_detectarray_3.v index 932bebb89..f83bf384d 100644 --- a/test_regress/t/t_detectarray_3.v +++ b/test_regress/t/t_detectarray_3.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 localparam ID_MSB = 1; diff --git a/test_regress/t/t_display.pl b/test_regress/t/t_display.pl index e7b4fce25..2934909ea 100755 --- a/test_regress/t/t_display.pl +++ b/test_regress/t/t_display.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display.v b/test_regress/t/t_display.v index 12bc6db5f..cfdeea257 100644 --- a/test_regress/t/t_display.v +++ b/test_regress/t/t_display.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; reg [40:0] quad; initial quad = 41'ha_bbbb_cccc; @@ -170,7 +171,9 @@ multiline", $time); $write("'%-8s'\n", "beep"); // $itord conversion bug, note a %d instead of proper float + // verilator lint_off REALCVT $display("log10(2) = %d", $log10(100)); + // verilator lint_on REALCVT $write("*-* All Finished *-*\n"); $finish; diff --git a/test_regress/t/t_display_bad.out b/test_regress/t/t_display_bad.out index 61ed03584..615589bd4 100644 --- a/test_regress/t/t_display_bad.out +++ b/test_regress/t/t_display_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_display_bad.v:10: Missing arguments for $display-like format - $display("%x"); - ^~~~~~~~ -%Error: t/t_display_bad.v:12: Unknown $display-like format code: '%q' - $display("%q"); - ^~~~~~~~ +%Error: t/t_display_bad.v:11:7: Missing arguments for $display-like format + 11 | $display("%x"); + | ^~~~~~~~ +%Error: t/t_display_bad.v:13:7: Unknown $display-like format code: '%q' + 13 | $display("%q"); + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_display_bad.pl b/test_regress/t/t_display_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_display_bad.pl +++ b/test_regress/t/t_display_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_display_bad.v b/test_regress/t/t_display_bad.v index fda28df89..4bf715f80 100644 --- a/test_regress/t/t_display_bad.v +++ b/test_regress/t/t_display_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; reg [40:0] disp; initial disp = 41'ha_bbbb_cccc; diff --git a/test_regress/t/t_display_esc_bad.out b/test_regress/t/t_display_esc_bad.out index 504024a19..a2c68c232 100644 --- a/test_regress/t/t_display_esc_bad.out +++ b/test_regress/t/t_display_esc_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_display_esc_bad.v:8: Unknown escape sequence: \x - $display("\x\y\z"); - ^~~~~~~~ +%Error: t/t_display_esc_bad.v:9:16: Unknown escape sequence: \x + 9 | $display("\x\y\z"); + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_display_esc_bad.pl b/test_regress/t/t_display_esc_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_display_esc_bad.pl +++ b/test_regress/t/t_display_esc_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_display_esc_bad.v b/test_regress/t/t_display_esc_bad.v index ec0b008eb..fbce610e4 100644 --- a/test_regress/t/t_display_esc_bad.v +++ b/test_regress/t/t_display_esc_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; initial begin diff --git a/test_regress/t/t_display_l.pl b/test_regress/t/t_display_l.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_display_l.pl +++ b/test_regress/t/t_display_l.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_l.v b/test_regress/t/t_display_l.v index c299f67cc..5bf917591 100644 --- a/test_regress/t/t_display_l.v +++ b/test_regress/t/t_display_l.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_display_mcd.pl b/test_regress/t/t_display_mcd.pl index e7b4fce25..2934909ea 100755 --- a/test_regress/t/t_display_mcd.pl +++ b/test_regress/t/t_display_mcd.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_mcd.v b/test_regress/t/t_display_mcd.v index db3c3e143..b56bacc46 100644 --- a/test_regress/t/t_display_mcd.v +++ b/test_regress/t/t_display_mcd.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; initial begin diff --git a/test_regress/t/t_display_merge.pl b/test_regress/t/t_display_merge.pl index 5ceeb966f..940d1ea85 100755 --- a/test_regress/t/t_display_merge.pl +++ b/test_regress/t/t_display_merge.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_merge.v b/test_regress/t/t_display_merge.v index c8e83b1d1..cdf8ea8cc 100644 --- a/test_regress/t/t_display_merge.v +++ b/test_regress/t/t_display_merge.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); initial begin diff --git a/test_regress/t/t_display_noopt.pl b/test_regress/t/t_display_noopt.pl index 0912cc664..836ade5ab 100755 --- a/test_regress/t/t_display_noopt.pl +++ b/test_regress/t/t_display_noopt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_real.pl b/test_regress/t/t_display_real.pl index f79178f86..b4e259e0a 100755 --- a/test_regress/t/t_display_real.pl +++ b/test_regress/t/t_display_real.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_real.v b/test_regress/t/t_display_real.v index d0756e831..1e5de3684 100644 --- a/test_regress/t/t_display_real.v +++ b/test_regress/t/t_display_real.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; real n0; initial n0 = 0.0; diff --git a/test_regress/t/t_display_real_noopt.pl b/test_regress/t/t_display_real_noopt.pl index 3841a9de6..10a283c91 100755 --- a/test_regress/t/t_display_real_noopt.pl +++ b/test_regress/t/t_display_real_noopt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_realtime.pl b/test_regress/t/t_display_realtime.pl index 113f68def..d2d6934bc 100755 --- a/test_regress/t/t_display_realtime.pl +++ b/test_regress/t/t_display_realtime.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_realtime.v b/test_regress/t/t_display_realtime.v index 2ab57a4fb..9dbcff308 100644 --- a/test_regress/t/t_display_realtime.v +++ b/test_regress/t/t_display_realtime.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_display_signed.pl b/test_regress/t/t_display_signed.pl index f79178f86..b4e259e0a 100755 --- a/test_regress/t/t_display_signed.pl +++ b/test_regress/t/t_display_signed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_signed.v b/test_regress/t/t_display_signed.v index cd4a5fa18..0a4491071 100644 --- a/test_regress/t/t_display_signed.v +++ b/test_regress/t/t_display_signed.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; reg signed [20:0] longp; diff --git a/test_regress/t/t_display_signed_noopt.pl b/test_regress/t/t_display_signed_noopt.pl index 082c36770..ebbb3d572 100755 --- a/test_regress/t/t_display_signed_noopt.pl +++ b/test_regress/t/t_display_signed_noopt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_string.pl b/test_regress/t/t_display_string.pl index e109f0f6c..ec985d291 100755 --- a/test_regress/t/t_display_string.pl +++ b/test_regress/t/t_display_string.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_string.v b/test_regress/t/t_display_string.v index f2bd7deaa..aaa4aa3b4 100644 --- a/test_regress/t/t_display_string.v +++ b/test_regress/t/t_display_string.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; function automatic string foo(int i); diff --git a/test_regress/t/t_display_time.pl b/test_regress/t/t_display_time.pl index 584f9a477..b0a9c5416 100755 --- a/test_regress/t/t_display_time.pl +++ b/test_regress/t/t_display_time.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_time.v b/test_regress/t/t_display_time.v index b4a514692..c68b89829 100644 --- a/test_regress/t/t_display_time.v +++ b/test_regress/t/t_display_time.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns diff --git a/test_regress/t/t_display_wide.pl b/test_regress/t/t_display_wide.pl index f09e06508..6c6caeae2 100755 --- a/test_regress/t/t_display_wide.pl +++ b/test_regress/t/t_display_wide.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_display_wide.v b/test_regress/t/t_display_wide.v index 0e583b5af..026ebecf2 100644 --- a/test_regress/t/t_display_wide.v +++ b/test_regress/t/t_display_wide.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_dist_cinclude.pl b/test_regress/t/t_dist_cinclude.pl index 5f7600264..a7737fc12 100755 --- a/test_regress/t/t_dist_cinclude.pl +++ b/test_regress/t/t_dist_cinclude.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; diff --git a/test_regress/t/t_dist_contributors.pl b/test_regress/t/t_dist_contributors.pl index 8450c47ae..dd2a848b2 100755 --- a/test_regress/t/t_dist_contributors.pl +++ b/test_regress/t/t_dist_contributors.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use strict; diff --git a/test_regress/t/t_dist_error_format.pl b/test_regress/t/t_dist_error_format.pl new file mode 100755 index 000000000..ce5b544ec --- /dev/null +++ b/test_regress/t/t_dist_error_format.pl @@ -0,0 +1,75 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +use IO::File; + +scenarios(dist => 1); + +my $root = ".."; +my $Debug; + +if (!-r "$root/.git") { + skip("Not in a git repository"); +} else { + formats(); +} + +ok(1); + +# Check all error messages match our standard format +# This assumes .out files cover all important errors + +sub formats { + my $files = "../test_regress/t/*.out"; + my %warns; + my $lnmatch = 0; + foreach my $file (glob $files) { + my $wholefile = file_contents($file); + $file =~ s!.*/!!; + if ($wholefile =~ /Exiting due to/ + || $wholefile =~ /%(Error|Warning)/) { + my $lineno = 0; + foreach my $line (split /\n/, $wholefile) { + ++$lineno; + if ($line =~ /(Error|Warning)/) { + # These formats are documented in bin/verilator + # Error with fileline + # For testing only: we assume no : in filename + my $match = $line; + $match =~ s/^\[\d+\] //; # Simplify runtime errors + if ($match =~ /^%(Error|Warning)(-[A-Z0-9_]+)?: ([^:]+):(\d+):((\d+):)? /) { + ++$lnmatch; + print "ok-el $file $line\n" if $Self->{verbose}; + } + # Error no fileline + # For testing only: we assume any : is single quoted + elsif ($match =~ /^%(Error|Warning)(-[A-Z0-9_]+)?: [^:']+/) { + print "ok-en $file $line\n" if $Self->{verbose}; + } + else { + #print "FF $file $line\n"; + $warns{$file.":".$lineno} = + "Non-standard warning/error: $file:$lineno: $line"; + } + } + } + } + } + $lnmatch or error("Check line number regexp is correct, no matches"); + if (keys %warns) { + # First warning lists everything as that's shown in the driver summary + error($summary." ",join(' ',sort keys %warns)); + foreach my $file (sort keys %warns) { + error($warns{$file}); + } + } +} + +1; diff --git a/test_regress/t/t_dist_fixme.pl b/test_regress/t/t_dist_fixme.pl index 92256ce87..1f72d5ce5 100755 --- a/test_regress/t/t_dist_fixme.pl +++ b/test_regress/t/t_dist_fixme.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; diff --git a/test_regress/t/t_dist_inctree.pl b/test_regress/t/t_dist_inctree.pl index 019d3254d..2ecddacb1 100755 --- a/test_regress/t/t_dist_inctree.pl +++ b/test_regress/t/t_dist_inctree.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use strict; diff --git a/test_regress/t/t_dist_install.pl b/test_regress/t/t_dist_install.pl index 90a2679c2..e2409251a 100755 --- a/test_regress/t/t_dist_install.pl +++ b/test_regress/t/t_dist_install.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use Cwd; diff --git a/test_regress/t/t_dist_manifest.pl b/test_regress/t/t_dist_manifest.pl index 7947d936f..ddb42a925 100755 --- a/test_regress/t/t_dist_manifest.pl +++ b/test_regress/t/t_dist_manifest.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_dist_portability.pl b/test_regress/t/t_dist_portability.pl index a4cb14859..d905f2ab5 100755 --- a/test_regress/t/t_dist_portability.pl +++ b/test_regress/t/t_dist_portability.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; diff --git a/test_regress/t/t_dist_tabs.pl b/test_regress/t/t_dist_tabs.pl index 606921a22..869f0e8f6 100755 --- a/test_regress/t/t_dist_tabs.pl +++ b/test_regress/t/t_dist_tabs.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_dist_untracked.pl b/test_regress/t/t_dist_untracked.pl index a0e8e57be..b711c5e5b 100755 --- a/test_regress/t/t_dist_untracked.pl +++ b/test_regress/t/t_dist_untracked.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_dist_whitespace.pl b/test_regress/t/t_dist_whitespace.pl index 1168b44d9..afd5174e1 100755 --- a/test_regress/t/t_dist_whitespace.pl +++ b/test_regress/t/t_dist_whitespace.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_dos.pl b/test_regress/t/t_dos.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_dos.pl +++ b/test_regress/t/t_dos.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dos.v b/test_regress/t/t_dos.v index 1b239bf33..52707c713 100755 --- a/test_regress/t/t_dos.v +++ b/test_regress/t/t_dos.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // This file has DOS carrage returns in it! module t (/*AUTOARG*/ diff --git a/test_regress/t/t_dpi_2exp_bad.out b/test_regress/t/t_dpi_2exp_bad.out index 31732bd6b..9216f2be0 100644 --- a/test_regress/t/t_dpi_2exp_bad.out +++ b/test_regress/t/t_dpi_2exp_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_dpi_2exp_bad.v:11: Function was already DPI Exported, duplicate not allowed: 'dpix_twice' - export "DPI-C" dpix_t_int_renamed = task dpix_twice; - ^~~~~~~~~~ +%Error: t/t_dpi_2exp_bad.v:12:45: Function was already DPI Exported, duplicate not allowed: 'dpix_twice' + 12 | export "DPI-C" dpix_t_int_renamed = task dpix_twice; + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_2exp_bad.pl b/test_regress/t/t_dpi_2exp_bad.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_dpi_2exp_bad.pl +++ b/test_regress/t/t_dpi_2exp_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_dpi_2exp_bad.v b/test_regress/t/t_dpi_2exp_bad.v index 7e540f3b5..5188398aa 100644 --- a/test_regress/t/t_dpi_2exp_bad.v +++ b/test_regress/t/t_dpi_2exp_bad.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_accessors.cpp b/test_regress/t/t_dpi_accessors.cpp index 8a201c40f..dbec01ec9 100644 --- a/test_regress/t/t_dpi_accessors.cpp +++ b/test_regress/t/t_dpi_accessors.cpp @@ -1,15 +1,11 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // -// Copyright 2012 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Copyright 2012 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, but WITHOUT -// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -// more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // // Contributed by Jeremy Bennett and Jie Xu // diff --git a/test_regress/t/t_dpi_accessors.pl b/test_regress/t/t_dpi_accessors.pl index d2741cc06..91ee59ecb 100755 --- a/test_regress/t/t_dpi_accessors.pl +++ b/test_regress/t/t_dpi_accessors.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2012 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2012 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # 8-Mar-2012: Modifications for this test contributed by Jeremy Bennett and # Jie Xu. diff --git a/test_regress/t/t_dpi_accessors.v b/test_regress/t/t_dpi_accessors.v index 8d3d70921..9fe29f04f 100644 --- a/test_regress/t/t_dpi_accessors.v +++ b/test_regress/t/t_dpi_accessors.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // // Contributed by Jeremy Bennett and Jie Xul // diff --git a/test_regress/t/t_dpi_accessors_inc.vh b/test_regress/t/t_dpi_accessors_inc.vh index 02b0de18d..a258018f2 100644 --- a/test_regress/t/t_dpi_accessors_inc.vh +++ b/test_regress/t/t_dpi_accessors_inc.vh @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by Jeremy Bennett and Jie Xu diff --git a/test_regress/t/t_dpi_accessors_macros_inc.vh b/test_regress/t/t_dpi_accessors_macros_inc.vh index 18a19b885..9a4dafcb6 100644 --- a/test_regress/t/t_dpi_accessors_macros_inc.vh +++ b/test_regress/t/t_dpi_accessors_macros_inc.vh @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // // Contributed by Jeremy Bennett and Jie Xu // diff --git a/test_regress/t/t_dpi_context.pl b/test_regress/t/t_dpi_context.pl index 10cc5c36c..2113d8cb2 100755 --- a/test_regress/t/t_dpi_context.pl +++ b/test_regress/t/t_dpi_context.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_context.v b/test_regress/t/t_dpi_context.v index d92fff4c6..70838b473 100644 --- a/test_regress/t/t_dpi_context.v +++ b/test_regress/t/t_dpi_context.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_context_c.cpp b/test_regress/t/t_dpi_context_c.cpp index 8d18468a7..3204c9bea 100644 --- a/test_regress/t/t_dpi_context_c.cpp +++ b/test_regress/t/t_dpi_context_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_context_noopt.pl b/test_regress/t/t_dpi_context_noopt.pl index ff6a80d18..54b35dbf7 100755 --- a/test_regress/t/t_dpi_context_noopt.pl +++ b/test_regress/t/t_dpi_context_noopt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_display.pl b/test_regress/t/t_dpi_display.pl index 058201cc0..101403671 100755 --- a/test_regress/t/t_dpi_display.pl +++ b/test_regress/t/t_dpi_display.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_display.v b/test_regress/t/t_dpi_display.v index 3fc8f1a08..756199801 100644 --- a/test_regress/t/t_dpi_display.v +++ b/test_regress/t/t_dpi_display.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_display_c.cpp b/test_regress/t/t_dpi_display_c.cpp index 8a38689fc..befb46dc5 100644 --- a/test_regress/t/t_dpi_display_c.cpp +++ b/test_regress/t/t_dpi_display_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_dup_bad.out b/test_regress/t/t_dpi_dup_bad.out index 9b951038f..88cc02fe1 100644 --- a/test_regress/t/t_dpi_dup_bad.out +++ b/test_regress/t/t_dpi_dup_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_dpi_dup_bad.v:12: Duplicate declaration of DPI function with different formal arguments: 't.oth_f_int2' - import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); - ^~~~~~~~~~ - : ... New prototype: pure int dpii_fa_bit (int, int) - t/t_dpi_dup_bad.v:11: ... Original prototype: int dpii_fa_bit (int) - import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); - ^~~~~~~~~~ +%Error: t/t_dpi_dup_bad.v:13:51: Duplicate declaration of DPI function with different formal arguments: 't.oth_f_int2' + 13 | import "DPI-C" pure dpii_fa_bit = function int oth_f_int2(input int i, input int bad); + | ^~~~~~~~~~ + : ... New prototype: pure int dpii_fa_bit (int, int) + t/t_dpi_dup_bad.v:12:47: ... Original prototype: int dpii_fa_bit (int) + 12 | import "DPI-C" dpii_fa_bit = function int oth_f_int1(input int i); + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_dup_bad.pl b/test_regress/t/t_dpi_dup_bad.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_dpi_dup_bad.pl +++ b/test_regress/t/t_dpi_dup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_dpi_dup_bad.v b/test_regress/t/t_dpi_dup_bad.v index 8b59d29dd..145b72a1d 100644 --- a/test_regress/t/t_dpi_dup_bad.v +++ b/test_regress/t/t_dpi_dup_bad.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_exp_bad.out b/test_regress/t/t_dpi_exp_bad.out index f98e051e9..4db2d6559 100644 --- a/test_regress/t/t_dpi_exp_bad.out +++ b/test_regress/t/t_dpi_exp_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_dpi_exp_bad.v:11: DPI functions cannot return > 32 bits or four-state; use a two-state type or task instead: 'dpix_f_bit48__Vfuncrtn' - function bit [47:0] dpix_f_bit48(bit [47:0] i); dpix_f_bit48 = ~i; endfunction - ^~~~~~~~~~~~ +%Error: t/t_dpi_exp_bad.v:12:24: DPI functions cannot return > 32 bits or four-state; use a two-state type or task instead: 'dpix_f_bit48__Vfuncrtn' + 12 | function bit [47:0] dpix_f_bit48(bit [47:0] i); dpix_f_bit48 = ~i; endfunction + | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_exp_bad.pl b/test_regress/t/t_dpi_exp_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_dpi_exp_bad.pl +++ b/test_regress/t/t_dpi_exp_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_dpi_exp_bad.v b/test_regress/t/t_dpi_exp_bad.v index 765905991..4f0cb56c9 100644 --- a/test_regress/t/t_dpi_exp_bad.v +++ b/test_regress/t/t_dpi_exp_bad.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_export.pl b/test_regress/t/t_dpi_export.pl index a665b7335..927a685e9 100755 --- a/test_regress/t/t_dpi_export.pl +++ b/test_regress/t/t_dpi_export.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end diff --git a/test_regress/t/t_dpi_export.v b/test_regress/t/t_dpi_export.v index a7eed5427..ad27183a8 100644 --- a/test_regress/t/t_dpi_export.v +++ b/test_regress/t/t_dpi_export.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_TIME diff --git a/test_regress/t/t_dpi_export_c.cpp b/test_regress/t/t_dpi_export_c.cpp index 46e78c3e2..297a6edc1 100644 --- a/test_regress/t/t_dpi_export_c.cpp +++ b/test_regress/t/t_dpi_export_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_export_context_bad.cpp b/test_regress/t/t_dpi_export_context_bad.cpp index 135bc7d3c..a4bad53d4 100644 --- a/test_regress/t/t_dpi_export_context_bad.cpp +++ b/test_regress/t/t_dpi_export_context_bad.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_dpi_export_context_bad.pl b/test_regress/t/t_dpi_export_context_bad.pl index 72e2ef077..af0dcdbd9 100755 --- a/test_regress/t/t_dpi_export_context_bad.pl +++ b/test_regress/t/t_dpi_export_context_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_export_context_bad.v b/test_regress/t/t_dpi_export_context_bad.v index ec52623af..dc4c50655 100644 --- a/test_regress/t/t_dpi_export_context_bad.v +++ b/test_regress/t/t_dpi_export_context_bad.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; export "DPI-C" task dpix_task; diff --git a/test_regress/t/t_dpi_export_noopt.pl b/test_regress/t/t_dpi_export_noopt.pl index 374aaf77b..1a4e6297e 100755 --- a/test_regress/t/t_dpi_export_noopt.pl +++ b/test_regress/t/t_dpi_export_noopt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # irun -sv top.v t_dpi_export.v -cpost t_dpi_export_c.c -end diff --git a/test_regress/t/t_dpi_imp_gen.pl b/test_regress/t/t_dpi_imp_gen.pl index 7232ad5ee..fc14166a9 100755 --- a/test_regress/t/t_dpi_imp_gen.pl +++ b/test_regress/t/t_dpi_imp_gen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2011 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2011 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_imp_gen.v b/test_regress/t/t_dpi_imp_gen.v index 2e4367888..e7678be43 100644 --- a/test_regress/t/t_dpi_imp_gen.v +++ b/test_regress/t/t_dpi_imp_gen.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_dpi_imp_gen_c.cpp b/test_regress/t/t_dpi_imp_gen_c.cpp index 366bb46c5..03f907f0d 100644 --- a/test_regress/t/t_dpi_imp_gen_c.cpp +++ b/test_regress/t/t_dpi_imp_gen_c.cpp @@ -6,6 +6,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include diff --git a/test_regress/t/t_dpi_import.pl b/test_regress/t/t_dpi_import.pl index ce88e2ad0..c1f710bda 100755 --- a/test_regress/t/t_dpi_import.pl +++ b/test_regress/t/t_dpi_import.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_import.v b/test_regress/t/t_dpi_import.v index e78cb284a..1f45833ae 100644 --- a/test_regress/t/t_dpi_import.v +++ b/test_regress/t/t_dpi_import.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_SHORTREAL diff --git a/test_regress/t/t_dpi_import_c.cpp b/test_regress/t/t_dpi_import_c.cpp index 29d135772..ebcbedef1 100644 --- a/test_regress/t/t_dpi_import_c.cpp +++ b/test_regress/t/t_dpi_import_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_import_hdr_only.pl b/test_regress/t/t_dpi_import_hdr_only.pl index a884ce466..dd4b84fde 100755 --- a/test_regress/t/t_dpi_import_hdr_only.pl +++ b/test_regress/t/t_dpi_import_hdr_only.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use File::Temp; use File::Compare; diff --git a/test_regress/t/t_dpi_lib.pl b/test_regress/t/t_dpi_lib.pl index 292f84bce..e31f5e846 100755 --- a/test_regress/t/t_dpi_lib.pl +++ b/test_regress/t/t_dpi_lib.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_lib.v b/test_regress/t/t_dpi_lib.v index 296889601..41b6348ef 100644 --- a/test_regress/t/t_dpi_lib.v +++ b/test_regress/t/t_dpi_lib.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_dpi_lib_c.cpp b/test_regress/t/t_dpi_lib_c.cpp index e1142a20b..bb214c594 100644 --- a/test_regress/t/t_dpi_lib_c.cpp +++ b/test_regress/t/t_dpi_lib_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_logic_bad.out b/test_regress/t/t_dpi_logic_bad.out index 3d701665c..b5ea2f431 100644 --- a/test_regress/t/t_dpi_logic_bad.out +++ b/test_regress/t/t_dpi_logic_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_dpi_logic_bad.v:11: DPI function may not return type BASICDTYPE 'logic' (IEEE 1800-2017 35.5.5) - import "DPI-C" dpii_fa_bit = function logic [2:0] oth_f_int1(input time i); - ^~~~~~~~~~ +%Error: t/t_dpi_logic_bad.v:12:54: DPI function may not return type BASICDTYPE 'logic' (IEEE 1800-2017 35.5.5) + 12 | import "DPI-C" dpii_fa_bit = function logic [2:0] oth_f_int1(input time i); + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_logic_bad.pl b/test_regress/t/t_dpi_logic_bad.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_dpi_logic_bad.pl +++ b/test_regress/t/t_dpi_logic_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_dpi_logic_bad.v b/test_regress/t/t_dpi_logic_bad.v index 44f86489d..2eccc0af4 100644 --- a/test_regress/t/t_dpi_logic_bad.v +++ b/test_regress/t/t_dpi_logic_bad.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_name_bad.out b/test_regress/t/t_dpi_name_bad.out index ebbef4650..a061f6f78 100644 --- a/test_regress/t/t_dpi_name_bad.out +++ b/test_regress/t/t_dpi_name_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_dpi_name_bad.v:11: DPI function has illegal characters in C identifier name: 'badly.named' - import "DPI-C" function int \badly.named (int i); - ^~~~~~~~~~~~ +%Error: t/t_dpi_name_bad.v:12:32: DPI function has illegal characters in C identifier name: 'badly.named' + 12 | import "DPI-C" function int \badly.named (int i); + | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_dpi_name_bad.pl b/test_regress/t/t_dpi_name_bad.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_dpi_name_bad.pl +++ b/test_regress/t/t_dpi_name_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_dpi_name_bad.v b/test_regress/t/t_dpi_name_bad.v index 33de52601..e8c066912 100644 --- a/test_regress/t/t_dpi_name_bad.v +++ b/test_regress/t/t_dpi_name_bad.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_open.pl b/test_regress/t/t_dpi_open.pl index c4ca90723..38e58ef3c 100755 --- a/test_regress/t/t_dpi_open.pl +++ b/test_regress/t/t_dpi_open.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_open.v b/test_regress/t/t_dpi_open.v index 9690dc86f..09bce4338 100644 --- a/test_regress/t/t_dpi_open.v +++ b/test_regress/t/t_dpi_open.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) diff --git a/test_regress/t/t_dpi_open_c.cpp b/test_regress/t/t_dpi_open_c.cpp index 127aac0a6..cf0440620 100644 --- a/test_regress/t/t_dpi_open_c.cpp +++ b/test_regress/t/t_dpi_open_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_openfirst.pl b/test_regress/t/t_dpi_openfirst.pl index 0e6e42ea9..e2e88b0b3 100755 --- a/test_regress/t/t_dpi_openfirst.pl +++ b/test_regress/t/t_dpi_openfirst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_openfirst.v b/test_regress/t/t_dpi_openfirst.v index 1fba53823..a79dc4dd1 100644 --- a/test_regress/t/t_dpi_openfirst.v +++ b/test_regress/t/t_dpi_openfirst.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) diff --git a/test_regress/t/t_dpi_openfirst_c.cpp b/test_regress/t/t_dpi_openfirst_c.cpp index 8de301afa..c5ba23795 100644 --- a/test_regress/t/t_dpi_openfirst_c.cpp +++ b/test_regress/t/t_dpi_openfirst_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_qw.pl b/test_regress/t/t_dpi_qw.pl index 5f46d7150..bb25c3c8c 100755 --- a/test_regress/t/t_dpi_qw.pl +++ b/test_regress/t/t_dpi_qw.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2011 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2011 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_qw.v b/test_regress/t/t_dpi_qw.v index 9c0cb4b8c..a23e50304 100644 --- a/test_regress/t/t_dpi_qw.v +++ b/test_regress/t/t_dpi_qw.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_dpi_qw_c.cpp b/test_regress/t/t_dpi_qw_c.cpp index 9f1a5f893..802f87991 100644 --- a/test_regress/t/t_dpi_qw_c.cpp +++ b/test_regress/t/t_dpi_qw_c.cpp @@ -6,6 +6,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 //************************************************************************* #include diff --git a/test_regress/t/t_dpi_shortcircuit.pl b/test_regress/t/t_dpi_shortcircuit.pl index addd715ef..1e00f07ea 100755 --- a/test_regress/t/t_dpi_shortcircuit.pl +++ b/test_regress/t/t_dpi_shortcircuit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug413 short circuit"); diff --git a/test_regress/t/t_dpi_shortcircuit.v b/test_regress/t/t_dpi_shortcircuit.v index c2ff2ac74..1b2c7b463 100644 --- a/test_regress/t/t_dpi_shortcircuit.v +++ b/test_regress/t/t_dpi_shortcircuit.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_SHORTREAL diff --git a/test_regress/t/t_dpi_shortcircuit2.pl b/test_regress/t/t_dpi_shortcircuit2.pl index c076932ad..1c4266501 100755 --- a/test_regress/t/t_dpi_shortcircuit2.pl +++ b/test_regress/t/t_dpi_shortcircuit2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_shortcircuit2.v b/test_regress/t/t_dpi_shortcircuit2.v index 81db3530c..ae2ec9476 100644 --- a/test_regress/t/t_dpi_shortcircuit2.v +++ b/test_regress/t/t_dpi_shortcircuit2.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VCS `define NO_SHORTREAL diff --git a/test_regress/t/t_dpi_shortcircuit_c.cpp b/test_regress/t/t_dpi_shortcircuit_c.cpp index 57384718b..4f381111a 100644 --- a/test_regress/t/t_dpi_shortcircuit_c.cpp +++ b/test_regress/t/t_dpi_shortcircuit_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2011-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_string.pl b/test_regress/t/t_dpi_string.pl index 9e6086334..d24f298c7 100755 --- a/test_regress/t/t_dpi_string.pl +++ b/test_regress/t/t_dpi_string.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_string.v b/test_regress/t/t_dpi_string.v index c1387545a..21141b81e 100644 --- a/test_regress/t/t_dpi_string.v +++ b/test_regress/t/t_dpi_string.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); diff --git a/test_regress/t/t_dpi_string_c.cpp b/test_regress/t/t_dpi_string_c.cpp index 29fb5966d..9b8a476eb 100644 --- a/test_regress/t/t_dpi_string_c.cpp +++ b/test_regress/t/t_dpi_string_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_sys.pl b/test_regress/t/t_dpi_sys.pl index baee7849c..797a29407 100755 --- a/test_regress/t/t_dpi_sys.pl +++ b/test_regress/t/t_dpi_sys.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_sys.v b/test_regress/t/t_dpi_sys.v index 173d89683..13673964e 100644 --- a/test_regress/t/t_dpi_sys.v +++ b/test_regress/t/t_dpi_sys.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // Global is the most likely usage scenario import "DPI-C" dpii_sys_task = function void \$dpii_sys (int i); diff --git a/test_regress/t/t_dpi_sys_c.cpp b/test_regress/t/t_dpi_sys_c.cpp index 50dafff10..b6a15e6d3 100644 --- a/test_regress/t/t_dpi_sys_c.cpp +++ b/test_regress/t/t_dpi_sys_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_threads.pl b/test_regress/t/t_dpi_threads.pl index 51bd34df3..d936d07c8 100755 --- a/test_regress/t/t_dpi_threads.pl +++ b/test_regress/t/t_dpi_threads.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2018 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2018 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); diff --git a/test_regress/t/t_dpi_threads.v b/test_regress/t/t_dpi_threads.v index 5f982b09b..2a80f029a 100644 --- a/test_regress/t/t_dpi_threads.v +++ b/test_regress/t/t_dpi_threads.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" dpii_sys_task = function void \$dpii_sys (); import "DPI-C" dpii_failure = function int \$dpii_failure (); diff --git a/test_regress/t/t_dpi_threads_c.cpp b/test_regress/t/t_dpi_threads_c.cpp index 8ed0ac701..edc7de5c5 100644 --- a/test_regress/t/t_dpi_threads_c.cpp +++ b/test_regress/t/t_dpi_threads_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2018-2018 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_threads_collide.pl b/test_regress/t/t_dpi_threads_collide.pl index d7897d8d1..8e9c07e4d 100755 --- a/test_regress/t/t_dpi_threads_collide.pl +++ b/test_regress/t/t_dpi_threads_collide.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2018 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2018 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->skip_if_too_few_cores(); diff --git a/test_regress/t/t_dpi_vams.cpp b/test_regress/t/t_dpi_vams.cpp index 5272d92e0..a7473f174 100644 --- a/test_regress/t/t_dpi_vams.cpp +++ b/test_regress/t/t_dpi_vams.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include "Vt_dpi_vams.h" diff --git a/test_regress/t/t_dpi_vams.pl b/test_regress/t/t_dpi_vams.pl index 66b07eadf..04b9aeb1c 100755 --- a/test_regress/t/t_dpi_vams.pl +++ b/test_regress/t/t_dpi_vams.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dpi_vams.v b/test_regress/t/t_dpi_vams.v index 09d458043..196b42f1b 100644 --- a/test_regress/t/t_dpi_vams.v +++ b/test_regress/t/t_dpi_vams.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //`begin_keywords "VAMS-2.3" `begin_keywords "1800+VAMS" diff --git a/test_regress/t/t_dpi_var.cpp b/test_regress/t/t_dpi_var.cpp index 146ddafe0..dad42dcc1 100644 --- a/test_regress/t/t_dpi_var.cpp +++ b/test_regress/t/t_dpi_var.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_dpi_var.pl b/test_regress/t/t_dpi_var.pl index 48029f606..a9210bf25 100755 --- a/test_regress/t/t_dpi_var.pl +++ b/test_regress/t/t_dpi_var.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); my $out_filename = "$Self->{obj_dir}/V$Self->{name}.xml"; @@ -17,10 +18,10 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_dpi_var.v b/test_regress/t/t_dpi_var.v index 4f9236a09..1ad0c1f3d 100644 --- a/test_regress/t/t_dpi_var.v +++ b/test_regress/t/t_dpi_var.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_dpi_var.vlt b/test_regress/t/t_dpi_var.vlt index 063a2284b..70216609d 100644 --- a/test_regress/t/t_dpi_var.vlt +++ b/test_regress/t/t_dpi_var.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_dpi_var_vlt.pl b/test_regress/t/t_dpi_var_vlt.pl index a6004fdc2..bc97cc595 100755 --- a/test_regress/t/t_dpi_var_vlt.pl +++ b/test_regress/t/t_dpi_var_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -19,10 +20,10 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_driver_random.pl b/test_regress/t/t_driver_random.pl index 7ea162a2a..cf3611fb2 100755 --- a/test_regress/t/t_driver_random.pl +++ b/test_regress/t/t_driver_random.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use Time::HiRes; diff --git a/test_regress/t/t_dynarray.pl b/test_regress/t/t_dynarray.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_dynarray.pl +++ b/test_regress/t/t_dynarray.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_dynarray.v b/test_regress/t/t_dynarray.v index 146ad0be2..584707bb0 100644 --- a/test_regress/t/t_dynarray.v +++ b/test_regress/t/t_dynarray.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); diff --git a/test_regress/t/t_dynarray_bad.out b/test_regress/t/t_dynarray_bad.out index c323f3ca2..7bb4e86b5 100644 --- a/test_regress/t/t_dynarray_bad.out +++ b/test_regress/t/t_dynarray_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTH: t/t_dynarray_bad.v:14: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits. - : ... In instance t - a = new [s]; - ^~~ +%Warning-WIDTH: t/t_dynarray_bad.v:15:11: Operator NEWDYNAMIC expects 32 bits on the new() size, but new() size's VARREF 's' generates 64 bits. + : ... In instance t + 15 | a = new [s]; + | ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Internal Error: ../V3Number.cpp:#: Number operation called with non-logic (double or string) argument: '"str"" diff --git a/test_regress/t/t_dynarray_bad.pl b/test_regress/t/t_dynarray_bad.pl index 4689d6999..e2ea28d29 100755 --- a/test_regress/t/t_dynarray_bad.pl +++ b/test_regress/t/t_dynarray_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_dynarray_bad.v b/test_regress/t/t_dynarray_bad.v index 2516a6deb..e2533af5a 100644 --- a/test_regress/t/t_dynarray_bad.v +++ b/test_regress/t/t_dynarray_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_embed1.pl b/test_regress/t/t_embed1.pl index 1f5d931b0..87e3fbcd3 100755 --- a/test_regress/t/t_embed1.pl +++ b/test_regress/t/t_embed1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use File::Spec; diff --git a/test_regress/t/t_embed1.v b/test_regress/t/t_embed1.v index d84751fc2..c65452f7d 100644 --- a/test_regress/t/t_embed1.v +++ b/test_regress/t/t_embed1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_embed1_c.cpp b/test_regress/t/t_embed1_c.cpp index 029d33323..ff9cf19ca 100644 --- a/test_regress/t/t_embed1_c.cpp +++ b/test_regress/t/t_embed1_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2011-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_embed1_child.v b/test_regress/t/t_embed1_child.v index ff7749727..3a78275b3 100644 --- a/test_regress/t/t_embed1_child.v +++ b/test_regress/t/t_embed1_child.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_embed1_child (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_embed1_wrap.v b/test_regress/t/t_embed1_wrap.v index da05a63dd..5aac6e631 100644 --- a/test_regress/t/t_embed1_wrap.v +++ b/test_regress/t/t_embed1_wrap.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_embed1_wrap (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_emit_constw.pl b/test_regress/t/t_emit_constw.pl index ed09e4347..ad1b43680 100755 --- a/test_regress/t/t_emit_constw.pl +++ b/test_regress/t/t_emit_constw.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_emit_constw.v b/test_regress/t/t_emit_constw.v index 40757de4b..e49d532de 100644 --- a/test_regress/t/t_emit_constw.v +++ b/test_regress/t/t_emit_constw.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkhw(gotv,w,expv) do if (gotv[(w)*32+:$bits(expv)] !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv[(w)*32+:32]), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_emit_memb_limit.pl b/test_regress/t/t_emit_memb_limit.pl index 39d551319..9cef22356 100755 --- a/test_regress/t/t_emit_memb_limit.pl +++ b/test_regress/t/t_emit_memb_limit.pl @@ -2,13 +2,15 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; -scenarios(simulator => 1); +# Very slow on vltmt, and doesn't test much of value there, so disabled +scenarios(vlt => 1); sub gen { my $filename = shift; diff --git a/test_regress/t/t_enum.pl b/test_regress/t/t_enum.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_enum.pl +++ b/test_regress/t/t_enum.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum.v b/test_regress/t/t_enum.v index 272471649..1a5c87b9b 100644 --- a/test_regress/t/t_enum.v +++ b/test_regress/t/t_enum.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 typedef enum logic [4:0] { diff --git a/test_regress/t/t_enum_bad_hide.out b/test_regress/t/t_enum_bad_hide.out index e9ab63481..27ce71294 100644 --- a/test_regress/t/t_enum_bad_hide.out +++ b/test_regress/t/t_enum_bad_hide.out @@ -1,8 +1,8 @@ -%Warning-VARHIDDEN: t/t_enum_bad_hide.v:10: Declaration of enum value hides declaration in upper scope: HIDE_VALUE - typedef enum { HIDE_VALUE = 0 } hide_enum_t; - ^~~~~~~~~~ - t/t_enum_bad_hide.v:6: ... Location of original declaration - typedef enum { HIDE_VALUE = 0 } hide_enum_t; - ^~~~~~~~~~ +%Warning-VARHIDDEN: t/t_enum_bad_hide.v:11:19: Declaration of enum value hides declaration in upper scope: HIDE_VALUE + 11 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; + | ^~~~~~~~~~ + t/t_enum_bad_hide.v:7:16: ... Location of original declaration + 11 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; + | ^~~~~~~~~~ ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_enum_bad_hide.pl b/test_regress/t/t_enum_bad_hide.pl index 2daf76efb..b76ca20f1 100755 --- a/test_regress/t/t_enum_bad_hide.pl +++ b/test_regress/t/t_enum_bad_hide.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_enum_bad_hide.v b/test_regress/t/t_enum_bad_hide.v index eafe4d03d..a234a212e 100644 --- a/test_regress/t/t_enum_bad_hide.v +++ b/test_regress/t/t_enum_bad_hide.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 typedef enum { HIDE_VALUE = 0 } hide_enum_t; diff --git a/test_regress/t/t_enum_func.pl b/test_regress/t/t_enum_func.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_enum_func.pl +++ b/test_regress/t/t_enum_func.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_func.v b/test_regress/t/t_enum_func.v index 1251a1b79..e9ae74c70 100644 --- a/test_regress/t/t_enum_func.v +++ b/test_regress/t/t_enum_func.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 typedef enum { EN_ZERO, EN_ONE diff --git a/test_regress/t/t_enum_int.pl b/test_regress/t/t_enum_int.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_enum_int.pl +++ b/test_regress/t/t_enum_int.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_int.v b/test_regress/t/t_enum_int.v index 042a0047a..a23b8a91e 100644 --- a/test_regress/t/t_enum_int.v +++ b/test_regress/t/t_enum_int.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_enum_large_methods.pl b/test_regress/t/t_enum_large_methods.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_enum_large_methods.pl +++ b/test_regress/t/t_enum_large_methods.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_large_methods.v b/test_regress/t/t_enum_large_methods.v index 0e338cafd..a8b75326b 100644 --- a/test_regress/t/t_enum_large_methods.v +++ b/test_regress/t/t_enum_large_methods.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_enum_name2.pl b/test_regress/t/t_enum_name2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_enum_name2.pl +++ b/test_regress/t/t_enum_name2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_name2.v b/test_regress/t/t_enum_name2.v index 6e420bd6f..0048905aa 100644 --- a/test_regress/t/t_enum_name2.v +++ b/test_regress/t/t_enum_name2.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. +// SPDX-License-Identifier: CC0-1.0 package our_pkg; typedef enum logic [8-1:0] { diff --git a/test_regress/t/t_enum_name3.pl b/test_regress/t/t_enum_name3.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_enum_name3.pl +++ b/test_regress/t/t_enum_name3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_name3.v b/test_regress/t/t_enum_name3.v index d7613f2e8..80b3ae0ba 100644 --- a/test_regress/t/t_enum_name3.v +++ b/test_regress/t/t_enum_name3.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. +// SPDX-License-Identifier: CC0-1.0 // bug855 module our; diff --git a/test_regress/t/t_enum_overlap_bad.out b/test_regress/t/t_enum_overlap_bad.out index 8e6aa75eb..6e745c509 100644 --- a/test_regress/t/t_enum_overlap_bad.out +++ b/test_regress/t/t_enum_overlap_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_enum_overlap_bad.v:11: Overlapping enumeration value: 'e1b' - : ... In instance t - e1b=1 - ^~~ - t/t_enum_overlap_bad.v:9: ... Location of original declaration - e1, - ^~ +%Error: t/t_enum_overlap_bad.v:12:11: Overlapping enumeration value: 'e1b' + : ... In instance t + 12 | e1b=1 + | ^~~ + t/t_enum_overlap_bad.v:10:11: ... Location of original declaration + 10 | e1, + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_enum_overlap_bad.pl b/test_regress/t/t_enum_overlap_bad.pl index 573f98f12..8e4fecbdb 100755 --- a/test_regress/t/t_enum_overlap_bad.pl +++ b/test_regress/t/t_enum_overlap_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_enum_overlap_bad.v b/test_regress/t/t_enum_overlap_bad.v index 00c84f7de..ed0e1f64e 100644 --- a/test_regress/t/t_enum_overlap_bad.v +++ b/test_regress/t/t_enum_overlap_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_enum_public.cpp b/test_regress/t/t_enum_public.cpp index 1a0f66f3e..e0d95de7a 100644 --- a/test_regress/t/t_enum_public.cpp +++ b/test_regress/t/t_enum_public.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include "Vt_enum_public.h" diff --git a/test_regress/t/t_enum_public.pl b/test_regress/t/t_enum_public.pl index a5a02b6b2..ae7a261c5 100755 --- a/test_regress/t/t_enum_public.pl +++ b/test_regress/t/t_enum_public.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_public.v b/test_regress/t/t_enum_public.v index d26a77bb2..dfae146c5 100644 --- a/test_regress/t/t_enum_public.v +++ b/test_regress/t/t_enum_public.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 package p3; typedef enum logic [2:0] { diff --git a/test_regress/t/t_enum_recurse_bad.out b/test_regress/t/t_enum_recurse_bad.out index b56550b32..3cc8a55d3 100644 --- a/test_regress/t/t_enum_recurse_bad.out +++ b/test_regress/t/t_enum_recurse_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_enum_recurse_bad.v:6: Recursive enum value: 'u' -enum {u=u} e_t; - ^ -%Error: t/t_enum_recurse_bad.v:6: Expecting expression to be constant, but variable isn't const: 'u' -enum {u=u} e_t; - ^ -%Error: t/t_enum_recurse_bad.v:6: Enum value isn't a constant -enum {u=u} e_t; - ^ +%Error: t/t_enum_recurse_bad.v:7:9: Recursive enum value: 'u' + 7 | enum {u=u} e_t; + | ^ +%Error: t/t_enum_recurse_bad.v:7:9: Expecting expression to be constant, but variable isn't const: 'u' + 7 | enum {u=u} e_t; + | ^ +%Error: t/t_enum_recurse_bad.v:7:9: Enum value isn't a constant + 7 | enum {u=u} e_t; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_enum_recurse_bad.pl b/test_regress/t/t_enum_recurse_bad.pl index ac8a3e44a..b1b5983b1 100755 --- a/test_regress/t/t_enum_recurse_bad.pl +++ b/test_regress/t/t_enum_recurse_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_recurse_bad.v b/test_regress/t/t_enum_recurse_bad.v index ea93cf6d5..d6a62f6de 100644 --- a/test_regress/t/t_enum_recurse_bad.v +++ b/test_regress/t/t_enum_recurse_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 enum {u=u} e_t; diff --git a/test_regress/t/t_enum_size.pl b/test_regress/t/t_enum_size.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_enum_size.pl +++ b/test_regress/t/t_enum_size.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_size.v b/test_regress/t/t_enum_size.v index 5fd56cae6..8cc2992f9 100644 --- a/test_regress/t/t_enum_size.v +++ b/test_regress/t/t_enum_size.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_enum_type_methods.pl b/test_regress/t/t_enum_type_methods.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_enum_type_methods.pl +++ b/test_regress/t/t_enum_type_methods.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_type_methods.v b/test_regress/t/t_enum_type_methods.v index 8433a389d..37697ddf7 100644 --- a/test_regress/t/t_enum_type_methods.v +++ b/test_regress/t/t_enum_type_methods.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_enum_type_methods_bad.out b/test_regress/t/t_enum_type_methods_bad.out index ca262cefa..7bcf19162 100644 --- a/test_regress/t/t_enum_type_methods_bad.out +++ b/test_regress/t/t_enum_type_methods_bad.out @@ -1,5 +1,5 @@ -%Error: Internal Error: t/t_enum_type_methods_bad.v:23: ../V3Width.cpp:#: Unsupported: enum next/prev with non-const argument - : ... In instance t - e.next(increment); - ^~~~~~~~~ +%Error: Internal Error: t/t_enum_type_methods_bad.v:24:14: ../V3Width.cpp:#: Unsupported: enum next/prev with non-const argument + : ... In instance t + 24 | e.next(increment); + | ^~~~~~~~~ ... See the manual and https://verilator.org for more assistance. diff --git a/test_regress/t/t_enum_type_methods_bad.pl b/test_regress/t/t_enum_type_methods_bad.pl index 45ec8147c..f38979026 100755 --- a/test_regress/t/t_enum_type_methods_bad.pl +++ b/test_regress/t/t_enum_type_methods_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_enum_type_methods_bad.v b/test_regress/t/t_enum_type_methods_bad.v index f65f1b146..3b0066db1 100644 --- a/test_regress/t/t_enum_type_methods_bad.v +++ b/test_regress/t/t_enum_type_methods_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_enum_type_pins.pl b/test_regress/t/t_enum_type_pins.pl index fa5aa5f6c..340f9836d 100755 --- a/test_regress/t/t_enum_type_pins.pl +++ b/test_regress/t/t_enum_type_pins.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); # Not yet working on Verilator diff --git a/test_regress/t/t_enum_type_pins.v b/test_regress/t/t_enum_type_pins.v index e701df472..de16dc9d5 100644 --- a/test_regress/t/t_enum_type_pins.v +++ b/test_regress/t/t_enum_type_pins.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, without // warranty. +// SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. diff --git a/test_regress/t/t_enum_x_bad.out b/test_regress/t/t_enum_x_bad.out index 0f6ffbf24..360ee2f57 100644 --- a/test_regress/t/t_enum_x_bad.out +++ b/test_regress/t/t_enum_x_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_enum_x_bad.v:8: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 1800-2017 6.19) - : ... In instance t - enum bit [1:0] { BADX = 2'b1x } BAD1; - ^~~~ -%Error: t/t_enum_x_bad.v:11: Enum value that is unassigned cannot follow value with X/Zs (IEEE 1800-2017 6.19) - : ... In instance t - e1 - ^~ +%Error: t/t_enum_x_bad.v:9:21: Enum value with X/Zs cannot be assigned to non-fourstate type (IEEE 1800-2017 6.19) + : ... In instance t + 9 | enum bit [1:0] { BADX = 2'b1x } BAD1; + | ^~~~ +%Error: t/t_enum_x_bad.v:12:23: Enum value that is unassigned cannot follow value with X/Zs (IEEE 1800-2017 6.19) + : ... In instance t + 12 | e1 + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_enum_x_bad.pl b/test_regress/t/t_enum_x_bad.pl index 573f98f12..8e4fecbdb 100755 --- a/test_regress/t/t_enum_x_bad.pl +++ b/test_regress/t/t_enum_x_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_enum_x_bad.v b/test_regress/t/t_enum_x_bad.v index 876ef29d5..9d021d08e 100644 --- a/test_regress/t/t_enum_x_bad.v +++ b/test_regress/t/t_enum_x_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_enumeration.pl b/test_regress/t/t_enumeration.pl index c8d460fa4..60a0147f8 100755 --- a/test_regress/t/t_enumeration.pl +++ b/test_regress/t/t_enumeration.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug460"); diff --git a/test_regress/t/t_enumeration.v b/test_regress/t/t_enumeration.v index 49bb9b89b..50c051c3c 100644 --- a/test_regress/t/t_enumeration.v +++ b/test_regress/t/t_enumeration.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_extend.pl b/test_regress/t/t_extend.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_extend.pl +++ b/test_regress/t/t_extend.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_extend.v b/test_regress/t/t_extend.v index e2a2ae788..689b7dd69 100644 --- a/test_regress/t/t_extend.v +++ b/test_regress/t/t_extend.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_extend_class.pl b/test_regress/t/t_extend_class.pl index 6da737e5a..2dad80579 100755 --- a/test_regress/t/t_extend_class.pl +++ b/test_regress/t/t_extend_class.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_extend_class.v b/test_regress/t/t_extend_class.v index 25250d88b..9eda467df 100644 --- a/test_regress/t/t_extend_class.v +++ b/test_regress/t/t_extend_class.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_extend_class_c.h b/test_regress/t/t_extend_class_c.h index 28f0db7d0..4c73f1a2b 100644 --- a/test_regress/t/t_extend_class_c.h +++ b/test_regress/t/t_extend_class_c.h @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006-2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006-2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 class t_extend_class_c { public: diff --git a/test_regress/t/t_final.pl b/test_regress/t/t_final.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_final.pl +++ b/test_regress/t/t_final.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_final.v b/test_regress/t/t_final.v index b66c49ed1..c3d4eb588 100644 --- a/test_regress/t/t_final.v +++ b/test_regress/t/t_final.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Charlie Brej. +// SPDX-License-Identifier: CC0-1.0 module submodule (); // This bug only appears when not inlining diff --git a/test_regress/t/t_flag_bboxsys.pl b/test_regress/t/t_flag_bboxsys.pl index 607c39a55..c34d556d0 100755 --- a/test_regress/t/t_flag_bboxsys.pl +++ b/test_regress/t/t_flag_bboxsys.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_bboxsys.v b/test_regress/t/t_flag_bboxsys.v index 92f922994..6dd8770e6 100644 --- a/test_regress/t/t_flag_bboxsys.v +++ b/test_regress/t/t_flag_bboxsys.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; reg a; diff --git a/test_regress/t/t_flag_context_bad.out b/test_regress/t/t_flag_context_bad.out index e1f8112fa..2fb7fe3ad 100644 --- a/test_regress/t/t_flag_context_bad.out +++ b/test_regress/t/t_flag_context_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTH: t/t_flag_context_bad.v:8: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. - : ... In instance t +%Warning-WIDTH: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. + : ... In instance t ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-UNUSED: t/t_flag_context_bad.v:8: Signal is not used: 'foo' - : ... In instance t +%Warning-UNUSED: t/t_flag_context_bad.v:9:15: Signal is not used: 'foo' + : ... In instance t %Error: Exiting due to diff --git a/test_regress/t/t_flag_context_bad.pl b/test_regress/t/t_flag_context_bad.pl index 0b9220293..2e4055cc0 100755 --- a/test_regress/t/t_flag_context_bad.pl +++ b/test_regress/t/t_flag_context_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_context_bad.v b/test_regress/t/t_flag_context_bad.v index 741efcfec..055678c3f 100644 --- a/test_regress/t/t_flag_context_bad.v +++ b/test_regress/t/t_flag_context_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_flag_csplit.pl b/test_regress/t/t_flag_csplit.pl index 4d08bb271..1a42472ea 100755 --- a/test_regress/t/t_flag_csplit.pl +++ b/test_regress/t/t_flag_csplit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); @@ -31,7 +32,7 @@ while (1) { "-C ".$Self->{obj_dir}, "-f $Self->{VM_PREFIX}.mk", "-j 4", - "VM_PARALLEL_BUILDS=1", # Important to this test + #"VM_PARALLEL_BUILDS=1", # Check is set by makefile "VM_PREFIX=$Self->{VM_PREFIX}", "TEST_OBJ_DIR=$Self->{obj_dir}", "CPPFLAGS_DRIVER=-D".uc($Self->{name}), diff --git a/test_regress/t/t_flag_csplit.v b/test_regress/t/t_flag_csplit.v index e4ea0c2e3..b1ad77045 100644 --- a/test_regress/t/t_flag_csplit.v +++ b/test_regress/t/t_flag_csplit.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_flag_debug_noleak.pl b/test_regress/t/t_flag_debug_noleak.pl index cdd1f209a..c9332269f 100755 --- a/test_regress/t/t_flag_debug_noleak.pl +++ b/test_regress/t/t_flag_debug_noleak.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_flag_debug_noleak.v b/test_regress/t/t_flag_debug_noleak.v index 6b8661775..207a1d8d6 100644 --- a/test_regress/t/t_flag_debug_noleak.v +++ b/test_regress/t/t_flag_debug_noleak.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; initial begin diff --git a/test_regress/t/t_flag_debugi9.pl b/test_regress/t/t_flag_debugi9.pl index cc772d533..b1b26e37e 100755 --- a/test_regress/t/t_flag_debugi9.pl +++ b/test_regress/t/t_flag_debugi9.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_flag_debugi9.v b/test_regress/t/t_flag_debugi9.v index 5d61f1f0d..dcff6d1ff 100644 --- a/test_regress/t/t_flag_debugi9.v +++ b/test_regress/t/t_flag_debugi9.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_flag_define.pl b/test_regress/t/t_flag_define.pl index 59d1d460b..59730598d 100755 --- a/test_regress/t/t_flag_define.pl +++ b/test_regress/t/t_flag_define.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_define.v b/test_regress/t/t_flag_define.v index 11a163184..f837114b6 100644 --- a/test_regress/t/t_flag_define.v +++ b/test_regress/t/t_flag_define.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // // Special cases of "string parameters" : // This table compares obtain results from big-3 simulators to Verilator diff --git a/test_regress/t/t_flag_errorlimit_bad.out b/test_regress/t/t_flag_errorlimit_bad.out index e25846d3d..13e32a4b7 100644 --- a/test_regress/t/t_flag_errorlimit_bad.out +++ b/test_regress/t/t_flag_errorlimit_bad.out @@ -1,13 +1,13 @@ -%Error: t/t_flag_errorlimit_bad.v:9: Duplicate declaration of signal: 'u1' - int u1; - ^~ - t/t_flag_errorlimit_bad.v:8: ... Location of original declaration - int u1; - ^~ -%Error: t/t_flag_errorlimit_bad.v:10: Duplicate declaration of signal: 'u1' - int u1; - ^~ - t/t_flag_errorlimit_bad.v:8: ... Location of original declaration - int u1; - ^~ +%Error: t/t_flag_errorlimit_bad.v:10:8: Duplicate declaration of signal: 'u1' + 10 | int u1; + | ^~ + t/t_flag_errorlimit_bad.v:9:8: ... Location of original declaration + 9 | int u1; + | ^~ +%Error: t/t_flag_errorlimit_bad.v:11:8: Duplicate declaration of signal: 'u1' + 11 | int u1; + | ^~ + t/t_flag_errorlimit_bad.v:9:8: ... Location of original declaration + 9 | int u1; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_flag_errorlimit_bad.pl b/test_regress/t/t_flag_errorlimit_bad.pl index cc0276c3a..653eef863 100755 --- a/test_regress/t/t_flag_errorlimit_bad.pl +++ b/test_regress/t/t_flag_errorlimit_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_errorlimit_bad.v b/test_regress/t/t_flag_errorlimit_bad.v index 2d3897457..112d2a878 100644 --- a/test_regress/t/t_flag_errorlimit_bad.v +++ b/test_regress/t/t_flag_errorlimit_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_flag_f.pl b/test_regress/t/t_flag_f.pl index d153e1bfe..7bd3df43d 100755 --- a/test_regress/t/t_flag_f.pl +++ b/test_regress/t/t_flag_f.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_f.v b/test_regress/t/t_flag_f.v index 5532d93da..e5ec47252 100644 --- a/test_regress/t/t_flag_f.v +++ b/test_regress/t/t_flag_f.v @@ -1,4 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "t_flag_f_tsub_inc.v" diff --git a/test_regress/t/t_flag_fi.cpp b/test_regress/t/t_flag_fi.cpp index f25e4b8d9..afad2c751 100644 --- a/test_regress/t/t_flag_fi.cpp +++ b/test_regress/t/t_flag_fi.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include "Vt_flag_fi.h" diff --git a/test_regress/t/t_flag_fi.pl b/test_regress/t/t_flag_fi.pl index 8acd952d7..5c9a2eb79 100755 --- a/test_regress/t/t_flag_fi.pl +++ b/test_regress/t/t_flag_fi.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_fi.v b/test_regress/t/t_flag_fi.v index 5ff06341e..bc826453a 100644 --- a/test_regress/t/t_flag_fi.v +++ b/test_regress/t/t_flag_fi.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (); initial begin diff --git a/test_regress/t/t_flag_fi_h.h b/test_regress/t/t_flag_fi_h.h index 3bbbeb84d..c92f7df3f 100644 --- a/test_regress/t/t_flag_fi_h.h +++ b/test_regress/t/t_flag_fi_h.h @@ -3,13 +3,9 @@ // // Copyright 2010-2017 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_future.pl b/test_regress/t/t_flag_future.pl index 6549e85d5..79d997082 100755 --- a/test_regress/t/t_flag_future.pl +++ b/test_regress/t/t_flag_future.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_future.v b/test_regress/t/t_flag_future.v index 4394b97df..ced0789ef 100644 --- a/test_regress/t/t_flag_future.v +++ b/test_regress/t/t_flag_future.v @@ -1,4 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; initial begin diff --git a/test_regress/t/t_flag_generate_key.pl b/test_regress/t/t_flag_generate_key.pl index d64a3bcee..75e3e2ae5 100755 --- a/test_regress/t/t_flag_generate_key.pl +++ b/test_regress/t/t_flag_generate_key.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_getenv.pl b/test_regress/t/t_flag_getenv.pl index 275affb39..c3a98bf4c 100755 --- a/test_regress/t/t_flag_getenv.pl +++ b/test_regress/t/t_flag_getenv.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_getenv.v b/test_regress/t/t_flag_getenv.v index 99a0ead12..5a0ce9330 100644 --- a/test_regress/t/t_flag_getenv.v +++ b/test_regress/t/t_flag_getenv.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define EMPTY 1 diff --git a/test_regress/t/t_flag_help.pl b/test_regress/t/t_flag_help.pl index c412c69c9..892719b3d 100755 --- a/test_regress/t/t_flag_help.pl +++ b/test_regress/t/t_flag_help.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_flag_language.pl b/test_regress/t/t_flag_language.pl index f0482a0e5..e38b29c49 100755 --- a/test_regress/t/t_flag_language.pl +++ b/test_regress/t/t_flag_language.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_language.v b/test_regress/t/t_flag_language.v index 4c3c8b6ef..4ec92c10e 100644 --- a/test_regress/t/t_flag_language.v +++ b/test_regress/t/t_flag_language.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_flag_ldflags.pl b/test_regress/t/t_flag_ldflags.pl index 16617b8ae..11db30326 100755 --- a/test_regress/t/t_flag_ldflags.pl +++ b/test_regress/t/t_flag_ldflags.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_ldflags.v b/test_regress/t/t_flag_ldflags.v index 1efc403bf..743c908a6 100644 --- a/test_regress/t/t_flag_ldflags.v +++ b/test_regress/t/t_flag_ldflags.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import "DPI-C" pure function void dpii_a_library(); import "DPI-C" pure function void dpii_c_library(); diff --git a/test_regress/t/t_flag_ldflags_a.cpp b/test_regress/t/t_flag_ldflags_a.cpp index bae28918f..10d3b3ddd 100644 --- a/test_regress/t/t_flag_ldflags_a.cpp +++ b/test_regress/t/t_flag_ldflags_a.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_ldflags_c.cpp b/test_regress/t/t_flag_ldflags_c.cpp index bf88d0e54..fa62acc3f 100644 --- a/test_regress/t/t_flag_ldflags_c.cpp +++ b/test_regress/t/t_flag_ldflags_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_ldflags_so.cpp b/test_regress/t/t_flag_ldflags_so.cpp index 144ba7de2..d9b2707cf 100644 --- a/test_regress/t/t_flag_ldflags_so.cpp +++ b/test_regress/t/t_flag_ldflags_so.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_flag_lib.pl b/test_regress/t/t_flag_lib.pl index 70632d38a..9d7f3a43d 100755 --- a/test_regress/t/t_flag_lib.pl +++ b/test_regress/t/t_flag_lib.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_lib.v b/test_regress/t/t_flag_lib.v index 012bf7104..690c0a3f3 100644 --- a/test_regress/t/t_flag_lib.v +++ b/test_regress/t/t_flag_lib.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_flag_libinc.v b/test_regress/t/t_flag_libinc.v index 26769e48b..09a864841 100644 --- a/test_regress/t/t_flag_libinc.v +++ b/test_regress/t/t_flag_libinc.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module liblib_a (/*AUTOARG*/); liblib_b b (); diff --git a/test_regress/t/t_flag_make_cmake.pl b/test_regress/t/t_flag_make_cmake.pl index 2acfd49b2..57d2f2d05 100755 --- a/test_regress/t/t_flag_make_cmake.pl +++ b/test_regress/t/t_flag_make_cmake.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_flag_make_cmake.v b/test_regress/t/t_flag_make_cmake.v index 51d5f55fe..2478ff819 100644 --- a/test_regress/t/t_flag_make_cmake.v +++ b/test_regress/t/t_flag_make_cmake.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_flag_make_cmake_sc.pl b/test_regress/t/t_flag_make_cmake_sc.pl index 1ece57841..da8bc690f 100755 --- a/test_regress/t/t_flag_make_cmake_sc.pl +++ b/test_regress/t/t_flag_make_cmake_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This test tests CMake support for SystemC diff --git a/test_regress/t/t_flag_make_cmake_sc.v b/test_regress/t/t_flag_make_cmake_sc.v index 51d5f55fe..2478ff819 100644 --- a/test_regress/t/t_flag_make_cmake_sc.v +++ b/test_regress/t/t_flag_make_cmake_sc.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_flag_names.pl b/test_regress/t/t_flag_names.pl index 150ac0668..ed0b5ca60 100755 --- a/test_regress/t/t_flag_names.pl +++ b/test_regress/t/t_flag_names.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_names.v b/test_regress/t/t_flag_names.v index 8f83f05ca..d8d17edfb 100644 --- a/test_regress/t/t_flag_names.v +++ b/test_regress/t/t_flag_names.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; sub sub (); diff --git a/test_regress/t/t_flag_nomod_bad.pl b/test_regress/t/t_flag_nomod_bad.pl index 72de436c6..30a536839 100755 --- a/test_regress/t/t_flag_nomod_bad.pl +++ b/test_regress/t/t_flag_nomod_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_nomod_bad.v b/test_regress/t/t_flag_nomod_bad.v index 99a0ead12..5a0ce9330 100644 --- a/test_regress/t/t_flag_nomod_bad.v +++ b/test_regress/t/t_flag_nomod_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define EMPTY 1 diff --git a/test_regress/t/t_flag_parameter.pl b/test_regress/t/t_flag_parameter.pl index 6152aa8ec..a993d37e9 100755 --- a/test_regress/t/t_flag_parameter.pl +++ b/test_regress/t/t_flag_parameter.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_parameter.v b/test_regress/t/t_flag_parameter.v index faad97e97..0ac314b7f 100644 --- a/test_regress/t/t_flag_parameter.v +++ b/test_regress/t/t_flag_parameter.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // // Special cases of "string parameters" : // This table compares obtain results from big-3 simulators to Verilator diff --git a/test_regress/t/t_flag_parameter_bad.pl b/test_regress/t/t_flag_parameter_bad.pl index 416b73cf0..9e7b3230a 100755 --- a/test_regress/t/t_flag_parameter_bad.pl +++ b/test_regress/t/t_flag_parameter_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_quiet_exit.pl b/test_regress/t/t_flag_quiet_exit.pl index 79327f42c..c4334956d 100755 --- a/test_regress/t/t_flag_quiet_exit.pl +++ b/test_regress/t/t_flag_quiet_exit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); @@ -16,10 +17,10 @@ top_filename("t/t_file_does_not_exist.v"); compile( v_flags2 => ["--quiet-exit"], fails => 1, - expect => -'%Error: Exiting due to \d+ error\(s\) -((?!Command Failed).)*$', ); +file_grep_not("$Self->{obj_dir}/vlt_compile.log", qr/Exiting due to/); +file_grep_not("$Self->{obj_dir}/vlt_compile.log", qr/Command Failed/); + ok(1); 1; diff --git a/test_regress/t/t_flag_relinc.pl b/test_regress/t/t_flag_relinc.pl index b1f547b3e..de6aff6d2 100755 --- a/test_regress/t/t_flag_relinc.pl +++ b/test_regress/t/t_flag_relinc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_relinc.v b/test_regress/t/t_flag_relinc.v index c9cdf700f..477af105f 100644 --- a/test_regress/t/t_flag_relinc.v +++ b/test_regress/t/t_flag_relinc.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; t_flag_relinc_sub sub (); diff --git a/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v b/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v index dd38e5e9d..84a4c77df 100644 --- a/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v +++ b/test_regress/t/t_flag_relinc_dir/chip/t_flag_relinc_sub.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `include "../include/t_flag_relinc.vh" diff --git a/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh b/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh index 6a19cfbdc..af1265d3e 100644 --- a/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh +++ b/test_regress/t/t_flag_relinc_dir/include/t_flag_relinc.vh @@ -4,5 +4,6 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define all_finished $write("*-* All Finished *-*\n") diff --git a/test_regress/t/t_flag_skipidentical.pl b/test_regress/t/t_flag_skipidentical.pl index 669423342..93d5d8b3d 100755 --- a/test_regress/t/t_flag_skipidentical.pl +++ b/test_regress/t/t_flag_skipidentical.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_skipidentical.v b/test_regress/t/t_flag_skipidentical.v index 7e30bb838..e5613cfd9 100644 --- a/test_regress/t/t_flag_skipidentical.v +++ b/test_regress/t/t_flag_skipidentical.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_flag_stats.pl b/test_regress/t/t_flag_stats.pl index addaf5a47..180d46aef 100755 --- a/test_regress/t/t_flag_stats.pl +++ b/test_regress/t/t_flag_stats.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_flag_stats.v b/test_regress/t/t_flag_stats.v index 2bd129e5d..319e410ff 100644 --- a/test_regress/t/t_flag_stats.v +++ b/test_regress/t/t_flag_stats.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (b); output reg [31:0] b; diff --git a/test_regress/t/t_flag_topmod2_bad.pl b/test_regress/t/t_flag_topmod2_bad.pl index e2811ebe0..a9293d164 100755 --- a/test_regress/t/t_flag_topmod2_bad.pl +++ b/test_regress/t/t_flag_topmod2_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_topmod2_bad.v b/test_regress/t/t_flag_topmod2_bad.v index 9933baf82..3d19fd0f5 100644 --- a/test_regress/t/t_flag_topmod2_bad.v +++ b/test_regress/t/t_flag_topmod2_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module a_top; a a (); diff --git a/test_regress/t/t_flag_topmodule.pl b/test_regress/t/t_flag_topmodule.pl index 8a29e5b05..6bb6f3756 100755 --- a/test_regress/t/t_flag_topmodule.pl +++ b/test_regress/t/t_flag_topmodule.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_topmodule.v b/test_regress/t/t_flag_topmodule.v index ba3e5b7f2..403ab4299 100644 --- a/test_regress/t/t_flag_topmodule.v +++ b/test_regress/t/t_flag_topmodule.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module a; c c (); diff --git a/test_regress/t/t_flag_topmodule_bad.out b/test_regress/t/t_flag_topmodule_bad.out index c4aed56b2..181364e4b 100644 --- a/test_regress/t/t_flag_topmodule_bad.out +++ b/test_regress/t/t_flag_topmodule_bad.out @@ -1,13 +1,13 @@ -%Warning-MULTITOP: t/t_flag_topmodule.v:14: Multiple top level modules - : ... Suggest see manual; fix the duplicates, or use --top-module to select top. +%Warning-MULTITOP: t/t_flag_topmodule.v:15:8: Multiple top level modules + : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. - : ... Top module 'a' -module a; - ^ - : ... Top module 'a2' -module a2; - ^~ - : ... Top module 'b' -module b; - ^ + : ... Top module 'a' + 7 | module a; + | ^ + : ... Top module 'a2' + 15 | module a2; + | ^~ + : ... Top module 'b' + 22 | module b; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_flag_topmodule_bad.pl b/test_regress/t/t_flag_topmodule_bad.pl index 1c769951e..578dc7df5 100755 --- a/test_regress/t/t_flag_topmodule_bad.pl +++ b/test_regress/t/t_flag_topmodule_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_topmodule_bad2.pl b/test_regress/t/t_flag_topmodule_bad2.pl index c4368e07a..f0bd89460 100755 --- a/test_regress/t/t_flag_topmodule_bad2.pl +++ b/test_regress/t/t_flag_topmodule_bad2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_topmodule_inline.pl b/test_regress/t/t_flag_topmodule_inline.pl index 71014e108..89b5d9b8b 100755 --- a/test_regress/t/t_flag_topmodule_inline.pl +++ b/test_regress/t/t_flag_topmodule_inline.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_topmodule_inline.v b/test_regress/t/t_flag_topmodule_inline.v index 1b9b737ea..45904e3ae 100644 --- a/test_regress/t/t_flag_topmodule_inline.v +++ b/test_regress/t/t_flag_topmodule_inline.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module a; a2 a2 (.tmp(1'b0)); diff --git a/test_regress/t/t_flag_version.pl b/test_regress/t/t_flag_version.pl index bb391902e..0c6cd25d4 100755 --- a/test_regress/t/t_flag_version.pl +++ b/test_regress/t/t_flag_version.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_flag_werror.v b/test_regress/t/t_flag_werror.v index 11acd8683..6ce736c79 100644 --- a/test_regress/t/t_flag_werror.v +++ b/test_regress/t/t_flag_werror.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_flag_werror_bad1.out b/test_regress/t/t_flag_werror_bad1.out index 3e2f8ee87..389d69336 100644 --- a/test_regress/t/t_flag_werror_bad1.out +++ b/test_regress/t/t_flag_werror_bad1.out @@ -1,6 +1,6 @@ -%Warning-WIDTH: t/t_flag_werror.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. - : ... In instance t - wire [3:0] foo = 6'h2e; - ^ +%Warning-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. + : ... In instance t + 10 | wire [3:0] foo = 6'h2e; + | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_flag_werror_bad1.pl b/test_regress/t/t_flag_werror_bad1.pl index 3b23709db..7ad23029f 100755 --- a/test_regress/t/t_flag_werror_bad1.pl +++ b/test_regress/t/t_flag_werror_bad1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_werror_bad2.out b/test_regress/t/t_flag_werror_bad2.out index bca8ecd32..9bf134b8b 100644 --- a/test_regress/t/t_flag_werror_bad2.out +++ b/test_regress/t/t_flag_werror_bad2.out @@ -1,5 +1,5 @@ -%Error-WIDTH: t/t_flag_werror.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. - : ... In instance t - wire [3:0] foo = 6'h2e; - ^ +%Error-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. + : ... In instance t + 10 | wire [3:0] foo = 6'h2e; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_flag_werror_bad2.pl b/test_regress/t/t_flag_werror_bad2.pl index daa93d9d7..c78346b14 100755 --- a/test_regress/t/t_flag_werror_bad2.pl +++ b/test_regress/t/t_flag_werror_bad2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_wfatal.out b/test_regress/t/t_flag_wfatal.out index bd41eb431..78410d838 100644 --- a/test_regress/t/t_flag_wfatal.out +++ b/test_regress/t/t_flag_wfatal.out @@ -1,5 +1,5 @@ -%Warning-WIDTH: t/t_flag_wfatal.v:9: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. - : ... In instance t - wire [3:0] foo = 6'h2e; - ^ +%Warning-WIDTH: t/t_flag_wfatal.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits. + : ... In instance t + 10 | wire [3:0] foo = 6'h2e; + | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_flag_wfatal.pl b/test_regress/t/t_flag_wfatal.pl index 4f4877afc..c56ff93f2 100755 --- a/test_regress/t/t_flag_wfatal.pl +++ b/test_regress/t/t_flag_wfatal.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_wfatal.v b/test_regress/t/t_flag_wfatal.v index 11acd8683..6ce736c79 100644 --- a/test_regress/t/t_flag_wfatal.v +++ b/test_regress/t/t_flag_wfatal.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_flag_woff.pl b/test_regress/t/t_flag_woff.pl index 3de9ecfaa..5a203983f 100755 --- a/test_regress/t/t_flag_woff.pl +++ b/test_regress/t/t_flag_woff.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_woff.v b/test_regress/t/t_flag_woff.v index 7c2936dd1..1626c524c 100644 --- a/test_regress/t/t_flag_woff.v +++ b/test_regress/t/t_flag_woff.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_flag_wpedantic_bad.out b/test_regress/t/t_flag_wpedantic_bad.out index 26e8ff0ae..4e9ac3f1b 100644 --- a/test_regress/t/t_flag_wpedantic_bad.out +++ b/test_regress/t/t_flag_wpedantic_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_flag_wpedantic_bad.v:7: syntax error, unexpected global, expecting IDENTIFIER or '=' or do or final - reg global; - ^ +%Error: t/t_flag_wpedantic_bad.v:8:14: syntax error, unexpected global, expecting IDENTIFIER or '=' or do or final + 8 | reg global; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_flag_wpedantic_bad.pl b/test_regress/t/t_flag_wpedantic_bad.pl index 18439afa9..bbd90df9f 100755 --- a/test_regress/t/t_flag_wpedantic_bad.pl +++ b/test_regress/t/t_flag_wpedantic_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_flag_wpedantic_bad.v b/test_regress/t/t_flag_wpedantic_bad.v index c21e4805b..5a0f604bc 100644 --- a/test_regress/t/t_flag_wpedantic_bad.v +++ b/test_regress/t/t_flag_wpedantic_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg global; diff --git a/test_regress/t/t_flag_xinitial_0.pl b/test_regress/t/t_flag_xinitial_0.pl index d0101e92b..4ef44eb49 100755 --- a/test_regress/t/t_flag_xinitial_0.pl +++ b/test_regress/t/t_flag_xinitial_0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_flag_xinitial_0.v b/test_regress/t/t_flag_xinitial_0.v index fed402a34..1d3bcc9f5 100644 --- a/test_regress/t/t_flag_xinitial_0.v +++ b/test_regress/t/t_flag_xinitial_0.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_flag_xinitial_unique.pl b/test_regress/t/t_flag_xinitial_unique.pl index 1c0e7f4ab..9cc7391f5 100755 --- a/test_regress/t/t_flag_xinitial_unique.pl +++ b/test_regress/t/t_flag_xinitial_unique.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_flag_xinitial_unique.v b/test_regress/t/t_flag_xinitial_unique.v index a23f071ad..04321788a 100644 --- a/test_regress/t/t_flag_xinitial_unique.v +++ b/test_regress/t/t_flag_xinitial_unique.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_for_break.pl b/test_regress/t/t_for_break.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_for_break.pl +++ b/test_regress/t/t_for_break.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_for_break.v b/test_regress/t/t_for_break.v index 748be3015..0e2084e9d 100644 --- a/test_regress/t/t_for_break.v +++ b/test_regress/t/t_for_break.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_for_comma_bad.out b/test_regress/t/t_for_comma_bad.out index 8549edd19..542c67fbb 100644 --- a/test_regress/t/t_for_comma_bad.out +++ b/test_regress/t/t_for_comma_bad.out @@ -1,28 +1,28 @@ -%Error: t/t_for_comma_bad.v:13: Unsupported: for loop step after the first comma - for (; ; a=a+1, b=b+1) ; - ^ -%Error: t/t_for_comma_bad.v:16: Unsupported: for loop step after the first comma - for (; a<1; a=a+1, b=b+1) ; - ^ -%Error: t/t_for_comma_bad.v:19: Unsupported: for loop step after the first comma - for (a=0; a<1; a=a+1, b=b+1) ; - ^ -%Error: t/t_for_comma_bad.v:22: Unsupported: for loop step after the first comma - for (integer a=0; a<1; a=a+1, b=b+1) ; - ^ -%Error: t/t_for_comma_bad.v:25: Unsupported: for loop step after the first comma - for (var integer a=0; a<1; a=a+1, b=b+1) ; - ^ -%Error: t/t_for_comma_bad.v:26: Unsupported: for loop initialization after the first comma - for (integer a=0, integer b=0; a<1; ) ; - ^ -%Error: t/t_for_comma_bad.v:27: Unsupported: for loop initialization after the first comma - for (integer a=0, integer b=0; a<1; a=a+1) ; - ^ -%Error: t/t_for_comma_bad.v:28: Unsupported: for loop initialization after the first comma - for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ; - ^ -%Error: t/t_for_comma_bad.v:28: Unsupported: for loop step after the first comma - for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ; - ^ +%Error: t/t_for_comma_bad.v:14:16: Unsupported: for loop step after the first comma + 14 | for (; ; a=a+1, b=b+1) ; + | ^ +%Error: t/t_for_comma_bad.v:17:19: Unsupported: for loop step after the first comma + 17 | for (; a<1; a=a+1, b=b+1) ; + | ^ +%Error: t/t_for_comma_bad.v:20:22: Unsupported: for loop step after the first comma + 20 | for (a=0; a<1; a=a+1, b=b+1) ; + | ^ +%Error: t/t_for_comma_bad.v:23:30: Unsupported: for loop step after the first comma + 23 | for (integer a=0; a<1; a=a+1, b=b+1) ; + | ^ +%Error: t/t_for_comma_bad.v:26:34: Unsupported: for loop step after the first comma + 26 | for (var integer a=0; a<1; a=a+1, b=b+1) ; + | ^ +%Error: t/t_for_comma_bad.v:27:23: Unsupported: for loop initialization after the first comma + 27 | for (integer a=0, integer b=0; a<1; ) ; + | ^ +%Error: t/t_for_comma_bad.v:28:23: Unsupported: for loop initialization after the first comma + 28 | for (integer a=0, integer b=0; a<1; a=a+1) ; + | ^ +%Error: t/t_for_comma_bad.v:29:23: Unsupported: for loop initialization after the first comma + 29 | for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ; + | ^ +%Error: t/t_for_comma_bad.v:29:43: Unsupported: for loop step after the first comma + 29 | for (integer a=0, integer b=0; a<1; a=a+1, b=b+1) ; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_for_comma_bad.pl b/test_regress/t/t_for_comma_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_for_comma_bad.pl +++ b/test_regress/t/t_for_comma_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_for_comma_bad.v b/test_regress/t/t_for_comma_bad.v index 3fec79887..384b9c517 100644 --- a/test_regress/t/t_for_comma_bad.v +++ b/test_regress/t/t_for_comma_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_for_count.pl b/test_regress/t/t_for_count.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_for_count.pl +++ b/test_regress/t/t_for_count.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_for_count.v b/test_regress/t/t_for_count.v index 99ac6d48c..c294853dc 100644 --- a/test_regress/t/t_for_count.v +++ b/test_regress/t/t_for_count.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_for_funcbound.pl b/test_regress/t/t_for_funcbound.pl index 808880367..5325f14e3 100755 --- a/test_regress/t/t_for_funcbound.pl +++ b/test_regress/t/t_for_funcbound.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_for_funcbound.v b/test_regress/t/t_for_funcbound.v index 5a098d433..b2eba60c3 100644 --- a/test_regress/t/t_for_funcbound.v +++ b/test_regress/t/t_for_funcbound.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_for_init_bug.pl b/test_regress/t/t_for_init_bug.pl index 47d4dd0ff..3d67ac05c 100755 --- a/test_regress/t/t_for_init_bug.pl +++ b/test_regress/t/t_for_init_bug.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_for_init_bug.v b/test_regress/t/t_for_init_bug.v index b00eeb2fd..9a3eab084 100644 --- a/test_regress/t/t_for_init_bug.v +++ b/test_regress/t/t_for_init_bug.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_for_local.pl b/test_regress/t/t_for_local.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_for_local.pl +++ b/test_regress/t/t_for_local.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_for_local.v b/test_regress/t/t_for_local.v index de6985173..94a2eb99d 100644 --- a/test_regress/t/t_for_local.v +++ b/test_regress/t/t_for_local.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_for_loop.pl b/test_regress/t/t_for_loop.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_for_loop.pl +++ b/test_regress/t/t_for_loop.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_for_loop.v b/test_regress/t/t_for_loop.v index 5cc70b77c..5de42aa49 100644 --- a/test_regress/t/t_for_loop.v +++ b/test_regress/t/t_for_loop.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_foreach.pl b/test_regress/t/t_foreach.pl index 44209520b..57f86352f 100755 --- a/test_regress/t/t_foreach.pl +++ b/test_regress/t/t_foreach.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_foreach.v b/test_regress/t/t_foreach.v index e6dcc5cfd..7055386c1 100644 --- a/test_regress/t/t_foreach.v +++ b/test_regress/t/t_foreach.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_func.pl b/test_regress/t/t_func.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func.pl +++ b/test_regress/t/t_func.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func.v b/test_regress/t/t_func.v index c9b71194f..c13221fdf 100644 --- a/test_regress/t/t_func.v +++ b/test_regress/t/t_func.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; reg [2:0] value; diff --git a/test_regress/t/t_func_bad.out b/test_regress/t/t_func_bad.out index 382023e2f..bf300bf2e 100644 --- a/test_regress/t/t_func_bad.out +++ b/test_regress/t/t_func_bad.out @@ -1,29 +1,29 @@ -%Error: t/t_func_bad.v:8: Missing argument on non-defaulted argument 'from2' in function call to FUNC 'add' - : ... In instance t - if (add(3'd1) != 0) $stop; - ^~~ -%Error: t/t_func_bad.v:9: Too many arguments in function call to FUNC 'add' - : ... In instance t - if (add(3'd1, 3'd2, 3'd3) != 0) $stop; - ^~~~ -%Error: t/t_func_bad.v:10: Missing argument on non-defaulted argument 'y' in function call to TASK 'x' - : ... In instance t - x; - ^ -%Error: t/t_func_bad.v:10: Unsupported: Function output argument 'y' requires 1 bits, but connection's CONST '?32?h0' generates 32 bits. - : ... In instance t - x; - ^ -%Error: t/t_func_bad.v:13: No such argument 'no_such' in function call to FUNC 'f' - : ... In instance t - f(.j(1), .no_such(2)); - ^~~~~~~ -%Error: t/t_func_bad.v:14: Duplicate argument 'dup' in function call to FUNC 'f' - : ... In instance t - f(.dup(1), .dup(3)); - ^~~ -%Error: t/t_func_bad.v:15: Too many arguments in function call to FUNC 'f' - : ... In instance t - f(1,2,3); - ^ +%Error: t/t_func_bad.v:9:11: Missing argument on non-defaulted argument 'from2' in function call to FUNC 'add' + : ... In instance t + 9 | if (add(3'd1) != 0) $stop; + | ^~~ +%Error: t/t_func_bad.v:10:27: Too many arguments in function call to FUNC 'add' + : ... In instance t + 10 | if (add(3'd1, 3'd2, 3'd3) != 0) $stop; + | ^~~~ +%Error: t/t_func_bad.v:11:7: Missing argument on non-defaulted argument 'y' in function call to TASK 'x' + : ... In instance t + 11 | x; + | ^ +%Error: t/t_func_bad.v:11:7: Unsupported: Function output argument 'y' requires 1 bits, but connection's CONST '?32?h0' generates 32 bits. + : ... In instance t + 11 | x; + | ^ +%Error: t/t_func_bad.v:14:17: No such argument 'no_such' in function call to FUNC 'f' + : ... In instance t + 14 | f(.j(1), .no_such(2)); + | ^~~~~~~ +%Error: t/t_func_bad.v:15:19: Duplicate argument 'dup' in function call to FUNC 'f' + : ... In instance t + 15 | f(.dup(1), .dup(3)); + | ^~~ +%Error: t/t_func_bad.v:16:13: Too many arguments in function call to FUNC 'f' + : ... In instance t + 16 | f(1,2,3); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_func_bad.pl b/test_regress/t/t_func_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_func_bad.pl +++ b/test_regress/t/t_func_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_bad.v b/test_regress/t/t_func_bad.v index 4ed56fa43..d16ecd5e2 100644 --- a/test_regress/t/t_func_bad.v +++ b/test_regress/t/t_func_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; initial begin diff --git a/test_regress/t/t_func_bad2.out b/test_regress/t/t_func_bad2.out index 012ba7557..c354564b7 100644 --- a/test_regress/t/t_func_bad2.out +++ b/test_regress/t/t_func_bad2.out @@ -1,5 +1,5 @@ -%Error: t/t_func_bad2.v:7: Unsupported: Recursive function or task call - : ... In instance t - function recurse; - ^~~~~~~ +%Error: t/t_func_bad2.v:8:13: Unsupported: Recursive function or task call + : ... In instance t + 8 | function recurse; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_bad2.pl b/test_regress/t/t_func_bad2.pl index 43933e6ae..c1dba4c49 100755 --- a/test_regress/t/t_func_bad2.pl +++ b/test_regress/t/t_func_bad2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_bad2.v b/test_regress/t/t_func_bad2.v index b90fa084c..19ead4dd4 100644 --- a/test_regress/t/t_func_bad2.v +++ b/test_regress/t/t_func_bad2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; function recurse; diff --git a/test_regress/t/t_func_bad_width.out b/test_regress/t/t_func_bad_width.out index c7c0a9535..8948c688a 100644 --- a/test_regress/t/t_func_bad_width.out +++ b/test_regress/t/t_func_bad_width.out @@ -1,10 +1,10 @@ -%Warning-WIDTH: t/t_func_bad_width.v:12: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits. - : ... In instance t - out = MUX (in); - ^~~ +%Warning-WIDTH: t/t_func_bad_width.v:13:13: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits. + : ... In instance t + 13 | out = MUX (in); + | ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_func_bad_width.v:12: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. - : ... In instance t - out = MUX (in); - ^ +%Warning-WIDTH: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. + : ... In instance t + 13 | out = MUX (in); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_func_bad_width.pl b/test_regress/t/t_func_bad_width.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_func_bad_width.pl +++ b/test_regress/t/t_func_bad_width.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_bad_width.v b/test_regress/t/t_func_bad_width.v index 163d9ff5f..22d9af299 100644 --- a/test_regress/t/t_func_bad_width.v +++ b/test_regress/t/t_func_bad_width.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_begin2.pl b/test_regress/t/t_func_begin2.pl index c5fa3f628..204f3112f 100755 --- a/test_regress/t/t_func_begin2.pl +++ b/test_regress/t/t_func_begin2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_begin2.v b/test_regress/t/t_func_begin2.v index 57f5f3c02..605eade03 100644 --- a/test_regress/t/t_func_begin2.v +++ b/test_regress/t/t_func_begin2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module init; diff --git a/test_regress/t/t_func_check.pl b/test_regress/t/t_func_check.pl index 06f37f010..623d7bbeb 100755 --- a/test_regress/t/t_func_check.pl +++ b/test_regress/t/t_func_check.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_check.v b/test_regress/t/t_func_check.v index 32e391d15..05b1ac9f8 100644 --- a/test_regress/t/t_func_check.v +++ b/test_regress/t/t_func_check.v @@ -1,4 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH // verilator lint_off VARHIDDEN diff --git a/test_regress/t/t_func_const.pl b/test_regress/t/t_func_const.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_const.pl +++ b/test_regress/t/t_func_const.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_const.v b/test_regress/t/t_func_const.v index fa0ed25e7..8fc23468e 100644 --- a/test_regress/t/t_func_const.v +++ b/test_regress/t/t_func_const.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 package testpackage; localparam PARAM = 1024 >> 3; diff --git a/test_regress/t/t_func_const2_bad.out b/test_regress/t/t_func_const2_bad.out index 41cf4ff10..8efe45a6e 100644 --- a/test_regress/t/t_func_const2_bad.out +++ b/test_regress/t/t_func_const2_bad.out @@ -1,15 +1,15 @@ %Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const2_bad.v:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' - : ... In instance t.b8_a7.c9 - t/t_func_const2_bad.v:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const2_bad.v:14: ... Called from f_add() with parameters: +%Error: t/t_func_const2_bad.v:22:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' + : ... In instance t.b8_a7.c9 + t/t_func_const2_bad.v:10:6: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const2_bad.v:15:13: ... Called from f_add() with parameters: a = 32'h7 b = 32'h8 - t/t_func_const2_bad.v:21: ... Called from f_add2() with parameters: + t/t_func_const2_bad.v:22:23: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - localparam SOMEP = f_add2(A, B, 9); - ^~~~~~ + 22 | localparam SOMEP = f_add2(A, B, 9); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const2_bad.pl b/test_regress/t/t_func_const2_bad.pl index 727a561fa..52ccee872 100755 --- a/test_regress/t/t_func_const2_bad.pl +++ b/test_regress/t/t_func_const2_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2017 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2017 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_const2_bad.v b/test_regress/t/t_func_const2_bad.v index 0c863b7ca..c90343878 100644 --- a/test_regress/t/t_func_const2_bad.v +++ b/test_regress/t/t_func_const2_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 function integer f_add(input [31:0] a, input [31:0] b); f_add = a+b; diff --git a/test_regress/t/t_func_const3_bad.out b/test_regress/t/t_func_const3_bad.out index cbf392c97..02585e023 100644 --- a/test_regress/t/t_func_const3_bad.out +++ b/test_regress/t/t_func_const3_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:11: More than a 8k bit replication is probably wrong: 9000 - : ... In instance t.b9k.c9 - localparam SOMEP = {BITS{1'b0}}; - ^ +%Warning-WIDTHCONCAT: t/t_func_const3_bad.v:12:28: More than a 8k bit replication is probably wrong: 9000 + : ... In instance t.b9k.c9 + 12 | localparam SOMEP = {BITS{1'b0}}; + | ^ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_func_const3_bad.pl b/test_regress/t/t_func_const3_bad.pl index e29c27375..d49d2e341 100755 --- a/test_regress/t/t_func_const3_bad.pl +++ b/test_regress/t/t_func_const3_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2017 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2017 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_const3_bad.v b/test_regress/t/t_func_const3_bad.v index f10970f62..9d6d7fe32 100644 --- a/test_regress/t/t_func_const3_bad.v +++ b/test_regress/t/t_func_const3_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module c9 #(parameter A = 1, diff --git a/test_regress/t/t_func_const_bad.out b/test_regress/t/t_func_const_bad.out index ba829d35c..9871a8a45 100644 --- a/test_regress/t/t_func_const_bad.out +++ b/test_regress/t/t_func_const_bad.out @@ -1,46 +1,46 @@ -%Error: t/t_func_const_bad.v:11: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_output' - : ... In instance t - t/t_func_const_bad.v:12: ... Location of non-constant VAR 'o': Language violation: Outputs/refs not allowed in constant functions - localparam B1 = f_bad_output(1,2); - ^~~~~~~~~~~~ -%Error: t/t_func_const_bad.v:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_dotted' - : ... In instance t - t/t_func_const_bad.v:22: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions - t/t_func_const_bad.v:20: ... Called from f_bad_dotted() with parameters: +%Error: t/t_func_const_bad.v:12:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_output' + : ... In instance t + t/t_func_const_bad.v:13:64: ... Location of non-constant VAR 'o': Language violation: Outputs/refs not allowed in constant functions + 12 | localparam B1 = f_bad_output(1,2); + | ^~~~~~~~~~~~ +%Error: t/t_func_const_bad.v:21:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_dotted' + : ... In instance t + t/t_func_const_bad.v:23:24: ... Location of non-constant VARXREF 'EIGHT': Language violation: Dotted hierarchical references not allowed in constant functions + t/t_func_const_bad.v:21:20: ... Called from f_bad_dotted() with parameters: a = ?32?h2 - localparam B2 = f_bad_dotted(2); - ^~~~~~~~~~~~ -%Error: t/t_func_const_bad.v:27: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_nonparam' - : ... In instance t - t/t_func_const_bad.v:29: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable - t/t_func_const_bad.v:27: ... Called from f_bad_nonparam() with parameters: + 21 | localparam B2 = f_bad_dotted(2); + | ^~~~~~~~~~~~ +%Error: t/t_func_const_bad.v:28:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_nonparam' + : ... In instance t + t/t_func_const_bad.v:30:24: ... Location of non-constant VARREF 'modvar': Language violation: reference to non-function-local variable + t/t_func_const_bad.v:28:20: ... Called from f_bad_nonparam() with parameters: a = ?32?h3 - localparam B3 = f_bad_nonparam(3); - ^~~~~~~~~~~~~~ -%Error: t/t_func_const_bad.v:35: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_infinite' - : ... In instance t - t/t_func_const_bad.v:37: ... Location of non-constant WHILE: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024 - t/t_func_const_bad.v:35: ... Called from f_bad_infinite() with parameters: + 28 | localparam B3 = f_bad_nonparam(3); + | ^~~~~~~~~~~~~~ +%Error: t/t_func_const_bad.v:36:20: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_infinite' + : ... In instance t + t/t_func_const_bad.v:38:7: ... Location of non-constant WHILE: Loop unrolling took too long; probably this is an infinite loop, or set --unroll-count above 1024 + t/t_func_const_bad.v:36:20: ... Called from f_bad_infinite() with parameters: a = ?32?h3 - localparam B4 = f_bad_infinite(3); - ^~~~~~~~~~~~~~ -%Error: t/t_func_const_bad.v:43: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_stop' - : ... In instance t - t/t_func_const_bad.v:45: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_bad.v:43: ... Called from f_bad_stop() with parameters: + 36 | localparam B4 = f_bad_infinite(3); + | ^~~~~~~~~~~~~~ +%Error: t/t_func_const_bad.v:44:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_stop' + : ... In instance t + t/t_func_const_bad.v:46:7: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_bad.v:44:23: ... Called from f_bad_stop() with parameters: a = ?32?h3 - localparam BSTOP = f_bad_stop(3); - ^~~~~~~~~~ + 44 | localparam BSTOP = f_bad_stop(3); + | ^~~~~~~~~~ -Info: "Printing in loop: 0" -Info: "Printing in loop: 1" -Info: "Printing in loop: 2" %Warning-USERFATAL: "Fatal Error" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const_bad.v:49: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal' - : ... In instance t - t/t_func_const_bad.v:54: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_bad.v:49: ... Called from f_bad_fatal() with parameters: +%Error: t/t_func_const_bad.v:50:24: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal' + : ... In instance t + t/t_func_const_bad.v:55:7: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_bad.v:50:24: ... Called from f_bad_fatal() with parameters: a = ?32?h3 - localparam BFATAL = f_bad_fatal(3); - ^~~~~~~~~~~ + 50 | localparam BFATAL = f_bad_fatal(3); + | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_bad.pl b/test_regress/t/t_func_const_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_func_const_bad.pl +++ b/test_regress/t/t_func_const_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_const_bad.v b/test_regress/t/t_func_const_bad.v index 3ef441f07..0334e46fa 100644 --- a/test_regress/t/t_func_const_bad.v +++ b/test_regress/t/t_func_const_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_const_packed_array_bad.out b/test_regress/t/t_func_const_packed_array_bad.out index 0c20156ca..25a3580a6 100644 --- a/test_regress/t/t_func_const_packed_array_bad.out +++ b/test_regress/t/t_func_const_packed_array_bad.out @@ -1,14 +1,14 @@ %Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const_packed_array_bad.v:11: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' - : ... In instance t - t/t_func_const_packed_array_bad.v:22: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_packed_array_bad.v:30: ... Called from f_add() with parameters: +%Error: t/t_func_const_packed_array_bad.v:12:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' + : ... In instance t + t/t_func_const_packed_array_bad.v:23:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_packed_array_bad.v:31:16: ... Called from f_add() with parameters: params = [0 = 32'h7, 1 = 32'h8] - t/t_func_const_packed_array_bad.v:11: ... Called from f_add2() with parameters: + t/t_func_const_packed_array_bad.v:12:21: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - localparam P24 = f_add2(7, 8, 9); - ^~~~~~ + 12 | localparam P24 = f_add2(7, 8, 9); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_packed_array_bad.pl b/test_regress/t/t_func_const_packed_array_bad.pl index 727a561fa..52ccee872 100755 --- a/test_regress/t/t_func_const_packed_array_bad.pl +++ b/test_regress/t/t_func_const_packed_array_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2017 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2017 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_const_packed_array_bad.v b/test_regress/t/t_func_const_packed_array_bad.v index 0ed2aa96c..25fbc4988 100644 --- a/test_regress/t/t_func_const_packed_array_bad.v +++ b/test_regress/t/t_func_const_packed_array_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_const_packed_struct_bad.out b/test_regress/t/t_func_const_packed_struct_bad.out index c31d93f62..48e0f996f 100644 --- a/test_regress/t/t_func_const_packed_struct_bad.out +++ b/test_regress/t/t_func_const_packed_struct_bad.out @@ -1,14 +1,14 @@ %Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const_packed_struct_bad.v:13: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' - : ... In instance t - t/t_func_const_packed_struct_bad.v:24: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_packed_struct_bad.v:32: ... Called from f_add() with parameters: +%Error: t/t_func_const_packed_struct_bad.v:14:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' + : ... In instance t + t/t_func_const_packed_struct_bad.v:25:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_packed_struct_bad.v:33:16: ... Called from f_add() with parameters: params = [0 = '{a: 32'h7, b: 32'h22b}, 1 = '{a: 32'h3039, b: 32'h8}] - t/t_func_const_packed_struct_bad.v:13: ... Called from f_add2() with parameters: + t/t_func_const_packed_struct_bad.v:14:21: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - localparam P24 = f_add2(7, 8, 9); - ^~~~~~ + 14 | localparam P24 = f_add2(7, 8, 9); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_packed_struct_bad.pl b/test_regress/t/t_func_const_packed_struct_bad.pl index 727a561fa..52ccee872 100755 --- a/test_regress/t/t_func_const_packed_struct_bad.pl +++ b/test_regress/t/t_func_const_packed_struct_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2017 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2017 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_const_packed_struct_bad.v b/test_regress/t/t_func_const_packed_struct_bad.v index 46d52cc3d..2ad2586ce 100644 --- a/test_regress/t/t_func_const_packed_struct_bad.v +++ b/test_regress/t/t_func_const_packed_struct_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_const_packed_struct_bad2.out b/test_regress/t/t_func_const_packed_struct_bad2.out index d84f42319..7e6d1dcb6 100644 --- a/test_regress/t/t_func_const_packed_struct_bad2.out +++ b/test_regress/t/t_func_const_packed_struct_bad2.out @@ -1,14 +1,14 @@ %Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const_packed_struct_bad2.v:19: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' - : ... In instance t - t/t_func_const_packed_struct_bad2.v:30: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_packed_struct_bad2.v:42: ... Called from f_add() with parameters: +%Error: t/t_func_const_packed_struct_bad2.v:20:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' + : ... In instance t + t/t_func_const_packed_struct_bad2.v:31:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_packed_struct_bad2.v:43:16: ... Called from f_add() with parameters: params = [0 = '{a: 32'h7, foo: 6'hb, sub_params: '{b: 32'h37, bar: 8'h6f}}, 1 = '{a: 32'h3039, foo: 6'hc, sub_params: '{b: 32'h8, bar: 8'h70}}] - t/t_func_const_packed_struct_bad2.v:19: ... Called from f_add2() with parameters: + t/t_func_const_packed_struct_bad2.v:20:21: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - localparam P24 = f_add2(7, 8, 9); - ^~~~~~ + 20 | localparam P24 = f_add2(7, 8, 9); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_packed_struct_bad2.pl b/test_regress/t/t_func_const_packed_struct_bad2.pl index 727a561fa..52ccee872 100755 --- a/test_regress/t/t_func_const_packed_struct_bad2.pl +++ b/test_regress/t/t_func_const_packed_struct_bad2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2017 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2017 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_const_packed_struct_bad2.v b/test_regress/t/t_func_const_packed_struct_bad2.v index 01a38a45d..77be332a6 100644 --- a/test_regress/t/t_func_const_packed_struct_bad2.v +++ b/test_regress/t/t_func_const_packed_struct_bad2.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_const_struct_bad.out b/test_regress/t/t_func_const_struct_bad.out index 2e00d5bf7..804a7d608 100644 --- a/test_regress/t/t_func_const_struct_bad.out +++ b/test_regress/t/t_func_const_struct_bad.out @@ -1,14 +1,14 @@ %Warning-USERFATAL: "f_add = 15" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_func_const_struct_bad.v:16: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' - : ... In instance t - t/t_func_const_struct_bad.v:27: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_func_const_struct_bad.v:37: ... Called from f_add() with parameters: +%Error: t/t_func_const_struct_bad.v:17:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' + : ... In instance t + t/t_func_const_struct_bad.v:28:9: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_func_const_struct_bad.v:38:16: ... Called from f_add() with parameters: params = '{a: 32'h7, b: 32'h8} - t/t_func_const_struct_bad.v:16: ... Called from f_add2() with parameters: + t/t_func_const_struct_bad.v:17:21: ... Called from f_add2() with parameters: a = ?32?h7 b = ?32?h8 c = ?32?h9 - localparam P24 = f_add2(7, 8, 9); - ^~~~~~ + 17 | localparam P24 = f_add2(7, 8, 9); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_const_struct_bad.pl b/test_regress/t/t_func_const_struct_bad.pl index 727a561fa..52ccee872 100755 --- a/test_regress/t/t_func_const_struct_bad.pl +++ b/test_regress/t/t_func_const_struct_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2017 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2017 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_const_struct_bad.v b/test_regress/t/t_func_const_struct_bad.v index c87514e26..c7e75afa5 100644 --- a/test_regress/t/t_func_const_struct_bad.v +++ b/test_regress/t/t_func_const_struct_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_crc.pl b/test_regress/t/t_func_crc.pl index 803dca735..d6841bed0 100755 --- a/test_regress/t/t_func_crc.pl +++ b/test_regress/t/t_func_crc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_crc.v b/test_regress/t/t_func_crc.v index 667b54a4f..21bc8a036 100644 --- a/test_regress/t/t_func_crc.v +++ b/test_regress/t/t_func_crc.v @@ -1,4 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_default_warn.pl b/test_regress/t/t_func_default_warn.pl index 5f07268a6..f142cc952 100755 --- a/test_regress/t/t_func_default_warn.pl +++ b/test_regress/t/t_func_default_warn.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_default_warn.v b/test_regress/t/t_func_default_warn.v index 3e555a093..bf7ff2eff 100644 --- a/test_regress/t/t_func_default_warn.v +++ b/test_regress/t/t_func_default_warn.v @@ -3,6 +3,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 function logic foo ( diff --git a/test_regress/t/t_func_defaults.pl b/test_regress/t/t_func_defaults.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_defaults.pl +++ b/test_regress/t/t_func_defaults.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_defaults.v b/test_regress/t/t_func_defaults.v index 5e3b60107..7928a0bce 100644 --- a/test_regress/t/t_func_defaults.v +++ b/test_regress/t/t_func_defaults.v @@ -3,6 +3,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 parameter logic Bar = 1'b1; diff --git a/test_regress/t/t_func_dotted.v b/test_regress/t/t_func_dotted.v index 892626ad0..c7e6a42e4 100644 --- a/test_regress/t/t_func_dotted.v +++ b/test_regress/t/t_func_dotted.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_dotted_inl0.pl b/test_regress/t/t_func_dotted_inl0.pl index f1ece27d9..c52fcacdb 100755 --- a/test_regress/t/t_func_dotted_inl0.pl +++ b/test_regress/t/t_func_dotted_inl0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -17,10 +18,10 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_func_dotted_inl0.vlt b/test_regress/t/t_func_dotted_inl0.vlt index eef5ae669..74d8c961a 100644 --- a/test_regress/t/t_func_dotted_inl0.vlt +++ b/test_regress/t/t_func_dotted_inl0.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_func_dotted_inl0_vlt.pl b/test_regress/t/t_func_dotted_inl0_vlt.pl index 92a4a7d81..57499e1bd 100755 --- a/test_regress/t/t_func_dotted_inl0_vlt.pl +++ b/test_regress/t/t_func_dotted_inl0_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -17,10 +18,10 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_func_dotted_inl1.pl b/test_regress/t/t_func_dotted_inl1.pl index 2f3b869d0..0e727a4a2 100755 --- a/test_regress/t/t_func_dotted_inl1.pl +++ b/test_regress/t/t_func_dotted_inl1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_dotted_inl1.vlt b/test_regress/t/t_func_dotted_inl1.vlt index e81ace1ff..f930d70a0 100644 --- a/test_regress/t/t_func_dotted_inl1.vlt +++ b/test_regress/t/t_func_dotted_inl1.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_func_dotted_inl1_vlt.pl b/test_regress/t/t_func_dotted_inl1_vlt.pl index 51a92a162..beea5f392 100755 --- a/test_regress/t/t_func_dotted_inl1_vlt.pl +++ b/test_regress/t/t_func_dotted_inl1_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_dotted_inl2.pl b/test_regress/t/t_func_dotted_inl2.pl index c6355044c..c958969e5 100755 --- a/test_regress/t/t_func_dotted_inl2.pl +++ b/test_regress/t/t_func_dotted_inl2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -17,8 +18,8 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_func_dotted_inl2.vlt b/test_regress/t/t_func_dotted_inl2.vlt index 68d53c3e6..855db3058 100644 --- a/test_regress/t/t_func_dotted_inl2.vlt +++ b/test_regress/t/t_func_dotted_inl2.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_func_dotted_inl2_vlt.pl b/test_regress/t/t_func_dotted_inl2_vlt.pl index a2c0873b2..4d31f5ec9 100755 --- a/test_regress/t/t_func_dotted_inl2_vlt.pl +++ b/test_regress/t/t_func_dotted_inl2_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -17,8 +18,8 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_func_endian.pl b/test_regress/t/t_func_endian.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_endian.pl +++ b/test_regress/t/t_func_endian.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_endian.v b/test_regress/t/t_func_endian.v index 1fe1d3fa8..30d4ecc04 100644 --- a/test_regress/t/t_func_endian.v +++ b/test_regress/t/t_func_endian.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_first.pl b/test_regress/t/t_func_first.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_first.pl +++ b/test_regress/t/t_func_first.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_first.v b/test_regress/t/t_func_first.v index 1ee1f80b8..6aedc2fcf 100644 --- a/test_regress/t/t_func_first.v +++ b/test_regress/t/t_func_first.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_flip.pl b/test_regress/t/t_func_flip.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_flip.pl +++ b/test_regress/t/t_func_flip.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_flip.v b/test_regress/t/t_func_flip.v index 3628599b6..302b6b0d5 100644 --- a/test_regress/t/t_func_flip.v +++ b/test_regress/t/t_func_flip.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define INT_RANGE 31:0 `define INT_RANGE 31:0 // Duplicate identical defs are OK diff --git a/test_regress/t/t_func_gen.pl b/test_regress/t/t_func_gen.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_gen.pl +++ b/test_regress/t/t_func_gen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_gen.v b/test_regress/t/t_func_gen.v index d5ef80e5e..410d7e0b9 100644 --- a/test_regress/t/t_func_gen.v +++ b/test_regress/t/t_func_gen.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_graphcirc.pl b/test_regress/t/t_func_graphcirc.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_graphcirc.pl +++ b/test_regress/t/t_func_graphcirc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_graphcirc.v b/test_regress/t/t_func_graphcirc.v index bc28e5b17..d5464771c 100644 --- a/test_regress/t/t_func_graphcirc.v +++ b/test_regress/t/t_func_graphcirc.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_grey.pl b/test_regress/t/t_func_grey.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_grey.pl +++ b/test_regress/t/t_func_grey.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_grey.v b/test_regress/t/t_func_grey.v index fac134607..2e77f477a 100644 --- a/test_regress/t/t_func_grey.v +++ b/test_regress/t/t_func_grey.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_lib.pl b/test_regress/t/t_func_lib.pl index e002e1c21..2142a98cd 100755 --- a/test_regress/t/t_func_lib.pl +++ b/test_regress/t/t_func_lib.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_lib.v b/test_regress/t/t_func_lib.v index cd5d55591..5882728ba 100644 --- a/test_regress/t/t_func_lib.v +++ b/test_regress/t/t_func_lib.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; initial begin diff --git a/test_regress/t/t_func_lib_sub.pl b/test_regress/t/t_func_lib_sub.pl index 95facfefc..6c7c759a8 100755 --- a/test_regress/t/t_func_lib_sub.pl +++ b/test_regress/t/t_func_lib_sub.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_func_lib_sub.v b/test_regress/t/t_func_lib_sub.v index fcc8cc766..18e9b477f 100644 --- a/test_regress/t/t_func_lib_sub.v +++ b/test_regress/t/t_func_lib_sub.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define zednkw 200 diff --git a/test_regress/t/t_func_mlog2.pl b/test_regress/t/t_func_mlog2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_mlog2.pl +++ b/test_regress/t/t_func_mlog2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_mlog2.v b/test_regress/t/t_func_mlog2.v index bddb2c8e7..4dfe03bfa 100644 --- a/test_regress/t/t_func_mlog2.v +++ b/test_regress/t/t_func_mlog2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_named.pl b/test_regress/t/t_func_named.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_named.pl +++ b/test_regress/t/t_func_named.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_named.v b/test_regress/t/t_func_named.v index f51fd9962..f3c016dd5 100644 --- a/test_regress/t/t_func_named.v +++ b/test_regress/t/t_func_named.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_func_noinl.pl b/test_regress/t/t_func_noinl.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_noinl.pl +++ b/test_regress/t/t_func_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_noinl.v b/test_regress/t/t_func_noinl.v index 4b6e40e96..cae0da0a5 100644 --- a/test_regress/t/t_func_noinl.v +++ b/test_regress/t/t_func_noinl.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_numones.pl b/test_regress/t/t_func_numones.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_numones.pl +++ b/test_regress/t/t_func_numones.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_numones.v b/test_regress/t/t_func_numones.v index e47fa50dd..d1ff279ea 100644 --- a/test_regress/t/t_func_numones.v +++ b/test_regress/t/t_func_numones.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_outfirst.pl b/test_regress/t/t_func_outfirst.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_outfirst.pl +++ b/test_regress/t/t_func_outfirst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_outfirst.v b/test_regress/t/t_func_outfirst.v index 14d72b422..589435311 100644 --- a/test_regress/t/t_func_outfirst.v +++ b/test_regress/t/t_func_outfirst.v @@ -1,5 +1,8 @@ -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define DDIFF_BITS 9 `define AOA_BITS 8 diff --git a/test_regress/t/t_func_outp.pl b/test_regress/t/t_func_outp.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_outp.pl +++ b/test_regress/t/t_func_outp.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_outp.v b/test_regress/t/t_func_outp.v index e0d6651a2..cbaa5afeb 100644 --- a/test_regress/t/t_func_outp.v +++ b/test_regress/t/t_func_outp.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_func_paramed.pl b/test_regress/t/t_func_paramed.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_paramed.pl +++ b/test_regress/t/t_func_paramed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_paramed.v b/test_regress/t/t_func_paramed.v index c9ccf9b29..158f78abe 100644 --- a/test_regress/t/t_func_paramed.v +++ b/test_regress/t/t_func_paramed.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_plog.pl b/test_regress/t/t_func_plog.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_plog.pl +++ b/test_regress/t/t_func_plog.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_plog.v b/test_regress/t/t_func_plog.v index fe3b9f98c..59b210b4b 100644 --- a/test_regress/t/t_func_plog.v +++ b/test_regress/t/t_func_plog.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_public.pl b/test_regress/t/t_func_public.pl index a29ba45ad..3ba182f70 100755 --- a/test_regress/t/t_func_public.pl +++ b/test_regress/t/t_func_public.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_public.v b/test_regress/t/t_func_public.v index 6b3da7b81..60ddfbc28 100644 --- a/test_regress/t/t_func_public.v +++ b/test_regress/t/t_func_public.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_public_trace.pl b/test_regress/t/t_func_public_trace.pl index 1bb6cb348..df1660cce 100755 --- a/test_regress/t/t_func_public_trace.pl +++ b/test_regress/t/t_func_public_trace.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_rand.cpp b/test_regress/t/t_func_rand.cpp index bda91faba..f69fd7243 100644 --- a/test_regress/t/t_func_rand.cpp +++ b/test_regress/t/t_func_rand.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include "Vt_func_rand.h" diff --git a/test_regress/t/t_func_rand.pl b/test_regress/t/t_func_rand.pl index 6c781245e..4d136dc52 100755 --- a/test_regress/t/t_func_rand.pl +++ b/test_regress/t/t_func_rand.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_func_rand.v b/test_regress/t/t_func_rand.v index 0d525bb9b..8839b156b 100644 --- a/test_regress/t/t_func_rand.v +++ b/test_regress/t/t_func_rand.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk, Rand); input clk; diff --git a/test_regress/t/t_func_range.pl b/test_regress/t/t_func_range.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_range.pl +++ b/test_regress/t/t_func_range.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_range.v b/test_regress/t/t_func_range.v index fc29e9ec0..c5a0cf3e0 100644 --- a/test_regress/t/t_func_range.v +++ b/test_regress/t/t_func_range.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_real_abs.pl b/test_regress/t/t_func_real_abs.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_real_abs.pl +++ b/test_regress/t/t_func_real_abs.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_real_abs.v b/test_regress/t/t_func_real_abs.v index 33719a72f..fd6c7c9a6 100644 --- a/test_regress/t/t_func_real_abs.v +++ b/test_regress/t/t_func_real_abs.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug591 diff --git a/test_regress/t/t_func_real_param.pl b/test_regress/t/t_func_real_param.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_real_param.pl +++ b/test_regress/t/t_func_real_param.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_real_param.v b/test_regress/t/t_func_real_param.v index 62c8a1830..dad6ec3b8 100644 --- a/test_regress/t/t_func_real_param.v +++ b/test_regress/t/t_func_real_param.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug475 diff --git a/test_regress/t/t_func_redef.pl b/test_regress/t/t_func_redef.pl index 5c448de7c..d1bf185c9 100755 --- a/test_regress/t/t_func_redef.pl +++ b/test_regress/t/t_func_redef.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_redef.v b/test_regress/t/t_func_redef.v index 042dfec12..19d4f4a89 100644 --- a/test_regress/t/t_func_redef.v +++ b/test_regress/t/t_func_redef.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 function automatic integer min(input integer a, input integer b); return (a < b) ? a : b; diff --git a/test_regress/t/t_func_regfirst.pl b/test_regress/t/t_func_regfirst.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_regfirst.pl +++ b/test_regress/t/t_func_regfirst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_regfirst.v b/test_regress/t/t_func_regfirst.v index ca3e2dcb2..c45dfc614 100644 --- a/test_regress/t/t_func_regfirst.v +++ b/test_regress/t/t_func_regfirst.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_return.pl b/test_regress/t/t_func_return.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_return.pl +++ b/test_regress/t/t_func_return.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_return.v b/test_regress/t/t_func_return.v index 8926ae8ee..5c6c54e69 100644 --- a/test_regress/t/t_func_return.v +++ b/test_regress/t/t_func_return.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug420 typedef logic [7-1:0] wb_ind_t; diff --git a/test_regress/t/t_func_sum.pl b/test_regress/t/t_func_sum.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_sum.pl +++ b/test_regress/t/t_func_sum.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_sum.v b/test_regress/t/t_func_sum.v index 5a652a928..ccbab0594 100644 --- a/test_regress/t/t_func_sum.v +++ b/test_regress/t/t_func_sum.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008-2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008-2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_task_bad.out b/test_regress/t/t_func_task_bad.out index a50e09a63..5a85eb04d 100644 --- a/test_regress/t/t_func_task_bad.out +++ b/test_regress/t/t_func_task_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_func_task_bad.v:9: Illegal call of a task as a function: 'task_as_func' - if (task_as_func(1'b0)) $stop; - ^~~~~~~~~~~~ +%Error: t/t_func_task_bad.v:10:11: Illegal call of a task as a function: 'task_as_func' + 10 | if (task_as_func(1'b0)) $stop; + | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_task_bad.pl b/test_regress/t/t_func_task_bad.pl index 6ed771616..1de2d764d 100755 --- a/test_regress/t/t_func_task_bad.pl +++ b/test_regress/t/t_func_task_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2011 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2011 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_task_bad.v b/test_regress/t/t_func_task_bad.v index c1623fd41..2f4887820 100644 --- a/test_regress/t/t_func_task_bad.v +++ b/test_regress/t/t_func_task_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_func_tie_bad.out b/test_regress/t/t_func_tie_bad.out index 0a7779940..2b7d3d9a9 100644 --- a/test_regress/t/t_func_tie_bad.out +++ b/test_regress/t/t_func_tie_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_func_tie_bad.v:10: Function/task output connected to constant instead of variable: 'b' - func(0, 1'b1); - ^~~~ +%Error: t/t_func_tie_bad.v:11:15: Function/task output connected to constant instead of variable: 'b' + 11 | func(0, 1'b1); + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_tie_bad.pl b/test_regress/t/t_func_tie_bad.pl index 6ed771616..1de2d764d 100755 --- a/test_regress/t/t_func_tie_bad.pl +++ b/test_regress/t/t_func_tie_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2011 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2011 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_tie_bad.v b/test_regress/t/t_func_tie_bad.v index 350a5e3ca..b31288598 100644 --- a/test_regress/t/t_func_tie_bad.v +++ b/test_regress/t/t_func_tie_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_func_twocall.pl b/test_regress/t/t_func_twocall.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_twocall.pl +++ b/test_regress/t/t_func_twocall.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_twocall.v b/test_regress/t/t_func_twocall.v index 324166c72..e6dcd1ee6 100644 --- a/test_regress/t/t_func_twocall.v +++ b/test_regress/t/t_func_twocall.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_types.pl b/test_regress/t/t_func_types.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_types.pl +++ b/test_regress/t/t_func_types.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_types.v b/test_regress/t/t_func_types.v index 9ee81c301..23e02f76d 100644 --- a/test_regress/t/t_func_types.v +++ b/test_regress/t/t_func_types.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_func_under.pl b/test_regress/t/t_func_under.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_under.pl +++ b/test_regress/t/t_func_under.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_under.v b/test_regress/t/t_func_under.v index ec7d7e67e..f4d8f0155 100644 --- a/test_regress/t/t_func_under.v +++ b/test_regress/t/t_func_under.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_func_under2.pl b/test_regress/t/t_func_under2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_under2.pl +++ b/test_regress/t/t_func_under2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_under2.v b/test_regress/t/t_func_under2.v index 4f0cd6211..30d2515c6 100644 --- a/test_regress/t/t_func_under2.v +++ b/test_regress/t/t_func_under2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug598 diff --git a/test_regress/t/t_func_unit.pl b/test_regress/t/t_func_unit.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_func_unit.pl +++ b/test_regress/t/t_func_unit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_unit.v b/test_regress/t/t_func_unit.v index 178d32480..6f92f2ee0 100644 --- a/test_regress/t/t_func_unit.v +++ b/test_regress/t/t_func_unit.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 task tsk(output tfo); tfo = 1'b0; diff --git a/test_regress/t/t_func_v.pl b/test_regress/t/t_func_v.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_v.pl +++ b/test_regress/t/t_func_v.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_v.v b/test_regress/t/t_func_v.v index 7f65b6067..0d553cf79 100644 --- a/test_regress/t/t_func_v.v +++ b/test_regress/t/t_func_v.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Chandan Egbert. +// SPDX-License-Identifier: CC0-1.0 // See bug569 diff --git a/test_regress/t/t_func_v_noinl.pl b/test_regress/t/t_func_v_noinl.pl index fd294abcb..c0bccceac 100755 --- a/test_regress/t/t_func_v_noinl.pl +++ b/test_regress/t/t_func_v_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_void.pl b/test_regress/t/t_func_void.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_void.pl +++ b/test_regress/t/t_func_void.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_void.v b/test_regress/t/t_func_void.v index 4241c5741..ca357d7ce 100644 --- a/test_regress/t/t_func_void.v +++ b/test_regress/t/t_func_void.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_void_bad.out b/test_regress/t/t_func_void_bad.out index b98f258c6..2eaf6b65c 100644 --- a/test_regress/t/t_func_void_bad.out +++ b/test_regress/t/t_func_void_bad.out @@ -1,5 +1,5 @@ -%Warning-IGNOREDRETURN: t/t_func_void_bad.v:25: Ignoring return value of non-void function (IEEE 1800-2017 13.4.1) - f1(20); - ^~ +%Warning-IGNOREDRETURN: t/t_func_void_bad.v:26:7: Ignoring return value of non-void function (IEEE 1800-2017 13.4.1) + 26 | f1(20); + | ^~ ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_func_void_bad.pl b/test_regress/t/t_func_void_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_func_void_bad.pl +++ b/test_regress/t/t_func_void_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_void_bad.v b/test_regress/t/t_func_void_bad.v index 228d5204d..3cea6abc8 100644 --- a/test_regress/t/t_func_void_bad.v +++ b/test_regress/t/t_func_void_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_while.pl b/test_regress/t/t_func_while.pl index b660b3660..7a2f89aa9 100755 --- a/test_regress/t/t_func_while.pl +++ b/test_regress/t/t_func_while.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_while.v b/test_regress/t/t_func_while.v index 1591d058f..b478bb2fe 100644 --- a/test_regress/t/t_func_while.v +++ b/test_regress/t/t_func_while.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Julien Margetts. +// SPDX-License-Identifier: CC0-1.0 module t #(parameter sz = 4096) ( diff --git a/test_regress/t/t_func_wide.pl b/test_regress/t/t_func_wide.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_func_wide.pl +++ b/test_regress/t/t_func_wide.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_func_wide.v b/test_regress/t/t_func_wide.v index b7e398e18..ede40e84a 100644 --- a/test_regress/t/t_func_wide.v +++ b/test_regress/t/t_func_wide.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_func_wide_out_bad.out b/test_regress/t/t_func_wide_out_bad.out index 954d47112..956791a50 100644 --- a/test_regress/t/t_func_wide_out_bad.out +++ b/test_regress/t/t_func_wide_out_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_func_wide_out_bad.v:16: Unsupported: Function output argument 'data' requires 4352 bits, but connection's VARREF 'msg' generates 4350 bits. - : ... In instance t - func(msg); - ^~~ +%Error: t/t_func_wide_out_bad.v:17:12: Unsupported: Function output argument 'data' requires 4352 bits, but connection's VARREF 'msg' generates 4350 bits. + : ... In instance t + 17 | func(msg); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_func_wide_out_bad.pl b/test_regress/t/t_func_wide_out_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_func_wide_out_bad.pl +++ b/test_regress/t/t_func_wide_out_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_func_wide_out_bad.v b/test_regress/t/t_func_wide_out_bad.v index f63f21676..e7fd53a4b 100644 --- a/test_regress/t/t_func_wide_out_bad.v +++ b/test_regress/t/t_func_wide_out_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_fuzz_always_bad.out b/test_regress/t/t_fuzz_always_bad.out index 63fc162df..6da8a3f17 100644 --- a/test_regress/t/t_fuzz_always_bad.out +++ b/test_regress/t/t_fuzz_always_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_fuzz_always_bad.v:9: Can't find definition of 'a' in dotted variable: 'c.a' - always @ c.a c:h; - ^ -%Error: t/t_fuzz_always_bad.v:9: Can't find definition of task/function: 'h' - always @ c.a c:h; - ^ -%Error: t/t_fuzz_always_bad.v:9: Unsupported: Complex statement in sensitivity list - always @ c.a c:h; - ^ +%Error: t/t_fuzz_always_bad.v:10:15: Can't find definition of 'a' in dotted variable: 'c.a' + 10 | always @ c.a c:h; + | ^ +%Error: t/t_fuzz_always_bad.v:10:19: Can't find definition of task/function: 'h' + 10 | always @ c.a c:h; + | ^ +%Error: t/t_fuzz_always_bad.v:10:14: Unsupported: Complex statement in sensitivity list + 10 | always @ c.a c:h; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_fuzz_always_bad.pl b/test_regress/t/t_fuzz_always_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_fuzz_always_bad.pl +++ b/test_regress/t/t_fuzz_always_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_fuzz_always_bad.v b/test_regress/t/t_fuzz_always_bad.v index ed2c10357..da50b761f 100644 --- a/test_regress/t/t_fuzz_always_bad.v +++ b/test_regress/t/t_fuzz_always_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug1577 diff --git a/test_regress/t/t_fuzz_eof_bad.pl b/test_regress/t/t_fuzz_eof_bad.pl index fd7324fbf..b3e120653 100755 --- a/test_regress/t/t_fuzz_eof_bad.pl +++ b/test_regress/t/t_fuzz_eof_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_fuzz_eqne_bad.out b/test_regress/t/t_fuzz_eqne_bad.out index 528089125..08bd37daf 100644 --- a/test_regress/t/t_fuzz_eqne_bad.out +++ b/test_regress/t/t_fuzz_eqne_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_fuzz_eqne_bad.v:11: Slice operator VARREF 't.b' on non-slicable (e.g. non-vector) right-hand-side operand - : ... In instance t.b - initial c = (a != &b); - ^ +%Error: t/t_fuzz_eqne_bad.v:12:23: Slice operator VARREF 't.b' on non-slicable (e.g. non-vector) right-hand-side operand + : ... In instance t.b + 12 | initial c = (a != &b); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_fuzz_eqne_bad.pl b/test_regress/t/t_fuzz_eqne_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_fuzz_eqne_bad.pl +++ b/test_regress/t/t_fuzz_eqne_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_fuzz_eqne_bad.v b/test_regress/t/t_fuzz_eqne_bad.v index bef8e3548..c4cd201fa 100644 --- a/test_regress/t/t_fuzz_eqne_bad.v +++ b/test_regress/t/t_fuzz_eqne_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug1587 module t; diff --git a/test_regress/t/t_fuzz_genintf_bad.out b/test_regress/t/t_fuzz_genintf_bad.out index 7ba1095b9..bd63bfbc4 100644 --- a/test_regress/t/t_fuzz_genintf_bad.out +++ b/test_regress/t/t_fuzz_genintf_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_fuzz_genintf_bad.v:23: Unsupported: Member call on object 'VARREF 'j'' which is a 'BASICDTYPE 'integer'' - : ... In instance t - j.e(0), - ^ -%Error: Internal Error: t/t_fuzz_genintf_bad.v:23: ../V3Width.cpp:#: Unlinked pin data type - : ... In instance t - j.e(0), - ^ +%Error: t/t_fuzz_genintf_bad.v:24:12: Unsupported: Member call on object 'VARREF 'j'' which is a 'BASICDTYPE 'integer'' + : ... In instance t + 24 | j.e(0), + | ^ +%Error: Internal Error: t/t_fuzz_genintf_bad.v:24:11: ../V3Width.cpp:#: Unlinked pin data type + : ... In instance t + 24 | j.e(0), + | ^ ... See the manual and https://verilator.org for more assistance. diff --git a/test_regress/t/t_fuzz_genintf_bad.pl b/test_regress/t/t_fuzz_genintf_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_fuzz_genintf_bad.pl +++ b/test_regress/t/t_fuzz_genintf_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_fuzz_genintf_bad.v b/test_regress/t/t_fuzz_genintf_bad.v index 5069935cc..53df6dea8 100644 --- a/test_regress/t/t_fuzz_genintf_bad.v +++ b/test_regress/t/t_fuzz_genintf_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug1588 interface intf; diff --git a/test_regress/t/t_fuzz_negwidth_bad.out b/test_regress/t/t_fuzz_negwidth_bad.out index ac8d41a77..7d1d69a9f 100644 --- a/test_regress/t/t_fuzz_negwidth_bad.out +++ b/test_regress/t/t_fuzz_negwidth_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_fuzz_negwidth_bad.v:8: Unsupported: Width of number exceeds implementation limit: 1231232312312312'd1 (IEEE 1800-2017 6.9.1) -int c = 1231232312312312'd1; - ^~~~~~~~~~~~~~~~~~~ +%Error: t/t_fuzz_negwidth_bad.v:9:9: Unsupported: Width of number exceeds implementation limit: 1231232312312312'd1 (IEEE 1800-2017 6.9.1) + 9 | int c = 1231232312312312'd1; + | ^~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_fuzz_negwidth_bad.pl b/test_regress/t/t_fuzz_negwidth_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_fuzz_negwidth_bad.pl +++ b/test_regress/t/t_fuzz_negwidth_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_fuzz_negwidth_bad.v b/test_regress/t/t_fuzz_negwidth_bad.v index 245e36a71..d9c7d3cdb 100644 --- a/test_regress/t/t_fuzz_negwidth_bad.v +++ b/test_regress/t/t_fuzz_negwidth_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 int a = -12'd1; int b = 65536'd1; diff --git a/test_regress/t/t_fuzz_triand_bad.out b/test_regress/t/t_fuzz_triand_bad.out index a881e799f..4e3319976 100644 --- a/test_regress/t/t_fuzz_triand_bad.out +++ b/test_regress/t/t_fuzz_triand_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_fuzz_triand_bad.v:7: Unsupported: Member call on object 'VARREF 'g'' which is a 'BASICDTYPE 'logic'' - : ... In instance t - tri g=g.and.g; - ^~~ -%Error: Internal Error: t/t_fuzz_triand_bad.v:7: ../V3Width.cpp:#: Unlinked data type - : ... In instance t - tri g=g.and.g; - ^~~ +%Error: t/t_fuzz_triand_bad.v:8:12: Unsupported: Member call on object 'VARREF 'g'' which is a 'BASICDTYPE 'logic'' + : ... In instance t + 8 | tri g=g.and.g; + | ^~~ +%Error: Internal Error: t/t_fuzz_triand_bad.v:8:12: ../V3Width.cpp:#: Unlinked data type + : ... In instance t + 8 | tri g=g.and.g; + | ^~~ ... See the manual and https://verilator.org for more assistance. diff --git a/test_regress/t/t_fuzz_triand_bad.pl b/test_regress/t/t_fuzz_triand_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_fuzz_triand_bad.pl +++ b/test_regress/t/t_fuzz_triand_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_fuzz_triand_bad.v b/test_regress/t/t_fuzz_triand_bad.v index 7f07d18a9..525b2c55b 100644 --- a/test_regress/t/t_fuzz_triand_bad.v +++ b/test_regress/t/t_fuzz_triand_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (); tri g=g.and.g; diff --git a/test_regress/t/t_gantt.pl b/test_regress/t/t_gantt.pl index f80bfacfd..1f62a459f 100755 --- a/test_regress/t/t_gantt.pl +++ b/test_regress/t/t_gantt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; diff --git a/test_regress/t/t_gate_array.pl b/test_regress/t/t_gate_array.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_gate_array.pl +++ b/test_regress/t/t_gate_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gate_array.v b/test_regress/t/t_gate_array.v index 6fcf23ccc..0ea797e6b 100644 --- a/test_regress/t/t_gate_array.v +++ b/test_regress/t/t_gate_array.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gate_basic.pl b/test_regress/t/t_gate_basic.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_gate_basic.pl +++ b/test_regress/t/t_gate_basic.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gate_basic.v b/test_regress/t/t_gate_basic.v index 4d5e87c44..8f120463a 100644 --- a/test_regress/t/t_gate_basic.v +++ b/test_regress/t/t_gate_basic.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gate_chained.pl b/test_regress/t/t_gate_chained.pl index 1dccf0ed7..2ccf6c4d3 100755 --- a/test_regress/t/t_gate_chained.pl +++ b/test_regress/t/t_gate_chained.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; scenarios(simulator => 1); diff --git a/test_regress/t/t_gate_delref.pl b/test_regress/t/t_gate_delref.pl index 683765bd3..86f045021 100755 --- a/test_regress/t/t_gate_delref.pl +++ b/test_regress/t/t_gate_delref.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gate_delref.v b/test_regress/t/t_gate_delref.v index 154559b72..c9255a9ee 100644 --- a/test_regress/t/t_gate_delref.v +++ b/test_regress/t/t_gate_delref.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug1475 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gate_elim.pl b/test_regress/t/t_gate_elim.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_gate_elim.pl +++ b/test_regress/t/t_gate_elim.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gate_elim.v b/test_regress/t/t_gate_elim.v index 2a145bea4..910a0ff4c 100644 --- a/test_regress/t/t_gate_elim.v +++ b/test_regress/t/t_gate_elim.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gate_fdup.pl b/test_regress/t/t_gate_fdup.pl index 683765bd3..86f045021 100755 --- a/test_regress/t/t_gate_fdup.pl +++ b/test_regress/t/t_gate_fdup.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gate_fdup.v b/test_regress/t/t_gate_fdup.v index eb1778815..8e829f33a 100644 --- a/test_regress/t/t_gate_fdup.v +++ b/test_regress/t/t_gate_fdup.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2005 by Thomas Dzetkulic. +// SPDX-License-Identifier: CC0-1.0 module fnor2(f, a, b); parameter W = 1; diff --git a/test_regress/t/t_gate_implicit.pl b/test_regress/t/t_gate_implicit.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gate_implicit.pl +++ b/test_regress/t/t_gate_implicit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gate_implicit.v b/test_regress/t/t_gate_implicit.v index 4255ff293..6b68b548a 100644 --- a/test_regress/t/t_gate_implicit.v +++ b/test_regress/t/t_gate_implicit.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gate_lvalue_const.pl b/test_regress/t/t_gate_lvalue_const.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_gate_lvalue_const.pl +++ b/test_regress/t/t_gate_lvalue_const.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gate_lvalue_const.v b/test_regress/t/t_gate_lvalue_const.v index 2119807d2..ac003d8f6 100644 --- a/test_regress/t/t_gate_lvalue_const.v +++ b/test_regress/t/t_gate_lvalue_const.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gate_ormux.pl b/test_regress/t/t_gate_ormux.pl new file mode 100755 index 000000000..7ecf561f6 --- /dev/null +++ b/test_regress/t/t_gate_ormux.pl @@ -0,0 +1,25 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +$Self->{cycles} = ($Self->{benchmark} ? 100_000_000 : 100); +$Self->{sim_time} = $Self->{cycles} * 10 + 1000; + +compile( + v_flags2 => ["+define+SIM_CYCLES=$Self->{cycles}",], + verilator_flags2=>["-Wno-UNOPTTHREADS"], + ); + +execute( + ); + +ok(1); +1; diff --git a/test_regress/t/t_gate_ormux.v b/test_regress/t/t_gate_ormux.v new file mode 100755 index 000000000..7033c45fa --- /dev/null +++ b/test_regress/t/t_gate_ormux.v @@ -0,0 +1,267 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + logic [31:0] rdata; + logic [31:0] rdata2; + wire [31:0] wdata = crc[31:0]; + wire [15:0] sel = {11'h0, crc[36:32]}; + wire we = crc[48]; + + Test test (/*AUTOINST*/ + // Outputs + .rdata (rdata[31:0]), + .rdata2 (rdata2[31:0]), + // Inputs + .clk (clk), + .we (we), + .sel (sel[15:0]), + .wdata (wdata[31:0])); + + // 5.07 4.42 -> 13% + wire [63:0] result = {rdata2, rdata}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (rdata2 != rdata) $stop; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc<10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'h8977713eb467bc86 + if (sum !== `EXPECTED_SUM) $stop; + end + else if (cyc == `SIM_CYCLES) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test(/*AUTOARG*/ + // Outputs + rdata, rdata2, + // Inputs + clk, we, sel, wdata + ); + input clk; + input we; + input [15:0] sel; + input [31:0] wdata; + output logic [31:0] rdata; + output logic [31:0] rdata2; + + logic we_d1r; + logic [15:0] sel_d1r; + logic [31:0] wdata_d1r; + always_ff @ (posedge clk) begin + we_d1r <= we; + sel_d1r <= sel; + wdata_d1r <= wdata; + end + + reg [31:0] csr0000; + reg [31:0] csr0001; + reg [31:0] csr0002; + reg [31:0] csr0003; + reg [31:0] csr0004; + reg [31:0] csr0005; + reg [31:0] csr0006; + reg [31:0] csr0007; + reg [31:0] csr0008; + reg [31:0] csr0009; + reg [31:0] csr000a; + reg [31:0] csr000b; + reg [31:0] csr000c; + reg [31:0] csr000d; + reg [31:0] csr000e; + reg [31:0] csr000f; + wire [31:0] csr0010 = 32'h33675230; + wire [31:0] csr0011 = 32'h00fa2144; + wire [31:0] csr0012 = 32'h6a5e8e10; + wire [31:0] csr0013 = 32'h000a5b5e; + wire [31:0] csr0014 = 32'h002fe51b; + wire [31:0] csr0015 = 32'h00027e00; + wire [31:0] csr0016 = 32'h0000e3c0; + wire [31:0] csr0017 = 32'h00efcf16; + wire [31:0] csr0018 = 32'h007a2600; + wire [31:0] csr0019 = 32'h0a4a9f10; + wire [31:0] csr001a = 32'h7d789de3; + wire [31:0] csr001b = 32'h40f655f9; + wire [31:0] csr001c = 32'hadad01f4; + wire [31:0] csr001d = 32'h02e7b33c; + wire [31:0] csr001e = 32'h12101533; + wire [31:0] csr001f = 32'h2cc1cce5; + initial begin + csr0000 = 32'he172d365; + csr0001 = 32'h35cc25e2; + csr0002 = 32'haf48436e; + csr0003 = 32'h135e55e4; + csr0004 = 32'h5fd6e48a; + csr0005 = 32'hb07d34ad; + csr0006 = 32'h2aa05deb; + csr0007 = 32'hfe97b680; + csr0008 = 32'h960f20bb; + csr0009 = 32'h251129f0; + csr000a = 32'hef3d2f93; + csr000b = 32'hef4bc127; + csr000c = 32'h3dfecb10; + csr000d = 32'h1b4690f5; + csr000e = 32'ha07822ab; + csr000f = 32'hf817cbf6; + end + + always_ff @ (posedge clk) begin + if (we_d1r && sel_d1r == 16'h0000) csr0000 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0001) csr0001 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0002) csr0002 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0003) csr0003 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0004) csr0004 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0005) csr0005 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0006) csr0006 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0007) csr0007 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0008) csr0008 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h0009) csr0009 <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000a) csr000a <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000b) csr000b <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000c) csr000c <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000d) csr000d <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000e) csr000e <= wdata_d1r; + if (we_d1r && sel_d1r == 16'h000f) csr000f <= wdata_d1r; + end + + wire dec0000 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0001 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0002 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0003 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0004 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0005 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0006 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0007 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0008 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0009 = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec000a = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec000b = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec000c = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec000d = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec000e = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec000f = sel_d1r[15:6] == 0 && !sel_d1r[5] && !sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0010 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0011 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0012 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0013 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0014 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0015 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec0016 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec0017 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && !sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec0018 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec0019 = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec001a = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec001b = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && !sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + wire dec001c = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && !sel_d1r[0]; + wire dec001d = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && !sel_d1r[1] && sel_d1r[0]; + wire dec001e = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && !sel_d1r[0]; + wire dec001f = sel_d1r[15:6] == 0 && !sel_d1r[5] && sel_d1r[4] && sel_d1r[3] && sel_d1r[2] && sel_d1r[1] && sel_d1r[0]; + + assign rdata = (32'h0 + | {32{dec0000}} & csr0000 + | {32{dec0001}} & csr0001 + | {32{dec0002}} & csr0002 + | {32{dec0003}} & csr0003 + | {32{dec0004}} & csr0004 + | {32{dec0005}} & csr0005 + | {32{dec0006}} & csr0006 + | {32{dec0007}} & csr0007 + | {32{dec0008}} & csr0008 + | {32{dec0009}} & csr0009 + | {32{dec000a}} & csr000a + | {32{dec000b}} & csr000b + | {32{dec000c}} & csr000c + | {32{dec000d}} & csr000d + | {32{dec000e}} & csr000e + | {32{dec000f}} & csr000f + | {32{dec0010}} & csr0010 + | {32{dec0011}} & csr0011 + | {32{dec0012}} & csr0012 + | {32{dec0013}} & csr0013 + | {32{dec0014}} & csr0014 + | {32{dec0015}} & csr0015 + | {32{dec0016}} & csr0016 + | {32{dec0017}} & csr0017 + | {32{dec0018}} & csr0018 + | {32{dec0019}} & csr0019 + | {32{dec001a}} & csr001a + | {32{dec001b}} & csr001b + | {32{dec001c}} & csr001c + | {32{dec001d}} & csr001d + | {32{dec001e}} & csr001e + | {32{dec001f}} & csr001f + ); + + always_comb begin + case (sel_d1r) + 16'h0000: rdata2 = csr0000; + 16'h0001: rdata2 = csr0001; + 16'h0002: rdata2 = csr0002; + 16'h0003: rdata2 = csr0003; + 16'h0004: rdata2 = csr0004; + 16'h0005: rdata2 = csr0005; + 16'h0006: rdata2 = csr0006; + 16'h0007: rdata2 = csr0007; + 16'h0008: rdata2 = csr0008; + 16'h0009: rdata2 = csr0009; + 16'h000a: rdata2 = csr000a; + 16'h000b: rdata2 = csr000b; + 16'h000c: rdata2 = csr000c; + 16'h000d: rdata2 = csr000d; + 16'h000e: rdata2 = csr000e; + 16'h000f: rdata2 = csr000f; + 16'h0010: rdata2 = csr0010; + 16'h0011: rdata2 = csr0011; + 16'h0012: rdata2 = csr0012; + 16'h0013: rdata2 = csr0013; + 16'h0014: rdata2 = csr0014; + 16'h0015: rdata2 = csr0015; + 16'h0016: rdata2 = csr0016; + 16'h0017: rdata2 = csr0017; + 16'h0018: rdata2 = csr0018; + 16'h0019: rdata2 = csr0019; + 16'h001a: rdata2 = csr001a; + 16'h001b: rdata2 = csr001b; + 16'h001c: rdata2 = csr001c; + 16'h001d: rdata2 = csr001d; + 16'h001e: rdata2 = csr001e; + 16'h001f: rdata2 = csr001f; + default: rdata2 = 0; + endcase + end + +endmodule diff --git a/test_regress/t/t_gate_tree.pl b/test_regress/t/t_gate_tree.pl index 7ceb6e365..eb24dd880 100755 --- a/test_regress/t/t_gate_tree.pl +++ b/test_regress/t/t_gate_tree.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; #use Data::Dumper; use strict; diff --git a/test_regress/t/t_gate_unsup.pl b/test_regress/t/t_gate_unsup.pl index af25d4b14..fceb65618 100755 --- a/test_regress/t/t_gate_unsup.pl +++ b/test_regress/t/t_gate_unsup.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_gate_unsup.v b/test_regress/t/t_gate_unsup.v index 2e78fd2a1..d12c44405 100644 --- a/test_regress/t/t_gate_unsup.v +++ b/test_regress/t/t_gate_unsup.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_gated_clk_1.pl b/test_regress/t/t_gated_clk_1.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gated_clk_1.pl +++ b/test_regress/t/t_gated_clk_1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gated_clk_1.v b/test_regress/t/t_gated_clk_1.v index a638cb606..65c4a13e5 100644 --- a/test_regress/t/t_gated_clk_1.v +++ b/test_regress/t/t_gated_clk_1.v @@ -16,6 +16,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett . +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_alw.pl b/test_regress/t/t_gen_alw.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_alw.pl +++ b/test_regress/t/t_gen_alw.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_alw.v b/test_regress/t/t_gen_alw.v index fd114b192..b30c20a03 100644 --- a/test_regress/t/t_gen_alw.v +++ b/test_regress/t/t_gen_alw.v @@ -1,4 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_assign.pl b/test_regress/t/t_gen_assign.pl index 45e24b34a..4262e4aea 100755 --- a/test_regress/t/t_gen_assign.pl +++ b/test_regress/t/t_gen_assign.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_gen_assign.v b/test_regress/t/t_gen_assign.v index 838d880d8..8bf840544 100644 --- a/test_regress/t/t_gen_assign.v +++ b/test_regress/t/t_gen_assign.v @@ -1,6 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 + `timescale 1ns / 1ps module t (/*AUTOARG*/ diff --git a/test_regress/t/t_gen_cond_bitrange.pl b/test_regress/t/t_gen_cond_bitrange.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_cond_bitrange.pl +++ b/test_regress/t/t_gen_cond_bitrange.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_cond_bitrange.v b/test_regress/t/t_gen_cond_bitrange.v index 67f6379f4..57b7fd5ec 100644 --- a/test_regress/t/t_gen_cond_bitrange.v +++ b/test_regress/t/t_gen_cond_bitrange.v @@ -6,7 +6,7 @@ // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2012 by Jeremy Bennett. - +// SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 4 diff --git a/test_regress/t/t_gen_cond_bitrange_bad.out b/test_regress/t/t_gen_cond_bitrange_bad.out index cb793ca13..0c77f2e84 100644 --- a/test_regress/t/t_gen_cond_bitrange_bad.out +++ b/test_regress/t/t_gen_cond_bitrange_bad.out @@ -1,18 +1,18 @@ -%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:58: Selection index out of range: 2:2 outside 1:0 - : ... In instance t.i_test_gen - if ((g < (SIZE + 1)) && MASK[g]) begin - ^ +%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:58:38: Selection index out of range: 2:2 outside 1:0 + : ... In instance t.i_test_gen + 58 | if ((g < (SIZE + 1)) && MASK[g]) begin + | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70: Selection index out of range: 2:2 outside 1:0 - : ... In instance t.i_test_gen - if ((g < SIZE) && MASK[g + 1]) begin - ^ -%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:83: Selection index out of range: 2:2 outside 1:0 - : ... In instance t.i_test_gen - if ((g < (SIZE)) & MASK[g]) begin - ^ -%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:96: Selection index out of range: 2:2 outside 1:0 - : ... In instance t.i_test_gen - if (!((g >= SIZE) | ~MASK[g])) begin - ^ +%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70:32: Selection index out of range: 2:2 outside 1:0 + : ... In instance t.i_test_gen + 70 | if ((g < SIZE) && MASK[g + 1]) begin + | ^ +%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:83:33: Selection index out of range: 2:2 outside 1:0 + : ... In instance t.i_test_gen + 83 | if ((g < (SIZE)) & MASK[g]) begin + | ^ +%Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:96:35: Selection index out of range: 2:2 outside 1:0 + : ... In instance t.i_test_gen + 96 | if (!((g >= SIZE) | ~MASK[g])) begin + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_gen_cond_bitrange_bad.pl b/test_regress/t/t_gen_cond_bitrange_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_gen_cond_bitrange_bad.pl +++ b/test_regress/t/t_gen_cond_bitrange_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_gen_cond_bitrange_bad.v b/test_regress/t/t_gen_cond_bitrange_bad.v index 90b785667..3ca0614cf 100644 --- a/test_regress/t/t_gen_cond_bitrange_bad.v +++ b/test_regress/t/t_gen_cond_bitrange_bad.v @@ -8,7 +8,7 @@ // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2012 by Jeremy Bennett. - +// SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 3 diff --git a/test_regress/t/t_gen_cond_const.pl b/test_regress/t/t_gen_cond_const.pl index 549d3c8f8..2785bec68 100755 --- a/test_regress/t/t_gen_cond_const.pl +++ b/test_regress/t/t_gen_cond_const.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_cond_const.v b/test_regress/t/t_gen_cond_const.v index e23daf4db..870ee4f12 100644 --- a/test_regress/t/t_gen_cond_const.v +++ b/test_regress/t/t_gen_cond_const.v @@ -5,6 +5,7 @@ // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 `define MAX_SIZE 4 diff --git a/test_regress/t/t_gen_defparam.pl b/test_regress/t/t_gen_defparam.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_defparam.pl +++ b/test_regress/t/t_gen_defparam.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_defparam.v b/test_regress/t/t_gen_defparam.v index 041cf2966..4d8bd560c 100644 --- a/test_regress/t/t_gen_defparam.v +++ b/test_regress/t/t_gen_defparam.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_div0.pl b/test_regress/t/t_gen_div0.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_div0.pl +++ b/test_regress/t/t_gen_div0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_div0.v b/test_regress/t/t_gen_div0.v index 2a552717a..d9cc0eb07 100644 --- a/test_regress/t/t_gen_div0.v +++ b/test_regress/t/t_gen_div0.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOINST*/); diff --git a/test_regress/t/t_gen_for.pl b/test_regress/t/t_gen_for.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_for.pl +++ b/test_regress/t/t_gen_for.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_for.v b/test_regress/t/t_gen_for.v index d0349503b..4ca2596d7 100644 --- a/test_regress/t/t_gen_for.v +++ b/test_regress/t/t_gen_for.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_for0.pl b/test_regress/t/t_gen_for0.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_for0.pl +++ b/test_regress/t/t_gen_for0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_for0.v b/test_regress/t/t_gen_for0.v index 1f5c8f239..08427d063 100644 --- a/test_regress/t/t_gen_for0.v +++ b/test_regress/t/t_gen_for0.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_for1.pl b/test_regress/t/t_gen_for1.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_for1.pl +++ b/test_regress/t/t_gen_for1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_for1.v b/test_regress/t/t_gen_for1.v index 469817e73..a7dc72e62 100644 --- a/test_regress/t/t_gen_for1.v +++ b/test_regress/t/t_gen_for1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_for2.pl b/test_regress/t/t_gen_for2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_for2.pl +++ b/test_regress/t/t_gen_for2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_for2.v b/test_regress/t/t_gen_for2.v index f4f83a8cb..63dff454d 100644 --- a/test_regress/t/t_gen_for2.v +++ b/test_regress/t/t_gen_for2.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 parameter N = 5; diff --git a/test_regress/t/t_gen_for_overlap.pl b/test_regress/t/t_gen_for_overlap.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_for_overlap.pl +++ b/test_regress/t/t_gen_for_overlap.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_for_overlap.v b/test_regress/t/t_gen_for_overlap.v index 87da513e4..1a0bdcc8a 100644 --- a/test_regress/t/t_gen_for_overlap.v +++ b/test_regress/t/t_gen_for_overlap.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug749 diff --git a/test_regress/t/t_gen_for_shuffle.pl b/test_regress/t/t_gen_for_shuffle.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_for_shuffle.pl +++ b/test_regress/t/t_gen_for_shuffle.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_for_shuffle.v b/test_regress/t/t_gen_for_shuffle.v index 92048f4d6..b71f4ffac 100644 --- a/test_regress/t/t_gen_for_shuffle.v +++ b/test_regress/t/t_gen_for_shuffle.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_forif.pl b/test_regress/t/t_gen_forif.pl index 26ef67a0b..814486756 100755 --- a/test_regress/t/t_gen_forif.pl +++ b/test_regress/t/t_gen_forif.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_forif.v b/test_regress/t/t_gen_forif.v index 6e542f089..91e3a913f 100644 --- a/test_regress/t/t_gen_forif.v +++ b/test_regress/t/t_gen_forif.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_genblk.out b/test_regress/t/t_gen_genblk.out index abaca2eeb..4eb73f9a4 100644 --- a/test_regress/t/t_gen_genblk.out +++ b/test_regress/t/t_gen_genblk.out @@ -1,6 +1,6 @@ -010: exp=top.t.show0 got=top.t.show0 -014: exp=top.t.genblk1.show1 got=top.t.genblk1.show1 -018: exp=top.t.genblk2.show2 got=top.t.genblk2.show2 -023: exp=top.t.genblk3.genblk1.show3 got=top.t.genblk3.genblk1.show3 -029: exp=top.t.x1.x3.show4 got=top.t.x1.x3.show4 +015: exp=top.t.show0 got=top.t.show0 +019: exp=top.t.genblk1.show1 got=top.t.genblk1.show1 +023: exp=top.t.genblk2.show2 got=top.t.genblk2.show2 +028: exp=top.t.genblk3.genblk1.show3 got=top.t.genblk3.genblk1.show3 +034: exp=top.t.x1.x3.show4 got=top.t.x1.x3.show4 *-* All Finished *-* diff --git a/test_regress/t/t_gen_genblk.pl b/test_regress/t/t_gen_genblk.pl index e109f0f6c..ec985d291 100755 --- a/test_regress/t/t_gen_genblk.pl +++ b/test_regress/t/t_gen_genblk.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_genblk.v b/test_regress/t/t_gen_genblk.v index bb28c18be..ee2dd3ea4 100644 --- a/test_regress/t/t_gen_genblk.v +++ b/test_regress/t/t_gen_genblk.v @@ -1,3 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + module t (/*AUTOARG*/ // Inputs clk, reset_l diff --git a/test_regress/t/t_gen_genblk_noinl.pl b/test_regress/t/t_gen_genblk_noinl.pl index 901e0993c..a9d24cab5 100755 --- a/test_regress/t/t_gen_genblk_noinl.pl +++ b/test_regress/t/t_gen_genblk_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 top_filename("t_gen_genblk.v"); diff --git a/test_regress/t/t_gen_if.pl b/test_regress/t/t_gen_if.pl index 33ff6d6c0..e847dac87 100755 --- a/test_regress/t/t_gen_if.pl +++ b/test_regress/t/t_gen_if.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_gen_if.v b/test_regress/t/t_gen_if.v index 33ef71071..bb1770742 100644 --- a/test_regress/t/t_gen_if.v +++ b/test_regress/t/t_gen_if.v @@ -4,6 +4,8 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 + `timescale 1ns / 1ps module t(data_i, data_o, single); diff --git a/test_regress/t/t_gen_inc.pl b/test_regress/t/t_gen_inc.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_inc.pl +++ b/test_regress/t/t_gen_inc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_inc.v b/test_regress/t/t_gen_inc.v index 2a9884f8d..eaa7ccc3d 100644 --- a/test_regress/t/t_gen_inc.v +++ b/test_regress/t/t_gen_inc.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_index.pl b/test_regress/t/t_gen_index.pl index b9cf6967c..0a43d363c 100755 --- a/test_regress/t/t_gen_index.pl +++ b/test_regress/t/t_gen_index.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_index.v b/test_regress/t/t_gen_index.v index cf5644445..810266adc 100644 --- a/test_regress/t/t_gen_index.v +++ b/test_regress/t/t_gen_index.v @@ -10,7 +10,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. - +// SPDX-License-Identifier: CC0-1.0 `define START 8 `define SIZE 4 diff --git a/test_regress/t/t_gen_intdot.pl b/test_regress/t/t_gen_intdot.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_intdot.pl +++ b/test_regress/t/t_gen_intdot.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_intdot.v b/test_regress/t/t_gen_intdot.v index fe457f57d..a4ffab809 100644 --- a/test_regress/t/t_gen_intdot.v +++ b/test_regress/t/t_gen_intdot.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_gen_intdot2.pl b/test_regress/t/t_gen_intdot2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_intdot2.pl +++ b/test_regress/t/t_gen_intdot2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_intdot2.v b/test_regress/t/t_gen_intdot2.v index 75a4d51ab..d405a9d47 100644 --- a/test_regress/t/t_gen_intdot2.v +++ b/test_regress/t/t_gen_intdot2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_gen_local.pl b/test_regress/t/t_gen_local.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_local.pl +++ b/test_regress/t/t_gen_local.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_local.v b/test_regress/t/t_gen_local.v index dcb7354e8..f9adfd461 100644 --- a/test_regress/t/t_gen_local.v +++ b/test_regress/t/t_gen_local.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_lsb.pl b/test_regress/t/t_gen_lsb.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_lsb.pl +++ b/test_regress/t/t_gen_lsb.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_lsb.v b/test_regress/t/t_gen_lsb.v index 27a7857a7..b442483e6 100644 --- a/test_regress/t/t_gen_lsb.v +++ b/test_regress/t/t_gen_lsb.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_gen_mislevel.pl b/test_regress/t/t_gen_mislevel.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_gen_mislevel.pl +++ b/test_regress/t/t_gen_mislevel.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_mislevel.v b/test_regress/t/t_gen_mislevel.v index e7edfcfbf..9e16e9096 100644 --- a/test_regress/t/t_gen_mislevel.v +++ b/test_regress/t/t_gen_mislevel.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 /// We define the modules in "backward" order. diff --git a/test_regress/t/t_gen_missing.pl b/test_regress/t/t_gen_missing.pl index 5582e61c4..2ede305ee 100755 --- a/test_regress/t/t_gen_missing.pl +++ b/test_regress/t/t_gen_missing.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_missing.v b/test_regress/t/t_gen_missing.v index a491964c7..44dad55f1 100644 --- a/test_regress/t/t_gen_missing.v +++ b/test_regress/t/t_gen_missing.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; // verilator lint_off PINMISSING diff --git a/test_regress/t/t_gen_missing_bad.out b/test_regress/t/t_gen_missing_bad.out index f1a07c9f8..c482a7ec0 100644 --- a/test_regress/t/t_gen_missing_bad.out +++ b/test_regress/t/t_gen_missing_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_gen_missing.v:42: Cannot find file containing module: 'foo_not_needed' - foo_not_needed i_foo(.x(foo[j]), .y(bar[j])); - ^~~~~~~~~~~~~~ +%Error: t/t_gen_missing.v:43:20: Cannot find file containing module: 'foo_not_needed' + 43 | foo_not_needed i_foo(.x(foo[j]), .y(bar[j])); + | ^~~~~~~~~~~~~~ ... Looked in: t/foo_not_needed t/foo_not_needed.v diff --git a/test_regress/t/t_gen_missing_bad.pl b/test_regress/t/t_gen_missing_bad.pl index 98670e56d..7567f33fe 100755 --- a/test_regress/t/t_gen_missing_bad.pl +++ b/test_regress/t/t_gen_missing_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_gen_self_return.pl b/test_regress/t/t_gen_self_return.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_gen_self_return.pl +++ b/test_regress/t/t_gen_self_return.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_self_return.v b/test_regress/t/t_gen_self_return.v index 9af9d9e12..708e50058 100644 --- a/test_regress/t/t_gen_self_return.v +++ b/test_regress/t/t_gen_self_return.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Roman Popov. +// SPDX-License-Identifier: CC0-1.0 module dut #( diff --git a/test_regress/t/t_gen_upscope.pl b/test_regress/t/t_gen_upscope.pl index f79178f86..b4e259e0a 100755 --- a/test_regress/t/t_gen_upscope.pl +++ b/test_regress/t/t_gen_upscope.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_gen_upscope.v b/test_regress/t/t_gen_upscope.v index 474658bdb..b9479e540 100644 --- a/test_regress/t/t_gen_upscope.v +++ b/test_regress/t/t_gen_upscope.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 /* Acceptable answer 1 created tag with scope = top.t.tag diff --git a/test_regress/t/t_gen_var_bad.out b/test_regress/t/t_gen_var_bad.out index f218cd478..e488e77d0 100644 --- a/test_regress/t/t_gen_var_bad.out +++ b/test_regress/t/t_gen_var_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_gen_var_bad.v:9: Non-genvar used in generate for: 'i' - : ... In instance t - for (i=0; i<3; i=i+1) begin - ^~~ +%Error: t/t_gen_var_bad.v:10:7: Non-genvar used in generate for: 'i' + : ... In instance t + 10 | for (i=0; i<3; i=i+1) begin + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_gen_var_bad.pl b/test_regress/t/t_gen_var_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_gen_var_bad.pl +++ b/test_regress/t/t_gen_var_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_gen_var_bad.v b/test_regress/t/t_gen_var_bad.v index 177667c68..f410dbed6 100644 --- a/test_regress/t/t_gen_var_bad.v +++ b/test_regress/t/t_gen_var_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; integer i; diff --git a/test_regress/t/t_generate_fatal_bad.out b/test_regress/t/t_generate_fatal_bad.out index 4e61e3f77..1e3d4e2b1 100644 --- a/test_regress/t/t_generate_fatal_bad.out +++ b/test_regress/t/t_generate_fatal_bad.out @@ -1,87 +1,87 @@ %Warning-USERFATAL: "boom" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.genloop[0].foo_inst - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.genloop[0].foo_inst + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = ?32?h0 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.genloop[1].foo_inst - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.genloop[1].foo_inst + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = ?32?h1 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.gen_l1[2].gen_l2[0].foo_inst2 - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.gen_l1[2].gen_l2[0].foo_inst2 + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h2 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.gen_l1[2].gen_l2[1].foo_inst2 - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.gen_l1[2].gen_l2[1].foo_inst2 + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h4 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.gen_l1[3].gen_l2[0].foo_inst2 - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.gen_l1[3].gen_l2[0].foo_inst2 + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h3 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.gen_l1[3].gen_l2[1].foo_inst2 - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.gen_l1[3].gen_l2[1].foo_inst2 + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h5 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.cond_true.foo_inst3 - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.cond_true.foo_inst3 + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = ?32?h6 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.genblk1.foo_inst4 - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.genblk1.foo_inst4 + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = ?32?h7 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.nested_loop[8].foo2_inst.foo2_loop[0].foo_in_foo2_inst - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.nested_loop[8].foo2_inst.foo2_loop[0].foo_in_foo2_inst + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h8 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.nested_loop[8].foo2_inst.foo2_loop[1].foo_in_foo2_inst - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.nested_loop[8].foo2_inst.foo2_loop[1].foo_in_foo2_inst + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'h9 - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.nested_loop[10].foo2_inst.foo2_loop[0].foo_in_foo2_inst - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.nested_loop[10].foo2_inst.foo2_loop[0].foo_in_foo2_inst + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'ha - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ -%Error: t/t_generate_fatal_bad.v:12: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst - t/t_generate_fatal_bad.v:8: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing - t/t_generate_fatal_bad.v:12: ... Called from get_baz() with parameters: + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ +%Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' + : ... In instance t.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst + t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing + t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = 32'hb - localparam integer BAZ = get_baz(BAR); - ^~~~~~~ + 13 | localparam integer BAZ = get_baz(BAR); + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_generate_fatal_bad.pl b/test_regress/t/t_generate_fatal_bad.pl index 1cc161a94..0ac2cd697 100755 --- a/test_regress/t/t_generate_fatal_bad.pl +++ b/test_regress/t/t_generate_fatal_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_generate_fatal_bad.v b/test_regress/t/t_generate_fatal_bad.v index f8f31811f..48b6dc761 100644 --- a/test_regress/t/t_generate_fatal_bad.v +++ b/test_regress/t/t_generate_fatal_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 function integer get_baz(input integer bar); get_baz = bar; diff --git a/test_regress/t/t_genfor_hier.pl b/test_regress/t/t_genfor_hier.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_genfor_hier.pl +++ b/test_regress/t/t_genfor_hier.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_genfor_hier.v b/test_regress/t/t_genfor_hier.v index cf69e3f0d..87292a4fa 100644 --- a/test_regress/t/t_genfor_hier.v +++ b/test_regress/t/t_genfor_hier.v @@ -3,6 +3,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module m1(); logic v1; diff --git a/test_regress/t/t_genvar_for_bad.out b/test_regress/t/t_genvar_for_bad.out index 33409bfd1..e5e807319 100644 --- a/test_regress/t/t_genvar_for_bad.out +++ b/test_regress/t/t_genvar_for_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_genvar_for_bad.v:22: Genvar not legal in non-generate for (IEEE 1800-2017 27.4): 't.i' - : ... Suggest move for loop upwards to generate-level scope. - for (i=0; i 1); diff --git a/test_regress/t/t_genvar_for_bad.v b/test_regress/t/t_genvar_for_bad.v index 846878bba..7dab4cafb 100644 --- a/test_regress/t/t_genvar_for_bad.v +++ b/test_regress/t/t_genvar_for_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_genvar_misuse_bad.pl b/test_regress/t/t_genvar_misuse_bad.pl index 829aa9986..31116e9bd 100755 --- a/test_regress/t/t_genvar_misuse_bad.pl +++ b/test_regress/t/t_genvar_misuse_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug408"); diff --git a/test_regress/t/t_genvar_misuse_bad.v b/test_regress/t/t_genvar_misuse_bad.v index 7ab459216..5c21347c2 100644 --- a/test_regress/t/t_genvar_misuse_bad.v +++ b/test_regress/t/t_genvar_misuse_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // See bug408 module top diff --git a/test_regress/t/t_hierarchy_identifier.pl b/test_regress/t/t_hierarchy_identifier.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_hierarchy_identifier.pl +++ b/test_regress/t/t_hierarchy_identifier.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_hierarchy_identifier.v b/test_regress/t/t_hierarchy_identifier.v index 3774c7812..88586661c 100644 --- a/test_regress/t/t_hierarchy_identifier.v +++ b/test_regress/t/t_hierarchy_identifier.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_hierarchy_identifier_bad.out b/test_regress/t/t_hierarchy_identifier_bad.out index b3a3a702b..35817198e 100644 --- a/test_regress/t/t_hierarchy_identifier_bad.out +++ b/test_regress/t/t_hierarchy_identifier_bad.out @@ -1,17 +1,17 @@ -%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:33: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' - end : if_cnt_finish_bad - ^~~~~~~~~~~~~~~~~ +%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:34:10: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' + 34 | end : if_cnt_finish_bad + | ^~~~~~~~~~~~~~~~~ ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message. -%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:39: End label 'generate_for_bad' does not match begin label 'generate_for' - end : generate_for_bad - ^~~~~~~~~~~~~~~~ -%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:46: End label 'generate_if_if_bad' does not match begin label 'generate_if_if' - end : generate_if_if_bad - ^~~~~~~~~~~~~~~~~~ -%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:50: End label 'generate_if_else_bad' does not match begin label 'generate_if_else' - end : generate_if_else_bad - ^~~~~~~~~~~~~~~~~~~~ -%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:53: End label 't_bad' does not match begin label 't' -endmodule : t_bad - ^~~~~ +%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:40:10: End label 'generate_for_bad' does not match begin label 'generate_for' + 40 | end : generate_for_bad + | ^~~~~~~~~~~~~~~~ +%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:47:10: End label 'generate_if_if_bad' does not match begin label 'generate_if_if' + 47 | end : generate_if_if_bad + | ^~~~~~~~~~~~~~~~~~ +%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:51:10: End label 'generate_if_else_bad' does not match begin label 'generate_if_else' + 51 | end : generate_if_else_bad + | ^~~~~~~~~~~~~~~~~~~~ +%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:54:13: End label 't_bad' does not match begin label 't' + 54 | endmodule : t_bad + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_hierarchy_identifier_bad.pl b/test_regress/t/t_hierarchy_identifier_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_hierarchy_identifier_bad.pl +++ b/test_regress/t/t_hierarchy_identifier_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_hierarchy_identifier_bad.v b/test_regress/t/t_hierarchy_identifier_bad.v index f8f12de5a..c94d393e3 100644 --- a/test_regress/t/t_hierarchy_identifier_bad.v +++ b/test_regress/t/t_hierarchy_identifier_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_hierarchy_unnamed.pl b/test_regress/t/t_hierarchy_unnamed.pl index 0bafa73ba..a4d74c0ba 100755 --- a/test_regress/t/t_hierarchy_unnamed.pl +++ b/test_regress/t/t_hierarchy_unnamed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_hierarchy_unnamed.v b/test_regress/t/t_hierarchy_unnamed.v index 37b55d454..a4c82b403 100644 --- a/test_regress/t/t_hierarchy_unnamed.v +++ b/test_regress/t/t_hierarchy_unnamed.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Chandan Egbert. +// SPDX-License-Identifier: CC0-1.0 module sub(); endmodule diff --git a/test_regress/t/t_if_deep.pl b/test_regress/t/t_if_deep.pl index 803dca735..d6841bed0 100755 --- a/test_regress/t/t_if_deep.pl +++ b/test_regress/t/t_if_deep.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_if_deep.v b/test_regress/t/t_if_deep.v index 2cdf4a87e..e8217c4a9 100644 --- a/test_regress/t/t_if_deep.v +++ b/test_regress/t/t_if_deep.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_iff.pl b/test_regress/t/t_iff.pl index 2ebdc7e15..5fb4f0f50 100755 --- a/test_regress/t/t_iff.pl +++ b/test_regress/t/t_iff.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug1482, iff not supported"); diff --git a/test_regress/t/t_iff.v b/test_regress/t/t_iff.v index 422c3dbd0..963257cc4 100644 --- a/test_regress/t/t_iff.v +++ b/test_regress/t/t_iff.v @@ -1,19 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Use this file as a template for submitting bugs, etc. -// This module takes a single clock input, and should either -// $write("*-* All Finished *-*\n"); -// $finish; -// on success, or $stop. -// -// The code as shown applies a random vector to the Test -// module, then calculates a CRC on the Test module's outputs. -// -// **If you do not wish for your code to be released to the public -// please note it here, otherwise:** -// -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by ____YOUR_NAME_HERE____. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_init_concat.pl b/test_regress/t/t_init_concat.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_init_concat.pl +++ b/test_regress/t/t_init_concat.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_init_concat.v b/test_regress/t/t_init_concat.v index 4629ae2a4..c459d2caa 100644 --- a/test_regress/t/t_init_concat.v +++ b/test_regress/t/t_init_concat.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_initarray_nonarray.pl b/test_regress/t/t_initarray_nonarray.pl index 5c448de7c..d1bf185c9 100755 --- a/test_regress/t/t_initarray_nonarray.pl +++ b/test_regress/t/t_initarray_nonarray.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_initarray_nonarray.v b/test_regress/t/t_initarray_nonarray.v index b1a9f6c8a..3eb518264 100644 --- a/test_regress/t/t_initarray_nonarray.v +++ b/test_regress/t/t_initarray_nonarray.v @@ -5,6 +5,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 typedef logic [7:0] mask_t [7:0]; diff --git a/test_regress/t/t_initial.pl b/test_regress/t/t_initial.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_initial.pl +++ b/test_regress/t/t_initial.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_initial.v b/test_regress/t/t_initial.v index ef38c11ba..ee6d6476e 100644 --- a/test_regress/t/t_initial.v +++ b/test_regress/t/t_initial.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_initial_dlyass.pl b/test_regress/t/t_initial_dlyass.pl index 8b4eb7d5d..e1c047468 100755 --- a/test_regress/t/t_initial_dlyass.pl +++ b/test_regress/t/t_initial_dlyass.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_initial_dlyass.v b/test_regress/t/t_initial_dlyass.v index 820ec5c5b..5e86b628c 100644 --- a/test_regress/t/t_initial_dlyass.v +++ b/test_regress/t/t_initial_dlyass.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_initial_dlyass_bad.out b/test_regress/t/t_initial_dlyass_bad.out index ad57dba85..315854b57 100644 --- a/test_regress/t/t_initial_dlyass_bad.out +++ b/test_regress/t/t_initial_dlyass_bad.out @@ -1,10 +1,10 @@ -%Warning-INITIALDLY: t/t_initial_dlyass.v:17: Delayed assignments (<=) in initial or final block - : ... Suggest blocking assignments (=) - a <= 22; - ^~ +%Warning-INITIALDLY: t/t_initial_dlyass.v:18:9: Delayed assignments (<=) in initial or final block + : ... Suggest blocking assignments (=) + 18 | a <= 22; + | ^~ ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. -%Warning-INITIALDLY: t/t_initial_dlyass.v:18: Delayed assignments (<=) in initial or final block - : ... Suggest blocking assignments (=) - b <= 33; - ^~ +%Warning-INITIALDLY: t/t_initial_dlyass.v:19:9: Delayed assignments (<=) in initial or final block + : ... Suggest blocking assignments (=) + 19 | b <= 33; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_initial_dlyass_bad.pl b/test_regress/t/t_initial_dlyass_bad.pl index 488051e6a..073d596ca 100755 --- a/test_regress/t/t_initial_dlyass_bad.pl +++ b/test_regress/t/t_initial_dlyass_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_initial_edge.pl b/test_regress/t/t_initial_edge.pl index a07391fc7..2290dcdab 100755 --- a/test_regress/t/t_initial_edge.pl +++ b/test_regress/t/t_initial_edge.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_initial_edge.v b/test_regress/t/t_initial_edge.v index f45fce583..5cb903b9c 100644 --- a/test_regress/t/t_initial_edge.v +++ b/test_regress/t/t_initial_edge.v @@ -19,8 +19,9 @@ // thus matching the behaviour of a 4-state simulator. This is reportedly also // the behaviour of commercial cycle accurate modelling tools as well. // -// This file ONLY is placed into the Public Domain, for any use, without -// warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `timescale 1ns/1ns diff --git a/test_regress/t/t_initial_edge_bad.pl b/test_regress/t/t_initial_edge_bad.pl index 3a4a9fa92..713dcb8e1 100755 --- a/test_regress/t/t_initial_edge_bad.pl +++ b/test_regress/t/t_initial_edge_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # This works with other vlt_alls, we we don't run it for them. It should # fail with Verilator if --x-initial-edge is not specified. diff --git a/test_regress/t/t_initial_inc.vh b/test_regress/t/t_initial_inc.vh index 9aad43c46..503776881 100644 --- a/test_regress/t/t_initial_inc.vh +++ b/test_regress/t/t_initial_inc.vh @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define foo bar `ifdef foo diff --git a/test_regress/t/t_inside.pl b/test_regress/t/t_inside.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inside.pl +++ b/test_regress/t/t_inside.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inside.v b/test_regress/t/t_inside.v index 06adfe4e3..0e7b1e6be 100644 --- a/test_regress/t/t_inside.v +++ b/test_regress/t/t_inside.v @@ -1,7 +1,8 @@ // DESCRIPTION::Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_inside_wild.pl b/test_regress/t/t_inside_wild.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inside_wild.pl +++ b/test_regress/t/t_inside_wild.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inside_wild.v b/test_regress/t/t_inside_wild.v index 103721c31..7b377ffc6 100644 --- a/test_regress/t/t_inside_wild.v +++ b/test_regress/t/t_inside_wild.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_aport.pl b/test_regress/t/t_inst_aport.pl index adbfdeea8..0a056ddda 100755 --- a/test_regress/t/t_inst_aport.pl +++ b/test_regress/t/t_inst_aport.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); unsupported("Verilator/commercial slice unsupported, bug711"); diff --git a/test_regress/t/t_inst_aport.v b/test_regress/t/t_inst_aport.v index a5a258f5f..4773acb8b 100644 --- a/test_regress/t/t_inst_aport.v +++ b/test_regress/t/t_inst_aport.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_array.v b/test_regress/t/t_inst_array.v index be559dcb9..09171df9b 100644 --- a/test_regress/t/t_inst_array.v +++ b/test_regress/t/t_inst_array.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_array_bad.out b/test_regress/t/t_inst_array_bad.out index 9b36e36d8..312b0b4c3 100644 --- a/test_regress/t/t_inst_array_bad.out +++ b/test_regress/t/t_inst_array_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_inst_array_bad.v:18: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. - : ... In instance t - sub sub [7:0] (allbits, onebitbad, bitout); - ^~~~~~~~~ +%Error: t/t_inst_array_bad.v:19:28: Input port connection 'onebit' as part of a module instance array requires 1 or 8 bits, but connection's VARREF 'onebitbad' generates 9 bits. + : ... In instance t + 19 | sub sub [7:0] (allbits, onebitbad, bitout); + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_array_bad.pl b/test_regress/t/t_inst_array_bad.pl index 518625206..f3dd1d2a1 100755 --- a/test_regress/t/t_inst_array_bad.pl +++ b/test_regress/t/t_inst_array_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_inst_array_bad.v b/test_regress/t/t_inst_array_bad.v index f5f5989ea..c0261f9e3 100644 --- a/test_regress/t/t_inst_array_bad.v +++ b/test_regress/t/t_inst_array_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_array_connect.pl b/test_regress/t/t_inst_array_connect.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_inst_array_connect.pl +++ b/test_regress/t/t_inst_array_connect.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_array_connect.v b/test_regress/t/t_inst_array_connect.v index db4995f90..48d5af727 100644 --- a/test_regress/t/t_inst_array_connect.v +++ b/test_regress/t/t_inst_array_connect.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Julien Margetts. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ clk diff --git a/test_regress/t/t_inst_array_inl0.pl b/test_regress/t/t_inst_array_inl0.pl index c4cccd0b0..2f246d648 100755 --- a/test_regress/t/t_inst_array_inl0.pl +++ b/test_regress/t/t_inst_array_inl0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_array_inl1.pl b/test_regress/t/t_inst_array_inl1.pl index 497533ec6..d92c6d47e 100755 --- a/test_regress/t/t_inst_array_inl1.pl +++ b/test_regress/t/t_inst_array_inl1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_array_partial.pl b/test_regress/t/t_inst_array_partial.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_array_partial.pl +++ b/test_regress/t/t_inst_array_partial.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_array_partial.v b/test_regress/t/t_inst_array_partial.v index f12601507..a216bbe87 100644 --- a/test_regress/t/t_inst_array_partial.v +++ b/test_regress/t/t_inst_array_partial.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2011 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_ccall.pl b/test_regress/t/t_inst_ccall.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_ccall.pl +++ b/test_regress/t/t_inst_ccall.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_ccall.v b/test_regress/t/t_inst_ccall.v index 42a69d536..3416a5915 100644 --- a/test_regress/t/t_inst_ccall.v +++ b/test_regress/t/t_inst_ccall.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_comma.v b/test_regress/t/t_inst_comma.v index b8c6e438d..312f8d1c7 100644 --- a/test_regress/t/t_inst_comma.v +++ b/test_regress/t/t_inst_comma.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_comma_inl0.pl b/test_regress/t/t_inst_comma_inl0.pl index b9b6bc01a..426de0c8a 100755 --- a/test_regress/t/t_inst_comma_inl0.pl +++ b/test_regress/t/t_inst_comma_inl0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_comma_inl1.pl b/test_regress/t/t_inst_comma_inl1.pl index 553b96107..3619a2a4a 100755 --- a/test_regress/t/t_inst_comma_inl1.pl +++ b/test_regress/t/t_inst_comma_inl1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_darray.pl b/test_regress/t/t_inst_darray.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_darray.pl +++ b/test_regress/t/t_inst_darray.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_darray.v b/test_regress/t/t_inst_darray.v index acf610e0a..1e92b0e82 100644 --- a/test_regress/t/t_inst_darray.v +++ b/test_regress/t/t_inst_darray.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by John Stevenson. +// SPDX-License-Identifier: CC0-1.0 typedef logic [63:0] uid_t; typedef logic [31:0] value_t; diff --git a/test_regress/t/t_inst_dff.pl b/test_regress/t/t_inst_dff.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_inst_dff.pl +++ b/test_regress/t/t_inst_dff.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dff.v b/test_regress/t/t_inst_dff.v index 053b427fe..0e7214233 100644 --- a/test_regress/t/t_inst_dff.v +++ b/test_regress/t/t_inst_dff.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_dtree.v b/test_regress/t/t_inst_dtree.v index 11cfa9a46..5d3b48193 100644 --- a/test_regress/t/t_inst_dtree.v +++ b/test_regress/t/t_inst_dtree.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_dtree_inla.pl b/test_regress/t/t_inst_dtree_inla.pl index 3862d5166..12a6bfa87 100755 --- a/test_regress/t/t_inst_dtree_inla.pl +++ b/test_regress/t/t_inst_dtree_inla.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dtree_inlab.pl b/test_regress/t/t_inst_dtree_inlab.pl index a17eec491..0d3968897 100755 --- a/test_regress/t/t_inst_dtree_inlab.pl +++ b/test_regress/t/t_inst_dtree_inlab.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dtree_inlac.pl b/test_regress/t/t_inst_dtree_inlac.pl index 31f5e113c..266c21e6a 100755 --- a/test_regress/t/t_inst_dtree_inlac.pl +++ b/test_regress/t/t_inst_dtree_inlac.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dtree_inlad.pl b/test_regress/t/t_inst_dtree_inlad.pl index c9aa2cfec..a3252aac2 100755 --- a/test_regress/t/t_inst_dtree_inlad.pl +++ b/test_regress/t/t_inst_dtree_inlad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dtree_inlb.pl b/test_regress/t/t_inst_dtree_inlb.pl index ddf31e7f3..37140d54c 100755 --- a/test_regress/t/t_inst_dtree_inlb.pl +++ b/test_regress/t/t_inst_dtree_inlb.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dtree_inlbc.pl b/test_regress/t/t_inst_dtree_inlbc.pl index f2046ecfb..220cff813 100755 --- a/test_regress/t/t_inst_dtree_inlbc.pl +++ b/test_regress/t/t_inst_dtree_inlbc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dtree_inlbd.pl b/test_regress/t/t_inst_dtree_inlbd.pl index d9a539536..a1922dee7 100755 --- a/test_regress/t/t_inst_dtree_inlbd.pl +++ b/test_regress/t/t_inst_dtree_inlbd.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dtree_inlc.pl b/test_regress/t/t_inst_dtree_inlc.pl index c36be6cda..6aec14efe 100755 --- a/test_regress/t/t_inst_dtree_inlc.pl +++ b/test_regress/t/t_inst_dtree_inlc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dtree_inlcd.pl b/test_regress/t/t_inst_dtree_inlcd.pl index fcc73c54d..3ea63c940 100755 --- a/test_regress/t/t_inst_dtree_inlcd.pl +++ b/test_regress/t/t_inst_dtree_inlcd.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_dtree_inld.pl b/test_regress/t/t_inst_dtree_inld.pl index 5c16b1988..73cd4b063 100755 --- a/test_regress/t/t_inst_dtree_inld.pl +++ b/test_regress/t/t_inst_dtree_inld.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_first.pl b/test_regress/t/t_inst_first.pl index 2b81fb995..214a71ff8 100755 --- a/test_regress/t/t_inst_first.pl +++ b/test_regress/t/t_inst_first.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_first.v b/test_regress/t/t_inst_first.v index 293cb8f25..a1c7b7c42 100644 --- a/test_regress/t/t_inst_first.v +++ b/test_regress/t/t_inst_first.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_first_a.v b/test_regress/t/t_inst_first_a.v index 9fded3410..4e2d6c35e 100644 --- a/test_regress/t/t_inst_first_a.v +++ b/test_regress/t/t_inst_first_a.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_inst_first_a (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_inst_first_b.v b/test_regress/t/t_inst_first_b.v index 098429334..e60332429 100644 --- a/test_regress/t/t_inst_first_b.v +++ b/test_regress/t/t_inst_first_b.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_inst_first_b (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_inst_implicit.pl b/test_regress/t/t_inst_implicit.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_implicit.pl +++ b/test_regress/t/t_inst_implicit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_implicit.v b/test_regress/t/t_inst_implicit.v index f1875ce2a..5a3a407a5 100644 --- a/test_regress/t/t_inst_implicit.v +++ b/test_regress/t/t_inst_implicit.v @@ -1,7 +1,8 @@ // DESCRIPTION:tor:ilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_long_bad.out b/test_regress/t/t_inst_long_bad.out index 24c5fdbae..12d38a513 100644 --- a/test_regress/t/t_inst_long_bad.out +++ b/test_regress/t/t_inst_long_bad.out @@ -1,6 +1,6 @@ -%Error: obj_vlt/t_inst_long_bad/t_inst_long.v:4: Cannot find file containing module: 'long_long_long_long_long_long_lo__Vhsh1JZCXQVBM1QiASYlLmgTuAXYyUr7VAbJYwVHfiAD' - long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_ inst (); - ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: obj_vlt/t_inst_long_bad/t_inst_long.v:4:3: Cannot find file containing module: 'long_long_long_long_long_long_lo__Vhsh1JZCXQVBM1QiASYlLmgTuAXYyUr7VAbJYwVHfiAD' + 4 | long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_long_ inst (); + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ... Unsupported: Name is longer than 127 characters; automatic file lookup not supported. ... Suggest putting filename with this module/package onto command line instead. %Error: Exiting due to diff --git a/test_regress/t/t_inst_long_bad.pl b/test_regress/t/t_inst_long_bad.pl index 7bcd414ac..85fe7605d 100755 --- a/test_regress/t/t_inst_long_bad.pl +++ b/test_regress/t/t_inst_long_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use strict; diff --git a/test_regress/t/t_inst_misarray_bad.out b/test_regress/t/t_inst_misarray_bad.out index 76c55ddb7..0e0a9a157 100644 --- a/test_regress/t/t_inst_misarray_bad.out +++ b/test_regress/t/t_inst_misarray_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_inst_misarray_bad.v:16: VARREF 't.foo' is not an unpacked array, but is in an unpacked array context - : ... In instance t.foo - .foo(foo)); - ^~~ +%Error: t/t_inst_misarray_bad.v:17:27: VARREF 't.foo' is not an unpacked array, but is in an unpacked array context + : ... In instance t.foo + 17 | .foo(foo)); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_misarray_bad.pl b/test_regress/t/t_inst_misarray_bad.pl index 3f77205ae..32c62a917 100755 --- a/test_regress/t/t_inst_misarray_bad.pl +++ b/test_regress/t/t_inst_misarray_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_inst_misarray_bad.v b/test_regress/t/t_inst_misarray_bad.v index 3af9f7b6a..ab99ad05b 100644 --- a/test_regress/t/t_inst_misarray_bad.v +++ b/test_regress/t/t_inst_misarray_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_mism.pl b/test_regress/t/t_inst_mism.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_mism.pl +++ b/test_regress/t/t_inst_mism.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_mism.v b/test_regress/t/t_inst_mism.v index bf1710b8b..03c98e56d 100644 --- a/test_regress/t/t_inst_mism.v +++ b/test_regress/t/t_inst_mism.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Alex Solomatnikov. +// SPDX-License-Identifier: CC0-1.0 //bug595 diff --git a/test_regress/t/t_inst_missing.pl b/test_regress/t/t_inst_missing.pl index 6ff8eb890..1be9716bd 100755 --- a/test_regress/t/t_inst_missing.pl +++ b/test_regress/t/t_inst_missing.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_inst_missing.v b/test_regress/t/t_inst_missing.v index e2ea9c143..69ecc51fe 100644 --- a/test_regress/t/t_inst_missing.v +++ b/test_regress/t/t_inst_missing.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); wire ok = 1'b0; diff --git a/test_regress/t/t_inst_missing_bad.out b/test_regress/t/t_inst_missing_bad.out index 42aa1eade..38937a462 100644 --- a/test_regress/t/t_inst_missing_bad.out +++ b/test_regress/t/t_inst_missing_bad.out @@ -1,11 +1,11 @@ -%Warning-PINNOCONNECT: t/t_inst_missing_bad.v:8: Cell pin is not connected: '__pinNumber2' - sub sub (.ok(ok), , .nc()); - ^ +%Warning-PINNOCONNECT: t/t_inst_missing_bad.v:9:22: Cell pin is not connected: '__pinNumber2' + 9 | sub sub (.ok(ok), , .nc()); + | ^ ... Use "/* verilator lint_off PINNOCONNECT */" and lint_on around source to disable this message. -%Warning-PINCONNECTEMPTY: t/t_inst_missing_bad.v:8: Cell pin connected by name with empty reference: 'nc' - sub sub (.ok(ok), , .nc()); - ^~ -%Warning-PINMISSING: t/t_inst_missing_bad.v:8: Cell has missing pin: 'missing' - sub sub (.ok(ok), , .nc()); - ^~~ +%Warning-PINCONNECTEMPTY: t/t_inst_missing_bad.v:9:25: Cell pin connected by name with empty reference: 'nc' + 9 | sub sub (.ok(ok), , .nc()); + | ^~ +%Warning-PINMISSING: t/t_inst_missing_bad.v:9:8: Cell has missing pin: 'missing' + 9 | sub sub (.ok(ok), , .nc()); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_missing_bad.pl b/test_regress/t/t_inst_missing_bad.pl index 5ed028473..94c7e9d90 100755 --- a/test_regress/t/t_inst_missing_bad.pl +++ b/test_regress/t/t_inst_missing_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_inst_missing_bad.v b/test_regress/t/t_inst_missing_bad.v index 74089d365..73f782433 100644 --- a/test_regress/t/t_inst_missing_bad.v +++ b/test_regress/t/t_inst_missing_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); wire ok = 1'b0; diff --git a/test_regress/t/t_inst_mnpipe.pl b/test_regress/t/t_inst_mnpipe.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_inst_mnpipe.pl +++ b/test_regress/t/t_inst_mnpipe.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_mnpipe.v b/test_regress/t/t_inst_mnpipe.v index 1839e7bec..a96141c51 100644 --- a/test_regress/t/t_inst_mnpipe.v +++ b/test_regress/t/t_inst_mnpipe.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_notunsized.pl b/test_regress/t/t_inst_notunsized.pl index 7654e1a4e..f36d03dff 100755 --- a/test_regress/t/t_inst_notunsized.pl +++ b/test_regress/t/t_inst_notunsized.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_notunsized.v b/test_regress/t/t_inst_notunsized.v index bf62f8f15..07d68a38f 100644 --- a/test_regress/t/t_inst_notunsized.v +++ b/test_regress/t/t_inst_notunsized.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_overwide.pl b/test_regress/t/t_inst_overwide.pl index 129fe6db7..9fe760e8d 100755 --- a/test_regress/t/t_inst_overwide.pl +++ b/test_regress/t/t_inst_overwide.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_overwide.v b/test_regress/t/t_inst_overwide.v index 339cfc024..5c5d365f3 100644 --- a/test_regress/t/t_inst_overwide.v +++ b/test_regress/t/t_inst_overwide.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_inst_overwide_bad.out b/test_regress/t/t_inst_overwide_bad.out index 7465dfda7..ba813dbf5 100644 --- a/test_regress/t/t_inst_overwide_bad.out +++ b/test_regress/t/t_inst_overwide_bad.out @@ -1,18 +1,18 @@ -%Warning-WIDTH: t/t_inst_overwide.v:22: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. - : ... In instance t - .outy_w92 (outc_w30), - ^~~~~~~~ +%Warning-WIDTH: t/t_inst_overwide.v:23:14: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits. + : ... In instance t + 23 | .outy_w92 (outc_w30), + | ^~~~~~~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_inst_overwide.v:23: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. - : ... In instance t - .outz_w22 (outd_w73), - ^~~~~~~~ -%Warning-WIDTH: t/t_inst_overwide.v:26: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. - : ... In instance t - .inw_w31 (ina_w1), - ^~~~~~~ -%Warning-WIDTH: t/t_inst_overwide.v:27: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. - : ... In instance t - .inx_w11 (inb_w61) - ^~~~~~~ +%Warning-WIDTH: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. + : ... In instance t + 24 | .outz_w22 (outd_w73), + | ^~~~~~~~ +%Warning-WIDTH: t/t_inst_overwide.v:27:14: Input port connection 'inw_w31' expects 31 bits on the pin connection, but pin connection's VARREF 'ina_w1' generates 1 bits. + : ... In instance t + 27 | .inw_w31 (ina_w1), + | ^~~~~~~ +%Warning-WIDTH: t/t_inst_overwide.v:28:14: Input port connection 'inx_w11' expects 11 bits on the pin connection, but pin connection's VARREF 'inb_w61' generates 61 bits. + : ... In instance t + 28 | .inx_w11 (inb_w61) + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_overwide_bad.pl b/test_regress/t/t_inst_overwide_bad.pl index b03acf9eb..3226e8e46 100755 --- a/test_regress/t/t_inst_overwide_bad.pl +++ b/test_regress/t/t_inst_overwide_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_inst_port_array.pl b/test_regress/t/t_inst_port_array.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_port_array.pl +++ b/test_regress/t/t_inst_port_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_port_array.v b/test_regress/t/t_inst_port_array.v index dd697f074..ef5071f58 100644 --- a/test_regress/t/t_inst_port_array.v +++ b/test_regress/t/t_inst_port_array.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Alex Solomatnikov. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_prepost.pl b/test_regress/t/t_inst_prepost.pl index 5c448de7c..d1bf185c9 100755 --- a/test_regress/t/t_inst_prepost.pl +++ b/test_regress/t/t_inst_prepost.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_prepost.v b/test_regress/t/t_inst_prepost.v index a00ecf957..2d50acb37 100644 --- a/test_regress/t/t_inst_prepost.v +++ b/test_regress/t/t_inst_prepost.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; sub #(10,11,12,13) sub (); diff --git a/test_regress/t/t_inst_recurse2_bad.out b/test_regress/t/t_inst_recurse2_bad.out index 827e25a76..e44e2eaed 100644 --- a/test_regress/t/t_inst_recurse2_bad.out +++ b/test_regress/t/t_inst_recurse2_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_inst_recurse2_bad.v:17: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped' - : ... In instance t.looped.looped -module looped ( ); - ^~~~~~ +%Error: t/t_inst_recurse2_bad.v:18:8: Unsupported: Identically recursive module (module instantiates itself, without changing parameters): 'looped' + : ... In instance t.looped.looped + 18 | module looped ( ); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse2_bad.pl b/test_regress/t/t_inst_recurse2_bad.pl index ac8a3e44a..b1b5983b1 100755 --- a/test_regress/t/t_inst_recurse2_bad.pl +++ b/test_regress/t/t_inst_recurse2_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_recurse2_bad.v b/test_regress/t/t_inst_recurse2_bad.v index bbf649654..2cba45e12 100644 --- a/test_regress/t/t_inst_recurse2_bad.v +++ b/test_regress/t/t_inst_recurse2_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_recurse_bad.out b/test_regress/t/t_inst_recurse_bad.out index 9d4c8093f..2b2919a8c 100644 --- a/test_regress/t/t_inst_recurse_bad.out +++ b/test_regress/t/t_inst_recurse_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_inst_recurse_bad.v:17: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): 'looped' +%Error: t/t_inst_recurse_bad.v:18:8: Unsupported: Recursive multiple modules (module instantiates something leading back to itself): 'looped' ... note: self-recursion (module instantiating itself directly) is supported. -module looped ( ); - ^~~~~~ + 18 | module looped ( ); + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse_bad.pl b/test_regress/t/t_inst_recurse_bad.pl index ac8a3e44a..b1b5983b1 100755 --- a/test_regress/t/t_inst_recurse_bad.pl +++ b/test_regress/t/t_inst_recurse_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_recurse_bad.v b/test_regress/t/t_inst_recurse_bad.v index f0a28be7f..9a1048fa2 100644 --- a/test_regress/t/t_inst_recurse_bad.v +++ b/test_regress/t/t_inst_recurse_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_signed.pl b/test_regress/t/t_inst_signed.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_signed.pl +++ b/test_regress/t/t_inst_signed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_signed.v b/test_regress/t/t_inst_signed.v index c92c0e3f8..7529608ae 100644 --- a/test_regress/t/t_inst_signed.v +++ b/test_regress/t/t_inst_signed.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_signed1.pl b/test_regress/t/t_inst_signed1.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_signed1.pl +++ b/test_regress/t/t_inst_signed1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_signed1.v b/test_regress/t/t_inst_signed1.v index df3251073..a1b1e4d5d 100644 --- a/test_regress/t/t_inst_signed1.v +++ b/test_regress/t/t_inst_signed1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_slice.pl b/test_regress/t/t_inst_slice.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_slice.pl +++ b/test_regress/t/t_inst_slice.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_slice.v b/test_regress/t/t_inst_slice.v index 55a4c3594..1a56b6260 100644 --- a/test_regress/t/t_inst_slice.v +++ b/test_regress/t/t_inst_slice.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Varun Koyyalagunta. +// SPDX-License-Identifier: CC0-1.0 // bug1015 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_inst_slice_noinl.pl b/test_regress/t/t_inst_slice_noinl.pl index d9c0024d1..e0808c054 100755 --- a/test_regress/t/t_inst_slice_noinl.pl +++ b/test_regress/t/t_inst_slice_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_sv.pl b/test_regress/t/t_inst_sv.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_inst_sv.pl +++ b/test_regress/t/t_inst_sv.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_sv.v b/test_regress/t/t_inst_sv.v index e92973cee..ebde35b38 100644 --- a/test_regress/t/t_inst_sv.v +++ b/test_regress/t/t_inst_sv.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_tree.v b/test_regress/t/t_inst_tree.v index 44530ccd8..ea4ab1d3c 100644 --- a/test_regress/t/t_inst_tree.v +++ b/test_regress/t/t_inst_tree.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_tree_inl0_pub0.pl b/test_regress/t/t_inst_tree_inl0_pub0.pl index 20bb1d857..cdc077d31 100755 --- a/test_regress/t/t_inst_tree_inl0_pub0.pl +++ b/test_regress/t/t_inst_tree_inl0_pub0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -17,12 +18,12 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_inst_tree_inl0_pub0.vlt b/test_regress/t/t_inst_tree_inl0_pub0.vlt index dabc18533..4743c1224 100644 --- a/test_regress/t/t_inst_tree_inl0_pub0.vlt +++ b/test_regress/t/t_inst_tree_inl0_pub0.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_inst_tree_inl0_pub1.pl b/test_regress/t/t_inst_tree_inl0_pub1.pl index 9ba3d3b56..d3958b0fa 100755 --- a/test_regress/t/t_inst_tree_inl0_pub1.pl +++ b/test_regress/t/t_inst_tree_inl0_pub1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_tree_inl0_pub1.vlt b/test_regress/t/t_inst_tree_inl0_pub1.vlt index cddd66b4a..26d803b7d 100644 --- a/test_regress/t/t_inst_tree_inl0_pub1.vlt +++ b/test_regress/t/t_inst_tree_inl0_pub1.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl b/test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl index fce7d84dc..4a0c82b5a 100755 --- a/test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl +++ b/test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_tree_inl1_pub0.pl b/test_regress/t/t_inst_tree_inl1_pub0.pl index fe4c65c1e..9e0524e89 100755 --- a/test_regress/t/t_inst_tree_inl1_pub0.pl +++ b/test_regress/t/t_inst_tree_inl1_pub0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -17,9 +18,9 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_inst_tree_inl1_pub0.vlt b/test_regress/t/t_inst_tree_inl1_pub0.vlt index 177a14d24..b27dcbff4 100644 --- a/test_regress/t/t_inst_tree_inl1_pub0.vlt +++ b/test_regress/t/t_inst_tree_inl1_pub0.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_inst_tree_inl1_pub1.pl b/test_regress/t/t_inst_tree_inl1_pub1.pl index 7124a2dce..ed3c5580e 100755 --- a/test_regress/t/t_inst_tree_inl1_pub1.pl +++ b/test_regress/t/t_inst_tree_inl1_pub1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -18,9 +19,9 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_inst_tree_inl1_pub1.vlt b/test_regress/t/t_inst_tree_inl1_pub1.vlt index 8d917e7d4..fda247a74 100644 --- a/test_regress/t/t_inst_tree_inl1_pub1.vlt +++ b/test_regress/t/t_inst_tree_inl1_pub1.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_inst_v2k.pl b/test_regress/t/t_inst_v2k.pl index 9ec792a0a..8e2ba933f 100755 --- a/test_regress/t/t_inst_v2k.pl +++ b/test_regress/t/t_inst_v2k.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_v2k.v b/test_regress/t/t_inst_v2k.v index b2340e028..6e60406c2 100644 --- a/test_regress/t/t_inst_v2k.v +++ b/test_regress/t/t_inst_v2k.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_inst_v2k__sub.vi b/test_regress/t/t_inst_v2k__sub.vi index ac75409db..ee4ee74b1 100644 --- a/test_regress/t/t_inst_v2k__sub.vi +++ b/test_regress/t/t_inst_v2k__sub.vi @@ -1,8 +1,9 @@ // -*- Verilog -*- // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // This file is named .vi to test +libext+ flags. module t_inst_v2k__sub diff --git a/test_regress/t/t_inst_wideconst.pl b/test_regress/t/t_inst_wideconst.pl index 60667b1d5..0373cc976 100755 --- a/test_regress/t/t_inst_wideconst.pl +++ b/test_regress/t/t_inst_wideconst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_inst_wideconst.v b/test_regress/t/t_inst_wideconst.v index 5e8423576..42a535f88 100644 --- a/test_regress/t/t_inst_wideconst.v +++ b/test_regress/t/t_inst_wideconst.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_interface.pl b/test_regress/t/t_interface.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_interface.pl +++ b/test_regress/t/t_interface.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface.v b/test_regress/t/t_interface.v index 1a9b8f0d7..608d3e443 100644 --- a/test_regress/t/t_interface.v +++ b/test_regress/t/t_interface.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_interface1.pl b/test_regress/t/t_interface1.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface1.pl +++ b/test_regress/t/t_interface1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface1.v b/test_regress/t/t_interface1.v index 3b3f9164a..569222085 100644 --- a/test_regress/t/t_interface1.v +++ b/test_regress/t/t_interface1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface1_modport.pl b/test_regress/t/t_interface1_modport.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface1_modport.pl +++ b/test_regress/t/t_interface1_modport.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface1_modport.v b/test_regress/t/t_interface1_modport.v index bf6923337..42ec3a821 100644 --- a/test_regress/t/t_interface1_modport.v +++ b/test_regress/t/t_interface1_modport.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface1_modport_nansi.pl b/test_regress/t/t_interface1_modport_nansi.pl index 29c3e909c..9a17be84f 100755 --- a/test_regress/t/t_interface1_modport_nansi.pl +++ b/test_regress/t/t_interface1_modport_nansi.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface1_modport_noinl.pl b/test_regress/t/t_interface1_modport_noinl.pl index a04b71dbe..9ccb327da 100755 --- a/test_regress/t/t_interface1_modport_noinl.pl +++ b/test_regress/t/t_interface1_modport_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface1_modport_trace.pl b/test_regress/t/t_interface1_modport_trace.pl index 336f9b7e8..54ac1c910 100755 --- a/test_regress/t/t_interface1_modport_trace.pl +++ b/test_regress/t/t_interface1_modport_trace.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface1_noinl.pl b/test_regress/t/t_interface1_noinl.pl index addef5226..18fdf1bc2 100755 --- a/test_regress/t/t_interface1_noinl.pl +++ b/test_regress/t/t_interface1_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface2.pl b/test_regress/t/t_interface2.pl index ccc8e57db..3921afc0f 100755 --- a/test_regress/t/t_interface2.pl +++ b/test_regress/t/t_interface2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface2.v b/test_regress/t/t_interface2.v index efe2611ab..caa6c1591 100644 --- a/test_regress/t/t_interface2.v +++ b/test_regress/t/t_interface2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_interface2_noinl.pl b/test_regress/t/t_interface2_noinl.pl index 782f20df7..3ed910af1 100755 --- a/test_regress/t/t_interface2_noinl.pl +++ b/test_regress/t/t_interface2_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_array.pl b/test_regress/t/t_interface_array.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_interface_array.pl +++ b/test_regress/t/t_interface_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_array.v b/test_regress/t/t_interface_array.v index 820b7f3c8..41a4a571b 100644 --- a/test_regress/t/t_interface_array.v +++ b/test_regress/t/t_interface_array.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; diff --git a/test_regress/t/t_interface_array_bad.out b/test_regress/t/t_interface_array_bad.out index e1004d1ab..0caac3af4 100644 --- a/test_regress/t/t_interface_array_bad.out +++ b/test_regress/t/t_interface_array_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_interface_array_bad.v:22: Expecting expression to be constant, but variable isn't const: 'bar' - : ... In instance t - assign foos[bar].a = 1'b1; - ^~~ -%Error: t/t_interface_array_bad.v:22: Could not expand constant selection inside dotted reference: 'bar' - : ... In instance t - assign foos[bar].a = 1'b1; - ^ +%Error: t/t_interface_array_bad.v:23:16: Expecting expression to be constant, but variable isn't const: 'bar' + : ... In instance t + 23 | assign foos[bar].a = 1'b1; + | ^~~ +%Error: t/t_interface_array_bad.v:23:15: Could not expand constant selection inside dotted reference: 'bar' + : ... In instance t + 23 | assign foos[bar].a = 1'b1; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_interface_array_bad.pl b/test_regress/t/t_interface_array_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_interface_array_bad.pl +++ b/test_regress/t/t_interface_array_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_array_bad.v b/test_regress/t/t_interface_array_bad.v index 2f550845b..07754dc9b 100644 --- a/test_regress/t/t_interface_array_bad.v +++ b/test_regress/t/t_interface_array_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; diff --git a/test_regress/t/t_interface_array_modport.pl b/test_regress/t/t_interface_array_modport.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_interface_array_modport.pl +++ b/test_regress/t/t_interface_array_modport.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_array_modport.v b/test_regress/t/t_interface_array_modport.v index cc6c5dc24..b63100f9a 100644 --- a/test_regress/t/t_interface_array_modport.v +++ b/test_regress/t/t_interface_array_modport.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; diff --git a/test_regress/t/t_interface_array_nocolon.pl b/test_regress/t/t_interface_array_nocolon.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_interface_array_nocolon.pl +++ b/test_regress/t/t_interface_array_nocolon.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_array_nocolon.v b/test_regress/t/t_interface_array_nocolon.v index a30690af0..7536b49ce 100644 --- a/test_regress/t/t_interface_array_nocolon.v +++ b/test_regress/t/t_interface_array_nocolon.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Mike Popoloski. +// SPDX-License-Identifier: CC0-1.0 interface foo_intf ( diff --git a/test_regress/t/t_interface_array_nocolon_bad.out b/test_regress/t/t_interface_array_nocolon_bad.out index 20fef2ba7..6d528dd58 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.out +++ b/test_regress/t/t_interface_array_nocolon_bad.out @@ -1,18 +1,18 @@ -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:25: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 - : ... In instance t - foo_intf foos [N] (.x(X)); - ^ +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 + : ... In instance t + 26 | foo_intf foos [N] (.x(X)); + | ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 - : ... In instance t - foo_intf fool [1:3] (.x(X)); - ^ -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:29: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 - : ... In instance t - foo_subm subs [N] (.x(X)); - ^ -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 - : ... In instance t - foo_subm subl [1:3] (.x(X)); - ^ +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 + : ... In instance t + 27 | foo_intf fool [1:3] (.x(X)); + | ^ +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 + : ... In instance t + 30 | foo_subm subs [N] (.x(X)); + | ^ +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 + : ... In instance t + 31 | foo_subm subl [1:3] (.x(X)); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_interface_array_nocolon_bad.pl b/test_regress/t/t_interface_array_nocolon_bad.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_interface_array_nocolon_bad.pl +++ b/test_regress/t/t_interface_array_nocolon_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_interface_array_nocolon_bad.v b/test_regress/t/t_interface_array_nocolon_bad.v index 0056d5d34..94431d640 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.v +++ b/test_regress/t/t_interface_array_nocolon_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Mike Popoloski. +// SPDX-License-Identifier: CC0-1.0 interface foo_intf ( diff --git a/test_regress/t/t_interface_array_noinl.pl b/test_regress/t/t_interface_array_noinl.pl index 740409044..90b52bc1a 100755 --- a/test_regress/t/t_interface_array_noinl.pl +++ b/test_regress/t/t_interface_array_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_arraymux.pl b/test_regress/t/t_interface_arraymux.pl index 0bafa73ba..a4d74c0ba 100755 --- a/test_regress/t/t_interface_arraymux.pl +++ b/test_regress/t/t_interface_arraymux.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_interface_arraymux.v b/test_regress/t/t_interface_arraymux.v index e9345a5cd..8709cbca4 100644 --- a/test_regress/t/t_interface_arraymux.v +++ b/test_regress/t/t_interface_arraymux.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by John Stevenson. +// SPDX-License-Identifier: CC0-1.0 package pkg; typedef logic [31:0] unique_id_t; diff --git a/test_regress/t/t_interface_asvar_bad.out b/test_regress/t/t_interface_asvar_bad.out index ce338eb60..ffcdb86d7 100644 --- a/test_regress/t/t_interface_asvar_bad.out +++ b/test_regress/t/t_interface_asvar_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_interface_asvar_bad.v:28: Operator ASSIGN expected non-interface on Assign RHS but 'itf' is an interface. - : ... In instance t.source - getter = itf; - ^~~ -%Error: t/t_interface_asvar_bad.v:29: Operator ADD expected non-interface on RHS but 'itf' is an interface. - : ... In instance t.source - getter = 4'd3 + itf; - ^~~ +%Error: t/t_interface_asvar_bad.v:29:16: Operator ASSIGN expected non-interface on Assign RHS but 'itf' is an interface. + : ... In instance t.source + 29 | getter = itf; + | ^~~ +%Error: t/t_interface_asvar_bad.v:30:23: Operator ADD expected non-interface on RHS but 'itf' is an interface. + : ... In instance t.source + 30 | getter = 4'd3 + itf; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_asvar_bad.pl b/test_regress/t/t_interface_asvar_bad.pl index dd358bf5b..8f0a03228 100755 --- a/test_regress/t/t_interface_asvar_bad.pl +++ b/test_regress/t/t_interface_asvar_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_interface_asvar_bad.v b/test_regress/t/t_interface_asvar_bad.v index aba9711dd..3238103d4 100644 --- a/test_regress/t/t_interface_asvar_bad.v +++ b/test_regress/t/t_interface_asvar_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_interface_bind_public.pl b/test_regress/t/t_interface_bind_public.pl index 60667b1d5..0373cc976 100755 --- a/test_regress/t/t_interface_bind_public.pl +++ b/test_regress/t/t_interface_bind_public.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_bind_public.v b/test_regress/t/t_interface_bind_public.v index c10851744..a95c01dfe 100644 --- a/test_regress/t/t_interface_bind_public.v +++ b/test_regress/t/t_interface_bind_public.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Alex Solomatnikov. +// SPDX-License-Identifier: CC0-1.0 interface hex2ram_if ( diff --git a/test_regress/t/t_interface_down.pl b/test_regress/t/t_interface_down.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_down.pl +++ b/test_regress/t/t_interface_down.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down.v b/test_regress/t/t_interface_down.v index bec0b2d9b..5925649f5 100644 --- a/test_regress/t/t_interface_down.v +++ b/test_regress/t/t_interface_down.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; diff --git a/test_regress/t/t_interface_down_gen.pl b/test_regress/t/t_interface_down_gen.pl index 371930c4e..b0147e5ba 100755 --- a/test_regress/t/t_interface_down_gen.pl +++ b/test_regress/t/t_interface_down_gen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, interface generates changing types"); diff --git a/test_regress/t/t_interface_down_gen.v b/test_regress/t/t_interface_down_gen.v index 31117d357..716d9bf71 100644 --- a/test_regress/t/t_interface_down_gen.v +++ b/test_regress/t/t_interface_down_gen.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // This test demonstrates how not only parameters but the type of a parent // interface could propagate down to child modules, changing their data type diff --git a/test_regress/t/t_interface_down_inla.pl b/test_regress/t/t_interface_down_inla.pl index 091f1e378..94da72fa9 100755 --- a/test_regress/t/t_interface_down_inla.pl +++ b/test_regress/t/t_interface_down_inla.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_inlab.pl b/test_regress/t/t_interface_down_inlab.pl index d656df509..e3058afb3 100755 --- a/test_regress/t/t_interface_down_inlab.pl +++ b/test_regress/t/t_interface_down_inlab.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_inlac.pl b/test_regress/t/t_interface_down_inlac.pl index 1480307b8..87c1d0557 100755 --- a/test_regress/t/t_interface_down_inlac.pl +++ b/test_regress/t/t_interface_down_inlac.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_inlad.pl b/test_regress/t/t_interface_down_inlad.pl index e406a91a9..5c1aa70b5 100755 --- a/test_regress/t/t_interface_down_inlad.pl +++ b/test_regress/t/t_interface_down_inlad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_inlb.pl b/test_regress/t/t_interface_down_inlb.pl index ed32d18c8..12252f189 100755 --- a/test_regress/t/t_interface_down_inlb.pl +++ b/test_regress/t/t_interface_down_inlb.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_inlbc.pl b/test_regress/t/t_interface_down_inlbc.pl index 42584154b..71ec4de4e 100755 --- a/test_regress/t/t_interface_down_inlbc.pl +++ b/test_regress/t/t_interface_down_inlbc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_inlbd.pl b/test_regress/t/t_interface_down_inlbd.pl index 76a90e4c6..3b0825c62 100755 --- a/test_regress/t/t_interface_down_inlbd.pl +++ b/test_regress/t/t_interface_down_inlbd.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_inlc.pl b/test_regress/t/t_interface_down_inlc.pl index 0c58dd9b8..3ca34b12c 100755 --- a/test_regress/t/t_interface_down_inlc.pl +++ b/test_regress/t/t_interface_down_inlc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_inlcd.pl b/test_regress/t/t_interface_down_inlcd.pl index b5b9ae967..097f7d332 100755 --- a/test_regress/t/t_interface_down_inlcd.pl +++ b/test_regress/t/t_interface_down_inlcd.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_inld.pl b/test_regress/t/t_interface_down_inld.pl index 2fb5e886f..93712a32c 100755 --- a/test_regress/t/t_interface_down_inld.pl +++ b/test_regress/t/t_interface_down_inld.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_down_noinl.pl b/test_regress/t/t_interface_down_noinl.pl index 2921a7686..a1f024b08 100755 --- a/test_regress/t/t_interface_down_noinl.pl +++ b/test_regress/t/t_interface_down_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_dups.pl b/test_regress/t/t_interface_dups.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_dups.pl +++ b/test_regress/t/t_interface_dups.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_dups.v b/test_regress/t/t_interface_dups.v index aa4281f1d..d434618f5 100644 --- a/test_regress/t/t_interface_dups.v +++ b/test_regress/t/t_interface_dups.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_interface_gen.pl b/test_regress/t/t_interface_gen.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen.pl +++ b/test_regress/t/t_interface_gen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen.v b/test_regress/t/t_interface_gen.v index 37f0dc29e..f4f8511f3 100644 --- a/test_regress/t/t_interface_gen.v +++ b/test_regress/t/t_interface_gen.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface_gen10.pl b/test_regress/t/t_interface_gen10.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen10.pl +++ b/test_regress/t/t_interface_gen10.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen10.v b/test_regress/t/t_interface_gen10.v index 0c7c73f69..2e64f700f 100644 --- a/test_regress/t/t_interface_gen10.v +++ b/test_regress/t/t_interface_gen10.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen10_noinl.pl b/test_regress/t/t_interface_gen10_noinl.pl index b2d964809..89cfa9d60 100755 --- a/test_regress/t/t_interface_gen10_noinl.pl +++ b/test_regress/t/t_interface_gen10_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen11.pl b/test_regress/t/t_interface_gen11.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen11.pl +++ b/test_regress/t/t_interface_gen11.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen11.v b/test_regress/t/t_interface_gen11.v index 9ce191346..62acbbba7 100644 --- a/test_regress/t/t_interface_gen11.v +++ b/test_regress/t/t_interface_gen11.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen11_noinl.pl b/test_regress/t/t_interface_gen11_noinl.pl index 41dbe23b8..378bfeff4 100755 --- a/test_regress/t/t_interface_gen11_noinl.pl +++ b/test_regress/t/t_interface_gen11_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen12.pl b/test_regress/t/t_interface_gen12.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen12.pl +++ b/test_regress/t/t_interface_gen12.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen12.v b/test_regress/t/t_interface_gen12.v index d93315bf7..bbf87fff1 100644 --- a/test_regress/t/t_interface_gen12.v +++ b/test_regress/t/t_interface_gen12.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // bug1005 diff --git a/test_regress/t/t_interface_gen12_noinl.pl b/test_regress/t/t_interface_gen12_noinl.pl index 1bde2074b..32dfbfb7a 100755 --- a/test_regress/t/t_interface_gen12_noinl.pl +++ b/test_regress/t/t_interface_gen12_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen2.pl b/test_regress/t/t_interface_gen2.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen2.pl +++ b/test_regress/t/t_interface_gen2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen2.v b/test_regress/t/t_interface_gen2.v index 13f0acbd5..83d5643db 100644 --- a/test_regress/t/t_interface_gen2.v +++ b/test_regress/t/t_interface_gen2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface_gen2_collision.pl b/test_regress/t/t_interface_gen2_collision.pl index e716bcb83..38e9eed6b 100755 --- a/test_regress/t/t_interface_gen2_collision.pl +++ b/test_regress/t/t_interface_gen2_collision.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen2_noinl.pl b/test_regress/t/t_interface_gen2_noinl.pl index 60b79c8ea..477887775 100755 --- a/test_regress/t/t_interface_gen2_noinl.pl +++ b/test_regress/t/t_interface_gen2_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen3.pl b/test_regress/t/t_interface_gen3.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen3.pl +++ b/test_regress/t/t_interface_gen3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen3.v b/test_regress/t/t_interface_gen3.v index e3c107ca8..59833d42c 100644 --- a/test_regress/t/t_interface_gen3.v +++ b/test_regress/t/t_interface_gen3.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Very simple test for interface pathclearing diff --git a/test_regress/t/t_interface_gen3_collision.pl b/test_regress/t/t_interface_gen3_collision.pl index f435422b5..efbdcc7f8 100755 --- a/test_regress/t/t_interface_gen3_collision.pl +++ b/test_regress/t/t_interface_gen3_collision.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen3_noinl.pl b/test_regress/t/t_interface_gen3_noinl.pl index 423aae5dc..1895ad227 100755 --- a/test_regress/t/t_interface_gen3_noinl.pl +++ b/test_regress/t/t_interface_gen3_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen4.pl b/test_regress/t/t_interface_gen4.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen4.pl +++ b/test_regress/t/t_interface_gen4.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen4.v b/test_regress/t/t_interface_gen4.v index 7678ac0a2..2c370310a 100644 --- a/test_regress/t/t_interface_gen4.v +++ b/test_regress/t/t_interface_gen4.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug789 generates diff --git a/test_regress/t/t_interface_gen4_noinl.pl b/test_regress/t/t_interface_gen4_noinl.pl index 130c1e314..4e1616c21 100755 --- a/test_regress/t/t_interface_gen4_noinl.pl +++ b/test_regress/t/t_interface_gen4_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen5.pl b/test_regress/t/t_interface_gen5.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen5.pl +++ b/test_regress/t/t_interface_gen5.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen5.v b/test_regress/t/t_interface_gen5.v index e497673ad..584db2bff 100644 --- a/test_regress/t/t_interface_gen5.v +++ b/test_regress/t/t_interface_gen5.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen5_noinl.pl b/test_regress/t/t_interface_gen5_noinl.pl index ea149c55b..a3a82fe7f 100755 --- a/test_regress/t/t_interface_gen5_noinl.pl +++ b/test_regress/t/t_interface_gen5_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen6.pl b/test_regress/t/t_interface_gen6.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen6.pl +++ b/test_regress/t/t_interface_gen6.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen6.v b/test_regress/t/t_interface_gen6.v index dfcec0972..4b7ef5dee 100644 --- a/test_regress/t/t_interface_gen6.v +++ b/test_regress/t/t_interface_gen6.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // bug1001 diff --git a/test_regress/t/t_interface_gen6_noinl.pl b/test_regress/t/t_interface_gen6_noinl.pl index 63b10b62d..af6821514 100755 --- a/test_regress/t/t_interface_gen6_noinl.pl +++ b/test_regress/t/t_interface_gen6_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen7.pl b/test_regress/t/t_interface_gen7.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen7.pl +++ b/test_regress/t/t_interface_gen7.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen7.v b/test_regress/t/t_interface_gen7.v index c1a0d2a41..3965e3602 100644 --- a/test_regress/t/t_interface_gen7.v +++ b/test_regress/t/t_interface_gen7.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen7_noinl.pl b/test_regress/t/t_interface_gen7_noinl.pl index eb3a4b4bb..f0b6c523c 100755 --- a/test_regress/t/t_interface_gen7_noinl.pl +++ b/test_regress/t/t_interface_gen7_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen8.pl b/test_regress/t/t_interface_gen8.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen8.pl +++ b/test_regress/t/t_interface_gen8.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen8.v b/test_regress/t/t_interface_gen8.v index be7080bd9..10b7373a8 100644 --- a/test_regress/t/t_interface_gen8.v +++ b/test_regress/t/t_interface_gen8.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen8_noinl.pl b/test_regress/t/t_interface_gen8_noinl.pl index 7cc674f2b..0275b2504 100755 --- a/test_regress/t/t_interface_gen8_noinl.pl +++ b/test_regress/t/t_interface_gen8_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen9.pl b/test_regress/t/t_interface_gen9.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_gen9.pl +++ b/test_regress/t/t_interface_gen9.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen9.v b/test_regress/t/t_interface_gen9.v index 10a2f838b..89d75adfb 100644 --- a/test_regress/t/t_interface_gen9.v +++ b/test_regress/t/t_interface_gen9.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 // bug998 diff --git a/test_regress/t/t_interface_gen9_noinl.pl b/test_regress/t/t_interface_gen9_noinl.pl index c8a37074e..e3f52153b 100755 --- a/test_regress/t/t_interface_gen9_noinl.pl +++ b/test_regress/t/t_interface_gen9_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_gen_noinl.pl b/test_regress/t/t_interface_gen_noinl.pl index 3f5a8ebcb..cefc49c45 100755 --- a/test_regress/t/t_interface_gen_noinl.pl +++ b/test_regress/t/t_interface_gen_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_inl.pl b/test_regress/t/t_interface_inl.pl index a15b99c13..abb511f5e 100755 --- a/test_regress/t/t_interface_inl.pl +++ b/test_regress/t/t_interface_inl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_mismodport_bad.out b/test_regress/t/t_interface_mismodport_bad.out index d829e3a74..20e79489d 100644 --- a/test_regress/t/t_interface_mismodport_bad.out +++ b/test_regress/t/t_interface_mismodport_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_interface_mismodport_bad.v:35: Can't find definition of 'bad' in dotted signal: 'isub.bad' - isub.bad = i_value; - ^~~ +%Error: t/t_interface_mismodport_bad.v:36:12: Can't find definition of 'bad' in dotted signal: 'isub.bad' + 36 | isub.bad = i_value; + | ^~~ ... Known scopes under 'bad': %Error: Exiting due to diff --git a/test_regress/t/t_interface_mismodport_bad.pl b/test_regress/t/t_interface_mismodport_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_interface_mismodport_bad.pl +++ b/test_regress/t/t_interface_mismodport_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_interface_mismodport_bad.v b/test_regress/t/t_interface_mismodport_bad.v index 80e6f01f4..1b5f656fc 100644 --- a/test_regress/t/t_interface_mismodport_bad.v +++ b/test_regress/t/t_interface_mismodport_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface ifc; integer ok; diff --git a/test_regress/t/t_interface_missing_bad.out b/test_regress/t/t_interface_missing_bad.out index 28c69c288..2e5302cfe 100644 --- a/test_regress/t/t_interface_missing_bad.out +++ b/test_regress/t/t_interface_missing_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_interface_missing_bad.v:13: Cannot find file containing interface: 'foo_intf' - foo_intf foo - ^~~~~~~~ -%Error: t/t_interface_missing_bad.v:19: Cannot find file containing interface: 'foo_intf' - foo_intf the_foo (); - ^~~~~~~~ -%Error: t/t_interface_missing_bad.v:24: Found definition of 'the_foo' as a CELL but expected a variable - .foo (the_foo) - ^~~~~~~ +%Error: t/t_interface_missing_bad.v:14:4: Cannot find file containing interface: 'foo_intf' + 14 | foo_intf foo + | ^~~~~~~~ +%Error: t/t_interface_missing_bad.v:20:4: Cannot find file containing interface: 'foo_intf' + 20 | foo_intf the_foo (); + | ^~~~~~~~ +%Error: t/t_interface_missing_bad.v:25:15: Found definition of 'the_foo' as a CELL but expected a variable + 25 | .foo (the_foo) + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_missing_bad.pl b/test_regress/t/t_interface_missing_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_interface_missing_bad.pl +++ b/test_regress/t/t_interface_missing_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_missing_bad.v b/test_regress/t/t_interface_missing_bad.v index 9e7209976..eb03718e2 100644 --- a/test_regress/t/t_interface_missing_bad.v +++ b/test_regress/t/t_interface_missing_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 // Interface intentionally not defined //interface foo_intf; diff --git a/test_regress/t/t_interface_modport.pl b/test_regress/t/t_interface_modport.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_modport.pl +++ b/test_regress/t/t_interface_modport.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_modport.v b/test_regress/t/t_interface_modport.v index 9544463d0..162963511 100644 --- a/test_regress/t/t_interface_modport.v +++ b/test_regress/t/t_interface_modport.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface counter_if; logic [3:0] value; diff --git a/test_regress/t/t_interface_modport_bad.out b/test_regress/t/t_interface_modport_bad.out index 4491a623a..cad2aaa0c 100644 --- a/test_regress/t/t_interface_modport_bad.out +++ b/test_regress/t/t_interface_modport_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_interface_modport_bad.v:22: Modport not found under interface 'ifc': 'oop_modport' - : ... Suggested alternative: 'out_modport' - ifc.oop_modport isub, - ^~~~~~~~~~~ +%Error: t/t_interface_modport_bad.v:23:8: Modport not found under interface 'ifc': 'oop_modport' + : ... Suggested alternative: 'out_modport' + 23 | ifc.oop_modport isub, + | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_modport_bad.pl b/test_regress/t/t_interface_modport_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_interface_modport_bad.pl +++ b/test_regress/t/t_interface_modport_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_interface_modport_bad.v b/test_regress/t/t_interface_modport_bad.v index 012aef164..8d9efffc9 100644 --- a/test_regress/t/t_interface_modport_bad.v +++ b/test_regress/t/t_interface_modport_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface ifc; integer ok; diff --git a/test_regress/t/t_interface_modport_dir_bad.out b/test_regress/t/t_interface_modport_dir_bad.out index 8ea68f01f..927f0c16e 100644 --- a/test_regress/t/t_interface_modport_dir_bad.out +++ b/test_regress/t/t_interface_modport_dir_bad.out @@ -1,12 +1,12 @@ -#Expecting something along the line of: +Expecting something along the line of: - %Error: t/t_interface_modport_dir_bad.v:36: Attempt to drive input-only modport: 'data' - : ... In instance t.source_i.source_i - ctrl.data <= ~ctrl.data; - ^~~~ - %Error: Exiting due to 1 error(s) - %Error: t/t_interface_modport_dir_bad.v:37: Attempt to drive input-only modport: 'valid' - : ... In instance t.source_i.source_i - ctrl.valid<= ~ctrl.valid; - ^~~~ - %Error: Exiting due to 1 error(s) +%Error: t/t_interface_modport_dir_bad.v:36: Attempt to drive input-only modport: 'data' +: ... In instance t.source_i.source_i +ctrl.data <= ~ctrl.data; +^~~~ +%Error: Exiting due to 1 error(s) +%Error: t/t_interface_modport_dir_bad.v:37: Attempt to drive input-only modport: 'valid' +: ... In instance t.source_i.source_i +ctrl.valid<= ~ctrl.valid; +^~~~ +%Error: Exiting due to 1 error(s) diff --git a/test_regress/t/t_interface_modport_dir_bad.pl b/test_regress/t/t_interface_modport_dir_bad.pl index e14ecd58d..1f547e042 100755 --- a/test_regress/t/t_interface_modport_dir_bad.pl +++ b/test_regress/t/t_interface_modport_dir_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, bug1622"); diff --git a/test_regress/t/t_interface_modport_dir_bad.v b/test_regress/t/t_interface_modport_dir_bad.v index 2b554ccea..477215312 100644 --- a/test_regress/t/t_interface_modport_dir_bad.v +++ b/test_regress/t/t_interface_modport_dir_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi +// SPDX-License-Identifier: CC0-1.0 interface validData ( diff --git a/test_regress/t/t_interface_modport_export.pl b/test_regress/t/t_interface_modport_export.pl index c28073c62..4513b2353 100755 --- a/test_regress/t/t_interface_modport_export.pl +++ b/test_regress/t/t_interface_modport_export.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug696"); diff --git a/test_regress/t/t_interface_modport_export.v b/test_regress/t/t_interface_modport_export.v index 11a59f135..e00ec479f 100644 --- a/test_regress/t/t_interface_modport_export.v +++ b/test_regress/t/t_interface_modport_export.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 interface test_if; diff --git a/test_regress/t/t_interface_modport_import.pl b/test_regress/t/t_interface_modport_import.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_interface_modport_import.pl +++ b/test_regress/t/t_interface_modport_import.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_modport_import.v b/test_regress/t/t_interface_modport_import.v index c963fbff7..57363e22b 100644 --- a/test_regress/t/t_interface_modport_import.v +++ b/test_regress/t/t_interface_modport_import.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 interface test_if; diff --git a/test_regress/t/t_interface_modport_import_noinl.pl b/test_regress/t/t_interface_modport_import_noinl.pl index eb3847bf8..e78a0753f 100755 --- a/test_regress/t/t_interface_modport_import_noinl.pl +++ b/test_regress/t/t_interface_modport_import_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_modport_inl.pl b/test_regress/t/t_interface_modport_inl.pl index 559f782ee..88a6d9a1e 100755 --- a/test_regress/t/t_interface_modport_inl.pl +++ b/test_regress/t/t_interface_modport_inl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_modport_noinl.pl b/test_regress/t/t_interface_modport_noinl.pl index d699c37b4..0c34a3249 100755 --- a/test_regress/t/t_interface_modport_noinl.pl +++ b/test_regress/t/t_interface_modport_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_modportlist.pl b/test_regress/t/t_interface_modportlist.pl index a02f58336..21d10121b 100755 --- a/test_regress/t/t_interface_modportlist.pl +++ b/test_regress/t/t_interface_modportlist.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_modportlist.v b/test_regress/t/t_interface_modportlist.v index 20ac0241e..c72fa490f 100644 --- a/test_regress/t/t_interface_modportlist.v +++ b/test_regress/t/t_interface_modportlist.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Adrian Wise +// without warranty, 2016 by Adrian Wise. +// SPDX-License-Identifier: CC0-1.0 //bug1246 diff --git a/test_regress/t/t_interface_mp_func.pl b/test_regress/t/t_interface_mp_func.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_interface_mp_func.pl +++ b/test_regress/t/t_interface_mp_func.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_mp_func.v b/test_regress/t/t_interface_mp_func.v index c52ce6769..5148b46a1 100644 --- a/test_regress/t/t_interface_mp_func.v +++ b/test_regress/t/t_interface_mp_func.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface pads_if(); modport mp_dig( diff --git a/test_regress/t/t_interface_mp_func_noinl.pl b/test_regress/t/t_interface_mp_func_noinl.pl index 43973a543..d2a19c1bb 100755 --- a/test_regress/t/t_interface_mp_func_noinl.pl +++ b/test_regress/t/t_interface_mp_func_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_nest.pl b/test_regress/t/t_interface_nest.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_interface_nest.pl +++ b/test_regress/t/t_interface_nest.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_nest.v b/test_regress/t/t_interface_nest.v index e0eeddf6a..f4eb0d643 100644 --- a/test_regress/t/t_interface_nest.v +++ b/test_regress/t/t_interface_nest.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by ____YOUR_NAME_HERE____. +// without warranty, 2017. +// SPDX-License-Identifier: CC0-1.0 interface if1; integer var1; diff --git a/test_regress/t/t_interface_nest_noinl.pl b/test_regress/t/t_interface_nest_noinl.pl index e1ba7a75d..f2544ca38 100755 --- a/test_regress/t/t_interface_nest_noinl.pl +++ b/test_regress/t/t_interface_nest_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_noinl.pl b/test_regress/t/t_interface_noinl.pl index 4b521e5a0..3c5d31d75 100755 --- a/test_regress/t/t_interface_noinl.pl +++ b/test_regress/t/t_interface_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_param1.pl b/test_regress/t/t_interface_param1.pl index 0bafa73ba..a4d74c0ba 100755 --- a/test_regress/t/t_interface_param1.pl +++ b/test_regress/t/t_interface_param1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_interface_param1.v b/test_regress/t/t_interface_param1.v index 61d018a61..bed33ea78 100644 --- a/test_regress/t/t_interface_param1.v +++ b/test_regress/t/t_interface_param1.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 //bug692 diff --git a/test_regress/t/t_interface_param2.pl b/test_regress/t/t_interface_param2.pl index 2f4001b09..d275261b6 100755 --- a/test_regress/t/t_interface_param2.pl +++ b/test_regress/t/t_interface_param2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug1104"); diff --git a/test_regress/t/t_interface_param2.v b/test_regress/t/t_interface_param2.v index 0b2afd5a0..7aaaee46e 100644 --- a/test_regress/t/t_interface_param2.v +++ b/test_regress/t/t_interface_param2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Adrian Wise +// without warranty, 2016 by Adrian Wise. +// SPDX-License-Identifier: CC0-1.0 //bug1104 diff --git a/test_regress/t/t_interface_param_acc_bits.out b/test_regress/t/t_interface_param_acc_bits.out index a12c72cb8..69419ae25 100644 --- a/test_regress/t/t_interface_param_acc_bits.out +++ b/test_regress/t/t_interface_param_acc_bits.out @@ -1,5 +1,5 @@ -%Error: t/t_interface_param_acc_bits.v:14: Parameter-resolved constants must not use dotted references: 'dummy' - : ... In instance t - simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); - ^~~~~ +%Error: t/t_interface_param_acc_bits.v:15:42: Parameter-resolved constants must not use dotted references: 'dummy' + : ... In instance t + 15 | simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_param_acc_bits.pl b/test_regress/t/t_interface_param_acc_bits.pl index 0ce3002b1..4c3cbf1ae 100755 --- a/test_regress/t/t_interface_param_acc_bits.pl +++ b/test_regress/t/t_interface_param_acc_bits.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_param_acc_bits.v b/test_regress/t/t_interface_param_acc_bits.v index 6859b90be..b89767876 100644 --- a/test_regress/t/t_interface_param_acc_bits.v +++ b/test_regress/t/t_interface_param_acc_bits.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 // bug1593 diff --git a/test_regress/t/t_interface_param_another_bad.out b/test_regress/t/t_interface_param_another_bad.out index e7ba35f89..c77f8eae3 100644 --- a/test_regress/t/t_interface_param_another_bad.out +++ b/test_regress/t/t_interface_param_another_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_interface_param_another_bad.v:8: Parameter-resolved constants must not use dotted references: 'dummy' - : ... In instance t - simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); - ^~~~~ +%Error: t/t_interface_param_another_bad.v:9:42: Parameter-resolved constants must not use dotted references: 'dummy' + : ... In instance t + 9 | simple_bus #(.PARAMETER($bits(sb_intf.dummy))) simple(); + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_param_another_bad.pl b/test_regress/t/t_interface_param_another_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_interface_param_another_bad.pl +++ b/test_regress/t/t_interface_param_another_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_param_another_bad.v b/test_regress/t/t_interface_param_another_bad.v index 13a6fded5..b5278fbc2 100644 --- a/test_regress/t/t_interface_param_another_bad.v +++ b/test_regress/t/t_interface_param_another_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 module t (); simple_bus sb_intf(); diff --git a/test_regress/t/t_interface_param_loop_bad.pl b/test_regress/t/t_interface_param_loop_bad.pl index 2cd34c191..7b55cbb24 100755 --- a/test_regress/t/t_interface_param_loop_bad.pl +++ b/test_regress/t/t_interface_param_loop_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, bug1626"); diff --git a/test_regress/t/t_interface_param_loop_bad.v b/test_regress/t/t_interface_param_loop_bad.v index 5a9fe1691..8a8113aed 100644 --- a/test_regress/t/t_interface_param_loop_bad.v +++ b/test_regress/t/t_interface_param_loop_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 module t (); simple_bus #(.WIDTH(simple.get_width())) sb_intf(); diff --git a/test_regress/t/t_interface_parameter_access.pl b/test_regress/t/t_interface_parameter_access.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_interface_parameter_access.pl +++ b/test_regress/t/t_interface_parameter_access.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_parameter_access.v b/test_regress/t/t_interface_parameter_access.v index f21948da8..3912fd2ff 100644 --- a/test_regress/t/t_interface_parameter_access.v +++ b/test_regress/t/t_interface_parameter_access.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader +// SPDX-License-Identifier: CC0-1.0 interface test_if #(parameter integer FOO = 1); diff --git a/test_regress/t/t_interface_parent_scope_bad.pl b/test_regress/t/t_interface_parent_scope_bad.pl index 89a1fffda..c68596a09 100755 --- a/test_regress/t/t_interface_parent_scope_bad.pl +++ b/test_regress/t/t_interface_parent_scope_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, bug1623"); diff --git a/test_regress/t/t_interface_parent_scope_bad.v b/test_regress/t/t_interface_parent_scope_bad.v index a8070445a..b8b17f7a8 100644 --- a/test_regress/t/t_interface_parent_scope_bad.v +++ b/test_regress/t/t_interface_parent_scope_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi +// without warranty, 2019 by Driss Hafdi. +// SPDX-License-Identifier: CC0-1.0 interface Foo(); logic quux; diff --git a/test_regress/t/t_interface_ref_trace.pl b/test_regress/t/t_interface_ref_trace.pl index 5dc97b54d..0614cda35 100755 --- a/test_regress/t/t_interface_ref_trace.pl +++ b/test_regress/t/t_interface_ref_trace.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_ref_trace.v b/test_regress/t/t_interface_ref_trace.v index ee59c80fb..4de2cd2c2 100644 --- a/test_regress/t/t_interface_ref_trace.v +++ b/test_regress/t/t_interface_ref_trace.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 // Test for trace file interface aliasing diff --git a/test_regress/t/t_interface_ref_trace_fst.pl b/test_regress/t/t_interface_ref_trace_fst.pl index b94b6c15c..c4aed592a 100755 --- a/test_regress/t/t_interface_ref_trace_fst.pl +++ b/test_regress/t/t_interface_ref_trace_fst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_ref_trace_inla.pl b/test_regress/t/t_interface_ref_trace_inla.pl index 6924687b4..a07280688 100755 --- a/test_regress/t/t_interface_ref_trace_inla.pl +++ b/test_regress/t/t_interface_ref_trace_inla.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_ref_trace_inlab.pl b/test_regress/t/t_interface_ref_trace_inlab.pl index 0b3bdc14d..ad9f1c195 100755 --- a/test_regress/t/t_interface_ref_trace_inlab.pl +++ b/test_regress/t/t_interface_ref_trace_inlab.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_ref_trace_inlb.pl b/test_regress/t/t_interface_ref_trace_inlb.pl index a8567211e..570742b4b 100755 --- a/test_regress/t/t_interface_ref_trace_inlb.pl +++ b/test_regress/t/t_interface_ref_trace_inlb.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_size_bad.out b/test_regress/t/t_interface_size_bad.out index 9a10d57ac..b5ccb6def 100644 --- a/test_regress/t/t_interface_size_bad.out +++ b/test_regress/t/t_interface_size_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_interface_size_bad.v:15: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 4. - : ... In instance t - baz baz4_inst (.foo(foo4)); - ^~~ -%Error: t/t_interface_size_bad.v:16: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 6. - : ... In instance t - baz baz6_inst (.foo(foo6)); - ^~~ +%Error: t/t_interface_size_bad.v:16:20: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 4. + : ... In instance t + 16 | baz baz4_inst (.foo(foo4)); + | ^~~ +%Error: t/t_interface_size_bad.v:17:20: Illegal port connection 'foo', mismatch between port which is an interface array of size 5, and expression which is an interface array of size 6. + : ... In instance t + 17 | baz baz6_inst (.foo(foo6)); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_size_bad.pl b/test_regress/t/t_interface_size_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_interface_size_bad.pl +++ b/test_regress/t/t_interface_size_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_size_bad.v b/test_regress/t/t_interface_size_bad.v index 4066254a8..bdccf5c84 100644 --- a/test_regress/t/t_interface_size_bad.v +++ b/test_regress/t/t_interface_size_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic a; diff --git a/test_regress/t/t_interface_star.pl b/test_regress/t/t_interface_star.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_star.pl +++ b/test_regress/t/t_interface_star.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_star.v b/test_regress/t/t_interface_star.v index e3e4b3b14..f8e3c9c25 100644 --- a/test_regress/t/t_interface_star.v +++ b/test_regress/t/t_interface_star.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_interface_top_bad.out b/test_regress/t/t_interface_top_bad.out index adaecff1c..118e343f0 100644 --- a/test_regress/t/t_interface_top_bad.out +++ b/test_regress/t/t_interface_top_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_interface_top_bad.v:16: Unsupported: Interfaced port on top level module - ifc.counter_mp c_data - ^~~~~~ -%Error: t/t_interface_top_bad.v:16: Parent cell's interface is not found: 'ifc' - ifc.counter_mp c_data - ^~~ +%Error: t/t_interface_top_bad.v:17:19: Unsupported: Interfaced port on top level module + 17 | ifc.counter_mp c_data + | ^~~~~~ +%Error: t/t_interface_top_bad.v:17:4: Parent cell's interface is not found: 'ifc' + 17 | ifc.counter_mp c_data + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_top_bad.pl b/test_regress/t/t_interface_top_bad.pl index 9832155f2..ddbffc478 100755 --- a/test_regress/t/t_interface_top_bad.pl +++ b/test_regress/t/t_interface_top_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_interface_top_bad.v b/test_regress/t/t_interface_top_bad.v index 2334789b0..0de35cbc5 100644 --- a/test_regress/t/t_interface_top_bad.v +++ b/test_regress/t/t_interface_top_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface ifc; logic [3:0] value; diff --git a/test_regress/t/t_interface_twod.pl b/test_regress/t/t_interface_twod.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_interface_twod.pl +++ b/test_regress/t/t_interface_twod.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_twod.v b/test_regress/t/t_interface_twod.v index 4fe47a6c0..76b8a9a77 100644 --- a/test_regress/t/t_interface_twod.v +++ b/test_regress/t/t_interface_twod.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; diff --git a/test_regress/t/t_interface_twod_noinl.pl b/test_regress/t/t_interface_twod_noinl.pl index af93c9ff2..d1fcc0f24 100755 --- a/test_regress/t/t_interface_twod_noinl.pl +++ b/test_regress/t/t_interface_twod_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_typo_bad.out b/test_regress/t/t_interface_typo_bad.out index 2785a1329..c509e157d 100644 --- a/test_regress/t/t_interface_typo_bad.out +++ b/test_regress/t/t_interface_typo_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_interface_typo_bad.v:13: Parent cell's interface is not found: 'foo_intf' - foo_intf foo - ^~~~~~~~ -%Error: t/t_interface_typo_bad.v:21: Cannot find file containing interface: 'fo_intf' - fo_intf the_foo; - ^~~~~~~ -%Error: t/t_interface_typo_bad.v:26: Found definition of 'the_foo' as a CELL but expected a variable - .foo (the_foo) - ^~~~~~~ +%Error: t/t_interface_typo_bad.v:14:4: Parent cell's interface is not found: 'foo_intf' + 14 | foo_intf foo + | ^~~~~~~~ +%Error: t/t_interface_typo_bad.v:22:4: Cannot find file containing interface: 'fo_intf' + 22 | fo_intf the_foo; + | ^~~~~~~ +%Error: t/t_interface_typo_bad.v:27:15: Found definition of 'the_foo' as a CELL but expected a variable + 27 | .foo (the_foo) + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_typo_bad.pl b/test_regress/t/t_interface_typo_bad.pl index 1cc3d45e3..a6e92b237 100755 --- a/test_regress/t/t_interface_typo_bad.pl +++ b/test_regress/t/t_interface_typo_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2005 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2005 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_interface_typo_bad.v b/test_regress/t/t_interface_typo_bad.v index d91f3393b..f684ba85c 100644 --- a/test_regress/t/t_interface_typo_bad.v +++ b/test_regress/t/t_interface_typo_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 //bug1097 diff --git a/test_regress/t/t_interface_wrong_bad.out b/test_regress/t/t_interface_wrong_bad.out index ae327c4d9..d4694955a 100644 --- a/test_regress/t/t_interface_wrong_bad.out +++ b/test_regress/t/t_interface_wrong_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_interface_wrong_bad.v:31: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface - : ... In instance t - .foo_port (bar) - ^~~~~~~~ +%Error: t/t_interface_wrong_bad.v:32:8: Port 'foo_port' expects 'foo_intf' interface but pin connects 'bar_intf' interface + : ... In instance t + 32 | .foo_port (bar) + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_interface_wrong_bad.pl b/test_regress/t/t_interface_wrong_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_interface_wrong_bad.pl +++ b/test_regress/t/t_interface_wrong_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_interface_wrong_bad.v b/test_regress/t/t_interface_wrong_bad.v index 233b9a656..374844072 100644 --- a/test_regress/t/t_interface_wrong_bad.v +++ b/test_regress/t/t_interface_wrong_bad.v @@ -3,6 +3,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 interface foo_intf; logic [7:0] a; diff --git a/test_regress/t/t_langext_1.pl b/test_regress/t/t_langext_1.pl index 6fb45726f..5960a700c 100755 --- a/test_regress/t/t_langext_1.pl +++ b/test_regress/t/t_langext_1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_langext_1.v b/test_regress/t/t_langext_1.v index bd8728f91..dfbef20de 100644 --- a/test_regress/t/t_langext_1.v +++ b/test_regress/t/t_langext_1.v @@ -10,6 +10,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_langext_1_bad.pl b/test_regress/t/t_langext_1_bad.pl index 7cf98edc1..8eafb0e35 100755 --- a/test_regress/t/t_langext_1_bad.pl +++ b/test_regress/t/t_langext_1_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_langext_2.pl b/test_regress/t/t_langext_2.pl index 688ab8c39..3164380b9 100755 --- a/test_regress/t/t_langext_2.pl +++ b/test_regress/t/t_langext_2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_langext_2.v b/test_regress/t/t_langext_2.v index 96c00d892..feac45c88 100644 --- a/test_regress/t/t_langext_2.v +++ b/test_regress/t/t_langext_2.v @@ -10,6 +10,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_langext_2_bad.pl b/test_regress/t/t_langext_2_bad.pl index d60988f7b..05fc58fcd 100755 --- a/test_regress/t/t_langext_2_bad.pl +++ b/test_regress/t/t_langext_2_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_langext_3.pl b/test_regress/t/t_langext_3.pl index 7dee7e04c..8e7c2ae5e 100755 --- a/test_regress/t/t_langext_3.pl +++ b/test_regress/t/t_langext_3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_langext_3.v b/test_regress/t/t_langext_3.v index eecc02615..8efa0085d 100644 --- a/test_regress/t/t_langext_3.v +++ b/test_regress/t/t_langext_3.v @@ -9,6 +9,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_langext_3_bad.pl b/test_regress/t/t_langext_3_bad.pl index 20abe2276..68d1172d1 100755 --- a/test_regress/t/t_langext_3_bad.pl +++ b/test_regress/t/t_langext_3_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_langext_4.pl b/test_regress/t/t_langext_4.pl index c21cc0c2a..244788f32 100755 --- a/test_regress/t/t_langext_4.pl +++ b/test_regress/t/t_langext_4.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_langext_4_bad.pl b/test_regress/t/t_langext_4_bad.pl index 4552902ae..b935c2cce 100755 --- a/test_regress/t/t_langext_4_bad.pl +++ b/test_regress/t/t_langext_4_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_langext_order.pl b/test_regress/t/t_langext_order.pl index 7dee7e04c..8e7c2ae5e 100755 --- a/test_regress/t/t_langext_order.pl +++ b/test_regress/t/t_langext_order.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_langext_order.v b/test_regress/t/t_langext_order.v index aea0dc00f..a40880794 100644 --- a/test_regress/t/t_langext_order.v +++ b/test_regress/t/t_langext_order.v @@ -2,8 +2,9 @@ // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD diff --git a/test_regress/t/t_langext_order_sub.v b/test_regress/t/t_langext_order_sub.v index 79cdaaa2a..3c6d48b5b 100644 --- a/test_regress/t/t_langext_order_sub.v +++ b/test_regress/t/t_langext_order_sub.v @@ -2,8 +2,9 @@ // // A test of the +verilog2001ext+ and +verilog2005ext+ flags. // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD diff --git a/test_regress/t/t_leak.cpp b/test_regress/t/t_leak.cpp index 573286941..c42d459fc 100644 --- a/test_regress/t/t_leak.cpp +++ b/test_regress/t/t_leak.cpp @@ -6,6 +6,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #include #include diff --git a/test_regress/t/t_leak.pl b/test_regress/t/t_leak.pl index af1d76b34..ba352d9dd 100755 --- a/test_regress/t/t_leak.pl +++ b/test_regress/t/t_leak.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 if ($Self->{vltmt} && exists $ENV{TRAVIS_DIST} && $ENV{TRAVIS_DIST} eq "trusty") diff --git a/test_regress/t/t_leak.v b/test_regress/t/t_leak.v index 667d998c8..b85a8099d 100644 --- a/test_regress/t/t_leak.v +++ b/test_regress/t/t_leak.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); diff --git a/test_regress/t/t_lint_always_comb_bad.out b/test_regress/t/t_lint_always_comb_bad.out index cf3700947..7f198d9e9 100644 --- a/test_regress/t/t_lint_always_comb_bad.out +++ b/test_regress/t/t_lint_always_comb_bad.out @@ -1,18 +1,18 @@ -%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1' - : ... In instance t - temp1 = 'h0; - ^~~~~ -%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:30: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1' - : ... In instance t - temp1 = (temp1_d1r - 'h1); - ^~~~~ -%Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:31: Always_comb variable driven after use: 'mid' - : ... In instance t - mid = (temp1_d1r == 'h0); - ^~~ +%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:29:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1' + : ... In instance t + 29 | temp1 = 'h0; + | ^~~~~ +%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1' + : ... In instance t + 31 | temp1 = (temp1_d1r - 'h1); + | ^~~~~ +%Warning-ALWCOMBORDER: t/t_lint_always_comb_bad.v:32:7: Always_comb variable driven after use: 'mid' + : ... In instance t + 32 | mid = (temp1_d1r == 'h0); + | ^~~ ... Use "/* verilator lint_off ALWCOMBORDER */" and lint_on around source to disable this message. -%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:45: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1_d1r' - : ... In instance t - temp1_d1r <= temp1; - ^~~~~~~~~ +%Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:46:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1_d1r' + : ... In instance t + 46 | temp1_d1r <= temp1; + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_always_comb_bad.pl b/test_regress/t/t_lint_always_comb_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_lint_always_comb_bad.pl +++ b/test_regress/t/t_lint_always_comb_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_always_comb_bad.v b/test_regress/t/t_lint_always_comb_bad.v index 789eaef96..1cb2cf2d1 100644 --- a/test_regress/t/t_lint_always_comb_bad.v +++ b/test_regress/t/t_lint_always_comb_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_lint_always_comb_iface.pl b/test_regress/t/t_lint_always_comb_iface.pl index 984b510bd..f7cc66737 100755 --- a/test_regress/t/t_lint_always_comb_iface.pl +++ b/test_regress/t/t_lint_always_comb_iface.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_always_comb_iface.v b/test_regress/t/t_lint_always_comb_iface.v index 0017a5e96..a51bc354f 100644 --- a/test_regress/t/t_lint_always_comb_iface.v +++ b/test_regress/t/t_lint_always_comb_iface.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Josh Redford. +// SPDX-License-Identifier: CC0-1.0 interface my_if; diff --git a/test_regress/t/t_lint_blksync_bad.out b/test_regress/t/t_lint_blksync_bad.out index 2ddeeabfe..3a5104638 100644 --- a/test_regress/t/t_lint_blksync_bad.out +++ b/test_regress/t/t_lint_blksync_bad.out @@ -1,12 +1,12 @@ -%Warning-BLKSEQ: t/t_lint_blksync_bad.v:23: Blocking assignments (=) in sequential (flop or latch) block - : ... Suggest delayed assignments (<=) - sync_blk = 1'b1; - ^ +%Warning-BLKSEQ: t/t_lint_blksync_bad.v:24:16: Blocking assignments (=) in sequential (flop or latch) block + : ... Suggest delayed assignments (<=) + 24 | sync_blk = 1'b1; + | ^ ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. -%Warning-COMBDLY: t/t_lint_blksync_bad.v:30: Delayed assignments (<=) in non-clocked (non flop or latch) block - : ... Suggest blocking assignments (=) - combo_nblk <= 1'b1; - ^~ +%Warning-COMBDLY: t/t_lint_blksync_bad.v:31:18: Delayed assignments (<=) in non-clocked (non flop or latch) block + : ... Suggest blocking assignments (=) + 31 | combo_nblk <= 1'b1; + | ^~ *** See the manual before disabling this, else you may end up with different sim results. %Error: Exiting due to diff --git a/test_regress/t/t_lint_blksync_bad.pl b/test_regress/t/t_lint_blksync_bad.pl index df455cd4c..bf192ff4c 100755 --- a/test_regress/t/t_lint_blksync_bad.pl +++ b/test_regress/t/t_lint_blksync_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_blksync_bad.v b/test_regress/t/t_lint_blksync_bad.v index ff0f9334e..f7bc51bf7 100644 --- a/test_regress/t/t_lint_blksync_bad.v +++ b/test_regress/t/t_lint_blksync_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_lint_blksync_loop.pl b/test_regress/t/t_lint_blksync_loop.pl index b89e43ba9..58912617c 100755 --- a/test_regress/t/t_lint_blksync_loop.pl +++ b/test_regress/t/t_lint_blksync_loop.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_blksync_loop.v b/test_regress/t/t_lint_blksync_loop.v index 2bf1ef4c7..dc707e7f6 100644 --- a/test_regress/t/t_lint_blksync_loop.v +++ b/test_regress/t/t_lint_blksync_loop.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_lint_block_redecl_bad.pl b/test_regress/t/t_lint_block_redecl_bad.pl index cf5892768..70003325c 100755 --- a/test_regress/t/t_lint_block_redecl_bad.pl +++ b/test_regress/t/t_lint_block_redecl_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug485, false begin due to WHILE conversion blocks duplicate name detection"); diff --git a/test_regress/t/t_lint_block_redecl_bad.v b/test_regress/t/t_lint_block_redecl_bad.v index 1bc434e24..0536ef0c3 100644 --- a/test_regress/t/t_lint_block_redecl_bad.v +++ b/test_regress/t/t_lint_block_redecl_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug485, but see t_gen_forif.v for an OK example. diff --git a/test_regress/t/t_lint_bsspace_bad.out b/test_regress/t/t_lint_bsspace_bad.out index 2c79ad74b..e7d583699 100644 --- a/test_regress/t/t_lint_bsspace_bad.out +++ b/test_regress/t/t_lint_bsspace_bad.out @@ -1,8 +1,8 @@ -%Warning-BSSPACE: t/t_lint_bsspace_bad.v:9: Backslash followed by whitespace, perhaps the whitespace is accidental? -`define FOO blak \ - ^ +%Warning-BSSPACE: t/t_lint_bsspace_bad.v:10:21: Backslash followed by whitespace, perhaps the whitespace is accidental? + 10 | `define FOO blak \ + | ^ ... Use "/* verilator lint_off BSSPACE */" and lint_on around source to disable this message. -%Error: t/t_lint_bsspace_bad.v:10: syntax error, unexpected IDENTIFIER - blak - ^~~~ +%Error: t/t_lint_bsspace_bad.v:11:4: syntax error, unexpected IDENTIFIER + 11 | blak + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_bsspace_bad.pl b/test_regress/t/t_lint_bsspace_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_lint_bsspace_bad.pl +++ b/test_regress/t/t_lint_bsspace_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_bsspace_bad.v b/test_regress/t/t_lint_bsspace_bad.v index b37bdbfa7..5ff67f178 100644 --- a/test_regress/t/t_lint_bsspace_bad.v +++ b/test_regress/t/t_lint_bsspace_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Fake binary character here '', so is treated as binary and // don't get whitespace violation. diff --git a/test_regress/t/t_lint_colonplus_bad.out b/test_regress/t/t_lint_colonplus_bad.out index ff1ae2b56..745bf6ae6 100644 --- a/test_regress/t/t_lint_colonplus_bad.out +++ b/test_regress/t/t_lint_colonplus_bad.out @@ -1,5 +1,5 @@ -%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:12: Perhaps instead of ':+' the intent was '+:'? - output [2:1] z = r[2 :+ 1]; - ^~ +%Warning-COLONPLUS: t/t_lint_colonplus_bad.v:13:25: Perhaps instead of ':+' the intent was '+:'? + 13 | output [2:1] z = r[2 :+ 1]; + | ^~ ... Use "/* verilator lint_off COLONPLUS */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_colonplus_bad.pl b/test_regress/t/t_lint_colonplus_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_lint_colonplus_bad.pl +++ b/test_regress/t/t_lint_colonplus_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_colonplus_bad.v b/test_regress/t/t_lint_colonplus_bad.v index 9bea31d96..85dba1403 100644 --- a/test_regress/t/t_lint_colonplus_bad.v +++ b/test_regress/t/t_lint_colonplus_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_lint_comb_bad.out b/test_regress/t/t_lint_comb_bad.out index c1ef33d26..902480d1d 100644 --- a/test_regress/t/t_lint_comb_bad.out +++ b/test_regress/t/t_lint_comb_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_lint_comb_bad.v:13: syntax error, unexpected '@' - always_comb @(*) begin - ^ +%Error: t/t_lint_comb_bad.v:14:16: syntax error, unexpected '@' + 14 | always_comb @(*) begin + | ^ %Error: Cannot continue diff --git a/test_regress/t/t_lint_comb_bad.pl b/test_regress/t/t_lint_comb_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_lint_comb_bad.pl +++ b/test_regress/t/t_lint_comb_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_comb_bad.v b/test_regress/t/t_lint_comb_bad.v index 360fb330f..53abf5f14 100644 --- a/test_regress/t/t_lint_comb_bad.v +++ b/test_regress/t/t_lint_comb_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_lint_comb_use.pl b/test_regress/t/t_lint_comb_use.pl index 54d7bac02..4052d7162 100755 --- a/test_regress/t/t_lint_comb_use.pl +++ b/test_regress/t/t_lint_comb_use.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_comb_use.v b/test_regress/t/t_lint_comb_use.v index cd9a97824..36b4206f4 100644 --- a/test_regress/t/t_lint_comb_use.v +++ b/test_regress/t/t_lint_comb_use.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_lint_declfilename.pl b/test_regress/t/t_lint_declfilename.pl index ab4b334e4..e0297030b 100755 --- a/test_regress/t/t_lint_declfilename.pl +++ b/test_regress/t/t_lint_declfilename.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_declfilename.v b/test_regress/t/t_lint_declfilename.v index 862be675f..b3922ab7e 100644 --- a/test_regress/t/t_lint_declfilename.v +++ b/test_regress/t/t_lint_declfilename.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; t_lint_declfilename sub (); diff --git a/test_regress/t/t_lint_declfilename_bad.out b/test_regress/t/t_lint_declfilename_bad.out index 32edff12e..9f9a150d7 100644 --- a/test_regress/t/t_lint_declfilename_bad.out +++ b/test_regress/t/t_lint_declfilename_bad.out @@ -1,5 +1,5 @@ -%Warning-DECLFILENAME: t/t_lint_declfilename.v:6: Filename 't_lint_declfilename' does not match MODULE name: 't' -module t; - ^ +%Warning-DECLFILENAME: t/t_lint_declfilename.v:7:8: Filename 't_lint_declfilename' does not match MODULE name: 't' + 7 | module t; + | ^ ... Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_declfilename_bad.pl b/test_regress/t/t_lint_declfilename_bad.pl index debd1ad78..92de58405 100755 --- a/test_regress/t/t_lint_declfilename_bad.pl +++ b/test_regress/t/t_lint_declfilename_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_defparam.pl b/test_regress/t/t_lint_defparam.pl index ab4b334e4..e0297030b 100755 --- a/test_regress/t/t_lint_defparam.pl +++ b/test_regress/t/t_lint_defparam.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_defparam.v b/test_regress/t/t_lint_defparam.v index 079fb0bd2..05bd79f41 100644 --- a/test_regress/t/t_lint_defparam.v +++ b/test_regress/t/t_lint_defparam.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_defparam_bad.out b/test_regress/t/t_lint_defparam_bad.out index 3b5105e5e..f7093b05a 100644 --- a/test_regress/t/t_lint_defparam_bad.out +++ b/test_regress/t/t_lint_defparam_bad.out @@ -1,5 +1,5 @@ -%Warning-DEFPARAM: t/t_lint_defparam.v:9: Suggest replace defparam assignment with Verilog 2001 #(.P(...etc...)) - defparam sub.P = 2; - ^ +%Warning-DEFPARAM: t/t_lint_defparam.v:10:19: Suggest replace defparam assignment with Verilog 2001 #(.P(...etc...)) + 10 | defparam sub.P = 2; + | ^ ... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_defparam_bad.pl b/test_regress/t/t_lint_defparam_bad.pl index f5054ec11..ac8b05b6d 100755 --- a/test_regress/t/t_lint_defparam_bad.pl +++ b/test_regress/t/t_lint_defparam_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_ifdepth_bad.out b/test_regress/t/t_lint_ifdepth_bad.out index 80c7d5b67..494d7100b 100644 --- a/test_regress/t/t_lint_ifdepth_bad.out +++ b/test_regress/t/t_lint_ifdepth_bad.out @@ -1,6 +1,6 @@ -%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:21: Deep 'if' statement; suggest unique/priority to avoid slow logic - : ... In instance t - else if (value==11) begin end - ^~ +%Warning-IFDEPTH: t/t_lint_ifdepth_bad.v:22:12: Deep 'if' statement; suggest unique/priority to avoid slow logic + : ... In instance t + 22 | else if (value==11) begin end + | ^~ ... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_ifdepth_bad.pl b/test_regress/t/t_lint_ifdepth_bad.pl index 8b5c00f6c..8af5bfd40 100755 --- a/test_regress/t/t_lint_ifdepth_bad.pl +++ b/test_regress/t/t_lint_ifdepth_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_lint_ifdepth_bad.v b/test_regress/t/t_lint_ifdepth_bad.v index 5b5b880fa..84873848f 100644 --- a/test_regress/t/t_lint_ifdepth_bad.v +++ b/test_regress/t/t_lint_ifdepth_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_lint_implicit.pl b/test_regress/t/t_lint_implicit.pl index 4288859cb..9f98be06b 100755 --- a/test_regress/t/t_lint_implicit.pl +++ b/test_regress/t/t_lint_implicit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_lint_implicit.v b/test_regress/t/t_lint_implicit.v index 5d56d499c..58961b897 100644 --- a/test_regress/t/t_lint_implicit.v +++ b/test_regress/t/t_lint_implicit.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (a,z); input a; diff --git a/test_regress/t/t_lint_implicit_bad.out b/test_regress/t/t_lint_implicit_bad.out index ac6800b5f..111126806 100644 --- a/test_regress/t/t_lint_implicit_bad.out +++ b/test_regress/t/t_lint_implicit_bad.out @@ -1,16 +1,16 @@ -%Warning-IMPLICIT: t/t_lint_implicit.v:10: Signal definition not found, creating implicitly: 'b' - assign b = 1'b1; - ^ +%Warning-IMPLICIT: t/t_lint_implicit.v:11:11: Signal definition not found, creating implicitly: 'b' + 11 | assign b = 1'b1; + | ^ ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. -%Warning-IMPLICIT: t/t_lint_implicit.v:12: Signal definition not found, creating implicitly: 'nt0' - or OR0 (nt0, a, b); - ^~~ -%Warning-IMPLICIT: t/t_lint_implicit.v:15: Signal definition not found, creating implicitly: 'dummy1' - : ... Suggested alternative: 'dummy_ip' - assign {dummy1, dummy2} = dummy_ip; - ^~~~~~ -%Warning-IMPLICIT: t/t_lint_implicit.v:15: Signal definition not found, creating implicitly: 'dummy2' - : ... Suggested alternative: 'dummy1' - assign {dummy1, dummy2} = dummy_ip; - ^~~~~~ +%Warning-IMPLICIT: t/t_lint_implicit.v:13:14: Signal definition not found, creating implicitly: 'nt0' + 13 | or OR0 (nt0, a, b); + | ^~~ +%Warning-IMPLICIT: t/t_lint_implicit.v:16:12: Signal definition not found, creating implicitly: 'dummy1' + : ... Suggested alternative: 'dummy_ip' + 16 | assign {dummy1, dummy2} = dummy_ip; + | ^~~~~~ +%Warning-IMPLICIT: t/t_lint_implicit.v:16:20: Signal definition not found, creating implicitly: 'dummy2' + : ... Suggested alternative: 'dummy1' + 16 | assign {dummy1, dummy2} = dummy_ip; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_bad.pl b/test_regress/t/t_lint_implicit_bad.pl index d22e7230f..e0cf4c95a 100755 --- a/test_regress/t/t_lint_implicit_bad.pl +++ b/test_regress/t/t_lint_implicit_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_implicit_def_bad.out b/test_regress/t/t_lint_implicit_def_bad.out index b9b0185e0..c6248d083 100644 --- a/test_regress/t/t_lint_implicit_def_bad.out +++ b/test_regress/t/t_lint_implicit_def_bad.out @@ -1,8 +1,8 @@ -%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:12: Signal definition not found, creating implicitly: 'imp_warn' - assign imp_warn = 1'b1; - ^~~~~~~~ +%Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:13:11: Signal definition not found, creating implicitly: 'imp_warn' + 13 | assign imp_warn = 1'b1; + | ^~~~~~~~ ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. -%Error: t/t_lint_implicit_def_bad.v:17: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err' - assign imp_err = 1'b1; - ^~~~~~~ +%Error: t/t_lint_implicit_def_bad.v:18:11: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err' + 18 | assign imp_err = 1'b1; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_def_bad.pl b/test_regress/t/t_lint_implicit_def_bad.pl index 8a36606fe..c2452eff5 100755 --- a/test_regress/t/t_lint_implicit_def_bad.pl +++ b/test_regress/t/t_lint_implicit_def_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_lint_implicit_def_bad.v b/test_regress/t/t_lint_implicit_def_bad.v index 6dc14ca06..0cb1bcc55 100644 --- a/test_regress/t/t_lint_implicit_def_bad.v +++ b/test_regress/t/t_lint_implicit_def_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (a,z); input a; diff --git a/test_regress/t/t_lint_implicit_port.pl b/test_regress/t/t_lint_implicit_port.pl index 4288859cb..9f98be06b 100755 --- a/test_regress/t/t_lint_implicit_port.pl +++ b/test_regress/t/t_lint_implicit_port.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_lint_implicit_port.v b/test_regress/t/t_lint_implicit_port.v index 637e5c6c6..a55ddbc50 100644 --- a/test_regress/t/t_lint_implicit_port.v +++ b/test_regress/t/t_lint_implicit_port.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_lint_import_name_bad.out b/test_regress/t/t_lint_import_name_bad.out index c790c7bb0..36a7cf18e 100644 --- a/test_regress/t/t_lint_import_name_bad.out +++ b/test_regress/t/t_lint_import_name_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_lint_import_name_bad.v:10: Import object not found: 'defs::sigs' -import defs::sigs; - ^~ +%Error: t/t_lint_import_name_bad.v:11:12: Import object not found: 'defs::sigs' + 11 | import defs::sigs; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_import_name_bad.pl b/test_regress/t/t_lint_import_name_bad.pl index 91df2c0f5..6a24a9424 100755 --- a/test_regress/t/t_lint_import_name_bad.pl +++ b/test_regress/t/t_lint_import_name_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_import_name_bad.v b/test_regress/t/t_lint_import_name_bad.v index 8ffea87e3..0c5d0c17a 100644 --- a/test_regress/t/t_lint_import_name_bad.v +++ b/test_regress/t/t_lint_import_name_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 package defs; int sig; diff --git a/test_regress/t/t_lint_importstar_bad.out b/test_regress/t/t_lint_importstar_bad.out index c75019b5b..7eaf12bc7 100644 --- a/test_regress/t/t_lint_importstar_bad.out +++ b/test_regress/t/t_lint_importstar_bad.out @@ -1,5 +1,5 @@ -%Warning-IMPORTSTAR: t/t_lint_importstar_bad.v:10: Import::* in $unit scope may pollute global namespace -import defs::*; - ^~ +%Warning-IMPORTSTAR: t/t_lint_importstar_bad.v:11:12: Import::* in $unit scope may pollute global namespace + 11 | import defs::*; + | ^~ ... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_importstar_bad.pl b/test_regress/t/t_lint_importstar_bad.pl index 91df2c0f5..6a24a9424 100755 --- a/test_regress/t/t_lint_importstar_bad.pl +++ b/test_regress/t/t_lint_importstar_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_importstar_bad.v b/test_regress/t/t_lint_importstar_bad.v index bea7837a3..d61e12f78 100644 --- a/test_regress/t/t_lint_importstar_bad.v +++ b/test_regress/t/t_lint_importstar_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 package defs; int sig; diff --git a/test_regress/t/t_lint_in_inc_bad.out b/test_regress/t/t_lint_in_inc_bad.out index ce1771397..b643c6ad8 100644 --- a/test_regress/t/t_lint_in_inc_bad.out +++ b/test_regress/t/t_lint_in_inc_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_lint_in_inc_bad_2.vh:8: syntax error, unexpected if, expecting '(' - if if if; - ^~ - t/t_lint_in_inc_bad_1.vh:7: ... note: In file included from t_lint_in_inc_bad_1.vh - t/t_lint_in_inc_bad.v:7: ... note: In file included from t_lint_in_inc_bad.v +%Error: t/t_lint_in_inc_bad_2.vh:9:7: syntax error, unexpected if, expecting '(' + 9 | if if if; + | ^~ + t/t_lint_in_inc_bad_1.vh:8:1: ... note: In file included from t_lint_in_inc_bad_1.vh + t/t_lint_in_inc_bad.v:8:1: ... note: In file included from t_lint_in_inc_bad.v %Error: Exiting due to diff --git a/test_regress/t/t_lint_in_inc_bad.pl b/test_regress/t/t_lint_in_inc_bad.pl index f7eae9397..e012834b1 100755 --- a/test_regress/t/t_lint_in_inc_bad.pl +++ b/test_regress/t/t_lint_in_inc_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_lint_in_inc_bad.v b/test_regress/t/t_lint_in_inc_bad.v index 54cab8972..c2fdd72b6 100644 --- a/test_regress/t/t_lint_in_inc_bad.v +++ b/test_regress/t/t_lint_in_inc_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "t_lint_in_inc_bad_1.vh" diff --git a/test_regress/t/t_lint_in_inc_bad_1.vh b/test_regress/t/t_lint_in_inc_bad_1.vh index 086d2890a..976417f23 100644 --- a/test_regress/t/t_lint_in_inc_bad_1.vh +++ b/test_regress/t/t_lint_in_inc_bad_1.vh @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "t_lint_in_inc_bad_2.vh" diff --git a/test_regress/t/t_lint_in_inc_bad_2.vh b/test_regress/t/t_lint_in_inc_bad_2.vh index 13e39c84e..2921bd853 100644 --- a/test_regress/t/t_lint_in_inc_bad_2.vh +++ b/test_regress/t/t_lint_in_inc_bad_2.vh @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module x; // Syntax error diff --git a/test_regress/t/t_lint_incabspath.pl b/test_regress/t/t_lint_incabspath.pl index ab4b334e4..e0297030b 100755 --- a/test_regress/t/t_lint_incabspath.pl +++ b/test_regress/t/t_lint_incabspath.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_incabspath.v b/test_regress/t/t_lint_incabspath.v index 47a56c2b3..2148dc776 100644 --- a/test_regress/t/t_lint_incabspath.v +++ b/test_regress/t/t_lint_incabspath.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "/dev/null" diff --git a/test_regress/t/t_lint_incabspath_bad.out b/test_regress/t/t_lint_incabspath_bad.out index b2af30de9..c90e6372b 100644 --- a/test_regress/t/t_lint_incabspath_bad.out +++ b/test_regress/t/t_lint_incabspath_bad.out @@ -1,5 +1,5 @@ -%Warning-INCABSPATH: t/t_lint_incabspath.v:6: Suggest `include with absolute path be made relative, and use +include: /dev/null -`include "/dev/null" - ^~~~~~~~~~~ +%Warning-INCABSPATH: t/t_lint_incabspath.v:7:10: Suggest `include with absolute path be made relative, and use +include: /dev/null + 7 | `include "/dev/null" + | ^~~~~~~~~~~ ... Use "/* verilator lint_off INCABSPATH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_incabspath_bad.pl b/test_regress/t/t_lint_incabspath_bad.pl index c1311d57e..f9d3031a7 100755 --- a/test_regress/t/t_lint_incabspath_bad.pl +++ b/test_regress/t/t_lint_incabspath_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_infinite.out b/test_regress/t/t_lint_infinite.out index 5172274a1..04de98f39 100644 --- a/test_regress/t/t_lint_infinite.out +++ b/test_regress/t/t_lint_infinite.out @@ -1,10 +1,10 @@ -%Warning-INFINITELOOP: t/t_lint_infinite.v:9: Infinite loop (condition always true) - : ... In instance t - forever begin end - ^~~~~~~ +%Warning-INFINITELOOP: t/t_lint_infinite.v:10:7: Infinite loop (condition always true) + : ... In instance t + 10 | forever begin end + | ^~~~~~~ ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. -%Warning-INFINITELOOP: t/t_lint_infinite.v:11: Infinite loop (condition always true) - : ... In instance t - for (reg [31:0] i=0; i>=0; i=i+1) begin end - ^~~ +%Warning-INFINITELOOP: t/t_lint_infinite.v:12:7: Infinite loop (condition always true) + : ... In instance t + 12 | for (reg [31:0] i=0; i>=0; i=i+1) begin end + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_infinite.pl b/test_regress/t/t_lint_infinite.pl index 9832155f2..ddbffc478 100755 --- a/test_regress/t/t_lint_infinite.pl +++ b/test_regress/t/t_lint_infinite.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_infinite.v b/test_regress/t/t_lint_infinite.v index 7afebb5c4..4bf795db2 100644 --- a/test_regress/t/t_lint_infinite.v +++ b/test_regress/t/t_lint_infinite.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_inherit.pl b/test_regress/t/t_lint_inherit.pl index 5c448de7c..d1bf185c9 100755 --- a/test_regress/t/t_lint_inherit.pl +++ b/test_regress/t/t_lint_inherit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_lint_inherit.v b/test_regress/t/t_lint_inherit.v index 1d30cf928..cfee91136 100644 --- a/test_regress/t/t_lint_inherit.v +++ b/test_regress/t/t_lint_inherit.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_lint_input_eq_bad.out b/test_regress/t/t_lint_input_eq_bad.out index c45d62534..c12a38f17 100644 --- a/test_regress/t/t_lint_input_eq_bad.out +++ b/test_regress/t/t_lint_input_eq_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_lint_input_eq_bad.v:9: Unsupported: Default value on module input: 'i2' - input wire i2 = i - ^~ +%Error: t/t_lint_input_eq_bad.v:10:15: Unsupported: Default value on module input: 'i2' + 10 | input wire i2 = i + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_input_eq_bad.pl b/test_regress/t/t_lint_input_eq_bad.pl index 72de436c6..30a536839 100755 --- a/test_regress/t/t_lint_input_eq_bad.pl +++ b/test_regress/t/t_lint_input_eq_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_input_eq_bad.v b/test_regress/t/t_lint_input_eq_bad.v index 809247f12..ef7c3c875 100644 --- a/test_regress/t/t_lint_input_eq_bad.v +++ b/test_regress/t/t_lint_input_eq_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_latch_bad.out b/test_regress/t/t_lint_latch_bad.out index 9334c03d7..751a7516f 100644 --- a/test_regress/t/t_lint_latch_bad.out +++ b/test_regress/t/t_lint_latch_bad.out @@ -1,7 +1,7 @@ -%Warning-COMBDLY: t/t_lint_latch_bad.v:24: Delayed assignments (<=) in non-clocked (non flop or latch) block - : ... Suggest blocking assignments (=) - bc <= a; - ^~ +%Warning-COMBDLY: t/t_lint_latch_bad.v:25:10: Delayed assignments (<=) in non-clocked (non flop or latch) block + : ... Suggest blocking assignments (=) + 25 | bc <= a; + | ^~ ... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message. *** See the manual before disabling this, else you may end up with different sim results. diff --git a/test_regress/t/t_lint_latch_bad.pl b/test_regress/t/t_lint_latch_bad.pl index b0c394b27..2485f55da 100755 --- a/test_regress/t/t_lint_latch_bad.pl +++ b/test_regress/t/t_lint_latch_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_latch_bad.v b/test_regress/t/t_lint_latch_bad.v index 8446ad562..74d7224a4 100644 --- a/test_regress/t/t_lint_latch_bad.v +++ b/test_regress/t/t_lint_latch_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_lint_literal_bad.out b/test_regress/t/t_lint_literal_bad.out index 9ed1d4c3e..88f210ea5 100644 --- a/test_regress/t/t_lint_literal_bad.out +++ b/test_regress/t/t_lint_literal_bad.out @@ -1,5 +1,5 @@ -%Warning-WIDTH: t/t_lint_literal_bad.v:9: Value too large for 8 bit number: 256 - localparam the_localparam = 8'd256; - ^~~~~~ +%Warning-WIDTH: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256 + 10 | localparam the_localparam = 8'd256; + | ^~~~~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_literal_bad.pl b/test_regress/t/t_lint_literal_bad.pl index 93c6cc548..5d4fb2e96 100755 --- a/test_regress/t/t_lint_literal_bad.pl +++ b/test_regress/t/t_lint_literal_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2017 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2017 by Todd Strader. This program is free software; you +# can predistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_lint_literal_bad.v b/test_regress/t/t_lint_literal_bad.v index 521bd10ef..456feed9b 100644 --- a/test_regress/t/t_lint_literal_bad.v +++ b/test_regress/t/t_lint_literal_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module t ( ); diff --git a/test_regress/t/t_lint_mod_paren_bad.out b/test_regress/t/t_lint_mod_paren_bad.out index f7783f03d..682bb8951 100644 --- a/test_regress/t/t_lint_mod_paren_bad.out +++ b/test_regress/t/t_lint_mod_paren_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_lint_mod_paren_bad.v:13: syntax error, unexpected '(', expecting ';' - output bar - ^~~~~~ +%Error: t/t_lint_mod_paren_bad.v:14:7: syntax error, unexpected '(', expecting ';' + 14 | output bar + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_mod_paren_bad.pl b/test_regress/t/t_lint_mod_paren_bad.pl index ef5190d79..dd76f697c 100755 --- a/test_regress/t/t_lint_mod_paren_bad.pl +++ b/test_regress/t/t_lint_mod_paren_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_mod_paren_bad.v b/test_regress/t/t_lint_mod_paren_bad.v index 353dd2a64..6f01fb8ab 100644 --- a/test_regress/t/t_lint_mod_paren_bad.v +++ b/test_regress/t/t_lint_mod_paren_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Should have been: //module t #( diff --git a/test_regress/t/t_lint_modport_dir_bad.out b/test_regress/t/t_lint_modport_dir_bad.out index 7aaa7a6e0..976bcd3b1 100644 --- a/test_regress/t/t_lint_modport_dir_bad.out +++ b/test_regress/t/t_lint_modport_dir_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_lint_modport_dir_bad.v:25: Attempt to drive input-only modport: 'signal' - : ... In instance t.sub - assign dummy_in.signal = signal_i; - ^~~~~~ +%Error: t/t_lint_modport_dir_bad.v:26:20: Attempt to drive input-only modport: 'signal' + : ... In instance t.sub + 26 | assign dummy_in.signal = signal_i; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_modport_dir_bad.pl b/test_regress/t/t_lint_modport_dir_bad.pl index 267f58ed7..2a6951323 100755 --- a/test_regress/t/t_lint_modport_dir_bad.pl +++ b/test_regress/t/t_lint_modport_dir_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_modport_dir_bad.v b/test_regress/t/t_lint_modport_dir_bad.v index 57ba33ffa..708b920f9 100644 --- a/test_regress/t/t_lint_modport_dir_bad.v +++ b/test_regress/t/t_lint_modport_dir_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic signal; diff --git a/test_regress/t/t_lint_multidriven_bad.out b/test_regress/t/t_lint_multidriven_bad.out index 4503dc79c..5839d7898 100644 --- a/test_regress/t/t_lint_multidriven_bad.out +++ b/test_regress/t/t_lint_multidriven_bad.out @@ -1,16 +1,16 @@ -%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:20: Signal has multiple driving blocks with different clocking: 't.mem' - t/t_lint_multidriven_bad.v:26: ... Location of first driving block - mem[a0] <= d1; - ^~~ - t/t_lint_multidriven_bad.v:23: ... Location of other driving block - mem[a0] <= d0; - ^~~ +%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:21:22: Signal has multiple driving blocks with different clocking: 't.mem' + t/t_lint_multidriven_bad.v:27:7: ... Location of first driving block + 27 | mem[a0] <= d1; + | ^~~ + t/t_lint_multidriven_bad.v:24:7: ... Location of other driving block + 24 | mem[a0] <= d0; + | ^~~ ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. -%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:18: Signal has multiple driving blocks with different clocking: 'out2' - t/t_lint_multidriven_bad.v:34: ... Location of first driving block - out2[15:8] <= d0; - ^~~~ - t/t_lint_multidriven_bad.v:31: ... Location of other driving block - out2[7:0] <= d0; - ^~~~ +%Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:22: Signal has multiple driving blocks with different clocking: 'out2' + t/t_lint_multidriven_bad.v:35:7: ... Location of first driving block + 35 | out2[15:8] <= d0; + | ^~~~ + t/t_lint_multidriven_bad.v:32:7: ... Location of other driving block + 32 | out2[7:0] <= d0; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_multidriven_bad.pl b/test_regress/t/t_lint_multidriven_bad.pl index 573f98f12..8e4fecbdb 100755 --- a/test_regress/t/t_lint_multidriven_bad.pl +++ b/test_regress/t/t_lint_multidriven_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_multidriven_bad.v b/test_regress/t/t_lint_multidriven_bad.v index 0eaa068db..19d4e86e1 100644 --- a/test_regress/t/t_lint_multidriven_bad.v +++ b/test_regress/t/t_lint_multidriven_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_lint_numwidth.pl b/test_regress/t/t_lint_numwidth.pl index adf0894d6..1f038cd03 100755 --- a/test_regress/t/t_lint_numwidth.pl +++ b/test_regress/t/t_lint_numwidth.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_numwidth.v b/test_regress/t/t_lint_numwidth.v index ff0d77aa3..52ec94895 100644 --- a/test_regress/t/t_lint_numwidth.v +++ b/test_regress/t/t_lint_numwidth.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 logic [65535:0] a = 65536'd1; logic [65536:0] b = 65537'd1; diff --git a/test_regress/t/t_lint_once_bad.out b/test_regress/t/t_lint_once_bad.out index 84e6e164d..fd18cfd0d 100644 --- a/test_regress/t/t_lint_once_bad.out +++ b/test_regress/t/t_lint_once_bad.out @@ -1,10 +1,10 @@ -%Warning-UNUSED: t/t_lint_once_bad.v:18: Signal is not driven, nor used: 'unus1' - : ... In instance t.sub3 - reg [A:0] unus1; reg [A:0] unus2; - ^~~~~ +%Warning-UNUSED: t/t_lint_once_bad.v:19:14: Signal is not driven, nor used: 'unus1' + : ... In instance t.sub3 + 19 | reg [A:0] unus1; reg [A:0] unus2; + | ^~~~~ ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. -%Warning-UNUSED: t/t_lint_once_bad.v:18: Signal is not driven, nor used: 'unus2' - : ... In instance t.sub3 - reg [A:0] unus1; reg [A:0] unus2; - ^~~~~ +%Warning-UNUSED: t/t_lint_once_bad.v:19:34: Signal is not driven, nor used: 'unus2' + : ... In instance t.sub3 + 19 | reg [A:0] unus1; reg [A:0] unus2; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_once_bad.pl b/test_regress/t/t_lint_once_bad.pl index 12dd2efbb..8bd893a71 100755 --- a/test_regress/t/t_lint_once_bad.pl +++ b/test_regress/t/t_lint_once_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_once_bad.v b/test_regress/t/t_lint_once_bad.v index c70b88e02..099f6d99d 100644 --- a/test_regress/t/t_lint_once_bad.v +++ b/test_regress/t/t_lint_once_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Check that we report warnings only once on parameterized modules // Also check that we don't suppress warnings on the same line diff --git a/test_regress/t/t_lint_only.pl b/test_regress/t/t_lint_only.pl index 342fcb3c4..0b111f8e8 100755 --- a/test_regress/t/t_lint_only.pl +++ b/test_regress/t/t_lint_only.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_only.v b/test_regress/t/t_lint_only.v index ce955f7ce..123bfbcb0 100644 --- a/test_regress/t/t_lint_only.v +++ b/test_regress/t/t_lint_only.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (); initial begin diff --git a/test_regress/t/t_lint_pindup_bad.out b/test_regress/t/t_lint_pindup_bad.out index 3769a5e47..0e4832769 100644 --- a/test_regress/t/t_lint_pindup_bad.out +++ b/test_regress/t/t_lint_pindup_bad.out @@ -1,31 +1,31 @@ -%Warning-PINMISSING: t/t_lint_pindup_bad.v:18: Cell has missing pin: 'exists' - sub (.o(o), - ^~~ +%Warning-PINMISSING: t/t_lint_pindup_bad.v:19:4: Cell has missing pin: 'exists' + 19 | sub (.o(o), + | ^~~ ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. -%Error: t/t_lint_pindup_bad.v:20: Duplicate pin connection: 'i' - .i(i2), - ^ - t/t_lint_pindup_bad.v:19: ... Location of original pin connection - .i(i), - ^ -%Error: t/t_lint_pindup_bad.v:21: Pin not found: 'nexist' - : ... Suggested alternative: 'exists' - .nexist(i2) - ^~~~~~ -%Error: t/t_lint_pindup_bad.v:15: Parameter pin not found: 'NEXIST' - : ... Suggested alternative: 'EXIST' - .NEXIST(1), - ^~~~~~ -%Error: t/t_lint_pindup_bad.v:16: Duplicate parameter pin connection: 'P' - .P(2), - ^ - t/t_lint_pindup_bad.v:14: ... Location of original parameter pin connection - #(, - ^ -%Error: t/t_lint_pindup_bad.v:17: Duplicate parameter pin connection: 'P' - .P(3)) - ^ - t/t_lint_pindup_bad.v:14: ... Location of original parameter pin connection - #(, - ^ +%Error: t/t_lint_pindup_bad.v:21:10: Duplicate pin connection: 'i' + 21 | .i(i2), + | ^ + t/t_lint_pindup_bad.v:20:10: ... Location of original pin connection + 20 | .i(i), + | ^ +%Error: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist' + : ... Suggested alternative: 'exists' + 22 | .nexist(i2) + | ^~~~~~ +%Error: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST' + : ... Suggested alternative: 'EXIST' + 16 | .NEXIST(1), + | ^~~~~~ +%Error: t/t_lint_pindup_bad.v:17:9: Duplicate parameter pin connection: 'P' + 17 | .P(2), + | ^ + t/t_lint_pindup_bad.v:15:8: ... Location of original parameter pin connection + 15 | #(, + | ^ +%Error: t/t_lint_pindup_bad.v:18:9: Duplicate parameter pin connection: 'P' + 18 | .P(3)) + | ^ + t/t_lint_pindup_bad.v:15:8: ... Location of original parameter pin connection + 15 | #(, + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_pindup_bad.pl b/test_regress/t/t_lint_pindup_bad.pl index 573f98f12..8e4fecbdb 100755 --- a/test_regress/t/t_lint_pindup_bad.pl +++ b/test_regress/t/t_lint_pindup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_pindup_bad.v b/test_regress/t/t_lint_pindup_bad.v index 971de76d8..115911643 100644 --- a/test_regress/t/t_lint_pindup_bad.v +++ b/test_regress/t/t_lint_pindup_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_pkg_colon_bad.out b/test_regress/t/t_lint_pkg_colon_bad.out index 3ba969bcd..9af5556c8 100644 --- a/test_regress/t/t_lint_pkg_colon_bad.out +++ b/test_regress/t/t_lint_pkg_colon_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_lint_pkg_colon_bad.v:6: syntax error, unexpected ::, expecting ')' or ',' -module t (input mispkg::foo_t a); - ^~ - : ... Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3) -%Error: t/t_lint_pkg_colon_bad.v:7: syntax error, unexpected ::, expecting ',' or ';' - reg mispkgb::bar_t b; - ^~ +%Error: t/t_lint_pkg_colon_bad.v:7:23: syntax error, unexpected ::, expecting ')' or ',' + 7 | module t (input mispkg::foo_t a); + | ^~ + : ... Perhaps 'mispkg' is a package which needs to be predeclared? (IEEE 1800-2017 26.3) +%Error: t/t_lint_pkg_colon_bad.v:8:15: syntax error, unexpected ::, expecting ',' or ';' + 8 | reg mispkgb::bar_t b; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_pkg_colon_bad.pl b/test_regress/t/t_lint_pkg_colon_bad.pl index 573f98f12..8e4fecbdb 100755 --- a/test_regress/t/t_lint_pkg_colon_bad.pl +++ b/test_regress/t/t_lint_pkg_colon_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_pkg_colon_bad.v b/test_regress/t/t_lint_pkg_colon_bad.v index 1f813e869..ece082d5b 100644 --- a/test_regress/t/t_lint_pkg_colon_bad.v +++ b/test_regress/t/t_lint_pkg_colon_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (input mispkg::foo_t a); reg mispkgb::bar_t b; diff --git a/test_regress/t/t_lint_realcvt_bad.out b/test_regress/t/t_lint_realcvt_bad.out index a41da1e6f..b21a18477 100644 --- a/test_regress/t/t_lint_realcvt_bad.out +++ b/test_regress/t/t_lint_realcvt_bad.out @@ -1,5 +1,5 @@ -%Warning-REALCVT: t/t_lint_realcvt_bad.v:9: Implicit conversion of real to integer - i = 23.2; - ^~~~ +%Warning-REALCVT: t/t_lint_realcvt_bad.v:10:11: Implicit conversion of real to integer + 10 | i = 23.2; + | ^~~~ ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_realcvt_bad.pl b/test_regress/t/t_lint_realcvt_bad.pl index 8c8597ccf..91afccfab 100755 --- a/test_regress/t/t_lint_realcvt_bad.pl +++ b/test_regress/t/t_lint_realcvt_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_realcvt_bad.v b/test_regress/t/t_lint_realcvt_bad.v index 54b659e2f..3ebd6ed7c 100644 --- a/test_regress/t/t_lint_realcvt_bad.v +++ b/test_regress/t/t_lint_realcvt_bad.v @@ -1,11 +1,13 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module sub; integer i; initial begin i = 23.2; + i = 23.0; // No warning - often happens with units of time end endmodule diff --git a/test_regress/t/t_lint_repeat_bad.out b/test_regress/t/t_lint_repeat_bad.out index 49bfe10d6..234280873 100644 --- a/test_regress/t/t_lint_repeat_bad.out +++ b/test_regress/t/t_lint_repeat_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTH: t/t_lint_repeat_bad.v:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits. - : ... In instance t.sub2 - wire [0:0] b = a; - ^ +%Warning-WIDTH: t/t_lint_repeat_bad.v:18:17: Operator ASSIGNW expects 1 bits on the Assign RHS, but Assign RHS's VARREF 'a' generates 2 bits. + : ... In instance t.sub2 + 18 | wire [0:0] b = a; + | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_repeat_bad.pl b/test_regress/t/t_lint_repeat_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_lint_repeat_bad.pl +++ b/test_regress/t/t_lint_repeat_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_repeat_bad.v b/test_regress/t/t_lint_repeat_bad.v index f0ab52b56..18dac4075 100644 --- a/test_regress/t/t_lint_repeat_bad.v +++ b/test_regress/t/t_lint_repeat_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_restore_bad.out b/test_regress/t/t_lint_restore_bad.out index e6def6ca1..b01c1a699 100644 --- a/test_regress/t/t_lint_restore_bad.out +++ b/test_regress/t/t_lint_restore_bad.out @@ -1,6 +1,6 @@ -%Warning-WIDTH: t/t_lint_restore_bad.v:18: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. - : ... In instance t - initial five = 64'h1; - ^ +%Warning-WIDTH: t/t_lint_restore_bad.v:19:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. + : ... In instance t + 19 | initial five = 64'h1; + | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_restore_bad.pl b/test_regress/t/t_lint_restore_bad.pl index 9832155f2..ddbffc478 100755 --- a/test_regress/t/t_lint_restore_bad.pl +++ b/test_regress/t/t_lint_restore_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_restore_bad.v b/test_regress/t/t_lint_restore_bad.v index 7f2637557..6ab896dbb 100644 --- a/test_regress/t/t_lint_restore_bad.v +++ b/test_regress/t/t_lint_restore_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_rsvd_bad.out b/test_regress/t/t_lint_rsvd_bad.out index 8f947efdb..8cf338ee9 100644 --- a/test_regress/t/t_lint_rsvd_bad.out +++ b/test_regress/t/t_lint_rsvd_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_lint_rsvd_bad.v:6: Unsupported: Verilog 2001-config reserved word not implemented: 'config' -config cfgBad; -^~~~~~ -%Error: t/t_lint_rsvd_bad.v:6: syntax error, unexpected IDENTIFIER -config cfgBad; - ^~~~~~ -%Error: t/t_lint_rsvd_bad.v:7: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig' -endconfig -^~~~~~~~~ +%Error: t/t_lint_rsvd_bad.v:7:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config' + 7 | config cfgBad; + | ^~~~~~ +%Error: t/t_lint_rsvd_bad.v:7:8: syntax error, unexpected IDENTIFIER + 7 | config cfgBad; + | ^~~~~~ +%Error: t/t_lint_rsvd_bad.v:8:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig' + 8 | endconfig + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_rsvd_bad.pl b/test_regress/t/t_lint_rsvd_bad.pl index 8c8597ccf..91afccfab 100755 --- a/test_regress/t/t_lint_rsvd_bad.pl +++ b/test_regress/t/t_lint_rsvd_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_rsvd_bad.v b/test_regress/t/t_lint_rsvd_bad.v index 4639f03d9..7fc2f16c5 100644 --- a/test_regress/t/t_lint_rsvd_bad.v +++ b/test_regress/t/t_lint_rsvd_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 config cfgBad; endconfig diff --git a/test_regress/t/t_lint_setout_bad.out b/test_regress/t/t_lint_setout_bad.out index 747b17c07..2ed7227db 100644 --- a/test_regress/t/t_lint_setout_bad.out +++ b/test_regress/t/t_lint_setout_bad.out @@ -1,5 +1,5 @@ -%Error-PORTSHORT: t/t_lint_setout_bad.v:16: Output port is connected to a constant pin, electrical short - : ... In instance t - .cpu_if_timeout(1'b0) - ^~~~~~~~~~~~~~ +%Error-PORTSHORT: t/t_lint_setout_bad.v:17:8: Output port is connected to a constant pin, electrical short + : ... In instance t + 17 | .cpu_if_timeout(1'b0) + | ^~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_setout_bad.pl b/test_regress/t/t_lint_setout_bad.pl index 573f98f12..8e4fecbdb 100755 --- a/test_regress/t/t_lint_setout_bad.pl +++ b/test_regress/t/t_lint_setout_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_setout_bad.v b/test_regress/t/t_lint_setout_bad.v index 0b8b01f75..23a4339ba 100644 --- a/test_regress/t/t_lint_setout_bad.v +++ b/test_regress/t/t_lint_setout_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_setout_bad_noinl.out b/test_regress/t/t_lint_setout_bad_noinl.out index 747b17c07..2ed7227db 100644 --- a/test_regress/t/t_lint_setout_bad_noinl.out +++ b/test_regress/t/t_lint_setout_bad_noinl.out @@ -1,5 +1,5 @@ -%Error-PORTSHORT: t/t_lint_setout_bad.v:16: Output port is connected to a constant pin, electrical short - : ... In instance t - .cpu_if_timeout(1'b0) - ^~~~~~~~~~~~~~ +%Error-PORTSHORT: t/t_lint_setout_bad.v:17:8: Output port is connected to a constant pin, electrical short + : ... In instance t + 17 | .cpu_if_timeout(1'b0) + | ^~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_setout_bad_noinl.pl b/test_regress/t/t_lint_setout_bad_noinl.pl index 716bf3389..885402cc2 100755 --- a/test_regress/t/t_lint_setout_bad_noinl.pl +++ b/test_regress/t/t_lint_setout_bad_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_subout_bad.out b/test_regress/t/t_lint_subout_bad.out index 9510845f0..32c40ece4 100644 --- a/test_regress/t/t_lint_subout_bad.out +++ b/test_regress/t/t_lint_subout_bad.out @@ -1,13 +1,13 @@ -%Error-PORTSHORT: t/t_lint_subout_bad.v:11: Output port is connected to a constant pin, electrical short - : ... In instance t - sub sub1(.out({32'b0, sig})); - ^~~ -%Error-PORTSHORT: t/t_lint_subout_bad.v:12: Output port is connected to a constant pin, electrical short - : ... In instance t - sub sub2(.out({32'b1, sig})); - ^~~ -%Error-PORTSHORT: t/t_lint_subout_bad.v:10: Output port is connected to a constant pin, electrical short - : ... In instance t - sub sub0(.out(33'b0)); - ^~~ +%Error-PORTSHORT: t/t_lint_subout_bad.v:12:14: Output port is connected to a constant pin, electrical short + : ... In instance t + 12 | sub sub1(.out({32'b0, sig})); + | ^~~ +%Error-PORTSHORT: t/t_lint_subout_bad.v:13:14: Output port is connected to a constant pin, electrical short + : ... In instance t + 13 | sub sub2(.out({32'b1, sig})); + | ^~~ +%Error-PORTSHORT: t/t_lint_subout_bad.v:11:14: Output port is connected to a constant pin, electrical short + : ... In instance t + 11 | sub sub0(.out(33'b0)); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_subout_bad.pl b/test_regress/t/t_lint_subout_bad.pl index 076f15279..31eb2c003 100755 --- a/test_regress/t/t_lint_subout_bad.pl +++ b/test_regress/t/t_lint_subout_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_lint_subout_bad.v b/test_regress/t/t_lint_subout_bad.v index 475803de8..703d59a1c 100644 --- a/test_regress/t/t_lint_subout_bad.v +++ b/test_regress/t/t_lint_subout_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNDRIVEN diff --git a/test_regress/t/t_lint_syncasyncnet_bad.out b/test_regress/t/t_lint_syncasyncnet_bad.out index 8ca9a32da..fd13ef2e0 100644 --- a/test_regress/t/t_lint_syncasyncnet_bad.out +++ b/test_regress/t/t_lint_syncasyncnet_bad.out @@ -1,9 +1,9 @@ -%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:15: Signal flopped as both synchronous and async: 'rst_both_l' - t/t_lint_syncasyncnet_bad.v:90: ... Location of async usage - q2 <= (~rst_both_l) ? 1'b0 : d; - ^~~~~~~~~~ - t/t_lint_syncasyncnet_bad.v:58: ... Location of sync usage - q2 <= (rst_both_l) ? d : 1'b0; - ^~~~~~~~~~ +%Warning-SYNCASYNCNET: t/t_lint_syncasyncnet_bad.v:16:25: Signal flopped as both synchronous and async: 'rst_both_l' + t/t_lint_syncasyncnet_bad.v:91:15: ... Location of async usage + 91 | q2 <= (~rst_both_l) ? 1'b0 : d; + | ^~~~~~~~~~ + t/t_lint_syncasyncnet_bad.v:59:14: ... Location of sync usage + 59 | q2 <= (rst_both_l) ? d : 1'b0; + | ^~~~~~~~~~ ... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_syncasyncnet_bad.pl b/test_regress/t/t_lint_syncasyncnet_bad.pl index 9d2f54367..91b01543a 100755 --- a/test_regress/t/t_lint_syncasyncnet_bad.pl +++ b/test_regress/t/t_lint_syncasyncnet_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_syncasyncnet_bad.v b/test_regress/t/t_lint_syncasyncnet_bad.v index 2335dbcc5..f941d0514 100644 --- a/test_regress/t/t_lint_syncasyncnet_bad.v +++ b/test_regress/t/t_lint_syncasyncnet_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_lint_unsized_bad.out b/test_regress/t/t_lint_unsized_bad.out index 11b16446c..3eaf50102 100644 --- a/test_regress/t/t_lint_unsized_bad.out +++ b/test_regress/t/t_lint_unsized_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_lint_unsized_bad.v:7: Too many digits for 32 bit number: 'd123456789123456789123456789 +%Error: t/t_lint_unsized_bad.v:8:22: Too many digits for 32 bit number: 'd123456789123456789123456789 ... As that number was unsized ('d...) it is limited to 32 bits (IEEE 1800-2017 5.7.1) ... Suggest adding a size to it. - bit [256:0] num = 'd123456789123456789123456789; - ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + 8 | bit [256:0] num = 'd123456789123456789123456789; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_unsized_bad.pl b/test_regress/t/t_lint_unsized_bad.pl index 573f98f12..8e4fecbdb 100755 --- a/test_regress/t/t_lint_unsized_bad.pl +++ b/test_regress/t/t_lint_unsized_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_unsized_bad.v b/test_regress/t/t_lint_unsized_bad.v index 1157b47b9..2449ade13 100644 --- a/test_regress/t/t_lint_unsized_bad.v +++ b/test_regress/t/t_lint_unsized_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; bit [256:0] num = 'd123456789123456789123456789; diff --git a/test_regress/t/t_lint_unsup_deassign.pl b/test_regress/t/t_lint_unsup_deassign.pl index 27b7e1ba7..fc2bfc33a 100755 --- a/test_regress/t/t_lint_unsup_deassign.pl +++ b/test_regress/t/t_lint_unsup_deassign.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_unsup_deassign.v b/test_regress/t/t_lint_unsup_deassign.v index c931e6213..05454d438 100644 --- a/test_regress/t/t_lint_unsup_deassign.v +++ b/test_regress/t/t_lint_unsup_deassign.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_unsup_mixed.pl b/test_regress/t/t_lint_unsup_mixed.pl index 27b7e1ba7..fc2bfc33a 100755 --- a/test_regress/t/t_lint_unsup_mixed.pl +++ b/test_regress/t/t_lint_unsup_mixed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_unsup_mixed.v b/test_regress/t/t_lint_unsup_mixed.v index 779b0396f..ec63e6a7f 100644 --- a/test_regress/t/t_lint_unsup_mixed.v +++ b/test_regress/t/t_lint_unsup_mixed.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_lint_unused.pl b/test_regress/t/t_lint_unused.pl index f8c7bf294..fedb2b1f8 100755 --- a/test_regress/t/t_lint_unused.pl +++ b/test_regress/t/t_lint_unused.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_unused.v b/test_regress/t/t_lint_unused.v index 801e50f9d..3042c127e 100644 --- a/test_regress/t/t_lint_unused.v +++ b/test_regress/t/t_lint_unused.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_lint_unused_bad.out b/test_regress/t/t_lint_unused_bad.out index 1d5a61c0f..9e888314f 100644 --- a/test_regress/t/t_lint_unused_bad.out +++ b/test_regress/t/t_lint_unused_bad.out @@ -1,26 +1,26 @@ -%Warning-UNUSED: t/t_lint_unused_bad.v:16: Bits of signal are not used: 'assunu1'[5:1] - : ... In instance t.sub - wire [5:0] assunu1 = 0; - ^~~~~~~ +%Warning-UNUSED: t/t_lint_unused_bad.v:17:15: Bits of signal are not used: 'assunu1'[5:1] + : ... In instance t.sub + 17 | wire [5:0] assunu1 = 0; + | ^~~~~~~ ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. -%Warning-UNDRIVEN: t/t_lint_unused_bad.v:20: Bits of signal are not driven: 'udrb2'[14:13,11] - : ... In instance t.sub - wire [15:10] udrb2; - ^~~~~ -%Warning-UNUSED: t/t_lint_unused_bad.v:25: Signal is not driven, nor used: 'unu3' - : ... In instance t.sub - wire unu3; - ^~~~ -%Warning-UNUSED: t/t_lint_unused_bad.v:27: Bits of signal are not driven, nor used: 'mixed'[3] - : ... In instance t.sub - wire [3:0] mixed; - ^~~~~ -%Warning-UNUSED: t/t_lint_unused_bad.v:27: Bits of signal are not used: 'mixed'[2] - : ... In instance t.sub - wire [3:0] mixed; - ^~~~~ -%Warning-UNDRIVEN: t/t_lint_unused_bad.v:27: Bits of signal are not driven: 'mixed'[1] - : ... In instance t.sub - wire [3:0] mixed; - ^~~~~ +%Warning-UNDRIVEN: t/t_lint_unused_bad.v:21:17: Bits of signal are not driven: 'udrb2'[14:13,11] + : ... In instance t.sub + 21 | wire [15:10] udrb2; + | ^~~~~ +%Warning-UNUSED: t/t_lint_unused_bad.v:26:15: Signal is not driven, nor used: 'unu3' + : ... In instance t.sub + 26 | wire unu3; + | ^~~~ +%Warning-UNUSED: t/t_lint_unused_bad.v:28:15: Bits of signal are not driven, nor used: 'mixed'[3] + : ... In instance t.sub + 28 | wire [3:0] mixed; + | ^~~~~ +%Warning-UNUSED: t/t_lint_unused_bad.v:28:15: Bits of signal are not used: 'mixed'[2] + : ... In instance t.sub + 28 | wire [3:0] mixed; + | ^~~~~ +%Warning-UNDRIVEN: t/t_lint_unused_bad.v:28:15: Bits of signal are not driven: 'mixed'[1] + : ... In instance t.sub + 28 | wire [3:0] mixed; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_unused_bad.pl b/test_regress/t/t_lint_unused_bad.pl index f064f16a6..545ee3858 100755 --- a/test_regress/t/t_lint_unused_bad.pl +++ b/test_regress/t/t_lint_unused_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_unused_bad.v b/test_regress/t/t_lint_unused_bad.v index 1c17495a7..9ee42b607 100644 --- a/test_regress/t/t_lint_unused_bad.v +++ b/test_regress/t/t_lint_unused_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_lint_unused_iface.pl b/test_regress/t/t_lint_unused_iface.pl index ec740171e..5980d5141 100755 --- a/test_regress/t/t_lint_unused_iface.pl +++ b/test_regress/t/t_lint_unused_iface.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_unused_iface.v b/test_regress/t/t_lint_unused_iface.v index cef438658..3b8f61fcb 100644 --- a/test_regress/t/t_lint_unused_iface.v +++ b/test_regress/t/t_lint_unused_iface.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic signal; diff --git a/test_regress/t/t_lint_unused_iface_bad.out b/test_regress/t/t_lint_unused_iface_bad.out index c8bbd21d5..917ccb9fe 100644 --- a/test_regress/t/t_lint_unused_iface_bad.out +++ b/test_regress/t/t_lint_unused_iface_bad.out @@ -1,10 +1,10 @@ -%Warning-UNDRIVEN: t/t_lint_unused_iface_bad.v:7: Signal is not driven: 'sig_udrv' - : ... In instance t.sub - logic sig_udrv; - ^~~~~~~~ +%Warning-UNDRIVEN: t/t_lint_unused_iface_bad.v:8:10: Signal is not driven: 'sig_udrv' + : ... In instance t.sub + 8 | logic sig_udrv; + | ^~~~~~~~ ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. -%Warning-UNUSED: t/t_lint_unused_iface_bad.v:8: Signal is not used: 'sig_uusd' - : ... In instance t.sub - logic sig_uusd; - ^~~~~~~~ +%Warning-UNUSED: t/t_lint_unused_iface_bad.v:9:10: Signal is not used: 'sig_uusd' + : ... In instance t.sub + 9 | logic sig_uusd; + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_unused_iface_bad.pl b/test_regress/t/t_lint_unused_iface_bad.pl index 94a80eba6..2d0d72931 100755 --- a/test_regress/t/t_lint_unused_iface_bad.pl +++ b/test_regress/t/t_lint_unused_iface_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_unused_iface_bad.v b/test_regress/t/t_lint_unused_iface_bad.v index 92edeee1a..7a46a8cc2 100644 --- a/test_regress/t/t_lint_unused_iface_bad.v +++ b/test_regress/t/t_lint_unused_iface_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface dummy_if (); logic sig_udrv; diff --git a/test_regress/t/t_lint_vcmarker_bad.out b/test_regress/t/t_lint_vcmarker_bad.out index 32354dc42..944368358 100644 --- a/test_regress/t/t_lint_vcmarker_bad.out +++ b/test_regress/t/t_lint_vcmarker_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_lint_vcmarker_bad.v:8: version control conflict marker in file -<<<<<<< HEAD -^~~~~~~~~~~~~~~ -%Error: t/t_lint_vcmarker_bad.v:10: version control conflict marker in file -======= -^~~~~~~~~~~ -%Error: t/t_lint_vcmarker_bad.v:12: version control conflict marker in file ->>>>>>> MERGE -^~~~~~~~~~~~~~~~ +%Error: t/t_lint_vcmarker_bad.v:9:1: version control conflict marker in file + 9 | <<<<<<< HEAD + | ^~~~~~~~~~~~~~~ +%Error: t/t_lint_vcmarker_bad.v:11:1: version control conflict marker in file + 11 | ======= + | ^~~~~~~~~~~ +%Error: t/t_lint_vcmarker_bad.v:13:1: version control conflict marker in file + 13 | >>>>>>> MERGE + | ^~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_vcmarker_bad.pl b/test_regress/t/t_lint_vcmarker_bad.pl index 9832155f2..ddbffc478 100755 --- a/test_regress/t/t_lint_vcmarker_bad.pl +++ b/test_regress/t/t_lint_vcmarker_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_vcmarker_bad.v b/test_regress/t/t_lint_vcmarker_bad.v index b959c373a..83a318ad2 100644 --- a/test_regress/t/t_lint_vcmarker_bad.v +++ b/test_regress/t/t_lint_vcmarker_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_lint_width.pl b/test_regress/t/t_lint_width.pl index 8b1228f9f..793cc4cb1 100755 --- a/test_regress/t/t_lint_width.pl +++ b/test_regress/t/t_lint_width.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_width.v b/test_regress/t/t_lint_width.v index 80e03b89d..18db807d8 100644 --- a/test_regress/t/t_lint_width.v +++ b/test_regress/t/t_lint_width.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_width_bad.out b/test_regress/t/t_lint_width_bad.out index e3fde1e3a..b2802d6b0 100644 --- a/test_regress/t/t_lint_width_bad.out +++ b/test_regress/t/t_lint_width_bad.out @@ -1,42 +1,42 @@ -%Warning-WIDTH: t/t_lint_width_bad.v:16: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. - : ... In instance t - localparam [3:0] XS = 'hx; - ^~ +%Warning-WIDTH: t/t_lint_width_bad.v:17:25: Operator VAR 'XS' expects 4 bits on the Initial value, but Initial value's CONST '?32?bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx' generates 32 bits. + : ... In instance t + 17 | localparam [3:0] XS = 'hx; + | ^~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_lint_width_bad.v:44: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. - : ... In instance t.p4 - wire [4:0] out = in; - ^ -%Warning-WIDTH: t/t_lint_width_bad.v:20: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits. - : ... In instance t - wire [4:0] d = (1'b1 << 2) + 5'b1; - ^~ -%Warning-WIDTH: t/t_lint_width_bad.v:26: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits. - : ... In instance t - wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); - ^ -%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits. - : ... In instance t - wire [2:0] cnt = (one + one + one + one); - ^ -%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. - : ... In instance t - wire [2:0] cnt = (one + one + one + one); - ^ -%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. - : ... In instance t - wire [2:0] cnt = (one + one + one + one); - ^ -%Warning-WIDTH: t/t_lint_width_bad.v:31: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. - : ... In instance t - wire [2:0] cnt = (one + one + one + one); - ^ -%Warning-WIDTH: t/t_lint_width_bad.v:36: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. - : ... In instance t - initial for (a = 0; a > THREE; ++a) $display(a); - ^ -%Warning-WIDTH: t/t_lint_width_bad.v:37: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. - : ... In instance t - initial for (a = 0; a >= THREE; ++a) $display(a); - ^~ +%Warning-WIDTH: t/t_lint_width_bad.v:45:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. + : ... In instance t.p4 + 45 | wire [4:0] out = in; + | ^ +%Warning-WIDTH: t/t_lint_width_bad.v:21:25: Operator SHIFTL expects 5 bits on the LHS, but LHS's CONST '1'h1' generates 1 bits. + : ... In instance t + 21 | wire [4:0] d = (1'b1 << 2) + 5'b1; + | ^~ +%Warning-WIDTH: t/t_lint_width_bad.v:27:32: Operator ASSIGNW expects 6 bits on the Assign RHS, but Assign RHS's SHIFTL generates 7 bits. + : ... In instance t + 27 | wire [WIDTH-1:0] masked = (({{(WIDTH){1'b0}}, one_bit}) << shifter); + | ^ +%Warning-WIDTH: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the LHS, but LHS's VARREF 'one' generates 1 bits. + : ... In instance t + 32 | wire [2:0] cnt = (one + one + one + one); + | ^ +%Warning-WIDTH: t/t_lint_width_bad.v:32:37: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + : ... In instance t + 32 | wire [2:0] cnt = (one + one + one + one); + | ^ +%Warning-WIDTH: t/t_lint_width_bad.v:32:43: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + : ... In instance t + 32 | wire [2:0] cnt = (one + one + one + one); + | ^ +%Warning-WIDTH: t/t_lint_width_bad.v:32:49: Operator ADD expects 3 bits on the RHS, but RHS's VARREF 'one' generates 1 bits. + : ... In instance t + 32 | wire [2:0] cnt = (one + one + one + one); + | ^ +%Warning-WIDTH: t/t_lint_width_bad.v:37:26: Operator GT expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. + : ... In instance t + 37 | initial for (a = 0; a > THREE; ++a) $display(a); + | ^ +%Warning-WIDTH: t/t_lint_width_bad.v:38:26: Operator GTE expects 41 bits on the LHS, but LHS's VARREF 'a' generates 32 bits. + : ... In instance t + 38 | initial for (a = 0; a >= THREE; ++a) $display(a); + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_bad.pl b/test_regress/t/t_lint_width_bad.pl index 9832155f2..ddbffc478 100755 --- a/test_regress/t/t_lint_width_bad.pl +++ b/test_regress/t/t_lint_width_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_lint_width_bad.v b/test_regress/t/t_lint_width_bad.v index 396f85ddb..e8f18a128 100644 --- a/test_regress/t/t_lint_width_bad.v +++ b/test_regress/t/t_lint_width_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_lint_width_genfor.pl b/test_regress/t/t_lint_width_genfor.pl index 54d98b479..0b00f8646 100755 --- a/test_regress/t/t_lint_width_genfor.pl +++ b/test_regress/t/t_lint_width_genfor.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all}; diff --git a/test_regress/t/t_lint_width_genfor.v b/test_regress/t/t_lint_width_genfor.v index 5cb1c001c..92241350d 100644 --- a/test_regress/t/t_lint_width_genfor.v +++ b/test_regress/t/t_lint_width_genfor.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_lint_width_genfor_bad.out b/test_regress/t/t_lint_width_genfor_bad.out index 4fb3f3a8b..5e344a696 100644 --- a/test_regress/t/t_lint_width_genfor_bad.out +++ b/test_regress/t/t_lint_width_genfor_bad.out @@ -1,22 +1,22 @@ -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:24: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?h10' generates 32 or 5 bits. - : ... In instance t - rg = g; - ^ +%Warning-WIDTH: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?h10' generates 32 or 5 bits. + : ... In instance t + 25 | rg = g; + | ^ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:25: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. - : ... In instance t - rp = P; - ^ -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:26: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. - : ... In instance t - rw = w; - ^ -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:27: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. - : ... In instance t - rc = 64'h1; - ^ -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:32: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. - : ... In instance t - ri = i; - ^ +%Warning-WIDTH: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. + : ... In instance t + 26 | rp = P; + | ^ +%Warning-WIDTH: t/t_lint_width_genfor_bad.v:27:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'w' generates 5 bits. + : ... In instance t + 27 | rw = w; + | ^ +%Warning-WIDTH: t/t_lint_width_genfor_bad.v:28:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits. + : ... In instance t + 28 | rc = 64'h1; + | ^ +%Warning-WIDTH: t/t_lint_width_genfor_bad.v:33:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. + : ... In instance t + 33 | ri = i; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_genfor_bad.pl b/test_regress/t/t_lint_width_genfor_bad.pl index 518625206..f3dd1d2a1 100755 --- a/test_regress/t/t_lint_width_genfor_bad.pl +++ b/test_regress/t/t_lint_width_genfor_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_lint_width_genfor_bad.v b/test_regress/t/t_lint_width_genfor_bad.v index 2641c90df..4463ccf71 100644 --- a/test_regress/t/t_lint_width_genfor_bad.v +++ b/test_regress/t/t_lint_width_genfor_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_math_arith.pl b/test_regress/t/t_math_arith.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_arith.pl +++ b/test_regress/t/t_math_arith.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_arith.v b/test_regress/t/t_math_arith.v index b9287c67c..44945b297 100644 --- a/test_regress/t/t_math_arith.v +++ b/test_regress/t/t_math_arith.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_clog2.pl b/test_regress/t/t_math_clog2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_clog2.pl +++ b/test_regress/t/t_math_clog2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_clog2.v b/test_regress/t/t_math_clog2.v index 3fad0bc9b..713cb15f5 100644 --- a/test_regress/t/t_math_clog2.v +++ b/test_regress/t/t_math_clog2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `ifdef verilator `define CLOG2 $clog2 diff --git a/test_regress/t/t_math_cmp.pl b/test_regress/t/t_math_cmp.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_cmp.pl +++ b/test_regress/t/t_math_cmp.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_cmp.v b/test_regress/t/t_math_cmp.v index 6402e205f..6df08388a 100644 --- a/test_regress/t/t_math_cmp.v +++ b/test_regress/t/t_math_cmp.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_concat.pl b/test_regress/t/t_math_concat.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_concat.pl +++ b/test_regress/t/t_math_concat.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_concat.v b/test_regress/t/t_math_concat.v index 7a6a79ff6..a70ec1afa 100644 --- a/test_regress/t/t_math_concat.v +++ b/test_regress/t/t_math_concat.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_concat0.pl b/test_regress/t/t_math_concat0.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_concat0.pl +++ b/test_regress/t/t_math_concat0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_concat0.v b/test_regress/t/t_math_concat0.v index eab897d2d..fd18e18aa 100644 --- a/test_regress/t/t_math_concat0.v +++ b/test_regress/t/t_math_concat0.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_concat64.pl b/test_regress/t/t_math_concat64.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_concat64.pl +++ b/test_regress/t/t_math_concat64.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_concat64.v b/test_regress/t/t_math_concat64.v index f40739b42..54f1ec601 100644 --- a/test_regress/t/t_math_concat64.v +++ b/test_regress/t/t_math_concat64.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_concat_sel_bad.pl b/test_regress/t/t_math_concat_sel_bad.pl index 41002ca7a..54363604a 100755 --- a/test_regress/t/t_math_concat_sel_bad.pl +++ b/test_regress/t/t_math_concat_sel_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_concat_sel_bad.v b/test_regress/t/t_math_concat_sel_bad.v index 78ec137eb..88620ca3d 100644 --- a/test_regress/t/t_math_concat_sel_bad.v +++ b/test_regress/t/t_math_concat_sel_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_cond_clean.pl b/test_regress/t/t_math_cond_clean.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_math_cond_clean.pl +++ b/test_regress/t/t_math_cond_clean.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_cond_clean.v b/test_regress/t/t_math_cond_clean.v index 4b0ab4039..ca804c671 100644 --- a/test_regress/t/t_math_cond_clean.v +++ b/test_regress/t/t_math_cond_clean.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_cond_huge.pl b/test_regress/t/t_math_cond_huge.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_cond_huge.pl +++ b/test_regress/t/t_math_cond_huge.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_cond_huge.v b/test_regress/t/t_math_cond_huge.v index 1205c6c79..22b9e65dd 100644 --- a/test_regress/t/t_math_cond_huge.v +++ b/test_regress/t/t_math_cond_huge.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_const.pl b/test_regress/t/t_math_const.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_const.pl +++ b/test_regress/t/t_math_const.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_const.v b/test_regress/t/t_math_const.v index abd6478c2..654a7161d 100644 --- a/test_regress/t/t_math_const.v +++ b/test_regress/t/t_math_const.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_div.pl b/test_regress/t/t_math_div.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_div.pl +++ b/test_regress/t/t_math_div.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_div.v b/test_regress/t/t_math_div.v index 2fe380be8..9c023a1e5 100644 --- a/test_regress/t/t_math_div.v +++ b/test_regress/t/t_math_div.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_div0.pl b/test_regress/t/t_math_div0.pl index 525dd83c5..5f57f767d 100755 --- a/test_regress/t/t_math_div0.pl +++ b/test_regress/t/t_math_div0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_div0.v b/test_regress/t/t_math_div0.v index 2d6fb09c3..6cc635a9c 100644 --- a/test_regress/t/t_math_div0.v +++ b/test_regress/t/t_math_div0.v @@ -1,3 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + module t(y); output [3:0] y; // bug775 diff --git a/test_regress/t/t_math_divw.pl b/test_regress/t/t_math_divw.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_divw.pl +++ b/test_regress/t/t_math_divw.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_divw.v b/test_regress/t/t_math_divw.v index f8c5d899b..0bb952bd7 100644 --- a/test_regress/t/t_math_divw.v +++ b/test_regress/t/t_math_divw.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_eq.pl b/test_regress/t/t_math_eq.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_eq.pl +++ b/test_regress/t/t_math_eq.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_eq.v b/test_regress/t/t_math_eq.v index 36a46643f..13f0f866f 100644 --- a/test_regress/t/t_math_eq.v +++ b/test_regress/t/t_math_eq.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_equal.pl b/test_regress/t/t_math_equal.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_math_equal.pl +++ b/test_regress/t/t_math_equal.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_equal.v b/test_regress/t/t_math_equal.v index 437bd0f6e..d9afe52f5 100644 --- a/test_regress/t/t_math_equal.v +++ b/test_regress/t/t_math_equal.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_imm.pl b/test_regress/t/t_math_imm.pl index 803dca735..d6841bed0 100755 --- a/test_regress/t/t_math_imm.pl +++ b/test_regress/t/t_math_imm.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_imm.v b/test_regress/t/t_math_imm.v index 709fcae81..6ef2eb10a 100644 --- a/test_regress/t/t_math_imm.v +++ b/test_regress/t/t_math_imm.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // // Example module to create problem. // diff --git a/test_regress/t/t_math_imm2.cpp b/test_regress/t/t_math_imm2.cpp index 16cf354b2..64d3544f2 100644 --- a/test_regress/t/t_math_imm2.cpp +++ b/test_regress/t/t_math_imm2.cpp @@ -1,4 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include "Vt_math_imm2.h" diff --git a/test_regress/t/t_math_imm2.pl b/test_regress/t/t_math_imm2.pl index da60e8024..f2624d772 100755 --- a/test_regress/t/t_math_imm2.pl +++ b/test_regress/t/t_math_imm2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_math_imm2.v b/test_regress/t/t_math_imm2.v index a14b9d83d..4a0bff5d3 100644 --- a/test_regress/t/t_math_imm2.v +++ b/test_regress/t/t_math_imm2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // // Example module to create problem. // diff --git a/test_regress/t/t_math_msvc_64.pl b/test_regress/t/t_math_msvc_64.pl index 4780ffb2e..c1a964fed 100755 --- a/test_regress/t/t_math_msvc_64.pl +++ b/test_regress/t/t_math_msvc_64.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_msvc_64.v b/test_regress/t/t_math_msvc_64.v index e5052f47d..27d49b279 100644 --- a/test_regress/t/t_math_msvc_64.v +++ b/test_regress/t/t_math_msvc_64.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_mul.pl b/test_regress/t/t_math_mul.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_mul.pl +++ b/test_regress/t/t_math_mul.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_mul.v b/test_regress/t/t_math_mul.v index 5f987eced..f83c751e0 100644 --- a/test_regress/t/t_math_mul.v +++ b/test_regress/t/t_math_mul.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_pick.pl b/test_regress/t/t_math_pick.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_pick.pl +++ b/test_regress/t/t_math_pick.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_pick.v b/test_regress/t/t_math_pick.v index 1e865f89f..03ccdb90d 100644 --- a/test_regress/t/t_math_pick.v +++ b/test_regress/t/t_math_pick.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_pow.pl b/test_regress/t/t_math_pow.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_pow.pl +++ b/test_regress/t/t_math_pow.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_pow.v b/test_regress/t/t_math_pow.v index 285d0b620..3afbf8433 100644 --- a/test_regress/t/t_math_pow.v +++ b/test_regress/t/t_math_pow.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `ifdef VERILATOR `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) diff --git a/test_regress/t/t_math_pow2.pl b/test_regress/t/t_math_pow2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_pow2.pl +++ b/test_regress/t/t_math_pow2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_pow2.v b/test_regress/t/t_math_pow2.v index e15c5b673..114f04f56 100644 --- a/test_regress/t/t_math_pow2.v +++ b/test_regress/t/t_math_pow2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_pow3.pl b/test_regress/t/t_math_pow3.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_pow3.pl +++ b/test_regress/t/t_math_pow3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_pow3.v b/test_regress/t/t_math_pow3.v index be35aa254..785e05382 100644 --- a/test_regress/t/t_math_pow3.v +++ b/test_regress/t/t_math_pow3.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail=1; end while(0) diff --git a/test_regress/t/t_math_pow4.pl b/test_regress/t/t_math_pow4.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_pow4.pl +++ b/test_regress/t/t_math_pow4.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_pow4.v b/test_regress/t/t_math_pow4.v index 392eb3f20..092bcbc0f 100644 --- a/test_regress/t/t_math_pow4.v +++ b/test_regress/t/t_math_pow4.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Clifford Wolf. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_pow5.pl b/test_regress/t/t_math_pow5.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_pow5.pl +++ b/test_regress/t/t_math_pow5.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_pow5.v b/test_regress/t/t_math_pow5.v index 1224836c8..3fe06f5e0 100644 --- a/test_regress/t/t_math_pow5.v +++ b/test_regress/t/t_math_pow5.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_pow6.pl b/test_regress/t/t_math_pow6.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_pow6.pl +++ b/test_regress/t/t_math_pow6.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_pow6.v b/test_regress/t/t_math_pow6.v index b3c88523e..8b9801229 100644 --- a/test_regress/t/t_math_pow6.v +++ b/test_regress/t/t_math_pow6.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_math_precedence.pl b/test_regress/t/t_math_precedence.pl index 2eff63c2b..88a9f757e 100755 --- a/test_regress/t/t_math_precedence.pl +++ b/test_regress/t/t_math_precedence.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_precedence.v b/test_regress/t/t_math_precedence.v index b22042c31..bae1119c9 100644 --- a/test_regress/t/t_math_precedence.v +++ b/test_regress/t/t_math_precedence.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_real.pl b/test_regress/t/t_math_real.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_real.pl +++ b/test_regress/t/t_math_real.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_real.v b/test_regress/t/t_math_real.v index ddf6d2b68..2bcf884e7 100644 --- a/test_regress/t/t_math_real.v +++ b/test_regress/t/t_math_real.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) diff --git a/test_regress/t/t_math_real_public.pl b/test_regress/t/t_math_real_public.pl index b362560d5..af34581d9 100755 --- a/test_regress/t/t_math_real_public.pl +++ b/test_regress/t/t_math_real_public.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_real_public.v b/test_regress/t/t_math_real_public.v index 4ddb2038b..55ecd1d4b 100644 --- a/test_regress/t/t_math_real_public.v +++ b/test_regress/t/t_math_real_public.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Alex Solomatnikov +// SPDX-License-Identifier: CC0-1.0 module t; sub #(.REAL(2.0)) sub; diff --git a/test_regress/t/t_math_real_round.pl b/test_regress/t/t_math_real_round.pl new file mode 100755 index 000000000..1d046ed3f --- /dev/null +++ b/test_regress/t/t_math_real_round.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_real_round.v b/test_regress/t/t_math_real_round.v new file mode 100644 index 000000000..5c6a56870 --- /dev/null +++ b/test_regress/t/t_math_real_round.v @@ -0,0 +1,101 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Copyright 2011 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +`define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + + real r; + reg [31:0] v32; + reg [63:0] v64; + reg [95:0] v96; + + initial begin + // verilator lint_off REALCVT + v32 = -1.5; + v64 = -1.5; + v96 = -1.5; + // verilator lint_on REALCVT + `checkh(v32, 32'hfffffffe); + `checkh(v64, 64'hfffffffffffffffe); + `checkh(v96, 96'hfffffffffffffffffffffffe); + + // verilator lint_off REALCVT + v32 = 12456789012345678912345.5; + v64 = 12456789012345678912345.5; + v96 = 12456789012345678912345.5; + // verilator lint_on REALCVT + `checkh(v32, 32'he5400000); + `checkh(v64, 64'h48acb7d4e5400000); + `checkh(v96, 96'h000002a348acb7d4e5400000); + + // verilator lint_off REALCVT + v32 = -12456789012345678912345.5; + v64 = -12456789012345678912345.5; + v96 = -12456789012345678912345.5; + // verilator lint_on REALCVT + `checkh(v32, 32'h1ac00000); + `checkh(v64, 64'hb753482b1ac00000); + `checkh(v96, 96'hfffffd5cb753482b1ac00000); + end + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc == 10) begin + r <= 0; + end + else if (cyc == 11) begin + // verilator lint_off REALCVT + v32 = r; + v64 = r; + v96 = r; + // verilator lint_on REALCVT + `checkh(v32, '0); + `checkh(v64, '0); + `checkh(v96, '0); + end + else if (cyc == 20) begin + r <= -5.24567; + end + else if (cyc == 21) begin + // verilator lint_off REALCVT + v32 = r; + v64 = r; + v96 = r; + // verilator lint_on REALCVT + `checkh(v32, 32'hfffffffb); + `checkh(v64, 64'hfffffffffffffffb); + `checkh(v96, 96'hfffffffffffffffffffffffb); + end + else if (cyc == 30) begin + r <= 12456789012345678912345.5; + end + else if (cyc == 31) begin + // verilator lint_off REALCVT + v32 = r; + v64 = r; + v96 = r; + // verilator lint_on REALCVT + `checkh(v32, 32'he5400000); + `checkh(v64, 64'h48acb7d4e5400000); + `checkh(v96, 96'h000002a348acb7d4e5400000); + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_math_repl.pl b/test_regress/t/t_math_repl.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_repl.pl +++ b/test_regress/t/t_math_repl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_repl.v b/test_regress/t/t_math_repl.v index 6995ef03c..43b57e044 100644 --- a/test_regress/t/t_math_repl.v +++ b/test_regress/t/t_math_repl.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_reverse.pl b/test_regress/t/t_math_reverse.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_reverse.pl +++ b/test_regress/t/t_math_reverse.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_reverse.v b/test_regress/t/t_math_reverse.v index 90bebd553..f8b6b8a20 100644 --- a/test_regress/t/t_math_reverse.v +++ b/test_regress/t/t_math_reverse.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_shift.pl b/test_regress/t/t_math_shift.pl index 0a3b50107..4a908581b 100755 --- a/test_regress/t/t_math_shift.pl +++ b/test_regress/t/t_math_shift.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_shift.v b/test_regress/t/t_math_shift.v index dfc282320..cd071be78 100644 --- a/test_regress/t/t_math_shift.v +++ b/test_regress/t/t_math_shift.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_math_shift_over_bad.out b/test_regress/t/t_math_shift_over_bad.out index 0054d0ccb..b731354e6 100644 --- a/test_regress/t/t_math_shift_over_bad.out +++ b/test_regress/t/t_math_shift_over_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_math_shift_over_bad.v:18: Value too wide for 32-bits expected in this context 64'h123456789abcdef - : ... In instance t - assign o = i << 64'h01234567_89abcdef; - ^~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_math_shift_over_bad.v:19:20: Value too wide for 32-bits expected in this context 64'h123456789abcdef + : ... In instance t + 19 | assign o = i << 64'h01234567_89abcdef; + | ^~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_math_shift_over_bad.pl b/test_regress/t/t_math_shift_over_bad.pl index 4ba881869..72a231777 100755 --- a/test_regress/t/t_math_shift_over_bad.pl +++ b/test_regress/t/t_math_shift_over_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_math_shift_over_bad.v b/test_regress/t/t_math_shift_over_bad.v index c7005817c..3df5d7b74 100644 --- a/test_regress/t/t_math_shift_over_bad.v +++ b/test_regress/t/t_math_shift_over_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_math_shift_rep.pl b/test_regress/t/t_math_shift_rep.pl index 426086634..e64fd774a 100755 --- a/test_regress/t/t_math_shift_rep.pl +++ b/test_regress/t/t_math_shift_rep.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_shift_rep.v b/test_regress/t/t_math_shift_rep.v index cca83d1ca..cd0011fe1 100644 --- a/test_regress/t/t_math_shift_rep.v +++ b/test_regress/t/t_math_shift_rep.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_shift_sel.pl b/test_regress/t/t_math_shift_sel.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_shift_sel.pl +++ b/test_regress/t/t_math_shift_sel.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_shift_sel.v b/test_regress/t/t_math_shift_sel.v index ecb39172f..e0b20211c 100644 --- a/test_regress/t/t_math_shift_sel.v +++ b/test_regress/t/t_math_shift_sel.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_shiftrs.pl b/test_regress/t/t_math_shiftrs.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_shiftrs.pl +++ b/test_regress/t/t_math_shiftrs.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_shiftrs.v b/test_regress/t/t_math_shiftrs.v index 3248a9412..d89c637dd 100644 --- a/test_regress/t/t_math_shiftrs.v +++ b/test_regress/t/t_math_shiftrs.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_shortreal.pl b/test_regress/t/t_math_shortreal.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_shortreal.pl +++ b/test_regress/t/t_math_shortreal.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_shortreal.v b/test_regress/t/t_math_shortreal.v index b9d1500e8..2d62cef84 100644 --- a/test_regress/t/t_math_shortreal.v +++ b/test_regress/t/t_math_shortreal.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `define is_near_real(a,b) (( ((a)<(b)) ? (b)-(a) : (a)-(b)) < (((a)/(b))*0.0001)) diff --git a/test_regress/t/t_math_shortreal_unsup_bad.out b/test_regress/t/t_math_shortreal_unsup_bad.out index 1e9fc1d38..b73e9626c 100644 --- a/test_regress/t/t_math_shortreal_unsup_bad.out +++ b/test_regress/t/t_math_shortreal_unsup_bad.out @@ -1,5 +1,5 @@ -%Warning-SHORTREAL: t/t_math_shortreal_unsup_bad.v:8: Unsupported: shortreal being promoted to real (suggest use real instead) - shortreal s; - ^~~~~~~~~ +%Warning-SHORTREAL: t/t_math_shortreal_unsup_bad.v:9:4: Unsupported: shortreal being promoted to real (suggest use real instead) + 9 | shortreal s; + | ^~~~~~~~~ ... Use "/* verilator lint_off SHORTREAL */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_math_shortreal_unsup_bad.pl b/test_regress/t/t_math_shortreal_unsup_bad.pl index 4ba881869..72a231777 100755 --- a/test_regress/t/t_math_shortreal_unsup_bad.pl +++ b/test_regress/t/t_math_shortreal_unsup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_math_shortreal_unsup_bad.v b/test_regress/t/t_math_shortreal_unsup_bad.v index 4fa2d5152..a1b356ba5 100644 --- a/test_regress/t/t_math_shortreal_unsup_bad.v +++ b/test_regress/t/t_math_shortreal_unsup_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_math_sign_extend.pl b/test_regress/t/t_math_sign_extend.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_sign_extend.pl +++ b/test_regress/t/t_math_sign_extend.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_sign_extend.v b/test_regress/t/t_math_sign_extend.v index 0dcba05c1..4ca6a714b 100644 --- a/test_regress/t/t_math_sign_extend.v +++ b/test_regress/t/t_math_sign_extend.v @@ -5,6 +5,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Mike Thyer. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_signed.pl b/test_regress/t/t_math_signed.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_signed.pl +++ b/test_regress/t/t_math_signed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_signed.v b/test_regress/t/t_math_signed.v index 2d176c04a..fc92d0d35 100644 --- a/test_regress/t/t_math_signed.v +++ b/test_regress/t/t_math_signed.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_signed2.pl b/test_regress/t/t_math_signed2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_signed2.pl +++ b/test_regress/t/t_math_signed2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_signed2.v b/test_regress/t/t_math_signed2.v index 1250f9922..41337b3d7 100644 --- a/test_regress/t/t_math_signed2.v +++ b/test_regress/t/t_math_signed2.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2007 by Peter Debacker. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_signed3.pl b/test_regress/t/t_math_signed3.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_signed3.pl +++ b/test_regress/t/t_math_signed3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_signed3.v b/test_regress/t/t_math_signed3.v index 079dfca84..3deed359d 100644 --- a/test_regress/t/t_math_signed3.v +++ b/test_regress/t/t_math_signed3.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) diff --git a/test_regress/t/t_math_signed4.pl b/test_regress/t/t_math_signed4.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_signed4.pl +++ b/test_regress/t/t_math_signed4.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_signed4.v b/test_regress/t/t_math_signed4.v index 200cb4718..0cec8a318 100644 --- a/test_regress/t/t_math_signed4.v +++ b/test_regress/t/t_math_signed4.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) diff --git a/test_regress/t/t_math_signed5.pl b/test_regress/t/t_math_signed5.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_signed5.pl +++ b/test_regress/t/t_math_signed5.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_signed5.v b/test_regress/t/t_math_signed5.v index c2f4ef3f8..c6ea2cb32 100644 --- a/test_regress/t/t_math_signed5.v +++ b/test_regress/t/t_math_signed5.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) `define checkf(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%f exp=%f\n", `__FILE__,`__LINE__, (gotv), (expv)); fail='1; end while(0) diff --git a/test_regress/t/t_math_signed6.pl b/test_regress/t/t_math_signed6.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_signed6.pl +++ b/test_regress/t/t_math_signed6.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_signed6.v b/test_regress/t/t_math_signed6.v index 665222516..3820a8b3c 100644 --- a/test_regress/t/t_math_signed6.v +++ b/test_regress/t/t_math_signed6.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) diff --git a/test_regress/t/t_math_signed7.pl b/test_regress/t/t_math_signed7.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_signed7.pl +++ b/test_regress/t/t_math_signed7.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_signed7.v b/test_regress/t/t_math_signed7.v index 421fde7c2..0ed55b0b0 100644 --- a/test_regress/t/t_math_signed7.v +++ b/test_regress/t/t_math_signed7.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) diff --git a/test_regress/t/t_math_signed_wire.pl b/test_regress/t/t_math_signed_wire.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_signed_wire.pl +++ b/test_regress/t/t_math_signed_wire.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_signed_wire.v b/test_regress/t/t_math_signed_wire.v index faa7e53c7..0ddd9fa97 100644 --- a/test_regress/t/t_math_signed_wire.v +++ b/test_regress/t/t_math_signed_wire.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug511 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_math_strwidth.pl b/test_regress/t/t_math_strwidth.pl index 1e3d87b0b..8e6465d34 100755 --- a/test_regress/t/t_math_strwidth.pl +++ b/test_regress/t/t_math_strwidth.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_strwidth.v b/test_regress/t/t_math_strwidth.v index 87dc82e96..37a58925b 100644 --- a/test_regress/t/t_math_strwidth.v +++ b/test_regress/t/t_math_strwidth.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008-2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008-2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_math_svl.pl b/test_regress/t/t_math_svl.pl index d10857db2..89995f82e 100755 --- a/test_regress/t/t_math_svl.pl +++ b/test_regress/t/t_math_svl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2005 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2005 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_svl.v b/test_regress/t/t_math_svl.v index 8f68717c8..6ece121c7 100644 --- a/test_regress/t/t_math_svl.v +++ b/test_regress/t/t_math_svl.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_svl2.pl b/test_regress/t/t_math_svl2.pl index aa70994c6..23acc7831 100755 --- a/test_regress/t/t_math_svl2.pl +++ b/test_regress/t/t_math_svl2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2006 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2006 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_svl2.v b/test_regress/t/t_math_svl2.v index bb6f7e4d1..022f62911 100644 --- a/test_regress/t/t_math_svl2.v +++ b/test_regress/t/t_math_svl2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_swap.pl b/test_regress/t/t_math_swap.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_swap.pl +++ b/test_regress/t/t_math_swap.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_swap.v b/test_regress/t/t_math_swap.v index 96daf421d..f5a78c2f3 100644 --- a/test_regress/t/t_math_swap.v +++ b/test_regress/t/t_math_swap.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_tri.pl b/test_regress/t/t_math_tri.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_tri.pl +++ b/test_regress/t/t_math_tri.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_tri.v b/test_regress/t/t_math_tri.v index 96a873716..eb32a4895 100644 --- a/test_regress/t/t_math_tri.v +++ b/test_regress/t/t_math_tri.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_math_trig.pl b/test_regress/t/t_math_trig.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_trig.pl +++ b/test_regress/t/t_math_trig.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_trig.v b/test_regress/t/t_math_trig.v index 2fa5815d0..a87816e80 100644 --- a/test_regress/t/t_math_trig.v +++ b/test_regress/t/t_math_trig.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_vgen.pl b/test_regress/t/t_math_vgen.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_vgen.pl +++ b/test_regress/t/t_math_vgen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_vgen.v b/test_regress/t/t_math_vgen.v index fc98f93c6..ca2ec8bd6 100644 --- a/test_regress/t/t_math_vgen.v +++ b/test_regress/t/t_math_vgen.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_vliw.pl b/test_regress/t/t_math_vliw.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_vliw.pl +++ b/test_regress/t/t_math_vliw.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_vliw.v b/test_regress/t/t_math_vliw.v index 98821cd42..bf6ab7291 100644 --- a/test_regress/t/t_math_vliw.v +++ b/test_regress/t/t_math_vliw.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_math_width.pl b/test_regress/t/t_math_width.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_math_width.pl +++ b/test_regress/t/t_math_width.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_math_width.v b/test_regress/t/t_math_width.v index 114996abe..a9ba18780 100644 --- a/test_regress/t/t_math_width.v +++ b/test_regress/t/t_math_width.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (); diff --git a/test_regress/t/t_mem.pl b/test_regress/t/t_mem.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem.pl +++ b/test_regress/t/t_mem.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem.v b/test_regress/t/t_mem.v index 4da2ad524..8a6ce3e30 100644 --- a/test_regress/t/t_mem.v +++ b/test_regress/t/t_mem.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_banks.pl b/test_regress/t/t_mem_banks.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_banks.pl +++ b/test_regress/t/t_mem_banks.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_banks.v b/test_regress/t/t_mem_banks.v index 27eb6955e..b810ca532 100644 --- a/test_regress/t/t_mem_banks.v +++ b/test_regress/t/t_mem_banks.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_mem_cond.pl b/test_regress/t/t_mem_cond.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_cond.pl +++ b/test_regress/t/t_mem_cond.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_cond.v b/test_regress/t/t_mem_cond.v index 558340078..b5d6f3f63 100644 --- a/test_regress/t/t_mem_cond.v +++ b/test_regress/t/t_mem_cond.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_mem_fifo.pl b/test_regress/t/t_mem_fifo.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_fifo.pl +++ b/test_regress/t/t_mem_fifo.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_fifo.v b/test_regress/t/t_mem_fifo.v index 12beb0664..8702c4969 100644 --- a/test_regress/t/t_mem_fifo.v +++ b/test_regress/t/t_mem_fifo.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_file.pl b/test_regress/t/t_mem_file.pl index 2b81fb995..214a71ff8 100755 --- a/test_regress/t/t_mem_file.pl +++ b/test_regress/t/t_mem_file.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_file.v b/test_regress/t/t_mem_file.v index 9d8af048d..e1a7574ed 100644 --- a/test_regress/t/t_mem_file.v +++ b/test_regress/t/t_mem_file.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_first.pl b/test_regress/t/t_mem_first.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_first.pl +++ b/test_regress/t/t_mem_first.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_first.v b/test_regress/t/t_mem_first.v index f994375fd..8db61242b 100644 --- a/test_regress/t/t_mem_first.v +++ b/test_regress/t/t_mem_first.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_func.pl b/test_regress/t/t_mem_func.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_func.pl +++ b/test_regress/t/t_mem_func.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_func.v b/test_regress/t/t_mem_func.v index 972dfe4b9..22ca9e223 100644 --- a/test_regress/t/t_mem_func.v +++ b/test_regress/t/t_mem_func.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_iforder.pl b/test_regress/t/t_mem_iforder.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_mem_iforder.pl +++ b/test_regress/t/t_mem_iforder.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_iforder.v b/test_regress/t/t_mem_iforder.v index 3a669005f..1c044fc6f 100644 --- a/test_regress/t/t_mem_iforder.v +++ b/test_regress/t/t_mem_iforder.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_multi_io.pl b/test_regress/t/t_mem_multi_io.pl index 6ab567600..4f35f28e6 100755 --- a/test_regress/t/t_mem_multi_io.pl +++ b/test_regress/t/t_mem_multi_io.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_multi_io.v b/test_regress/t/t_mem_multi_io.v index 5c1c09646..e94b9860a 100644 --- a/test_regress/t/t_mem_multi_io.v +++ b/test_regress/t/t_mem_multi_io.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_multi_io2.cpp b/test_regress/t/t_mem_multi_io2.cpp index ca53cd327..ea00ec3e6 100644 --- a/test_regress/t/t_mem_multi_io2.cpp +++ b/test_regress/t/t_mem_multi_io2.cpp @@ -1,7 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_mem_multi_io2.v b/test_regress/t/t_mem_multi_io2.v index 33d8cfa94..d43e65d2f 100644 --- a/test_regress/t/t_mem_multi_io2.v +++ b/test_regress/t/t_mem_multi_io2.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_mem_multi_io2_cc.pl b/test_regress/t/t_mem_multi_io2_cc.pl index 83a749623..afd7676a5 100755 --- a/test_regress/t/t_mem_multi_io2_cc.pl +++ b/test_regress/t/t_mem_multi_io2_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_mem_multi_io2_sc.pl b/test_regress/t/t_mem_multi_io2_sc.pl index e5d7f745b..7fa5e3930 100755 --- a/test_regress/t/t_mem_multi_io2_sc.pl +++ b/test_regress/t/t_mem_multi_io2_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_mem_multi_io3.cpp b/test_regress/t/t_mem_multi_io3.cpp index 2108bc73e..6191d051d 100644 --- a/test_regress/t/t_mem_multi_io3.cpp +++ b/test_regress/t/t_mem_multi_io3.cpp @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty. +// SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_mem_multi_io3.v b/test_regress/t/t_mem_multi_io3.v index 76878fb69..a7624c047 100644 --- a/test_regress/t/t_mem_multi_io3.v +++ b/test_regress/t/t_mem_multi_io3.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_mem_multi_io3_cc.pl b/test_regress/t/t_mem_multi_io3_cc.pl index 57f12c140..0e10b7948 100755 --- a/test_regress/t/t_mem_multi_io3_cc.pl +++ b/test_regress/t/t_mem_multi_io3_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_mem_multi_io3_sc.pl b/test_regress/t/t_mem_multi_io3_sc.pl index 1ecc7694f..cb1372c5e 100755 --- a/test_regress/t/t_mem_multi_io3_sc.pl +++ b/test_regress/t/t_mem_multi_io3_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_mem_multi_ref_bad.out b/test_regress/t/t_mem_multi_ref_bad.out index e12873d3e..d7aad1413 100644 --- a/test_regress/t/t_mem_multi_ref_bad.out +++ b/test_regress/t/t_mem_multi_ref_bad.out @@ -1,38 +1,38 @@ -%Error: t/t_mem_multi_ref_bad.v:14: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... In instance t - dimn[1:0] = 0; - ^ -%Error: t/t_mem_multi_ref_bad.v:14: Extracting 2 bits from only 1 bit number - : ... In instance t - dimn[1:0] = 0; - ^ -%Error: t/t_mem_multi_ref_bad.v:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... In instance t - dim0[1][1] = 0; - ^ -%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:15: Selection index out of range: 1:1 outside 0:0 - : ... In instance t - dim0[1][1] = 0; - ^ +%Error: t/t_mem_multi_ref_bad.v:15:11: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... In instance t + 15 | dimn[1:0] = 0; + | ^ +%Error: t/t_mem_multi_ref_bad.v:15:11: Extracting 2 bits from only 1 bit number + : ... In instance t + 15 | dimn[1:0] = 0; + | ^ +%Error: t/t_mem_multi_ref_bad.v:16:14: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... In instance t + 16 | dim0[1][1] = 0; + | ^ +%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:16:14: Selection index out of range: 1:1 outside 0:0 + : ... In instance t + 16 | dim0[1][1] = 0; + | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Error: t/t_mem_multi_ref_bad.v:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... In instance t - dim1[1][1][1] = 0; - ^ -%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:16: Selection index out of range: 1:1 outside 0:0 - : ... In instance t - dim1[1][1][1] = 0; - ^ -%Error: t/t_mem_multi_ref_bad.v:18: Illegal +: or -: select; type already selected, or bad dimension: data type is 'logic[1:0]$[1:0][1:0]' - : ... In instance t - dim2[0 +: 1][1] = 0; - ^ -%Error: t/t_mem_multi_ref_bad.v:22: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... In instance t - dim0nv[1][1] = 0; - ^ -%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:22: Selection index out of range: 1:1 outside 0:0 - : ... In instance t - dim0nv[1][1] = 0; - ^ +%Error: t/t_mem_multi_ref_bad.v:17:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... In instance t + 17 | dim1[1][1][1] = 0; + | ^ +%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:17:17: Selection index out of range: 1:1 outside 0:0 + : ... In instance t + 17 | dim1[1][1][1] = 0; + | ^ +%Error: t/t_mem_multi_ref_bad.v:19:11: Illegal +: or -: select; type already selected, or bad dimension: data type is 'logic[1:0]$[1:0][1:0]' + : ... In instance t + 19 | dim2[0 +: 1][1] = 0; + | ^ +%Error: t/t_mem_multi_ref_bad.v:23:16: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... In instance t + 23 | dim0nv[1][1] = 0; + | ^ +%Warning-SELRANGE: t/t_mem_multi_ref_bad.v:23:16: Selection index out of range: 1:1 outside 0:0 + : ... In instance t + 23 | dim0nv[1][1] = 0; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mem_multi_ref_bad.pl b/test_regress/t/t_mem_multi_ref_bad.pl index 113565b37..d334f74e1 100755 --- a/test_regress/t/t_mem_multi_ref_bad.pl +++ b/test_regress/t/t_mem_multi_ref_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_multi_ref_bad.v b/test_regress/t/t_mem_multi_ref_bad.v index 099640e3f..8cc98a544 100644 --- a/test_regress/t/t_mem_multi_ref_bad.v +++ b/test_regress/t/t_mem_multi_ref_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); reg dimn; diff --git a/test_regress/t/t_mem_multidim.pl b/test_regress/t/t_mem_multidim.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_multidim.pl +++ b/test_regress/t/t_mem_multidim.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_multidim.v b/test_regress/t/t_mem_multidim.v index 4cdbf8003..cee7bcd29 100644 --- a/test_regress/t/t_mem_multidim.v +++ b/test_regress/t/t_mem_multidim.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_multidim_Ox.pl b/test_regress/t/t_mem_multidim_Ox.pl index 31172a9fc..04c6294a4 100755 --- a/test_regress/t/t_mem_multidim_Ox.pl +++ b/test_regress/t/t_mem_multidim_Ox.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_multidim_trace.pl b/test_regress/t/t_mem_multidim_trace.pl index e337974fe..c448302fd 100755 --- a/test_regress/t/t_mem_multidim_trace.pl +++ b/test_regress/t/t_mem_multidim_trace.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_multiwire.pl b/test_regress/t/t_mem_multiwire.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_multiwire.pl +++ b/test_regress/t/t_mem_multiwire.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_multiwire.v b/test_regress/t/t_mem_multiwire.v index 016b141a5..663df9be3 100644 --- a/test_regress/t/t_mem_multiwire.v +++ b/test_regress/t/t_mem_multiwire.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_packed.pl b/test_regress/t/t_mem_packed.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_packed.pl +++ b/test_regress/t/t_mem_packed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_packed.v b/test_regress/t/t_mem_packed.v index 14b2fa19e..55ec2deca 100644 --- a/test_regress/t/t_mem_packed.v +++ b/test_regress/t/t_mem_packed.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_packed_assign.pl b/test_regress/t/t_mem_packed_assign.pl index ede6d329a..66f3a66cf 100755 --- a/test_regress/t/t_mem_packed_assign.pl +++ b/test_regress/t/t_mem_packed_assign.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_packed_assign.v b/test_regress/t/t_mem_packed_assign.v index 98613d822..98e5c9112 100644 --- a/test_regress/t/t_mem_packed_assign.v +++ b/test_regress/t/t_mem_packed_assign.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_packed_bad.out b/test_regress/t/t_mem_packed_bad.out index 33d55f0ce..f4dce2369 100644 --- a/test_regress/t/t_mem_packed_bad.out +++ b/test_regress/t/t_mem_packed_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_mem_packed_bad.v:26: CONST '28'h0' unexpected in assignment to unpacked array - ch04 <= 56'd0; - ^~~~~ +%Error: t/t_mem_packed_bad.v:27:32: CONST '28'h0' unexpected in assignment to unpacked array + 27 | ch04 <= 56'd0; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_mem_packed_bad.pl b/test_regress/t/t_mem_packed_bad.pl index 4ba881869..72a231777 100755 --- a/test_regress/t/t_mem_packed_bad.pl +++ b/test_regress/t/t_mem_packed_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_mem_packed_bad.v b/test_regress/t/t_mem_packed_bad.v index 28453ca75..386c671e9 100644 --- a/test_regress/t/t_mem_packed_bad.v +++ b/test_regress/t/t_mem_packed_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_shift.pl b/test_regress/t/t_mem_shift.pl index 99aa582e6..b1cd59018 100755 --- a/test_regress/t/t_mem_shift.pl +++ b/test_regress/t/t_mem_shift.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_shift.v b/test_regress/t/t_mem_shift.v index 9d2ee0f1e..9302f09e1 100644 --- a/test_regress/t/t_mem_shift.v +++ b/test_regress/t/t_mem_shift.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_slice.pl b/test_regress/t/t_mem_slice.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_slice.pl +++ b/test_regress/t/t_mem_slice.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_slice.v b/test_regress/t/t_mem_slice.v index 81815172c..fe084c1e3 100644 --- a/test_regress/t/t_mem_slice.v +++ b/test_regress/t/t_mem_slice.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_slice_bad.out b/test_regress/t/t_mem_slice_bad.out index 43b60c992..35f165b59 100644 --- a/test_regress/t/t_mem_slice_bad.out +++ b/test_regress/t/t_mem_slice_bad.out @@ -1,25 +1,25 @@ -%Error: t/t_mem_slice_bad.v:38: Slice selection index '[2:0]' outside data type's '[1:0]' - : ... In instance t - assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - ^ -%Error: t/t_mem_slice_bad.v:38: Slice selection index '[3:0]' outside data type's '[2:0]' - : ... In instance t - assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - ^ -%Error: t/t_mem_slice_bad.v:38: Slice selection index '[2:0]' outside data type's '[1:0]' - : ... In instance t - assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - ^ -%Error: t/t_mem_slice_bad.v:38: Slice selection index '[3:0]' outside data type's '[2:0]' - : ... In instance t - assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - ^ -%Error: t/t_mem_slice_bad.v:38: Slice selection index '[3:0]' outside data type's '[1:0]' - : ... In instance t - assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; - ^ -%Error: t/t_mem_slice_bad.v:50: Slice selection index '[8:0]' outside data type's '[7:0]' - : ... In instance t - active_command4[7:0] <= command_A4[8:0]; - ^ +%Error: t/t_mem_slice_bad.v:39:31: Slice selection index '[2:0]' outside data type's '[1:0]' + : ... In instance t + 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ +%Error: t/t_mem_slice_bad.v:39:36: Slice selection index '[3:0]' outside data type's '[2:0]' + : ... In instance t + 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ +%Error: t/t_mem_slice_bad.v:39:72: Slice selection index '[2:0]' outside data type's '[1:0]' + : ... In instance t + 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ +%Error: t/t_mem_slice_bad.v:39:77: Slice selection index '[3:0]' outside data type's '[2:0]' + : ... In instance t + 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ +%Error: t/t_mem_slice_bad.v:39:105: Slice selection index '[3:0]' outside data type's '[1:0]' + : ... In instance t + 39 | assign active_command3[1:0][2:0][3:0] = (use_AnB) ? command_A3[1:0][2:0][3:0] : command_B3[1:0][1:0][3:0]; + | ^ +%Error: t/t_mem_slice_bad.v:51:41: Slice selection index '[8:0]' outside data type's '[7:0]' + : ... In instance t + 51 | active_command4[7:0] <= command_A4[8:0]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mem_slice_bad.pl b/test_regress/t/t_mem_slice_bad.pl index 4ba881869..72a231777 100755 --- a/test_regress/t/t_mem_slice_bad.pl +++ b/test_regress/t/t_mem_slice_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_mem_slice_bad.v b/test_regress/t/t_mem_slice_bad.v index f14bc22e1..29aa8aaa9 100644 --- a/test_regress/t/t_mem_slice_bad.v +++ b/test_regress/t/t_mem_slice_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mem_slice_conc_bad.pl b/test_regress/t/t_mem_slice_conc_bad.pl index fd7324fbf..b3e120653 100755 --- a/test_regress/t/t_mem_slice_conc_bad.pl +++ b/test_regress/t/t_mem_slice_conc_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_mem_slice_conc_bad.v b/test_regress/t/t_mem_slice_conc_bad.v index 214fd647e..2f7118f1f 100644 --- a/test_regress/t/t_mem_slice_conc_bad.v +++ b/test_regress/t/t_mem_slice_conc_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // // bug354 diff --git a/test_regress/t/t_mem_slice_dtype_bad.out b/test_regress/t/t_mem_slice_dtype_bad.out index 92c5454e4..9968631a6 100644 --- a/test_regress/t/t_mem_slice_dtype_bad.out +++ b/test_regress/t/t_mem_slice_dtype_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_mem_slice_dtype_bad.v:22: ADD unexpected in assignment to unpacked array - completed_cnt[id] <= completed_cnt_dp + 1; - ^ +%Error: t/t_mem_slice_dtype_bad.v:23:45: ADD unexpected in assignment to unpacked array + 23 | completed_cnt[id] <= completed_cnt_dp + 1; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mem_slice_dtype_bad.pl b/test_regress/t/t_mem_slice_dtype_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_mem_slice_dtype_bad.pl +++ b/test_regress/t/t_mem_slice_dtype_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_slice_dtype_bad.v b/test_regress/t/t_mem_slice_dtype_bad.v index 71876b724..687b2957c 100644 --- a/test_regress/t/t_mem_slice_dtype_bad.v +++ b/test_regress/t/t_mem_slice_dtype_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Alex Solomatnikov. +// SPDX-License-Identifier: CC0-1.0 typedef logic [$clog2(26+1)-1:0] way_cnt_t; diff --git a/test_regress/t/t_mem_slot.cpp b/test_regress/t/t_mem_slot.cpp index 0ea8f4d55..dc6d2acba 100644 --- a/test_regress/t/t_mem_slot.cpp +++ b/test_regress/t/t_mem_slot.cpp @@ -1,4 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include diff --git a/test_regress/t/t_mem_slot.pl b/test_regress/t/t_mem_slot.pl index da60e8024..f2624d772 100755 --- a/test_regress/t/t_mem_slot.pl +++ b/test_regress/t/t_mem_slot.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_mem_slot.v b/test_regress/t/t_mem_slot.v index 0811b9a29..9c03ffac3 100644 --- a/test_regress/t/t_mem_slot.v +++ b/test_regress/t/t_mem_slot.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define RegDel 1 diff --git a/test_regress/t/t_mem_twoedge.pl b/test_regress/t/t_mem_twoedge.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mem_twoedge.pl +++ b/test_regress/t/t_mem_twoedge.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mem_twoedge.v b/test_regress/t/t_mem_twoedge.v index 69740401e..2a2af9faf 100644 --- a/test_regress/t/t_mem_twoedge.v +++ b/test_regress/t/t_mem_twoedge.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_metacmt_onoff.out b/test_regress/t/t_metacmt_onoff.out index e49dc4f6b..d1233b4d7 100644 --- a/test_regress/t/t_metacmt_onoff.out +++ b/test_regress/t/t_metacmt_onoff.out @@ -1,8 +1,8 @@ -%Warning-LITENDIAN: t/t_metacmt_onoff.v:5: Little bit endian vector: MSB < LSB of bit range: 0:1 - reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; - ^ +%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:8: Little bit endian vector: MSB < LSB of bit range: 0:1 + 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; + | ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. -%Warning-LITENDIAN: t/t_metacmt_onoff.v:5: Little bit endian vector: MSB < LSB of bit range: 0:3 - reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; - ^ +%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:109: Little bit endian vector: MSB < LSB of bit range: 0:3 + 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_metacmt_onoff.pl b/test_regress/t/t_metacmt_onoff.pl index 6ff127a73..4e13d3fc5 100755 --- a/test_regress/t/t_metacmt_onoff.pl +++ b/test_regress/t/t_metacmt_onoff.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_metacmt_onoff.v b/test_regress/t/t_metacmt_onoff.v index 4b0cda551..7b7c5735e 100644 --- a/test_regress/t/t_metacmt_onoff.v +++ b/test_regress/t/t_metacmt_onoff.v @@ -1,4 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; // Test turning on and off a message on the same line; only middle reg shouldn't warn diff --git a/test_regress/t/t_mod_dup_bad.out b/test_regress/t/t_mod_dup_bad.out index e0a5d6893..87b31425b 100644 --- a/test_regress/t/t_mod_dup_bad.out +++ b/test_regress/t/t_mod_dup_bad.out @@ -1,16 +1,16 @@ -%Warning-MODDUP: t/t_mod_dup_bad.v:13: Duplicate declaration of module: 'a' -module a(); - ^ - t/t_mod_dup_bad.v:6: ... Location of original declaration -module a(); - ^ +%Warning-MODDUP: t/t_mod_dup_bad.v:14:8: Duplicate declaration of module: 'a' + 14 | module a(); + | ^ + t/t_mod_dup_bad.v:7:8: ... Location of original declaration + 7 | module a(); + | ^ ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. -%Warning-MULTITOP: t/t_mod_dup_bad.v:16: Multiple top level modules - : ... Suggest see manual; fix the duplicates, or use --top-module to select top. - : ... Top module 'test' -module test(); - ^~~~ - : ... Top module 'b' -module b(); - ^ +%Warning-MULTITOP: t/t_mod_dup_bad.v:17:8: Multiple top level modules + : ... Suggest see manual; fix the duplicates, or use --top-module to select top. + : ... Top module 'test' + 10 | module test(); + | ^~~~ + : ... Top module 'b' + 17 | module b(); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mod_dup_bad.pl b/test_regress/t/t_mod_dup_bad.pl index 856b43919..527a39935 100755 --- a/test_regress/t/t_mod_dup_bad.pl +++ b/test_regress/t/t_mod_dup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_mod_dup_bad.v b/test_regress/t/t_mod_dup_bad.v index 296f098ac..ad2b678af 100644 --- a/test_regress/t/t_mod_dup_bad.v +++ b/test_regress/t/t_mod_dup_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module a(); endmodule diff --git a/test_regress/t/t_mod_dup_ign.pl b/test_regress/t/t_mod_dup_ign.pl index cc4c85b1f..193a62348 100755 --- a/test_regress/t/t_mod_dup_ign.pl +++ b/test_regress/t/t_mod_dup_ign.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_mod_dup_ign.v b/test_regress/t/t_mod_dup_ign.v index 7283d0889..8b06b4457 100644 --- a/test_regress/t/t_mod_dup_ign.v +++ b/test_regress/t/t_mod_dup_ign.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; sub sub (); diff --git a/test_regress/t/t_mod_interface_array0.pl b/test_regress/t/t_mod_interface_array0.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mod_interface_array0.pl +++ b/test_regress/t/t_mod_interface_array0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_interface_array0.v b/test_regress/t/t_mod_interface_array0.v index 30a2a2ad0..00c600b91 100644 --- a/test_regress/t/t_mod_interface_array0.v +++ b/test_regress/t/t_mod_interface_array0.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 parameter N = 4; diff --git a/test_regress/t/t_mod_interface_array0_noinl.pl b/test_regress/t/t_mod_interface_array0_noinl.pl index 9db4bf967..ec6f350af 100755 --- a/test_regress/t/t_mod_interface_array0_noinl.pl +++ b/test_regress/t/t_mod_interface_array0_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_interface_array1.pl b/test_regress/t/t_mod_interface_array1.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mod_interface_array1.pl +++ b/test_regress/t/t_mod_interface_array1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_interface_array1.v b/test_regress/t/t_mod_interface_array1.v index 0ae3acb64..f524a79a6 100644 --- a/test_regress/t/t_mod_interface_array1.v +++ b/test_regress/t/t_mod_interface_array1.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 parameter N = 4; diff --git a/test_regress/t/t_mod_interface_array1_noinl.pl b/test_regress/t/t_mod_interface_array1_noinl.pl index a08606902..c13ae3a86 100755 --- a/test_regress/t/t_mod_interface_array1_noinl.pl +++ b/test_regress/t/t_mod_interface_array1_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_interface_array2.pl b/test_regress/t/t_mod_interface_array2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mod_interface_array2.pl +++ b/test_regress/t/t_mod_interface_array2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_interface_array2.v b/test_regress/t/t_mod_interface_array2.v index 2ff66d682..0c8101c6b 100644 --- a/test_regress/t/t_mod_interface_array2.v +++ b/test_regress/t/t_mod_interface_array2.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 parameter N = 4; // verilator lint_off LITENDIAN diff --git a/test_regress/t/t_mod_interface_array2_noinl.pl b/test_regress/t/t_mod_interface_array2_noinl.pl index 588fdf3fb..15a876518 100755 --- a/test_regress/t/t_mod_interface_array2_noinl.pl +++ b/test_regress/t/t_mod_interface_array2_noinl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_interface_array3.out b/test_regress/t/t_mod_interface_array3.out index ad92220e4..80bde9afc 100644 --- a/test_regress/t/t_mod_interface_array3.out +++ b/test_regress/t/t_mod_interface_array3.out @@ -1,7 +1,7 @@ -%Error: t/t_mod_interface_array3.v:24: Unsupported: Multidimensional cells/interfaces. - a_if iface [2:0][1:0]; - ^ -%Error: t/t_mod_interface_array3.v:26: Unsupported: Multidimensional cells/interfaces. - sub i_sub[2:0][1:0] (.s(str)); - ^ +%Error: t/t_mod_interface_array3.v:25:20: Unsupported: Multidimensional cells/interfaces. + 25 | a_if iface [2:0][1:0]; + | ^ +%Error: t/t_mod_interface_array3.v:27:18: Unsupported: Multidimensional cells/interfaces. + 27 | sub i_sub[2:0][1:0] (.s(str)); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_mod_interface_array3.pl b/test_regress/t/t_mod_interface_array3.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_mod_interface_array3.pl +++ b/test_regress/t/t_mod_interface_array3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_interface_array3.v b/test_regress/t/t_mod_interface_array3.v index 6e0ab4aef..603fb3588 100644 --- a/test_regress/t/t_mod_interface_array3.v +++ b/test_regress/t/t_mod_interface_array3.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork. +// SPDX-License-Identifier: CC0-1.0 `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_mod_longname.pl b/test_regress/t/t_mod_longname.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mod_longname.pl +++ b/test_regress/t/t_mod_longname.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_longname.v b/test_regress/t/t_mod_longname.v index 8198fda02..777f25193 100644 --- a/test_regress/t/t_mod_longname.v +++ b/test_regress/t/t_mod_longname.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 `define LONG_NAME_MOD modlongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie `define LONG_NAME_SUB sublongnameiuqyrewewriqyewroiquyweriuqyewriuyewrioryqoiewyriuewyrqrqioeyriuqyewriuqyeworqiurewyqoiuewyrqiuewoyewriuoeyqiuewryqiuewyroiqyewiuryqeiuwryuqiyreoiqyewiuryqewiruyqiuewyroiuqyewroiuyqewoiryqiewuyrqiuewyroqiyewriuqyewrewqroiuyqiuewyriuqyewroiqyewroiquewyriuqyewroiqewyriuqewyroiqyewroiyewoiuryqoiewyriuqyewiuryqoierwyqoiuewyrewoiuyqroiewuryewurqyoiweyrqiuewyreqwroiyweroiuyqweoiuryqiuewyroiuqyroie diff --git a/test_regress/t/t_mod_nomod.pl b/test_regress/t/t_mod_nomod.pl index 379b79eb8..a43fd86d3 100755 --- a/test_regress/t/t_mod_nomod.pl +++ b/test_regress/t/t_mod_nomod.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_mod_nomod.v b/test_regress/t/t_mod_nomod.v index bb6c64274..e19757ef6 100644 --- a/test_regress/t/t_mod_nomod.v +++ b/test_regress/t/t_mod_nomod.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug 1381 diff --git a/test_regress/t/t_mod_recurse.pl b/test_regress/t/t_mod_recurse.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mod_recurse.pl +++ b/test_regress/t/t_mod_recurse.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_recurse.v b/test_regress/t/t_mod_recurse.v index 031e97f6e..096843aad 100644 --- a/test_regress/t/t_mod_recurse.v +++ b/test_regress/t/t_mod_recurse.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Sean Moore. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_mod_recurse1.pl b/test_regress/t/t_mod_recurse1.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_mod_recurse1.pl +++ b/test_regress/t/t_mod_recurse1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_recurse1.v b/test_regress/t/t_mod_recurse1.v index ae493982f..785e38869 100644 --- a/test_regress/t/t_mod_recurse1.v +++ b/test_regress/t/t_mod_recurse1.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Sean Moore. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_mod_uselib.pl b/test_regress/t/t_mod_uselib.pl index a1d77d628..b29350dd1 100755 --- a/test_regress/t/t_mod_uselib.pl +++ b/test_regress/t/t_mod_uselib.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_mod_uselib.v b/test_regress/t/t_mod_uselib.v index 8a97b958e..f51299a04 100644 --- a/test_regress/t/t_mod_uselib.v +++ b/test_regress/t/t_mod_uselib.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); // // `uselib {dir= | file= | libext= | lib= diff --git a/test_regress/t/t_multitop1.pl b/test_regress/t/t_multitop1.pl index ecd47aaf6..446d729c9 100755 --- a/test_regress/t/t_multitop1.pl +++ b/test_regress/t/t_multitop1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_multitop1.v b/test_regress/t/t_multitop1.v index 1eaaea718..a89daf8a9 100644 --- a/test_regress/t/t_multitop1.v +++ b/test_regress/t/t_multitop1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_multitop1s.v b/test_regress/t/t_multitop1s.v index 2fc35f055..34282dd67 100644 --- a/test_regress/t/t_multitop1s.v +++ b/test_regress/t/t_multitop1s.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_multitop1s; initial $display("In '%m'"); diff --git a/test_regress/t/t_multitop_sig.cpp b/test_regress/t/t_multitop_sig.cpp index d631a3738..e548d25ad 100644 --- a/test_regress/t/t_multitop_sig.cpp +++ b/test_regress/t/t_multitop_sig.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include diff --git a/test_regress/t/t_multitop_sig.pl b/test_regress/t/t_multitop_sig.pl index 6f98c4cda..ed1fdcbc0 100755 --- a/test_regress/t/t_multitop_sig.pl +++ b/test_regress/t/t_multitop_sig.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_multitop_sig.v b/test_regress/t/t_multitop_sig.v index cc20c3287..4f1d34338 100644 --- a/test_regress/t/t_multitop_sig.v +++ b/test_regress/t/t_multitop_sig.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module a(in, out); input in; diff --git a/test_regress/t/t_multitop_sig_bad.out b/test_regress/t/t_multitop_sig_bad.out index 02a6e508c..b905115db 100644 --- a/test_regress/t/t_multitop_sig_bad.out +++ b/test_regress/t/t_multitop_sig_bad.out @@ -1,13 +1,13 @@ -%Warning-MULTITOP: t/t_multitop_sig.v:14: Multiple top level modules - : ... Suggest see manual; fix the duplicates, or use --top-module to select top. +%Warning-MULTITOP: t/t_multitop_sig.v:15:8: Multiple top level modules + : ... Suggest see manual; fix the duplicates, or use --top-module to select top. ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. - : ... Top module 'a' -module a(in, out); - ^ - : ... Top module 'b' -module b(in, out); - ^ - : ... Top module 'c' -module c(uniq_in, uniq_out); - ^ + : ... Top module 'a' + 7 | module a(in, out); + | ^ + : ... Top module 'b' + 15 | module b(in, out); + | ^ + : ... Top module 'c' + 23 | module c(uniq_in, uniq_out); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_multitop_sig_bad.pl b/test_regress/t/t_multitop_sig_bad.pl index 24556312b..baa0eb8f6 100755 --- a/test_regress/t/t_multitop_sig_bad.pl +++ b/test_regress/t/t_multitop_sig_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_noprot_lib.pl b/test_regress/t/t_noprot_lib.pl index f1cf7c246..0f333cce1 100755 --- a/test_regress/t/t_noprot_lib.pl +++ b/test_regress/t/t_noprot_lib.pl @@ -5,10 +5,11 @@ unshift(@ARGV, "--trace"); if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios( vlt => 1, diff --git a/test_regress/t/t_number_bad.out b/test_regress/t/t_number_bad.out index 41224dd39..b88db4a1f 100644 --- a/test_regress/t/t_number_bad.out +++ b/test_regress/t/t_number_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_number_bad.v:8: Number is missing value digits: 32'd - parameter integer FOO2 = 32'd-6; - ^~~~ -%Error: t/t_number_bad.v:9: Number is missing value digits: 32'd - parameter integer FOO3 = 32'd; - ^~~~ -%Error: t/t_number_bad.v:10: Number is missing value digits: 32'h - parameter integer FOO4 = 32'h; - ^~~~ +%Error: t/t_number_bad.v:9:29: Number is missing value digits: 32'd + 9 | parameter integer FOO2 = 32'd-6; + | ^~~~ +%Error: t/t_number_bad.v:10:29: Number is missing value digits: 32'd + 10 | parameter integer FOO3 = 32'd; + | ^~~~ +%Error: t/t_number_bad.v:11:29: Number is missing value digits: 32'h + 11 | parameter integer FOO4 = 32'h; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_number_bad.pl b/test_regress/t/t_number_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_number_bad.pl +++ b/test_regress/t/t_number_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_number_bad.v b/test_regress/t/t_number_bad.v index b269347fd..b2c1ae547 100644 --- a/test_regress/t/t_number_bad.v +++ b/test_regress/t/t_number_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Test of select from constant // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_optm_if_array.pl b/test_regress/t/t_optm_if_array.pl index 37ce368a9..0a7853f4a 100755 --- a/test_regress/t/t_optm_if_array.pl +++ b/test_regress/t/t_optm_if_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_optm_if_array.v b/test_regress/t/t_optm_if_array.v index bfcd1f03e..5be6aae1d 100644 --- a/test_regress/t/t_optm_if_array.v +++ b/test_regress/t/t_optm_if_array.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_optm_redor.pl b/test_regress/t/t_optm_redor.pl index 37ce368a9..0a7853f4a 100755 --- a/test_regress/t/t_optm_redor.pl +++ b/test_regress/t/t_optm_redor.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_optm_redor.v b/test_regress/t/t_optm_redor.v index b82e58b13..11df0a68f 100644 --- a/test_regress/t/t_optm_redor.v +++ b/test_regress/t/t_optm_redor.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order.pl b/test_regress/t/t_order.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_order.pl +++ b/test_regress/t/t_order.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order.v b/test_regress/t/t_order.v index 84fbedad8..3613c85c9 100644 --- a/test_regress/t/t_order.v +++ b/test_regress/t/t_order.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order_2d.pl b/test_regress/t/t_order_2d.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_order_2d.pl +++ b/test_regress/t/t_order_2d.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order_2d.v b/test_regress/t/t_order_2d.v index 35f0c35dd..84e45021b 100644 --- a/test_regress/t/t_order_2d.v +++ b/test_regress/t/t_order_2d.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order_a.v b/test_regress/t/t_order_a.v index 199272dcc..2cad003f6 100644 --- a/test_regress/t/t_order_a.v +++ b/test_regress/t/t_order_a.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_order_a (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_order_b.v b/test_regress/t/t_order_b.v index c19f566e2..b941580ae 100644 --- a/test_regress/t/t_order_b.v +++ b/test_regress/t/t_order_b.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_order_b (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_order_clkinst.pl b/test_regress/t/t_order_clkinst.pl index 9eb9fc47d..b7178dc92 100755 --- a/test_regress/t/t_order_clkinst.pl +++ b/test_regress/t/t_order_clkinst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order_clkinst.v b/test_regress/t/t_order_clkinst.v index a1ed5559a..4897d540a 100644 --- a/test_regress/t/t_order_clkinst.v +++ b/test_regress/t/t_order_clkinst.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order_clkinst_bad.out b/test_regress/t/t_order_clkinst_bad.out index 79330f780..bd4b51c51 100644 --- a/test_regress/t/t_order_clkinst_bad.out +++ b/test_regress/t/t_order_clkinst_bad.out @@ -1,23 +1,23 @@ -%Warning-IMPERFECTSCH: t/t_order_clkinst.v:17: Imperfect scheduling of variable: 't.c1_start' - reg c1_start; initial c1_start = 0; - ^~~~~~~~ +%Warning-IMPERFECTSCH: t/t_order_clkinst.v:18:16: Imperfect scheduling of variable: 't.c1_start' + 18 | reg c1_start; initial c1_start = 0; + | ^~~~~~~~ ... Use "/* verilator lint_off IMPERFECTSCH */" and lint_on around source to disable this message. -%Warning-IMPERFECTSCH: t/t_order_clkinst.v:18: Imperfect scheduling of variable: 't.c1_count' - wire [31:0] c1_count; - ^~~~~~~~ -%Warning-IMPERFECTSCH: t/t_order_clkinst.v:22: Imperfect scheduling of variable: 't.s2_count' - wire [31:0] s2_count; - ^~~~~~~~ -%Warning-IMPERFECTSCH: t/t_order_clkinst.v:26: Imperfect scheduling of variable: 't.c3_count' - wire [31:0] c3_count; - ^~~~~~~~ -%Warning-IMPERFECTSCH: t/t_order_clkinst.v:70: Imperfect scheduling of variable: 't.c1.runner' - reg [31:0] runnerm1, runner; initial runner = 0; - ^~~~~~ -%Warning-IMPERFECTSCH: t/t_order_clkinst.v:99: Imperfect scheduling of variable: 't.s2.runner' - reg [31:0] runnerm1, runner; initial runner = 0; - ^~~~~~ -%Warning-IMPERFECTSCH: t/t_order_clkinst.v:70: Imperfect scheduling of variable: 't.c3.runner' - reg [31:0] runnerm1, runner; initial runner = 0; - ^~~~~~ +%Warning-IMPERFECTSCH: t/t_order_clkinst.v:19:16: Imperfect scheduling of variable: 't.c1_count' + 19 | wire [31:0] c1_count; + | ^~~~~~~~ +%Warning-IMPERFECTSCH: t/t_order_clkinst.v:23:16: Imperfect scheduling of variable: 't.s2_count' + 23 | wire [31:0] s2_count; + | ^~~~~~~~ +%Warning-IMPERFECTSCH: t/t_order_clkinst.v:27:16: Imperfect scheduling of variable: 't.c3_count' + 27 | wire [31:0] c3_count; + | ^~~~~~~~ +%Warning-IMPERFECTSCH: t/t_order_clkinst.v:71:28: Imperfect scheduling of variable: 't.c1.runner' + 71 | reg [31:0] runnerm1, runner; initial runner = 0; + | ^~~~~~ +%Warning-IMPERFECTSCH: t/t_order_clkinst.v:100:28: Imperfect scheduling of variable: 't.s2.runner' + 100 | reg [31:0] runnerm1, runner; initial runner = 0; + | ^~~~~~ +%Warning-IMPERFECTSCH: t/t_order_clkinst.v:71:28: Imperfect scheduling of variable: 't.c3.runner' + 71 | reg [31:0] runnerm1, runner; initial runner = 0; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_order_clkinst_bad.pl b/test_regress/t/t_order_clkinst_bad.pl index 62ff8731a..2617e225b 100755 --- a/test_regress/t/t_order_clkinst_bad.pl +++ b/test_regress/t/t_order_clkinst_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order_comboclkloop.pl b/test_regress/t/t_order_comboclkloop.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_order_comboclkloop.pl +++ b/test_regress/t/t_order_comboclkloop.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order_comboclkloop.v b/test_regress/t/t_order_comboclkloop.v index e750675a0..b6d6ac295 100644 --- a/test_regress/t/t_order_comboclkloop.v +++ b/test_regress/t/t_order_comboclkloop.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order_comboloop.pl b/test_regress/t/t_order_comboloop.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_order_comboloop.pl +++ b/test_regress/t/t_order_comboloop.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order_comboloop.v b/test_regress/t/t_order_comboloop.v index 0d98f10ce..9056a08d8 100644 --- a/test_regress/t/t_order_comboloop.v +++ b/test_regress/t/t_order_comboloop.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order_doubleloop.pl b/test_regress/t/t_order_doubleloop.pl index 1bb3331e9..a8a66f6ba 100755 --- a/test_regress/t/t_order_doubleloop.pl +++ b/test_regress/t/t_order_doubleloop.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order_doubleloop.v b/test_regress/t/t_order_doubleloop.v index d8e172901..3b61fbedc 100644 --- a/test_regress/t/t_order_doubleloop.v +++ b/test_regress/t/t_order_doubleloop.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order_first.pl b/test_regress/t/t_order_first.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_order_first.pl +++ b/test_regress/t/t_order_first.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order_first.v b/test_regress/t/t_order_first.v index 645d1333f..5fe4d1c54 100644 --- a/test_regress/t/t_order_first.v +++ b/test_regress/t/t_order_first.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order_loop_bad.pl b/test_regress/t/t_order_loop_bad.pl index c7478bafa..d73ccbb11 100755 --- a/test_regress/t/t_order_loop_bad.pl +++ b/test_regress/t/t_order_loop_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); @@ -14,9 +15,9 @@ lint( # Can't use expect_filename here as unstable output expect => '%Error: Circular logic when ordering code .* - *t/t_order_loop_bad.v:\d+: + Example path: ALWAYS - *t/t_order_loop_bad.v:\d+: + Example path: t.ready - *t/t_order_loop_bad.v:\d+: + Example path: ACTIVE + *t/t_order_loop_bad.v:\d+:\d+: + Example path: ALWAYS + *t/t_order_loop_bad.v:\d+:\d+: + Example path: t.ready + *t/t_order_loop_bad.v:\d+:\d+: + Example path: ACTIVE .*', ); diff --git a/test_regress/t/t_order_loop_bad.v b/test_regress/t/t_order_loop_bad.v index 6b6b51a41..9b4c0175e 100644 --- a/test_regress/t/t_order_loop_bad.v +++ b/test_regress/t/t_order_loop_bad.v @@ -8,6 +8,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order_multialways.pl b/test_regress/t/t_order_multialways.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_order_multialways.pl +++ b/test_regress/t/t_order_multialways.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order_multialways.v b/test_regress/t/t_order_multialways.v index 23e1626d1..63f75c5eb 100644 --- a/test_regress/t/t_order_multialways.v +++ b/test_regress/t/t_order_multialways.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_order_multidriven.cpp b/test_regress/t/t_order_multidriven.cpp index 7e4f76744..7a7e3adc7 100644 --- a/test_regress/t/t_order_multidriven.cpp +++ b/test_regress/t/t_order_multidriven.cpp @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Ted Campbell. +// SPDX-License-Identifier: CC0-1.0 #include "Vt_order_multidriven.h" #include "verilated.h" diff --git a/test_regress/t/t_order_multidriven.pl b/test_regress/t/t_order_multidriven.pl index 7881a8cb4..a2245ee51 100755 --- a/test_regress/t/t_order_multidriven.pl +++ b/test_regress/t/t_order_multidriven.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_order_multidriven.v b/test_regress/t/t_order_multidriven.v index ebe854786..b91f81797 100644 --- a/test_regress/t/t_order_multidriven.v +++ b/test_regress/t/t_order_multidriven.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Ted Campbell. +// SPDX-License-Identifier: CC0-1.0 //With MULTI_CLK defined shows bug, without it is hidden `define MULTI_CLK diff --git a/test_regress/t/t_order_quad.cpp b/test_regress/t/t_order_quad.cpp index bfd0920e1..700e18ca5 100644 --- a/test_regress/t/t_order_quad.cpp +++ b/test_regress/t/t_order_quad.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include "Vt_order_quad.h" diff --git a/test_regress/t/t_order_quad.pl b/test_regress/t/t_order_quad.pl index 66b07eadf..04b9aeb1c 100755 --- a/test_regress/t/t_order_quad.pl +++ b/test_regress/t/t_order_quad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_order_quad.v b/test_regress/t/t_order_quad.v index 60635c549..02a873239 100644 --- a/test_regress/t/t_order_quad.v +++ b/test_regress/t/t_order_quad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug 762 module t(a0, y); diff --git a/test_regress/t/t_order_wireloop.pl b/test_regress/t/t_order_wireloop.pl index 6dc17910d..0fb5aa1b3 100755 --- a/test_regress/t/t_order_wireloop.pl +++ b/test_regress/t/t_order_wireloop.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2005 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2005 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -15,7 +16,7 @@ compile( # However we no longer gate optimize this # Can't use expect_filename here as unstable output expect => -'%Warning-UNOPT: t/t_order_wireloop.v:\d+: Signal unoptimizable: Feedback to public clock or circular logic: \'bar\' +'%Warning-UNOPT: t/t_order_wireloop.v:\d+:\d+: Signal unoptimizable: Feedback to public clock or circular logic: \'bar\' ', ); diff --git a/test_regress/t/t_order_wireloop.v b/test_regress/t/t_order_wireloop.v index b1156cf82..a98131e99 100644 --- a/test_regress/t/t_order_wireloop.v +++ b/test_regress/t/t_order_wireloop.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_package.pl b/test_regress/t/t_package.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_package.pl +++ b/test_regress/t/t_package.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_package.v b/test_regress/t/t_package.v index 3273062c2..12bd01ab6 100644 --- a/test_regress/t/t_package.v +++ b/test_regress/t/t_package.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 typedef int unit_type_t; diff --git a/test_regress/t/t_package_abs.pl b/test_regress/t/t_package_abs.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_package_abs.pl +++ b/test_regress/t/t_package_abs.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_package_abs.v b/test_regress/t/t_package_abs.v index 00c0f42e5..b91b45a97 100644 --- a/test_regress/t/t_package_abs.v +++ b/test_regress/t/t_package_abs.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // see bug491 diff --git a/test_regress/t/t_package_ddecl.pl b/test_regress/t/t_package_ddecl.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_package_ddecl.pl +++ b/test_regress/t/t_package_ddecl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_package_ddecl.v b/test_regress/t/t_package_ddecl.v index 310ff2bb3..e6b4ab541 100644 --- a/test_regress/t/t_package_ddecl.v +++ b/test_regress/t/t_package_ddecl.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // see bug 474 package functions; diff --git a/test_regress/t/t_package_dimport.pl b/test_regress/t/t_package_dimport.pl index bff7cfb29..02efadae6 100755 --- a/test_regress/t/t_package_dimport.pl +++ b/test_regress/t/t_package_dimport.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_package_dimport.v b/test_regress/t/t_package_dimport.v index 2305c5820..8d8baddb0 100644 --- a/test_regress/t/t_package_dimport.v +++ b/test_regress/t/t_package_dimport.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 package defs; function automatic integer max; diff --git a/test_regress/t/t_package_dot.pl b/test_regress/t/t_package_dot.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_package_dot.pl +++ b/test_regress/t/t_package_dot.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_package_dot.v b/test_regress/t/t_package_dot.v index b848b228e..fe345dfe8 100644 --- a/test_regress/t/t_package_dot.v +++ b/test_regress/t/t_package_dot.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 package pkg; typedef struct packed { diff --git a/test_regress/t/t_package_enum.pl b/test_regress/t/t_package_enum.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_package_enum.pl +++ b/test_regress/t/t_package_enum.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_package_enum.v b/test_regress/t/t_package_enum.v index c3402e574..97ddf0255 100644 --- a/test_regress/t/t_package_enum.v +++ b/test_regress/t/t_package_enum.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 package pkg; typedef enum bit [1:0] diff --git a/test_regress/t/t_package_export.pl b/test_regress/t/t_package_export.pl index 939096741..8fe275fdc 100755 --- a/test_regress/t/t_package_export.pl +++ b/test_regress/t/t_package_export.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vcs} and unsupported("VCS unsupported"); diff --git a/test_regress/t/t_package_export.v b/test_regress/t/t_package_export.v index e8dbece18..4118f94ac 100644 --- a/test_regress/t/t_package_export.v +++ b/test_regress/t/t_package_export.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Jeremy Bennett +// without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 // see bug 591 diff --git a/test_regress/t/t_package_export_bad.out b/test_regress/t/t_package_export_bad.out index 54980b7c8..94ff0920b 100644 --- a/test_regress/t/t_package_export_bad.out +++ b/test_regress/t/t_package_export_bad.out @@ -1,25 +1,25 @@ -%Error: t/t_package_export.v:56: Can't find definition of scope/variable: 'PARAM2' - : ... Suggested alternative: 'PARAM1' - reg [pkg11::PARAM2 : 0] bus12; - ^~~~~~ -%Error: t/t_package_export.v:57: Can't find definition of scope/variable: 'PARAM3' - : ... Suggested alternative: 'PARAM1' - reg [pkg11::PARAM3 : 0] bus13; - ^~~~~~ -%Error: t/t_package_export.v:60: Can't find definition of scope/variable: 'PARAM2' - : ... Suggested alternative: 'PARAM1' - reg [pkg21::PARAM2 : 0] bus22; - ^~~~~~ -%Error: t/t_package_export.v:61: Can't find definition of scope/variable: 'PARAM3' - : ... Suggested alternative: 'PARAM1' - reg [pkg21::PARAM3 : 0] bus23; - ^~~~~~ -%Error: t/t_package_export.v:64: Can't find definition of scope/variable: 'PARAM2' - : ... Suggested alternative: 'PARAM1' - reg [pkg31::PARAM2 : 0] bus32; - ^~~~~~ -%Error: t/t_package_export.v:65: Can't find definition of scope/variable: 'PARAM3' - : ... Suggested alternative: 'PARAM1' - reg [pkg31::PARAM3 : 0] bus33; - ^~~~~~ +%Error: t/t_package_export.v:57:16: Can't find definition of scope/variable: 'PARAM2' + : ... Suggested alternative: 'PARAM1' + 57 | reg [pkg11::PARAM2 : 0] bus12; + | ^~~~~~ +%Error: t/t_package_export.v:58:16: Can't find definition of scope/variable: 'PARAM3' + : ... Suggested alternative: 'PARAM1' + 58 | reg [pkg11::PARAM3 : 0] bus13; + | ^~~~~~ +%Error: t/t_package_export.v:61:16: Can't find definition of scope/variable: 'PARAM2' + : ... Suggested alternative: 'PARAM1' + 61 | reg [pkg21::PARAM2 : 0] bus22; + | ^~~~~~ +%Error: t/t_package_export.v:62:16: Can't find definition of scope/variable: 'PARAM3' + : ... Suggested alternative: 'PARAM1' + 62 | reg [pkg21::PARAM3 : 0] bus23; + | ^~~~~~ +%Error: t/t_package_export.v:65:16: Can't find definition of scope/variable: 'PARAM2' + : ... Suggested alternative: 'PARAM1' + 65 | reg [pkg31::PARAM2 : 0] bus32; + | ^~~~~~ +%Error: t/t_package_export.v:66:16: Can't find definition of scope/variable: 'PARAM3' + : ... Suggested alternative: 'PARAM1' + 66 | reg [pkg31::PARAM3 : 0] bus33; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_package_export_bad.pl b/test_regress/t/t_package_export_bad.pl index 506f5b1b3..ebec1a74f 100755 --- a/test_regress/t/t_package_export_bad.pl +++ b/test_regress/t/t_package_export_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_package_param.pl b/test_regress/t/t_package_param.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_package_param.pl +++ b/test_regress/t/t_package_param.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_package_param.v b/test_regress/t/t_package_param.v index fe4e492f8..5fa2e81fc 100644 --- a/test_regress/t/t_package_param.v +++ b/test_regress/t/t_package_param.v @@ -5,7 +5,8 @@ // below is valid SystemVerilog. // // This file ONLY is placed into the Public Domain, for any use, without -// warranty, 2013 by Jie Xu +// warranty, 2013 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 package defs; parameter NUMBER = 8; diff --git a/test_regress/t/t_package_twodeep.pl b/test_regress/t/t_package_twodeep.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_package_twodeep.pl +++ b/test_regress/t/t_package_twodeep.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_package_twodeep.v b/test_regress/t/t_package_twodeep.v index 3008e1cfd..1f11482de 100644 --- a/test_regress/t/t_package_twodeep.v +++ b/test_regress/t/t_package_twodeep.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett +// SPDX-License-Identifier: CC0-1.0 // see bug 591 diff --git a/test_regress/t/t_package_verb.pl b/test_regress/t/t_package_verb.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_package_verb.pl +++ b/test_regress/t/t_package_verb.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_package_verb.v b/test_regress/t/t_package_verb.v index bc3191d07..e0fbdb094 100644 --- a/test_regress/t/t_package_verb.v +++ b/test_regress/t/t_package_verb.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug474 package verb_pkg; diff --git a/test_regress/t/t_packed_concat.v b/test_regress/t/t_packed_concat.v index 30cf7bbac..39d97a672 100644 --- a/test_regress/t/t_packed_concat.v +++ b/test_regress/t/t_packed_concat.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_packed_concat_bad.out b/test_regress/t/t_packed_concat_bad.out index d7f88ead6..3bbac473d 100644 --- a/test_regress/t/t_packed_concat_bad.out +++ b/test_regress/t/t_packed_concat_bad.out @@ -1,14 +1,14 @@ -%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:16: Unsized numbers/parameters not allowed in replications. - : ... In instance t - localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; - ^~~~~ +%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:17:47: Unsized numbers/parameters not allowed in replications. + : ... In instance t + 17 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; + | ^~~~~ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. -%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:17: Unsized numbers/parameters not allowed in concatenations. - : ... In instance t - localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; - ^~~~~ -%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:17: Unsized numbers/parameters not allowed in replications. - : ... In instance t - localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; - ^ +%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:46: Unsized numbers/parameters not allowed in concatenations. + : ... In instance t + 18 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; + | ^~~~~ +%Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:60: Unsized numbers/parameters not allowed in replications. + : ... In instance t + 18 | localparam bit_int_t [1:0] count_bitsc = {$bits(count_t), $bits(count_t)}; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_packed_concat_bad.pl b/test_regress/t/t_packed_concat_bad.pl index 46d54cf79..8bc59ae60 100755 --- a/test_regress/t/t_packed_concat_bad.pl +++ b/test_regress/t/t_packed_concat_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_packed_concat_bad.v b/test_regress/t/t_packed_concat_bad.v index fcae999d3..ee0e3fc07 100644 --- a/test_regress/t/t_packed_concat_bad.v +++ b/test_regress/t/t_packed_concat_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param.pl b/test_regress/t/t_param.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param.pl +++ b/test_regress/t/t_param.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param.v b/test_regress/t/t_param.v index 8418cf417..9f84db5cf 100644 --- a/test_regress/t/t_param.v +++ b/test_regress/t/t_param.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_array.pl b/test_regress/t/t_param_array.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_array.pl +++ b/test_regress/t/t_param_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_array.v b/test_regress/t/t_param_array.v index 7084c6581..2a58a1318 100644 --- a/test_regress/t/t_param_array.v +++ b/test_regress/t/t_param_array.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_param_array2.pl b/test_regress/t/t_param_array2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_array2.pl +++ b/test_regress/t/t_param_array2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_array2.v b/test_regress/t/t_param_array2.v index 93bde7de4..c4b61c398 100644 --- a/test_regress/t/t_param_array2.v +++ b/test_regress/t/t_param_array2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; localparam int c[4] = '{5, 6, 7, 8}; diff --git a/test_regress/t/t_param_array3.pl b/test_regress/t/t_param_array3.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_array3.pl +++ b/test_regress/t/t_param_array3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_array3.v b/test_regress/t/t_param_array3.v index 72cd4afac..fb6926365 100644 --- a/test_regress/t/t_param_array3.v +++ b/test_regress/t/t_param_array3.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; parameter int SIZES [3:0] = '{1,2,3,4}; diff --git a/test_regress/t/t_param_array4.pl b/test_regress/t/t_param_array4.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_array4.pl +++ b/test_regress/t/t_param_array4.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_array4.v b/test_regress/t/t_param_array4.v index e8f3a1d36..13626edc4 100644 --- a/test_regress/t/t_param_array4.v +++ b/test_regress/t/t_param_array4.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; parameter int SIZES [3:1] = '{10,20,30}; diff --git a/test_regress/t/t_param_array5.pl b/test_regress/t/t_param_array5.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_array5.pl +++ b/test_regress/t/t_param_array5.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_array5.v b/test_regress/t/t_param_array5.v index cd3dfe4c7..356c051a3 100644 --- a/test_regress/t/t_param_array5.v +++ b/test_regress/t/t_param_array5.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug1578 module t; diff --git a/test_regress/t/t_param_avec.pl b/test_regress/t/t_param_avec.pl index f016b8c8c..8271e4b7c 100755 --- a/test_regress/t/t_param_avec.pl +++ b/test_regress/t/t_param_avec.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug477"); diff --git a/test_regress/t/t_param_avec.v b/test_regress/t/t_param_avec.v index 809f43768..18806b3bc 100644 --- a/test_regress/t/t_param_avec.v +++ b/test_regress/t/t_param_avec.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_param_bit_sel.pl b/test_regress/t/t_param_bit_sel.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_bit_sel.pl +++ b/test_regress/t/t_param_bit_sel.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_bit_sel.v b/test_regress/t/t_param_bit_sel.v index f28d56c88..9159485f4 100644 --- a/test_regress/t/t_param_bit_sel.v +++ b/test_regress/t/t_param_bit_sel.v @@ -7,6 +7,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_ceil.pl b/test_regress/t/t_param_ceil.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_ceil.pl +++ b/test_regress/t/t_param_ceil.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_ceil.v b/test_regress/t/t_param_ceil.v index 14008fa5c..e66c57db0 100644 --- a/test_regress/t/t_param_ceil.v +++ b/test_regress/t/t_param_ceil.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_param_chain.pl b/test_regress/t/t_param_chain.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_chain.pl +++ b/test_regress/t/t_param_chain.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_chain.v b/test_regress/t/t_param_chain.v index 543a1781a..80ee98fda 100644 --- a/test_regress/t/t_param_chain.v +++ b/test_regress/t/t_param_chain.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_param_circ_bad.out b/test_regress/t/t_param_circ_bad.out index 35e6d04ea..ce70ca9d9 100644 --- a/test_regress/t/t_param_circ_bad.out +++ b/test_regress/t/t_param_circ_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_param_circ_bad.v:10: Variable's initial value is circular: 'X' - : ... In instance t.sub -module sub #(parameter WIDTH=X, parameter X=WIDTH) - ^ +%Error: t/t_param_circ_bad.v:11:43: Variable's initial value is circular: 'X' + : ... In instance t.sub + 11 | module sub #(parameter WIDTH=X, parameter X=WIDTH) + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_param_circ_bad.pl b/test_regress/t/t_param_circ_bad.pl index 573f98f12..8e4fecbdb 100755 --- a/test_regress/t/t_param_circ_bad.pl +++ b/test_regress/t/t_param_circ_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_circ_bad.v b/test_regress/t/t_param_circ_bad.v index 0775dc467..f27e73f29 100644 --- a/test_regress/t/t_param_circ_bad.v +++ b/test_regress/t/t_param_circ_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); sub sub (); diff --git a/test_regress/t/t_param_concat.pl b/test_regress/t/t_param_concat.pl index f018b8d24..47a8cad0b 100755 --- a/test_regress/t/t_param_concat.pl +++ b/test_regress/t/t_param_concat.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_concat.v b/test_regress/t/t_param_concat.v index 11fde4e7a..4d86d79ce 100644 --- a/test_regress/t/t_param_concat.v +++ b/test_regress/t/t_param_concat.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_concat_bad.out b/test_regress/t/t_param_concat_bad.out index e65f9494e..5c7036e34 100644 --- a/test_regress/t/t_param_concat_bad.out +++ b/test_regress/t/t_param_concat_bad.out @@ -1,14 +1,14 @@ -%Warning-WIDTHCONCAT: t/t_param_concat.v:18: Unsized numbers/parameters not allowed in concatenations. - : ... In instance t - if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; - ^~~~~~~ +%Warning-WIDTHCONCAT: t/t_param_concat.v:19:15: Unsized numbers/parameters not allowed in concatenations. + : ... In instance t + 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; + | ^~~~~~~ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. -%Warning-WIDTHCONCAT: t/t_param_concat.v:18: Unsized numbers/parameters not allowed in replications. - : ... In instance t - if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; - ^ -%Warning-WIDTHCONCAT: t/t_param_concat.v:19: Unsized numbers/parameters not allowed in replications. - : ... In instance t - if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; - ^~~~~~~ +%Warning-WIDTHCONCAT: t/t_param_concat.v:19:22: Unsized numbers/parameters not allowed in replications. + : ... In instance t + 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; + | ^ +%Warning-WIDTHCONCAT: t/t_param_concat.v:20:17: Unsized numbers/parameters not allowed in replications. + : ... In instance t + 20 | if ({2{UNSIZED}} != {32'd10, 32'd10}) $stop; + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_concat_bad.pl b/test_regress/t/t_param_concat_bad.pl index 8b3788624..550235b23 100755 --- a/test_regress/t/t_param_concat_bad.pl +++ b/test_regress/t/t_param_concat_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_const_part.pl b/test_regress/t/t_param_const_part.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_const_part.pl +++ b/test_regress/t/t_param_const_part.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_const_part.v b/test_regress/t/t_param_const_part.v index 1de26f4bc..601731f20 100644 --- a/test_regress/t/t_param_const_part.v +++ b/test_regress/t/t_param_const_part.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; function integer bottom_4bits; diff --git a/test_regress/t/t_param_ddeep_width.pl b/test_regress/t/t_param_ddeep_width.pl index 0bafa73ba..a4d74c0ba 100755 --- a/test_regress/t/t_param_ddeep_width.pl +++ b/test_regress/t/t_param_ddeep_width.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_ddeep_width.v b/test_regress/t/t_param_ddeep_width.v index 54cb9f969..379a77e80 100644 --- a/test_regress/t/t_param_ddeep_width.v +++ b/test_regress/t/t_param_ddeep_width.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use. +// SPDX-License-Identifier: CC0-1.0 // bug541 module t(clk,odata); diff --git a/test_regress/t/t_param_default.pl b/test_regress/t/t_param_default.pl index 990186320..333d76a24 100755 --- a/test_regress/t/t_param_default.pl +++ b/test_regress/t/t_param_default.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_default.v b/test_regress/t/t_param_default.v index 117569913..d4655bccc 100644 --- a/test_regress/t/t_param_default.v +++ b/test_regress/t/t_param_default.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module m #(parameter int Foo); endmodule diff --git a/test_regress/t/t_param_default_bad.out b/test_regress/t/t_param_default_bad.out index acea32421..630da39db 100644 --- a/test_regress/t/t_param_default_bad.out +++ b/test_regress/t/t_param_default_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_param_default_bad.v:6: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'Foo' - : ... In instance t.foo -module m #(parameter int Foo); - ^~~ +%Error: t/t_param_default_bad.v:7:26: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'Foo' + : ... In instance t.foo + 7 | module m #(parameter int Foo); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_default_bad.pl b/test_regress/t/t_param_default_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_param_default_bad.pl +++ b/test_regress/t/t_param_default_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_default_bad.v b/test_regress/t/t_param_default_bad.v index 16ab64e8d..d2a8d4fc6 100644 --- a/test_regress/t/t_param_default_bad.v +++ b/test_regress/t/t_param_default_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module m #(parameter int Foo); endmodule diff --git a/test_regress/t/t_param_default_presv_bad.out b/test_regress/t/t_param_default_presv_bad.out index e7e159d88..b491e2719 100644 --- a/test_regress/t/t_param_default_presv_bad.out +++ b/test_regress/t/t_param_default_presv_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_param_default_bad.v:6: Parameter requires default value, or use IEEE 1800-2009 or later. -module m #(parameter int Foo); - ^~~ +%Error: t/t_param_default_bad.v:7:26: Parameter requires default value, or use IEEE 1800-2009 or later. + 7 | module m #(parameter int Foo); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_default_presv_bad.pl b/test_regress/t/t_param_default_presv_bad.pl index 86898f848..abf6ec05e 100755 --- a/test_regress/t/t_param_default_presv_bad.pl +++ b/test_regress/t/t_param_default_presv_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_first.pl b/test_regress/t/t_param_first.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_first.pl +++ b/test_regress/t/t_param_first.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_first.v b/test_regress/t/t_param_first.v index e9a8391d6..8e812bd3c 100644 --- a/test_regress/t/t_param_first.v +++ b/test_regress/t/t_param_first.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_first_a.v b/test_regress/t/t_param_first_a.v index 4dbd52f13..66c180b2d 100644 --- a/test_regress/t/t_param_first_a.v +++ b/test_regress/t/t_param_first_a.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_param_first_a (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_param_first_b.v b/test_regress/t/t_param_first_b.v index 60d630430..99e8971c1 100644 --- a/test_regress/t/t_param_first_b.v +++ b/test_regress/t/t_param_first_b.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t_param_first_b (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_param_func.pl b/test_regress/t/t_param_func.pl index 5c448de7c..d1bf185c9 100755 --- a/test_regress/t/t_param_func.pl +++ b/test_regress/t/t_param_func.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_func.v b/test_regress/t/t_param_func.v index 4706a8325..c3a309e06 100644 --- a/test_regress/t/t_param_func.v +++ b/test_regress/t/t_param_func.v @@ -5,6 +5,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Roland Kruse and Jie Xu. +// SPDX-License-Identifier: CC0-1.0 module test#( parameter size = 4, diff --git a/test_regress/t/t_param_if_blk.pl b/test_regress/t/t_param_if_blk.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_if_blk.pl +++ b/test_regress/t/t_param_if_blk.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_if_blk.v b/test_regress/t/t_param_if_blk.v index 1ff45e612..b2a71800d 100644 --- a/test_regress/t/t_param_if_blk.v +++ b/test_regress/t/t_param_if_blk.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013. +// SPDX-License-Identifier: CC0-1.0 // bug648 diff --git a/test_regress/t/t_param_in_func_bad.out b/test_regress/t/t_param_in_func_bad.out index e9b7f3081..6e4c64cef 100644 --- a/test_regress/t/t_param_in_func_bad.out +++ b/test_regress/t/t_param_in_func_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_param_in_func_bad.v:23: Unsupported: Parameters in functions. - localparam logic[7:0] digits[10] - ^~~~~~ -%Error: t/t_param_in_func_bad.v:27: Can't find definition of variable: 'digits' - return digits[d]; - ^~~~~~ +%Error: t/t_param_in_func_bad.v:24:26: Unsupported: Parameters in functions. + 24 | localparam logic[7:0] digits[10] + | ^~~~~~ +%Error: t/t_param_in_func_bad.v:28:11: Can't find definition of variable: 'digits' + 28 | return digits[d]; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_in_func_bad.pl b/test_regress/t/t_param_in_func_bad.pl index 2cbb360e2..1ea1f5c79 100755 --- a/test_regress/t/t_param_in_func_bad.pl +++ b/test_regress/t/t_param_in_func_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_in_func_bad.v b/test_regress/t/t_param_in_func_bad.v index 2efba2f38..02a451f42 100644 --- a/test_regress/t/t_param_in_func_bad.v +++ b/test_regress/t/t_param_in_func_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_local.pl b/test_regress/t/t_param_local.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_local.pl +++ b/test_regress/t/t_param_local.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_local.v b/test_regress/t/t_param_local.v index a500bf9b1..ceb51cab7 100644 --- a/test_regress/t/t_param_local.v +++ b/test_regress/t/t_param_local.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_long.pl b/test_regress/t/t_param_long.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_long.pl +++ b/test_regress/t/t_param_long.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_long.v b/test_regress/t/t_param_long.v index ebf6c0a78..34c3cf6fc 100644 --- a/test_regress/t/t_param_long.v +++ b/test_regress/t/t_param_long.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_mem_attr.pl b/test_regress/t/t_param_mem_attr.pl index 3a7763b0d..cec0590f8 100755 --- a/test_regress/t/t_param_mem_attr.pl +++ b/test_regress/t/t_param_mem_attr.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_mem_attr.v b/test_regress/t/t_param_mem_attr.v index 0499d4068..f9b312dcb 100644 --- a/test_regress/t/t_param_mem_attr.v +++ b/test_regress/t/t_param_mem_attr.v @@ -14,6 +14,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_module.pl b/test_regress/t/t_param_module.pl index 39c42f7d0..f0260d694 100755 --- a/test_regress/t/t_param_module.pl +++ b/test_regress/t/t_param_module.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_module.v b/test_regress/t/t_param_module.v index 3ba3d5d99..69c7f1b77 100644 --- a/test_regress/t/t_param_module.v +++ b/test_regress/t/t_param_module.v @@ -12,6 +12,7 @@ // // This file ONLY is placed into the Public Domain, for any use, without // warranty, 2013 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 // bug606 diff --git a/test_regress/t/t_param_named.pl b/test_regress/t/t_param_named.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_named.pl +++ b/test_regress/t/t_param_named.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_named.v b/test_regress/t/t_param_named.v index bdbc2901b..54de8242c 100644 --- a/test_regress/t/t_param_named.v +++ b/test_regress/t/t_param_named.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_named_2.pl b/test_regress/t/t_param_named_2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_named_2.pl +++ b/test_regress/t/t_param_named_2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_named_2.v b/test_regress/t/t_param_named_2.v index f4e4126cd..d0682db1e 100644 --- a/test_regress/t/t_param_named_2.v +++ b/test_regress/t/t_param_named_2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_no_parentheses.pl b/test_regress/t/t_param_no_parentheses.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_no_parentheses.pl +++ b/test_regress/t/t_param_no_parentheses.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_no_parentheses.v b/test_regress/t/t_param_no_parentheses.v index f992cbe4c..a5f427104 100644 --- a/test_regress/t/t_param_no_parentheses.v +++ b/test_regress/t/t_param_no_parentheses.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // // This is a copy of t_param.v with the parentheses around the module parameters // removed. diff --git a/test_regress/t/t_param_noval_bad.out b/test_regress/t/t_param_noval_bad.out index 9ce66cb4a..82cc48819 100644 --- a/test_regress/t/t_param_noval_bad.out +++ b/test_regress/t/t_param_noval_bad.out @@ -1,29 +1,29 @@ -%Error: t/t_param_noval_bad.v:6: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'P' - : ... In instance t -module t #(parameter P); - ^ -%Warning-WIDTH: t/t_param_noval_bad.v:9: Logical Operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. - : ... In instance t - for (j=0; P; j++) - ^~~ +%Error: t/t_param_noval_bad.v:7:22: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'P' + : ... In instance t + 7 | module t #(parameter P); + | ^ +%Warning-WIDTH: t/t_param_noval_bad.v:10:7: Logical Operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. + : ... In instance t + 10 | for (j=0; P; j++) + | ^~~ ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. -%Error: t/t_param_noval_bad.v:9: Non-genvar used in generate for: 'j' - : ... In instance t - for (j=0; P; j++) - ^~~ -%Error: t/t_param_noval_bad.v:9: Loop unrolling failed. - : ... In instance t - for (j=0; P; j++) - ^~~ -%Error: t/t_param_noval_bad.v:9: Unsupported: Can't unroll generate for; Unable to unroll loop - : ... In instance t - for (j=0; P; j++) - ^~~ -%Error: t/t_param_noval_bad.v:9: For loop doesn't have genvar index, or is malformed - : ... In instance t - for (j=0; P; j++) - ^~~ -%Error: Internal Error: t/t_param_noval_bad.v:9: ../V3Param.cpp:#: GENFOR should have been wrapped in BEGIN - : ... In instance t - for (j=0; P; j++) - ^~~ +%Error: t/t_param_noval_bad.v:10:7: Non-genvar used in generate for: 'j' + : ... In instance t + 10 | for (j=0; P; j++) + | ^~~ +%Error: t/t_param_noval_bad.v:10:7: Loop unrolling failed. + : ... In instance t + 10 | for (j=0; P; j++) + | ^~~ +%Error: t/t_param_noval_bad.v:10:7: Unsupported: Can't unroll generate for; Unable to unroll loop + : ... In instance t + 10 | for (j=0; P; j++) + | ^~~ +%Error: t/t_param_noval_bad.v:10:7: For loop doesn't have genvar index, or is malformed + : ... In instance t + 10 | for (j=0; P; j++) + | ^~~ +%Error: Internal Error: t/t_param_noval_bad.v:10:7: ../V3Param.cpp:#: GENFOR should have been wrapped in BEGIN + : ... In instance t + 10 | for (j=0; P; j++) + | ^~~ diff --git a/test_regress/t/t_param_noval_bad.pl b/test_regress/t/t_param_noval_bad.pl index 573f98f12..8e4fecbdb 100755 --- a/test_regress/t/t_param_noval_bad.pl +++ b/test_regress/t/t_param_noval_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_noval_bad.v b/test_regress/t/t_param_noval_bad.v index 9575ca824..3dde4948a 100644 --- a/test_regress/t/t_param_noval_bad.v +++ b/test_regress/t/t_param_noval_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t #(parameter P); generate diff --git a/test_regress/t/t_param_package.pl b/test_regress/t/t_param_package.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_package.pl +++ b/test_regress/t/t_param_package.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_package.v b/test_regress/t/t_param_package.v index 21be7f149..a51891452 100644 --- a/test_regress/t/t_param_package.v +++ b/test_regress/t/t_param_package.v @@ -1,4 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; Test0 t0 (.val0('0)); diff --git a/test_regress/t/t_param_public.cpp b/test_regress/t/t_param_public.cpp index fe4ec5788..b167dbf31 100644 --- a/test_regress/t/t_param_public.cpp +++ b/test_regress/t/t_param_public.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include "Vt_param_public.h" diff --git a/test_regress/t/t_param_public.pl b/test_regress/t/t_param_public.pl index a5a02b6b2..ae7a261c5 100755 --- a/test_regress/t/t_param_public.pl +++ b/test_regress/t/t_param_public.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_public.v b/test_regress/t/t_param_public.v index e8b815ffb..36851a343 100644 --- a/test_regress/t/t_param_public.v +++ b/test_regress/t/t_param_public.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug505 diff --git a/test_regress/t/t_param_real.pl b/test_regress/t/t_param_real.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_real.pl +++ b/test_regress/t/t_param_real.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_real.v b/test_regress/t/t_param_real.v index f7b1f4c57..6fc950a82 100644 --- a/test_regress/t/t_param_real.v +++ b/test_regress/t/t_param_real.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Johan Bjork +// SPDX-License-Identifier: CC0-1.0 module mod #( parameter real HZ = 0 diff --git a/test_regress/t/t_param_real2.pl b/test_regress/t/t_param_real2.pl index b78f33caa..ce21a8188 100755 --- a/test_regress/t/t_param_real2.pl +++ b/test_regress/t/t_param_real2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can predistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_real2.v b/test_regress/t/t_param_real2.v index dc497255a..c0286032d 100644 --- a/test_regress/t/t_param_real2.v +++ b/test_regress/t/t_param_real2.v @@ -1,3 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + module foo #( parameter real bar = 2.0) (); diff --git a/test_regress/t/t_param_real2_collision.pl b/test_regress/t/t_param_real2_collision.pl index 5db448f03..8f0c687e0 100755 --- a/test_regress/t/t_param_real2_collision.pl +++ b/test_regress/t/t_param_real2_collision.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_repl.pl b/test_regress/t/t_param_repl.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_repl.pl +++ b/test_regress/t/t_param_repl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_repl.v b/test_regress/t/t_param_repl.v index 2043bceff..39f22a119 100644 --- a/test_regress/t/t_param_repl.v +++ b/test_regress/t/t_param_repl.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_scope_bad.out b/test_regress/t/t_param_scope_bad.out index c42f66b15..ca3fc7560 100644 --- a/test_regress/t/t_param_scope_bad.out +++ b/test_regress/t/t_param_scope_bad.out @@ -1,5 +1,5 @@ -%Warning-CASEOVERLAP: t/t_param_scope_bad.v:27: Case values overlap (example pattern 0x2) - 2'h2: $stop; - ^~~~ +%Warning-CASEOVERLAP: t/t_param_scope_bad.v:28:9: Case values overlap (example pattern 0x2) + 28 | 2'h2: $stop; + | ^~~~ ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_param_scope_bad.pl b/test_regress/t/t_param_scope_bad.pl index 518625206..f3dd1d2a1 100755 --- a/test_regress/t/t_param_scope_bad.pl +++ b/test_regress/t/t_param_scope_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_scope_bad.v b/test_regress/t/t_param_scope_bad.v index 5c7fbf58b..0e4c2b117 100644 --- a/test_regress/t/t_param_scope_bad.v +++ b/test_regress/t/t_param_scope_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_seg.pl b/test_regress/t/t_param_seg.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_seg.pl +++ b/test_regress/t/t_param_seg.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_seg.v b/test_regress/t/t_param_seg.v index 1b878032e..447c44d5e 100644 --- a/test_regress/t/t_param_seg.v +++ b/test_regress/t/t_param_seg.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Mandy Xu. +// SPDX-License-Identifier: CC0-1.0 // verilator lint_off WIDTH diff --git a/test_regress/t/t_param_sel.pl b/test_regress/t/t_param_sel.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_sel.pl +++ b/test_regress/t/t_param_sel.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_sel.v b/test_regress/t/t_param_sel.v index e12ff5266..3c91fef16 100644 --- a/test_regress/t/t_param_sel.v +++ b/test_regress/t/t_param_sel.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_sel_range.pl b/test_regress/t/t_param_sel_range.pl index 8ec012d6b..6e59f9f23 100755 --- a/test_regress/t/t_param_sel_range.pl +++ b/test_regress/t/t_param_sel_range.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_sel_range.v b/test_regress/t/t_param_sel_range.v index 26bb6bed6..85ea4a7d8 100644 --- a/test_regress/t/t_param_sel_range.v +++ b/test_regress/t/t_param_sel_range.v @@ -1,4 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug477 diff --git a/test_regress/t/t_param_sel_range_bad.out b/test_regress/t/t_param_sel_range_bad.out index db349a12f..a4dec58b9 100644 --- a/test_regress/t/t_param_sel_range_bad.out +++ b/test_regress/t/t_param_sel_range_bad.out @@ -1,6 +1,6 @@ -%Warning-SELRANGE: t/t_param_sel_range.v:40: Selection index out of range: 7:7 outside 4:0 - : ... In instance t.u2 - r_rst[i] <= r_rst[i-1]; - ^ +%Warning-SELRANGE: t/t_param_sel_range.v:43:35: Selection index out of range: 7:7 outside 4:0 + : ... In instance t.u2 + 43 | r_rst[i] <= r_rst[i-1]; + | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_param_sel_range_bad.pl b/test_regress/t/t_param_sel_range_bad.pl index bf58ad231..25a5b6d0d 100755 --- a/test_regress/t/t_param_sel_range_bad.pl +++ b/test_regress/t/t_param_sel_range_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_shift.pl b/test_regress/t/t_param_shift.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_shift.pl +++ b/test_regress/t/t_param_shift.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_shift.v b/test_regress/t/t_param_shift.v index cc493a10e..66d22359b 100644 --- a/test_regress/t/t_param_shift.v +++ b/test_regress/t/t_param_shift.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Mandy Xu. +// SPDX-License-Identifier: CC0-1.0 module t #(parameter[95:0] P = 1) diff --git a/test_regress/t/t_param_type.pl b/test_regress/t/t_param_type.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_type.pl +++ b/test_regress/t/t_param_type.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_type.v b/test_regress/t/t_param_type.v index 7820f6e5c..9d6accc31 100644 --- a/test_regress/t/t_param_type.v +++ b/test_regress/t/t_param_type.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_param_type2.pl b/test_regress/t/t_param_type2.pl index 73dc10324..9abe0d581 100755 --- a/test_regress/t/t_param_type2.pl +++ b/test_regress/t/t_param_type2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_type2.v b/test_regress/t/t_param_type2.v index e103c1c2a..8cdd09d70 100644 --- a/test_regress/t/t_param_type2.v +++ b/test_regress/t/t_param_type2.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 package tt_pkg; typedef enum logic [1:0] {L0, L1, L2, L3} test_t; diff --git a/test_regress/t/t_param_type3.pl b/test_regress/t/t_param_type3.pl new file mode 100755 index 000000000..9abe0d581 --- /dev/null +++ b/test_regress/t/t_param_type3.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +#execute( +# check_finished => 1, +# ); + +ok(1); +1; diff --git a/test_regress/t/t_param_type3.v b/test_regress/t/t_param_type3.v new file mode 100644 index 000000000..d0fc19307 --- /dev/null +++ b/test_regress/t/t_param_type3.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2012 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 + +typedef logic T_t; + +module t (/*AUTOARG*/ + // Outputs + o, o2, + // Inputs + i + ); + + input T_t i; + output T_t o; + output T_t o2; + + sub #(.T_t(T_t)) + sub (.i, .o); + + sub2 #(.T_t(T_t)) + sub2 (.i, .o(o2)); + +endmodule + +module sub (i,o); + parameter type T_t = logic; + localparam type T2_t = T_t; + input T_t i; + output T2_t o; + assign o = i; +endmodule + +module sub2 + #( + parameter type T_t = logic, + localparam type T2_t = T_t + ) + ( + input T_t i, + output T_t o + ); + assign o = i; +endmodule + +// Local Variables: +// verilog-typedef-regexp: "_t$" +// End: diff --git a/test_regress/t/t_param_type_bad.out b/test_regress/t/t_param_type_bad.out index 269e88619..b2a9ea9de 100644 --- a/test_regress/t/t_param_type_bad.out +++ b/test_regress/t/t_param_type_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_param_type_bad.v:8: Parameter type's initial value isn't a type: 'bad2' - localparam type bad2 = 2; - ^~~~ +%Error: t/t_param_type_bad.v:9:27: syntax error, unexpected INTEGER NUMBER, expecting TYPE-IDENTIFIER + 9 | localparam type bad2 = 2; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_param_type_bad.pl b/test_regress/t/t_param_type_bad.pl index ef912260b..5cfa596fd 100755 --- a/test_regress/t/t_param_type_bad.pl +++ b/test_regress/t/t_param_type_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_param_type_bad.v b/test_regress/t/t_param_type_bad.v index 686f415c4..45d05240b 100644 --- a/test_regress/t/t_param_type_bad.v +++ b/test_regress/t/t_param_type_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; localparam type t = logic; // Fine diff --git a/test_regress/t/t_param_type_bad2.out b/test_regress/t/t_param_type_bad2.out index 481444c92..381c74e76 100644 --- a/test_regress/t/t_param_type_bad2.out +++ b/test_regress/t/t_param_type_bad2.out @@ -1,9 +1,7 @@ -%Error: t/t_param_type_bad2.v:7: Operator VAR 't' expected non-datatype Initial value but 'logic' is a datatype. - : ... In instance t - localparam t = logic; - ^~~~~ -%Error: t/t_param_type_bad2.v:8: Operator VAR 't2' expected non-datatype Initial value but 'real' is a datatype. - : ... In instance t - localparam t2 = realtime; - ^~~~~~~~ +%Error: t/t_param_type_bad2.v:8:24: syntax error, unexpected ';', expecting "'{" + 8 | localparam t = logic; + | ^ +%Error: t/t_param_type_bad2.v:9:28: syntax error, unexpected ';', expecting "'{" + 9 | localparam t2 = realtime; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_param_type_bad2.pl b/test_regress/t/t_param_type_bad2.pl index 847928628..e749f6d6d 100755 --- a/test_regress/t/t_param_type_bad2.pl +++ b/test_regress/t/t_param_type_bad2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_param_type_bad2.v b/test_regress/t/t_param_type_bad2.v index 36ea92fe5..b61f9af0d 100644 --- a/test_regress/t/t_param_type_bad2.v +++ b/test_regress/t/t_param_type_bad2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; localparam t = logic; // Bad diff --git a/test_regress/t/t_param_type_collision.pl b/test_regress/t/t_param_type_collision.pl index c9b64dc69..babaa90eb 100755 --- a/test_regress/t/t_param_type_collision.pl +++ b/test_regress/t/t_param_type_collision.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_up_bad.out b/test_regress/t/t_param_up_bad.out index 3ce943df0..2b2a88e6b 100644 --- a/test_regress/t/t_param_up_bad.out +++ b/test_regress/t/t_param_up_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_param_up_bad.v:15: Can't find definition of scope/variable: 'bar' - assign a_bad = bar.foo; - ^~~ +%Error: t/t_param_up_bad.v:16:19: Can't find definition of scope/variable: 'bar' + 16 | assign a_bad = bar.foo; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_param_up_bad.pl b/test_regress/t/t_param_up_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_param_up_bad.pl +++ b/test_regress/t/t_param_up_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_param_up_bad.v b/test_regress/t/t_param_up_bad.v index d69afcb6b..1d5ebf566 100644 --- a/test_regress/t/t_param_up_bad.v +++ b/test_regress/t/t_param_up_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Ian Thompson. +// SPDX-License-Identifier: CC0-1.0 //bug1099 diff --git a/test_regress/t/t_param_value.pl b/test_regress/t/t_param_value.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_value.pl +++ b/test_regress/t/t_param_value.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_value.v b/test_regress/t/t_param_value.v index 5aed9defc..c74e18db7 100644 --- a/test_regress/t/t_param_value.v +++ b/test_regress/t/t_param_value.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_param_while.pl b/test_regress/t/t_param_while.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_param_while.pl +++ b/test_regress/t/t_param_while.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_while.v b/test_regress/t/t_param_while.v index 211be1f8b..8a08f8a44 100644 --- a/test_regress/t/t_param_while.v +++ b/test_regress/t/t_param_while.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug505 diff --git a/test_regress/t/t_param_wide_io.pl b/test_regress/t/t_param_wide_io.pl index fc7eccce3..a96625ee7 100755 --- a/test_regress/t/t_param_wide_io.pl +++ b/test_regress/t/t_param_wide_io.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_param_wide_io.v b/test_regress/t/t_param_wide_io.v index d10a8ca33..31168ccac 100644 --- a/test_regress/t/t_param_wide_io.v +++ b/test_regress/t/t_param_wide_io.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // issue 1991 diff --git a/test_regress/t/t_param_width_loc_bad.pl b/test_regress/t/t_param_width_loc_bad.pl index 1611882c2..9180cf4ec 100755 --- a/test_regress/t/t_param_width_loc_bad.pl +++ b/test_regress/t/t_param_width_loc_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 $Self->{vlt_all} and unsupported("Verilator unsupported, bug1624"); diff --git a/test_regress/t/t_param_width_loc_bad.v b/test_regress/t/t_param_width_loc_bad.v index 70b175888..5923bc497 100644 --- a/test_regress/t/t_param_width_loc_bad.v +++ b/test_regress/t/t_param_width_loc_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Driss Hafdi. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_parse_delay.pl b/test_regress/t/t_parse_delay.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_parse_delay.pl +++ b/test_regress/t/t_parse_delay.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_parse_delay.v b/test_regress/t/t_parse_delay.v index ba51cbaa4..2b8711734 100644 --- a/test_regress/t/t_parse_delay.v +++ b/test_regress/t/t_parse_delay.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_past.pl b/test_regress/t/t_past.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_past.pl +++ b/test_regress/t/t_past.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_past.v b/test_regress/t/t_past.v index ed7f0add8..6f5a353b0 100644 --- a/test_regress/t/t_past.v +++ b/test_regress/t/t_past.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_past_bad.out b/test_regress/t/t_past_bad.out index d6ac044d4..86d72e272 100644 --- a/test_regress/t/t_past_bad.out +++ b/test_regress/t/t_past_bad.out @@ -1,10 +1,10 @@ -%Error: t/t_past_bad.v:11: $past tick value must be constant (IEEE 1800-2017 16.9.3) - : ... In instance t - if ($past(d, 0)) $stop; - ^~~~~ -%Warning-TICKCOUNT: t/t_past_bad.v:12: $past tick value of 10000 may have a large performance cost - : ... In instance t - if ($past(d, 10000)) $stop; - ^~~~~ +%Error: t/t_past_bad.v:12:11: $past tick value must be constant (IEEE 1800-2017 16.9.3) + : ... In instance t + 12 | if ($past(d, 0)) $stop; + | ^~~~~ +%Warning-TICKCOUNT: t/t_past_bad.v:13:20: $past tick value of 10000 may have a large performance cost + : ... In instance t + 13 | if ($past(d, 10000)) $stop; + | ^~~~~ ... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_past_bad.pl b/test_regress/t/t_past_bad.pl index adc555a8d..bfd1147c6 100755 --- a/test_regress/t/t_past_bad.pl +++ b/test_regress/t/t_past_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_past_bad.v b/test_regress/t/t_past_bad.v index 0bada018b..e8ffae7de 100644 --- a/test_regress/t/t_past_bad.v +++ b/test_regress/t/t_past_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (d, clk); input d; diff --git a/test_regress/t/t_past_unsup_bad.out b/test_regress/t/t_past_unsup_bad.out index aaac41288..d4a86b845 100644 --- a/test_regress/t/t_past_unsup_bad.out +++ b/test_regress/t/t_past_unsup_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_past_unsup_bad.v:12: Unsupported: $past expr2 and clock arguments - if ($past(d, 0, 0, 0)) $stop; - ^~~~~ +%Error: t/t_past_unsup_bad.v:13:11: Unsupported: $past expr2 and clock arguments + 13 | if ($past(d, 0, 0, 0)) $stop; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_past_unsup_bad.pl b/test_regress/t/t_past_unsup_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_past_unsup_bad.pl +++ b/test_regress/t/t_past_unsup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_past_unsup_bad.v b/test_regress/t/t_past_unsup_bad.v index 2ee501754..750897cb2 100644 --- a/test_regress/t/t_past_unsup_bad.v +++ b/test_regress/t/t_past_unsup_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (d, clk); input d; diff --git a/test_regress/t/t_pipe_exit_bad.pf b/test_regress/t/t_pipe_exit_bad.pf index ff75390a7..a1302b938 100644 --- a/test_regress/t/t_pipe_exit_bad.pf +++ b/test_regress/t/t_pipe_exit_bad.pf @@ -1,9 +1,10 @@ #!/usr/bin/perl -w # DESCRIPTION: Verilator: Verilog Test example --pipe-filter script # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 die "%Error: t_pipe_exit_bad.pf: Intentional bad exit status...\n"; diff --git a/test_regress/t/t_pipe_exit_bad.pl b/test_regress/t/t_pipe_exit_bad.pl index cd25112cc..59c3c659b 100755 --- a/test_regress/t/t_pipe_exit_bad.pl +++ b/test_regress/t/t_pipe_exit_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010-2011 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pipe_filter.out b/test_regress/t/t_pipe_filter.out index b32f7e2aa..60d00f061 100644 --- a/test_regress/t/t_pipe_filter.out +++ b/test_regress/t/t_pipe_filter.out @@ -4,64 +4,67 @@ `line 3 "t/t_pipe_filter.v" 0 + -`line 6 "t/t_pipe_filter.v" 0 +`line 7 "t/t_pipe_filter.v" 0 -`line 10 "t/t_pipe_filter.v" 0 +`line 11 "t/t_pipe_filter.v" 0 example line 10; example line 11; -`line 13 "t/t_pipe_filter.v" 0 - -`line 13 "t/t_pipe_filter.v" 0 -`line 1 "t/t_pipe_filter_inc.vh" 1 -int lint_off_line_7 = 1; -`line 2 "t/t_pipe_filter_inc.vh" 0 -int lint_off_line_8 = 1; - - -`line 5 "t/t_pipe_filter_inc.vh" 0 - - - -`line 8 "t/t_pipe_filter_inc.vh" 0 -inc line 6; -inc line 7; -inc line 8; -inc line 9; - -`line 13 "t/t_pipe_filter_inc.vh" 2 -`line 13 "t/t_pipe_filter.v" 0 - `line 14 "t/t_pipe_filter.v" 0 - -`line 15 "t/t_pipe_filter.v" 0 +`line 14 "t/t_pipe_filter.v" 0 `line 1 "t/t_pipe_filter_inc.vh" 1 -int lint_off_line_7 = 1; -`line 2 "t/t_pipe_filter_inc.vh" 0 int lint_off_line_8 = 1; +`line 2 "t/t_pipe_filter_inc.vh" 0 +int lint_off_line_9 = 1; `line 5 "t/t_pipe_filter_inc.vh" 0 + -`line 8 "t/t_pipe_filter_inc.vh" 0 +`line 9 "t/t_pipe_filter_inc.vh" 0 inc line 6; inc line 7; inc line 8; inc line 9; -`line 13 "t/t_pipe_filter_inc.vh" 2 +`line 14 "t/t_pipe_filter_inc.vh" 2 +`line 14 "t/t_pipe_filter.v" 0 + `line 15 "t/t_pipe_filter.v" 0 + + +`line 16 "t/t_pipe_filter.v" 0 +`line 1 "t/t_pipe_filter_inc.vh" 1 +int lint_off_line_8 = 1; +`line 2 "t/t_pipe_filter_inc.vh" 0 +int lint_off_line_9 = 1; + + +`line 5 "t/t_pipe_filter_inc.vh" 0 + + + + +`line 9 "t/t_pipe_filter_inc.vh" 0 +inc line 6; +inc line 7; +inc line 8; +inc line 9; + +`line 14 "t/t_pipe_filter_inc.vh" 2 +`line 16 "t/t_pipe_filter.v" 0 -`line 17 "t/t_pipe_filter.v" 0 +`line 18 "t/t_pipe_filter.v" 0 example line 15; example line 16; -`line 20 "t/t_pipe_filter.v" 2 +`line 21 "t/t_pipe_filter.v" 2 diff --git a/test_regress/t/t_pipe_filter.pf b/test_regress/t/t_pipe_filter.pf index 04176a33d..82604c63b 100644 --- a/test_regress/t/t_pipe_filter.pf +++ b/test_regress/t/t_pipe_filter.pf @@ -1,10 +1,11 @@ #!/usr/bin/perl -w # DESCRIPTION: Verilator: Verilog Test example --pipe-filter script # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; use strict; diff --git a/test_regress/t/t_pipe_filter.pl b/test_regress/t/t_pipe_filter.pl index 026517e70..24f7aa9bb 100755 --- a/test_regress/t/t_pipe_filter.pl +++ b/test_regress/t/t_pipe_filter.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010-2011 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010-2011 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pipe_filter.v b/test_regress/t/t_pipe_filter.v index 42930b36e..ce2e441a1 100644 --- a/test_regress/t/t_pipe_filter.v +++ b/test_regress/t/t_pipe_filter.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //=========================================================================== // Includes diff --git a/test_regress/t/t_pipe_filter_inc.vh b/test_regress/t/t_pipe_filter_inc.vh index 021ede616..aff08071e 100644 --- a/test_regress/t/t_pipe_filter_inc.vh +++ b/test_regress/t/t_pipe_filter_inc.vh @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 inc line 6; inc line 7; // example_lint_off_line FOO diff --git a/test_regress/t/t_pp_circ_subst_bad.out b/test_regress/t/t_pp_circ_subst_bad.out index a9e9b211a..657d44e8a 100644 --- a/test_regress/t/t_pp_circ_subst_bad.out +++ b/test_regress/t/t_pp_circ_subst_bad.out @@ -1,3 +1,3 @@ -%Error: t/t_pp_circ_subst_bad.v:7: Too many preprocessor tokens on a line (>20000); perhaps recursive `define -%Error: t/t_pp_circ_subst_bad.v:7: syntax error, unexpected IDENTIFIER +%Error: t/t_pp_circ_subst_bad.v:8:40002: Too many preprocessor tokens on a line (>20000); perhaps recursive `define +%Error: t/t_pp_circ_subst_bad.v:8:1: syntax error, unexpected IDENTIFIER %Error: Exiting due to diff --git a/test_regress/t/t_pp_circ_subst_bad.pl b/test_regress/t/t_pp_circ_subst_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_pp_circ_subst_bad.pl +++ b/test_regress/t/t_pp_circ_subst_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_pp_circ_subst_bad.v b/test_regress/t/t_pp_circ_subst_bad.v index ef10ca1ce..a1abbbabb 100644 --- a/test_regress/t/t_pp_circ_subst_bad.v +++ b/test_regress/t/t_pp_circ_subst_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define e fun `e `e diff --git a/test_regress/t/t_pp_circdef_bad.out b/test_regress/t/t_pp_circdef_bad.out index 1039efb61..68de58b97 100644 --- a/test_regress/t/t_pp_circdef_bad.out +++ b/test_regress/t/t_pp_circdef_bad.out @@ -1,3 +1,3 @@ -%Error: t/t_pp_circdef_bad.v:13: Recursive `define or other nested inclusion -%Error: t/t_pp_circdef_bad.v:14: syntax error, unexpected $end, expecting TYPE-IDENTIFIER +%Error: t/t_pp_circdef_bad.v:14:21985: Recursive `define or other nested inclusion +%Error: t/t_pp_circdef_bad.v:15:1: syntax error, unexpected $end, expecting TYPE-IDENTIFIER %Error: Exiting due to diff --git a/test_regress/t/t_pp_circdef_bad.pl b/test_regress/t/t_pp_circdef_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_pp_circdef_bad.pl +++ b/test_regress/t/t_pp_circdef_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_circdef_bad.v b/test_regress/t/t_pp_circdef_bad.v index 7db7add3b..0b822957b 100644 --- a/test_regress/t/t_pp_circdef_bad.v +++ b/test_regress/t/t_pp_circdef_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // // bug445 diff --git a/test_regress/t/t_pp_defkwd_bad.out b/test_regress/t/t_pp_defkwd_bad.out index f64b09e20..0878c544d 100644 --- a/test_regress/t/t_pp_defkwd_bad.out +++ b/test_regress/t/t_pp_defkwd_bad.out @@ -1,2 +1,2 @@ -%Error: t/t_pp_defkwd_bad.v:7: Attempting to define built-in directive: '`define' (IEEE 1800-2017 22.5.1) +%Error: t/t_pp_defkwd_bad.v:8:18: Attempting to define built-in directive: '`define' (IEEE 1800-2017 22.5.1) %Error: Exiting due to diff --git a/test_regress/t/t_pp_defkwd_bad.pl b/test_regress/t/t_pp_defkwd_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_pp_defkwd_bad.pl +++ b/test_regress/t/t_pp_defkwd_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_pp_defkwd_bad.v b/test_regress/t/t_pp_defkwd_bad.v index 7139326b9..ec5a3c731 100644 --- a/test_regress/t/t_pp_defkwd_bad.v +++ b/test_regress/t/t_pp_defkwd_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define define 1 diff --git a/test_regress/t/t_pp_defparen_bad.out b/test_regress/t/t_pp_defparen_bad.out index 58bbefbb8..c6c16d023 100644 --- a/test_regress/t/t_pp_defparen_bad.out +++ b/test_regress/t/t_pp_defparen_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_pp_defparen_bad.v:9: Illegal text before '(' that starts define arguments - ( 1,2) - ^ -%Error: t/t_pp_defparen_bad.v:9: syntax error, unexpected '(' -((val 1) + (2)) - ^ +%Error: t/t_pp_defparen_bad.v:10:2: Illegal text before '(' that starts define arguments + 10 | ( 1,2) + | ^ +%Error: t/t_pp_defparen_bad.v:10:2: syntax error, unexpected '(' + 10 | ((val 1) + (2)) + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_pp_defparen_bad.pl b/test_regress/t/t_pp_defparen_bad.pl index 18439afa9..bbd90df9f 100755 --- a/test_regress/t/t_pp_defparen_bad.pl +++ b/test_regress/t/t_pp_defparen_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_defparen_bad.v b/test_regress/t/t_pp_defparen_bad.v index 232d54dbc..558bad346 100644 --- a/test_regress/t/t_pp_defparen_bad.v +++ b/test_regress/t/t_pp_defparen_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define test(a1,a2) ((a1) + (a2)) diff --git a/test_regress/t/t_pp_display.out b/test_regress/t/t_pp_display.out index 90c146e4f..d61ba2f2c 100644 --- a/test_regress/t/t_pp_display.out +++ b/test_regress/t/t_pp_display.out @@ -12,5 +12,5 @@ left side: "right side" left side: "right side" standalone twoline: "first second" -Line 49 File "t/t_pp_display.v" +Line 50 File "t/t_pp_display.v" *-* All Finished *-* diff --git a/test_regress/t/t_pp_display.pl b/test_regress/t/t_pp_display.pl index 25bcb3853..4b7e1d16f 100755 --- a/test_regress/t/t_pp_display.pl +++ b/test_regress/t/t_pp_display.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_display.v b/test_regress/t/t_pp_display.v index 1cbd4568e..4a0fcca0c 100644 --- a/test_regress/t/t_pp_display.v +++ b/test_regress/t/t_pp_display.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; wire d1 = 1'b1; diff --git a/test_regress/t/t_pp_dupdef.pl b/test_regress/t/t_pp_dupdef.pl index 792632ceb..cabafdf50 100755 --- a/test_regress/t/t_pp_dupdef.pl +++ b/test_regress/t/t_pp_dupdef.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_dupdef.v b/test_regress/t/t_pp_dupdef.v index 19a3dd52d..4e2405777 100644 --- a/test_regress/t/t_pp_dupdef.v +++ b/test_regress/t/t_pp_dupdef.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_pp_dupdef_bad.out b/test_regress/t/t_pp_dupdef_bad.out index f0fdab49e..82ffa436e 100644 --- a/test_regress/t/t_pp_dupdef_bad.out +++ b/test_regress/t/t_pp_dupdef_bad.out @@ -1,6 +1,6 @@ -%Warning-REDEFMACRO: t/t_pp_dupdef.v:10: Redefining existing define: 'DUP', with different value: barney +%Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Redefining existing define: 'DUP', with different value: barney ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message. -%Warning-REDEFMACRO: t/t_pp_dupdef.v:10: Previous definition is here, with value: fred -%Warning-REDEFMACRO: t/t_pp_dupdef.v:13: Redefining existing define: 'DUPP', with different value: paramed(x,z) (x*z) -%Warning-REDEFMACRO: t/t_pp_dupdef.v:13: Previous definition is here, with value: paramed(x) (x) +%Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Previous definition is here, with value: fred +%Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Redefining existing define: 'DUPP', with different value: paramed(x,z) (x*z) +%Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Previous definition is here, with value: paramed(x) (x) %Error: Exiting due to diff --git a/test_regress/t/t_pp_dupdef_bad.pl b/test_regress/t/t_pp_dupdef_bad.pl index ace749f8a..e9a4794a7 100755 --- a/test_regress/t/t_pp_dupdef_bad.pl +++ b/test_regress/t/t_pp_dupdef_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_lib.pl b/test_regress/t/t_pp_lib.pl index 96c8d22f9..ca19fd9bf 100755 --- a/test_regress/t/t_pp_lib.pl +++ b/test_regress/t/t_pp_lib.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_lib.v b/test_regress/t/t_pp_lib.v index 4c066fbdf..ae984a1a1 100644 --- a/test_regress/t/t_pp_lib.v +++ b/test_regress/t/t_pp_lib.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "t_pp_lib_inc.vh" module t(); diff --git a/test_regress/t/t_pp_lib_inc.vh b/test_regress/t/t_pp_lib_inc.vh index 4c32a16fe..734024343 100644 --- a/test_regress/t/t_pp_lib_inc.vh +++ b/test_regress/t/t_pp_lib_inc.vh @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define WIDTH 10 diff --git a/test_regress/t/t_pp_lib_library.v b/test_regress/t/t_pp_lib_library.v index 1059eedcf..316c8844c 100644 --- a/test_regress/t/t_pp_lib_library.v +++ b/test_regress/t/t_pp_lib_library.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module library_cell(a); input [`WIDTH-1:0] a; diff --git a/test_regress/t/t_pp_line_bad.out b/test_regress/t/t_pp_line_bad.out index 609b3befb..15958d5ff 100644 --- a/test_regress/t/t_pp_line_bad.out +++ b/test_regress/t/t_pp_line_bad.out @@ -1,15 +1,13 @@ -%Error: t/t_pp_line_bad.v:100: `line was not properly formed with '`line number "filename" level' -`line 100 -^ -%Error: somefile:100: `line was not properly formed with '`line number "filename" level' -`line 100 -^ -%Error: somefile:100: `line was not properly formed with '`line number "filename" level' -%Error-internal-no-contents -^ -%Error: t/t_pp_line_bad.v:6: Define or directive not defined: '`line' -`line -^~~~~ -%Error: somefile:100: `line was not properly formed with '`line number "filename" level' - t/t_pp_line_bad.v:101: ... note: In file included from t_pp_line_bad.v +%Error: t/t_pp_line_bad.v:100:1: `line was not properly formed with '`line number "filename" level' + 100 | `line 100 + | ^ +%Error: somefile:100:1: `line was not properly formed with '`line number "filename" level' + 100 | `line 100 + | ^ +%Error: somefile:100:1: `line was not properly formed with '`line number "filename" level' +%Error: t/t_pp_line_bad.v:7:1: Define or directive not defined: '`line' + 7 | `line + | ^~~~~ +%Error: somefile:100:1: `line was not properly formed with '`line number "filename" level' + t/t_pp_line_bad.v:101:1: ... note: In file included from t_pp_line_bad.v %Error: Exiting due to diff --git a/test_regress/t/t_pp_line_bad.pl b/test_regress/t/t_pp_line_bad.pl index 18439afa9..bbd90df9f 100755 --- a/test_regress/t/t_pp_line_bad.pl +++ b/test_regress/t/t_pp_line_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_line_bad.v b/test_regress/t/t_pp_line_bad.v index ee4975ba0..e1ac808a4 100644 --- a/test_regress/t/t_pp_line_bad.v +++ b/test_regress/t/t_pp_line_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `line `line 100 diff --git a/test_regress/t/t_pp_misdef_bad.out b/test_regress/t/t_pp_misdef_bad.out index 6cb34ad26..4e32fd0ae 100644 --- a/test_regress/t/t_pp_misdef_bad.out +++ b/test_regress/t/t_pp_misdef_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_pp_misdef_bad.v:10: Define or directive not defined: '`NDEFINED' - : ... Suggested alternative: '`DEFINED' - `NDEFINED - ^~~~~~~~~ -%Error: t/t_pp_misdef_bad.v:13: Define or directive not defined: '`imescale' - : ... Suggested alternative: '`timescale' - `imescale - ^~~~~~~~~ +%Error: t/t_pp_misdef_bad.v:11:4: Define or directive not defined: '`NDEFINED' + : ... Suggested alternative: '`DEFINED' + 11 | `NDEFINED + | ^~~~~~~~~ +%Error: t/t_pp_misdef_bad.v:14:6: Define or directive not defined: '`imescale' + : ... Suggested alternative: '`timescale' + 14 | `imescale + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_pp_misdef_bad.pl b/test_regress/t/t_pp_misdef_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_pp_misdef_bad.pl +++ b/test_regress/t/t_pp_misdef_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_misdef_bad.v b/test_regress/t/t_pp_misdef_bad.v index 1a2eaa145..6328c26db 100644 --- a/test_regress/t/t_pp_misdef_bad.v +++ b/test_regress/t/t_pp_misdef_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; `define DEFINED diff --git a/test_regress/t/t_pp_pragma_bad.out b/test_regress/t/t_pp_pragma_bad.out index 8ba8ab7cd..912313652 100644 --- a/test_regress/t/t_pp_pragma_bad.out +++ b/test_regress/t/t_pp_pragma_bad.out @@ -1,15 +1,16 @@ -%Error: t/t_pp_pragma_bad.v:6: `pragma is missing a pragma_expression. -`pragma -^~~~~~~ +%Error: t/t_pp_pragma_bad.v:7:1: `pragma is missing a pragma_expression. + 7 | `pragma + | ^~~~~~~ `line 1 "t/t_pp_pragma_bad.v" 1 `line 3 "t/t_pp_pragma_bad.v" 0 + -`line 6 "t/t_pp_pragma_bad.v" 0 +`line 7 "t/t_pp_pragma_bad.v" 0 `pragma -`line 8 "t/t_pp_pragma_bad.v" 2 +`line 9 "t/t_pp_pragma_bad.v" 2 %Error: Exiting due to diff --git a/test_regress/t/t_pp_pragma_bad.pl b/test_regress/t/t_pp_pragma_bad.pl index b2b1453c0..9e2158836 100755 --- a/test_regress/t/t_pp_pragma_bad.pl +++ b/test_regress/t/t_pp_pragma_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_pp_pragma_bad.v b/test_regress/t/t_pp_pragma_bad.v index 2abfe64b7..82c596225 100644 --- a/test_regress/t/t_pp_pragma_bad.v +++ b/test_regress/t/t_pp_pragma_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `pragma diff --git a/test_regress/t/t_pp_pragmas.pl b/test_regress/t/t_pp_pragmas.pl index beafec13a..3b6486e92 100755 --- a/test_regress/t/t_pp_pragmas.pl +++ b/test_regress/t/t_pp_pragmas.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_pragmas.v b/test_regress/t/t_pp_pragmas.v index 83ff9c1e7..2da128a39 100644 --- a/test_regress/t/t_pp_pragmas.v +++ b/test_regress/t/t_pp_pragmas.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `timescale 1ns/10ps `verilog diff --git a/test_regress/t/t_pp_resetall_bad.out b/test_regress/t/t_pp_resetall_bad.out index 8de09b7c5..123e39280 100644 --- a/test_regress/t/t_pp_resetall_bad.out +++ b/test_regress/t/t_pp_resetall_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_pp_resetall_bad.v:8: syntax error, unexpected `resetall -`resetall -^~~~~~~~~ +%Error: t/t_pp_resetall_bad.v:9:1: syntax error, unexpected `resetall + 9 | `resetall + | ^~~~~~~~~ %Error: Cannot continue diff --git a/test_regress/t/t_pp_resetall_bad.pl b/test_regress/t/t_pp_resetall_bad.pl index 4d5945c09..1be077634 100755 --- a/test_regress/t/t_pp_resetall_bad.pl +++ b/test_regress/t/t_pp_resetall_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_pp_resetall_bad.v b/test_regress/t/t_pp_resetall_bad.v index f38c41ac0..1d9cc583a 100644 --- a/test_regress/t/t_pp_resetall_bad.v +++ b/test_regress/t/t_pp_resetall_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `resetall // Ok module t; diff --git a/test_regress/t/t_pp_underline_bad.out b/test_regress/t/t_pp_underline_bad.out index 4c83f2957..b68627482 100644 --- a/test_regress/t/t_pp_underline_bad.out +++ b/test_regress/t/t_pp_underline_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_pp_underline_bad.v:7: Extra underscore in meta-comment; use /*verilator {...}*/ not /*verilator_{...}*/ - // verilator_no_inline_module - ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Error: t/t_pp_underline_bad.v:7: Unknown verilator comment: /*verilator _no_inline_module*/ - /*verilator _no_inline_module*/ - ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_pp_underline_bad.v:8:4: Extra underscore in meta-comment; use /*verilator {...}*/ not /*verilator_{...}*/ + 8 | // verilator_no_inline_module + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_pp_underline_bad.v:8:4: Unknown verilator comment: /*verilator _no_inline_module*/ + 8 | /*verilator _no_inline_module*/ + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_pp_underline_bad.pl b/test_regress/t/t_pp_underline_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_pp_underline_bad.pl +++ b/test_regress/t/t_pp_underline_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_pp_underline_bad.v b/test_regress/t/t_pp_underline_bad.v index 28e1b26f4..63f0c9c47 100644 --- a/test_regress/t/t_pp_underline_bad.v +++ b/test_regress/t/t_pp_underline_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; // verilator_no_inline_module diff --git a/test_regress/t/t_preproc.out b/test_regress/t/t_preproc.out index df2757029..d7dbfb30c 100644 --- a/test_regress/t/t_preproc.out +++ b/test_regress/t/t_preproc.out @@ -2,66 +2,69 @@ + -`line 5 "t/t_preproc.v" 0 +`line 6 "t/t_preproc.v" 0 -`line 7 "t/t_preproc.v" 0 +`line 8 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 `line 2 "t/t_preproc_inc2.vh" 0 -At file "t/t_preproc_inc2.vh" line 4 + +At file "t/t_preproc_inc2.vh" line 5 -`line 6 "t/t_preproc_inc2.vh" 0 +`line 7 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 `line 2 "inc3_a_filename_from_line_directive" 0 + -`line 6 "inc3_a_filename_from_line_directive" 0 +`line 7 "inc3_a_filename_from_line_directive" 0 - At file "inc3_a_filename_from_line_directive" line 10 + At file "inc3_a_filename_from_line_directive" line 11 -`line 12 "inc3_a_filename_from_line_directive" 0 +`line 13 "inc3_a_filename_from_line_directive" 0 -`line 15 "inc3_a_filename_from_line_directive" 0 +`line 16 "inc3_a_filename_from_line_directive" 0 -`line 19 "inc3_a_filename_from_line_directive" 2 -`line 6 "t/t_preproc_inc2.vh" 0 +`line 20 "inc3_a_filename_from_line_directive" 2 +`line 7 "t/t_preproc_inc2.vh" 0 -`line 8 "t/t_preproc_inc2.vh" 2 -`line 7 "t/t_preproc.v" 0 +`line 9 "t/t_preproc_inc2.vh" 2 +`line 8 "t/t_preproc.v" 0 -`line 9 "t/t_preproc.v" 0 +`line 10 "t/t_preproc.v" 0 -`line 12 "t/t_preproc.v" 0 +`line 13 "t/t_preproc.v" 0 /*verilator pass_thru comment*/ -`line 14 "t/t_preproc.v" 0 +`line 15 "t/t_preproc.v" 0 /*verilator pass_thru_comment2*/ -`line 16 "t/t_preproc.v" 0 +`line 17 "t/t_preproc.v" 0 -`line 19 "t/t_preproc.v" 0 +`line 20 "t/t_preproc.v" 0 @@ -72,104 +75,104 @@ At file "t/t_preproc_inc2.vh" line 4 1'b1 }; -`line 29 "t/t_preproc.v" 0 +`line 30 "t/t_preproc.v" 0 text. -`line 31 "t/t_preproc.v" 0 +`line 32 "t/t_preproc.v" 0 foo bar foobar2 -`line 36 "t/t_preproc.v" 0 +`line 37 "t/t_preproc.v" 0 -`line 40 "t/t_preproc.v" 0 +`line 41 "t/t_preproc.v" 0 -`line 45 "t/t_preproc.v" 0 +`line 46 "t/t_preproc.v" 0 first part -`line 46 "t/t_preproc.v" 0 +`line 47 "t/t_preproc.v" 0 second part -`line 46 "t/t_preproc.v" 0 +`line 47 "t/t_preproc.v" 0 third part { -`line 47 "t/t_preproc.v" 0 +`line 48 "t/t_preproc.v" 0 a, -`line 47 "t/t_preproc.v" 0 +`line 48 "t/t_preproc.v" 0 b, -`line 47 "t/t_preproc.v" 0 +`line 48 "t/t_preproc.v" 0 c} -Line_Preproc_Check 48 +Line_Preproc_Check 49 -`line 50 "t/t_preproc.v" 0 +`line 51 "t/t_preproc.v" 0 -`line 52 "t/t_preproc.v" 0 +`line 53 "t/t_preproc.v" 0 -`line 54 "t/t_preproc.v" 0 +`line 55 "t/t_preproc.v" 0 deep deep -`line 58 "t/t_preproc.v" 0 +`line 59 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" -`line 63 "t/t_preproc.v" 0 +`line 64 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s -`line 69 "t/t_preproc.v" 0 +`line 70 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line -`line 71 "t/t_preproc.v" 0 +`line 72 "t/t_preproc.v" 0 x y LLZZ "x" y -`line 74 "t/t_preproc.v" 0 +`line 75 "t/t_preproc.v" 0 (a,b)(a,b) -`line 77 "t/t_preproc.v" 0 +`line 78 "t/t_preproc.v" 0 $display("left side: \"right side\"") -`line 80 "t/t_preproc.v" 0 +`line 81 "t/t_preproc.v" 0 bar_suffix more -`line 83 "t/t_preproc.v" 0 +`line 84 "t/t_preproc.v" 0 -`line 85 "t/t_preproc.v" 0 - $c("Zap(\"",bug1,"\");");; - `line 86 "t/t_preproc.v" 0 + $c("Zap(\"",bug1,"\");");; + +`line 87 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; -`line 88 "t/t_preproc.v" 0 +`line 89 "t/t_preproc.v" 0 -`line 91 "t/t_preproc.v" 0 +`line 92 "t/t_preproc.v" 0 -`line 94 "t/t_preproc.v" 0 +`line 95 "t/t_preproc.v" 0 @@ -191,7 +194,7 @@ bar_suffix more $display("left side: \"right side\""); $display("standalone"); -`line 115 "t/t_preproc.v" 0 +`line 116 "t/t_preproc.v" 0 @@ -202,73 +205,73 @@ bar_suffix more end endmodule -`line 125 "t/t_preproc.v" 0 +`line 126 "t/t_preproc.v" 0 -`line 128 "t/t_preproc.v" 0 +`line 129 "t/t_preproc.v" 0 -`line 133 "t/t_preproc.v" 0 +`line 134 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); -`line 134 "t/t_preproc.v" 0 +`line 135 "t/t_preproc.v" 0 wire tmp_d1 = d1; -`line 134 "t/t_preproc.v" 0 +`line 135 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; -`line 134 "t/t_preproc.v" 0 +`line 135 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; endmodule module add2 ( input wire d2, output wire o2); -`line 137 "t/t_preproc.v" 0 +`line 138 "t/t_preproc.v" 0 wire tmp_d2 = d2; -`line 137 "t/t_preproc.v" 0 +`line 138 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; -`line 137 "t/t_preproc.v" 0 +`line 138 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; endmodule -`line 140 "t/t_preproc.v" 0 +`line 141 "t/t_preproc.v" 0 -`line 146 "t/t_preproc.v" 0 +`line 147 "t/t_preproc.v" 0 -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 end endgenerate -`line 153 "t/t_preproc.v" 0 +`line 154 "t/t_preproc.v" 0 module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] -`line 159 "t/t_preproc.v" 0 +`line 160 "t/t_preproc.v" 0 `endprotected endmodule -`line 163 "t/t_preproc.v" 0 +`line 164 "t/t_preproc.v" 0 @@ -279,78 +282,79 @@ endmodule -`line 173 "t/t_preproc.v" 0 +`line 174 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more -`line 177 "t/t_preproc.v" 0 +`line 178 "t/t_preproc.v" 0 -`line 180 "t/t_preproc.v" 0 +`line 181 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 - -`line 5 "t/t_preproc_inc4.vh" 0 -`line 7 "t/t_preproc_inc4.vh" 2 -`line 180 "t/t_preproc.v" 0 +`line 6 "t/t_preproc_inc4.vh" 0 + +`line 8 "t/t_preproc_inc4.vh" 2 `line 181 "t/t_preproc.v" 0 + +`line 182 "t/t_preproc.v" 0 -`line 184 "t/t_preproc.v" 0 +`line 185 "t/t_preproc.v" 0 -`line 186 "t/t_preproc.v" 0 +`line 187 "t/t_preproc.v" 0 -`line 190 "t/t_preproc.v" 0 +`line 191 "t/t_preproc.v" 0 -`line 193 "t/t_preproc.v" 0 +`line 194 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); -`line 199 "t/t_preproc.v" 0 +`line 200 "t/t_preproc.v" 0 -`line 202 "t/t_preproc.v" 0 +`line 203 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire -`line 206 "t/t_preproc.v" 0 +`line 207 "t/t_preproc.v" 0 -`line 209 "t/t_preproc.v" 0 +`line 210 "t/t_preproc.v" 0 -`line 213 "t/t_preproc.v" 0 -Line_Preproc_Check 213 +`line 214 "t/t_preproc.v" 0 +Line_Preproc_Check 214 -`line 215 "t/t_preproc.v" 0 +`line 216 "t/t_preproc.v" 0 -`line 218 "t/t_preproc.v" 0 +`line 219 "t/t_preproc.v" 0 @@ -358,15 +362,15 @@ Line_Preproc_Check 213 -`line 225 "t/t_preproc.v" 0 +`line 226 "t/t_preproc.v" 0 (x,y) -Line_Preproc_Check 226 +Line_Preproc_Check 227 -`line 228 "t/t_preproc.v" 0 +`line 229 "t/t_preproc.v" 0 -`line 231 "t/t_preproc.v" 0 +`line 232 "t/t_preproc.v" 0 @@ -375,17 +379,17 @@ beginend beginend "beginend" -`line 239 "t/t_preproc.v" 0 +`line 240 "t/t_preproc.v" 0 `\esc`def -`line 245 "t/t_preproc.v" 0 +`line 246 "t/t_preproc.v" 0 Not a \`define -`line 247 "t/t_preproc.v" 0 +`line 248 "t/t_preproc.v" 0 @@ -394,23 +398,23 @@ Not a \`define x,y)--bee submacro has comma paren -`line 255 "t/t_preproc.v" 0 +`line 256 "t/t_preproc.v" 0 $display("10 %d %d", $bits(foo), 10); -`line 260 "t/t_preproc.v" 0 +`line 261 "t/t_preproc.v" 0 -`line 265 "t/t_preproc.v" 0 +`line 266 "t/t_preproc.v" 0 -`line 268 "t/t_preproc.v" 0 +`line 269 "t/t_preproc.v" 0 @@ -425,30 +429,30 @@ $display("10 %d %d", $bits(foo), 10); -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 assign a3 = ~b3 ; -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 284 "t/t_preproc.v" 0 +`line 285 "t/t_preproc.v" 0 \ @@ -459,56 +463,56 @@ $display("10 %d %d", $bits(foo), 10); -`line 293 "t/t_preproc.v" 0 +`line 294 "t/t_preproc.v" 0 -`line 293 "t/t_preproc.v" 0 +`line 294 "t/t_preproc.v" 0 -`line 293 "t/t_preproc.v" 0 +`line 294 "t/t_preproc.v" 0 def i -`line 295 "t/t_preproc.v" 0 +`line 296 "t/t_preproc.v" 0 -`line 297 "t/t_preproc.v" 0 +`line 298 "t/t_preproc.v" 0 -`line 301 "t/t_preproc.v" 0 +`line 302 "t/t_preproc.v" 0 -`line 307 "t/t_preproc.v" 0 +`line 308 "t/t_preproc.v" 0 1 /*verilator NOT IN DEFINE*/ (nodef) 2 /*verilator PART OF DEFINE*/ (hasdef) 3 -`line 309 "t/t_preproc.v" 0 +`line 310 "t/t_preproc.v" 0 /*verilator NOT PART OF DEFINE*/ (nodef) -`line 310 "t/t_preproc.v" 0 +`line 311 "t/t_preproc.v" 0 4 -`line 310 "t/t_preproc.v" 0 +`line 311 "t/t_preproc.v" 0 /*verilator PART OF DEFINE*/ (nodef) -`line 311 "t/t_preproc.v" 0 +`line 312 "t/t_preproc.v" 0 5 also in -`line 311 "t/t_preproc.v" 0 +`line 312 "t/t_preproc.v" 0 also3 (nodef) HAS a NEW -`line 314 "t/t_preproc.v" 0 +`line 315 "t/t_preproc.v" 0 LINE -`line 316 "t/t_preproc.v" 0 +`line 317 "t/t_preproc.v" 0 -`line 318 "t/t_preproc.v" 0 +`line 319 "t/t_preproc.v" 0 @@ -522,11 +526,11 @@ LINE -`line 331 "t/t_preproc.v" 0 +`line 332 "t/t_preproc.v" 0 -`line 334 "t/t_preproc.v" 0 +`line 335 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen @@ -534,44 +538,44 @@ EXP: clxx_scen EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 do -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 - if (start("t/t_preproc.v", 340)) begin -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 + if (start("t/t_preproc.v", 341)) begin +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 end -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 while(0); -`line 342 "t/t_preproc.v" 0 +`line 343 "t/t_preproc.v" 0 -`line 344 "t/t_preproc.v" 0 +`line 345 "t/t_preproc.v" 0 -`line 348 "t/t_preproc.v" 0 - -`line 348 "t/t_preproc.v" 0 - - `line 349 "t/t_preproc.v" 0 + +`line 349 "t/t_preproc.v" 0 + + +`line 350 "t/t_preproc.v" 0 EXP: This is fooed @@ -579,7 +583,7 @@ This is fooed EXP: This is fooed_2 This is fooed_2 -`line 356 "t/t_preproc.v" 0 +`line 357 "t/t_preproc.v" 0 np @@ -591,11 +595,11 @@ np -`line 367 "t/t_preproc.v" 0 +`line 368 "t/t_preproc.v" 0 -`line 370 "t/t_preproc.v" 0 +`line 371 "t/t_preproc.v" 0 @@ -604,12 +608,12 @@ np -`line 378 "t/t_preproc.v" 0 +`line 379 "t/t_preproc.v" 0 -`line 382 "t/t_preproc.v" 0 +`line 383 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 @@ -617,20 +621,21 @@ hello4hello4hello4hello4 -`line 388 "t/t_preproc.v" 0 +`line 389 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 `line 2 "t/t_preproc_inc4.vh" 0 - -`line 5 "t/t_preproc_inc4.vh" 0 -`line 7 "t/t_preproc_inc4.vh" 2 -`line 388 "t/t_preproc.v" 0 +`line 6 "t/t_preproc_inc4.vh" 0 + +`line 8 "t/t_preproc_inc4.vh" 2 `line 389 "t/t_preproc.v" 0 + +`line 390 "t/t_preproc.v" 0 @@ -640,28 +645,28 @@ hello4hello4hello4hello4 -`line 397 "t/t_preproc.v" 0 +`line 398 "t/t_preproc.v" 0 -Line_Preproc_Check 401 +Line_Preproc_Check 402 -Line_Preproc_Check 407 +Line_Preproc_Check 408 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " -`line 410 "t/t_preproc.v" 0 -Line_Preproc_Check 410 +`line 411 "t/t_preproc.v" 0 +Line_Preproc_Check 411 -`line 414 "t/t_preproc.v" 0 +`line 415 "t/t_preproc.v" 0 @@ -672,14 +677,14 @@ abc -`line 424 "t/t_preproc.v" 0 +`line 425 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame -`line 430 "t/t_preproc.v" 0 +`line 431 "t/t_preproc.v" 0 EXP: sonet_frame @@ -690,7 +695,7 @@ sonet_frame EXP: sonet_frame sonet_frame -`line 440 "t/t_preproc.v" 0 +`line 441 "t/t_preproc.v" 0 @@ -698,13 +703,13 @@ EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule -`line 447 "t/t_preproc.v" 0 +`line 448 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule -`line 452 "t/t_preproc.v" 0 +`line 453 "t/t_preproc.v" 0 integer foo; @@ -718,7 +723,7 @@ module t; initial begin : \`LEX_CAT(a[0],_assignment) -`line 464 "t/t_preproc.v" 0 +`line 465 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end @@ -727,7 +732,7 @@ module t; initial begin : \a[0]_assignment_a[1] -`line 471 "t/t_preproc.v" 0 +`line 472 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end @@ -743,7 +748,7 @@ module t; initial begin : \`CAT(ff,bb) -`line 485 "t/t_preproc.v" 0 +`line 486 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end @@ -751,7 +756,7 @@ module t; initial begin : \`zzz -`line 491 "t/t_preproc.v" 0 +`line 492 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end @@ -760,11 +765,11 @@ module t; initial begin : \`FOO -`line 498 "t/t_preproc.v" 0 +`line 499 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end initial begin : \xx`FOO -`line 500 "t/t_preproc.v" 0 +`line 501 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end @@ -797,27 +802,27 @@ module t; initial -`line 531 "t/t_preproc.v" 0 +`line 532 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule -`line 534 "t/t_preproc.v" 0 +`line 535 "t/t_preproc.v" 0 -`line 537 "t/t_preproc.v" 0 +`line 538 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); -`line 542 "t/t_preproc.v" 0 +`line 543 "t/t_preproc.v" 0 -`line 547 "t/t_preproc.v" 0 +`line 548 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ @@ -825,7 +830,7 @@ XXE_FAMILY = XXE_ $display("XXE_ is defined"); -`line 554 "t/t_preproc.v" 0 +`line 555 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ @@ -833,7 +838,7 @@ XYE_FAMILY = XYE_ $display("XYE_ is defined"); -`line 561 "t/t_preproc.v" 0 +`line 562 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some @@ -841,7 +846,7 @@ XXS_FAMILY = XXS_some $display("XXS_some is defined"); -`line 568 "t/t_preproc.v" 0 +`line 569 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo @@ -849,10 +854,10 @@ XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); -`line 575 "t/t_preproc.v" 0 +`line 576 "t/t_preproc.v" 0 -`line 577 "t/t_preproc.v" 0 +`line 578 "t/t_preproc.v" 0 @@ -861,7 +866,7 @@ XYS_FAMILY = XYS_foo -`line 585 "t/t_preproc.v" 0 +`line 586 "t/t_preproc.v" 0 @@ -869,7 +874,7 @@ XYS_FAMILY = XYS_foo -`line 592 "t/t_preproc.v" 0 +`line 593 "t/t_preproc.v" 0 @@ -877,7 +882,7 @@ XYS_FAMILY = XYS_foo -`line 599 "t/t_preproc.v" 0 +`line 600 "t/t_preproc.v" 0 @@ -885,26 +890,26 @@ XYS_FAMILY = XYS_foo -`line 606 "t/t_preproc.v" 0 +`line 607 "t/t_preproc.v" 0 -`line 608 "t/t_preproc.v" 0 +`line 609 "t/t_preproc.v" 0 -`line 610 "t/t_preproc.v" 0 +`line 611 "t/t_preproc.v" 0 (.mySig (myInterface.pa5), -`line 614 "t/t_preproc.v" 0 +`line 615 "t/t_preproc.v" 0 -`line 617 "t/t_preproc.v" 0 +`line 618 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); -`line 620 "t/t_preproc.v" 0 +`line 621 "t/t_preproc.v" 0 @@ -913,22 +918,22 @@ XYS_FAMILY = XYS_foo -`line 628 "t/t_preproc.v" 0 +`line 629 "t/t_preproc.v" 0 module pcc2_cfg; generate -`line 630 "t/t_preproc.v" 0 +`line 631 "t/t_preproc.v" 0 covergroup a @(posedge b); -`line 630 "t/t_preproc.v" 0 +`line 631 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup -`line 630 "t/t_preproc.v" 0 +`line 631 "t/t_preproc.v" 0 a u_a; -`line 630 "t/t_preproc.v" 0 +`line 631 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule -`line 634 "t/t_preproc.v" 0 +`line 635 "t/t_preproc.v" 0 @@ -951,4 +956,4 @@ predef 2 2 -`line 656 "t/t_preproc.v" 2 +`line 657 "t/t_preproc.v" 2 diff --git a/test_regress/t/t_preproc.pl b/test_regress/t/t_preproc.pl index 7fab97211..625065541 100755 --- a/test_regress/t/t_preproc.pl +++ b/test_regress/t/t_preproc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_preproc.v b/test_regress/t/t_preproc.v index c1c645c31..580998ce9 100644 --- a/test_regress/t/t_preproc.v +++ b/test_regress/t/t_preproc.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2000-2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //=========================================================================== // Includes diff --git a/test_regress/t/t_preproc_cmtend_bad.out b/test_regress/t/t_preproc_cmtend_bad.out index 9a57b89a5..5fe061ed9 100644 --- a/test_regress/t/t_preproc_cmtend_bad.out +++ b/test_regress/t/t_preproc_cmtend_bad.out @@ -1,2 +1,2 @@ -%Error: t/t_preproc_cmtend_bad.v:9: EOF in '/* ... */' block comment +%Error: t/t_preproc_cmtend_bad.v:10:1: EOF in '/* ... */' block comment %Error: Exiting due to diff --git a/test_regress/t/t_preproc_cmtend_bad.pl b/test_regress/t/t_preproc_cmtend_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_preproc_cmtend_bad.pl +++ b/test_regress/t/t_preproc_cmtend_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_preproc_cmtend_bad.v b/test_regress/t/t_preproc_cmtend_bad.v index 165be9aaf..d458fe340 100644 --- a/test_regress/t/t_preproc_cmtend_bad.v +++ b/test_regress/t/t_preproc_cmtend_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 /*Blah blah diff --git a/test_regress/t/t_preproc_comments.out b/test_regress/t/t_preproc_comments.out index 37d76bdcc..2397ac8f9 100644 --- a/test_regress/t/t_preproc_comments.out +++ b/test_regress/t/t_preproc_comments.out @@ -1,67 +1,70 @@ `line 1 "t/t_preproc.v" 1 // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2000-2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 -`line 5 "t/t_preproc.v" 0 +`line 6 "t/t_preproc.v" 0 //=========================================================================== // Includes -`line 7 "t/t_preproc.v" 0 +`line 8 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc2.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc2.vh" 0 -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2000-2007 by Wilson Snyder. -At file "t/t_preproc_inc2.vh" line 4 +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2000-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 +At file "t/t_preproc_inc2.vh" line 5 -`line 6 "t/t_preproc_inc2.vh" 0 +`line 7 "t/t_preproc_inc2.vh" 0 `line 1 "t/t_preproc_inc3.vh" 1 `line 2 "inc3_a_filename_from_line_directive" 0 // DESCRIPTION: Verilog::Preproc: Example source code -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2000-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2000-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 -`line 6 "inc3_a_filename_from_line_directive" 0 +`line 7 "inc3_a_filename_from_line_directive" 0 // FOO - At file "inc3_a_filename_from_line_directive" line 10 + At file "inc3_a_filename_from_line_directive" line 11 -`line 12 "inc3_a_filename_from_line_directive" 0 +`line 13 "inc3_a_filename_from_line_directive" 0 // guard -`line 15 "inc3_a_filename_from_line_directive" 0 +`line 16 "inc3_a_filename_from_line_directive" 0 -`line 19 "inc3_a_filename_from_line_directive" 2 -`line 6 "t/t_preproc_inc2.vh" 0 +`line 20 "inc3_a_filename_from_line_directive" 2 +`line 7 "t/t_preproc_inc2.vh" 0 -`line 8 "t/t_preproc_inc2.vh" 2 -`line 7 "t/t_preproc.v" 0 +`line 9 "t/t_preproc_inc2.vh" 2 +`line 8 "t/t_preproc.v" 0 -`line 9 "t/t_preproc.v" 0 +`line 10 "t/t_preproc.v" 0 //=========================================================================== // Comments -`line 12 "t/t_preproc.v" 0 +`line 13 "t/t_preproc.v" 0 /* verilator pass_thru comment */ -`line 14 "t/t_preproc.v" 0 +`line 15 "t/t_preproc.v" 0 // verilator pass_thru_comment2 -`line 16 "t/t_preproc.v" 0 +`line 17 "t/t_preproc.v" 0 //=========================================================================== // Defines -`line 19 "t/t_preproc.v" 0 +`line 20 "t/t_preproc.v" 0 // DEF_A0 set by command line @@ -72,104 +75,104 @@ At file "t/t_preproc_inc2.vh" line 4 1'b1 }; -`line 29 "t/t_preproc.v" 0 +`line 30 "t/t_preproc.v" 0 text. -`line 31 "t/t_preproc.v" 0 +`line 32 "t/t_preproc.v" 0 foo /*this */ bar /* this too */ foobar2 // but not -`line 36 "t/t_preproc.v" 0 +`line 37 "t/t_preproc.v" 0 -`line 40 "t/t_preproc.v" 0 +`line 41 "t/t_preproc.v" 0 -`line 45 "t/t_preproc.v" 0 +`line 46 "t/t_preproc.v" 0 /*******COMMENT*****/ first part -`line 46 "t/t_preproc.v" 0 +`line 47 "t/t_preproc.v" 0 second part -`line 46 "t/t_preproc.v" 0 +`line 47 "t/t_preproc.v" 0 third part { -`line 47 "t/t_preproc.v" 0 +`line 48 "t/t_preproc.v" 0 a, -`line 47 "t/t_preproc.v" 0 +`line 48 "t/t_preproc.v" 0 b, -`line 47 "t/t_preproc.v" 0 +`line 48 "t/t_preproc.v" 0 c} -Line_Preproc_Check 48 +Line_Preproc_Check 49 -`line 50 "t/t_preproc.v" 0 +`line 51 "t/t_preproc.v" 0 //=========================================================================== -`line 52 "t/t_preproc.v" 0 +`line 53 "t/t_preproc.v" 0 -`line 54 "t/t_preproc.v" 0 +`line 55 "t/t_preproc.v" 0 deep deep -`line 58 "t/t_preproc.v" 0 +`line 59 "t/t_preproc.v" 0 "Inside: `nosubst" "`nosubst" -`line 63 "t/t_preproc.v" 0 +`line 64 "t/t_preproc.v" 0 x y LLZZ x y p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s -`line 69 "t/t_preproc.v" 0 +`line 70 "t/t_preproc.v" 0 firstline comma","line LLZZ firstline comma","line -`line 71 "t/t_preproc.v" 0 +`line 72 "t/t_preproc.v" 0 x y LLZZ "x" y // Simulators disagree here; some substitute "a" others do not -`line 74 "t/t_preproc.v" 0 +`line 75 "t/t_preproc.v" 0 (a,b)(a,b) -`line 77 "t/t_preproc.v" 0 +`line 78 "t/t_preproc.v" 0 $display("left side: \"right side\"") -`line 80 "t/t_preproc.v" 0 +`line 81 "t/t_preproc.v" 0 bar_suffix more -`line 83 "t/t_preproc.v" 0 +`line 84 "t/t_preproc.v" 0 -`line 85 "t/t_preproc.v" 0 +`line 86 "t/t_preproc.v" 0 $c("Zap(\"",bug1,"\");");; -`line 86 "t/t_preproc.v" 0 +`line 87 "t/t_preproc.v" 0 $c("Zap(\"","bug2","\");");; -`line 88 "t/t_preproc.v" 0 +`line 89 "t/t_preproc.v" 0 /* Define inside comment: `DEEPER and `WITHTICK */ // More commentary: `zap(bug1); `zap("bug2"); -`line 91 "t/t_preproc.v" 0 +`line 92 "t/t_preproc.v" 0 //====================================================================== // display passthru -`line 94 "t/t_preproc.v" 0 +`line 95 "t/t_preproc.v" 0 @@ -191,7 +194,7 @@ bar_suffix more $display("left side: \"right side\""); $display("standalone"); -`line 115 "t/t_preproc.v" 0 +`line 116 "t/t_preproc.v" 0 // Unspecified when the stringification has multiple lines @@ -202,73 +205,73 @@ bar_suffix more end endmodule -`line 125 "t/t_preproc.v" 0 +`line 126 "t/t_preproc.v" 0 //====================================================================== // rt.cpan.org bug34429 -`line 128 "t/t_preproc.v" 0 +`line 129 "t/t_preproc.v" 0 -`line 133 "t/t_preproc.v" 0 +`line 134 "t/t_preproc.v" 0 module add1 ( input wire d1, output wire o1); -`line 134 "t/t_preproc.v" 0 +`line 135 "t/t_preproc.v" 0 wire tmp_d1 = d1; -`line 134 "t/t_preproc.v" 0 +`line 135 "t/t_preproc.v" 0 wire tmp_o1 = tmp_d1 + 1; -`line 134 "t/t_preproc.v" 0 +`line 135 "t/t_preproc.v" 0 assign o1 = tmp_o1 ; // expansion is OK endmodule module add2 ( input wire d2, output wire o2); -`line 137 "t/t_preproc.v" 0 +`line 138 "t/t_preproc.v" 0 wire tmp_d2 = d2; -`line 137 "t/t_preproc.v" 0 +`line 138 "t/t_preproc.v" 0 wire tmp_o2 = tmp_d2 + 1; -`line 137 "t/t_preproc.v" 0 +`line 138 "t/t_preproc.v" 0 assign o2 = tmp_o2 ; // expansion is bad endmodule -`line 140 "t/t_preproc.v" 0 +`line 141 "t/t_preproc.v" 0 -`line 146 "t/t_preproc.v" 0 +`line 147 "t/t_preproc.v" 0 // parameterized macro with arguments that are macros -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 generate for (i=0; i<(3); i=i+1) begin -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; -`line 151 "t/t_preproc.v" 0 +`line 152 "t/t_preproc.v" 0 end endgenerate // ignorecmt -`line 153 "t/t_preproc.v" 0 +`line 154 "t/t_preproc.v" 0 //====================================================================== // Quotes are legal in protected blocks. Grr. module prot(); `protected I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl) #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk] -`line 159 "t/t_preproc.v" 0 +`line 160 "t/t_preproc.v" 0 `endprotected endmodule //" -`line 163 "t/t_preproc.v" 0 +`line 164 "t/t_preproc.v" 0 //====================================================================== // macro call with define that has comma @@ -279,78 +282,79 @@ endmodule -`line 173 "t/t_preproc.v" 0 +`line 174 "t/t_preproc.v" 0 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more -`line 177 "t/t_preproc.v" 0 +`line 178 "t/t_preproc.v" 0 //====================================================================== // include of parameterized file -`line 180 "t/t_preproc.v" 0 +`line 181 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2000-2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 -`line 5 "t/t_preproc_inc4.vh" 0 +`line 6 "t/t_preproc_inc4.vh" 0 -`line 7 "t/t_preproc_inc4.vh" 2 -`line 180 "t/t_preproc.v" 0 - +`line 8 "t/t_preproc_inc4.vh" 2 `line 181 "t/t_preproc.v" 0 + +`line 182 "t/t_preproc.v" 0 -`line 184 "t/t_preproc.v" 0 +`line 185 "t/t_preproc.v" 0 -`line 186 "t/t_preproc.v" 0 +`line 187 "t/t_preproc.v" 0 -`line 190 "t/t_preproc.v" 0 +`line 191 "t/t_preproc.v" 0 //====================================================================== // macro call with , in {} -`line 193 "t/t_preproc.v" 0 +`line 194 "t/t_preproc.v" 0 $blah("ab,cd","e,f"); $blah(this.logfile,vec); $blah(this.logfile,vec[1,2,3]); $blah(this.logfile,{blah.name(), " is not foo"}); -`line 199 "t/t_preproc.v" 0 +`line 200 "t/t_preproc.v" 0 //====================================================================== // pragma/default net type -`line 202 "t/t_preproc.v" 0 +`line 203 "t/t_preproc.v" 0 `pragma foo = 1 `default_nettype none `default_nettype uwire -`line 206 "t/t_preproc.v" 0 +`line 207 "t/t_preproc.v" 0 //====================================================================== // Ifdef -`line 209 "t/t_preproc.v" 0 +`line 210 "t/t_preproc.v" 0 -`line 213 "t/t_preproc.v" 0 -Line_Preproc_Check 213 +`line 214 "t/t_preproc.v" 0 +Line_Preproc_Check 214 -`line 215 "t/t_preproc.v" 0 +`line 216 "t/t_preproc.v" 0 //====================================================================== // bug84 -`line 218 "t/t_preproc.v" 0 +`line 219 "t/t_preproc.v" 0 // Hello, comments MIGHT not be legal /*more,,)cmts*/ // But newlines ARE legal... who speced THAT? @@ -358,15 +362,15 @@ Line_Preproc_Check 213 -`line 225 "t/t_preproc.v" 0 +`line 226 "t/t_preproc.v" 0 (//Here x,y //Too) -Line_Preproc_Check 226 +Line_Preproc_Check 227 -`line 228 "t/t_preproc.v" 0 +`line 229 "t/t_preproc.v" 0 //====================================================================== // defines split arguments -`line 231 "t/t_preproc.v" 0 +`line 232 "t/t_preproc.v" 0 @@ -375,17 +379,17 @@ beginend // 2001 spec doesn't require two tokens, so "beginend" ok beginend // 2001 spec doesn't require two tokens, so "beginend" ok "beginend" // No space "beginend" -`line 239 "t/t_preproc.v" 0 +`line 240 "t/t_preproc.v" 0 //====================================================================== // bug106 `\esc`def -`line 245 "t/t_preproc.v" 0 +`line 246 "t/t_preproc.v" 0 Not a \`define -`line 247 "t/t_preproc.v" 0 +`line 248 "t/t_preproc.v" 0 //====================================================================== // misparsed comma in submacro @@ -394,23 +398,23 @@ Not a \`define x,y)--bee submacro has comma paren -`line 255 "t/t_preproc.v" 0 +`line 256 "t/t_preproc.v" 0 //====================================================================== // bug191 $display("10 %d %d", $bits(foo), 10); -`line 260 "t/t_preproc.v" 0 +`line 261 "t/t_preproc.v" 0 //====================================================================== // 1800-2009 -`line 265 "t/t_preproc.v" 0 +`line 266 "t/t_preproc.v" 0 -`line 268 "t/t_preproc.v" 0 +`line 269 "t/t_preproc.v" 0 //====================================================================== // bug202 @@ -425,34 +429,34 @@ $display("10 %d %d", $bits(foo), 10); -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 assign a3 = ~b3 ; -`line 282 "t/t_preproc.v" 0 +`line 283 "t/t_preproc.v" 0 -`line 284 "t/t_preproc.v" 0 +`line 285 "t/t_preproc.v" 0 /* multi \ line1*/ \ -`line 286 "t/t_preproc.v" 0 +`line 287 "t/t_preproc.v" 0 /*multi \ line2*/ @@ -461,59 +465,59 @@ $display("10 %d %d", $bits(foo), 10); -`line 293 "t/t_preproc.v" 0 +`line 294 "t/t_preproc.v" 0 -`line 293 "t/t_preproc.v" 0 +`line 294 "t/t_preproc.v" 0 -`line 293 "t/t_preproc.v" 0 +`line 294 "t/t_preproc.v" 0 /* multi line 3*/ -`line 293 "t/t_preproc.v" 0 +`line 294 "t/t_preproc.v" 0 def i -`line 295 "t/t_preproc.v" 0 +`line 296 "t/t_preproc.v" 0 //====================================================================== -`line 297 "t/t_preproc.v" 0 +`line 298 "t/t_preproc.v" 0 -`line 301 "t/t_preproc.v" 0 +`line 302 "t/t_preproc.v" 0 -`line 307 "t/t_preproc.v" 0 +`line 308 "t/t_preproc.v" 0 1 // verilator NOT IN DEFINE (nodef) 2 /* verilator PART OF DEFINE */ (hasdef) 3 -`line 309 "t/t_preproc.v" 0 +`line 310 "t/t_preproc.v" 0 /* verilator NOT PART OF DEFINE */ (nodef) -`line 310 "t/t_preproc.v" 0 +`line 311 "t/t_preproc.v" 0 4 -`line 310 "t/t_preproc.v" 0 +`line 311 "t/t_preproc.v" 0 /* verilator PART OF DEFINE */ (nodef) -`line 311 "t/t_preproc.v" 0 +`line 312 "t/t_preproc.v" 0 5 also in -`line 311 "t/t_preproc.v" 0 +`line 312 "t/t_preproc.v" 0 also3 // CMT NOT (nodef) HAS a NEW -`line 314 "t/t_preproc.v" 0 +`line 315 "t/t_preproc.v" 0 LINE -`line 316 "t/t_preproc.v" 0 +`line 317 "t/t_preproc.v" 0 //====================================================================== -`line 318 "t/t_preproc.v" 0 +`line 319 "t/t_preproc.v" 0 @@ -527,11 +531,11 @@ LINE -`line 331 "t/t_preproc.v" 0 +`line 332 "t/t_preproc.v" 0 -`line 334 "t/t_preproc.v" 0 +`line 335 "t/t_preproc.v" 0 EXP: clxx_scen clxx_scen EXP: clxx_scen @@ -539,44 +543,44 @@ EXP: clxx_scen EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0); -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 do -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 /* synopsys translate_off */ -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 - if (start("t/t_preproc.v", 340)) begin -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 + if (start("t/t_preproc.v", 341)) begin +`line 341 "t/t_preproc.v" 0 -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 message({"Blah-", "clx_scen", " end"}); -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 end -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 /* synopsys translate_on */ -`line 340 "t/t_preproc.v" 0 +`line 341 "t/t_preproc.v" 0 while(0); -`line 342 "t/t_preproc.v" 0 +`line 343 "t/t_preproc.v" 0 //====================================================================== -`line 344 "t/t_preproc.v" 0 +`line 345 "t/t_preproc.v" 0 -`line 348 "t/t_preproc.v" 0 +`line 349 "t/t_preproc.v" 0 -`line 348 "t/t_preproc.v" 0 +`line 349 "t/t_preproc.v" 0 -`line 349 "t/t_preproc.v" 0 +`line 350 "t/t_preproc.v" 0 //`ifndef def_fooed_2 `error "No def_fooed_2" `endif EXP: This is fooed @@ -584,7 +588,7 @@ This is fooed EXP: This is fooed_2 This is fooed_2 -`line 356 "t/t_preproc.v" 0 +`line 357 "t/t_preproc.v" 0 //====================================================================== np @@ -596,11 +600,11 @@ np -`line 367 "t/t_preproc.v" 0 +`line 368 "t/t_preproc.v" 0 -`line 370 "t/t_preproc.v" 0 +`line 371 "t/t_preproc.v" 0 //====================================================================== // Metaprogramming @@ -609,12 +613,12 @@ np -`line 378 "t/t_preproc.v" 0 +`line 379 "t/t_preproc.v" 0 -`line 382 "t/t_preproc.v" 0 +`line 383 "t/t_preproc.v" 0 hello3hello3hello3 hello4hello4hello4hello4 //====================================================================== @@ -622,20 +626,21 @@ hello4hello4hello4hello4 -`line 388 "t/t_preproc.v" 0 +`line 389 "t/t_preproc.v" 0 `line 1 "t/t_preproc_inc4.vh" 1 // DESCRIPTION: Verilog::Preproc: Example source code `line 2 "t/t_preproc_inc4.vh" 0 -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2000-2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 -`line 5 "t/t_preproc_inc4.vh" 0 +`line 6 "t/t_preproc_inc4.vh" 0 -`line 7 "t/t_preproc_inc4.vh" 2 -`line 388 "t/t_preproc.v" 0 - +`line 8 "t/t_preproc_inc4.vh" 2 `line 389 "t/t_preproc.v" 0 + +`line 390 "t/t_preproc.v" 0 //====================================================================== // Defines doing defines @@ -645,28 +650,28 @@ hello4hello4hello4hello4 -`line 397 "t/t_preproc.v" 0 +`line 398 "t/t_preproc.v" 0 -Line_Preproc_Check 401 +Line_Preproc_Check 402 //====================================================================== // Quoted multiline - track line numbers, and ensure \\n gets propagated -Line_Preproc_Check 407 +Line_Preproc_Check 408 "FOO \ BAR " "arg_line1 \ arg_line2" "FOO \ BAR " -`line 410 "t/t_preproc.v" 0 -Line_Preproc_Check 410 +`line 411 "t/t_preproc.v" 0 +Line_Preproc_Check 411 //====================================================================== // bug283 -`line 414 "t/t_preproc.v" 0 +`line 415 "t/t_preproc.v" 0 @@ -677,14 +682,14 @@ abc -`line 424 "t/t_preproc.v" 0 +`line 425 "t/t_preproc.v" 0 EXP: sonet_frame sonet_frame -`line 430 "t/t_preproc.v" 0 +`line 431 "t/t_preproc.v" 0 EXP: sonet_frame @@ -695,7 +700,7 @@ sonet_frame EXP: sonet_frame sonet_frame -`line 440 "t/t_preproc.v" 0 +`line 441 "t/t_preproc.v" 0 // The existance of non-existance of a base define can make a difference @@ -703,13 +708,13 @@ EXP: module zzz ; endmodule module zzz ; endmodule module zzz ; endmodule -`line 447 "t/t_preproc.v" 0 +`line 448 "t/t_preproc.v" 0 EXP: module a_b ; endmodule module a_b ; endmodule module a_b ; endmodule -`line 452 "t/t_preproc.v" 0 +`line 453 "t/t_preproc.v" 0 //====================================================================== // bug311 integer/*NEED_SPACE*/ foo; @@ -723,7 +728,7 @@ module t; initial begin : \`LEX_CAT(a[0],_assignment) -`line 464 "t/t_preproc.v" 0 +`line 465 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end //----- // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from @@ -732,7 +737,7 @@ module t; initial begin : \a[0]_assignment_a[1] -`line 471 "t/t_preproc.v" 0 +`line 472 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end //----- @@ -748,7 +753,7 @@ module t; // Similar to above; \ does not allow expansion after substitution initial begin : \`CAT(ff,bb) -`line 485 "t/t_preproc.v" 0 +`line 486 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end //----- @@ -756,7 +761,7 @@ module t; // MUST: Unknown macro with backslash escape stays as escaped symbol name initial begin : \`zzz -`line 491 "t/t_preproc.v" 0 +`line 492 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end //----- @@ -765,11 +770,11 @@ module t; // SHOULD(simulator-dependant): Known macro with backslash escape expands initial begin : \`FOO -`line 498 "t/t_preproc.v" 0 +`line 499 "t/t_preproc.v" 0 $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end // SHOULD(simulator-dependant): Prefix breaks the above initial begin : \xx`FOO -`line 500 "t/t_preproc.v" 0 +`line 501 "t/t_preproc.v" 0 $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end //----- @@ -802,27 +807,27 @@ module t; initial -`line 531 "t/t_preproc.v" 0 +`line 532 "t/t_preproc.v" 0 $display("%s%s","a1","b2c3\n"); endmodule -`line 534 "t/t_preproc.v" 0 +`line 535 "t/t_preproc.v" 0 //====================================================================== //bug1225 -`line 537 "t/t_preproc.v" 0 +`line 538 "t/t_preproc.v" 0 $display("RAM0"); $display("CPU"); -`line 542 "t/t_preproc.v" 0 +`line 543 "t/t_preproc.v" 0 -`line 547 "t/t_preproc.v" 0 +`line 548 "t/t_preproc.v" 0 XXE_FAMILY = XXE_ @@ -830,7 +835,7 @@ XXE_FAMILY = XXE_ $display("XXE_ is defined"); -`line 554 "t/t_preproc.v" 0 +`line 555 "t/t_preproc.v" 0 XYE_FAMILY = XYE_ @@ -838,7 +843,7 @@ XYE_FAMILY = XYE_ $display("XYE_ is defined"); -`line 561 "t/t_preproc.v" 0 +`line 562 "t/t_preproc.v" 0 XXS_FAMILY = XXS_some @@ -846,7 +851,7 @@ XXS_FAMILY = XXS_some $display("XXS_some is defined"); -`line 568 "t/t_preproc.v" 0 +`line 569 "t/t_preproc.v" 0 XYS_FAMILY = XYS_foo @@ -854,10 +859,10 @@ XYS_FAMILY = XYS_foo $display("XYS_foo is defined"); -`line 575 "t/t_preproc.v" 0 +`line 576 "t/t_preproc.v" 0 //==== -`line 577 "t/t_preproc.v" 0 +`line 578 "t/t_preproc.v" 0 @@ -866,7 +871,7 @@ XYS_FAMILY = XYS_foo -`line 585 "t/t_preproc.v" 0 +`line 586 "t/t_preproc.v" 0 @@ -874,7 +879,7 @@ XYS_FAMILY = XYS_foo -`line 592 "t/t_preproc.v" 0 +`line 593 "t/t_preproc.v" 0 @@ -882,7 +887,7 @@ XYS_FAMILY = XYS_foo -`line 599 "t/t_preproc.v" 0 +`line 600 "t/t_preproc.v" 0 @@ -890,26 +895,26 @@ XYS_FAMILY = XYS_foo -`line 606 "t/t_preproc.v" 0 +`line 607 "t/t_preproc.v" 0 -`line 608 "t/t_preproc.v" 0 +`line 609 "t/t_preproc.v" 0 // NEVER -`line 610 "t/t_preproc.v" 0 +`line 611 "t/t_preproc.v" 0 //bug1227 (.mySig (myInterface.pa5), -`line 614 "t/t_preproc.v" 0 +`line 615 "t/t_preproc.v" 0 //====================================================================== // Stringify bug -`line 617 "t/t_preproc.v" 0 +`line 618 "t/t_preproc.v" 0 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp")); -`line 620 "t/t_preproc.v" 0 +`line 621 "t/t_preproc.v" 0 @@ -918,22 +923,22 @@ XYS_FAMILY = XYS_foo -`line 628 "t/t_preproc.v" 0 +`line 629 "t/t_preproc.v" 0 module pcc2_cfg; generate -`line 630 "t/t_preproc.v" 0 +`line 631 "t/t_preproc.v" 0 covergroup a @(posedge b); -`line 630 "t/t_preproc.v" 0 +`line 631 "t/t_preproc.v" 0 c: coverpoint d iff ((c) === 1'b1); endgroup -`line 630 "t/t_preproc.v" 0 +`line 631 "t/t_preproc.v" 0 a u_a; -`line 630 "t/t_preproc.v" 0 +`line 631 "t/t_preproc.v" 0 initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0); endgenerate endmodule -`line 634 "t/t_preproc.v" 0 +`line 635 "t/t_preproc.v" 0 //====================================================================== // IEEE mandated predefines // undefineall should have no effect on these @@ -956,4 +961,4 @@ predef 2 2 // After `undefineall above, for testing --dump-defines -`line 656 "t/t_preproc.v" 2 +`line 657 "t/t_preproc.v" 2 diff --git a/test_regress/t/t_preproc_comments.pl b/test_regress/t/t_preproc_comments.pl index 76a564caf..1773d00f9 100755 --- a/test_regress/t/t_preproc_comments.pl +++ b/test_regress/t/t_preproc_comments.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_preproc_def09.out b/test_regress/t/t_preproc_def09.out index f6cec7721..1958e614e 100644 --- a/test_regress/t/t_preproc_def09.out +++ b/test_regress/t/t_preproc_def09.out @@ -4,10 +4,11 @@ `line 3 "t/t_preproc_def09.v" 0 + -`line 8 "t/t_preproc_def09.v" 0 +`line 9 "t/t_preproc_def09.v" 0 @@ -25,7 +26,7 @@ -`line 25 "t/t_preproc_def09.v" 0 +`line 26 "t/t_preproc_def09.v" 0 '$display(5,,2,,3);' @@ -36,7 +37,7 @@ '$display(5,,2,,);' -`line 35 "t/t_preproc_def09.v" 0 +`line 36 "t/t_preproc_def09.v" 0 '$display(1,,,,3);' '$display(5,,,,"C");' @@ -45,7 +46,7 @@ '$display(5,,2,,"C");' '$display(5,,2,,"C");' -`line 43 "t/t_preproc_def09.v" 0 +`line 44 "t/t_preproc_def09.v" 0 '$display(1,,0,,"C");' '$display(1 ,,0,,"C");' @@ -53,18 +54,18 @@ '$display(5,,0,,"C");' -`line 50 "t/t_preproc_def09.v" 0 +`line 51 "t/t_preproc_def09.v" 0 'b + 1 + 42 + a' 'b + 1 + 42 + a' -`line 54 "t/t_preproc_def09.v" 0 +`line 55 "t/t_preproc_def09.v" 0 '"==)" "((((" () '; '"==)" "((((" () '; -`line 59 "t/t_preproc_def09.v" 0 +`line 60 "t/t_preproc_def09.v" 0 @@ -76,11 +77,11 @@ -`line 70 "t/t_preproc_def09.v" 0 +`line 71 "t/t_preproc_def09.v" 0 '(6) (eq=al) ZOT' -HERE-71 - Line71 +HERE-72 - Line71 -`line 73 "t/t_preproc_def09.v" 0 +`line 74 "t/t_preproc_def09.v" 0 -`line 75 "t/t_preproc_def09.v" 2 +`line 76 "t/t_preproc_def09.v" 2 diff --git a/test_regress/t/t_preproc_def09.pl b/test_regress/t/t_preproc_def09.pl index 841fbc144..c31a87dbc 100755 --- a/test_regress/t/t_preproc_def09.pl +++ b/test_regress/t/t_preproc_def09.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_preproc_def09.v b/test_regress/t/t_preproc_def09.v index 88c27c235..05c68e7a6 100644 --- a/test_regress/t/t_preproc_def09.v +++ b/test_regress/t/t_preproc_def09.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `undefineall diff --git a/test_regress/t/t_preproc_defines.pl b/test_regress/t/t_preproc_defines.pl index 175d16f15..936036834 100755 --- a/test_regress/t/t_preproc_defines.pl +++ b/test_regress/t/t_preproc_defines.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_preproc_dos.pl b/test_regress/t/t_preproc_dos.pl index 7496f75ef..d203cf947 100755 --- a/test_regress/t/t_preproc_dos.pl +++ b/test_regress/t/t_preproc_dos.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2006-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2006-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_preproc_ifdef.pl b/test_regress/t/t_preproc_ifdef.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_preproc_ifdef.pl +++ b/test_regress/t/t_preproc_ifdef.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_preproc_ifdef.v b/test_regress/t/t_preproc_ifdef.v index 7c5e23be6..19bf9c25e 100644 --- a/test_regress/t/t_preproc_ifdef.v +++ b/test_regress/t/t_preproc_ifdef.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); integer num; diff --git a/test_regress/t/t_preproc_inc2.vh b/test_regress/t/t_preproc_inc2.vh index 77d993ef0..89ab6d752 100644 --- a/test_regress/t/t_preproc_inc2.vh +++ b/test_regress/t/t_preproc_inc2.vh @@ -1,6 +1,7 @@ // DESCRIPTION: Verilog::Preproc: Example source code -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2000-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2000-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 At file `__FILE__ line `__LINE__ `define INCFILE `include `INCFILE diff --git a/test_regress/t/t_preproc_inc3.vh b/test_regress/t/t_preproc_inc3.vh index 04e8a5a6c..0abaf0e7a 100644 --- a/test_regress/t/t_preproc_inc3.vh +++ b/test_regress/t/t_preproc_inc3.vh @@ -1,7 +1,8 @@ `line 2 "inc3_a_filename_from_line_directive" 0 // DESCRIPTION: Verilog::Preproc: Example source code -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2000-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2000-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `ifndef _EXAMPLE_INC2_V_ `define _EXAMPLE_INC2_V_ 1 diff --git a/test_regress/t/t_preproc_inc4.vh b/test_regress/t/t_preproc_inc4.vh index f4720758d..7f5b187a3 100644 --- a/test_regress/t/t_preproc_inc4.vh +++ b/test_regress/t/t_preproc_inc4.vh @@ -1,5 +1,6 @@ // DESCRIPTION: Verilog::Preproc: Example source code -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2000-2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2000-2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define T_PREPROC_INC4 diff --git a/test_regress/t/t_preproc_inc_bad.out b/test_regress/t/t_preproc_inc_bad.out new file mode 100644 index 000000000..295d92512 --- /dev/null +++ b/test_regress/t/t_preproc_inc_bad.out @@ -0,0 +1,5 @@ +%Error: t/t_preproc_inc_inc_bad.vh:11:1: syntax error, unexpected endmodule, expecting IDENTIFIER + 11 | endmodule + | ^~~~~~~~~ + t/t_preproc_inc_bad.v:10:1: ... note: In file included from t_preproc_inc_bad.v +%Error: Exiting due to diff --git a/test_regress/t/t_preproc_inc_bad.pl b/test_regress/t/t_preproc_inc_bad.pl index ec7744e00..523cfcda1 100755 --- a/test_regress/t/t_preproc_inc_bad.pl +++ b/test_regress/t/t_preproc_inc_bad.pl @@ -2,18 +2,18 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); lint( fails => 1, # The .vh file has the error, not the .v file - expect => -'%Error: t/t_preproc_inc_inc_bad.vh:10: syntax error, unexpected endmodule, expecting IDENTIFIER' + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_preproc_inc_bad.v b/test_regress/t/t_preproc_inc_bad.v index 1c8b9ff76..a9dd80fc6 100644 --- a/test_regress/t/t_preproc_inc_bad.v +++ b/test_regress/t/t_preproc_inc_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //See bug289 diff --git a/test_regress/t/t_preproc_inc_inc_bad.vh b/test_regress/t/t_preproc_inc_inc_bad.vh index 329c771f3..83cab6aaf 100644 --- a/test_regress/t/t_preproc_inc_inc_bad.vh +++ b/test_regress/t/t_preproc_inc_inc_bad.vh @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module xx; diff --git a/test_regress/t/t_preproc_inc_notfound_bad.out b/test_regress/t/t_preproc_inc_notfound_bad.out index 41a4268eb..d2d6ba31d 100644 --- a/test_regress/t/t_preproc_inc_notfound_bad.out +++ b/test_regress/t/t_preproc_inc_notfound_bad.out @@ -1,6 +1,6 @@ -%Error: t/t_preproc_inc_notfound_bad.v:6: Cannot find include file: this_file_is_not_found.vh -`include "this_file_is_not_found.vh" - ^~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_preproc_inc_notfound_bad.v:7:10: Cannot find include file: this_file_is_not_found.vh + 7 | `include "this_file_is_not_found.vh" + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ... Looked in: t/this_file_is_not_found.vh t/this_file_is_not_found.vh.v diff --git a/test_regress/t/t_preproc_inc_notfound_bad.pl b/test_regress/t/t_preproc_inc_notfound_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_preproc_inc_notfound_bad.pl +++ b/test_regress/t/t_preproc_inc_notfound_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_preproc_inc_notfound_bad.v b/test_regress/t/t_preproc_inc_notfound_bad.v index e225ca5cd..fb4d0cfbd 100644 --- a/test_regress/t/t_preproc_inc_notfound_bad.v +++ b/test_regress/t/t_preproc_inc_notfound_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "this_file_is_not_found.vh" diff --git a/test_regress/t/t_preproc_inc_recurse_bad.out b/test_regress/t/t_preproc_inc_recurse_bad.out index a4ac2808b..1751134af 100644 --- a/test_regress/t/t_preproc_inc_recurse_bad.out +++ b/test_regress/t/t_preproc_inc_recurse_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_preproc_inc_recurse_bad.v:6: Recursive inclusion of file: t/t_preproc_inc_recurse_bad.v -`include "t_preproc_inc_recurse_bad.v" - ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Error: t/t_preproc_inc_recurse_bad.v:7:10: Recursive inclusion of file: t/t_preproc_inc_recurse_bad.v + 7 | `include "t_preproc_inc_recurse_bad.v" + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_preproc_inc_recurse_bad.pl b/test_regress/t/t_preproc_inc_recurse_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_preproc_inc_recurse_bad.pl +++ b/test_regress/t/t_preproc_inc_recurse_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_preproc_inc_recurse_bad.v b/test_regress/t/t_preproc_inc_recurse_bad.v index da097aeaf..21497beef 100644 --- a/test_regress/t/t_preproc_inc_recurse_bad.v +++ b/test_regress/t/t_preproc_inc_recurse_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "t_preproc_inc_recurse_bad.v" diff --git a/test_regress/t/t_preproc_kwd.pl b/test_regress/t/t_preproc_kwd.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_preproc_kwd.pl +++ b/test_regress/t/t_preproc_kwd.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_preproc_kwd.v b/test_regress/t/t_preproc_kwd.v index f62e5124e..ab22e2983 100644 --- a/test_regress/t/t_preproc_kwd.v +++ b/test_regress/t/t_preproc_kwd.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_preproc_noline.out b/test_regress/t/t_preproc_noline.out index f7b77d57c..18da0f41d 100644 --- a/test_regress/t/t_preproc_noline.out +++ b/test_regress/t/t_preproc_noline.out @@ -2,4 +2,4 @@ Hello in t_preproc_psl.v yes Multi text multiline line -Line: 20 +Line: 21 diff --git a/test_regress/t/t_preproc_noline.pl b/test_regress/t/t_preproc_noline.pl index e85ef091f..7d1bd17f1 100755 --- a/test_regress/t/t_preproc_noline.pl +++ b/test_regress/t/t_preproc_noline.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_preproc_noline.v b/test_regress/t/t_preproc_noline.v index 8d89b0e5e..3f7c72700 100644 --- a/test_regress/t/t_preproc_noline.v +++ b/test_regress/t/t_preproc_noline.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define CHECK text \ multiline diff --git a/test_regress/t/t_preproc_persist.pl b/test_regress/t/t_preproc_persist.pl index 0cf8c2a41..e6025e6ab 100755 --- a/test_regress/t/t_preproc_persist.pl +++ b/test_regress/t/t_preproc_persist.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2017 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_preproc_persist.v b/test_regress/t/t_preproc_persist.v index 0f3f45687..b78e3d90d 100644 --- a/test_regress/t/t_preproc_persist.v +++ b/test_regress/t/t_preproc_persist.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 Inside `__FILE__. diff --git a/test_regress/t/t_preproc_persist2.v b/test_regress/t/t_preproc_persist2.v index 0f3f45687..b78e3d90d 100644 --- a/test_regress/t/t_preproc_persist2.v +++ b/test_regress/t/t_preproc_persist2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 Inside `__FILE__. diff --git a/test_regress/t/t_preproc_persist_inc.v b/test_regress/t/t_preproc_persist_inc.v index 0e62c6b1d..d16add4c7 100644 --- a/test_regress/t/t_preproc_persist_inc.v +++ b/test_regress/t/t_preproc_persist_inc.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `ifndef COMMON_GUARD `define COMMON_GUARD 1 diff --git a/test_regress/t/t_preproc_stringend_bad.out b/test_regress/t/t_preproc_stringend_bad.out index a0c3c04b1..a1d821ac8 100644 --- a/test_regress/t/t_preproc_stringend_bad.out +++ b/test_regress/t/t_preproc_stringend_bad.out @@ -1,2 +1,2 @@ -%Error: t/t_preproc_stringend_bad.v:7: Unterminated string +%Error: t/t_preproc_stringend_bad.v:8:1: Unterminated string %Error: Exiting due to diff --git a/test_regress/t/t_preproc_stringend_bad.pl b/test_regress/t/t_preproc_stringend_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_preproc_stringend_bad.pl +++ b/test_regress/t/t_preproc_stringend_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_preproc_stringend_bad.v b/test_regress/t/t_preproc_stringend_bad.v index 7dfbdde6b..6c7f56c2d 100644 --- a/test_regress/t/t_preproc_stringend_bad.v +++ b/test_regress/t/t_preproc_stringend_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 "Blah diff --git a/test_regress/t/t_preproc_ttempty.pl b/test_regress/t/t_preproc_ttempty.pl index f54f0332d..7c5e3d3c6 100755 --- a/test_regress/t/t_preproc_ttempty.pl +++ b/test_regress/t/t_preproc_ttempty.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2017 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2017 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_preproc_ttempty.v b/test_regress/t/t_preproc_ttempty.v index 572108d87..75fdd9499 100644 --- a/test_regress/t/t_preproc_ttempty.v +++ b/test_regress/t/t_preproc_ttempty.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //`define TARGET_PACKAGE diff --git a/test_regress/t/t_preproc_undefineall.pl b/test_regress/t/t_preproc_undefineall.pl index 056297803..5634c06de 100755 --- a/test_regress/t/t_preproc_undefineall.pl +++ b/test_regress/t/t_preproc_undefineall.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_preproc_undefineall.v b/test_regress/t/t_preproc_undefineall.v index 2f86b17e9..3c233eb5d 100644 --- a/test_regress/t/t_preproc_undefineall.v +++ b/test_regress/t/t_preproc_undefineall.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_program.pl b/test_regress/t/t_program.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_program.pl +++ b/test_regress/t/t_program.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_program.v b/test_regress/t/t_program.v index 4f2436f99..d87524c1f 100644 --- a/test_regress/t/t_program.v +++ b/test_regress/t/t_program.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 program t; initial begin diff --git a/test_regress/t/t_prot_lib.pl b/test_regress/t/t_prot_lib.pl index 2e26dd256..fa5e18254 100755 --- a/test_regress/t/t_prot_lib.pl +++ b/test_regress/t/t_prot_lib.pl @@ -5,10 +5,11 @@ unshift(@ARGV, "--trace"); if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios( vlt => 1, diff --git a/test_regress/t/t_prot_lib.v b/test_regress/t/t_prot_lib.v index 346c54e82..0bd2b0837 100644 --- a/test_regress/t/t_prot_lib.v +++ b/test_regress/t/t_prot_lib.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 `define DRIVE(sig) \ /* Just throw a bunch of bits at the input */ \ diff --git a/test_regress/t/t_prot_lib_clk_gated.pl b/test_regress/t/t_prot_lib_clk_gated.pl index 394bc08b9..9c89a6b89 100755 --- a/test_regress/t/t_prot_lib_clk_gated.pl +++ b/test_regress/t/t_prot_lib_clk_gated.pl @@ -5,10 +5,11 @@ unshift(@ARGV, "--trace"); if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios( vlt => 1, diff --git a/test_regress/t/t_prot_lib_inout_bad.out b/test_regress/t/t_prot_lib_inout_bad.out index 6c5b91eb6..681f98209 100644 --- a/test_regress/t/t_prot_lib_inout_bad.out +++ b/test_regress/t/t_prot_lib_inout_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_prot_lib_inout_bad.v:8: Unsupported: protect-lib port direction: INOUT - inout z, - ^ +%Error: t/t_prot_lib_inout_bad.v:9:28: Unsupported: protect-lib port direction: INOUT + 9 | inout z, + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_prot_lib_inout_bad.pl b/test_regress/t/t_prot_lib_inout_bad.pl index 99abf81a8..3969ea7f3 100755 --- a/test_regress/t/t_prot_lib_inout_bad.pl +++ b/test_regress/t/t_prot_lib_inout_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_prot_lib_inout_bad.v b/test_regress/t/t_prot_lib_inout_bad.v index c083c38cb..5fbd371f0 100644 --- a/test_regress/t/t_prot_lib_inout_bad.v +++ b/test_regress/t/t_prot_lib_inout_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module secret_impl ( input a, diff --git a/test_regress/t/t_prot_lib_secret.pl b/test_regress/t/t_prot_lib_secret.pl index 7af5143ef..1a2556857 100755 --- a/test_regress/t/t_prot_lib_secret.pl +++ b/test_regress/t/t_prot_lib_secret.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_prot_lib_secret.v b/test_regress/t/t_prot_lib_secret.v index 6f0abc1b4..e959c8e42 100644 --- a/test_regress/t/t_prot_lib_secret.v +++ b/test_regress/t/t_prot_lib_secret.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module secret #(parameter GATED_CLK = 0) ( diff --git a/test_regress/t/t_prot_lib_unpacked_bad.out b/test_regress/t/t_prot_lib_unpacked_bad.out index 4c5fa6726..afd642456 100644 --- a/test_regress/t/t_prot_lib_unpacked_bad.out +++ b/test_regress/t/t_prot_lib_unpacked_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_prot_lib_unpacked_bad.v:6: Unsupported: unpacked arrays with protect-lib on 'unpacked_in' - input unpacked_in [7:0], - ^~~~~~~~~~~ -%Error: t/t_prot_lib_unpacked_bad.v:7: Unsupported: unpacked arrays with protect-lib on 'unpacked_out' - output unpacked_out [7:0]); - ^~~~~~~~~~~~ +%Error: t/t_prot_lib_unpacked_bad.v:7:28: Unsupported: unpacked arrays with protect-lib on 'unpacked_in' + 7 | input unpacked_in [7:0], + | ^~~~~~~~~~~ +%Error: t/t_prot_lib_unpacked_bad.v:8:28: Unsupported: unpacked arrays with protect-lib on 'unpacked_out' + 8 | output unpacked_out [7:0]); + | ^~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_prot_lib_unpacked_bad.pl b/test_regress/t/t_prot_lib_unpacked_bad.pl index 99abf81a8..3969ea7f3 100755 --- a/test_regress/t/t_prot_lib_unpacked_bad.pl +++ b/test_regress/t/t_prot_lib_unpacked_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_prot_lib_unpacked_bad.v b/test_regress/t/t_prot_lib_unpacked_bad.v index fb6b5da74..91cfcdffb 100644 --- a/test_regress/t/t_prot_lib_unpacked_bad.v +++ b/test_regress/t/t_prot_lib_unpacked_bad.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module secret_impl ( input unpacked_in [7:0], diff --git a/test_regress/t/t_protect_ids.pl b/test_regress/t/t_protect_ids.pl index b107ea36c..b4c0d2cd4 100755 --- a/test_regress/t/t_protect_ids.pl +++ b/test_regress/t/t_protect_ids.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_protect_ids.v b/test_regress/t/t_protect_ids.v index e82d3e020..ef6bb188a 100644 --- a/test_regress/t/t_protect_ids.v +++ b/test_regress/t/t_protect_ids.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 interface secret_intf(); logic secret_a; diff --git a/test_regress/t/t_protect_ids_bad.pl b/test_regress/t/t_protect_ids_bad.pl index c45b262af..11451f1f9 100755 --- a/test_regress/t/t_protect_ids_bad.pl +++ b/test_regress/t/t_protect_ids_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_protect_ids_bad.v b/test_regress/t/t_protect_ids_bad.v index 52742f831..582a47b4a 100644 --- a/test_regress/t/t_protect_ids_bad.v +++ b/test_regress/t/t_protect_ids_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); endmodule diff --git a/test_regress/t/t_protect_ids_c.cpp b/test_regress/t/t_protect_ids_c.cpp index 63484f67f..36198253e 100644 --- a/test_regress/t/t_protect_ids_c.cpp +++ b/test_regress/t/t_protect_ids_c.cpp @@ -3,13 +3,9 @@ // // Copyright 2009-2009 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_protect_ids_key.pl b/test_regress/t/t_protect_ids_key.pl index 503b3d5bd..d00f7890d 100755 --- a/test_regress/t/t_protect_ids_key.pl +++ b/test_regress/t/t_protect_ids_key.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_queue.pl b/test_regress/t/t_queue.pl index 6b3b15be5..e02817219 100755 --- a/test_regress/t/t_queue.pl +++ b/test_regress/t/t_queue.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_queue.v b/test_regress/t/t_queue.v index 3ec91d79c..a590d33ae 100644 --- a/test_regress/t/t_queue.v +++ b/test_regress/t/t_queue.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); diff --git a/test_regress/t/t_queue_bounded.pl b/test_regress/t/t_queue_bounded.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_queue_bounded.pl +++ b/test_regress/t/t_queue_bounded.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_queue_bounded.v b/test_regress/t/t_queue_bounded.v index f708a0435..e6020465b 100644 --- a/test_regress/t/t_queue_bounded.v +++ b/test_regress/t/t_queue_bounded.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_queue_unsup_bad.out b/test_regress/t/t_queue_unsup_bad.out index 2be8b4f3c..8c82b034b 100644 --- a/test_regress/t/t_queue_unsup_bad.out +++ b/test_regress/t/t_queue_unsup_bad.out @@ -1,61 +1,61 @@ -%Error: t/t_queue_unsup_bad.v:20: Unsupported: Replication to form 'string[$]' data type - : ... In instance t - q = {"q", "b", "c", "d", "e", "f"}; - ^ -%Error: t/t_queue_unsup_bad.v:23: Unsupported: Queue .delete(index) method, as is O(n) complexity and slow. - : ... In instance t - q.delete(1); - ^~~~~~ -%Error: t/t_queue_unsup_bad.v:27: Unsupported: Queue .insert method, as is O(n) complexity and slow. - : ... In instance t - q.insert(2, "ins2"); - ^~~~~~ -%Error: t/t_queue_unsup_bad.v:33: Unsupported: Replication to form 'string[$]' data type - : ... In instance t - q = {q, "f1"}; - ^ -%Error: t/t_queue_unsup_bad.v:34: Unsupported: Replication to form 'string[$]' data type - : ... In instance t - q = {q, "f2"}; - ^ -%Error: t/t_queue_unsup_bad.v:35: Unsupported: Replication to form 'string[$]' data type - : ... In instance t - q = {"b1", q}; - ^ -%Error: t/t_queue_unsup_bad.v:36: Unsupported: Replication to form 'string[$]' data type - : ... In instance t - q = {"b2", q}; - ^ -%Error: t/t_queue_unsup_bad.v:37: Unsupported: Replication to form 'string[$]' data type - : ... In instance t - q = {q[0], q[2:$]}; - ^ -%Error: t/t_queue_unsup_bad.v:37: Unsupported/illegal unbounded ('$') in this context. - : ... In instance t - q = {q[0], q[2:$]}; - ^ -%Error: t/t_queue_unsup_bad.v:37: Expecting expression to be constant, but can't convert a UNBOUNDED to constant. - : ... In instance t - q = {q[0], q[2:$]}; - ^ -%Error: t/t_queue_unsup_bad.v:37: First value of [a:b] isn't a constant, maybe you want +: or -: - : ... In instance t - q = {q[0], q[2:$]}; - ^ -%Error: t/t_queue_unsup_bad.v:37: Illegal range select; type already selected, or bad dimension: data type is 'string[$]' - : ... In instance t - q = {q[0], q[2:$]}; - ^ -%Error: t/t_queue_unsup_bad.v:41: Unsupported: Replication to form 'string[$]' data type - : ... In instance t - string ai[$] = { "Foo", "Bar" }; - ^ -%Error: t/t_queue_unsup_bad.v:46: Unsupported: Assignment pattern applies against non struct/union data type: 'string[$]' - : ... In instance t - q = '{ "BB", "CC" }; - ^~ -%Error: t/t_queue_unsup_bad.v:49: Unsupported: Replication to form 'string[$]' data type - : ... In instance t - q = { "BB", "CC" }; - ^ +%Error: t/t_queue_unsup_bad.v:21:11: Unsupported: Replication to form 'string[$]' data type + : ... In instance t + 21 | q = {"q", "b", "c", "d", "e", "f"}; + | ^ +%Error: t/t_queue_unsup_bad.v:24:9: Unsupported: Queue .delete(index) method, as is O(n) complexity and slow. + : ... In instance t + 24 | q.delete(1); + | ^~~~~~ +%Error: t/t_queue_unsup_bad.v:28:9: Unsupported: Queue .insert method, as is O(n) complexity and slow. + : ... In instance t + 28 | q.insert(2, "ins2"); + | ^~~~~~ +%Error: t/t_queue_unsup_bad.v:34:11: Unsupported: Replication to form 'string[$]' data type + : ... In instance t + 34 | q = {q, "f1"}; + | ^ +%Error: t/t_queue_unsup_bad.v:35:11: Unsupported: Replication to form 'string[$]' data type + : ... In instance t + 35 | q = {q, "f2"}; + | ^ +%Error: t/t_queue_unsup_bad.v:36:11: Unsupported: Replication to form 'string[$]' data type + : ... In instance t + 36 | q = {"b1", q}; + | ^ +%Error: t/t_queue_unsup_bad.v:37:11: Unsupported: Replication to form 'string[$]' data type + : ... In instance t + 37 | q = {"b2", q}; + | ^ +%Error: t/t_queue_unsup_bad.v:38:11: Unsupported: Replication to form 'string[$]' data type + : ... In instance t + 38 | q = {q[0], q[2:$]}; + | ^ +%Error: t/t_queue_unsup_bad.v:38:22: Unsupported/illegal unbounded ('$') in this context. + : ... In instance t + 38 | q = {q[0], q[2:$]}; + | ^ +%Error: t/t_queue_unsup_bad.v:38:22: Expecting expression to be constant, but can't convert a UNBOUNDED to constant. + : ... In instance t + 38 | q = {q[0], q[2:$]}; + | ^ +%Error: t/t_queue_unsup_bad.v:38:22: First value of [a:b] isn't a constant, maybe you want +: or -: + : ... In instance t + 38 | q = {q[0], q[2:$]}; + | ^ +%Error: t/t_queue_unsup_bad.v:38:19: Illegal range select; type already selected, or bad dimension: data type is 'string[$]' + : ... In instance t + 38 | q = {q[0], q[2:$]}; + | ^ +%Error: t/t_queue_unsup_bad.v:42:25: Unsupported: Replication to form 'string[$]' data type + : ... In instance t + 42 | string ai[$] = { "Foo", "Bar" }; + | ^ +%Error: t/t_queue_unsup_bad.v:47:14: Unsupported: Assignment pattern applies against non struct/union data type: 'string[$]' + : ... In instance t + 47 | q = '{ "BB", "CC" }; + | ^~ +%Error: t/t_queue_unsup_bad.v:50:14: Unsupported: Replication to form 'string[$]' data type + : ... In instance t + 50 | q = { "BB", "CC" }; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_queue_unsup_bad.pl b/test_regress/t/t_queue_unsup_bad.pl index adc555a8d..bfd1147c6 100755 --- a/test_regress/t/t_queue_unsup_bad.pl +++ b/test_regress/t/t_queue_unsup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_queue_unsup_bad.v b/test_regress/t/t_queue_unsup_bad.v index 2cffaedae..e58e21113 100644 --- a/test_regress/t/t_queue_unsup_bad.v +++ b/test_regress/t/t_queue_unsup_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); diff --git a/test_regress/t/t_real_param.pl b/test_regress/t/t_real_param.pl index b78f33caa..f4ca8a9d8 100755 --- a/test_regress/t/t_real_param.pl +++ b/test_regress/t/t_real_param.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_real_param.v b/test_regress/t/t_real_param.v index 99b07ac94..16737272a 100644 --- a/test_regress/t/t_real_param.v +++ b/test_regress/t/t_real_param.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module foo #( parameter real bar = 2.0) diff --git a/test_regress/t/t_reloop_cam.pl b/test_regress/t/t_reloop_cam.pl index bd17b5a29..6136a1112 100755 --- a/test_regress/t/t_reloop_cam.pl +++ b/test_regress/t/t_reloop_cam.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_reloop_cam.v b/test_regress/t/t_reloop_cam.v index cda35471d..4333577ec 100644 --- a/test_regress/t/t_reloop_cam.v +++ b/test_regress/t/t_reloop_cam.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_repeat.pl b/test_regress/t/t_repeat.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_repeat.pl +++ b/test_regress/t/t_repeat.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_repeat.v b/test_regress/t/t_repeat.v index 9d0c1a356..49fcca977 100644 --- a/test_regress/t/t_repeat.v +++ b/test_regress/t/t_repeat.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_rnd.pl b/test_regress/t/t_rnd.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_rnd.pl +++ b/test_regress/t/t_rnd.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_rnd.v b/test_regress/t/t_rnd.v index c080df8a3..0cc259988 100644 --- a/test_regress/t/t_rnd.v +++ b/test_regress/t/t_rnd.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_runflag.pl b/test_regress/t/t_runflag.pl index 7f80734c0..99dd267a6 100755 --- a/test_regress/t/t_runflag.pl +++ b/test_regress/t/t_runflag.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_runflag.v b/test_regress/t/t_runflag.v index 5edda933b..ff98975dc 100644 --- a/test_regress/t/t_runflag.v +++ b/test_regress/t/t_runflag.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; initial begin diff --git a/test_regress/t/t_runflag_errorlimit.out b/test_regress/t/t_runflag_errorlimit.out index 1a0255428..223b5e2e5 100644 --- a/test_regress/t/t_runflag_errorlimit.out +++ b/test_regress/t/t_runflag_errorlimit.out @@ -1,7 +1,7 @@ -[0] %Error: t_runflag_errorlimit.v:8: Assertion failed in top.t: One --Info: t/t_runflag_errorlimit.v:8: Verilog $stop, ignored due to +verilator+error+limit -[0] %Error: t_runflag_errorlimit.v:9: Assertion failed in top.t: Two +[0] %Error: t_runflag_errorlimit.v:9: Assertion failed in top.t: One -Info: t/t_runflag_errorlimit.v:9: Verilog $stop, ignored due to +verilator+error+limit -[0] %Error: t_runflag_errorlimit.v:10: Assertion failed in top.t: Three -%Error: t/t_runflag_errorlimit.v:10: Verilog $stop +[0] %Error: t_runflag_errorlimit.v:10: Assertion failed in top.t: Two +-Info: t/t_runflag_errorlimit.v:10: Verilog $stop, ignored due to +verilator+error+limit +[0] %Error: t_runflag_errorlimit.v:11: Assertion failed in top.t: Three +%Error: t/t_runflag_errorlimit.v:11: Verilog $stop Aborting... diff --git a/test_regress/t/t_runflag_errorlimit.pl b/test_regress/t/t_runflag_errorlimit.pl index fed6bf129..638425fb0 100755 --- a/test_regress/t/t_runflag_errorlimit.pl +++ b/test_regress/t/t_runflag_errorlimit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_runflag_errorlimit.v b/test_regress/t/t_runflag_errorlimit.v index 7487479b7..00ef993e9 100644 --- a/test_regress/t/t_runflag_errorlimit.v +++ b/test_regress/t/t_runflag_errorlimit.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; initial begin diff --git a/test_regress/t/t_runflag_seed.pl b/test_regress/t/t_runflag_seed.pl index f5639384e..d30b5a08d 100755 --- a/test_regress/t/t_runflag_seed.pl +++ b/test_regress/t/t_runflag_seed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_runflag_seed.v b/test_regress/t/t_runflag_seed.v index 16e901d19..74d90f219 100644 --- a/test_regress/t/t_runflag_seed.v +++ b/test_regress/t/t_runflag_seed.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_savable.pl b/test_regress/t/t_savable.pl index 942feae4d..f693b79f4 100755 --- a/test_regress/t/t_savable.pl +++ b/test_regress/t/t_savable.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_savable.v b/test_regress/t/t_savable.v index ac168cf85..76b18144f 100644 --- a/test_regress/t/t_savable.v +++ b/test_regress/t/t_savable.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_scope_map.cpp b/test_regress/t/t_scope_map.cpp index 4179e9c7c..ca00e8cb0 100644 --- a/test_regress/t/t_scope_map.cpp +++ b/test_regress/t/t_scope_map.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include diff --git a/test_regress/t/t_scope_map.pl b/test_regress/t/t_scope_map.pl index e93d68454..ac72b1aa1 100755 --- a/test_regress/t/t_scope_map.pl +++ b/test_regress/t/t_scope_map.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2015 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2015 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_scope_map.v b/test_regress/t/t_scope_map.v index a69acdb26..1ba241d96 100644 --- a/test_regress/t/t_scope_map.v +++ b/test_regress/t/t_scope_map.v @@ -3,6 +3,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_select_bad_msb.out b/test_regress/t/t_select_bad_msb.out index 08edfb421..98533f4d2 100644 --- a/test_regress/t/t_select_bad_msb.out +++ b/test_regress/t/t_select_bad_msb.out @@ -1,9 +1,9 @@ -%Warning-LITENDIAN: t/t_select_bad_msb.v:11: Little bit endian vector: MSB < LSB of bit range: 0:22 - reg [0:22] backwd; - ^ +%Warning-LITENDIAN: t/t_select_bad_msb.v:12:8: Little bit endian vector: MSB < LSB of bit range: 0:22 + 12 | reg [0:22] backwd; + | ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. -%Error: t/t_select_bad_msb.v:15: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1] - : ... In instance t - sel2 = mi[1:4]; - ^ +%Error: t/t_select_bad_msb.v:16:16: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1] + : ... In instance t + 16 | sel2 = mi[1:4]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_msb.pl b/test_regress/t/t_select_bad_msb.pl index b3eb5b75d..92e61ce57 100755 --- a/test_regress/t/t_select_bad_msb.pl +++ b/test_regress/t/t_select_bad_msb.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_select_bad_msb.v b/test_regress/t/t_select_bad_msb.v index 26198e9cf..cbcd8f2c2 100644 --- a/test_regress/t/t_select_bad_msb.v +++ b/test_regress/t/t_select_bad_msb.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_select_bad_range.out b/test_regress/t/t_select_bad_range.out index 189af895f..c72a978d5 100644 --- a/test_regress/t/t_select_bad_range.out +++ b/test_regress/t/t_select_bad_range.out @@ -1,10 +1,10 @@ -%Warning-SELRANGE: t/t_select_bad_range.v:15: Selection index out of range: 44:44 outside 43:0 - : ... In instance t - sel = mi[44]; - ^ +%Warning-SELRANGE: t/t_select_bad_range.v:16:15: Selection index out of range: 44:44 outside 43:0 + : ... In instance t + 16 | sel = mi[44]; + | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. -%Warning-SELRANGE: t/t_select_bad_range.v:16: Selection index out of range: 44:41 outside 43:0 - : ... In instance t - sel2 = mi[44:41]; - ^ +%Warning-SELRANGE: t/t_select_bad_range.v:17:16: Selection index out of range: 44:41 outside 43:0 + : ... In instance t + 17 | sel2 = mi[44:41]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range.pl b/test_regress/t/t_select_bad_range.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_select_bad_range.pl +++ b/test_regress/t/t_select_bad_range.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_select_bad_range.v b/test_regress/t/t_select_bad_range.v index dee1f0433..deb03f130 100644 --- a/test_regress/t/t_select_bad_range.v +++ b/test_regress/t/t_select_bad_range.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_select_bad_range2.out b/test_regress/t/t_select_bad_range2.out index 68a68164c..fc2bb2d0d 100644 --- a/test_regress/t/t_select_bad_range2.out +++ b/test_regress/t/t_select_bad_range2.out @@ -1,6 +1,6 @@ -%Warning-SELRANGE: t/t_select_bad_range2.v:50: Selection index out of range: 3:2 outside 1:0 - : ... In instance t.test - assign out32 = in[3:2]; - ^ +%Warning-SELRANGE: t/t_select_bad_range2.v:51:21: Selection index out of range: 3:2 outside 1:0 + : ... In instance t.test + 51 | assign out32 = in[3:2]; + | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range2.pl b/test_regress/t/t_select_bad_range2.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_select_bad_range2.pl +++ b/test_regress/t/t_select_bad_range2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_select_bad_range2.v b/test_regress/t/t_select_bad_range2.v index 942195c05..ae1ab47d9 100644 --- a/test_regress/t/t_select_bad_range2.v +++ b/test_regress/t/t_select_bad_range2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_bad_range3.out b/test_regress/t/t_select_bad_range3.out index 1ba08436d..30c14d08d 100644 --- a/test_regress/t/t_select_bad_range3.out +++ b/test_regress/t/t_select_bad_range3.out @@ -1,6 +1,6 @@ -%Warning-SELRANGE: t/t_select_bad_range3.v:18: Selection index out of range: 13 outside 12:10 - : ... In instance t - assign outwires[12] = inwires[13]; - ^ +%Warning-SELRANGE: t/t_select_bad_range3.v:19:33: Selection index out of range: 13 outside 12:10 + : ... In instance t + 19 | assign outwires[12] = inwires[13]; + | ^ ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range3.pl b/test_regress/t/t_select_bad_range3.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_select_bad_range3.pl +++ b/test_regress/t/t_select_bad_range3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_select_bad_range3.v b/test_regress/t/t_select_bad_range3.v index 11e2928b3..3a788636e 100644 --- a/test_regress/t/t_select_bad_range3.v +++ b/test_regress/t/t_select_bad_range3.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2015 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2015 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_select_bad_tri.out b/test_regress/t/t_select_bad_tri.out index 37a5a5458..fd015e9f8 100644 --- a/test_regress/t/t_select_bad_tri.out +++ b/test_regress/t/t_select_bad_tri.out @@ -1,5 +1,5 @@ -%Error: t/t_select_bad_tri.v:10: Selection index is constantly unknown or tristated: lsb=7'bxxxxxxx width=32'sh47 - : ... In instance t - if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; - ^ +%Error: t/t_select_bad_tri.v:11:13: Selection index is constantly unknown or tristated: lsb=7'bxxxxxxx width=32'sh47 + : ... In instance t + 11 | if (in[( (1'h0 / 1'b0) )+:71] != 71'h0) $stop; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_tri.pl b/test_regress/t/t_select_bad_tri.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_select_bad_tri.pl +++ b/test_regress/t/t_select_bad_tri.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_select_bad_tri.v b/test_regress/t/t_select_bad_tri.v index e7eed140e..1e272a53e 100644 --- a/test_regress/t/t_select_bad_tri.v +++ b/test_regress/t/t_select_bad_tri.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_select_bound1.pl b/test_regress/t/t_select_bound1.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_bound1.pl +++ b/test_regress/t/t_select_bound1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_bound1.v b/test_regress/t/t_select_bound1.v index 8c57e1802..af2861c60 100644 --- a/test_regress/t/t_select_bound1.v +++ b/test_regress/t/t_select_bound1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug823 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_bound2.pl b/test_regress/t/t_select_bound2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_bound2.pl +++ b/test_regress/t/t_select_bound2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_bound2.v b/test_regress/t/t_select_bound2.v index ff6600d0a..681a92457 100644 --- a/test_regress/t/t_select_bound2.v +++ b/test_regress/t/t_select_bound2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug823 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_select_index.pl b/test_regress/t/t_select_index.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_index.pl +++ b/test_regress/t/t_select_index.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_index.v b/test_regress/t/t_select_index.v index 53ab68565..65ad39660 100644 --- a/test_regress/t/t_select_index.v +++ b/test_regress/t/t_select_index.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003-2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003-2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_index2.pl b/test_regress/t/t_select_index2.pl index 0bafa73ba..a4d74c0ba 100755 --- a/test_regress/t/t_select_index2.pl +++ b/test_regress/t/t_select_index2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_select_index2.v b/test_regress/t/t_select_index2.v index 475550c9c..87cca6568 100644 --- a/test_regress/t/t_select_index2.v +++ b/test_regress/t/t_select_index2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_lhs_oob.pl b/test_regress/t/t_select_lhs_oob.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_lhs_oob.pl +++ b/test_regress/t/t_select_lhs_oob.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_lhs_oob.v b/test_regress/t/t_select_lhs_oob.v index 82dc65ab6..b34470849 100644 --- a/test_regress/t/t_select_lhs_oob.v +++ b/test_regress/t/t_select_lhs_oob.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_lhs_oob2.pl b/test_regress/t/t_select_lhs_oob2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_lhs_oob2.pl +++ b/test_regress/t/t_select_lhs_oob2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_lhs_oob2.v b/test_regress/t/t_select_lhs_oob2.v index 1c33db94d..10cff1cf9 100644 --- a/test_regress/t/t_select_lhs_oob2.v +++ b/test_regress/t/t_select_lhs_oob2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_little.pl b/test_regress/t/t_select_little.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_little.pl +++ b/test_regress/t/t_select_little.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_little.v b/test_regress/t/t_select_little.v index 8840fcbe1..2b7b9e93c 100644 --- a/test_regress/t/t_select_little.v +++ b/test_regress/t/t_select_little.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_little_pack.pl b/test_regress/t/t_select_little_pack.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_little_pack.pl +++ b/test_regress/t/t_select_little_pack.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_little_pack.v b/test_regress/t/t_select_little_pack.v index cf2b8b37c..e265f3b1f 100644 --- a/test_regress/t/t_select_little_pack.v +++ b/test_regress/t/t_select_little_pack.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_loop.pl b/test_regress/t/t_select_loop.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_loop.pl +++ b/test_regress/t/t_select_loop.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_loop.v b/test_regress/t/t_select_loop.v index 42dc3605c..c057d4b91 100644 --- a/test_regress/t/t_select_loop.v +++ b/test_regress/t/t_select_loop.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_negative.pl b/test_regress/t/t_select_negative.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_negative.pl +++ b/test_regress/t/t_select_negative.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_negative.v b/test_regress/t/t_select_negative.v index a75eb061c..bd0e66687 100644 --- a/test_regress/t/t_select_negative.v +++ b/test_regress/t/t_select_negative.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_param.pl b/test_regress/t/t_select_param.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_param.pl +++ b/test_regress/t/t_select_param.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_param.v b/test_regress/t/t_select_param.v index 12b835729..a8830d6b4 100644 --- a/test_regress/t/t_select_param.v +++ b/test_regress/t/t_select_param.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; parameter [ BMSB : BLSB ] B = A[23:20]; // 3 diff --git a/test_regress/t/t_select_plus.pl b/test_regress/t/t_select_plus.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_plus.pl +++ b/test_regress/t/t_select_plus.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_plus.v b/test_regress/t/t_select_plus.v index 0d078c374..9d9e55879 100644 --- a/test_regress/t/t_select_plus.v +++ b/test_regress/t/t_select_plus.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_plusloop.pl b/test_regress/t/t_select_plusloop.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_plusloop.pl +++ b/test_regress/t/t_select_plusloop.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_plusloop.v b/test_regress/t/t_select_plusloop.v index b15b01019..58249e4ee 100644 --- a/test_regress/t/t_select_plusloop.v +++ b/test_regress/t/t_select_plusloop.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_select_runtime_range.pl b/test_regress/t/t_select_runtime_range.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_runtime_range.pl +++ b/test_regress/t/t_select_runtime_range.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_runtime_range.v b/test_regress/t/t_select_runtime_range.v index 85e32018c..b43330e11 100644 --- a/test_regress/t/t_select_runtime_range.v +++ b/test_regress/t/t_select_runtime_range.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_select_set.pl b/test_regress/t/t_select_set.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_select_set.pl +++ b/test_regress/t/t_select_set.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_select_set.v b/test_regress/t/t_select_set.v index ff6d97bc1..30054a00e 100644 --- a/test_regress/t/t_select_set.v +++ b/test_regress/t/t_select_set.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_slice_cond.pl b/test_regress/t/t_slice_cond.pl index 5c448de7c..d1bf185c9 100755 --- a/test_regress/t/t_slice_cond.pl +++ b/test_regress/t/t_slice_cond.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_slice_cond.v b/test_regress/t/t_slice_cond.v index 7e3be3c92..8560bbce0 100644 --- a/test_regress/t/t_slice_cond.v +++ b/test_regress/t/t_slice_cond.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_slice_init.pl b/test_regress/t/t_slice_init.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_slice_init.pl +++ b/test_regress/t/t_slice_init.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_slice_init.v b/test_regress/t/t_slice_init.v index 828a914eb..b1901f7a6 100644 --- a/test_regress/t/t_slice_init.v +++ b/test_regress/t/t_slice_init.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_slice_struct_array_modport.pl b/test_regress/t/t_slice_struct_array_modport.pl index 0bafa73ba..a4d74c0ba 100755 --- a/test_regress/t/t_slice_struct_array_modport.pl +++ b/test_regress/t/t_slice_struct_array_modport.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_slice_struct_array_modport.v b/test_regress/t/t_slice_struct_array_modport.v index 18c90a8fd..d13ac77bb 100644 --- a/test_regress/t/t_slice_struct_array_modport.v +++ b/test_regress/t/t_slice_struct_array_modport.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Varun Koyyalagunta. +// SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic p; diff --git a/test_regress/t/t_split_var_0.pl b/test_regress/t/t_split_var_0.pl index b74a78821..b401de638 100755 --- a/test_regress/t/t_split_var_0.pl +++ b/test_regress/t/t_split_var_0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -13,7 +14,8 @@ scenarios(simulator => 1); # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performace wise, but ok. compile( - verilator_flags2 => ['--stats' . ($Self->{vltmt} ? ' --threads 6' : '')], + verilator_flags2 => ['--stats' . ($Self->{vltmt} ? ' --threads 6' : ''), + "$Self->{t_dir}/t_split_var_0.vlt"], ); execute( diff --git a/test_regress/t/t_split_var_0.v b/test_regress/t/t_split_var_0.v index d7111f948..507b5469e 100644 --- a/test_regress/t/t_split_var_0.v +++ b/test_regress/t/t_split_var_0.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA. +// SPDX-License-Identifier: CC0-1.0 // If split_var pragma is removed, UNOPTFLAT appears. @@ -9,7 +10,11 @@ module barshift_1d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH) (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out /*verilator split_var*/); localparam OFFSET = -3; +`ifdef TEST_ATTRIBUTES logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET] /*verilator split_var*/; +`else + logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET]; +`endif generate for(genvar i = 0; i < DEPTH; ++i) begin always_comb diff --git a/test_regress/t/t_split_var_0.vlt b/test_regress/t/t_split_var_0.vlt new file mode 100644 index 000000000..1f346a112 --- /dev/null +++ b/test_regress/t/t_split_var_0.vlt @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2020 by Marco Widmer. +// SPDX-License-Identifier: CC0-1.0 + +`verilator_config + +split_var -module "barshift_1d_unpacked" -var "tmp" diff --git a/test_regress/t/t_split_var_1_bad.out b/test_regress/t/t_split_var_1_bad.out index 197e42cdb..b51f38b0b 100644 --- a/test_regress/t/t_split_var_1_bad.out +++ b/test_regress/t/t_split_var_1_bad.out @@ -1,65 +1,65 @@ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:6: 'should_show_warning_global0' has split_var metacomment, but will not be split because it is not declared in a module. -logic [7:0] should_show_warning_global0 /*verilator split_var*/ ; - ^~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:7:13: 'should_show_warning_global0' has split_var metacomment, but will not be split because it is not declared in a module. + 7 | logic [7:0] should_show_warning_global0 /*verilator split_var*/ ; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ ... Use "/* verilator lint_off SPLITVAR */" and lint_on around source to disable this message. -%Warning-SPLITVAR: t/t_split_var_1_bad.v:7: 'should_show_warning_global1' has split_var metacomment, but will not be split because it is not declared in a module. -logic [7:0] should_show_warning_global1 [1:0] /*verilator split_var*/ ; - ^~~~~~~~~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:10: 'should_show_warning_ifs0' has split_var metacomment, but will not be split because it is not declared in a module. - logic [7:0] should_show_warning_ifs0 /*verilator split_var*/ ; - ^~~~~~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:11: 'should_show_warning_ifs1' has split_var metacomment, but will not be split because it is not declared in a module. - logic [7:0] should_show_warning_ifs1 [1:0] /*verilator split_var*/ ; - ^~~~~~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:37: 'cannot_split1' has split_var metacomment but will not be split because it is accessed from another module via a dot. - i_sub0.cannot_split1[0] = 0; - ^~~~~~~~~~~~~ -%Warning-SELRANGE: t/t_split_var_1_bad.v:82: Selection index out of range: 13 outside 12:10 - : ... In instance t.i_sub3 - assign outwires[12] = inwires[13]; - ^ -%Warning-WIDTH: t/t_split_var_1_bad.v:38: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits. - : ... In instance t - i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); - ^ -%Error: t/t_split_var_1_bad.v:71: Illegal assignment of constant to unpacked array - : ... In instance t.i_sub2 - assign b = a[0]; - ^ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:50: 'cannot_split0' has split_var metacomment but will not be split because index cannot be determined statically. - : ... In instance t.i_sub0 - rd_data = cannot_split0[addr]; - ^~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:82: 'inwires' has split_var metacomment but will not be split because index is out of range. - : ... In instance t.i_sub3 - assign outwires[12] = inwires[13]; - ^~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:16: 'should_show_warning0' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic +%Warning-SPLITVAR: t/t_split_var_1_bad.v:8:13: 'should_show_warning_global1' has split_var metacomment, but will not be split because it is not declared in a module. + 8 | logic [7:0] should_show_warning_global1 [1:0] /*verilator split_var*/ ; + | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:11:16: 'should_show_warning_ifs0' has split_var metacomment, but will not be split because it is not declared in a module. + 11 | logic [7:0] should_show_warning_ifs0 /*verilator split_var*/ ; + | ^~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:12:16: 'should_show_warning_ifs1' has split_var metacomment, but will not be split because it is not declared in a module. + 12 | logic [7:0] should_show_warning_ifs1 [1:0] /*verilator split_var*/ ; + | ^~~~~~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:38:14: 'cannot_split1' has split_var metacomment but will not be split because it is accessed from another module via a dot. + 38 | i_sub0.cannot_split1[0] = 0; + | ^~~~~~~~~~~~~ +%Warning-SELRANGE: t/t_split_var_1_bad.v:83:33: Selection index out of range: 13 outside 12:10 + : ... In instance t.i_sub3 + 83 | assign outwires[12] = inwires[13]; + | ^ +%Warning-WIDTH: t/t_split_var_1_bad.v:39:31: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS's FUNCREF 'bad_func' generates 32 bits. : ... In instance t - real should_show_warning0 /*verilator split_var*/ ; - ^~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:17: 'should_show_warning1' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic - : ... In instance t - string should_show_warning1 /*verilator split_var*/ ; - ^~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:18: 'should_show_warning2' has split_var metacomment but will not be split because its bitwidth is 1 - : ... In instance t - wire should_show_warning2 /*verilator split_var*/ ; - ^~~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:29: 'inout_port' has split_var metacomment but will not be split because it is an inout port - : ... In instance t - function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/ , - ^~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:30: 'ref_port' has split_var metacomment but will not be split because it is a ref argument - : ... In instance t - ref logic [7:0] ref_port /*verilator split_var*/ ); - ^~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:56: 'cannot_split_genvar' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic - : ... In instance t.i_sub1 - genvar cannot_split_genvar /*verilator split_var*/ ; - ^~~~~~~~~~~~~~~~~~~ -%Warning-SPLITVAR: t/t_split_var_1_bad.v:59: 'cannot_split' has split_var metacomment but will not be split because its bit range cannot be determined statically. - : ... In instance t.i_sub1 - rd_data = cannot_split[addr]; - ^ + 39 | i_sub0.cannot_split1[1] = bad_func(addr, rd_data0); + | ^ +%Error: t/t_split_var_1_bad.v:72:16: Illegal assignment of constant to unpacked array + : ... In instance t.i_sub2 + 72 | assign b = a[0]; + | ^ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:51:31: 'cannot_split0' has split_var metacomment but will not be split because index cannot be determined statically. + : ... In instance t.i_sub0 + 51 | rd_data = cannot_split0[addr]; + | ^~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:83:34: 'inwires' has split_var metacomment but will not be split because index is out of range. + : ... In instance t.i_sub3 + 83 | assign outwires[12] = inwires[13]; + | ^~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:17:9: 'should_show_warning0' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic + : ... In instance t + 17 | real should_show_warning0 /*verilator split_var*/ ; + | ^~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:18:11: 'should_show_warning1' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic + : ... In instance t + 18 | string should_show_warning1 /*verilator split_var*/ ; + | ^~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:19:11: 'should_show_warning2' has split_var metacomment but will not be split because its bitwidth is 1 + : ... In instance t + 19 | wire should_show_warning2 /*verilator split_var*/ ; + | ^~~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:30:44: 'inout_port' has split_var metacomment but will not be split because it is an inout port + : ... In instance t + 30 | function int bad_func(inout logic [3:0] inout_port /*verilator split_var*/ , + | ^~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:31:42: 'ref_port' has split_var metacomment but will not be split because it is a ref argument + : ... In instance t + 31 | ref logic [7:0] ref_port /*verilator split_var*/ ); + | ^~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:57:11: 'cannot_split_genvar' has split_var metacomment but will not be split because it is not an aggregate type of bit nor logic + : ... In instance t.i_sub1 + 57 | genvar cannot_split_genvar /*verilator split_var*/ ; + | ^~~~~~~~~~~~~~~~~~~ +%Warning-SPLITVAR: t/t_split_var_1_bad.v:60:29: 'cannot_split' has split_var metacomment but will not be split because its bit range cannot be determined statically. + : ... In instance t.i_sub1 + 60 | rd_data = cannot_split[addr]; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_split_var_1_bad.pl b/test_regress/t/t_split_var_1_bad.pl index 5b8e1ff31..16d5325a7 100755 --- a/test_regress/t/t_split_var_1_bad.pl +++ b/test_regress/t/t_split_var_1_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_split_var_1_bad.v b/test_regress/t/t_split_var_1_bad.v index d3e5b9e04..27868479a 100644 --- a/test_regress/t/t_split_var_1_bad.v +++ b/test_regress/t/t_split_var_1_bad.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2020 by Yutetsu TAKATSUKASA. +// SPDX-License-Identifier: CC0-1.0 logic [7:0] should_show_warning_global0 /* verilator split_var */; logic [7:0] should_show_warning_global1 [1:0] /* verilator split_var */; diff --git a/test_regress/t/t_split_var_2_trace.pl b/test_regress/t/t_split_var_2_trace.pl index 64a77d139..0d815e82b 100755 --- a/test_regress/t/t_split_var_2_trace.pl +++ b/test_regress/t/t_split_var_2_trace.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); top_filename("t/t_split_var_0.v"); @@ -14,7 +15,8 @@ top_filename("t/t_split_var_0.v"); # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. # So use 6 threads here though it's not optimal in performace wise, but ok. compile( - verilator_flags2 => ['--cc --trace --stats' . ($Self->{vltmt} ? ' --threads 6' : '')], + verilator_flags2 => ['--cc --trace --stats' . ($Self->{vltmt} ? ' --threads 6' : ''), + '+define+TEST_ATTRIBUTES'], ); execute( diff --git a/test_regress/t/t_static_elab.pl b/test_regress/t/t_static_elab.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_static_elab.pl +++ b/test_regress/t/t_static_elab.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_static_elab.v b/test_regress/t/t_static_elab.v index 213d7af67..afb29e374 100644 --- a/test_regress/t/t_static_elab.v +++ b/test_regress/t/t_static_elab.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_stop_bad.out b/test_regress/t/t_stop_bad.out index a5b0b94b3..f22e6a47a 100644 --- a/test_regress/t/t_stop_bad.out +++ b/test_regress/t/t_stop_bad.out @@ -1,3 +1,3 @@ Intentional stop -%Error: t/t_stop_bad.v:9: Verilog $stop +%Error: t/t_stop_bad.v:10: Verilog $stop Aborting... diff --git a/test_regress/t/t_stop_bad.pl b/test_regress/t/t_stop_bad.pl index 477a847d8..16bcd07b8 100755 --- a/test_regress/t/t_stop_bad.pl +++ b/test_regress/t/t_stop_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_stop_bad.v b/test_regress/t/t_stop_bad.v index 950a2d00f..6fd1152fa 100644 --- a/test_regress/t/t_stop_bad.v +++ b/test_regress/t/t_stop_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; initial begin diff --git a/test_regress/t/t_stream.pl b/test_regress/t/t_stream.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_stream.pl +++ b/test_regress/t/t_stream.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_stream.v b/test_regress/t/t_stream.v index e41a54af9..22b16f59c 100644 --- a/test_regress/t/t_stream.v +++ b/test_regress/t/t_stream.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Glen Gibb. +// SPDX-License-Identifier: CC0-1.0 //module t; module t (/*AUTOARG*/ diff --git a/test_regress/t/t_stream2.pl b/test_regress/t/t_stream2.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_stream2.pl +++ b/test_regress/t/t_stream2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_stream2.v b/test_regress/t/t_stream2.v index 148b28e2c..65d07ffe8 100644 --- a/test_regress/t/t_stream2.v +++ b/test_regress/t/t_stream2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_stream3.pl b/test_regress/t/t_stream3.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_stream3.pl +++ b/test_regress/t/t_stream3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_stream3.v b/test_regress/t/t_stream3.v index ec0f4bce4..76e40a5fc 100644 --- a/test_regress/t/t_stream3.v +++ b/test_regress/t/t_stream3.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0) diff --git a/test_regress/t/t_string.pl b/test_regress/t/t_string.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_string.pl +++ b/test_regress/t/t_string.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_string.v b/test_regress/t/t_string.v index e06cb2a2e..11bf3ac16 100644 --- a/test_regress/t/t_string.v +++ b/test_regress/t/t_string.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got=\"%s\" exp=\"%s\"\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_string_type_methods.pl b/test_regress/t/t_string_type_methods.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_string_type_methods.pl +++ b/test_regress/t/t_string_type_methods.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_string_type_methods.v b/test_regress/t/t_string_type_methods.v index 180090b7a..85e410d71 100644 --- a/test_regress/t/t_string_type_methods.v +++ b/test_regress/t/t_string_type_methods.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); `define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_string_type_methods_bad.out b/test_regress/t/t_string_type_methods_bad.out index 92116ca77..69015ba0f 100644 --- a/test_regress/t/t_string_type_methods_bad.out +++ b/test_regress/t/t_string_type_methods_bad.out @@ -1,13 +1,13 @@ -%Error: t/t_string_type_methods_bad.v:14: The 1 arguments passed to .len method does not match its requiring 0 arguments - : ... In instance t - i = s.len(0); - ^~~ -%Error: t/t_string_type_methods_bad.v:15: The 0 arguments passed to .itoa method does not match its requiring 1 arguments - : ... In instance t - s.itoa; - ^~~~ -%Error: t/t_string_type_methods_bad.v:16: The 3 arguments passed to .itoa method does not match its requiring 1 arguments - : ... In instance t - s.itoa(1,2,3); - ^~~~ +%Error: t/t_string_type_methods_bad.v:15:13: The 1 arguments passed to .len method does not match its requiring 0 arguments + : ... In instance t + 15 | i = s.len(0); + | ^~~ +%Error: t/t_string_type_methods_bad.v:16:9: The 0 arguments passed to .itoa method does not match its requiring 1 arguments + : ... In instance t + 16 | s.itoa; + | ^~~~ +%Error: t/t_string_type_methods_bad.v:17:9: The 3 arguments passed to .itoa method does not match its requiring 1 arguments + : ... In instance t + 17 | s.itoa(1,2,3); + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_string_type_methods_bad.pl b/test_regress/t/t_string_type_methods_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_string_type_methods_bad.pl +++ b/test_regress/t/t_string_type_methods_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_string_type_methods_bad.v b/test_regress/t/t_string_type_methods_bad.v index 851cc0338..45c845d0b 100644 --- a/test_regress/t/t_string_type_methods_bad.v +++ b/test_regress/t/t_string_type_methods_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_struct_anon.pl b/test_regress/t/t_struct_anon.pl index 0bafa73ba..a4d74c0ba 100755 --- a/test_regress/t/t_struct_anon.pl +++ b/test_regress/t/t_struct_anon.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_struct_anon.v b/test_regress/t/t_struct_anon.v index cad5c4144..5793e88c7 100644 --- a/test_regress/t/t_struct_anon.v +++ b/test_regress/t/t_struct_anon.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Anonymous struct packed { diff --git a/test_regress/t/t_struct_array.pl b/test_regress/t/t_struct_array.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_array.pl +++ b/test_regress/t/t_struct_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_array.v b/test_regress/t/t_struct_array.v index 614e537e3..9ea97e318 100644 --- a/test_regress/t/t_struct_array.v +++ b/test_regress/t/t_struct_array.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 package TEST_TYPES; typedef struct packed { diff --git a/test_regress/t/t_struct_genfor.pl b/test_regress/t/t_struct_genfor.pl new file mode 100755 index 000000000..a4d74c0ba --- /dev/null +++ b/test_regress/t/t_struct_genfor.pl @@ -0,0 +1,16 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint(); + +ok(1); +1; diff --git a/test_regress/t/t_struct_genfor.v b/test_regress/t/t_struct_genfor.v new file mode 100644 index 000000000..41af7634d --- /dev/null +++ b/test_regress/t/t_struct_genfor.v @@ -0,0 +1,25 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (); + + for (genvar g = 0; g < 2; ++g) begin : genfor + typedef struct packed { + logic [31:0] val1; + logic [31:0] val2; + } struct_t; + struct_t forvar; + + initial begin + forvar.val1 = 1; + forvar.val2 = 2; + if (forvar.val1 != 1) $stop; + if (forvar.val2 != 2) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule diff --git a/test_regress/t/t_struct_init.pl b/test_regress/t/t_struct_init.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_init.pl +++ b/test_regress/t/t_struct_init.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_init.v b/test_regress/t/t_struct_init.v index 914ac28cd..81f0b2263 100644 --- a/test_regress/t/t_struct_init.v +++ b/test_regress/t/t_struct_init.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_struct_init_bad.out b/test_regress/t/t_struct_init_bad.out index 57615827a..739b169af 100644 --- a/test_regress/t/t_struct_init_bad.out +++ b/test_regress/t/t_struct_init_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_struct_init.v:53: Assignment pattern contains duplicate entry: b1 - : ... In instance t - const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1}; - ^~ +%Error: t/t_struct_init.v:54:40: Assignment pattern contains duplicate entry: b1 + : ... In instance t + 54 | const b4_t b4_const_c = '{b1: 1'b1, b1: 1'b0, b0:1'b0, b2: 1'b1, b3: 1'b1}; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_struct_init_bad.pl b/test_regress/t/t_struct_init_bad.pl index 5fe79d7c0..682abbc5e 100755 --- a/test_regress/t/t_struct_init_bad.pl +++ b/test_regress/t/t_struct_init_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_init_trace.pl b/test_regress/t/t_struct_init_trace.pl index 972550651..6ff009330 100755 --- a/test_regress/t/t_struct_init_trace.pl +++ b/test_regress/t/t_struct_init_trace.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_nest.pl b/test_regress/t/t_struct_nest.pl index 0bafa73ba..a4d74c0ba 100755 --- a/test_regress/t/t_struct_nest.pl +++ b/test_regress/t/t_struct_nest.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_struct_nest.v b/test_regress/t/t_struct_nest.v index 9059568f3..549abd217 100644 --- a/test_regress/t/t_struct_nest.v +++ b/test_regress/t/t_struct_nest.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 typedef struct packed { logic [1:0] b1; diff --git a/test_regress/t/t_struct_notfound_bad.out b/test_regress/t/t_struct_notfound_bad.out index 91b308665..f35348c30 100644 --- a/test_regress/t/t_struct_notfound_bad.out +++ b/test_regress/t/t_struct_notfound_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_struct_notfound_bad.v:12: Member 'nfmember' not found in structure - : ... In instance t - s.nfmember = 0; - ^~~~~~~~ +%Error: t/t_struct_notfound_bad.v:13:9: Member 'nfmember' not found in structure + : ... In instance t + 13 | s.nfmember = 0; + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_struct_notfound_bad.pl b/test_regress/t/t_struct_notfound_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_struct_notfound_bad.pl +++ b/test_regress/t/t_struct_notfound_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_notfound_bad.v b/test_regress/t/t_struct_notfound_bad.v index b029ee6b9..bf264fe38 100644 --- a/test_regress/t/t_struct_notfound_bad.v +++ b/test_regress/t/t_struct_notfound_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_struct_packed_sysfunct.pl b/test_regress/t/t_struct_packed_sysfunct.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_packed_sysfunct.pl +++ b/test_regress/t/t_struct_packed_sysfunct.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_packed_sysfunct.v b/test_regress/t/t_struct_packed_sysfunct.v index da483721d..acbe00291 100644 --- a/test_regress/t/t_struct_packed_sysfunct.v +++ b/test_regress/t/t_struct_packed_sysfunct.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_struct_packed_value_list.pl b/test_regress/t/t_struct_packed_value_list.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_packed_value_list.pl +++ b/test_regress/t/t_struct_packed_value_list.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_packed_value_list.v b/test_regress/t/t_struct_packed_value_list.v index 308547afb..41c84d3b9 100644 --- a/test_regress/t/t_struct_packed_value_list.v +++ b/test_regress/t/t_struct_packed_value_list.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_struct_packed_write_read.pl b/test_regress/t/t_struct_packed_write_read.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_packed_write_read.pl +++ b/test_regress/t/t_struct_packed_write_read.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_packed_write_read.v b/test_regress/t/t_struct_packed_write_read.v index 3b689e935..7616b1593 100644 --- a/test_regress/t/t_struct_packed_write_read.v +++ b/test_regress/t/t_struct_packed_write_read.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2009 by Iztok Jeras. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_struct_param.pl b/test_regress/t/t_struct_param.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_param.pl +++ b/test_regress/t/t_struct_param.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_param.v b/test_regress/t/t_struct_param.v index a4cedb878..2a9a7ce7a 100644 --- a/test_regress/t/t_struct_param.v +++ b/test_regress/t/t_struct_param.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Matt Myers. +// SPDX-License-Identifier: CC0-1.0 `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_struct_pat_width.pl b/test_regress/t/t_struct_pat_width.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_pat_width.pl +++ b/test_regress/t/t_struct_pat_width.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_pat_width.v b/test_regress/t/t_struct_pat_width.v index 398d1dec8..d5110959d 100644 --- a/test_regress/t/t_struct_pat_width.v +++ b/test_regress/t/t_struct_pat_width.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2016 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2016 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_struct_port.pl b/test_regress/t/t_struct_port.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_port.pl +++ b/test_regress/t/t_struct_port.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_port.v b/test_regress/t/t_struct_port.v index 3ee634c0e..58cf5beeb 100644 --- a/test_regress/t/t_struct_port.v +++ b/test_regress/t/t_struct_port.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 typedef struct packed { bit b9; diff --git a/test_regress/t/t_struct_portsel.pl b/test_regress/t/t_struct_portsel.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_portsel.pl +++ b/test_regress/t/t_struct_portsel.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_portsel.v b/test_regress/t/t_struct_portsel.v index d9bbb3040..3146a3eab 100644 --- a/test_regress/t/t_struct_portsel.v +++ b/test_regress/t/t_struct_portsel.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_struct_unaligned.pl b/test_regress/t/t_struct_unaligned.pl index 35849af98..eda64373b 100755 --- a/test_regress/t/t_struct_unaligned.pl +++ b/test_regress/t/t_struct_unaligned.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_unaligned.v b/test_regress/t/t_struct_unaligned.v index 9faf1fff2..8fdb06cb1 100644 --- a/test_regress/t/t_struct_unaligned.v +++ b/test_regress/t/t_struct_unaligned.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jeff Bush. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_struct_unpacked.pl b/test_regress/t/t_struct_unpacked.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_struct_unpacked.pl +++ b/test_regress/t/t_struct_unpacked.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_unpacked.v b/test_regress/t/t_struct_unpacked.v index b499329c8..7014a9b08 100644 --- a/test_regress/t/t_struct_unpacked.v +++ b/test_regress/t/t_struct_unpacked.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module x; diff --git a/test_regress/t/t_struct_unpacked_bad.out b/test_regress/t/t_struct_unpacked_bad.out index 6f32a647a..96bc2b963 100644 --- a/test_regress/t/t_struct_unpacked_bad.out +++ b/test_regress/t/t_struct_unpacked_bad.out @@ -1,5 +1,5 @@ -%Warning-UNPACKED: t/t_struct_unpacked_bad.v:8: Unsupported: Unpacked struct/union - typedef struct { - ^~~~~~ +%Warning-UNPACKED: t/t_struct_unpacked_bad.v:9:12: Unsupported: Unpacked struct/union + 9 | typedef struct { + | ^~~~~~ ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_struct_unpacked_bad.pl b/test_regress/t/t_struct_unpacked_bad.pl index 43933e6ae..c1dba4c49 100755 --- a/test_regress/t/t_struct_unpacked_bad.pl +++ b/test_regress/t/t_struct_unpacked_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_struct_unpacked_bad.v b/test_regress/t/t_struct_unpacked_bad.v index a05607066..e062db15a 100644 --- a/test_regress/t/t_struct_unpacked_bad.v +++ b/test_regress/t/t_struct_unpacked_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module x; diff --git a/test_regress/t/t_sv_bus_mux_demux.pl b/test_regress/t/t_sv_bus_mux_demux.pl index 26ebce83b..db4e357ac 100755 --- a/test_regress/t/t_sv_bus_mux_demux.pl +++ b/test_regress/t/t_sv_bus_mux_demux.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug181"); diff --git a/test_regress/t/t_sv_bus_mux_demux.v b/test_regress/t/t_sv_bus_mux_demux.v index f62c837e7..445cda1d2 100644 --- a/test_regress/t/t_sv_bus_mux_demux.v +++ b/test_regress/t/t_sv_bus_mux_demux.v @@ -2,6 +2,7 @@ // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // +// SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv index c68194655..30e64add1 100644 --- a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv @@ -2,6 +2,7 @@ // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // +// SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv index 4f214ae07..7c68214fb 100644 --- a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv @@ -2,6 +2,7 @@ // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // +// SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv index 93e320049..8c70875ad 100644 --- a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv @@ -2,6 +2,7 @@ // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // +// SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// diff --git a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv index 0715188ac..7ca87c358 100644 --- a/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv +++ b/test_regress/t/t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv @@ -2,6 +2,7 @@ // // // This file is placed into the Public Domain, for any use, without warranty. // // 2012 by Iztok Jeras // +// SPDX-License-Identifier: CC0-1.0 // // // //////////////////////////////////////////////////////////////////////////////// diff --git a/test_regress/t/t_sv_conditional.pl b/test_regress/t/t_sv_conditional.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_sv_conditional.pl +++ b/test_regress/t/t_sv_conditional.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sv_conditional.v b/test_regress/t/t_sv_conditional.v index 71f19cd39..516605ac3 100644 --- a/test_regress/t/t_sv_conditional.v +++ b/test_regress/t/t_sv_conditional.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, without // warranty. +// SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. diff --git a/test_regress/t/t_sv_cpu.pl b/test_regress/t/t_sv_cpu.pl index 4ffed6304..a9984d5a8 100755 --- a/test_regress/t/t_sv_cpu.pl +++ b/test_regress/t/t_sv_cpu.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sv_cpu.v b/test_regress/t/t_sv_cpu.v index efa0449c3..4e11d99b4 100644 --- a/test_regress/t/t_sv_cpu.v +++ b/test_regress/t/t_sv_cpu.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, without // warranty. +// SPDX-License-Identifier: CC0-1.0 // Contributed 2012 by M W Lund, Atmel Corporation and Jeremy Bennett, Embecosm. diff --git a/test_regress/t/t_sv_cpu_code/ac.sv b/test_regress/t/t_sv_cpu_code/ac.sv index cfc23cbe5..b4a41006c 100644 --- a/test_regress/t/t_sv_cpu_code/ac.sv +++ b/test_regress/t/t_sv_cpu_code/ac.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/ac_ana.sv b/test_regress/t/t_sv_cpu_code/ac_ana.sv index b8fc0928d..a40728c29 100644 --- a/test_regress/t/t_sv_cpu_code/ac_ana.sv +++ b/test_regress/t/t_sv_cpu_code/ac_ana.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/ac_dig.sv b/test_regress/t/t_sv_cpu_code/ac_dig.sv index ac71cb3c6..046eae2f5 100644 --- a/test_regress/t/t_sv_cpu_code/ac_dig.sv +++ b/test_regress/t/t_sv_cpu_code/ac_dig.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/adrdec.sv b/test_regress/t/t_sv_cpu_code/adrdec.sv index acbbad2da..0d2f925e0 100644 --- a/test_regress/t/t_sv_cpu_code/adrdec.sv +++ b/test_regress/t/t_sv_cpu_code/adrdec.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/chip.sv b/test_regress/t/t_sv_cpu_code/chip.sv index 50a5da6bb..4f374cc6d 100644 --- a/test_regress/t/t_sv_cpu_code/chip.sv +++ b/test_regress/t/t_sv_cpu_code/chip.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/cpu.sv b/test_regress/t/t_sv_cpu_code/cpu.sv index 4ec44eff9..9f8a3526a 100644 --- a/test_regress/t/t_sv_cpu_code/cpu.sv +++ b/test_regress/t/t_sv_cpu_code/cpu.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/genbus_if.sv b/test_regress/t/t_sv_cpu_code/genbus_if.sv index 082a16ac1..430e20ded 100644 --- a/test_regress/t/t_sv_cpu_code/genbus_if.sv +++ b/test_regress/t/t_sv_cpu_code/genbus_if.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pad_gnd.sv b/test_regress/t/t_sv_cpu_code/pad_gnd.sv index c9481edea..e64220f29 100644 --- a/test_regress/t/t_sv_cpu_code/pad_gnd.sv +++ b/test_regress/t/t_sv_cpu_code/pad_gnd.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pad_gpio.sv b/test_regress/t/t_sv_cpu_code/pad_gpio.sv index 18763de51..5c99714d7 100644 --- a/test_regress/t/t_sv_cpu_code/pad_gpio.sv +++ b/test_regress/t/t_sv_cpu_code/pad_gpio.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pad_vdd.sv b/test_regress/t/t_sv_cpu_code/pad_vdd.sv index 0096dbc1e..bad7cc902 100644 --- a/test_regress/t/t_sv_cpu_code/pad_vdd.sv +++ b/test_regress/t/t_sv_cpu_code/pad_vdd.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pads.sv b/test_regress/t/t_sv_cpu_code/pads.sv index d8ac363d1..2eb20e318 100644 --- a/test_regress/t/t_sv_cpu_code/pads.sv +++ b/test_regress/t/t_sv_cpu_code/pads.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pads_h.sv b/test_regress/t/t_sv_cpu_code/pads_h.sv index a10ebc5c4..4955d77c1 100644 --- a/test_regress/t/t_sv_cpu_code/pads_h.sv +++ b/test_regress/t/t_sv_cpu_code/pads_h.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pads_if.sv b/test_regress/t/t_sv_cpu_code/pads_if.sv index 81083a93b..acdbef77a 100644 --- a/test_regress/t/t_sv_cpu_code/pads_if.sv +++ b/test_regress/t/t_sv_cpu_code/pads_if.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/pinout_h.sv b/test_regress/t/t_sv_cpu_code/pinout_h.sv index 082889722..6955249eb 100644 --- a/test_regress/t/t_sv_cpu_code/pinout_h.sv +++ b/test_regress/t/t_sv_cpu_code/pinout_h.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/ports.sv b/test_regress/t/t_sv_cpu_code/ports.sv index 6a84f754f..3eeb00b3d 100644 --- a/test_regress/t/t_sv_cpu_code/ports.sv +++ b/test_regress/t/t_sv_cpu_code/ports.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/ports_h.sv b/test_regress/t/t_sv_cpu_code/ports_h.sv index 6a6c97028..57676835b 100644 --- a/test_regress/t/t_sv_cpu_code/ports_h.sv +++ b/test_regress/t/t_sv_cpu_code/ports_h.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/program_h.sv b/test_regress/t/t_sv_cpu_code/program_h.sv index 33ab17ba8..999ea668b 100644 --- a/test_regress/t/t_sv_cpu_code/program_h.sv +++ b/test_regress/t/t_sv_cpu_code/program_h.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/rom.sv b/test_regress/t/t_sv_cpu_code/rom.sv index 6e5c05a56..25252d6cb 100644 --- a/test_regress/t/t_sv_cpu_code/rom.sv +++ b/test_regress/t/t_sv_cpu_code/rom.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sv_cpu_code/timescale.sv b/test_regress/t/t_sv_cpu_code/timescale.sv index 1bb501097..cd6404194 100644 --- a/test_regress/t/t_sv_cpu_code/timescale.sv +++ b/test_regress/t/t_sv_cpu_code/timescale.sv @@ -2,6 +2,7 @@ // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012. +// SPDX-License-Identifier: CC0-1.0 // Contributed by M W Lund, Atmel Corporation. diff --git a/test_regress/t/t_sys_file_autoflush.pl b/test_regress/t/t_sys_file_autoflush.pl index db9de3301..70f8f6f68 100755 --- a/test_regress/t/t_sys_file_autoflush.pl +++ b/test_regress/t/t_sys_file_autoflush.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_file_basic.pl b/test_regress/t/t_sys_file_basic.pl index 5e4c3a3ba..1e25a84c4 100755 --- a/test_regress/t/t_sys_file_basic.pl +++ b/test_regress/t/t_sys_file_basic.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_file_basic.v b/test_regress/t/t_sys_file_basic.v index 60ed787bb..bd431eb33 100644 --- a/test_regress/t/t_sys_file_basic.v +++ b/test_regress/t/t_sys_file_basic.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "verilated.v" diff --git a/test_regress/t/t_sys_file_scan.pl b/test_regress/t/t_sys_file_scan.pl index 037bb339b..f9d78641c 100755 --- a/test_regress/t/t_sys_file_scan.pl +++ b/test_regress/t/t_sys_file_scan.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_file_scan.v b/test_regress/t/t_sys_file_scan.v index e3c51bb1a..d02ee749d 100644 --- a/test_regress/t/t_sys_file_scan.v +++ b/test_regress/t/t_sys_file_scan.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "verilated.v" diff --git a/test_regress/t/t_sys_fread.pl b/test_regress/t/t_sys_fread.pl index d92562d68..144b8e678 100755 --- a/test_regress/t/t_sys_fread.pl +++ b/test_regress/t/t_sys_fread.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; #use Data::Dumper; use strict; diff --git a/test_regress/t/t_sys_fread.v b/test_regress/t/t_sys_fread.v index 9f44ce048..60921f3f0 100644 --- a/test_regress/t/t_sys_fread.v +++ b/test_regress/t/t_sys_fread.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" `define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_sys_plusargs.pl b/test_regress/t/t_sys_plusargs.pl index 99b5b07cf..56ca5c0f3 100755 --- a/test_regress/t/t_sys_plusargs.pl +++ b/test_regress/t/t_sys_plusargs.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_plusargs.v b/test_regress/t/t_sys_plusargs.v index 470f7929a..f387b5fa2 100644 --- a/test_regress/t/t_sys_plusargs.v +++ b/test_regress/t/t_sys_plusargs.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_plusargs_bad.pl b/test_regress/t/t_sys_plusargs_bad.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_sys_plusargs_bad.pl +++ b/test_regress/t/t_sys_plusargs_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_plusargs_bad.v b/test_regress/t/t_sys_plusargs_bad.v index d3a149b5c..b01d56f05 100644 --- a/test_regress/t/t_sys_plusargs_bad.v +++ b/test_regress/t/t_sys_plusargs_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_rand.pl b/test_regress/t/t_sys_rand.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_sys_rand.pl +++ b/test_regress/t/t_sys_rand.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_rand.v b/test_regress/t/t_sys_rand.v index 80287feac..bdfb7f3e1 100644 --- a/test_regress/t/t_sys_rand.v +++ b/test_regress/t/t_sys_rand.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem.pl b/test_regress/t/t_sys_readmem.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_sys_readmem.pl +++ b/test_regress/t/t_sys_readmem.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_readmem.v b/test_regress/t/t_sys_readmem.v index a85269837..d128dfb4e 100644 --- a/test_regress/t/t_sys_readmem.v +++ b/test_regress/t/t_sys_readmem.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_align_h.mem b/test_regress/t/t_sys_readmem_align_h.mem index b23a4b92b..8c37e101e 100644 --- a/test_regress/t/t_sys_readmem_align_h.mem +++ b/test_regress/t/t_sys_readmem_align_h.mem @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 77554004_37654321_27654321_17654321_07654321_abcdef10 diff --git a/test_regress/t/t_sys_readmem_assoc.pl b/test_regress/t/t_sys_readmem_assoc.pl index d9e1753c8..f797f73ce 100755 --- a/test_regress/t/t_sys_readmem_assoc.pl +++ b/test_regress/t/t_sys_readmem_assoc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_readmem_assoc.v b/test_regress/t/t_sys_readmem_assoc.v index 31c31f052..9d0654c2e 100644 --- a/test_regress/t/t_sys_readmem_assoc.v +++ b/test_regress/t/t_sys_readmem_assoc.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_sys_readmem_assoc_bad.out b/test_regress/t/t_sys_readmem_assoc_bad.out index 42a2644f4..ccb95325d 100644 --- a/test_regress/t/t_sys_readmem_assoc_bad.out +++ b/test_regress/t/t_sys_readmem_assoc_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_sys_readmem_assoc_bad.v:12: $readmemb address/key must be integral (IEEE 1800-2017 21.4.1) - : ... In instance t - $readmemb("not", assoc_bad_key); - ^~~~~~~~~~~~~ -%Error: t/t_sys_readmem_assoc_bad.v:13: Unsupported: $readmemb array values must be integral - : ... In instance t - $readmemb("not", assoc_bad_value); - ^~~~~~~~~~~~~~~ +%Error: t/t_sys_readmem_assoc_bad.v:13:24: $readmemb address/key must be integral (IEEE 1800-2017 21.4.1) + : ... In instance t + 13 | $readmemb("not", assoc_bad_key); + | ^~~~~~~~~~~~~ +%Error: t/t_sys_readmem_assoc_bad.v:14:24: Unsupported: $readmemb array values must be integral + : ... In instance t + 14 | $readmemb("not", assoc_bad_value); + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_sys_readmem_assoc_bad.pl b/test_regress/t/t_sys_readmem_assoc_bad.pl index 43933e6ae..c1dba4c49 100755 --- a/test_regress/t/t_sys_readmem_assoc_bad.pl +++ b/test_regress/t/t_sys_readmem_assoc_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_readmem_assoc_bad.v b/test_regress/t/t_sys_readmem_assoc_bad.v index bb3d58455..8d6ca224e 100644 --- a/test_regress/t/t_sys_readmem_assoc_bad.v +++ b/test_regress/t/t_sys_readmem_assoc_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_b.mem b/test_regress/t/t_sys_readmem_b.mem index 67c886399..eeec4a511 100644 --- a/test_regress/t/t_sys_readmem_b.mem +++ b/test_regress/t/t_sys_readmem_b.mem @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # SRecord style comment diff --git a/test_regress/t/t_sys_readmem_b_8.mem b/test_regress/t/t_sys_readmem_b_8.mem index 5b8fd5296..693796c33 100644 --- a/test_regress/t/t_sys_readmem_b_8.mem +++ b/test_regress/t/t_sys_readmem_b_8.mem @@ -1,9 +1,10 @@ // DESCRIPTION: Verilator: Verilog Test data file // -// Copyright 2006 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU +// Copyright 2006 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // ** Note this file has DOS CR's so we can test them! diff --git a/test_regress/t/t_sys_readmem_bad_addr.mem b/test_regress/t/t_sys_readmem_bad_addr.mem index ea2878f9c..7d3c5dbe7 100644 --- a/test_regress/t/t_sys_readmem_bad_addr.mem +++ b/test_regress/t/t_sys_readmem_bad_addr.mem @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @121212 10 diff --git a/test_regress/t/t_sys_readmem_bad_addr.out b/test_regress/t/t_sys_readmem_bad_addr.out new file mode 100644 index 000000000..205e6d0a9 --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_addr.out @@ -0,0 +1,2 @@ +%Error: t/t_sys_readmem_bad_addr.mem:9: $readmem file address beyond bounds of array +Aborting... diff --git a/test_regress/t/t_sys_readmem_bad_addr.pl b/test_regress/t/t_sys_readmem_bad_addr.pl index 8e05d5ac6..1d965ffec 100755 --- a/test_regress/t/t_sys_readmem_bad_addr.pl +++ b/test_regress/t/t_sys_readmem_bad_addr.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -14,8 +15,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'%Error: t/t_sys_readmem_bad_addr.mem:\d+: \$readmem file address beyond bounds of array', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_sys_readmem_bad_addr.v b/test_regress/t/t_sys_readmem_bad_addr.v index 1d2306e32..ce030da54 100644 --- a/test_regress/t/t_sys_readmem_bad_addr.v +++ b/test_regress/t/t_sys_readmem_bad_addr.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; reg [175:0] hex [15:0]; diff --git a/test_regress/t/t_sys_readmem_bad_digit.mem b/test_regress/t/t_sys_readmem_bad_digit.mem index bd4ba9b2d..c67d16fa3 100644 --- a/test_regress/t/t_sys_readmem_bad_digit.mem +++ b/test_regress/t/t_sys_readmem_bad_digit.mem @@ -4,5 +4,6 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 a0 diff --git a/test_regress/t/t_sys_readmem_bad_digit.out b/test_regress/t/t_sys_readmem_bad_digit.out new file mode 100644 index 000000000..a67b3d212 --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_digit.out @@ -0,0 +1,2 @@ +%Error: t/t_sys_readmem_bad_digit.mem:8: $readmemb (binary) file contains hex characters +Aborting... diff --git a/test_regress/t/t_sys_readmem_bad_digit.pl b/test_regress/t/t_sys_readmem_bad_digit.pl index d8a51828e..1d965ffec 100755 --- a/test_regress/t/t_sys_readmem_bad_digit.pl +++ b/test_regress/t/t_sys_readmem_bad_digit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -14,8 +15,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'%Error: t/t_sys_readmem_bad_digit.mem:\d+: \$readmemb \(binary\) file contains hex characters', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_sys_readmem_bad_digit.v b/test_regress/t/t_sys_readmem_bad_digit.v index ca568120a..52eb6f5ec 100644 --- a/test_regress/t/t_sys_readmem_bad_digit.v +++ b/test_regress/t/t_sys_readmem_bad_digit.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_bad_end.mem b/test_regress/t/t_sys_readmem_bad_end.mem index 88a97c81e..ddebc6e54 100644 --- a/test_regress/t/t_sys_readmem_bad_end.mem +++ b/test_regress/t/t_sys_readmem_bad_end.mem @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 00 01 diff --git a/test_regress/t/t_sys_readmem_bad_end.out b/test_regress/t/t_sys_readmem_bad_end.out new file mode 100644 index 000000000..752129a5b --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_end.out @@ -0,0 +1,2 @@ +%Error: t/t_sys_readmem_bad_end.mem:12: $readmem file ended before specified final address (IEEE 2017 21.4) +Aborting... diff --git a/test_regress/t/t_sys_readmem_bad_end.pl b/test_regress/t/t_sys_readmem_bad_end.pl index debf6df30..1d965ffec 100755 --- a/test_regress/t/t_sys_readmem_bad_end.pl +++ b/test_regress/t/t_sys_readmem_bad_end.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -14,8 +15,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'%Error: t/t_sys_readmem_bad_end.mem:\d+: \$readmem file ended before specified final address', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_sys_readmem_bad_end.v b/test_regress/t/t_sys_readmem_bad_end.v index 26c526992..7aee6a967 100644 --- a/test_regress/t/t_sys_readmem_bad_end.v +++ b/test_regress/t/t_sys_readmem_bad_end.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_bad_notfound.out b/test_regress/t/t_sys_readmem_bad_notfound.out new file mode 100644 index 000000000..317be5d9a --- /dev/null +++ b/test_regress/t/t_sys_readmem_bad_notfound.out @@ -0,0 +1,2 @@ +%Error: t/t_sys_readmem_bad_NOTFOUND.mem:0: $readmem file not found +Aborting... diff --git a/test_regress/t/t_sys_readmem_bad_notfound.pl b/test_regress/t/t_sys_readmem_bad_notfound.pl index 499e85c9f..1d965ffec 100755 --- a/test_regress/t/t_sys_readmem_bad_notfound.pl +++ b/test_regress/t/t_sys_readmem_bad_notfound.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -14,8 +15,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'%Error: t/t_sys_readmem_bad_NOTFOUND.mem:\d+: \$readmem file not found', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_sys_readmem_bad_notfound.v b/test_regress/t/t_sys_readmem_bad_notfound.v index d44ba3e0a..910b510dc 100644 --- a/test_regress/t/t_sys_readmem_bad_notfound.v +++ b/test_regress/t/t_sys_readmem_bad_notfound.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_readmem_h.mem b/test_regress/t/t_sys_readmem_h.mem index 5c07d6829..5974c9c59 100644 --- a/test_regress/t/t_sys_readmem_h.mem +++ b/test_regress/t/t_sys_readmem_h.mem @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 @4 4004_37654321_27654321_17654321_07654321_abcdef10 diff --git a/test_regress/t/t_sys_sformat.pl b/test_regress/t/t_sys_sformat.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_sys_sformat.pl +++ b/test_regress/t/t_sys_sformat.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_sformat.v b/test_regress/t/t_sys_sformat.v index 6d099042f..ecd5f8eb3 100644 --- a/test_regress/t/t_sys_sformat.v +++ b/test_regress/t/t_sys_sformat.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `include "verilated.v" diff --git a/test_regress/t/t_sys_sformat_noopt.pl b/test_regress/t/t_sys_sformat_noopt.pl index b2bb8f60b..5a82f0df1 100755 --- a/test_regress/t/t_sys_sformat_noopt.pl +++ b/test_regress/t/t_sys_sformat_noopt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_system.pl b/test_regress/t/t_sys_system.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_sys_system.pl +++ b/test_regress/t/t_sys_system.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_system.v b/test_regress/t/t_sys_system.v index 612797f7c..2ea7a2c0d 100644 --- a/test_regress/t/t_sys_system.v +++ b/test_regress/t/t_sys_system.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_sys_time.pl b/test_regress/t/t_sys_time.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_sys_time.pl +++ b/test_regress/t/t_sys_time.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_sys_time.v b/test_regress/t/t_sys_time.v index 19f280074..0a05a6cdb 100644 --- a/test_regress/t/t_sys_time.v +++ b/test_regress/t/t_sys_time.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_sys_writemem.pl b/test_regress/t/t_sys_writemem.pl index ceadb09e2..93c8b1672 100755 --- a/test_regress/t/t_sys_writemem.pl +++ b/test_regress/t/t_sys_writemem.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_table_fsm.pl b/test_regress/t/t_table_fsm.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_table_fsm.pl +++ b/test_regress/t/t_table_fsm.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_table_fsm.v b/test_regress/t/t_table_fsm.v index 1ac617f8a..f4d574288 100644 --- a/test_regress/t/t_table_fsm.v +++ b/test_regress/t/t_table_fsm.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_threads_counter.v b/test_regress/t/t_threads_counter.v index dabcf0a77..fad058267 100644 --- a/test_regress/t/t_threads_counter.v +++ b/test_regress/t/t_threads_counter.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_threads_counter_0.pl b/test_regress/t/t_threads_counter_0.pl index b7ad02b32..189abd405 100755 --- a/test_regress/t/t_threads_counter_0.pl +++ b/test_regress/t/t_threads_counter_0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_threads_counter_1.pl b/test_regress/t/t_threads_counter_1.pl index bc7ea206a..0c3a06a5d 100755 --- a/test_regress/t/t_threads_counter_1.pl +++ b/test_regress/t/t_threads_counter_1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); diff --git a/test_regress/t/t_threads_counter_2.pl b/test_regress/t/t_threads_counter_2.pl index c5b325ae6..76c97a8b7 100755 --- a/test_regress/t/t_threads_counter_2.pl +++ b/test_regress/t/t_threads_counter_2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); diff --git a/test_regress/t/t_threads_counter_4.pl b/test_regress/t/t_threads_counter_4.pl index 3f8fab395..856750e0f 100755 --- a/test_regress/t/t_threads_counter_4.pl +++ b/test_regress/t/t_threads_counter_4.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); diff --git a/test_regress/t/t_threads_nondeterminism.pl b/test_regress/t/t_threads_nondeterminism.pl index 19e7f0b6f..0d4850945 100755 --- a/test_regress/t/t_threads_nondeterminism.pl +++ b/test_regress/t/t_threads_nondeterminism.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); diff --git a/test_regress/t/t_timescale.cpp b/test_regress/t/t_timescale.cpp index befd0843a..f0bddf194 100644 --- a/test_regress/t/t_timescale.cpp +++ b/test_regress/t/t_timescale.cpp @@ -1,4 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include diff --git a/test_regress/t/t_timescale.pl b/test_regress/t/t_timescale.pl index cd165daa1..7cd01c28d 100755 --- a/test_regress/t/t_timescale.pl +++ b/test_regress/t/t_timescale.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_array.pl b/test_regress/t/t_trace_array.pl index 77ee5fd51..fd2cd5027 100755 --- a/test_regress/t/t_trace_array.pl +++ b/test_regress/t/t_trace_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_array.v b/test_regress/t/t_trace_array.v index 6cf6ce82e..9622f78ff 100644 --- a/test_regress/t/t_trace_array.v +++ b/test_regress/t/t_trace_array.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_trace_array_fst.pl b/test_regress/t/t_trace_array_fst.pl index 71df415e7..f3b30bbf0 100755 --- a/test_regress/t/t_trace_array_fst.pl +++ b/test_regress/t/t_trace_array_fst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_trace_cat.cpp b/test_regress/t/t_trace_cat.cpp index d919121d6..f1f5aed79 100644 --- a/test_regress/t/t_trace_cat.cpp +++ b/test_regress/t/t_trace_cat.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include diff --git a/test_regress/t/t_trace_cat.pl b/test_regress/t/t_trace_cat.pl index 5444778a2..958db5f1c 100755 --- a/test_regress/t/t_trace_cat.pl +++ b/test_regress/t/t_trace_cat.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_cat.v b/test_regress/t/t_trace_cat.v index f9c6d1f21..7428682b5 100644 --- a/test_regress/t/t_trace_cat.v +++ b/test_regress/t/t_trace_cat.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_trace_cat_renew.pl b/test_regress/t/t_trace_cat_renew.pl index 9242ce46e..45b0aabb0 100755 --- a/test_regress/t/t_trace_cat_renew.pl +++ b/test_regress/t/t_trace_cat_renew.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_cat_reopen.pl b/test_regress/t/t_trace_cat_reopen.pl index 9242ce46e..45b0aabb0 100755 --- a/test_regress/t/t_trace_cat_reopen.pl +++ b/test_regress/t/t_trace_cat_reopen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_complex.pl b/test_regress/t/t_trace_complex.pl index a48d29e99..5fde2b79c 100755 --- a/test_regress/t/t_trace_complex.pl +++ b/test_regress/t/t_trace_complex.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index bf8e184ea..8f283e2e8 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 bit global_bit; diff --git a/test_regress/t/t_trace_complex_fst.pl b/test_regress/t/t_trace_complex_fst.pl index f44a661c8..9b76e1c36 100755 --- a/test_regress/t/t_trace_complex_fst.pl +++ b/test_regress/t/t_trace_complex_fst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_complex_fst_thread.pl b/test_regress/t/t_trace_complex_fst_thread.pl index f52f24b8a..59ffac304 100755 --- a/test_regress/t/t_trace_complex_fst_thread.pl +++ b/test_regress/t/t_trace_complex_fst_thread.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_complex_params.pl b/test_regress/t/t_trace_complex_params.pl index 9134b577b..0c896905a 100755 --- a/test_regress/t/t_trace_complex_params.pl +++ b/test_regress/t/t_trace_complex_params.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_complex_params_fst.pl b/test_regress/t/t_trace_complex_params_fst.pl index 436680ea9..ecb5daf90 100755 --- a/test_regress/t/t_trace_complex_params_fst.pl +++ b/test_regress/t/t_trace_complex_params_fst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_complex_structs.pl b/test_regress/t/t_trace_complex_structs.pl index 24d5e7d7d..c02c2edba 100755 --- a/test_regress/t/t_trace_complex_structs.pl +++ b/test_regress/t/t_trace_complex_structs.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_complex_structs_fst.pl b/test_regress/t/t_trace_complex_structs_fst.pl index 3a6b98aa1..08626b897 100755 --- a/test_regress/t/t_trace_complex_structs_fst.pl +++ b/test_regress/t/t_trace_complex_structs_fst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_decoration.pl b/test_regress/t/t_trace_decoration.pl index dd6023334..1e56e3468 100755 --- a/test_regress/t/t_trace_decoration.pl +++ b/test_regress/t/t_trace_decoration.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_decoration.v b/test_regress/t/t_trace_decoration.v index 80f511d13..06ac8bfdb 100644 --- a/test_regress/t/t_trace_decoration.v +++ b/test_regress/t/t_trace_decoration.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_trace_dumporder_bad.pl b/test_regress/t/t_trace_dumporder_bad.pl index cae730749..f631d6efd 100755 --- a/test_regress/t/t_trace_dumporder_bad.pl +++ b/test_regress/t/t_trace_dumporder_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_trace_dumporder_bad.v b/test_regress/t/t_trace_dumporder_bad.v index fe443f75e..9eea149ee 100644 --- a/test_regress/t/t_trace_dumporder_bad.v +++ b/test_regress/t/t_trace_dumporder_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); initial begin diff --git a/test_regress/t/t_trace_ena.v b/test_regress/t/t_trace_ena.v index 1792cf765..85b3d3f40 100644 --- a/test_regress/t/t_trace_ena.v +++ b/test_regress/t/t_trace_ena.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_trace_ena_cc.pl b/test_regress/t/t_trace_ena_cc.pl index 33dc0c3eb..c21a28eac 100755 --- a/test_regress/t/t_trace_ena_cc.pl +++ b/test_regress/t/t_trace_ena_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_ena_sc.pl b/test_regress/t/t_trace_ena_sc.pl index 6e649beaf..1b3f63236 100755 --- a/test_regress/t/t_trace_ena_sc.pl +++ b/test_regress/t/t_trace_ena_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_flag_off.out b/test_regress/t/t_trace_flag_off.out index 680eb2bcf..7cfdc9ff2 100644 --- a/test_regress/t/t_trace_flag_off.out +++ b/test_regress/t/t_trace_flag_off.out @@ -1,2 +1,2 @@ --Info: t/t_trace_flag_off.v:9: $dumpvar ignored, as Verilated without --trace +-Info: t/t_trace_flag_off.v:10: $dumpvar ignored, as Verilated without --trace *-* All Finished *-* diff --git a/test_regress/t/t_trace_flag_off.pl b/test_regress/t/t_trace_flag_off.pl index bc3f03af6..08f94898c 100755 --- a/test_regress/t/t_trace_flag_off.pl +++ b/test_regress/t/t_trace_flag_off.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test that without --trace we get a message when turning on traces scenarios(vlt => 1); diff --git a/test_regress/t/t_trace_flag_off.v b/test_regress/t/t_trace_flag_off.v index b8348526f..dc9079720 100644 --- a/test_regress/t/t_trace_flag_off.v +++ b/test_regress/t/t_trace_flag_off.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); initial begin diff --git a/test_regress/t/t_trace_fst.pl b/test_regress/t/t_trace_fst.pl index 5a10032c3..f03d12134 100755 --- a/test_regress/t/t_trace_fst.pl +++ b/test_regress/t/t_trace_fst.pl @@ -1,6 +1,12 @@ #!/usr/bin/perl -# This file ONLY is placed into the Public Domain, for any use, -# Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } diff --git a/test_regress/t/t_trace_fst.v b/test_regress/t/t_trace_fst.v index 6d3ff0bfb..288ddadfc 100644 --- a/test_regress/t/t_trace_fst.v +++ b/test_regress/t/t_trace_fst.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, // Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_trace_off_cc.pl b/test_regress/t/t_trace_off_cc.pl index 15b22d079..e339997bf 100755 --- a/test_regress/t/t_trace_off_cc.pl +++ b/test_regress/t/t_trace_off_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_off_sc.pl b/test_regress/t/t_trace_off_sc.pl index b14cfb7e2..3a5f13f69 100755 --- a/test_regress/t/t_trace_off_sc.pl +++ b/test_regress/t/t_trace_off_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_packed_struct.pl b/test_regress/t/t_trace_packed_struct.pl index a25a14034..d41b7c1ba 100755 --- a/test_regress/t/t_trace_packed_struct.pl +++ b/test_regress/t/t_trace_packed_struct.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_packed_struct.v b/test_regress/t/t_trace_packed_struct.v index 1c800d0d5..06daeb581 100644 --- a/test_regress/t/t_trace_packed_struct.v +++ b/test_regress/t/t_trace_packed_struct.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Andrew Bardsley. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_trace_packed_struct_fst.pl b/test_regress/t/t_trace_packed_struct_fst.pl index 259774eea..a84d85f7d 100755 --- a/test_regress/t/t_trace_packed_struct_fst.pl +++ b/test_regress/t/t_trace_packed_struct_fst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_param.pl b/test_regress/t/t_trace_param.pl index 527cc3283..d9fbe89cc 100755 --- a/test_regress/t/t_trace_param.pl +++ b/test_regress/t/t_trace_param.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_param.v b/test_regress/t/t_trace_param.v index 8f81eec0f..c112e0251 100644 --- a/test_regress/t/t_trace_param.v +++ b/test_regress/t/t_trace_param.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jonathon Donaldson. +// SPDX-License-Identifier: CC0-1.0 package my_funcs; function automatic int simple_func (input int value); diff --git a/test_regress/t/t_trace_param_fst.pl b/test_regress/t/t_trace_param_fst.pl index 178442550..87446f8d1 100755 --- a/test_regress/t/t_trace_param_fst.pl +++ b/test_regress/t/t_trace_param_fst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_primitive.pl b/test_regress/t/t_trace_primitive.pl index 5a360b082..515d10698 100755 --- a/test_regress/t/t_trace_primitive.pl +++ b/test_regress/t/t_trace_primitive.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_primitive.v b/test_regress/t/t_trace_primitive.v index 00fb855d4..176c053ca 100644 --- a/test_regress/t/t_trace_primitive.v +++ b/test_regress/t/t_trace_primitive.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2014 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_trace_primitive_fst.pl b/test_regress/t/t_trace_primitive_fst.pl index 1f5bf4d7b..f2b56c2bd 100755 --- a/test_regress/t/t_trace_primitive_fst.pl +++ b/test_regress/t/t_trace_primitive_fst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_public.v b/test_regress/t/t_trace_public.v index 06080d229..c3d0c9603 100644 --- a/test_regress/t/t_trace_public.v +++ b/test_regress/t/t_trace_public.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( input wire CLK, diff --git a/test_regress/t/t_trace_public_func.cpp b/test_regress/t/t_trace_public_func.cpp index d5e055111..8f4de6e76 100644 --- a/test_regress/t/t_trace_public_func.cpp +++ b/test_regress/t/t_trace_public_func.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include diff --git a/test_regress/t/t_trace_public_func.pl b/test_regress/t/t_trace_public_func.pl index 1a9d8c57a..672d8ce55 100755 --- a/test_regress/t/t_trace_public_func.pl +++ b/test_regress/t/t_trace_public_func.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_public_func.vlt b/test_regress/t/t_trace_public_func.vlt index 15b96feeb..41089da90 100644 --- a/test_regress/t/t_trace_public_func.vlt +++ b/test_regress/t/t_trace_public_func.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_trace_public_func_vlt.pl b/test_regress/t/t_trace_public_func_vlt.pl index a7f553931..29380e643 100755 --- a/test_regress/t/t_trace_public_func_vlt.pl +++ b/test_regress/t/t_trace_public_func_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_public_sig.cpp b/test_regress/t/t_trace_public_sig.cpp index 983a5449a..7733c2eca 100644 --- a/test_regress/t/t_trace_public_sig.cpp +++ b/test_regress/t/t_trace_public_sig.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include diff --git a/test_regress/t/t_trace_public_sig.pl b/test_regress/t/t_trace_public_sig.pl index f06a83b83..c882e2679 100755 --- a/test_regress/t/t_trace_public_sig.pl +++ b/test_regress/t/t_trace_public_sig.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_public_sig.vlt b/test_regress/t/t_trace_public_sig.vlt index ec8647b5d..dbe85510d 100644 --- a/test_regress/t/t_trace_public_sig.vlt +++ b/test_regress/t/t_trace_public_sig.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_trace_public_sig_vlt.pl b/test_regress/t/t_trace_public_sig_vlt.pl index e8140045a..7ecac0618 100755 --- a/test_regress/t/t_trace_public_sig_vlt.pl +++ b/test_regress/t/t_trace_public_sig_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); @@ -19,7 +20,7 @@ compile( ); if ($Self->{vlt_all}) { - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_trace_scstruct.pl b/test_regress/t/t_trace_scstruct.pl index 51382a932..77cb15478 100755 --- a/test_regress/t/t_trace_scstruct.pl +++ b/test_regress/t/t_trace_scstruct.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_scstruct.v b/test_regress/t/t_trace_scstruct.v index 0993f0fc8..613171027 100644 --- a/test_regress/t/t_trace_scstruct.v +++ b/test_regress/t/t_trace_scstruct.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // verilator lint_off UNUSED // verilator lint_off UNDRIVEN diff --git a/test_regress/t/t_trace_string.pl b/test_regress/t/t_trace_string.pl index b6ba517f5..d3096503a 100755 --- a/test_regress/t/t_trace_string.pl +++ b/test_regress/t/t_trace_string.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_string.v b/test_regress/t/t_trace_string.v index 9f3fb8d83..cb48d4770 100644 --- a/test_regress/t/t_trace_string.v +++ b/test_regress/t/t_trace_string.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_trace_string_fst.pl b/test_regress/t/t_trace_string_fst.pl index 2a4758cc9..01a7456be 100755 --- a/test_regress/t/t_trace_string_fst.pl +++ b/test_regress/t/t_trace_string_fst.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_timescale.cpp b/test_regress/t/t_trace_timescale.cpp index 8dead4e12..bac0d5179 100644 --- a/test_regress/t/t_trace_timescale.cpp +++ b/test_regress/t/t_trace_timescale.cpp @@ -2,8 +2,9 @@ // // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include #include diff --git a/test_regress/t/t_trace_timescale.pl b/test_regress/t/t_trace_timescale.pl index 4185d5102..91e596a94 100755 --- a/test_regress/t/t_trace_timescale.pl +++ b/test_regress/t/t_trace_timescale.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2013 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_timescale.v b/test_regress/t/t_trace_timescale.v index f9c6d1f21..7428682b5 100644 --- a/test_regress/t/t_trace_timescale.v +++ b/test_regress/t/t_trace_timescale.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2013 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_trace_two_a.v b/test_regress/t/t_trace_two_a.v index 86533cc90..a9b87db05 100644 --- a/test_regress/t/t_trace_two_a.v +++ b/test_regress/t/t_trace_two_a.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define CONCAT(a, b) a``b `define STRINGIFY(x) `"x`" diff --git a/test_regress/t/t_trace_two_b.v b/test_regress/t/t_trace_two_b.v index 047e7a15f..22aad670b 100644 --- a/test_regress/t/t_trace_two_b.v +++ b/test_regress/t/t_trace_two_b.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_trace_two_cc.cpp b/test_regress/t/t_trace_two_cc.cpp index 2a4455ac5..e0554a7e8 100644 --- a/test_regress/t/t_trace_two_cc.cpp +++ b/test_regress/t/t_trace_two_cc.cpp @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #include "verilatedos.h" #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_trace_two_dump_cc.pl b/test_regress/t/t_trace_two_dump_cc.pl index 2d3e34fd4..e76663909 100755 --- a/test_regress/t/t_trace_two_dump_cc.pl +++ b/test_regress/t/t_trace_two_dump_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_two_dump_sc.pl b/test_regress/t/t_trace_two_dump_sc.pl index 6579e2cec..68b7e66fa 100755 --- a/test_regress/t/t_trace_two_dump_sc.pl +++ b/test_regress/t/t_trace_two_dump_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_two_dumpfst_cc.pl b/test_regress/t/t_trace_two_dumpfst_cc.pl index 87ce59a99..d2288c696 100755 --- a/test_regress/t/t_trace_two_dumpfst_cc.pl +++ b/test_regress/t/t_trace_two_dumpfst_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_two_hdr_cc.pl b/test_regress/t/t_trace_two_hdr_cc.pl index 1fbe3fd38..a9c610767 100755 --- a/test_regress/t/t_trace_two_hdr_cc.pl +++ b/test_regress/t/t_trace_two_hdr_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_two_hdr_sc.pl b/test_regress/t/t_trace_two_hdr_sc.pl index 7cbd882a0..922edf3cd 100755 --- a/test_regress/t/t_trace_two_hdr_sc.pl +++ b/test_regress/t/t_trace_two_hdr_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_two_hdrfst_cc.pl b/test_regress/t/t_trace_two_hdrfst_cc.pl index ec1cd5937..dd4712626 100755 --- a/test_regress/t/t_trace_two_hdrfst_cc.pl +++ b/test_regress/t/t_trace_two_hdrfst_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_two_port_cc.pl b/test_regress/t/t_trace_two_port_cc.pl index 31abb926b..e12876ece 100755 --- a/test_regress/t/t_trace_two_port_cc.pl +++ b/test_regress/t/t_trace_two_port_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_two_port_sc.pl b/test_regress/t/t_trace_two_port_sc.pl index 177f24f65..ce581bf42 100755 --- a/test_regress/t/t_trace_two_port_sc.pl +++ b/test_regress/t/t_trace_two_port_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_trace_two_portfst_cc.pl b/test_regress/t/t_trace_two_portfst_cc.pl index ce9131110..acb6176b9 100755 --- a/test_regress/t/t_trace_two_portfst_cc.pl +++ b/test_regress/t/t_trace_two_portfst_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # Test tracing with two models instanced scenarios(vlt_all => 1); diff --git a/test_regress/t/t_trace_two_sc.cpp b/test_regress/t/t_trace_two_sc.cpp index c3c1d12ac..1f313d7d7 100644 --- a/test_regress/t/t_trace_two_sc.cpp +++ b/test_regress/t/t_trace_two_sc.cpp @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 #include "verilatedos.h" #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_tri_array.pl b/test_regress/t/t_tri_array.pl index 7c9c9c1dd..638ba1876 100755 --- a/test_regress/t/t_tri_array.pl +++ b/test_regress/t/t_tri_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_array.v b/test_regress/t/t_tri_array.v index a110a3780..7601f94f2 100644 --- a/test_regress/t/t_tri_array.v +++ b/test_regress/t/t_tri_array.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_array_bufif.pl b/test_regress/t/t_tri_array_bufif.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_tri_array_bufif.pl +++ b/test_regress/t/t_tri_array_bufif.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_array_bufif.v b/test_regress/t/t_tri_array_bufif.v index e767faced..083353bea 100644 --- a/test_regress/t/t_tri_array_bufif.v +++ b/test_regress/t/t_tri_array_bufif.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_array_pull.pl b/test_regress/t/t_tri_array_pull.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_tri_array_pull.pl +++ b/test_regress/t/t_tri_array_pull.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_array_pull.v b/test_regress/t/t_tri_array_pull.v index e1ce8e2af..b29d1d5b5 100644 --- a/test_regress/t/t_tri_array_pull.v +++ b/test_regress/t/t_tri_array_pull.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2018 by Rod Steward. +// SPDX-License-Identifier: CC0-1.0 module IOBUF ( input T, input I, output O, inout IO ); assign O = IO; diff --git a/test_regress/t/t_tri_compass_bad.out b/test_regress/t/t_tri_compass_bad.out index ccfb73039..a7cdf0192 100644 --- a/test_regress/t/t_tri_compass_bad.out +++ b/test_regress/t/t_tri_compass_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_tri_compass_bad.v:15: Unsupported: tristate in top-level IO: '__pinNumber1' - : ... In instance t - sub sub(i, o); - ^ +%Error: t/t_tri_compass_bad.v:16:12: Unsupported: tristate in top-level IO: '__pinNumber1' + : ... In instance t + 16 | sub sub(i, o); + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_tri_compass_bad.pl b/test_regress/t/t_tri_compass_bad.pl index 3264f888b..a0cbbba4d 100755 --- a/test_regress/t/t_tri_compass_bad.pl +++ b/test_regress/t/t_tri_compass_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_tri_compass_bad.v b/test_regress/t/t_tri_compass_bad.v index abe36c903..d95ced5c1 100644 --- a/test_regress/t/t_tri_compass_bad.v +++ b/test_regress/t/t_tri_compass_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_tri_dangle.pl b/test_regress/t/t_tri_dangle.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_tri_dangle.pl +++ b/test_regress/t/t_tri_dangle.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_dangle.v b/test_regress/t/t_tri_dangle.v index 030aa65ad..20a5363e4 100644 --- a/test_regress/t/t_tri_dangle.v +++ b/test_regress/t/t_tri_dangle.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inouts diff --git a/test_regress/t/t_tri_eqcase.pl b/test_regress/t/t_tri_eqcase.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_tri_eqcase.pl +++ b/test_regress/t/t_tri_eqcase.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_eqcase.v b/test_regress/t/t_tri_eqcase.v index ca86c34fd..a922a4b94 100644 --- a/test_regress/t/t_tri_eqcase.v +++ b/test_regress/t/t_tri_eqcase.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_gate.cpp b/test_regress/t/t_tri_gate.cpp index a0e57553e..8a6cce86a 100644 --- a/test_regress/t/t_tri_gate.cpp +++ b/test_regress/t/t_tri_gate.cpp @@ -1,7 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_tri_gate.v b/test_regress/t/t_tri_gate.v index 7209f354f..bf0cccb8d 100644 --- a/test_regress/t/t_tri_gate.v +++ b/test_regress/t/t_tri_gate.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 module top (input SEL, input[1:0] A, output W, output X, output Y, output Z); mux mux2 (.A(A), .SEL(SEL), .Z(W)); diff --git a/test_regress/t/t_tri_gate_bufif0.pl b/test_regress/t/t_tri_gate_bufif0.pl index f7f617e73..839f4bd91 100755 --- a/test_regress/t/t_tri_gate_bufif0.pl +++ b/test_regress/t/t_tri_gate_bufif0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_gate_bufif1.pl b/test_regress/t/t_tri_gate_bufif1.pl index 1e1ba6013..75b89c4a0 100755 --- a/test_regress/t/t_tri_gate_bufif1.pl +++ b/test_regress/t/t_tri_gate_bufif1.pl @@ -1,10 +1,11 @@ #!/usr/bin/perl # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_gate_cond.pl b/test_regress/t/t_tri_gate_cond.pl index 41695b762..d59a475b1 100755 --- a/test_regress/t/t_tri_gate_cond.pl +++ b/test_regress/t/t_tri_gate_cond.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_gate_nmos.pl b/test_regress/t/t_tri_gate_nmos.pl index 024edd03e..d6bd9b4db 100755 --- a/test_regress/t/t_tri_gate_nmos.pl +++ b/test_regress/t/t_tri_gate_nmos.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_gate_notif0.pl b/test_regress/t/t_tri_gate_notif0.pl index d0bd5f0ec..a2d66b275 100755 --- a/test_regress/t/t_tri_gate_notif0.pl +++ b/test_regress/t/t_tri_gate_notif0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_gate_notif1.pl b/test_regress/t/t_tri_gate_notif1.pl index ba4d5997e..b7f8fb168 100755 --- a/test_regress/t/t_tri_gate_notif1.pl +++ b/test_regress/t/t_tri_gate_notif1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_gate_pmos.pl b/test_regress/t/t_tri_gate_pmos.pl index 5cc799f74..02b626999 100755 --- a/test_regress/t/t_tri_gate_pmos.pl +++ b/test_regress/t/t_tri_gate_pmos.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_gen.pl b/test_regress/t/t_tri_gen.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_tri_gen.pl +++ b/test_regress/t/t_tri_gen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_gen.v b/test_regress/t/t_tri_gen.v index 9fa7a3d2c..8b11130ca 100644 --- a/test_regress/t/t_tri_gen.v +++ b/test_regress/t/t_tri_gen.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_graph.pl b/test_regress/t/t_tri_graph.pl index 6312119ef..c8c83176b 100755 --- a/test_regress/t/t_tri_graph.pl +++ b/test_regress/t/t_tri_graph.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_graph.v b/test_regress/t/t_tri_graph.v index fde19535d..1a50d6e52 100644 --- a/test_regress/t/t_tri_graph.v +++ b/test_regress/t/t_tri_graph.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_ifbegin.pl b/test_regress/t/t_tri_ifbegin.pl index 96d9ccfa3..b4e63dfda 100755 --- a/test_regress/t/t_tri_ifbegin.pl +++ b/test_regress/t/t_tri_ifbegin.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_ifbegin.v b/test_regress/t/t_tri_ifbegin.v index 3be9c2a00..cd567515a 100644 --- a/test_regress/t/t_tri_ifbegin.v +++ b/test_regress/t/t_tri_ifbegin.v @@ -1,4 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_inout.cpp b/test_regress/t/t_tri_inout.cpp index 217ca8c35..c9c591cb7 100644 --- a/test_regress/t/t_tri_inout.cpp +++ b/test_regress/t/t_tri_inout.cpp @@ -1,7 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_inout.h" diff --git a/test_regress/t/t_tri_inout.pl b/test_regress/t/t_tri_inout.pl index 6c781245e..4d136dc52 100755 --- a/test_regress/t/t_tri_inout.pl +++ b/test_regress/t/t_tri_inout.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_inout.v b/test_regress/t/t_tri_inout.v index 7322cf43d..d466259cd 100644 --- a/test_regress/t/t_tri_inout.v +++ b/test_regress/t/t_tri_inout.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 module top (input A, input B, input SEL, output Y1, output Y2, output Z); io io1(.A(A), .OE( SEL), .Z(Z), .Y(Y1)); diff --git a/test_regress/t/t_tri_inout2.pl b/test_regress/t/t_tri_inout2.pl index 9904360ae..1d046ed3f 100755 --- a/test_regress/t/t_tri_inout2.pl +++ b/test_regress/t/t_tri_inout2.pl @@ -2,9 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU -# General Public License or the Perl Artistic License. +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_inout2.v b/test_regress/t/t_tri_inout2.v index a7b66982e..fef98bff2 100644 --- a/test_regress/t/t_tri_inout2.v +++ b/test_regress/t/t_tri_inout2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_inz.cpp b/test_regress/t/t_tri_inz.cpp index 127ddd8de..a2674bda5 100644 --- a/test_regress/t/t_tri_inz.cpp +++ b/test_regress/t/t_tri_inz.cpp @@ -1,4 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_inz.h" diff --git a/test_regress/t/t_tri_inz.pl b/test_regress/t/t_tri_inz.pl index e50597b5e..0f7f6d060 100755 --- a/test_regress/t/t_tri_inz.pl +++ b/test_regress/t/t_tri_inz.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2018 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2018 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_inz.v b/test_regress/t/t_tri_inz.v index 6baa8e6c5..f26fce1cd 100644 --- a/test_regress/t/t_tri_inz.v +++ b/test_regress/t/t_tri_inz.v @@ -1,5 +1,8 @@ -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module top (input d, diff --git a/test_regress/t/t_tri_public.pl b/test_regress/t/t_tri_public.pl index 6312119ef..c8c83176b 100755 --- a/test_regress/t/t_tri_public.pl +++ b/test_regress/t/t_tri_public.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_public.v b/test_regress/t/t_tri_public.v index f18f980d3..1ab31be63 100644 --- a/test_regress/t/t_tri_public.v +++ b/test_regress/t/t_tri_public.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Rob Stoddard. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_tri_pull01.pl b/test_regress/t/t_tri_pull01.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_tri_pull01.pl +++ b/test_regress/t/t_tri_pull01.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_pull01.v b/test_regress/t/t_tri_pull01.v index e38765f8d..2d1248a9b 100644 --- a/test_regress/t/t_tri_pull01.v +++ b/test_regress/t/t_tri_pull01.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_pull2_bad.out b/test_regress/t/t_tri_pull2_bad.out index f8b81e684..f80de4b1f 100644 --- a/test_regress/t/t_tri_pull2_bad.out +++ b/test_regress/t/t_tri_pull2_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_tri_pull2_bad.v:9: Unsupported: Conflicting pull directions. - : ... In instance t - pullup p1(A); - ^~ - t/t_tri_pull2_bad.v:19: ... Location of conflicting pull. - pulldown p2(A); - ^~ +%Error: t/t_tri_pull2_bad.v:12:11: Unsupported: Conflicting pull directions. + : ... In instance t + 12 | pullup p1(A); + | ^~ + t/t_tri_pull2_bad.v:22:13: ... Location of conflicting pull. + 22 | pulldown p2(A); + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_tri_pull2_bad.pl b/test_regress/t/t_tri_pull2_bad.pl index 43933e6ae..c1dba4c49 100755 --- a/test_regress/t/t_tri_pull2_bad.pl +++ b/test_regress/t/t_tri_pull2_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_pull2_bad.v b/test_regress/t/t_tri_pull2_bad.v index 26080aeae..5c8fbc500 100644 --- a/test_regress/t/t_tri_pull2_bad.v +++ b/test_regress/t/t_tri_pull2_bad.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_tri_pull_bad.out b/test_regress/t/t_tri_pull_bad.out index 518ace295..f9e60554b 100644 --- a/test_regress/t/t_tri_pull_bad.out +++ b/test_regress/t/t_tri_pull_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_tri_pull_bad.v:10: Unsupported: Conflicting pull directions. - : ... In instance t - pulldown p2(A); - ^~ - t/t_tri_pull_bad.v:9: ... Location of conflicting pull. - pullup p1(A); - ^~ +%Error: t/t_tri_pull_bad.v:13:13: Unsupported: Conflicting pull directions. + : ... In instance t + 13 | pulldown p2(A); + | ^~ + t/t_tri_pull_bad.v:12:11: ... Location of conflicting pull. + 12 | pullup p1(A); + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_tri_pull_bad.pl b/test_regress/t/t_tri_pull_bad.pl index 43933e6ae..c1dba4c49 100755 --- a/test_regress/t/t_tri_pull_bad.pl +++ b/test_regress/t/t_tri_pull_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_pull_bad.v b/test_regress/t/t_tri_pull_bad.v index 8241a7a3b..793786a1a 100644 --- a/test_regress/t/t_tri_pull_bad.v +++ b/test_regress/t/t_tri_pull_bad.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2010 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_tri_pullup.cpp b/test_regress/t/t_tri_pullup.cpp index e487ae342..4906ed218 100644 --- a/test_regress/t/t_tri_pullup.cpp +++ b/test_regress/t/t_tri_pullup.cpp @@ -1,7 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_pullup.h" diff --git a/test_regress/t/t_tri_pullup.pl b/test_regress/t/t_tri_pullup.pl index 6c781245e..4d136dc52 100755 --- a/test_regress/t/t_tri_pullup.pl +++ b/test_regress/t/t_tri_pullup.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_pullup.v b/test_regress/t/t_tri_pullup.v index 68617da5c..00c41ce0a 100644 --- a/test_regress/t/t_tri_pullup.v +++ b/test_regress/t/t_tri_pullup.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 module top (input A, input OE, output X, output Y, output Z); diff --git a/test_regress/t/t_tri_pullvec_bad.out b/test_regress/t/t_tri_pullvec_bad.out index 290cd83b8..68bf7c55d 100644 --- a/test_regress/t/t_tri_pullvec_bad.out +++ b/test_regress/t/t_tri_pullvec_bad.out @@ -1,15 +1,15 @@ -%Error: t/t_tri_pullvec_bad.v:10: Unsupported: Conflicting pull directions. - : ... In instance t - pulldown p1 (w[1]); - ^~ - t/t_tri_pullvec_bad.v:9: ... Location of conflicting pull. - pullup p0 (w[0]); - ^~ -%Error: t/t_tri_pullvec_bad.v:11: Unsupported: Conflicting pull directions. - : ... In instance t - pulldown p2 (w[2]); - ^~ - t/t_tri_pullvec_bad.v:9: ... Location of conflicting pull. - pullup p0 (w[0]); - ^~ +%Error: t/t_tri_pullvec_bad.v:13:13: Unsupported: Conflicting pull directions. + : ... In instance t + 13 | pulldown p1 (w[1]); + | ^~ + t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. + 12 | pullup p0 (w[0]); + | ^~ +%Error: t/t_tri_pullvec_bad.v:14:13: Unsupported: Conflicting pull directions. + : ... In instance t + 14 | pulldown p2 (w[2]); + | ^~ + t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. + 12 | pullup p0 (w[0]); + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_tri_pullvec_bad.pl b/test_regress/t/t_tri_pullvec_bad.pl index 2bfe462ad..2e7d95bc6 100755 --- a/test_regress/t/t_tri_pullvec_bad.pl +++ b/test_regress/t/t_tri_pullvec_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_tri_pullvec_bad.v b/test_regress/t/t_tri_pullvec_bad.v index c0724c40e..cd38fd202 100644 --- a/test_regress/t/t_tri_pullvec_bad.v +++ b/test_regress/t/t_tri_pullvec_bad.v @@ -1,5 +1,8 @@ -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_tri_select.cpp b/test_regress/t/t_tri_select.cpp index cf023bdee..6e76584e9 100644 --- a/test_regress/t/t_tri_select.cpp +++ b/test_regress/t/t_tri_select.cpp @@ -1,4 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include "Vt_tri_select.h" diff --git a/test_regress/t/t_tri_select.pl b/test_regress/t/t_tri_select.pl index 6c781245e..4d136dc52 100755 --- a/test_regress/t/t_tri_select.pl +++ b/test_regress/t/t_tri_select.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_tri_select.v b/test_regress/t/t_tri_select.v index 48714cf73..a270dd927 100644 --- a/test_regress/t/t_tri_select.v +++ b/test_regress/t/t_tri_select.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 `define WIDTH 2 diff --git a/test_regress/t/t_tri_select_unsized.pl b/test_regress/t/t_tri_select_unsized.pl index bbe51465d..6b3816add 100755 --- a/test_regress/t/t_tri_select_unsized.pl +++ b/test_regress/t/t_tri_select_unsized.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_select_unsized.v b/test_regress/t/t_tri_select_unsized.v index f626d28a5..6c9430780 100644 --- a/test_regress/t/t_tri_select_unsized.v +++ b/test_regress/t/t_tri_select_unsized.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2012 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_unconn.pl b/test_regress/t/t_tri_unconn.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_tri_unconn.pl +++ b/test_regress/t/t_tri_unconn.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_unconn.v b/test_regress/t/t_tri_unconn.v index d90db96d7..368c2638f 100644 --- a/test_regress/t/t_tri_unconn.v +++ b/test_regress/t/t_tri_unconn.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_tri_various.pl b/test_regress/t/t_tri_various.pl index 1be18a66c..6e82e9cdb 100755 --- a/test_regress/t/t_tri_various.pl +++ b/test_regress/t/t_tri_various.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_tri_various.v b/test_regress/t/t_tri_various.v index 945130d70..9aa9dbcf0 100644 --- a/test_regress/t/t_tri_various.v +++ b/test_regress/t/t_tri_various.v @@ -1,5 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Lane Brooks +// without warranty, 2008 by Lane Brooks. +// SPDX-License-Identifier: CC0-1.0 module t (clk); input clk; diff --git a/test_regress/t/t_type.pl b/test_regress/t/t_type.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_type.pl +++ b/test_regress/t/t_type.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_type.v b/test_regress/t/t_type.v index f0f0e029f..bb8bd852a 100644 --- a/test_regress/t/t_type.v +++ b/test_regress/t/t_type.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t(/*AUTOARG*/); diff --git a/test_regress/t/t_type_param.pl b/test_regress/t/t_type_param.pl index b78f33caa..f4ca8a9d8 100755 --- a/test_regress/t/t_type_param.pl +++ b/test_regress/t/t_type_param.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_type_param.v b/test_regress/t/t_type_param.v index b2bf9865c..891f7da2a 100644 --- a/test_regress/t/t_type_param.v +++ b/test_regress/t/t_type_param.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Todd Strader. +// SPDX-License-Identifier: CC0-1.0 module foo #(parameter type bar = logic) diff --git a/test_regress/t/t_type_param_collision.pl b/test_regress/t/t_type_param_collision.pl index 6d50174d7..28b538faf 100755 --- a/test_regress/t/t_type_param_collision.pl +++ b/test_regress/t/t_type_param_collision.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Todd Strader. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Todd Strader. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_typedef.pl b/test_regress/t/t_typedef.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_typedef.pl +++ b/test_regress/t/t_typedef.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_typedef.v b/test_regress/t/t_typedef.v index 58ccd88bd..78f966825 100644 --- a/test_regress/t/t_typedef.v +++ b/test_regress/t/t_typedef.v @@ -1,11 +1,14 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 program t; parameter SIZE = 5; + typedef vec_t; // Forward + typedef reg [SIZE-1:0] vec_t ; vec_t a; initial a =0; diff --git a/test_regress/t/t_typedef_array.pl b/test_regress/t/t_typedef_array.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_typedef_array.pl +++ b/test_regress/t/t_typedef_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_typedef_array.v b/test_regress/t/t_typedef_array.v index cabcf3b2e..018d6abbd 100644 --- a/test_regress/t/t_typedef_array.v +++ b/test_regress/t/t_typedef_array.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by James Pallister. +// SPDX-License-Identifier: CC0-1.0 typedef logic logic_alias_t; diff --git a/test_regress/t/t_typedef_circ_bad.out b/test_regress/t/t_typedef_circ_bad.out index 33179862f..4c0dd704b 100644 --- a/test_regress/t/t_typedef_circ_bad.out +++ b/test_regress/t/t_typedef_circ_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_typedef_circ_bad.v:5: Typedef's type is circular: a_t -typedef a_t b_t; - ^~~ +%Error: t/t_typedef_circ_bad.v:8:9: Typedef's type is circular: a_t + 8 | typedef a_t b_t; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_typedef_circ_bad.pl b/test_regress/t/t_typedef_circ_bad.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_typedef_circ_bad.pl +++ b/test_regress/t/t_typedef_circ_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_typedef_circ_bad.v b/test_regress/t/t_typedef_circ_bad.v index 5c2075242..937eb24bb 100644 --- a/test_regress/t/t_typedef_circ_bad.v +++ b/test_regress/t/t_typedef_circ_bad.v @@ -1,5 +1,8 @@ -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 typedef a_t; typedef a_t b_t; diff --git a/test_regress/t/t_typedef_package.pl b/test_regress/t/t_typedef_package.pl new file mode 100755 index 000000000..1d046ed3f --- /dev/null +++ b/test_regress/t/t_typedef_package.pl @@ -0,0 +1,21 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_typedef_package.v b/test_regress/t/t_typedef_package.v new file mode 100644 index 000000000..d3ce84cca --- /dev/null +++ b/test_regress/t/t_typedef_package.v @@ -0,0 +1,24 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2020 by Driss Hafdi. +// SPDX-License-Identifier: CC0-1.0 + +package pkg1; + typedef logic [7:0] uint8_t; +endpackage + +package pkg2; + typedef enum pkg1::uint8_t { + a = 8'd1, + b = 8'd2 + } opts; +endpackage + +module t (/*AUTOARG*/); + initial begin + $display("%d", pkg2::a); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_typedef_param.pl b/test_regress/t/t_typedef_param.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_typedef_param.pl +++ b/test_regress/t/t_typedef_param.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_typedef_param.v b/test_regress/t/t_typedef_param.v index 4cbba8f20..c9c98202f 100644 --- a/test_regress/t/t_typedef_param.v +++ b/test_regress/t/t_typedef_param.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 typedef reg [2:0] threeansi_t; diff --git a/test_regress/t/t_typedef_port.pl b/test_regress/t/t_typedef_port.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_typedef_port.pl +++ b/test_regress/t/t_typedef_port.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_typedef_port.v b/test_regress/t/t_typedef_port.v index 0bc651432..44d24d05d 100644 --- a/test_regress/t/t_typedef_port.v +++ b/test_regress/t/t_typedef_port.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 typedef reg [2:0] threeansi_t; diff --git a/test_regress/t/t_typedef_signed.pl b/test_regress/t/t_typedef_signed.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_typedef_signed.pl +++ b/test_regress/t/t_typedef_signed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_typedef_signed.v b/test_regress/t/t_typedef_signed.v index 2432f94a5..0f7bf55ee 100644 --- a/test_regress/t/t_typedef_signed.v +++ b/test_regress/t/t_typedef_signed.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug456 diff --git a/test_regress/t/t_typedef_unused_bad.out b/test_regress/t/t_typedef_unused_bad.out new file mode 100644 index 000000000..0d5e678af --- /dev/null +++ b/test_regress/t/t_typedef_unused_bad.out @@ -0,0 +1,4 @@ +%Error: t/t_typedef_unused_bad.v:9:9: Forward typedef unused or does not resolve to a data type (IEEE 1800-2017 6.18): 'fwd_undecl_t' + 9 | typedef fwd_undecl_t; + | ^~~~~~~~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_typedef_unused_bad.pl b/test_regress/t/t_typedef_unused_bad.pl new file mode 100755 index 000000000..7c259dcfb --- /dev/null +++ b/test_regress/t/t_typedef_unused_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + verilator_flags2 => ["--Wpedantic"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_typedef_unused_bad.v b/test_regress/t/t_typedef_unused_bad.v new file mode 100644 index 000000000..896840cd7 --- /dev/null +++ b/test_regress/t/t_typedef_unused_bad.v @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +typedef logic ok_t; + +typedef fwd_undecl_t; diff --git a/test_regress/t/t_typename.pl b/test_regress/t/t_typename.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_typename.pl +++ b/test_regress/t/t_typename.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_typename.v b/test_regress/t/t_typename.v index 7edda4a3a..c76ee0e05 100644 --- a/test_regress/t/t_typename.v +++ b/test_regress/t/t_typename.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0); diff --git a/test_regress/t/t_udp.v b/test_regress/t/t_udp.v index e946fd876..a40afa70e 100644 --- a/test_regress/t/t_udp.v +++ b/test_regress/t/t_udp.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_udp_bad.out b/test_regress/t/t_udp_bad.out index 2ab137bee..ff1599baa 100644 --- a/test_regress/t/t_udp_bad.out +++ b/test_regress/t/t_udp_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_udp.v:103: Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables. - table - ^~~~~ +%Error: t/t_udp.v:104:4: Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables. + 104 | table + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad.pl b/test_regress/t/t_udp_bad.pl index 79dccc3a2..90bbf23a2 100755 --- a/test_regress/t/t_udp_bad.pl +++ b/test_regress/t/t_udp_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_udp_lint.pl b/test_regress/t/t_udp_lint.pl index 7b441fd91..a49bf45aa 100755 --- a/test_regress/t/t_udp_lint.pl +++ b/test_regress/t/t_udp_lint.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_udp_noname.pl b/test_regress/t/t_udp_noname.pl index 677a9e770..cf8db6e7e 100755 --- a/test_regress/t/t_udp_noname.pl +++ b/test_regress/t/t_udp_noname.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug468"); diff --git a/test_regress/t/t_udp_noname.v b/test_regress/t/t_udp_noname.v index 4ac198647..258f6f42e 100644 --- a/test_regress/t/t_udp_noname.v +++ b/test_regress/t/t_udp_noname.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unicode.pl b/test_regress/t/t_unicode.pl index ecc4c14c2..0dfe66ecb 100755 --- a/test_regress/t/t_unicode.pl +++ b/test_regress/t/t_unicode.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 use IO::File; #use Data::Dumper; use strict; diff --git a/test_regress/t/t_uniqueif.pl b/test_regress/t/t_uniqueif.pl index f97a8c4aa..4c0a46a1c 100755 --- a/test_regress/t/t_uniqueif.pl +++ b/test_regress/t/t_uniqueif.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_uniqueif.v b/test_regress/t/t_uniqueif.v index 7700eb5cb..137b860f2 100644 --- a/test_regress/t/t_uniqueif.v +++ b/test_regress/t/t_uniqueif.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_uniqueif_fail1.out b/test_regress/t/t_uniqueif_fail1.out new file mode 100644 index 000000000..7767184d8 --- /dev/null +++ b/test_regress/t/t_uniqueif_fail1.out @@ -0,0 +1,4 @@ +testing fail 1: 1 +[10] %Error: t_uniqueif.v:74: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:74: Verilog $stop +Aborting... diff --git a/test_regress/t/t_uniqueif_fail1.pl b/test_regress/t/t_uniqueif_fail1.pl index 0f4d84c8b..dd4176156 100755 --- a/test_regress/t/t_uniqueif_fail1.pl +++ b/test_regress/t/t_uniqueif_fail1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -20,10 +21,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated -%Error: t/t_uniqueif.v:\d+: Verilog \$stop -.*', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_uniqueif_fail2.out b/test_regress/t/t_uniqueif_fail2.out new file mode 100644 index 000000000..cba3a812b --- /dev/null +++ b/test_regress/t/t_uniqueif_fail2.out @@ -0,0 +1,3 @@ +[10] %Error: t_uniqueif.v:82: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:82: Verilog $stop +Aborting... diff --git a/test_regress/t/t_uniqueif_fail2.pl b/test_regress/t/t_uniqueif_fail2.pl index 49fd1027f..7e98ebff7 100755 --- a/test_regress/t/t_uniqueif_fail2.pl +++ b/test_regress/t/t_uniqueif_fail2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -20,10 +21,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated -%Error: t/t_uniqueif.v:\d+: Verilog \$stop -.*', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_uniqueif_fail3.out b/test_regress/t/t_uniqueif_fail3.out new file mode 100644 index 000000000..02b41441b --- /dev/null +++ b/test_regress/t/t_uniqueif_fail3.out @@ -0,0 +1,3 @@ +[10] %Error: t_uniqueif.v:90: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:90: Verilog $stop +Aborting... diff --git a/test_regress/t/t_uniqueif_fail3.pl b/test_regress/t/t_uniqueif_fail3.pl index 5ac0fa625..2c56473fb 100755 --- a/test_regress/t/t_uniqueif_fail3.pl +++ b/test_regress/t/t_uniqueif_fail3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -20,10 +21,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated -%Error: t/t_uniqueif.v:\d+: Verilog \$stop -.*', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_uniqueif_fail4.out b/test_regress/t/t_uniqueif_fail4.out new file mode 100644 index 000000000..3e327cbff --- /dev/null +++ b/test_regress/t/t_uniqueif_fail4.out @@ -0,0 +1,3 @@ +[10] %Error: t_uniqueif.v:102: Assertion failed in top.t: 'unique if' statement violated +%Error: t/t_uniqueif.v:102: Verilog $stop +Aborting... diff --git a/test_regress/t/t_uniqueif_fail4.pl b/test_regress/t/t_uniqueif_fail4.pl index 70f1622db..1c5269864 100755 --- a/test_regress/t/t_uniqueif_fail4.pl +++ b/test_regress/t/t_uniqueif_fail4.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -20,10 +21,7 @@ compile( execute( fails => $Self->{vlt_all}, - expect => -'.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated -%Error: t/t_uniqueif.v:\d+: Verilog \$stop -.*', + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_unopt_array.pl b/test_regress/t/t_unopt_array.pl index e9c629464..703ea7959 100755 --- a/test_regress/t/t_unopt_array.pl +++ b/test_regress/t/t_unopt_array.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unopt_array.v b/test_regress/t/t_unopt_array.v index ab2faede7..1158c8bb4 100644 --- a/test_regress/t/t_unopt_array.v +++ b/test_regress/t/t_unopt_array.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unopt_array_csplit.pl b/test_regress/t/t_unopt_array_csplit.pl index 27ec9551f..3022bb2d4 100755 --- a/test_regress/t/t_unopt_array_csplit.pl +++ b/test_regress/t/t_unopt_array_csplit.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_unopt_bound.pl b/test_regress/t/t_unopt_bound.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_unopt_bound.pl +++ b/test_regress/t/t_unopt_bound.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unopt_bound.v b/test_regress/t/t_unopt_bound.v index ba60499c1..f02be70b5 100644 --- a/test_regress/t/t_unopt_bound.v +++ b/test_regress/t/t_unopt_bound.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jue Xu. +// SPDX-License-Identifier: CC0-1.0 // bug630 diff --git a/test_regress/t/t_unopt_combo.pl b/test_regress/t/t_unopt_combo.pl index d8968a2c2..8dff1bf03 100755 --- a/test_regress/t/t_unopt_combo.pl +++ b/test_regress/t/t_unopt_combo.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unopt_combo.v b/test_regress/t/t_unopt_combo.v index 8e74883f2..c4d7e6d14 100644 --- a/test_regress/t/t_unopt_combo.v +++ b/test_regress/t/t_unopt_combo.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unopt_combo_bad.out b/test_regress/t/t_unopt_combo_bad.out index 6c675c42b..a4be2fab5 100644 --- a/test_regress/t/t_unopt_combo_bad.out +++ b/test_regress/t/t_unopt_combo_bad.out @@ -1,10 +1,10 @@ -%Warning-UNOPTFLAT: t/t_unopt_combo.v:23: Signal unoptimizable: Feedback to clock or circular logic: 't.c' - wire [31:0] c; - ^ +%Warning-UNOPTFLAT: t/t_unopt_combo.v:24:25: Signal unoptimizable: Feedback to clock or circular logic: 't.c' + 24 | wire [31:0] c; + | ^ ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. - t/t_unopt_combo.v:23: Example path: t.c - t/t_unopt_combo.v:80: Example path: ALWAYS - t/t_unopt_combo.v:22: Example path: t.b - t/t_unopt_combo.v:123: Example path: ALWAYS - t/t_unopt_combo.v:23: Example path: t.c + t/t_unopt_combo.v:24:25: Example path: t.c + t/t_unopt_combo.v:81:4: Example path: ALWAYS + t/t_unopt_combo.v:23:25: Example path: t.b + t/t_unopt_combo.v:124:4: Example path: ALWAYS + t/t_unopt_combo.v:24:25: Example path: t.c %Error: Exiting due to diff --git a/test_regress/t/t_unopt_combo_bad.pl b/test_regress/t/t_unopt_combo_bad.pl index 81bf42fa9..c89d32b25 100755 --- a/test_regress/t/t_unopt_combo_bad.pl +++ b/test_regress/t/t_unopt_combo_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unopt_combo_isolate.pl b/test_regress/t/t_unopt_combo_isolate.pl index 874c44f07..1791984a2 100755 --- a/test_regress/t/t_unopt_combo_isolate.pl +++ b/test_regress/t/t_unopt_combo_isolate.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -18,11 +19,11 @@ compile( if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_unopt_combo_isolate.vlt b/test_regress/t/t_unopt_combo_isolate.vlt index 44546c5a9..1fe38e10e 100644 --- a/test_regress/t/t_unopt_combo_isolate.vlt +++ b/test_regress/t/t_unopt_combo_isolate.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_unopt_combo_isolate_vlt.pl b/test_regress/t/t_unopt_combo_isolate_vlt.pl index 25cf700f7..e89062929 100755 --- a/test_regress/t/t_unopt_combo_isolate_vlt.pl +++ b/test_regress/t/t_unopt_combo_isolate_vlt.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -18,11 +19,11 @@ compile( if ($Self->{vlt_all}) { file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); - file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); + file_grep("$out_filename", qr/\/i); } execute( diff --git a/test_regress/t/t_unopt_converge.v b/test_regress/t/t_unopt_converge.v index fc2e23591..702c0f32a 100644 --- a/test_regress/t/t_unopt_converge.v +++ b/test_regress/t/t_unopt_converge.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_unopt_converge_initial.v b/test_regress/t/t_unopt_converge_initial.v index 7806042a4..abfc6f32e 100644 --- a/test_regress/t/t_unopt_converge_initial.v +++ b/test_regress/t/t_unopt_converge_initial.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_unopt_converge_initial_run_bad.out b/test_regress/t/t_unopt_converge_initial_run_bad.out index 3c8924f4f..56c0369a6 100644 --- a/test_regress/t/t_unopt_converge_initial_run_bad.out +++ b/test_regress/t/t_unopt_converge_initial_run_bad.out @@ -1,5 +1,5 @@ -V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_unopt_converge_initial_run_bad::_change_request --V{t#,#} CHANGE: t/t_unopt_converge_initial.v:18: x -%Error: t/t_unopt_converge_initial.v:6: Verilated model didn't DC converge +-V{t#,#} CHANGE: t/t_unopt_converge_initial.v:19: x +%Error: t/t_unopt_converge_initial.v:7: Verilated model didn't DC converge Aborting... diff --git a/test_regress/t/t_unopt_converge_initial_run_bad.pl b/test_regress/t/t_unopt_converge_initial_run_bad.pl index b680fe33d..388e31558 100755 --- a/test_regress/t/t_unopt_converge_initial_run_bad.pl +++ b/test_regress/t/t_unopt_converge_initial_run_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2007 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2007 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unopt_converge_ndbg_bad.out b/test_regress/t/t_unopt_converge_ndbg_bad.out index 1484d8577..c54c40377 100644 --- a/test_regress/t/t_unopt_converge_ndbg_bad.out +++ b/test_regress/t/t_unopt_converge_ndbg_bad.out @@ -1,2 +1,2 @@ -%Error: t/t_unopt_converge.v:6: Verilated model didn't converge +%Error: t/t_unopt_converge.v:7: Verilated model didn't converge Aborting... diff --git a/test_regress/t/t_unopt_converge_ndbg_bad.pl b/test_regress/t/t_unopt_converge_ndbg_bad.pl index a2cc6c968..a1444cabe 100755 --- a/test_regress/t/t_unopt_converge_ndbg_bad.pl +++ b/test_regress/t/t_unopt_converge_ndbg_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2007 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2007 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unopt_converge_print_bad.out b/test_regress/t/t_unopt_converge_print_bad.out index 3cc147cb3..328c68219 100644 --- a/test_regress/t/t_unopt_converge_print_bad.out +++ b/test_regress/t/t_unopt_converge_print_bad.out @@ -1,5 +1,5 @@ -V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_unopt_converge_print_bad::_change_request --V{t#,#} CHANGE: t/t_unopt_converge.v:18: x -%Error: t/t_unopt_converge.v:6: Verilated model didn't converge +-V{t#,#} CHANGE: t/t_unopt_converge.v:19: x +%Error: t/t_unopt_converge.v:7: Verilated model didn't converge Aborting... diff --git a/test_regress/t/t_unopt_converge_print_bad.pl b/test_regress/t/t_unopt_converge_print_bad.pl index b2d9c3bfe..69982d4b5 100755 --- a/test_regress/t/t_unopt_converge_print_bad.pl +++ b/test_regress/t/t_unopt_converge_print_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2007 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2007 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unopt_converge_run_bad.out b/test_regress/t/t_unopt_converge_run_bad.out index bd3150508..6f057f8d1 100644 --- a/test_regress/t/t_unopt_converge_run_bad.out +++ b/test_regress/t/t_unopt_converge_run_bad.out @@ -1,5 +1,5 @@ -V{t#,#}- Verilated::debug is on. Message prefix indicates {,}. -V{t#,#}+ Vt_unopt_converge_run_bad::_change_request --V{t#,#} CHANGE: t/t_unopt_converge.v:18: x -%Error: t/t_unopt_converge.v:6: Verilated model didn't converge +-V{t#,#} CHANGE: t/t_unopt_converge.v:19: x +%Error: t/t_unopt_converge.v:7: Verilated model didn't converge Aborting... diff --git a/test_regress/t/t_unopt_converge_run_bad.pl b/test_regress/t/t_unopt_converge_run_bad.pl index b6a17767b..48b386937 100755 --- a/test_regress/t/t_unopt_converge_run_bad.pl +++ b/test_regress/t/t_unopt_converge_run_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2007 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2007 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unopt_converge_unopt_bad.out b/test_regress/t/t_unopt_converge_unopt_bad.out index 9e70e6ee2..2a978fa65 100644 --- a/test_regress/t/t_unopt_converge_unopt_bad.out +++ b/test_regress/t/t_unopt_converge_unopt_bad.out @@ -1,8 +1,8 @@ -%Warning-UNOPT: t/t_unopt_converge.v:18: Signal unoptimizable: Feedback to public clock or circular logic: 'x' - output x; - ^ +%Warning-UNOPT: t/t_unopt_converge.v:19:11: Signal unoptimizable: Feedback to public clock or circular logic: 'x' + 19 | output x; + | ^ ... Use "/* verilator lint_off UNOPT */" and lint_on around source to disable this message. - t/t_unopt_converge.v:18: Example path: x - t/t_unopt_converge.v:21: Example path: ALWAYS - t/t_unopt_converge.v:18: Example path: x + t/t_unopt_converge.v:19:11: Example path: x + t/t_unopt_converge.v:22:4: Example path: ALWAYS + t/t_unopt_converge.v:19:11: Example path: x %Error: Exiting due to diff --git a/test_regress/t/t_unopt_converge_unopt_bad.pl b/test_regress/t/t_unopt_converge_unopt_bad.pl index 0310a823a..7d8530609 100755 --- a/test_regress/t/t_unopt_converge_unopt_bad.pl +++ b/test_regress/t/t_unopt_converge_unopt_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2007 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2007 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_unoptflat_simple.v b/test_regress/t/t_unoptflat_simple.v index f3e5be00d..7c9f63f82 100644 --- a/test_regress/t/t_unoptflat_simple.v +++ b/test_regress/t/t_unoptflat_simple.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unoptflat_simple_2.v b/test_regress/t/t_unoptflat_simple_2.v index 56feec201..549f69b43 100644 --- a/test_regress/t/t_unoptflat_simple_2.v +++ b/test_regress/t/t_unoptflat_simple_2.v @@ -4,6 +4,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unoptflat_simple_2_bad.out b/test_regress/t/t_unoptflat_simple_2_bad.out index ff0be7f54..e03cad9b2 100644 --- a/test_regress/t/t_unoptflat_simple_2_bad.out +++ b/test_regress/t/t_unoptflat_simple_2_bad.out @@ -1,13 +1,13 @@ -%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:14: Signal unoptimizable: Feedback to clock or circular logic: 't.x' - wire [2:0] x; - ^ +%Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:15:15: Signal unoptimizable: Feedback to clock or circular logic: 't.x' + 15 | wire [2:0] x; + | ^ ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. - t/t_unoptflat_simple_2.v:14: Example path: t.x - t/t_unoptflat_simple_2.v:16: Example path: ASSIGNW - t/t_unoptflat_simple_2.v:14: Example path: t.x + t/t_unoptflat_simple_2.v:15:15: Example path: t.x + t/t_unoptflat_simple_2.v:17:18: Example path: ASSIGNW + t/t_unoptflat_simple_2.v:15:15: Example path: t.x ... Widest candidate vars to split: - t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 10, can split_var + t/t_unoptflat_simple_2.v:15:15: t.x, width 3, fanout 10, can split_var ... Most fanned out candidate vars to split: - t/t_unoptflat_simple_2.v:14: t.x, width 3, fanout 10, can split_var + t/t_unoptflat_simple_2.v:15:15: t.x, width 3, fanout 10, can split_var ... Suggest add /*verilator split_var*/ to appropriate variables above. %Error: Exiting due to diff --git a/test_regress/t/t_unoptflat_simple_2_bad.pl b/test_regress/t/t_unoptflat_simple_2_bad.pl index 18b3fcc9b..740fdb35c 100755 --- a/test_regress/t/t_unoptflat_simple_2_bad.pl +++ b/test_regress/t/t_unoptflat_simple_2_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unoptflat_simple_3.v b/test_regress/t/t_unoptflat_simple_3.v index d8a469169..09c33e22a 100644 --- a/test_regress/t/t_unoptflat_simple_3.v +++ b/test_regress/t/t_unoptflat_simple_3.v @@ -5,6 +5,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jeremy Bennett. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unoptflat_simple_3_bad.pl b/test_regress/t/t_unoptflat_simple_3_bad.pl index a16bb204b..69b727070 100755 --- a/test_regress/t/t_unoptflat_simple_3_bad.pl +++ b/test_regress/t/t_unoptflat_simple_3_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unoptflat_simple_bad.pl b/test_regress/t/t_unoptflat_simple_bad.pl index 179c80e5a..d12e45fe3 100755 --- a/test_regress/t/t_unoptflat_simple_bad.pl +++ b/test_regress/t/t_unoptflat_simple_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unpacked_array_order.pl b/test_regress/t/t_unpacked_array_order.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_unpacked_array_order.pl +++ b/test_regress/t/t_unpacked_array_order.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unpacked_array_order.v b/test_regress/t/t_unpacked_array_order.v index ea1c67ad3..adee38eec 100644 --- a/test_regress/t/t_unpacked_array_order.v +++ b/test_regress/t/t_unpacked_array_order.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Duraid Madina. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unpacked_concat_bad.out b/test_regress/t/t_unpacked_concat_bad.out index 53dcbfdee..f47940153 100644 --- a/test_regress/t/t_unpacked_concat_bad.out +++ b/test_regress/t/t_unpacked_concat_bad.out @@ -1,22 +1,22 @@ -%Error: t/t_unpacked_concat_bad.v:16: Unsupported: Replication to form 'bit[31:0]$[1:0]' data type - : ... In instance t - localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; - ^ -%Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:16: Unsized numbers/parameters not allowed in replications. - : ... In instance t - localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; - ^~~~~ +%Error: t/t_unpacked_concat_bad.v:17:46: Unsupported: Replication to form 'bit[31:0]$[1:0]' data type + : ... In instance t + 17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; + | ^ +%Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:17:47: Unsized numbers/parameters not allowed in replications. + : ... In instance t + 17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; + | ^~~~~ ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. -%Error: t/t_unpacked_concat_bad.v:17: Unsupported: Replication to form 'bit[31:0]$[1:0]' data type - : ... In instance t - localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; - ^ -%Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:17: Unsized numbers/parameters not allowed in concatenations. - : ... In instance t - localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; - ^~~~~ -%Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:17: Unsized numbers/parameters not allowed in replications. - : ... In instance t - localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; - ^ +%Error: t/t_unpacked_concat_bad.v:18:45: Unsupported: Replication to form 'bit[31:0]$[1:0]' data type + : ... In instance t + 18 | localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; + | ^ +%Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:18:46: Unsized numbers/parameters not allowed in concatenations. + : ... In instance t + 18 | localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; + | ^~~~~ +%Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:18:60: Unsized numbers/parameters not allowed in replications. + : ... In instance t + 18 | localparam bit_int_t count_bitsc [1:0] = {$bits(count_t), $bits(count_t)}; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_unpacked_concat_bad.pl b/test_regress/t/t_unpacked_concat_bad.pl index 49151b6cd..2365c113e 100755 --- a/test_regress/t/t_unpacked_concat_bad.pl +++ b/test_regress/t/t_unpacked_concat_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2019 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_unpacked_concat_bad.v b/test_regress/t/t_unpacked_concat_bad.v index 90947af52..70cb5c37a 100644 --- a/test_regress/t/t_unpacked_concat_bad.v +++ b/test_regress/t/t_unpacked_concat_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Driss Hafdi +// without warranty, 2019 by Driss Hafdi. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unroll_complexcond.pl b/test_regress/t/t_unroll_complexcond.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_unroll_complexcond.pl +++ b/test_regress/t/t_unroll_complexcond.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unroll_complexcond.v b/test_regress/t/t_unroll_complexcond.v index 49592a5c0..6857616c9 100644 --- a/test_regress/t/t_unroll_complexcond.v +++ b/test_regress/t/t_unroll_complexcond.v @@ -6,6 +6,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2013 by Jie Xu. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unroll_forfor.pl b/test_regress/t/t_unroll_forfor.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_unroll_forfor.pl +++ b/test_regress/t/t_unroll_forfor.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unroll_forfor.v b/test_regress/t/t_unroll_forfor.v index fee7b8c00..b43f64ecf 100644 --- a/test_regress/t/t_unroll_forfor.v +++ b/test_regress/t/t_unroll_forfor.v @@ -5,6 +5,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2016 by Jan Egil Ruud. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_unroll_genf.pl b/test_regress/t/t_unroll_genf.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_unroll_genf.pl +++ b/test_regress/t/t_unroll_genf.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unroll_genf.v b/test_regress/t/t_unroll_genf.v index 776f1b328..70d4852c7 100644 --- a/test_regress/t/t_unroll_genf.v +++ b/test_regress/t/t_unroll_genf.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 //bug830 module sub(); diff --git a/test_regress/t/t_unroll_signed.pl b/test_regress/t/t_unroll_signed.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_unroll_signed.pl +++ b/test_regress/t/t_unroll_signed.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_unroll_signed.v b/test_regress/t/t_unroll_signed.v index 38f287b80..5be7038bf 100644 --- a/test_regress/t/t_unroll_signed.v +++ b/test_regress/t/t_unroll_signed.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_vams_basic.pl b/test_regress/t/t_vams_basic.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_vams_basic.pl +++ b/test_regress/t/t_vams_basic.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vams_basic.v b/test_regress/t/t_vams_basic.v index e7caa969d..c658d64e2 100644 --- a/test_regress/t/t_vams_basic.v +++ b/test_regress/t/t_vams_basic.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" diff --git a/test_regress/t/t_vams_wreal.pl b/test_regress/t/t_vams_wreal.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_vams_wreal.pl +++ b/test_regress/t/t_vams_wreal.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vams_wreal.v b/test_regress/t/t_vams_wreal.v index e7b5d037d..d2c453b9b 100644 --- a/test_regress/t/t_vams_wreal.v +++ b/test_regress/t/t_vams_wreal.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `begin_keywords "VAMS-2.3" diff --git a/test_regress/t/t_var_assign_landr.pl b/test_regress/t/t_var_assign_landr.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_assign_landr.pl +++ b/test_regress/t/t_var_assign_landr.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_assign_landr.v b/test_regress/t/t_var_assign_landr.v index 28323e2e2..4713eea8f 100644 --- a/test_regress/t/t_var_assign_landr.v +++ b/test_regress/t/t_var_assign_landr.v @@ -1,19 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// Use this file as a template for submitting bugs, etc. -// This module takes a single clock input, and should either -// $write("*-* All Finished *-*\n"); -// $finish; -// on success, or $stop. -// -// The code as shown applies a random vector to the Test -// module, then calculates a CRC on the Test module's outputs. -// -// **If you do not wish for your code to be released to the public -// please note it here, otherwise:** -// // This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by ____YOUR_NAME_HERE____. +// without warranty, 2014. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_bad_hide.out b/test_regress/t/t_var_bad_hide.out index 865f47ecc..7746fd863 100644 --- a/test_regress/t/t_var_bad_hide.out +++ b/test_regress/t/t_var_bad_hide.out @@ -1,14 +1,14 @@ -%Warning-VARHIDDEN: t/t_var_bad_hide.v:15: Declaration of signal hides declaration in upper scope: 'top' - output top; - ^~~ - t/t_var_bad_hide.v:12: ... Location of original declaration - integer top; - ^~~ +%Warning-VARHIDDEN: t/t_var_bad_hide.v:16:14: Declaration of signal hides declaration in upper scope: 'top' + 16 | output top; + | ^~~ + t/t_var_bad_hide.v:13:12: ... Location of original declaration + 13 | integer top; + | ^~~ ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. -%Warning-VARHIDDEN: t/t_var_bad_hide.v:21: Declaration of signal hides declaration in upper scope: 'top' - integer top; - ^~~ - t/t_var_bad_hide.v:12: ... Location of original declaration - integer top; - ^~~ +%Warning-VARHIDDEN: t/t_var_bad_hide.v:22:18: Declaration of signal hides declaration in upper scope: 'top' + 22 | integer top; + | ^~~ + t/t_var_bad_hide.v:13:12: ... Location of original declaration + 13 | integer top; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_hide.pl b/test_regress/t/t_var_bad_hide.pl index 2daf76efb..b76ca20f1 100755 --- a/test_regress/t/t_var_bad_hide.pl +++ b/test_regress/t/t_var_bad_hide.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_bad_hide.v b/test_regress/t/t_var_bad_hide.v index 95971018e..88130fb8a 100644 --- a/test_regress/t/t_var_bad_hide.v +++ b/test_regress/t/t_var_bad_hide.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_bad_hide2.out b/test_regress/t/t_var_bad_hide2.out index d92a97678..3318750c1 100644 --- a/test_regress/t/t_var_bad_hide2.out +++ b/test_regress/t/t_var_bad_hide2.out @@ -1,8 +1,8 @@ -%Warning-VARHIDDEN: t/t_var_bad_hide2.v:13: Declaration of signal hides declaration in upper scope: 't' - integer t; - ^ - t/t_var_bad_hide2.v:6: ... Location of original declaration -module t; - ^ +%Warning-VARHIDDEN: t/t_var_bad_hide2.v:14:12: Declaration of signal hides declaration in upper scope: 't' + 14 | integer t; + | ^ + t/t_var_bad_hide2.v:7:8: ... Location of original declaration + 7 | module t; + | ^ ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_hide2.pl b/test_regress/t/t_var_bad_hide2.pl index c547cb9f9..58d9f8138 100755 --- a/test_regress/t/t_var_bad_hide2.pl +++ b/test_regress/t/t_var_bad_hide2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_bad_hide2.v b/test_regress/t/t_var_bad_hide2.v index 1ae2317e6..2861ac167 100644 --- a/test_regress/t/t_var_bad_hide2.v +++ b/test_regress/t/t_var_bad_hide2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_bad_sameas.out b/test_regress/t/t_var_bad_sameas.out index 05cc448ab..e2a345466 100644 --- a/test_regress/t/t_var_bad_sameas.out +++ b/test_regress/t/t_var_bad_sameas.out @@ -1,31 +1,31 @@ -%Error: t/t_var_bad_sameas.v:9: Unsupported in C: Cell has the same name as variable: 'varfirst' - sub varfirst (); - ^~~~~~~~ - t/t_var_bad_sameas.v:8: ... Location of original declaration - integer varfirst; - ^~~~~~~~ -%Error: t/t_var_bad_sameas.v:10: Unsupported in C: Task has the same name as cell: 'varfirst' - task varfirst; begin end endtask - ^~~~~~~~ - t/t_var_bad_sameas.v:9: ... Location of original declaration - sub varfirst (); - ^~~~~~~~ -%Error: t/t_var_bad_sameas.v:13: Unsupported in C: Variable has same name as cell: 'cellfirst' - integer cellfirst; - ^~~~~~~~~ -%Error: t/t_var_bad_sameas.v:14: Unsupported in C: Task has the same name as cell: 'cellfirst' - task cellfirst; begin end endtask - ^~~~~~~~~ - t/t_var_bad_sameas.v:12: ... Location of original declaration - sub cellfirst (); - ^~~~~~~~~ -%Error: t/t_var_bad_sameas.v:17: Unsupported in C: Variable has same name as task: 'taskfirst' - integer taskfirst; - ^~~~~~~~~ -%Error: t/t_var_bad_sameas.v:18: Unsupported in C: Cell has the same name as task: 'taskfirst' - sub taskfirst (); - ^~~~~~~~~ - t/t_var_bad_sameas.v:16: ... Location of original declaration - task taskfirst; begin end endtask - ^~~~~~~~~ +%Error: t/t_var_bad_sameas.v:10:8: Unsupported in C: Cell has the same name as variable: 'varfirst' + 10 | sub varfirst (); + | ^~~~~~~~ + t/t_var_bad_sameas.v:9:12: ... Location of original declaration + 9 | integer varfirst; + | ^~~~~~~~ +%Error: t/t_var_bad_sameas.v:11:9: Unsupported in C: Task has the same name as cell: 'varfirst' + 11 | task varfirst; begin end endtask + | ^~~~~~~~ + t/t_var_bad_sameas.v:10:8: ... Location of original declaration + 10 | sub varfirst (); + | ^~~~~~~~ +%Error: t/t_var_bad_sameas.v:14:12: Unsupported in C: Variable has same name as cell: 'cellfirst' + 14 | integer cellfirst; + | ^~~~~~~~~ +%Error: t/t_var_bad_sameas.v:15:9: Unsupported in C: Task has the same name as cell: 'cellfirst' + 15 | task cellfirst; begin end endtask + | ^~~~~~~~~ + t/t_var_bad_sameas.v:13:8: ... Location of original declaration + 13 | sub cellfirst (); + | ^~~~~~~~~ +%Error: t/t_var_bad_sameas.v:18:12: Unsupported in C: Variable has same name as task: 'taskfirst' + 18 | integer taskfirst; + | ^~~~~~~~~ +%Error: t/t_var_bad_sameas.v:19:8: Unsupported in C: Cell has the same name as task: 'taskfirst' + 19 | sub taskfirst (); + | ^~~~~~~~~ + t/t_var_bad_sameas.v:17:9: ... Location of original declaration + 17 | task taskfirst; begin end endtask + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_sameas.pl b/test_regress/t/t_var_bad_sameas.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_var_bad_sameas.pl +++ b/test_regress/t/t_var_bad_sameas.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_bad_sameas.v b/test_regress/t/t_var_bad_sameas.v index d09fe4a66..65f9178fa 100644 --- a/test_regress/t/t_var_bad_sameas.v +++ b/test_regress/t/t_var_bad_sameas.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_bad_sv.out b/test_regress/t/t_var_bad_sv.out index c97f9325d..c27c1e81c 100644 --- a/test_regress/t/t_var_bad_sv.out +++ b/test_regress/t/t_var_bad_sv.out @@ -1,11 +1,11 @@ -%Error: t/t_var_bad_sv.v:7: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. +%Error: t/t_var_bad_sv.v:8:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. ... Suggest modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language. - reg do; - ^~ -%Error: t/t_var_bad_sv.v:8: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. - mod mod (.do(bar)); - ^~ -%Error: t/t_var_bad_sv.v:8: syntax error, unexpected '(', expecting ')' - mod mod (.do(bar)); - ^~~ + 8 | reg do; + | ^~ +%Error: t/t_var_bad_sv.v:9:14: Unexpected 'do': 'do' is a SystemVerilog keyword misused as an identifier. + 9 | mod mod (.do(bar)); + | ^~ +%Error: t/t_var_bad_sv.v:9:17: syntax error, unexpected '(', expecting ')' + 9 | mod mod (.do(bar)); + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_sv.pl b/test_regress/t/t_var_bad_sv.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_var_bad_sv.pl +++ b/test_regress/t/t_var_bad_sv.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_bad_sv.v b/test_regress/t/t_var_bad_sv.v index f3fb61a63..08bc61ab1 100644 --- a/test_regress/t/t_var_bad_sv.v +++ b/test_regress/t/t_var_bad_sv.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; reg do; diff --git a/test_regress/t/t_var_const.pl b/test_regress/t/t_var_const.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_const.pl +++ b/test_regress/t/t_var_const.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_const.v b/test_regress/t/t_var_const.v index 2eebf5b49..c8ff9be07 100644 --- a/test_regress/t/t_var_const.v +++ b/test_regress/t/t_var_const.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_const_bad.out b/test_regress/t/t_var_const_bad.out index ac39d015c..f29ef0b8a 100644 --- a/test_regress/t/t_var_const_bad.out +++ b/test_regress/t/t_var_const_bad.out @@ -1,5 +1,5 @@ -%Error: t/t_var_const_bad.v:16: Assigning to const variable: 'five' - : ... In instance t - five = 3'd4; - ^~~~ +%Error: t/t_var_const_bad.v:17:7: Assigning to const variable: 'five' + : ... In instance t + 17 | five = 3'd4; + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_const_bad.pl b/test_regress/t/t_var_const_bad.pl index 209e4aea3..fb61de158 100755 --- a/test_regress/t/t_var_const_bad.pl +++ b/test_regress/t/t_var_const_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2005 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2005 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_const_bad.v b/test_regress/t/t_var_const_bad.v index f37a58213..1a1914c21 100644 --- a/test_regress/t/t_var_const_bad.v +++ b/test_regress/t/t_var_const_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2011 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2011 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_dotted1.v b/test_regress/t/t_var_dotted1.v index da1fb4c7b..dd6e79fce 100644 --- a/test_regress/t/t_var_dotted1.v +++ b/test_regress/t/t_var_dotted1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2006 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2006 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_dotted1_inl0.pl b/test_regress/t/t_var_dotted1_inl0.pl index 3dde25892..392cbc8fd 100755 --- a/test_regress/t/t_var_dotted1_inl0.pl +++ b/test_regress/t/t_var_dotted1_inl0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_dotted1_inl1.pl b/test_regress/t/t_var_dotted1_inl1.pl index a1676170d..a9f4d1ec1 100755 --- a/test_regress/t/t_var_dotted1_inl1.pl +++ b/test_regress/t/t_var_dotted1_inl1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_dotted1_inl2.pl b/test_regress/t/t_var_dotted1_inl2.pl index 39dbfed77..37b5ee565 100755 --- a/test_regress/t/t_var_dotted1_inl2.pl +++ b/test_regress/t/t_var_dotted1_inl2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_dotted2.v b/test_regress/t/t_var_dotted2.v index 7138dbd86..ca34202a5 100644 --- a/test_regress/t/t_var_dotted2.v +++ b/test_regress/t/t_var_dotted2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `ifdef USE_INLINE `define INLINE_MODULE /*verilator inline_module*/ diff --git a/test_regress/t/t_var_dotted2_inl0.pl b/test_regress/t/t_var_dotted2_inl0.pl index 8c524642d..269dead50 100755 --- a/test_regress/t/t_var_dotted2_inl0.pl +++ b/test_regress/t/t_var_dotted2_inl0.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_dotted2_inl1.pl b/test_regress/t/t_var_dotted2_inl1.pl index eba0adacc..be6eb9e43 100755 --- a/test_regress/t/t_var_dotted2_inl1.pl +++ b/test_regress/t/t_var_dotted2_inl1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_dotted_dup_bad.out b/test_regress/t/t_var_dotted_dup_bad.out index bcda5f416..8bdda3bde 100644 --- a/test_regress/t/t_var_dotted_dup_bad.out +++ b/test_regress/t/t_var_dotted_dup_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_var_dotted_dup_bad.v:13: Duplicate declaration of cell: 'dccm_bank' - eh2_ram dccm_bank (.*); - ^~~~~~~~~ - t/t_var_dotted_dup_bad.v:10: ... Location of original declaration - eh2_ram dccm_bank (.*); - ^~~~~~~~~ +%Error: t/t_var_dotted_dup_bad.v:14:18: Duplicate declaration of cell: 'dccm_bank' + 14 | eh2_ram dccm_bank (.*); + | ^~~~~~~~~ + t/t_var_dotted_dup_bad.v:11:18: ... Location of original declaration + 11 | eh2_ram dccm_bank (.*); + | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_dotted_dup_bad.pl b/test_regress/t/t_var_dotted_dup_bad.pl index e142ae153..6db424386 100755 --- a/test_regress/t/t_var_dotted_dup_bad.pl +++ b/test_regress/t/t_var_dotted_dup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2005 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2005 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_var_dotted_dup_bad.v b/test_regress/t/t_var_dotted_dup_bad.v index e22f6e514..a4e3eba44 100644 --- a/test_regress/t/t_var_dotted_dup_bad.v +++ b/test_regress/t/t_var_dotted_dup_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty 2020 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_var_dup2.pl b/test_regress/t/t_var_dup2.pl index f697727ea..857f82607 100755 --- a/test_regress/t/t_var_dup2.pl +++ b/test_regress/t/t_var_dup2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_dup2.v b/test_regress/t/t_var_dup2.v index 142dfb8fb..d2b18006f 100644 --- a/test_regress/t/t_var_dup2.v +++ b/test_regress/t/t_var_dup2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Legal with ANSI Verilog 2001 style ports module t diff --git a/test_regress/t/t_var_dup2_bad.out b/test_regress/t/t_var_dup2_bad.out index 2b8ad7717..347ba1095 100644 --- a/test_regress/t/t_var_dup2_bad.out +++ b/test_regress/t/t_var_dup2_bad.out @@ -1,14 +1,14 @@ -%Error: t/t_var_dup2_bad.v:12: Duplicate declaration of signal: 'bad_o_w' - : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2) - wire bad_o_w; - ^~~~~~~ - t/t_var_dup2_bad.v:9: ... Location of original declaration - output bad_o_w, - ^~~~~~~ -%Error: t/t_var_dup2_bad.v:13: Duplicate declaration of signal: 'bad_o_r' - reg bad_o_r; - ^~~~~~~ - t/t_var_dup2_bad.v:10: ... Location of original declaration - output bad_o_r); - ^~~~~~~ +%Error: t/t_var_dup2_bad.v:13:9: Duplicate declaration of signal: 'bad_o_w' + : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2) + 13 | wire bad_o_w; + | ^~~~~~~ + t/t_var_dup2_bad.v:10:11: ... Location of original declaration + 10 | output bad_o_w, + | ^~~~~~~ +%Error: t/t_var_dup2_bad.v:14:9: Duplicate declaration of signal: 'bad_o_r' + 14 | reg bad_o_r; + | ^~~~~~~ + t/t_var_dup2_bad.v:11:11: ... Location of original declaration + 11 | output bad_o_r); + | ^~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_dup2_bad.pl b/test_regress/t/t_var_dup2_bad.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_var_dup2_bad.pl +++ b/test_regress/t/t_var_dup2_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_dup2_bad.v b/test_regress/t/t_var_dup2_bad.v index 7ae8bc37a..21eb3cb4b 100644 --- a/test_regress/t/t_var_dup2_bad.v +++ b/test_regress/t/t_var_dup2_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Illegal with ANSI Verilog 2001 style ports module t diff --git a/test_regress/t/t_var_dup3.pl b/test_regress/t/t_var_dup3.pl index f697727ea..857f82607 100755 --- a/test_regress/t/t_var_dup3.pl +++ b/test_regress/t/t_var_dup3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_dup3.v b/test_regress/t/t_var_dup3.v index 38375af31..812c92746 100644 --- a/test_regress/t/t_var_dup3.v +++ b/test_regress/t/t_var_dup3.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Legal with Verilog 1995 style ports diff --git a/test_regress/t/t_var_dup_bad.out b/test_regress/t/t_var_dup_bad.out index 727573ca7..4f86e876a 100644 --- a/test_regress/t/t_var_dup_bad.out +++ b/test_regress/t/t_var_dup_bad.out @@ -1,110 +1,110 @@ -%Error: t/t_var_dup_bad.v:16: Duplicate declaration of signal: 'a' - reg a; - ^ - t/t_var_dup_bad.v:15: ... Location of original declaration - reg a; - ^ -%Error: t/t_var_dup_bad.v:19: Duplicate declaration of signal: 'l' - integer l; - ^ - t/t_var_dup_bad.v:18: ... Location of original declaration - integer l; - ^ -%Error: t/t_var_dup_bad.v:22: Duplicate declaration of signal: 'b' - bit b; - ^ - t/t_var_dup_bad.v:21: ... Location of original declaration - bit b; - ^ -%Error: t/t_var_dup_bad.v:25: Duplicate declaration of signal: 'o' - output o; - ^ - t/t_var_dup_bad.v:24: ... Location of original declaration - output o; - ^ -%Error: t/t_var_dup_bad.v:28: Duplicate declaration of signal: 'i' - input i; - ^ - t/t_var_dup_bad.v:27: ... Location of original declaration - input i; - ^ -%Error: t/t_var_dup_bad.v:31: Duplicate declaration of signal: 'oi' - input oi; - ^~ - t/t_var_dup_bad.v:30: ... Location of original declaration - output oi; - ^~ -%Error: t/t_var_dup_bad.v:38: Duplicate declaration of signal: 'org' - output reg org; - ^~~ - t/t_var_dup_bad.v:37: ... Location of original declaration - output reg org; - ^~~ -%Error: t/t_var_dup_bad.v:65: Duplicate declaration of signal: 'bad_reout_port' - output bad_reout_port; - ^~~~~~~~~~~~~~ - t/t_var_dup_bad.v:63: ... Location of original declaration - output bad_reout_port - ^~~~~~~~~~~~~~ -%Error: t/t_var_dup_bad.v:72: Duplicate declaration of signal: 'bad_rewire' - : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2) - wire bad_rewire; - ^~~~~~~~~~ - t/t_var_dup_bad.v:69: ... Location of original declaration - (output wire bad_rewire, - ^~~~~~~~~~ -%Error: t/t_var_dup_bad.v:73: Duplicate declaration of signal: 'bad_rereg' - reg bad_rereg; - ^~~~~~~~~ - t/t_var_dup_bad.v:70: ... Location of original declaration - output reg bad_rereg - ^~~~~~~~~ -%Error: t/t_var_dup_bad.v:12: Duplicate declaration of port: 'oi' - i, oi - ^~ - t/t_var_dup_bad.v:30: ... Location of original declaration - output oi; - ^~ -%Error: t/t_var_dup_bad.v:49: Duplicate declaration of port: 'bad_duport' - bad_duport - ^~~~~~~~~~ - t/t_var_dup_bad.v:51: ... Location of original declaration - output bad_duport; - ^~~~~~~~~~ -%Error: t/t_var_dup_bad.v:57: Duplicate declaration of port: 'bad_mixport' - output bad_mixport - ^~~~~~~~~~~ - t/t_var_dup_bad.v:57: ... Location of original declaration - output bad_mixport - ^~~~~~~~~~~ -%Error: t/t_var_dup_bad.v:40: Can't find definition of variable: 'bad_duport' - sub0 sub0(.*); - ^~~~ -%Error: t/t_var_dup_bad.v:40: Duplicate pin connection: 'bad_duport' - sub0 sub0(.*); - ^~~~ - t/t_var_dup_bad.v:40: ... Location of original pin connection - sub0 sub0(.*); - ^~~~ -%Error: t/t_var_dup_bad.v:41: Can't find definition of variable: 'bad_mixport' - : ... Suggested alternative: 'bad_duport' - sub1 sub1(.*); - ^~~~ -%Error: t/t_var_dup_bad.v:41: Duplicate pin connection: 'bad_mixport' - sub1 sub1(.*); - ^~~~ - t/t_var_dup_bad.v:41: ... Location of original pin connection - sub1 sub1(.*); - ^~~~ -%Error: t/t_var_dup_bad.v:42: Can't find definition of variable: 'bad_reout_port' - : ... Suggested alternative: 'bad_duport' - sub2 sub2(.*); - ^~~~ -%Error: t/t_var_dup_bad.v:43: Can't find definition of variable: 'bad_rewire' - sub3 sub3(.*); - ^~~~ -%Error: t/t_var_dup_bad.v:43: Can't find definition of variable: 'bad_rereg' - : ... Suggested alternative: 'bad_rewire' - sub3 sub3(.*); - ^~~~ +%Error: t/t_var_dup_bad.v:17:11: Duplicate declaration of signal: 'a' + 17 | reg a; + | ^ + t/t_var_dup_bad.v:16:11: ... Location of original declaration + 16 | reg a; + | ^ +%Error: t/t_var_dup_bad.v:20:12: Duplicate declaration of signal: 'l' + 20 | integer l; + | ^ + t/t_var_dup_bad.v:19:12: ... Location of original declaration + 19 | integer l; + | ^ +%Error: t/t_var_dup_bad.v:23:12: Duplicate declaration of signal: 'b' + 23 | bit b; + | ^ + t/t_var_dup_bad.v:22:12: ... Location of original declaration + 22 | bit b; + | ^ +%Error: t/t_var_dup_bad.v:26:11: Duplicate declaration of signal: 'o' + 26 | output o; + | ^ + t/t_var_dup_bad.v:25:11: ... Location of original declaration + 25 | output o; + | ^ +%Error: t/t_var_dup_bad.v:29:11: Duplicate declaration of signal: 'i' + 29 | input i; + | ^ + t/t_var_dup_bad.v:28:11: ... Location of original declaration + 28 | input i; + | ^ +%Error: t/t_var_dup_bad.v:32:11: Duplicate declaration of signal: 'oi' + 32 | input oi; + | ^~ + t/t_var_dup_bad.v:31:11: ... Location of original declaration + 31 | output oi; + | ^~ +%Error: t/t_var_dup_bad.v:39:15: Duplicate declaration of signal: 'org' + 39 | output reg org; + | ^~~ + t/t_var_dup_bad.v:38:15: ... Location of original declaration + 38 | output reg org; + | ^~~ +%Error: t/t_var_dup_bad.v:66:11: Duplicate declaration of signal: 'bad_reout_port' + 66 | output bad_reout_port; + | ^~~~~~~~~~~~~~ + t/t_var_dup_bad.v:64:11: ... Location of original declaration + 64 | output bad_reout_port + | ^~~~~~~~~~~~~~ +%Error: t/t_var_dup_bad.v:73:9: Duplicate declaration of signal: 'bad_rewire' + : ... note: ANSI ports must have type declared with the I/O (IEEE 1800-2017 23.2.2.2) + 73 | wire bad_rewire; + | ^~~~~~~~~~ + t/t_var_dup_bad.v:70:16: ... Location of original declaration + 70 | (output wire bad_rewire, + | ^~~~~~~~~~ +%Error: t/t_var_dup_bad.v:74:9: Duplicate declaration of signal: 'bad_rereg' + 74 | reg bad_rereg; + | ^~~~~~~~~ + t/t_var_dup_bad.v:71:15: ... Location of original declaration + 71 | output reg bad_rereg + | ^~~~~~~~~ +%Error: t/t_var_dup_bad.v:13:7: Duplicate declaration of port: 'oi' + 13 | i, oi + | ^~ + t/t_var_dup_bad.v:31:11: ... Location of original declaration + 31 | output oi; + | ^~ +%Error: t/t_var_dup_bad.v:50:4: Duplicate declaration of port: 'bad_duport' + 50 | bad_duport + | ^~~~~~~~~~ + t/t_var_dup_bad.v:52:11: ... Location of original declaration + 52 | output bad_duport; + | ^~~~~~~~~~ +%Error: t/t_var_dup_bad.v:58:11: Duplicate declaration of port: 'bad_mixport' + 58 | output bad_mixport + | ^~~~~~~~~~~ + t/t_var_dup_bad.v:58:11: ... Location of original declaration + 58 | output bad_mixport + | ^~~~~~~~~~~ +%Error: t/t_var_dup_bad.v:41:9: Can't find definition of variable: 'bad_duport' + 41 | sub0 sub0(.*); + | ^~~~ +%Error: t/t_var_dup_bad.v:41:9: Duplicate pin connection: 'bad_duport' + 41 | sub0 sub0(.*); + | ^~~~ + t/t_var_dup_bad.v:41:9: ... Location of original pin connection + 41 | sub0 sub0(.*); + | ^~~~ +%Error: t/t_var_dup_bad.v:42:9: Can't find definition of variable: 'bad_mixport' + : ... Suggested alternative: 'bad_duport' + 42 | sub1 sub1(.*); + | ^~~~ +%Error: t/t_var_dup_bad.v:42:9: Duplicate pin connection: 'bad_mixport' + 42 | sub1 sub1(.*); + | ^~~~ + t/t_var_dup_bad.v:42:9: ... Location of original pin connection + 42 | sub1 sub1(.*); + | ^~~~ +%Error: t/t_var_dup_bad.v:43:9: Can't find definition of variable: 'bad_reout_port' + : ... Suggested alternative: 'bad_duport' + 43 | sub2 sub2(.*); + | ^~~~ +%Error: t/t_var_dup_bad.v:44:9: Can't find definition of variable: 'bad_rewire' + 44 | sub3 sub3(.*); + | ^~~~ +%Error: t/t_var_dup_bad.v:44:9: Can't find definition of variable: 'bad_rereg' + : ... Suggested alternative: 'bad_rewire' + 44 | sub3 sub3(.*); + | ^~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_dup_bad.pl b/test_regress/t/t_var_dup_bad.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_var_dup_bad.pl +++ b/test_regress/t/t_var_dup_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_var_dup_bad.v b/test_regress/t/t_var_dup_bad.v index 06b7ad040..ae153fbed 100644 --- a/test_regress/t/t_var_dup_bad.v +++ b/test_regress/t/t_var_dup_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2007 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2007 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( diff --git a/test_regress/t/t_var_escape.pl b/test_regress/t/t_var_escape.pl index d734136aa..8636c72ab 100755 --- a/test_regress/t/t_var_escape.pl +++ b/test_regress/t/t_var_escape.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_escape.v b/test_regress/t/t_var_escape.v index 4d063ec85..4cd91d58d 100644 --- a/test_regress/t/t_var_escape.v +++ b/test_regress/t/t_var_escape.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_var_in_assign.pl b/test_regress/t/t_var_in_assign.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_in_assign.pl +++ b/test_regress/t/t_var_in_assign.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_in_assign.v b/test_regress/t/t_var_in_assign.v index ed7475a32..263775599 100644 --- a/test_regress/t/t_var_in_assign.v +++ b/test_regress/t/t_var_in_assign.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_in_assign_bad.out b/test_regress/t/t_var_in_assign_bad.out index cd6b4a463..87acaf9f1 100644 --- a/test_regress/t/t_var_in_assign_bad.out +++ b/test_regress/t/t_var_in_assign_bad.out @@ -1,7 +1,7 @@ -%Error-ASSIGNIN: t/t_var_in_assign_bad.v:11: Assigning to input/const variable: 'value' - assign value = 4'h0; - ^~~~~ -%Error-ASSIGNIN: t/t_var_in_assign_bad.v:20: Assigning to input/const variable: 'valueSub' - assign valueSub = 4'h0; - ^~~~~~~~ +%Error-ASSIGNIN: t/t_var_in_assign_bad.v:12:16: Assigning to input/const variable: 'value' + 12 | assign value = 4'h0; + | ^~~~~ +%Error-ASSIGNIN: t/t_var_in_assign_bad.v:21:16: Assigning to input/const variable: 'valueSub' + 21 | assign valueSub = 4'h0; + | ^~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_in_assign_bad.pl b/test_regress/t/t_var_in_assign_bad.pl index 69a6ddcf2..6fd21d17b 100755 --- a/test_regress/t/t_var_in_assign_bad.pl +++ b/test_regress/t/t_var_in_assign_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2005 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2005 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_var_in_assign_bad.v b/test_regress/t/t_var_in_assign_bad.v index a3f5ae53c..bf4614b10 100644 --- a/test_regress/t/t_var_in_assign_bad.v +++ b/test_regress/t/t_var_in_assign_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_init.pl b/test_regress/t/t_var_init.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_init.pl +++ b/test_regress/t/t_var_init.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_init.v b/test_regress/t/t_var_init.v index 577516707..87f4dfab0 100644 --- a/test_regress/t/t_var_init.v +++ b/test_regress/t/t_var_init.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_life.pl b/test_regress/t/t_var_life.pl index 751a3e4ce..7523d760b 100755 --- a/test_regress/t/t_var_life.pl +++ b/test_regress/t/t_var_life.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_life.v b/test_regress/t/t_var_life.v index 2a4520de1..f8a876eb0 100644 --- a/test_regress/t/t_var_life.v +++ b/test_regress/t/t_var_life.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_local.pl b/test_regress/t/t_var_local.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_local.pl +++ b/test_regress/t/t_var_local.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_local.v b/test_regress/t/t_var_local.v index 4128e7912..25a112a01 100644 --- a/test_regress/t/t_var_local.v +++ b/test_regress/t/t_var_local.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; diff --git a/test_regress/t/t_var_nonamebegin.pl b/test_regress/t/t_var_nonamebegin.pl index 4fc84b7fc..055e01a1a 100755 --- a/test_regress/t/t_var_nonamebegin.pl +++ b/test_regress/t/t_var_nonamebegin.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_nonamebegin.v b/test_regress/t/t_var_nonamebegin.v index 03a25363c..164e5a3b8 100644 --- a/test_regress/t/t_var_nonamebegin.v +++ b/test_regress/t/t_var_nonamebegin.v @@ -1,3 +1,8 @@ +// DESCRIPTION: Verilator: Verilog Test module +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + module t (/*AUTOARG*/ // Inputs clk, reset_l diff --git a/test_regress/t/t_var_notfound_bad.out b/test_regress/t/t_var_notfound_bad.out index 44bae4abf..826f9a68e 100644 --- a/test_regress/t/t_var_notfound_bad.out +++ b/test_regress/t/t_var_notfound_bad.out @@ -1,24 +1,24 @@ -%Error: t/t_var_notfound_bad.v:17: Can't find definition of variable: 'nf' - nf = 0; - ^~ -%Error: t/t_var_notfound_bad.v:18: Can't find definition of 'subsubz' in dotted scope/variable: 'sub.subsubz' - sub.subsubz.inss = 0; - ^~~~~~~ +%Error: t/t_var_notfound_bad.v:18:7: Can't find definition of variable: 'nf' + 18 | nf = 0; + | ^~ +%Error: t/t_var_notfound_bad.v:19:11: Can't find definition of 'subsubz' in dotted scope/variable: 'sub.subsubz' + 19 | sub.subsubz.inss = 0; + | ^~~~~~~ ... Known scopes under 'sub': subsub -%Error: t/t_var_notfound_bad.v:19: Can't find definition of task/function: 'nofunc' - : ... Suggested alternative: 'notfunc' - i = nofunc(); - ^~~~~~ -%Error: t/t_var_notfound_bad.v:20: Can't find definition of 'nofuncs' in dotted task/function: 'sub.nofuncs' - : ... Suggested alternative: 'notfuncs' - i = sub.nofuncs(); - ^~~~~~~ +%Error: t/t_var_notfound_bad.v:20:11: Can't find definition of task/function: 'nofunc' + : ... Suggested alternative: 'notfunc' + 20 | i = nofunc(); + | ^~~~~~ +%Error: t/t_var_notfound_bad.v:21:15: Can't find definition of 'nofuncs' in dotted task/function: 'sub.nofuncs' + : ... Suggested alternative: 'notfuncs' + 21 | i = sub.nofuncs(); + | ^~~~~~~ ... Known scopes under 'nofuncs': sub -%Error: t/t_var_notfound_bad.v:21: Can't find definition of task/function: 'notask' - : ... Suggested alternative: 'nottask' - notask(); - ^~~~~~ -%Error: t/t_var_notfound_bad.v:22: Found definition of 'a_var' as a VAR but expected a task/function - a_var(); - ^~~~~ +%Error: t/t_var_notfound_bad.v:22:7: Can't find definition of task/function: 'notask' + : ... Suggested alternative: 'nottask' + 22 | notask(); + | ^~~~~~ +%Error: t/t_var_notfound_bad.v:23:7: Found definition of 'a_var' as a VAR but expected a task/function + 23 | a_var(); + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_notfound_bad.pl b/test_regress/t/t_var_notfound_bad.pl index 3361369bf..dba098eb6 100755 --- a/test_regress/t/t_var_notfound_bad.pl +++ b/test_regress/t/t_var_notfound_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_notfound_bad.v b/test_regress/t/t_var_notfound_bad.v index 41f667774..34580ad38 100644 --- a/test_regress/t/t_var_notfound_bad.v +++ b/test_regress/t/t_var_notfound_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_var_outoforder.pl b/test_regress/t/t_var_outoforder.pl index b1acebe26..d89c3301f 100755 --- a/test_regress/t/t_var_outoforder.pl +++ b/test_regress/t/t_var_outoforder.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2004 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2004 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_outoforder.v b/test_regress/t/t_var_outoforder.v index 752a2d718..9c01c7358 100644 --- a/test_regress/t/t_var_outoforder.v +++ b/test_regress/t/t_var_outoforder.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2004 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2004 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_overcmp.pl b/test_regress/t/t_var_overcmp.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_overcmp.pl +++ b/test_regress/t/t_var_overcmp.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_overcmp.v b/test_regress/t/t_var_overcmp.v index b04f0baeb..c647e4df1 100644 --- a/test_regress/t/t_var_overcmp.v +++ b/test_regress/t/t_var_overcmp.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_var_overwidth_bad.cpp b/test_regress/t/t_var_overwidth_bad.cpp index ff7560b5c..30573b0b4 100644 --- a/test_regress/t/t_var_overwidth_bad.cpp +++ b/test_regress/t/t_var_overwidth_bad.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_var_overwidth_bad.out b/test_regress/t/t_var_overwidth_bad.out new file mode 100644 index 000000000..c4b17aece --- /dev/null +++ b/test_regress/t/t_var_overwidth_bad.out @@ -0,0 +1,2 @@ +%Error: unknown:0: Testbench C set input 'clk' to value that overflows what the signal's width can fit +Aborting... diff --git a/test_regress/t/t_var_overwidth_bad.pl b/test_regress/t/t_var_overwidth_bad.pl index ae65608f2..e51f3030a 100755 --- a/test_regress/t/t_var_overwidth_bad.pl +++ b/test_regress/t/t_var_overwidth_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); @@ -16,9 +17,7 @@ compile( execute( fails => 1, - expect => -qr{%Error: unknown:0: Testbench C set input 'clk' to value that overflows what the signal's width can fit -Aborting....*} + expect_filename => $Self->{golden_filename}, ); ok(1); diff --git a/test_regress/t/t_var_overwidth_bad.v b/test_regress/t/t_var_overwidth_bad.v index 52fe460f7..96d441841 100644 --- a/test_regress/t/t_var_overwidth_bad.v +++ b/test_regress/t/t_var_overwidth_bad.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_overzero.pl b/test_regress/t/t_var_overzero.pl index 8477d8386..baeeef11c 100755 --- a/test_regress/t/t_var_overzero.pl +++ b/test_regress/t/t_var_overzero.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_overzero.v b/test_regress/t/t_var_overzero.v index 559f5d009..f2e6ed040 100644 --- a/test_regress/t/t_var_overzero.v +++ b/test_regress/t/t_var_overzero.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_var_pins_cc.pl b/test_regress/t/t_var_pins_cc.pl index d5c23f443..3f712d899 100755 --- a/test_regress/t/t_var_pins_cc.pl +++ b/test_regress/t/t_var_pins_cc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_var_pins_sc1.pl b/test_regress/t/t_var_pins_sc1.pl index 3a41be17d..53dcc30a8 100755 --- a/test_regress/t/t_var_pins_sc1.pl +++ b/test_regress/t/t_var_pins_sc1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_var_pins_sc2.pl b/test_regress/t/t_var_pins_sc2.pl index 2d1d53916..7bdb70b64 100755 --- a/test_regress/t/t_var_pins_sc2.pl +++ b/test_regress/t/t_var_pins_sc2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_var_pins_sc32.pl b/test_regress/t/t_var_pins_sc32.pl index 800adf220..7a9318e1d 100755 --- a/test_regress/t/t_var_pins_sc32.pl +++ b/test_regress/t/t_var_pins_sc32.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_var_pins_sc64.pl b/test_regress/t/t_var_pins_sc64.pl index 0182586e2..9cc52b1ca 100755 --- a/test_regress/t/t_var_pins_sc64.pl +++ b/test_regress/t/t_var_pins_sc64.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_var_pins_sc_biguint.pl b/test_regress/t/t_var_pins_sc_biguint.pl index 342ab120a..2ad896891 100755 --- a/test_regress/t/t_var_pins_sc_biguint.pl +++ b/test_regress/t/t_var_pins_sc_biguint.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_var_pins_sc_uint.pl b/test_regress/t/t_var_pins_sc_uint.pl index e3d1f3fea..318a15105 100755 --- a/test_regress/t/t_var_pins_sc_uint.pl +++ b/test_regress/t/t_var_pins_sc_uint.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_var_pins_sc_uint_biguint.pl b/test_regress/t/t_var_pins_sc_uint_biguint.pl index ea9182433..ca2ee804c 100755 --- a/test_regress/t/t_var_pins_sc_uint_biguint.pl +++ b/test_regress/t/t_var_pins_sc_uint_biguint.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_var_pins_scui.pl b/test_regress/t/t_var_pins_scui.pl index f8ea4c9cb..ddc57d2d8 100755 --- a/test_regress/t/t_var_pins_scui.pl +++ b/test_regress/t/t_var_pins_scui.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_var_pinsizes.cpp b/test_regress/t/t_var_pinsizes.cpp index e6f88be13..3b74de365 100644 --- a/test_regress/t/t_var_pinsizes.cpp +++ b/test_regress/t/t_var_pinsizes.cpp @@ -1,4 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include VM_PREFIX_INCLUDE diff --git a/test_regress/t/t_var_pinsizes.v b/test_regress/t/t_var_pinsizes.v index e8e47533f..22ac179cc 100644 --- a/test_regress/t/t_var_pinsizes.v +++ b/test_regress/t/t_var_pinsizes.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2003 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2003 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Also check that SystemC is ordering properly // verilator lint_on IMPERFECTSCH diff --git a/test_regress/t/t_var_pinsizes.vlt b/test_regress/t/t_var_pinsizes.vlt index 7febde1d9..9387fc27d 100644 --- a/test_regress/t/t_var_pinsizes.vlt +++ b/test_regress/t/t_var_pinsizes.vlt @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2019 by Stefan Wallentowitz. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_var_port2_bad.out b/test_regress/t/t_var_port2_bad.out index 2ca15102a..1decff5e6 100644 --- a/test_regress/t/t_var_port2_bad.out +++ b/test_regress/t/t_var_port2_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_var_port2_bad.v:6: Input/output/inout declaration not found for port: 'portwithoin' -module t (portwithoin); - ^~~~~~~~~~~ -%Error: t/t_var_port2_bad.v:7: Input/output/inout does not appear in port list: 'portwithin' - input portwithin; - ^~~~~~~~~~ +%Error: t/t_var_port2_bad.v:7:11: Input/output/inout declaration not found for port: 'portwithoin' + 7 | module t (portwithoin); + | ^~~~~~~~~~~ +%Error: t/t_var_port2_bad.v:8:10: Input/output/inout does not appear in port list: 'portwithin' + 8 | input portwithin; + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_port2_bad.pl b/test_regress/t/t_var_port2_bad.pl index 5ee4228c2..9112f3486 100755 --- a/test_regress/t/t_var_port2_bad.pl +++ b/test_regress/t/t_var_port2_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_port2_bad.v b/test_regress/t/t_var_port2_bad.v index e059fdc21..504af82db 100644 --- a/test_regress/t/t_var_port2_bad.v +++ b/test_regress/t/t_var_port2_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (portwithoin); input portwithin; diff --git a/test_regress/t/t_var_port_bad.out b/test_regress/t/t_var_port_bad.out index a0fda600c..3965217c2 100644 --- a/test_regress/t/t_var_port_bad.out +++ b/test_regress/t/t_var_port_bad.out @@ -1,4 +1,4 @@ -%Error: t/t_var_port_bad.v:15: Input/output/inout does not appear in port list: 'b' - input a, b; - ^ +%Error: t/t_var_port_bad.v:16:13: Input/output/inout does not appear in port list: 'b' + 16 | input a, b; + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_var_port_bad.pl b/test_regress/t/t_var_port_bad.pl index 5ee4228c2..9112f3486 100755 --- a/test_regress/t/t_var_port_bad.pl +++ b/test_regress/t/t_var_port_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_port_bad.v b/test_regress/t/t_var_port_bad.v index 75d46915c..03f042560 100644 --- a/test_regress/t/t_var_port_bad.v +++ b/test_regress/t/t_var_port_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; subok subok (.a(1'b1), .b(1'b0)); diff --git a/test_regress/t/t_var_ref.pl b/test_regress/t/t_var_ref.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_ref.pl +++ b/test_regress/t/t_var_ref.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_ref.v b/test_regress/t/t_var_ref.v index 27c216e0e..494abbe9a 100644 --- a/test_regress/t/t_var_ref.v +++ b/test_regress/t/t_var_ref.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv));; end while(0); diff --git a/test_regress/t/t_var_ref_bad1.out b/test_regress/t/t_var_ref_bad1.out index 32bece252..fad8332f9 100644 --- a/test_regress/t/t_var_ref_bad1.out +++ b/test_regress/t/t_var_ref_bad1.out @@ -1,5 +1,5 @@ -%Error: t/t_var_ref_bad1.v:13: Ref connection 'bad_sub_ref' requires matching types; ref requires 'real' data type but connection is 'bit' data type. - : ... In instance t - (.bad_sub_ref(bad_parent)); - ^~~~~~~~~~~ +%Error: t/t_var_ref_bad1.v:14:8: Ref connection 'bad_sub_ref' requires matching types; ref requires 'real' data type but connection is 'bit' data type. + : ... In instance t + 14 | (.bad_sub_ref(bad_parent)); + | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_bad1.pl b/test_regress/t/t_var_ref_bad1.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_var_ref_bad1.pl +++ b/test_regress/t/t_var_ref_bad1.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_var_ref_bad1.v b/test_regress/t/t_var_ref_bad1.v index 0d2258a7f..1cc34567e 100644 --- a/test_regress/t/t_var_ref_bad1.v +++ b/test_regress/t/t_var_ref_bad1.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH diff --git a/test_regress/t/t_var_ref_bad2.out b/test_regress/t/t_var_ref_bad2.out index 0a9591591..28a384b6b 100644 --- a/test_regress/t/t_var_ref_bad2.out +++ b/test_regress/t/t_var_ref_bad2.out @@ -1,9 +1,9 @@ -%Error: t/t_var_ref_bad2.v:12: Assigning to const ref variable: 'bad_const_set' - : ... In instance t - bad_const_set = 32'h4567; - ^~~~~~~~~~~~~ -%Error: t/t_var_ref_bad2.v:22: Ref argument requires matching types; port 'int_ref' requires VAR 'int_ref' but connection is VARREF 'bad_non_int'. - : ... In instance t - checkset2(bad_non_int); - ^~~~~~~~~~~ +%Error: t/t_var_ref_bad2.v:13:7: Assigning to const ref variable: 'bad_const_set' + : ... In instance t + 13 | bad_const_set = 32'h4567; + | ^~~~~~~~~~~~~ +%Error: t/t_var_ref_bad2.v:23:17: Ref argument requires matching types; port 'int_ref' requires VAR 'int_ref' but connection is VARREF 'bad_non_int'. + : ... In instance t + 23 | checkset2(bad_non_int); + | ^~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_bad2.pl b/test_regress/t/t_var_ref_bad2.pl index b09f43e8b..67a7abcb0 100755 --- a/test_regress/t/t_var_ref_bad2.pl +++ b/test_regress/t/t_var_ref_bad2.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_ref_bad2.v b/test_regress/t/t_var_ref_bad2.v index e4d3dc17c..c6ce5e267 100644 --- a/test_regress/t/t_var_ref_bad2.v +++ b/test_regress/t/t_var_ref_bad2.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH diff --git a/test_regress/t/t_var_ref_bad3.out b/test_regress/t/t_var_ref_bad3.out index 78118fc6d..967d473af 100644 --- a/test_regress/t/t_var_ref_bad3.out +++ b/test_regress/t/t_var_ref_bad3.out @@ -1,4 +1,4 @@ -%Error: t/t_var_ref_bad3.v:9: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' -module t(ref int bad_primary_ref - ^~~~~~~~~~~~~~~ +%Error: t/t_var_ref_bad3.v:10:18: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' + 10 | module t(ref int bad_primary_ref + | ^~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_ref_bad3.pl b/test_regress/t/t_var_ref_bad3.pl index 385b304e3..ac387c7d9 100755 --- a/test_regress/t/t_var_ref_bad3.pl +++ b/test_regress/t/t_var_ref_bad3.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_var_ref_bad3.v b/test_regress/t/t_var_ref_bad3.v index 5fbf8b325..36db55697 100644 --- a/test_regress/t/t_var_ref_bad3.v +++ b/test_regress/t/t_var_ref_bad3.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Make sure type errors aren't suppressable // verilator lint_off WIDTH diff --git a/test_regress/t/t_var_ref_noinline.pl b/test_regress/t/t_var_ref_noinline.pl index 6e9eff2fa..06315e8c9 100755 --- a/test_regress/t/t_var_ref_noinline.pl +++ b/test_regress/t/t_var_ref_noinline.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 top_filename("t/t_var_ref.v"); diff --git a/test_regress/t/t_var_rsvd.pl b/test_regress/t/t_var_rsvd.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_rsvd.pl +++ b/test_regress/t/t_var_rsvd.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_rsvd.v b/test_regress/t/t_var_rsvd.v index e4ea140e1..e006ff85c 100644 --- a/test_regress/t/t_var_rsvd.v +++ b/test_regress/t/t_var_rsvd.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // verilator lint_off SYMRSVDWORD diff --git a/test_regress/t/t_var_rsvd_bad.out b/test_regress/t/t_var_rsvd_bad.out index 833353c9d..5a4cd49ab 100644 --- a/test_regress/t/t_var_rsvd_bad.out +++ b/test_regress/t/t_var_rsvd_bad.out @@ -1,9 +1,9 @@ -%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:11: Symbol matches C++ keyword: 'bool' - input bool; - ^~~~ +%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:12:10: Symbol matches C++ keyword: 'bool' + 12 | input bool; + | ^~~~ ... Use "/* verilator lint_off SYMRSVDWORD */" and lint_on around source to disable this message. -%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:14: Symbol matches C++ keyword: 'switch' - : ... In instance t - reg switch /*verilator public*/ ; - ^~~~~~ +%Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:15:9: Symbol matches C++ keyword: 'switch' + : ... In instance t + 15 | reg switch /*verilator public*/ ; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_rsvd_bad.pl b/test_regress/t/t_var_rsvd_bad.pl index 478bb3ef1..0e4c147b8 100755 --- a/test_regress/t/t_var_rsvd_bad.pl +++ b/test_regress/t/t_var_rsvd_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_rsvd_port.pl b/test_regress/t/t_var_rsvd_port.pl index 816372e7e..ff17d510c 100755 --- a/test_regress/t/t_var_rsvd_port.pl +++ b/test_regress/t/t_var_rsvd_port.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_rsvd_port.v b/test_regress/t/t_var_rsvd_port.v index 615bba58a..5d00596fe 100644 --- a/test_regress/t/t_var_rsvd_port.v +++ b/test_regress/t/t_var_rsvd_port.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2005 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2005 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_set_link.pl b/test_regress/t/t_var_set_link.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_set_link.pl +++ b/test_regress/t/t_var_set_link.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_set_link.v b/test_regress/t/t_var_set_link.v index c12cf7941..d01f989df 100644 --- a/test_regress/t/t_var_set_link.v +++ b/test_regress/t/t_var_set_link.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2008 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_var_static.pl b/test_regress/t/t_var_static.pl index 9eaffcdbf..0194e8e7d 100755 --- a/test_regress/t/t_var_static.pl +++ b/test_regress/t/t_var_static.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); $Self->{vlt_all} and unsupported("Verilator unsupported, bug546"); diff --git a/test_regress/t/t_var_static.v b/test_regress/t/t_var_static.v index ad8f2a825..48a94b7dc 100644 --- a/test_regress/t/t_var_static.v +++ b/test_regress/t/t_var_static.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2014 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2014 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_var_suggest_bad.out b/test_regress/t/t_var_suggest_bad.out index e861eadd6..19ce808cd 100644 --- a/test_regress/t/t_var_suggest_bad.out +++ b/test_regress/t/t_var_suggest_bad.out @@ -1,9 +1,9 @@ -%Error: t/t_var_suggest_bad.v:12: Can't find definition of variable: 'foobat' - : ... Suggested alternative: 'foobar' - if (foobat) $stop; - ^~~~~~ -%Error: t/t_var_suggest_bad.v:13: Can't find definition of task/function: 'boobat' - : ... Suggested alternative: 'boobar' - boobat; - ^~~~~~ +%Error: t/t_var_suggest_bad.v:13:11: Can't find definition of variable: 'foobat' + : ... Suggested alternative: 'foobar' + 13 | if (foobat) $stop; + | ^~~~~~ +%Error: t/t_var_suggest_bad.v:14:7: Can't find definition of task/function: 'boobat' + : ... Suggested alternative: 'boobar' + 14 | boobat; + | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_suggest_bad.pl b/test_regress/t/t_var_suggest_bad.pl index 57ecc0da2..056b9974f 100755 --- a/test_regress/t/t_var_suggest_bad.pl +++ b/test_regress/t/t_var_suggest_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_suggest_bad.v b/test_regress/t/t_var_suggest_bad.v index 90685dd1c..8d321505a 100644 --- a/test_regress/t/t_var_suggest_bad.v +++ b/test_regress/t/t_var_suggest_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t; reg foobar; diff --git a/test_regress/t/t_var_tieout.pl b/test_regress/t/t_var_tieout.pl index 89a4e77d9..1d046ed3f 100755 --- a/test_regress/t/t_var_tieout.pl +++ b/test_regress/t/t_var_tieout.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_tieout.v b/test_regress/t/t_var_tieout.v index efdf8f2e2..17ecee2e4 100644 --- a/test_regress/t/t_var_tieout.v +++ b/test_regress/t/t_var_tieout.v @@ -1,6 +1,7 @@ // DESCRIPTION: Verilator: Verilog Test module -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug291 module t (/*AUTOARG*/ diff --git a/test_regress/t/t_var_types.pl b/test_regress/t/t_var_types.pl index 2ac96a92f..3a8a4d160 100755 --- a/test_regress/t/t_var_types.pl +++ b/test_regress/t/t_var_types.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_types.v b/test_regress/t/t_var_types.v index 9d3bd8155..75a06d55e 100644 --- a/test_regress/t/t_var_types.v +++ b/test_regress/t/t_var_types.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_var_types_bad.out b/test_regress/t/t_var_types_bad.out index 9dbd0471d..e4c100627 100644 --- a/test_regress/t/t_var_types_bad.out +++ b/test_regress/t/t_var_types_bad.out @@ -1,36 +1,36 @@ -%Error: t/t_var_types_bad.v:38: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'bit' - : ... In instance t - d_bitz[0] = 1'b1; - ^ -%Error: t/t_var_types_bad.v:39: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... In instance t - d_logicz[0] = 1'b1; - ^ -%Error: t/t_var_types_bad.v:40: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' - : ... In instance t - d_regz[0] = 1'b1; - ^ -%Error: t/t_var_types_bad.v:45: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' - : ... In instance t - d_real[0] = 1'b1; - ^ -%Error: t/t_var_types_bad.v:45: Expected integral (non-real) input to SEL - : ... In instance t - d_real[0] = 1'b1; - ^~~~~~ -%Warning-REALCVT: t/t_var_types_bad.v:45: Implicit conversion of real to integer - d_real[0] = 1'b1; - ^~~~~~ +%Error: t/t_var_types_bad.v:39:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'bit' + : ... In instance t + 39 | d_bitz[0] = 1'b1; + | ^ +%Error: t/t_var_types_bad.v:40:15: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... In instance t + 40 | d_logicz[0] = 1'b1; + | ^ +%Error: t/t_var_types_bad.v:41:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' + : ... In instance t + 41 | d_regz[0] = 1'b1; + | ^ +%Error: t/t_var_types_bad.v:46:13: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' + : ... In instance t + 46 | d_real[0] = 1'b1; + | ^ +%Error: t/t_var_types_bad.v:46:7: Expected integral (non-real) input to SEL + : ... In instance t + 46 | d_real[0] = 1'b1; + | ^~~~~~ +%Warning-REALCVT: t/t_var_types_bad.v:46:7: Implicit conversion of real to integer + 46 | d_real[0] = 1'b1; + | ^~~~~~ ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. -%Error: t/t_var_types_bad.v:46: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' - : ... In instance t - d_realtime[0] = 1'b1; - ^ -%Error: t/t_var_types_bad.v:46: Expected integral (non-real) input to SEL - : ... In instance t - d_realtime[0] = 1'b1; - ^~~~~~~~~~ -%Warning-REALCVT: t/t_var_types_bad.v:46: Implicit conversion of real to integer - d_realtime[0] = 1'b1; - ^~~~~~~~~~ +%Error: t/t_var_types_bad.v:47:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' + : ... In instance t + 47 | d_realtime[0] = 1'b1; + | ^ +%Error: t/t_var_types_bad.v:47:7: Expected integral (non-real) input to SEL + : ... In instance t + 47 | d_realtime[0] = 1'b1; + | ^~~~~~~~~~ +%Warning-REALCVT: t/t_var_types_bad.v:47:7: Implicit conversion of real to integer + 47 | d_realtime[0] = 1'b1; + | ^~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_var_types_bad.pl b/test_regress/t/t_var_types_bad.pl index 63de4f6d5..ef023b9fc 100755 --- a/test_regress/t/t_var_types_bad.pl +++ b/test_regress/t/t_var_types_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_types_bad.v b/test_regress/t/t_var_types_bad.v index e67cd7655..7d6341d33 100644 --- a/test_regress/t/t_var_types_bad.v +++ b/test_regress/t/t_var_types_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2009 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/); diff --git a/test_regress/t/t_var_vec_sel.pl b/test_regress/t/t_var_vec_sel.pl index 0bafa73ba..a4d74c0ba 100755 --- a/test_regress/t/t_var_vec_sel.pl +++ b/test_regress/t/t_var_vec_sel.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(linter => 1); diff --git a/test_regress/t/t_var_vec_sel.v b/test_regress/t/t_var_vec_sel.v index 22e135499..e55cf45a8 100644 --- a/test_regress/t/t_var_vec_sel.v +++ b/test_regress/t/t_var_vec_sel.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // bug601 diff --git a/test_regress/t/t_var_xref_gen.pl b/test_regress/t/t_var_xref_gen.pl index 1f7906aae..f126bab59 100755 --- a/test_regress/t/t_var_xref_gen.pl +++ b/test_regress/t/t_var_xref_gen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_var_xref_gen.v b/test_regress/t/t_var_xref_gen.v index ac15a246f..cb01b3375 100644 --- a/test_regress/t/t_var_xref_gen.v +++ b/test_regress/t/t_var_xref_gen.v @@ -5,6 +5,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2015 by Jie Xu and Roland Kruse. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_verilated_all.pl b/test_regress/t/t_verilated_all.pl index 0c19346e0..d3b70bac5 100755 --- a/test_regress/t/t_verilated_all.pl +++ b/test_regress/t/t_verilated_all.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_verilated_all.v b/test_regress/t/t_verilated_all.v index 8746bff67..8edabe38a 100644 --- a/test_regress/t/t_verilated_all.v +++ b/test_regress/t/t_verilated_all.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_verilated_all_newest.pl b/test_regress/t/t_verilated_all_newest.pl index 40885f90e..702f6cf07 100755 --- a/test_regress/t/t_verilated_all_newest.pl +++ b/test_regress/t/t_verilated_all_newest.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_verilated_all_oldest.pl b/test_regress/t/t_verilated_all_oldest.pl index 131f80c6f..11fa3349c 100755 --- a/test_regress/t/t_verilated_all_oldest.pl +++ b/test_regress/t/t_verilated_all_oldest.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_verilated_debug.pl b/test_regress/t/t_verilated_debug.pl index 49a7987a6..08d810c99 100755 --- a/test_regress/t/t_verilated_debug.pl +++ b/test_regress/t/t_verilated_debug.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_verilated_debug.v b/test_regress/t/t_verilated_debug.v index d90fb7797..e541f39d9 100644 --- a/test_regress/t/t_verilated_debug.v +++ b/test_regress/t/t_verilated_debug.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2017 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2017 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_verilated_threaded.pl b/test_regress/t/t_verilated_threaded.pl index ddb4c822c..5f8920700 100755 --- a/test_regress/t/t_verilated_threaded.pl +++ b/test_regress/t/t_verilated_threaded.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vltmt => 1); diff --git a/test_regress/t/t_vgen.pl b/test_regress/t/t_vgen.pl index 16b665aa1..8c25ac412 100755 --- a/test_regress/t/t_vgen.pl +++ b/test_regress/t/t_vgen.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vlcov_debugi.pl b/test_regress/t/t_vlcov_debugi.pl index a310de3ab..5517958e8 100755 --- a/test_regress/t/t_vlcov_debugi.pl +++ b/test_regress/t/t_vlcov_debugi.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_vlcov_merge.pl b/test_regress/t/t_vlcov_merge.pl index d7a011d6b..3437bfdb1 100755 --- a/test_regress/t/t_vlcov_merge.pl +++ b/test_regress/t/t_vlcov_merge.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_vlcov_nfound_bad.pl b/test_regress/t/t_vlcov_nfound_bad.pl index 9b7a627db..35e66208a 100755 --- a/test_regress/t/t_vlcov_nfound_bad.pl +++ b/test_regress/t/t_vlcov_nfound_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_vlcov_rank.pl b/test_regress/t/t_vlcov_rank.pl index 8b367e852..2d8d806f7 100755 --- a/test_regress/t/t_vlcov_rank.pl +++ b/test_regress/t/t_vlcov_rank.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_vlcov_rewrite.pl b/test_regress/t/t_vlcov_rewrite.pl index 26c0387e2..81634291e 100755 --- a/test_regress/t/t_vlcov_rewrite.pl +++ b/test_regress/t/t_vlcov_rewrite.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(dist => 1); diff --git a/test_regress/t/t_vlt_syntax_bad.out b/test_regress/t/t_vlt_syntax_bad.out index a33d90118..7db02e54b 100644 --- a/test_regress/t/t_vlt_syntax_bad.out +++ b/test_regress/t/t_vlt_syntax_bad.out @@ -1,7 +1,7 @@ -%Error: t/t_vlt_syntax_bad.vlt:8: sensitivity not expected for attribute -public -module "t" @(posedge clk) - ^ -%Error: t/t_vlt_syntax_bad.vlt:9: isolate_assignments only applies to signals or functions/tasks -isolate_assignments -module "t" -^~~~~~~~~~~~~~~~~~~ +%Error: t/t_vlt_syntax_bad.vlt:9:20: sensitivity not expected for attribute + 9 | public -module "t" @(posedge clk) + | ^ +%Error: t/t_vlt_syntax_bad.vlt:10:1: isolate_assignments only applies to signals or functions/tasks + 10 | isolate_assignments -module "t" + | ^~~~~~~~~~~~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_vlt_syntax_bad.pl b/test_regress/t/t_vlt_syntax_bad.pl index b53b7da4d..80bf52112 100755 --- a/test_regress/t/t_vlt_syntax_bad.pl +++ b/test_regress/t/t_vlt_syntax_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); diff --git a/test_regress/t/t_vlt_syntax_bad.vlt b/test_regress/t/t_vlt_syntax_bad.vlt index 51140ca01..df7bda927 100644 --- a/test_regress/t/t_vlt_syntax_bad.vlt +++ b/test_regress/t/t_vlt_syntax_bad.vlt @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vlt_warn.pl b/test_regress/t/t_vlt_warn.pl index 078632d69..d1ec9e8ed 100755 --- a/test_regress/t/t_vlt_warn.pl +++ b/test_regress/t/t_vlt_warn.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_vlt_warn.v b/test_regress/t/t_vlt_warn.v index 1c2a936d4..4de6b49f4 100644 --- a/test_regress/t/t_vlt_warn.v +++ b/test_regress/t/t_vlt_warn.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 // Try inline config `ifdef verilator diff --git a/test_regress/t/t_vlt_warn.vlt b/test_regress/t/t_vlt_warn.vlt index 3aaac32bb..e4f858780 100644 --- a/test_regress/t/t_vlt_warn.vlt +++ b/test_regress/t/t_vlt_warn.vlt @@ -1,18 +1,19 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `verilator_config -lint_off -rule DEPRECATED -file "t/t_vlt_warn.vlt" -lines 13 +lint_off -rule DEPRECATED -file "t/t_vlt_warn.vlt" -lines 14 lint_off -rule CASEINCOMPLETE -file "t/t_vlt_warn.v" -lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 18 +lint_off -rule WIDTH -file "t/t_vlt_warn.v" -lines 19 lint_off -rule DECLFILENAME -file "*/t_vlt_warn.v" // Test wildcard filenames -lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 19-19 +lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 20-20 // Test global disables -lint_off -file "*/t_vlt_warn.v" -lines 20-20 +lint_off -file "*/t_vlt_warn.v" -lines 21-21 // Test match lint_off -rule UNUSED -file "*/t_vlt_warn.v" -match "Signal is not used: 'width_warn*'" diff --git a/test_regress/t/t_vlt_warn_bad.out b/test_regress/t/t_vlt_warn_bad.out index 0a847a31a..4e5fcde5a 100644 --- a/test_regress/t/t_vlt_warn_bad.out +++ b/test_regress/t/t_vlt_warn_bad.out @@ -1,5 +1,9 @@ -%Warning-DEPRECATED: t/t_vlt_warn_bad.vlt:11: Deprecated -msg in configuration files, use -rule instead. -lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 19-19 - ^~~~ +%Warning-DEPRECATED: t/t_vlt_warn_bad.vlt:12:10: Deprecated -msg in configuration files, use -rule instead. + 12 | lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 19-19 + | ^~~~ ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. +%Warning-WIDTH: t/t_vlt_warn.v:21:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits. + : ... In instance t + 21 | reg width_warn3_var_line20 = 2'b11; + | ^~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_vlt_warn_bad.pl b/test_regress/t/t_vlt_warn_bad.pl index 5dd7bae92..2fea6cef3 100755 --- a/test_regress/t/t_vlt_warn_bad.pl +++ b/test_regress/t/t_vlt_warn_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2008 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_vlt_warn_bad.vlt b/test_regress/t/t_vlt_warn_bad.vlt index b16f429b1..3b07dacac 100644 --- a/test_regress/t/t_vlt_warn_bad.vlt +++ b/test_regress/t/t_vlt_warn_bad.vlt @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2010 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2010 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 `verilator_config diff --git a/test_regress/t/t_vpi_get.cpp b/test_regress/t/t_vpi_get.cpp index 0bed48be3..3f66a7f10 100644 --- a/test_regress/t/t_vpi_get.cpp +++ b/test_regress/t/t_vpi_get.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_get.pl b/test_regress/t/t_vpi_get.pl index 6e0ee3bae..93f8dbb0c 100755 --- a/test_regress/t/t_vpi_get.pl +++ b/test_regress/t/t_vpi_get.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vpi_get.v b/test_regress/t/t_vpi_get.v index ca4709391..d6b120790 100644 --- a/test_regress/t/t_vpi_get.v +++ b/test_regress/t/t_vpi_get.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 diff --git a/test_regress/t/t_vpi_get_public_rw_switch.pl b/test_regress/t/t_vpi_get_public_rw_switch.pl index ad0c83f9a..8228d7585 100755 --- a/test_regress/t/t_vpi_get_public_rw_switch.pl +++ b/test_regress/t/t_vpi_get_public_rw_switch.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vpi_memory.cpp b/test_regress/t/t_vpi_memory.cpp index ef7829a1c..74ace580f 100644 --- a/test_regress/t/t_vpi_memory.cpp +++ b/test_regress/t/t_vpi_memory.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_memory.pl b/test_regress/t/t_vpi_memory.pl index 4e1d4d3e6..1a6da9c4a 100755 --- a/test_regress/t/t_vpi_memory.pl +++ b/test_regress/t/t_vpi_memory.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vpi_memory.v b/test_regress/t/t_vpi_memory.v index ea1681071..f140f12e0 100644 --- a/test_regress/t/t_vpi_memory.v +++ b/test_regress/t/t_vpi_memory.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 diff --git a/test_regress/t/t_vpi_module.cpp b/test_regress/t/t_vpi_module.cpp index 8b7322dcb..d0559b26e 100644 --- a/test_regress/t/t_vpi_module.cpp +++ b/test_regress/t/t_vpi_module.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_module.pl b/test_regress/t/t_vpi_module.pl index 9318d6cec..2e99e1a83 100755 --- a/test_regress/t/t_vpi_module.pl +++ b/test_regress/t/t_vpi_module.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vpi_module.v b/test_regress/t/t_vpi_module.v index 35be2a9a7..f411143fd 100644 --- a/test_regress/t/t_vpi_module.v +++ b/test_regress/t/t_vpi_module.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 diff --git a/test_regress/t/t_vpi_sc.cpp b/test_regress/t/t_vpi_sc.cpp index e4fca6c38..e6be1c64b 100644 --- a/test_regress/t/t_vpi_sc.cpp +++ b/test_regress/t/t_vpi_sc.cpp @@ -1,4 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 #include "Vt_vpi_sc.h" diff --git a/test_regress/t/t_vpi_sc.pl b/test_regress/t/t_vpi_sc.pl index bc9248d9f..730065a65 100755 --- a/test_regress/t/t_vpi_sc.pl +++ b/test_regress/t/t_vpi_sc.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vpi_sc.v b/test_regress/t/t_vpi_sc.v index 99e6af81f..fdd3bc959 100644 --- a/test_regress/t/t_vpi_sc.v +++ b/test_regress/t/t_vpi_sc.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t; diff --git a/test_regress/t/t_vpi_time_cb.cpp b/test_regress/t/t_vpi_time_cb.cpp index 00a4d8443..12a5e774b 100644 --- a/test_regress/t/t_vpi_time_cb.cpp +++ b/test_regress/t/t_vpi_time_cb.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* @@ -239,6 +235,7 @@ int main(int argc, char** argv, char** env) { topp->eval(); VerilatedVpi::callValueCbs(); VerilatedVpi::callTimedCbs(); + CHECK_RESULT(VerilatedVpi::cbNextDeadline(), main_time+1); topp->clk = !topp->clk; // mon_do(); #if VM_TRACE diff --git a/test_regress/t/t_vpi_time_cb.pl b/test_regress/t/t_vpi_time_cb.pl index 4c2bcfcf1..94c01d0cb 100755 --- a/test_regress/t/t_vpi_time_cb.pl +++ b/test_regress/t/t_vpi_time_cb.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1, iv => 1); diff --git a/test_regress/t/t_vpi_time_cb.v b/test_regress/t/t_vpi_time_cb.v index 56502dce3..96f5ba107 100644 --- a/test_regress/t/t_vpi_time_cb.v +++ b/test_regress/t/t_vpi_time_cb.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_vpi_unimpl.cpp b/test_regress/t/t_vpi_unimpl.cpp index b8f82cdb4..dd9eb9fad 100644 --- a/test_regress/t/t_vpi_unimpl.cpp +++ b/test_regress/t/t_vpi_unimpl.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_unimpl.pl b/test_regress/t/t_vpi_unimpl.pl index 0b01888b4..5160957d8 100755 --- a/test_regress/t/t_vpi_unimpl.pl +++ b/test_regress/t/t_vpi_unimpl.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vpi_unimpl.v b/test_regress/t/t_vpi_unimpl.v index f56270883..978303008 100644 --- a/test_regress/t/t_vpi_unimpl.v +++ b/test_regress/t/t_vpi_unimpl.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef VERILATOR //We call it via $c so we can verify DPI isn't required - see bug572 diff --git a/test_regress/t/t_vpi_var.cpp b/test_regress/t/t_vpi_var.cpp index 26d5deb89..739cfd235 100644 --- a/test_regress/t/t_vpi_var.cpp +++ b/test_regress/t/t_vpi_var.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_var.pl b/test_regress/t/t_vpi_var.pl index 48387ade3..c21977991 100755 --- a/test_regress/t/t_vpi_var.pl +++ b/test_regress/t/t_vpi_var.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_vpi_var.v b/test_regress/t/t_vpi_var.v index dfa61ec48..74119a4dc 100644 --- a/test_regress/t/t_vpi_var.v +++ b/test_regress/t/t_vpi_var.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 `ifdef USE_VPI_NOT_DPI //We call it via $c so we can verify DPI isn't required - see bug572 diff --git a/test_regress/t/t_vpi_zero_time_cb.cpp b/test_regress/t/t_vpi_zero_time_cb.cpp index 10164ec87..94f7bf46c 100644 --- a/test_regress/t/t_vpi_zero_time_cb.cpp +++ b/test_regress/t/t_vpi_zero_time_cb.cpp @@ -3,13 +3,9 @@ // // Copyright 2010-2011 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License. +// Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. -// -// Verilator is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 // //************************************************************************* diff --git a/test_regress/t/t_vpi_zero_time_cb.pl b/test_regress/t/t_vpi_zero_time_cb.pl index 51b2ff9f6..58239f1a7 100755 --- a/test_regress/t/t_vpi_zero_time_cb.pl +++ b/test_regress/t/t_vpi_zero_time_cb.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2010 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2010 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1, iv => 1); diff --git a/test_regress/t/t_vpi_zero_time_cb.v b/test_regress/t/t_vpi_zero_time_cb.v index d07b88af7..052b9f4ba 100644 --- a/test_regress/t/t_vpi_zero_time_cb.v +++ b/test_regress/t/t_vpi_zero_time_cb.v @@ -4,6 +4,7 @@ // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License // Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_wire_beh1364_bad.out b/test_regress/t/t_wire_beh1364_bad.out index 9f8606a6a..18834bf3a 100644 --- a/test_regress/t/t_wire_beh1364_bad.out +++ b/test_regress/t/t_wire_beh1364_bad.out @@ -1,21 +1,21 @@ -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' - : ... In instance t - w = '0; - ^ -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' - : ... In instance t - o = '0; - ^ -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' - : ... In instance t - oa = '0; - ^~ -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo' - : ... In instance t - wo = '0; - ^~ -%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa' - : ... In instance t - woa = '0; - ^~~ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' + : ... In instance t + 25 | w = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' + : ... In instance t + 26 | o = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' + : ... In instance t + 27 | oa = '0; + | ^~ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo' + : ... In instance t + 28 | wo = '0; + | ^~ +%Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa' + : ... In instance t + 29 | woa = '0; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_beh1364_bad.pl b/test_regress/t/t_wire_beh1364_bad.pl index fa3fa6b10..0c056a285 100755 --- a/test_regress/t/t_wire_beh1364_bad.pl +++ b/test_regress/t/t_wire_beh1364_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_wire_beh1364_bad.v b/test_regress/t/t_wire_beh1364_bad.v index c88bbe3bc..e8ca5744c 100644 --- a/test_regress/t/t_wire_beh1364_bad.v +++ b/test_regress/t/t_wire_beh1364_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_wire_beh1800_bad.out b/test_regress/t/t_wire_beh1800_bad.out index 0d07bcd89..4300d3caf 100644 --- a/test_regress/t/t_wire_beh1800_bad.out +++ b/test_regress/t/t_wire_beh1800_bad.out @@ -1,21 +1,21 @@ -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' - : ... In instance t - w = '0; - ^ -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' - : ... In instance t - o = '0; - ^ -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' - : ... In instance t - oa = '0; - ^~ -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo' - : ... In instance t - wo = '0; - ^~ -%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa' - : ... In instance t - woa = '0; - ^~~ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' + : ... In instance t + 25 | w = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' + : ... In instance t + 26 | o = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:27:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' + : ... In instance t + 27 | oa = '0; + | ^~ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:28:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'wo' + : ... In instance t + 28 | wo = '0; + | ^~ +%Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:29:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'woa' + : ... In instance t + 29 | woa = '0; + | ^~~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_beh1800_bad.pl b/test_regress/t/t_wire_beh1800_bad.pl index 8c9b1887a..8bf670e39 100755 --- a/test_regress/t/t_wire_beh1800_bad.pl +++ b/test_regress/t/t_wire_beh1800_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_wire_beh1800_bad.v b/test_regress/t/t_wire_beh1800_bad.v index baddf265e..9f080c9eb 100644 --- a/test_regress/t/t_wire_beh1800_bad.v +++ b/test_regress/t/t_wire_beh1800_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_wire_behp1364_bad.out b/test_regress/t/t_wire_behp1364_bad.out index 824dd2350..73e9d1c53 100644 --- a/test_regress/t/t_wire_behp1364_bad.out +++ b/test_regress/t/t_wire_behp1364_bad.out @@ -1,13 +1,13 @@ -%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' - : ... In instance t - w = '0; - ^ -%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' - : ... In instance t - o = '0; - ^ -%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' - : ... In instance t - oa = '0; - ^~ +%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:23:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' + : ... In instance t + 23 | w = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' + : ... In instance t + 24 | o = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' + : ... In instance t + 25 | oa = '0; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_behp1364_bad.pl b/test_regress/t/t_wire_behp1364_bad.pl index fa3fa6b10..0c056a285 100755 --- a/test_regress/t/t_wire_behp1364_bad.pl +++ b/test_regress/t/t_wire_behp1364_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_wire_behp1364_bad.v b/test_regress/t/t_wire_behp1364_bad.v index a80d4d6e2..42a67c340 100644 --- a/test_regress/t/t_wire_behp1364_bad.v +++ b/test_regress/t/t_wire_behp1364_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( output o, diff --git a/test_regress/t/t_wire_behp1800_bad.out b/test_regress/t/t_wire_behp1800_bad.out index 70434db94..ec76bc00c 100644 --- a/test_regress/t/t_wire_behp1800_bad.out +++ b/test_regress/t/t_wire_behp1800_bad.out @@ -1,13 +1,13 @@ -%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:22: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' - : ... In instance t - w = '0; - ^ -%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' - : ... In instance t - o = '0; - ^ -%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' - : ... In instance t - oa = '0; - ^~ +%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:23:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'w' + : ... In instance t + 23 | w = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' + : ... In instance t + 24 | o = '0; + | ^ +%Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:25:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'oa' + : ... In instance t + 25 | oa = '0; + | ^~ %Error: Exiting due to diff --git a/test_regress/t/t_wire_behp1800_bad.pl b/test_regress/t/t_wire_behp1800_bad.pl index 8c9b1887a..8bf670e39 100755 --- a/test_regress/t/t_wire_behp1800_bad.pl +++ b/test_regress/t/t_wire_behp1800_bad.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_wire_behp1800_bad.v b/test_regress/t/t_wire_behp1800_bad.v index e2d890e7f..b80f7c041 100644 --- a/test_regress/t/t_wire_behp1800_bad.v +++ b/test_regress/t/t_wire_behp1800_bad.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2018 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2018 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t ( output o, diff --git a/test_regress/t/t_wire_types.pl b/test_regress/t/t_wire_types.pl index 2ac96a92f..3a8a4d160 100755 --- a/test_regress/t/t_wire_types.pl +++ b/test_regress/t/t_wire_types.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2003 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(simulator => 1); diff --git a/test_regress/t/t_wire_types.v b/test_regress/t/t_wire_types.v index 7145c3591..11952324a 100644 --- a/test_regress/t/t_wire_types.v +++ b/test_regress/t/t_wire_types.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Inputs diff --git a/test_regress/t/t_xml_first.out b/test_regress/t/t_xml_first.out index 5e4edbca8..4c75a4867 100644 --- a/test_regress/t/t_xml_first.out +++ b/test_regress/t/t_xml_first.out @@ -11,75 +11,75 @@ - - - + + + - - - - - - - - + + + + + + + + - - + + - - + + - - - + + + - - + + - - + + - - - + + + - - - - - + + + + + - - - - + + + + - - - + + + - - - - - - - + + + + + + + - - - + + + diff --git a/test_regress/t/t_xml_first.pl b/test_regress/t/t_xml_first.pl index 5f8089cdd..8a75bfd1e 100755 --- a/test_regress/t/t_xml_first.pl +++ b/test_regress/t/t_xml_first.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2012 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2012 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_xml_first.v b/test_regress/t/t_xml_first.v index 8c87572c5..7e594036d 100644 --- a/test_regress/t/t_xml_first.v +++ b/test_regress/t/t_xml_first.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2012 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2012 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module t (/*AUTOARG*/ // Outputs diff --git a/test_regress/t/t_xml_output.out b/test_regress/t/t_xml_output.out index 52a262c06..3426e21ae 100644 --- a/test_regress/t/t_xml_output.out +++ b/test_regress/t/t_xml_output.out @@ -11,14 +11,14 @@ - + - - + + - + diff --git a/test_regress/t/t_xml_output.pl b/test_regress/t/t_xml_output.pl index 6c53c5c9d..1c0df5f82 100755 --- a/test_regress/t/t_xml_output.pl +++ b/test_regress/t/t_xml_output.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2012 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2012 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_xml_output.v b/test_regress/t/t_xml_output.v index 28a39022f..ccde3378d 100644 --- a/test_regress/t/t_xml_output.v +++ b/test_regress/t/t_xml_output.v @@ -1,7 +1,8 @@ // DESCRIPTION: Verilator: Verilog Test module // -// This file ONLY is placed into the Public Domain, for any use, -// without warranty, 2019 by Wilson Snyder. +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2019 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 module m (input clk); // verilator tag foo_op diff --git a/test_regress/t/t_xml_tag.out b/test_regress/t/t_xml_tag.out index e192a9b65..30f20a7ca 100644 --- a/test_regress/t/t_xml_tag.out +++ b/test_regress/t/t_xml_tag.out @@ -11,72 +11,72 @@ - - + + - - - - - - - - - - - - + + + + + + + + + + + + - - - - - - + + + + + + - - - - - + + + + + - - - - + + + + - - - - - - - - + + + + + + + + - - - - - - - - - + + + + + + + + + - - + + diff --git a/test_regress/t/t_xml_tag.pl b/test_regress/t/t_xml_tag.pl index 5f8089cdd..8a75bfd1e 100755 --- a/test_regress/t/t_xml_tag.pl +++ b/test_regress/t/t_xml_tag.pl @@ -2,10 +2,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } # DESCRIPTION: Verilator: Verilog Test driver/expect definition # -# Copyright 2012 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2012 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt => 1); diff --git a/test_regress/t/t_xml_tag.v b/test_regress/t/t_xml_tag.v index 1126c8005..6b5a75fe9 100644 --- a/test_regress/t/t_xml_tag.v +++ b/test_regress/t/t_xml_tag.v @@ -2,6 +2,7 @@ // // This file ONLY is placed into the Public Domain, for any use, // without warranty, 2017 by Chris Randall. +// SPDX-License-Identifier: CC0-1.0 interface ifc; integer value; diff --git a/test_regress/vgen.pl b/test_regress/vgen.pl index dd9955f82..03bd0b6f1 100755 --- a/test_regress/vgen.pl +++ b/test_regress/vgen.pl @@ -1046,14 +1046,12 @@ Include some signed arithmetic in the generated code. Experimental. =head1 DISTRIBUTION -Copyright 2001-2020 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. +Copyright 2001-2020 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 =head1 AUTHORS diff --git a/verilator-config-version.cmake.in b/verilator-config-version.cmake.in index d20a842ba..a22cd29f2 100644 --- a/verilator-config-version.cmake.in +++ b/verilator-config-version.cmake.in @@ -7,10 +7,11 @@ # # find_package(verilate 4.0) # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ###################################################################### diff --git a/verilator-config.cmake.in b/verilator-config.cmake.in index e7fe515d4..458b74c49 100644 --- a/verilator-config.cmake.in +++ b/verilator-config.cmake.in @@ -11,10 +11,11 @@ # add_executable(simulator ) # verilate(simulator SOURCES ) # -# Copyright 2003-2020 by Wilson Snyder. This program is free software; you can -# redistribute it and/or modify it under the terms of either the GNU +# Copyright 2003-2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # ######################################################################