diff --git a/Changes b/Changes
index abd146359..93a1e1700 100644
--- a/Changes
+++ b/Changes
@@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 * Verilator 3.711 2009/**
 
+*** Support zero-width constants in concatenations.  [Jeff Winston]
+
 *** Add verilator --pins-uint8 option to use sc_in<uint8_t/uint16_t>.
 
 *** Add verilator -V option, to show verbose version.
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 879154a58..2b06e9470 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -202,6 +202,22 @@ private:
 	    nodep->rhsp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,BOTH).p());
 	    nodep->width(nodep->lhsp()->width() + nodep->rhsp()->width(),
 			 nodep->lhsp()->widthMin() + nodep->rhsp()->widthMin());
+	    // Cleanup zero width Verilog2001 {x,{0{foo}}} now,
+	    // otherwise having width(0) will cause later assertions to fire
+	    if (AstReplicate* repp=nodep->lhsp()->castReplicate()) {
+		if (repp->width()==0) {  // Keep rhs
+		    nodep->replaceWith(nodep->rhsp()->unlinkFrBack());
+		    pushDeletep(nodep); nodep=NULL;
+		    return;
+		}
+	    }
+	    if (AstReplicate* repp=nodep->rhsp()->castReplicate()) {
+		if (repp->width()==0) {  // Keep lhs
+		    nodep->replaceWith(nodep->lhsp()->unlinkFrBack());
+		    pushDeletep(nodep); nodep=NULL;
+		    return;
+		}
+	    }
 	}
 	if (vup->c()->final()) {
 	    if (!nodep->widthSized()) {
@@ -218,7 +234,9 @@ private:
 	    AstConst* constp = nodep->rhsp()->castConst();
 	    if (!constp) { nodep->v3error("Replication value isn't a constant."); return; }
 	    uint32_t times = constp->toUInt();
-	    if (times==0) { nodep->v3error("Replication value is 0."); times=1; }
+	    if (times==0 && !nodep->backp()->castConcat()) {  // Concat Visitor will clean it up.
+		nodep->v3error("Replication value of 0 is only legal under a concatenation."); times=1;
+	    }
 	    nodep->width((nodep->lhsp()->width() * times),
 			 (nodep->lhsp()->widthMin() * times));
 	}
diff --git a/test_regress/t/t_EXAMPLE.v b/test_regress/t/t_EXAMPLE.v
index 891ce56c5..059e8465d 100644
--- a/test_regress/t/t_EXAMPLE.v
+++ b/test_regress/t/t_EXAMPLE.v
@@ -87,13 +87,8 @@ module Test (/*AUTOARG*/
    // merge the output values into the result vector.
 
    input clk;
-   input  [31:0] in;
-   output [31:0] out;
-
-   /*AUTOREG*/
-   // Beginning of automatic regs (for this module's undeclared outputs)
-   reg [31:0] 		out;
-   // End of automatics
+   input [31:0]      in;
+   output reg [31:0] out;
 
    always @(posedge clk) begin
       out <= in;
diff --git a/test_regress/t/t_math_concat0.pl b/test_regress/t/t_math_concat0.pl
new file mode 100755
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_math_concat0.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_math_concat0.v b/test_regress/t/t_math_concat0.v
new file mode 100644
index 000000000..eab897d2d
--- /dev/null
+++ b/test_regress/t/t_math_concat0.v
@@ -0,0 +1,87 @@
+// DESCRIPTION: Verilator: Verilog Test module
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [15:0]  in = crc[15:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [15:0]		outa;			// From test of Test.v
+   wire [15:0]		outb;			// From test of Test.v
+   wire [15:0]		outc;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .outa			(outa[15:0]),
+	      .outb			(outb[15:0]),
+	      .outc			(outc[15:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[15:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {16'h0, outa, outb, outc};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h09be74b1b0f8c35d
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   outa, outb, outc,
+   // Inputs
+   clk, in
+   );
+
+   input clk;
+   input [15:0]      in;
+   output reg [15:0] outa;
+   output reg [15:0] outb;
+   output reg [15:0] outc;
+
+   parameter WIDTH = 0;
+   always @(posedge clk) begin
+      outa <= {in};
+      outb <= {{WIDTH{1'b0}}, in};
+      outc <= {in, {WIDTH{1'b0}}};
+   end
+endmodule