diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp
index cb646a942..7345bd773 100644
--- a/src/V3SplitVar.cpp
+++ b/src/V3SplitVar.cpp
@@ -453,12 +453,17 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
         m_forPackedSplit.m_refs[m_modp].add(refp);
         return refp;
     }
+    void handleVarXRef(AstVarXRef* const nodep) {
+        UINFO(4, nodep->varp() << " Has hierarchical reference");
+        m_forPackedSplit.m_hasXref.emplace(nodep->varp());
+    }
 
     void visit(AstNode* nodep) override { iterateChildren(nodep); }
     void visit(AstNodeModule* nodep) override {
         UINFO(4, "Start checking " << nodep->prettyNameQ());
         if (!VN_IS(nodep, Module)) {
             UINFO(4, "Skip " << nodep->prettyNameQ());
+            nodep->foreach([this](AstVarXRef* const nodep) { handleVarXRef(nodep); });
             return;
         }
         UASSERT_OBJ(!m_modp, m_modp, "Nested module declaration");
@@ -547,10 +552,7 @@ class SplitUnpackedVarVisitor final : public VNVisitor, public SplitVarImpl {
             m_foundTargetVar.insert(nodep->varp());
         }
     }
-    void visit(AstVarXRef* nodep) override {
-        UINFO(4, nodep->varp() << " Has hierarchical reference");
-        m_forPackedSplit.m_hasXref.emplace(nodep->varp());
-    }
+    void visit(AstVarXRef* nodep) override { handleVarXRef(nodep); }
     void visit(AstSel* nodep) override {
         if (VN_IS(nodep->fromp(), VarRef)) m_forPackedSplit.m_refs[m_modp].add(nodep);
         iterateChildren(nodep);
diff --git a/test_regress/t/t_split_var_xref.py b/test_regress/t/t_split_var_xref.py
new file mode 100755
index 000000000..3476171ff
--- /dev/null
+++ b/test_regress/t/t_split_var_xref.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(timing_loop=True, verilator_flags2=["--timing"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_split_var_xref.v b/test_regress/t/t_split_var_xref.v
new file mode 100644
index 000000000..022ec212d
--- /dev/null
+++ b/test_regress/t/t_split_var_xref.v
@@ -0,0 +1,33 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2025 by Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+module child (
+    input logic test_out
+);
+  initial begin
+    #1;
+    if (test_out != 1) $stop;
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule
+
+module parent;
+  logic [1:0] test_out;
+
+  child u0 (.test_out(test_out[0]));
+endmodule
+
+interface my_if;
+  initial begin
+    t.test_parent.test_out = 1;
+  end
+endinterface
+
+module t;
+  parent test_parent ();
+  my_if intf ();
+endmodule