diff --git a/src/verilog.y b/src/verilog.y
index 87c964bc4..1638c83fa 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -6224,10 +6224,11 @@ property_port_itemDirE:
         ;
 
 property_declarationBody<nodep>:  // IEEE: part of property_declaration
-        //UNSUP assertion_variable_declarationList property_statement_spec  {}
+                assertion_variable_declarationList
+                        { $$ = nullptr; BBUNSUP($1->fileline(), "Unsupported: property variable declaration"); }
         //                      // IEEE-2012: Incorrectly has yCOVER ySEQUENCE then property_spec here.
         //                      // Fixed in IEEE 1800-2017
-                property_spec                           { $$ = $1; }
+        |       property_spec                           { $$ = $1; }
         |       property_spec ';'                       { $$ = $1; }
         ;
 
diff --git a/test_regress/t/t_assert_property_var_unsup.out b/test_regress/t/t_assert_property_var_unsup.out
index ad85bd9df..16e308717 100644
--- a/test_regress/t/t_assert_property_var_unsup.out
+++ b/test_regress/t/t_assert_property_var_unsup.out
@@ -1,10 +1,14 @@
-%Error: t/t_assert_property_var_unsup.v:17:11: syntax error, unexpected IDENTIFIER, expecting "'{"
+%Error-UNSUPPORTED: t/t_assert_property_var_unsup.v:17:11: Unsupported: property variable declaration
    17 |       int prevcyc;
       |           ^~~~~~~
+                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
+%Error: t/t_assert_property_var_unsup.v:18:7: syntax error, unexpected '(', expecting endproperty
+   18 |       (valid, prevcyc = cyc) |=> (cyc == prevcyc + 1);
+      |       ^
 %Error-UNSUPPORTED: t/t_assert_property_var_unsup.v:24:31: Unsupported: property variable default value
    24 |    property with_def(int nine = 9);
       |                               ^
-                    ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
 %Error: Internal Error: t/t_assert_property_var_unsup.v:7:8: ../V3ParseSym.h:#: Symbols suggest ending PROPERTY 'prop' but parser thinks ending MODULE 't'
     7 | module t ( 
       |        ^
+                        ... See the manual at https://verilator.org/verilator_doc.html for more assistance.