From bc853e260bfad2f9f21e4294c45425e3bb99e7e7 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Wed, 12 Jun 2024 17:07:33 +0100
Subject: [PATCH] Support StructSel in unpacked array assignments (#5176)

---
 src/V3Slice.cpp                     |  2 +-
 test_regress/t/t_array_in_struct.pl | 21 ++++++++++
 test_regress/t/t_array_in_struct.v  | 61 +++++++++++++++++++++++++++++
 3 files changed, 83 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_array_in_struct.pl
 create mode 100644 test_regress/t/t_array_in_struct.v

diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp
index 229403338..ca5b40c59 100644
--- a/src/V3Slice.cpp
+++ b/src/V3Slice.cpp
@@ -200,7 +200,7 @@ class SliceVisitor final : public VNVisitor {
                                    leOffset};
         } else if (VN_IS(nodep, ArraySel) || VN_IS(nodep, NodeVarRef) || VN_IS(nodep, NodeSel)
                    || VN_IS(nodep, CMethodHard) || VN_IS(nodep, MemberSel)
-                   || VN_IS(nodep, ExprStmt)) {
+                   || VN_IS(nodep, ExprStmt) || VN_IS(nodep, StructSel)) {
             UINFO(9, "  cloneSel(" << elements << "," << elemIdx << ") " << nodep << endl);
             const int leOffset = !arrayp->rangep()->ascending()
                                      ? arrayp->rangep()->elementsConst() - 1 - elemIdx
diff --git a/test_regress/t/t_array_in_struct.pl b/test_regress/t/t_array_in_struct.pl
new file mode 100755
index 000000000..b46d46042
--- /dev/null
+++ b/test_regress/t/t_array_in_struct.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_array_in_struct.v b/test_regress/t/t_array_in_struct.v
new file mode 100644
index 000000000..3f8823f92
--- /dev/null
+++ b/test_regress/t/t_array_in_struct.v
@@ -0,0 +1,61 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2024 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+//bug991
+module t (/*AUTOARG*/);
+
+   typedef struct {
+      logic [31:0] arr [3:0];
+   } a_t;
+
+   typedef struct {
+      logic [31:0] arr [0:3];
+   } b_t;
+
+
+   a_t array_assign;
+   a_t array_other;
+
+   b_t larray_assign;
+   b_t larray_other;
+
+   initial begin
+      array_assign.arr[0] = 32'd1;
+      array_assign.arr[3:1] = '{32'd4, 32'd3, 32'd2};
+
+      array_other.arr[0] = array_assign.arr[0]+10;
+      array_other.arr[3:1] = array_assign.arr[3:1];
+      if (array_other.arr[0] != 11) $stop;
+      if (array_other.arr[1] != 2) $stop;
+      if (array_other.arr[2] != 3) $stop;
+      if (array_other.arr[3] != 4) $stop;
+
+      larray_assign.arr[0] = 32'd1;
+      larray_assign.arr[1:3] = '{32'd4, 32'd3, 32'd2};
+
+      larray_other.arr[0] = larray_assign.arr[0]+10;
+      larray_other.arr[1:3] = larray_assign.arr[1:3];
+      if (larray_other.arr[0] != 11) $stop;
+      if (larray_other.arr[1] != 4) $stop;
+      if (larray_other.arr[2] != 3) $stop;
+      if (larray_other.arr[3] != 2) $stop;
+
+      larray_other.arr = '{5, 6, 7, 8};
+      if (larray_other.arr[0] != 5) $stop;
+      if (larray_other.arr[1] != 6) $stop;
+      if (larray_other.arr[2] != 7) $stop;
+      if (larray_other.arr[3] != 8) $stop;
+
+      larray_other.arr = larray_assign.arr;
+      if (larray_other.arr[0] != 1) $stop;
+      if (larray_other.arr[1] != 4) $stop;
+      if (larray_other.arr[2] != 3) $stop;
+      if (larray_other.arr[3] != 2) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule