From bb0300f605e90371a02e053902c75860c54df610 Mon Sep 17 00:00:00 2001
From: Jakub Michalski <143384197+jmichalski-ant@users.noreply.github.com>
Date: Fri, 24 Jul 2026 14:50:03 +0200
Subject: [PATCH] Fix table optimization causing not contextually convertible
 to bool error (#7983)

Signed-off-by: Jakub Michalski <jmichalski@antmicro.com>
---
 src/V3Table.cpp                |   7 +-
 test_regress/t/t_table_wide.py |  16 ++++
 test_regress/t/t_table_wide.v  | 146 +++++++++++++++++++++++++++++++++
 3 files changed, 167 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_table_wide.py
 create mode 100644 test_regress/t/t_table_wide.v

diff --git a/src/V3Table.cpp b/src/V3Table.cpp
index d99f25e27..8a974afa4 100644
--- a/src/V3Table.cpp
+++ b/src/V3Table.cpp
@@ -370,8 +370,11 @@ private:
                 V3Number outputChgMask{nodep, static_cast<int>(m_outVarps.size()), 0};
                 outputChgMask.setBit(tov.ord(), 1);
                 AstNodeExpr* const condp
-                    = new AstAnd{fl, select(fl, outputAssignedTableVscp, indexVscp),
-                                 new AstConst{fl, outputChgMask}};
+                    = new AstNeq{fl,
+                                 new AstAnd{fl, select(fl, outputAssignedTableVscp, indexVscp),
+                                            new AstConst{fl, outputChgMask}},
+                                 new AstConst{fl, AstConst::WidthedValue{},
+                                              static_cast<int>(m_outVarps.size()), 0}};
                 outsetp = new AstIf{fl, condp, outsetp};
             }
 
diff --git a/test_regress/t/t_table_wide.py b/test_regress/t/t_table_wide.py
new file mode 100755
index 000000000..8e271fdb8
--- /dev/null
+++ b/test_regress/t/t_table_wide.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.passes()
diff --git a/test_regress/t/t_table_wide.v b/test_regress/t/t_table_wide.v
new file mode 100644
index 000000000..cd644dac4
--- /dev/null
+++ b/test_regress/t/t_table_wide.v
@@ -0,0 +1,146 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+module m(input in);
+  // at least 65 variables are required
+  reg id42;
+  reg id43;
+  reg id44;
+  reg id45;
+  reg id46;
+  reg id47;
+  reg id48;
+  reg id49;
+  reg id50;
+  reg id51;
+  reg id52;
+  reg id53;
+  reg id54;
+  reg id55;
+  reg id56;
+  reg id57;
+  reg id58;
+  reg id59;
+  reg id60;
+  reg id61;
+  reg id62;
+  reg id63;
+  reg id64;
+  reg id65;
+  reg id66;
+  reg id67;
+  reg id68;
+  reg id69;
+  reg id70;
+  reg id71;
+  reg id72;
+  reg id73;
+  reg id74;
+  reg id75;
+  reg id76;
+  reg id77;
+  reg id78;
+  reg id79;
+  reg id80;
+  reg id81;
+  reg id82;
+  reg id83;
+  reg id84;
+  reg id85;
+  reg id86;
+  reg id87;
+  reg id88;
+  reg id89;
+  reg id90;
+  reg id91;
+  reg id92;
+  reg id93;
+  reg id94;
+  reg id95;
+  reg id96;
+  reg id97;
+  reg id98;
+  reg id99;
+  reg id100;
+  reg id101;
+  reg id102;
+  reg id103;
+  reg id104;
+  reg id105;
+  reg id106;
+  always @(posedge in) begin
+    if (in) begin
+      id42 <= 1'h0;
+      id43 <= 1'h0;
+      id44 <= 1'h0;
+      id45 <= 1'h0;
+      id46 <= 1'h0;
+      id47 <= 1'h0;
+      id48 <= 1'h0;
+      id49 <= 1'h0;
+      id50 <= 1'h0;
+      id51 <= 1'h0;
+      id52 <= 1'h0;
+      id53 <= 1'h0;
+      id54 <= 1'h0;
+      id55 <= 1'h0;
+      id56 <= 1'h0;
+      id57 <= 1'h0;
+      id58 <= 1'h0;
+      id59 <= 1'h0;
+      id60 <= 1'h0;
+      id61 <= 1'h0;
+      id62 <= 1'h0;
+      id63 <= 1'h0;
+      id64 <= 1'h0;
+      id65 <= 1'h0;
+      id66 <= 1'h0;
+      id67 <= 1'h0;
+      id68 <= 1'h0;
+      id69 <= 1'h0;
+      id70 <= 1'h0;
+      id71 <= 1'h0;
+      id72 <= 1'h0;
+      id73 <= 1'h0;
+      id74 <= 1'h0;
+      id75 <= 1'h0;
+      id76 <= 1'h0;
+      id77 <= 1'h0;
+      id78 <= 1'h0;
+      id79 <= 1'h0;
+      id80 <= 1'h0;
+      id81 <= 1'h0;
+      id82 <= 1'h0;
+      id83 <= 1'h0;
+      id84 <= 1'h0;
+      id85 <= 1'h0;
+      id86 <= 1'h0;
+      id87 <= 1'h0;
+      id88 <= 1'h0;
+      id89 <= 1'h0;
+      id90 <= 1'h0;
+      id91 <= 1'h0;
+      id92 <= 1'h0;
+      id93 <= 1'h0;
+      id94 <= 1'h0;
+      id95 <= 1'h0;
+      id96 <= 1'h0;
+      id97 <= 1'h0;
+      id98 <= 1'h0;
+      id99 <= 1'h0;
+      id100 <= 1'h0;
+      id101 <= 1'h0;
+      id102 <= 1'h0;
+      id103 <= 1'h0;
+      id104 <= 1'h0;
+      id105 <= 1'h0;
+      id106 <= 1'h0;
+    end
+  end
+  always @(posedge id106) begin
+    $display("abc");
+  end
+endmodule