From b9be4ae4e8cd24c6132b9a9a7708f5a7c373d169 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 8 Jun 2009 15:59:33 -0400
Subject: [PATCH] Fix segfault on unrolling for's with bad inits, bug90.

---
 Changes                          |  4 ++++
 src/V3Unroll.cpp                 |  1 +
 test_regress/t/t_for_init_bug.pl | 16 ++++++++++++++
 test_regress/t/t_for_init_bug.v  | 37 ++++++++++++++++++++++++++++++++
 4 files changed, 58 insertions(+)
 create mode 100755 test_regress/t/t_for_init_bug.pl
 create mode 100644 test_regress/t/t_for_init_bug.v

diff --git a/Changes b/Changes
index da4ccf27f..8a2a8be30 100644
--- a/Changes
+++ b/Changes
@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.71***
+
+**** Fix segfault on unrolling for's with bad inits, bug90. [Andreas Olofsson]
+
 * Verilator 3.710 2009/05/19
 
 **   Verilator is now licensed under LGPL v3 and/or Artistic v2.0.
diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp
index aaab9264b..59f5795ce 100644
--- a/src/V3Unroll.cpp
+++ b/src/V3Unroll.cpp
@@ -102,6 +102,7 @@ private:
 	AstAssign* initAssp = initp->castAssign();
 	if (!initAssp) return cantUnroll(nodep, "no initial assignment");
 	if (initp->nextp() && initp->nextp()!=nodep) nodep->v3fatalSrc("initial assignment shouldn't be a list");
+	if (!initAssp->lhsp()->castVarRef()) return cantUnroll(nodep, "no initial assignment to simple variable");
 	m_forVarp = initAssp->lhsp()->castVarRef()->varp();
 	m_forVscp = initAssp->lhsp()->castVarRef()->varScopep();
 	if (nodep->castGenFor() && !m_forVarp->isGenVar()) {
diff --git a/test_regress/t/t_for_init_bug.pl b/test_regress/t/t_for_init_bug.pl
new file mode 100755
index 000000000..abf04bf42
--- /dev/null
+++ b/test_regress/t/t_for_init_bug.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+#execute ()
+
+ok(1);
+1;
diff --git a/test_regress/t/t_for_init_bug.v b/test_regress/t/t_for_init_bug.v
new file mode 100644
index 000000000..e9167ee9b
--- /dev/null
+++ b/test_regress/t/t_for_init_bug.v
@@ -0,0 +1,37 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   priority_mask,
+   // Inputs
+   muxed_requests
+   );
+
+   parameter ARW = 7;
+
+   // verilator lint_off UNOPTFLAT
+   integer i,j;
+
+   output reg [ARW-1:0] priority_mask;
+
+   input [ARW-1:0] muxed_requests;
+
+   always @* begin
+      for (i=ARW-1;i>0;i=i-1) begin
+	 priority_mask[i]=1'b0;
+	 //   vvvv=== note j=j not j=i; was bug
+	 for( j=j;j>=0;j=j-1)
+	   priority_mask[i]=priority_mask[j] | muxed_requests[j];
+      end
+      //Bit zero is always enabled
+      priority_mask[0]=1'b0;
+   end
+   
+endmodule
+
+// Local Variables:
+// verilog-auto-inst-param-value: t
+// End: