From b97df914ddcbff470c5a37d3c1bd99d9813f4698 Mon Sep 17 00:00:00 2001
From: Pawel Kojma <pkojma@internships.antmicro.com>
Date: Fri, 3 Jul 2026 12:37:48 +0200
Subject: [PATCH] Fix clang++ ambiguous overload of '==' operator (#7863)

---
 include/verilated_types.h          | 18 +++++++++++++-
 test_regress/t/t_clang_overload.py | 16 ++++++++++++
 test_regress/t/t_clang_overload.v  | 39 ++++++++++++++++++++++++++++++
 3 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_clang_overload.py
 create mode 100644 test_regress/t/t_clang_overload.v

diff --git a/include/verilated_types.h b/include/verilated_types.h
index 40847b65e..fd0341a2d 100644
--- a/include/verilated_types.h
+++ b/include/verilated_types.h
@@ -2069,8 +2069,24 @@ struct VlNull final {
     operator T*() const {
         return nullptr;
     }
+    template <class T>
+    bool operator==(T* rhs) const {
+        return !rhs;
+    }
+    template <class T>
+    bool operator==(const T* rhs) const {
+        return !rhs;
+    }
 };
-inline bool operator==(const void* ptr, VlNull) { return !ptr; }
+
+template <class T>
+inline bool operator==(T* lhs, VlNull) {
+    return !lhs;
+}
+template <class T>
+inline bool operator==(const T* lhs, VlNull) {
+    return !lhs;
+}
 
 //===================================================================
 // Verilog class reference container
diff --git a/test_regress/t/t_clang_overload.py b/test_regress/t/t_clang_overload.py
new file mode 100755
index 000000000..0f1f5d0a0
--- /dev/null
+++ b/test_regress/t/t_clang_overload.py
@@ -0,0 +1,16 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of either the GNU Lesser General Public License Version 3
+# or the Perl Artistic License Version 2.0.
+# SPDX-FileCopyrightText: 2026 Wilson Snyder
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('vlt')
+
+test.compile(verilator_flags2=['--binary', '-Wno-WIDTHTRUNC'])
+
+test.passes()
diff --git a/test_regress/t/t_clang_overload.v b/test_regress/t/t_clang_overload.v
new file mode 100644
index 000000000..02f67f60f
--- /dev/null
+++ b/test_regress/t/t_clang_overload.v
@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain.
+// SPDX-FileCopyrightText: 2026 Antmicro
+// SPDX-License-Identifier: CC0-1.0
+
+interface irq_if (
+    input logic clk,
+    input logic resetn
+);
+  logic irq;
+  logic te;
+  logic halted;
+  logic fault;
+  logic wfi;
+  clocking cb @(posedge clk);
+    default input #1step output #2ns;
+    output irq;
+    output te;
+    input halted;
+    input fault;
+    input wfi;
+  endclocking
+  modport DUT_IRQ_PORT(input clk, resetn, output halted, fault, wfi);
+endinterface
+class base_test_class;
+  function int foo();
+  endfunction
+  virtual irq_if.DUT_IRQ_PORT irq_vif;
+  function new(string name);
+  endfunction
+  virtual function void build_phase();
+    if (irq_vif == null) begin
+      if (foo()) $display();
+    end
+  endfunction
+endclass
+module tb_top;
+endmodule