diff --git a/src/V3AstNodeExpr.h b/src/V3AstNodeExpr.h
index 4d1870467..47e290711 100644
--- a/src/V3AstNodeExpr.h
+++ b/src/V3AstNodeExpr.h
@@ -2241,8 +2241,6 @@ public:
     string emitVerilog() override { V3ERROR_NA_RETURN(""); }
     string emitC() override { V3ERROR_NA_RETURN(""); }
     bool cleanOut() const override { V3ERROR_NA_RETURN(""); }
-    int instrCount() const override { return widthInstrs(); }
-    bool isMultiCycleSva() const override { return false; }
 };
 class AstSConsRep final : public AstNodeExpr {
     // Consecutive repetition [*N], [*N:M], [+], [*] (IEEE 1800-2023 16.9.2)
diff --git a/test_regress/t/t_assert_seq_clocking.v b/test_regress/t/t_assert_seq_clocking.v
index f5b4be4b3..db1bdaf24 100644
--- a/test_regress/t/t_assert_seq_clocking.v
+++ b/test_regress/t/t_assert_seq_clocking.v
@@ -15,7 +15,7 @@ module t (
 
   // verilog_format: off  // verible does not support clocking events inside sequence declarations
   sequence s_single;
-    @(posedge clk) a;
+    @(posedge clk) a
   endsequence
 
   sequence s_multi;
diff --git a/test_regress/t/t_assert_seq_clocking_unsup.out b/test_regress/t/t_assert_seq_clocking_unsup.out
index 4ecec0be5..5ab9bb741 100644
--- a/test_regress/t/t_assert_seq_clocking_unsup.out
+++ b/test_regress/t/t_assert_seq_clocking_unsup.out
@@ -11,12 +11,20 @@
                                                         : ... note: In instance 't'
    23 |     @clk a;
       |     ^
-%Error-UNSUPPORTED: t/t_assert_seq_clocking_unsup.v:28:3: Unsupported: Unclocked assertion
+%Error-UNSUPPORTED: t/t_assert_seq_clocking_unsup.v:27:5: Unsupported: non-edge clocking event on a sequence; use an edge such as @(posedge clk)
                                                         : ... note: In instance 't'
-   28 |   assert property (s_nest ##1 a);
+   27 |     @clk a
+      |     ^
+%Error-UNSUPPORTED: t/t_assert_seq_clocking_unsup.v:32:3: Unsupported: Unclocked assertion
+                                                        : ... note: In instance 't'
+   32 |   assert property (s_nest ##1 a);
       |   ^~~~~~
-%Error-UNSUPPORTED: t/t_assert_seq_clocking_unsup.v:29:3: Unsupported: Unclocked assertion
+%Error-UNSUPPORTED: t/t_assert_seq_clocking_unsup.v:33:3: Unsupported: Unclocked assertion
                                                         : ... note: In instance 't'
-   29 |   assert property (s_level);
+   33 |   assert property (s_level);
+      |   ^~~~~~
+%Error-UNSUPPORTED: t/t_assert_seq_clocking_unsup.v:34:3: Unsupported: Unclocked assertion
+                                                        : ... note: In instance 't'
+   34 |   assert property (s_level2);
       |   ^~~~~~
 %Error: Exiting due to
diff --git a/test_regress/t/t_assert_seq_clocking_unsup.v b/test_regress/t/t_assert_seq_clocking_unsup.v
index 5d092ea66..785c67000 100644
--- a/test_regress/t/t_assert_seq_clocking_unsup.v
+++ b/test_regress/t/t_assert_seq_clocking_unsup.v
@@ -22,10 +22,15 @@ module t (
   sequence s_level;
     @clk a;
   endsequence
+
+  sequence s_level2;
+    @clk a
+  endsequence
   // verilog_format: on
 
   assert property (@(posedge clk2) s_multi);
   assert property (s_nest ##1 a);
   assert property (s_level);
+  assert property (s_level2);
 
 endmodule