diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 2898db155..60847b0ec 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -691,7 +691,6 @@ void EmitCSyms::emitSymImp() { ++it) { string name = it->second.m_prettyName; if (it->first == "TOP") continue; - name = name.replace(0, 4, ""); // Remove the "TOP." if ((name.find('.') == string::npos) && (it->second.m_type == "SCOPE_MODULE")) { puts("__Vhier.add(0, &" + protect("__Vscope_" + it->second.m_symName) + ");\n"); } diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 312069210..1b607579d 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -1161,7 +1161,7 @@ sub compile { if ($param{make_pli}) { $self->oprint("Compile vpi\n") if $self->{verbose}; - my @cmd = ($ENV{CXX}, @{$param{pli_flags}}, "-DIS_VPI", + my @cmd = ($ENV{CXX}, @{$param{pli_flags}}, "-DIS_VPI", $ENV{CFLAGS}, "$self->{t_dir}/$self->{pli_filename}"); $self->_run(logfile=>"$self->{obj_dir}/pli_compile.log", @@ -2731,7 +2731,7 @@ Run simulator-agnostic distribution tests. Run GHDL simulator tests. -=item --iverilog +=item --iv Run Icarus Verilog simulator tests. diff --git a/test_regress/t/t_vpi_module.cpp b/test_regress/t/t_vpi_module.cpp index 589ebd82c..feb429d47 100644 --- a/test_regress/t/t_vpi_module.cpp +++ b/test_regress/t/t_vpi_module.cpp @@ -48,6 +48,12 @@ unsigned int main_time = 0; return __LINE__; \ } +#define CHECK_RESULT_Z(got) \ + if (got) { \ + printf("%%Error: %s:%d: GOT = !NULL EXP = NULL\n", FILENM, __LINE__); \ + return __LINE__; \ + } + #define CHECK_RESULT_CSTR(got, exp) \ if (strcmp((got), (exp))) { \ printf("%%Error: %s:%d: GOT = '%s' EXP = '%s'\n", FILENM, __LINE__, \ @@ -55,17 +61,45 @@ unsigned int main_time = 0; return __LINE__; \ } +void modDump(const TestVpiHandle& it, int n) { + while (TestVpiHandle hndl = vpi_scan(it)) { + const char* nm = vpi_get_str(vpiName, hndl); + for (int i = 0; i < n; i++) printf(" "); + printf("%s\n", nm); + TestVpiHandle subIt = vpi_iterate(vpiModule, hndl); + if (subIt) modDump(subIt, n + 1); + } +} + extern "C" { int mon_check() { TestVpiHandle it = vpi_iterate(vpiModule, NULL); +#ifdef IS_ICARUS + // Icarus segfaults when some VPI handles are freed + it.nofree(); +#endif CHECK_RESULT_NZ(it); + // Uncomment to see what other simulators return + // modDump(it, 0); + // return 1; TestVpiHandle topmod = vpi_scan(it); CHECK_RESULT_NZ(topmod); - char* name = vpi_get_str(vpiName, topmod); - CHECK_RESULT_NZ(name); - CHECK_RESULT_CSTR(name, "t"); + const char* t_name = vpi_get_str(vpiName, topmod); + CHECK_RESULT_NZ(t_name); + + // Icarus reports the top most module as "top" + if (strcmp(t_name, "top") == 0) { + it = vpi_iterate(vpiModule, topmod); + CHECK_RESULT_NZ(it); + topmod = vpi_scan(it); + t_name = vpi_get_str(vpiName, topmod); + CHECK_RESULT_NZ(t_name); + } + CHECK_RESULT_CSTR(t_name, "t"); + TestVpiHandle topmod_done = (vpi_scan(it)); + CHECK_RESULT_Z(topmod_done); TestVpiHandle it2 = vpi_iterate(vpiModule, topmod); CHECK_RESULT_NZ(it2); @@ -73,8 +107,8 @@ int mon_check() { TestVpiHandle mod2 = vpi_scan(it2); CHECK_RESULT_NZ(mod2); - name = vpi_get_str(vpiName, mod2); - CHECK_RESULT_CSTR(name, "mod_a"); + const char* mod_a_name = vpi_get_str(vpiName, mod2); + CHECK_RESULT_CSTR(mod_a_name, "mod_a"); TestVpiHandle it3 = vpi_iterate(vpiModule, mod2); CHECK_RESULT_NZ(it3); @@ -82,14 +116,14 @@ int mon_check() { TestVpiHandle mod3 = vpi_scan(it3); CHECK_RESULT_NZ(mod3); - name = vpi_get_str(vpiName, mod3); - if (strcmp(name, "mod_b") == 0) { + const char* mod_c_name = vpi_get_str(vpiName, mod3); + if (strcmp(mod_c_name, "mod_b") == 0) { // Full visibility in other simulators, skip mod_b TestVpiHandle mod4 = vpi_scan(it3); CHECK_RESULT_NZ(mod4); - name = vpi_get_str(vpiName, mod4); + mod_c_name = vpi_get_str(vpiName, mod4); } - CHECK_RESULT_CSTR(name, "mod_c."); + CHECK_RESULT_CSTR(mod_c_name, "mod_c."); return 0; // Ok }