diff --git a/Changes b/Changes index e4594ab08..d08c07200 100644 --- a/Changes +++ b/Changes @@ -10,9 +10,11 @@ indicates the contributor was also the author of the fix; Thanks! *** Fix memory delayed assignments from multiple clock domains. [Andrew Ling] +*** Support arrayed SystemC I/O pins. [Christophe Joly] + *** Report MULTIDRIVEN on memories set in multiple clock domains. -*** Support arrayed SystemC I/O pins. [Christophe Joly] +*** Report ENDLABEL on mismatching end labels, bug450. [Iztok Jeras] **** Fix expansion of back-slashed escaped macros, bug441. [Alberto Del Rio] diff --git a/bin/verilator b/bin/verilator index 01d02313e..c3490c789 100755 --- a/bin/verilator +++ b/bin/verilator @@ -905,9 +905,9 @@ Disable the specified warning message. Disable all lint related warning messages, and all style warnings. This is equivalent to "-Wno-CASEINCOMPLETE -Wno-CASEOVERLAP -Wno-CASEX --Wno-CASEWITHX -Wno-CMPCONST -Wno-IMPLICIT -Wno-LITENDIAN -Wno-SYNCASYNCNET --Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED -Wno-WIDTH" plus the list shown for -Wno-style. +-Wno-CASEWITHX -Wno-CMPCONST -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN +-Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED -Wno-WIDTH" plus +the list shown for Wno-style. It is strongly recommended you cleanup your code rather than using this option, it is only intended to be use when running test-cases of code @@ -937,8 +937,8 @@ Enables the specified warning message. Enable all lint related warning messages (note by default they are already enabled), but do not affect style messages. This is equivalent to "-Wwarn-CASEINCOMPLETE -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASEWITHX --Wwarn-CMPCONST -Wwarn-IMPLICIT -Wwarn-LITENDIAN -Wwarn-REALCVT --Wwarn-UNSIGNED -Wwarn-WIDTH". +-Wwarn-CMPCONST -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN +-Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH". =item -Wwarn-style @@ -2585,6 +2585,14 @@ designs should now be using the #(...) format to specify parameters. Disabled by default as this is a code style warning; it will simulate correctly. +=item ENDLABEL + +Warns that a label attached to a "end"-something statement does not match +the label attached to the block start. + +Ignoring this warning will only suppress the lint check, it will simulate +correctly. + =item GENCLK Warns that the specified signal is generated, but is also being used as a diff --git a/src/V3Error.h b/src/V3Error.h index 96e382e73..6177f8ed4 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -69,6 +69,7 @@ public: COMBDLY, // Combinatorial delayed assignment DEFPARAM, // Style: Defparam DECLFILENAME, // Declaration doesn't match filename + ENDLABEL, // End lable name mismatch GENCLK, // Generated Clock IFDEPTH, // If statements too deep IMPERFECTSCH, // Imperfect schedule (disabled by default) @@ -114,7 +115,7 @@ public: "BLKANDNBLK", "BLKSEQ", "CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CDCRSTLOGIC", "CMPCONST", "COMBDLY", "DEFPARAM", "DECLFILENAME", - "GENCLK", + "ENDLABEL", "GENCLK", "IFDEPTH", "IMPERFECTSCH", "IMPLICIT", "IMPURE", "INCABSPATH", "LITENDIAN", "MODDUP", "MULTIDRIVEN", @@ -141,6 +142,7 @@ public: bool lintError() const { return ( m_e==CASEINCOMPLETE || m_e==CASEOVERLAP || m_e==CASEWITHX || m_e==CASEX || m_e==CMPCONST + || m_e==ENDLABEL || m_e==IMPLICIT || m_e==LITENDIAN || m_e==REALCVT diff --git a/src/verilog.y b/src/verilog.y index 6344bbe6c..a8b50233f 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -96,6 +96,12 @@ public: nodep->addNext(new AstStop(fileline)); return nodep; } + void endLabel(FileLine* fl, AstNode* nodep, string* endnamep) { endLabel(fl, nodep->prettyName(), endnamep); } + void endLabel(FileLine* fl, string name, string* endnamep) { + if (fl && endnamep && *endnamep != "" && name != *endnamep) { + fl->v3warn(ENDLABEL,"End label '"<<*endnamep<<"' does not match begin label '"<deleteTree(); m_varDTypep=NULL; } // It was cloned, so this is safe. m_varDTypep = dtypep; @@ -631,7 +637,8 @@ package_declaration: // ==IEEE: package_declaration packageFront package_itemListE yENDPACKAGE endLabelE { $1->modTrace(v3Global.opt.trace() && $1->fileline()->tracingOn()); // Stash for implicit wires, etc if ($2) $1->addStmtp($2); - SYMP->popScope($1); } + SYMP->popScope($1); + GRAMMARP->endLabel($4,$1,$4); } ; packageFront: @@ -708,13 +715,15 @@ module_declaration: // ==IEEE: module_declaration { $1->modTrace(v3Global.opt.trace() && $1->fileline()->tracingOn()); // Stash for implicit wires, etc if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); if ($5) $1->addStmtp($5); - SYMP->popScope($1); } + SYMP->popScope($1); + GRAMMARP->endLabel($7,$1,$7); } | udpFront parameter_port_listE portsStarE ';' module_itemListE yENDPRIMITIVE endLabelE { $1->modTrace(false); // Stash for implicit wires, etc if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); if ($5) $1->addStmtp($5); - SYMP->popScope($1); } + SYMP->popScope($1); + GRAMMARP->endLabel($7,$1,$7); } // //UNSUP yEXTERN modFront parameter_port_listE portsStarE ';' //UNSUP { UNSUP } @@ -885,7 +894,8 @@ program_declaration: // IEEE: program_declaration + program_nonansi_header + pr { $1->modTrace(v3Global.opt.trace() && $1->fileline()->tracingOn()); // Stash for implicit wires, etc if ($2) $1->addStmtp($2); if ($3) $1->addStmtp($3); if ($5) $1->addStmtp($5); - SYMP->popScope($1); } + SYMP->popScope($1); + GRAMMARP->endLabel($7,$1,$7); } //UNSUP yEXTERN pgmFront parameter_port_listE portsStarE ';' //UNSUP { PARSEP->symPopScope(VAstType::PROGRAM); } ; @@ -1453,10 +1463,10 @@ genTopBlock: genItemBegin: // IEEE: part of generate_block yBEGIN genItemList yEND { $$ = new AstBegin($1,"genblk",$2); } | yBEGIN yEND { $$ = NULL; } - | id ':' yBEGIN genItemList yEND endLabelE { $$ = new AstBegin($2,*$1,$4); } - | id ':' yBEGIN yEND endLabelE { $$ = NULL; } - | yBEGIN ':' idAny genItemList yEND endLabelE { $$ = new AstBegin($2,*$3,$4); } - | yBEGIN ':' idAny yEND endLabelE { $$ = NULL; } + | id ':' yBEGIN genItemList yEND endLabelE { $$ = new AstBegin($2,*$1,$4); GRAMMARP->endLabel($6,*$1,$6); } + | id ':' yBEGIN yEND endLabelE { $$ = NULL; GRAMMARP->endLabel($5,*$1,$5); } + | yBEGIN ':' idAny genItemList yEND endLabelE { $$ = new AstBegin($2,*$3,$4); GRAMMARP->endLabel($6,*$3,$6); } + | yBEGIN ':' idAny yEND endLabelE { $$ = NULL; GRAMMARP->endLabel($5,*$3,$5); } ; genItemList: @@ -1827,8 +1837,8 @@ stmtBlock: // IEEE: statement + seq_block + par_block seq_block: // ==IEEE: seq_block // // IEEE doesn't allow declarations in unnamed blocks, but several simulators do. // // So need begin's even if unnamed to scope variables down - seq_blockFront blockDeclStmtList yEND endLabelE { $$=$1; $1->addStmtsp($2); SYMP->popScope($1); } - | seq_blockFront /**/ yEND endLabelE { $$=$1; SYMP->popScope($1); } + seq_blockFront blockDeclStmtList yEND endLabelE { $$=$1; $1->addStmtsp($2); SYMP->popScope($1); GRAMMARP->endLabel($4,$1,$4); } + | seq_blockFront /**/ yEND endLabelE { $$=$1; SYMP->popScope($1); GRAMMARP->endLabel($3,$1,$3); } ; seq_blockFront: // IEEE: part of par_block @@ -2230,7 +2240,8 @@ list_of_argumentsE: // IEEE: [list_of_arguments] task_declaration: // ==IEEE: task_declaration yTASK lifetimeE taskId tfGuts yENDTASK endLabelE - { $$ = $3; $$->addStmtsp($4); SYMP->popScope($$); } + { $$ = $3; $$->addStmtsp($4); SYMP->popScope($$); + GRAMMARP->endLabel($6,$$,$6); } ; task_prototype: // ==IEEE: task_prototype @@ -2240,7 +2251,8 @@ task_prototype: // ==IEEE: task_prototype function_declaration: // IEEE: function_declaration + function_body_declaration yFUNCTION lifetimeE funcId funcIsolateE tfGuts yENDFUNCTION endLabelE { $$ = $3; $3->attrIsolateAssign($4); $$->addStmtsp($5); - SYMP->popScope($$); } + SYMP->popScope($$); + GRAMMARP->endLabel($7,$$,$7); } ; function_prototype: // IEEE: function_prototype @@ -3004,10 +3016,10 @@ strAsText: yaSTRING { $$ = GRAMMARP->createTextQuoted($1,*$1);} ; -endLabelE: - /* empty */ { } - | ':' idAny { } - //UNSUP ':' yNEW__ETC { } +endLabelE: + /* empty */ { $$ = NULL; $$=NULL; } + | ':' idAny { $$ = $2; $$=$2; } + //UNSUP ':' yNEW__ETC { $$ = $2; $$=$2; } ; //************************************************ diff --git a/test_regress/t/t_hierarchy_identifier_bad.pl b/test_regress/t/t_hierarchy_identifier_bad.pl index 7058e622f..64a865a77 100755 --- a/test_regress/t/t_hierarchy_identifier_bad.pl +++ b/test_regress/t/t_hierarchy_identifier_bad.pl @@ -8,11 +8,17 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Version 2.0. compile ( + v_flags2 => ["--lint-only"], + fails=>1, + expect=> +q{%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' +%Warning-ENDLABEL: Use .* +%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'generate_for_bad' does not match begin label 'generate_for' +%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'generate_if_if_bad' does not match begin label 'generate_if_if' +%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 'generate_if_else_bad' does not match begin label 'generate_if_else' +%Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:\d+: End label 't_bad' does not match begin label 't' +%Error: Exiting due to.*}, ); -execute ( - check_finished=>1, - ); - ok(1); 1;