diff --git a/Changes b/Changes
index 60a9feb69..020cb7193 100644
--- a/Changes
+++ b/Changes
@@ -13,6 +13,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix some delayed assignments of typedefed unpacked arrays.
 
+****  Fix wire declarations with size and not range, bug466. [Alex Solomatnikov]
+
 ****  Fix parameter pin vs. normal pin error, bug704. [Alex Solomatnikov]
 
 
diff --git a/src/verilog.y b/src/verilog.y
index 3663ee035..4837a21b6 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1879,7 +1879,7 @@ netSigList<varp>:		// IEEE: list_of_port_identifiers
 netSig<varp>:			// IEEE: net_decl_assignment -  one element from list_of_port_identifiers
 		netId sigAttrListE			{ $$ = VARDONEA($<fl>1,*$1, NULL, $2); }
 	|	netId sigAttrListE '=' expr		{ $$ = VARDONEA($<fl>1,*$1, NULL, $2); $$->addNext(new AstAssignW($3,new AstVarRef($3,$$->name(),true),$4)); }
-	|	netId rangeList sigAttrListE		{ $$ = VARDONEA($<fl>1,*$1, $2, $3); }
+	|	netId variable_dimensionList sigAttrListE	{ $$ = VARDONEA($<fl>1,*$1, $2, $3); }
 	;
 
 netId<strp>:
diff --git a/test_regress/t/t_mem_multiwire.v b/test_regress/t/t_mem_multiwire.v
index 89b36608d..016b141a5 100644
--- a/test_regress/t/t_mem_multiwire.v
+++ b/test_regress/t/t_mem_multiwire.v
@@ -12,6 +12,7 @@ module t (/*AUTOARG*/
 
    // verilator lint_off LITENDIAN
    wire [7:0] array [2:0][1:3];
+   wire [7:0] arrayNoColon [2][3];
    // verilator lint_on LITENDIAN
 
    integer cyc; initial cyc=0;