From b51d1971174fad84d5d437a78ac892eb1d432b29 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 7 Aug 2012 18:24:51 -0400
Subject: [PATCH] Fix defparam in generate broke in 3.840, bug543.

---
 Changes                          |  2 ++
 src/V3LinkDot.cpp                |  9 +++++--
 test_regress/t/t_gen_defparam.pl | 18 +++++++++++++
 test_regress/t/t_gen_defparam.v  | 43 ++++++++++++++++++++++++++++++++
 4 files changed, 70 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_gen_defparam.pl
 create mode 100644 test_regress/t/t_gen_defparam.v

diff --git a/Changes b/Changes
index ecc54683c..effde60ea 100644
--- a/Changes
+++ b/Changes
@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix double-deep parameter cell WIDTHs, bug541.  [Hiroki Honda]
 
+****  Fix defparam in generate broke in 3.840, bug543. [Alex Solomatnikov]
+
 
 * Verilator 3.840 2012/07/31 Beta
 
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 1f6478c38..3fb9f586a 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -544,6 +544,10 @@ private:
 	    m_statep->insertInline(aboveSymp, m_modSymp, nodep, nodep->name());
 	}
     }
+    virtual void visit(AstDefParam* nodep, AstNUser*) {
+	nodep->user1p(m_curSymp);
+	nodep->iterateChildren(*this);
+    }
     virtual void visit(AstGenerate* nodep, AstNUser*) {
 	// Begin: ... blocks often replicate under genif/genfor, so simply suppress duplicate checks
 	// See t_gen_forif.v for an example.
@@ -834,14 +838,15 @@ private:
     virtual void visit(AstDefParam* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
 	nodep->v3warn(DEFPARAM,"Suggest replace defparam with Verilog 2001 #(."<<nodep->name()<<"(...etc...))");
-	VSymEnt* foundp = m_statep->getNodeSym(m_modp)->findIdFallback(nodep->path());
+	VSymEnt* foundp = m_statep->getNodeSym(nodep)->findIdFallback(nodep->path());
 	AstCell* cellp = foundp->nodep()->castCell();
 	if (!cellp) {
 	    nodep->v3error("In defparam, cell "<<nodep->path()<<" never declared");
 	} else {
 	    AstNode* exprp = nodep->rhsp()->unlinkFrBack();
 	    UINFO(9,"Defparam cell "<<nodep->path()<<"."<<nodep->name()
-		  <<" <= "<<exprp<<endl);
+		  <<" attach-to "<<cellp
+		  <<"  <= "<<exprp<<endl);
 	    // Don't need to check the name of the defparam exists.  V3Param does.
 	    AstPin* pinp = new AstPin (nodep->fileline(),
 				       -1, // Pin# not relevant
diff --git a/test_regress/t/t_gen_defparam.pl b/test_regress/t/t_gen_defparam.pl
new file mode 100755
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_gen_defparam.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_gen_defparam.v b/test_regress/t/t_gen_defparam.v
new file mode 100644
index 000000000..041cf2966
--- /dev/null
+++ b/test_regress/t/t_gen_defparam.v
@@ -0,0 +1,43 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2012 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   parameter PAR = 3;
+
+   wire [31:0] o1a,o1b;
+
+   m1 #(0) m1a(.o(o1a));
+   m1 #(1) m1b(.o(o1b));
+
+   always @ (posedge clk) begin
+      if (o1a != 8) $stop;
+      if (o1b != 4) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module m1 (output wire [31:0] o);
+   parameter W = 0;
+   generate
+      if (W == 0) begin
+         m2 m2 (.o(o));
+	 defparam m2.PAR2 = 8;
+      end
+      else begin
+         m2 m2 (.o(o));
+	 defparam m2.PAR2 = 4;
+      end
+   endgenerate
+endmodule
+
+module m2 (output wire [31:0] o);
+   parameter PAR2 = 10;
+   assign o = PAR2;
+endmodule