diff --git a/bin/verilator b/bin/verilator
index 328d74ee0..2ded9a60d 100755
--- a/bin/verilator
+++ b/bin/verilator
@@ -903,7 +903,8 @@ declarations inside port lists.
 Verilator supports the `begin_keywords and `end_keywords compiler
 directives.
 
-Verilator treats the uwire keyword as if it were the normal wire keyword.
+Verilator supports the uwire, $countones, $isunknown, $onehot and $onehot0
+keywords.  Verilator partially supports the uwire keyword.
 
 =head1 SYSTEMVERILOG (IEEE 1800-2005) SUPPORT
 
@@ -916,12 +917,15 @@ always_comb, always_ff, always_latch, and final.
 
 =head1 SUGAR/PSL SUPPORT
 
-With the --assert switch, Verilator is just beginning to support the
-Property Specification Language (PSL), specifically the simple subset
-without time-branching primitives.  Verilator currently only converts PSL
+Most future work is being directed towards improving SystemVerilog
+assertions instead of PSL.  If you are using these PSL features, please
+contact the author as they may be depreciated in future versions.
+
+With the --assert switch, Verilator enables support of the Property
+Specification Language (PSL), specifically the simple PSL subset without
+time-branching primitives.  Verilator currently only converts PSL
 assertions to simple "if (...) error" statements, and coverage statements
-to increment the line counters described in the coverage section.  If you
-need additional features please contact the author.
+to increment the line counters described in the coverage section.
 
 Verilator implements these keywords: assert, assume (same as assert),
 default (for clocking), countones, cover, isunknown, onehot, onehot0,
@@ -1296,12 +1300,6 @@ prepended.  (If you don't know what this means, Verilator will do what you
 probably expect -- what C does. The default behavior of Verilog is
 different.)
 
-=head2 Generate Statements
-
-All instantiations and variables in generate blocks will be placed under
-hierarchy that has a name different from that required in the language
-specification.
-
 =head2 Generated Clocks
 
 Verilator attempts to deal with generated clocks correctly, however new
@@ -1356,6 +1354,35 @@ will give a width warning and wrap around the power-of-2 size.  For
 non-power-of-2 sizes, it will return a unspecified constant of the
 appropriate width.
 
+=head1 LANGUAGE KEYWORD LIMITATIONS
+
+This section describes specific limitations for each language keyword.
+
+=over 4
+
+=item always always_comb always_ff always_latch and assign begin buf case
+casex casez default defparam else end endcase endfunction endgenerate
+endmodule endspecify endtask final for function generate genvar if initial
+inout input integer localparam macromodule module nand negedge nor not or
+output parameter posedge reg scalared signed supply0 supply1 task tri
+vectored wire xnor xor
+
+Generally supported.
+
+=item specify specparam
+
+All specify blocks and timing checks are ignored.
+
+=item uwire
+
+Verilator does not perform warning checking on uwires, it treats the uwire
+keyword as if it were the normal wire keyword.
+
+=item $bits, $countones, $finish, $isunknown, $onehot, $onehot0, $readmemb,
+$readmemh, $signed, $stop, $time, $unsigned
+
+Generally supported.
+
 =item $display, $write, $fdisplay, $fwrite
 
 $display and friends must have a constant format string as the first
@@ -1376,12 +1403,23 @@ are 32 bits while FILE*s may be 64 bits, the descriptor must be stored in a
 reg [63:0] rather then an integer.  The define `verilator_file_descriptor in
 verilated.v can be used to hide this difference.
 
+=item $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal,
+$setup, $setuphold, $skew, $timeskew, $width
+
+All specify blocks and timing checks are ignored.
+
 =item $readmemb, $readmemh
 
 Read memory commands should work properly.  Note Verilator and the Verilog
 specification does not include support for readmem to multi-dimensional
 arrays.
 
+=item $realtime
+
+Treated as $time.
+
+=back
+
 =head1 ERRORS AND WARNINGS
 
 Warnings may be disabled in two ways.  First, when the warning is