diff --git a/Changes b/Changes
index 413c4a827..d6d0e1282 100644
--- a/Changes
+++ b/Changes
@@ -16,6 +16,8 @@ Verilator 4.217 devel
 * Primary inputs and outputs (VL_INW/VL_OUTW) now use VlWide type.
   In general this should be backward compatible, but may lead to some
   wrapper code needing changes.
+* Option --cdc is deprecated and is planned for removal,
+  file a bug if this is still being used.
 
 **Minor:**
 
diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst
index d2572c2e7..0099b8d9d 100644
--- a/docs/guide/deprecations.rst
+++ b/docs/guide/deprecations.rst
@@ -23,3 +23,7 @@ Configuration File -msg
 XML locations
   The XML "fl" attribute has been replaced with the "loc" attribute.  "fl"
   is planned for removal no sooner than January 2021.
+
+Option `--cdc`
+  The experimental `--cdc` option is believed to be generally unused and is
+  planned for removeal no sooner than January 2023.
diff --git a/src/V3Options.cpp b/src/V3Options.cpp
index d909aa25e..95e98bda4 100644
--- a/src/V3Options.cpp
+++ b/src/V3Options.cpp
@@ -718,6 +718,10 @@ void V3Options::notify() {
                 "--xml-only or --E option");
     }
 
+    if (cdc()) {
+        cmdfl->v3warn(DEPRECATED, "Option --cdc is deprecated and is planned for removal");
+    }
+
     if (m_build && (m_gmake || m_cmake)) {
         cmdfl->v3error("--make cannot be used together with --build. Suggest see manual");
     }
diff --git a/test_regress/t/t_cdc_async_bad.out b/test_regress/t/t_cdc_async_bad.out
index 64dd3783f..697a80fe0 100644
--- a/test_regress/t/t_cdc_async_bad.out
+++ b/test_regress/t/t_cdc_async_bad.out
@@ -1,8 +1,9 @@
+%Warning-DEPRECATED: Option --cdc is deprecated and is planned for removal
+                     ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest
+                     ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message.
 %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:28:21: Logic in path that feeds async reset, via signal: 't.rst2_bad_n'
    28 |    wire  rst2_bad_n = rst0_n | rst1_n;
       |                     ^
-                      ... For warning description see https://verilator.org/warn/CDCRSTLOGIC?v=latest
-                      ... Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message.
 %Warning-CDCRSTLOGIC:      See details in obj_vlt/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt
 %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53:21: Logic in path that feeds async reset, via signal: 't.rst6a_bad_n'
    53 |    wire rst6a_bad_n = rst6_bad_n ^ $c1("0");