From b4d2f6d2b15f173adc9b03e21e19f5bfa5d1205b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Bart=C5=82omiej=20Chmiel?= <bchmiel@antmicro.com>
Date: Fri, 21 Feb 2025 16:44:18 +0100
Subject: [PATCH] Tests: Add setuphold test
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Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com>
---
 test_regress/t/t_setuphold.py | 18 +++++++++++++
 test_regress/t/t_setuphold.v  | 49 +++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+)
 create mode 100755 test_regress/t/t_setuphold.py
 create mode 100644 test_regress/t/t_setuphold.v

diff --git a/test_regress/t/t_setuphold.py b/test_regress/t/t_setuphold.py
new file mode 100755
index 000000000..f989a35fb
--- /dev/null
+++ b/test_regress/t/t_setuphold.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile()
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_setuphold.v b/test_regress/t/t_setuphold.v
new file mode 100644
index 000000000..b5f86fc40
--- /dev/null
+++ b/test_regress/t/t_setuphold.v
@@ -0,0 +1,49 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2025 by Antmicro.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk,
+   d
+   );
+
+   input clk;
+   input d;
+   wire delayed_CLK;
+   wire delayed_D;
+   reg notifier;
+
+   logic[3:0] sh1 = 1;
+   logic[3:0] sh2 = 2;
+   logic[3:0] sh3 = 3;
+   logic[3:0] sh4 = 4;
+
+   int cyc = 0;
+
+   specify
+      $setuphold (posedge clk, negedge d, 0, 0, notifier,,, delayed_CLK, delayed_D);
+      $setuphold (posedge sh1, negedge sh3, 0, 0, notifier,,, sh2, sh4);
+      $setuphold (posedge clk, negedge d, 0, 0);
+   endspecify
+
+   initial begin
+      if (sh1 != sh2 || sh3 != sh4) begin
+         $stop;
+      end
+   end
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      $display("%d %d", clk, delayed_CLK);
+      if (delayed_CLK != clk || delayed_D != d) begin
+         $stop;
+      end
+      if (cyc == 10) begin
+         $display("*-* All Finished *-*");
+         $finish;
+      end
+   end
+endmodule