diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index 3b1269274..b5d113238 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -341,10 +341,10 @@ private: // Arrayed instants: one bit for each of the instants (each // assign is 1 pinwidth wide) if (m_cellRangep->littleEndian()) { - nodep->exprp()->v3warn( - LITENDIAN, - "Little endian cell range connecting to vector: MSB < LSB of cell range: " - << m_cellRangep->lsbConst() << ":" << m_cellRangep->msbConst()); + nodep->exprp()->v3warn(LITENDIAN, "Little endian cell range connecting to " + "vector: left < right of cell range: [" + << m_cellRangep->leftConst() << ":" + << m_cellRangep->rightConst() << "]"); } AstNode* exprp = nodep->exprp()->unlinkFrBack(); bool inputPin = nodep->modVarp()->isNonOutput(); diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 186697fe5..cfe7efb8d 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -777,8 +777,9 @@ private: // Note width() not set on range; use elementsConst() if (nodep->littleEndian() && !VN_IS(nodep->backp(), UnpackArrayDType) && !VN_IS(nodep->backp(), Cell)) { // For cells we warn in V3Inst - nodep->v3warn(LITENDIAN, "Little bit endian vector: MSB < LSB of bit range: " - << nodep->lsbConst() << ":" << nodep->msbConst()); + nodep->v3warn(LITENDIAN, "Little bit endian vector: left < right of bit range: [" + << nodep->leftConst() << ":" << nodep->rightConst() + << "]"); } } } diff --git a/test_regress/t/t_interface_array_nocolon_bad.out b/test_regress/t/t_interface_array_nocolon_bad.out index 6d528dd58..6779dde05 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.out +++ b/test_regress/t/t_interface_array_nocolon_bad.out @@ -1,17 +1,17 @@ -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:26:26: Little endian cell range connecting to vector: left < right of cell range: [0:2] : ... In instance t 26 | foo_intf foos [N] (.x(X)); | ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian cell range connecting to vector: left < right of cell range: [1:3] : ... In instance t 27 | foo_intf fool [1:3] (.x(X)); | ^ -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:30:26: Little endian cell range connecting to vector: left < right of cell range: [0:2] : ... In instance t 30 | foo_subm subs [N] (.x(X)); | ^ -%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:31:28: Little endian cell range connecting to vector: left < right of cell range: [1:3] : ... In instance t 31 | foo_subm subl [1:3] (.x(X)); | ^ diff --git a/test_regress/t/t_metacmt_onoff.out b/test_regress/t/t_metacmt_onoff.out index 5de179f75..7001223a5 100644 --- a/test_regress/t/t_metacmt_onoff.out +++ b/test_regress/t/t_metacmt_onoff.out @@ -1,9 +1,9 @@ -%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:8: Little bit endian vector: MSB < LSB of bit range: 0:1 +%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:8: Little bit endian vector: left < right of bit range: [0:1] : ... In instance t 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; | ^ ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. -%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:109: Little bit endian vector: MSB < LSB of bit range: 0:3 +%Warning-LITENDIAN: t/t_metacmt_onoff.v:8:109: Little bit endian vector: left < right of bit range: [0:3] : ... In instance t 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; | ^ diff --git a/test_regress/t/t_select_bad_msb.out b/test_regress/t/t_select_bad_msb.out index f31c7e096..69147264b 100644 --- a/test_regress/t/t_select_bad_msb.out +++ b/test_regress/t/t_select_bad_msb.out @@ -1,4 +1,4 @@ -%Warning-LITENDIAN: t/t_select_bad_msb.v:12:8: Little bit endian vector: MSB < LSB of bit range: 0:22 +%Warning-LITENDIAN: t/t_select_bad_msb.v:12:8: Little bit endian vector: left < right of bit range: [0:22] : ... In instance t 12 | reg [0:22] backwd; | ^