diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 06e8bfef5..894e610ea 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -2116,6 +2116,7 @@ private:
             nodep->v3error("Assigning to const ref variable: " << nodep->prettyNameQ());
         } else if (nodep->access().isWriteOrRW() && nodep->varp()->isConst() && !m_paramsOnly
                    && (!m_ftaskp || !m_ftaskp->isConstructor())
+                   && !VN_IS(m_procedurep, InitialAutomatic)
                    && !VN_IS(m_procedurep, InitialStatic)) {
             // Too loose, but need to allow our generated first assignment
             // Move this to a property of the AstInitial block
diff --git a/test_regress/t/t_class_const.pl b/test_regress/t/t_class_const.pl
new file mode 100755
index 000000000..1aa73f80a
--- /dev/null
+++ b/test_regress/t/t_class_const.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_class_const.v b/test_regress/t/t_class_const.v
new file mode 100644
index 000000000..5c30fa001
--- /dev/null
+++ b/test_regress/t/t_class_const.v
@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+class Cls;
+   const int aconst = 10;
+   static const int astatic = 20;
+endclass
+
+module t;
+   initial begin
+      Cls c = new;
+      if (c.aconst !== 10) $stop;
+      if (Cls::astatic !== 20) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule