From b26a19279a8df512b63788863a89d9fbb8d2e8bb Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 6 Apr 2025 23:42:49 -0400 Subject: [PATCH] Support simple `checker` blocks (#4066). --- Changes | 1 + src/V3AstNodeOther.h | 22 +++- src/V3AstNodes.cpp | 10 ++ src/verilog.y | 101 ++++++++++++++---- test_regress/t/t_checker.py | 18 ++++ test_regress/t/t_checker.v | 47 ++++++++ test_regress/t/t_checker_top.py | 16 +++ test_regress/t/t_checker_top.v | 11 ++ test_regress/t/t_checker_unsup.out | 50 +++------ test_regress/t/t_checker_unsup.v | 4 +- test_regress/t/t_constraint_json_only.out | 4 +- test_regress/t/t_dump_json.out | 6 +- test_regress/t/t_func_dotted_inl0.py | 3 +- test_regress/t/t_json_only_begin_hier.out | 8 +- test_regress/t/t_json_only_debugcheck.out | 4 +- test_regress/t/t_json_only_first.out | 8 +- test_regress/t/t_json_only_flat.out | 4 +- .../t/t_json_only_flat_no_inline_mod.out | 4 +- test_regress/t/t_json_only_flat_pub_mod.out | 4 +- test_regress/t/t_json_only_flat_vlvbound.out | 4 +- test_regress/t/t_json_only_output.out | 4 +- test_regress/t/t_json_only_tag.out | 4 +- test_regress/t/t_var_port_json_only.out | 32 +++--- 23 files changed, 262 insertions(+), 107 deletions(-) create mode 100755 test_regress/t/t_checker.py create mode 100644 test_regress/t/t_checker.v create mode 100755 test_regress/t/t_checker_top.py create mode 100644 test_regress/t/t_checker_top.v diff --git a/Changes b/Changes index 10e627476..a025bd983 100644 --- a/Changes +++ b/Changes @@ -19,6 +19,7 @@ Verilator 5.035 devel **Other:** +* Support simple `checker` blocks (#4066). [Srinivasan Venkataramanan] * Support force/release with a variable reference (#5721) (#5810). [Bartłomiej Chmiel, Antmicro Ltd.] * Support command-line overriding `define (#5900) (#5908). [Brian Li] * Support `$setuphold` (#5884). [Krzysztof Sychla] diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index e25f1502b..5070c34c3 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -2489,14 +2489,28 @@ public: }; class AstModule final : public AstNodeModule { // A module declaration - const bool m_isProgram; // Module represents a program + const bool m_isChecker = false; // Module represents a checker + const bool m_isProgram = false; // Module represents a program public: - AstModule(FileLine* fl, const string& name, bool program = false) + class Checker {}; // for constructor type-overload selection + class Program {}; // for constructor type-overload selection + AstModule(FileLine* fl, const string& name) + : ASTGEN_SUPER_Module(fl, name) {} + AstModule(FileLine* fl, const string& name, Checker) : ASTGEN_SUPER_Module(fl, name) - , m_isProgram{program} {} + , m_isChecker{true} {} + AstModule(FileLine* fl, const string& name, Program) + : ASTGEN_SUPER_Module(fl, name) + , m_isProgram{true} {} ASTGEN_MEMBERS_AstModule; - string verilogKwd() const override { return m_isProgram ? "program" : "module"; } + string verilogKwd() const override { + return m_isChecker ? "checker" : m_isProgram ? "program" : "module"; + } bool timescaleMatters() const override { return true; } + bool isChecker() const { return m_isChecker; } + bool isProgram() const { return m_isProgram; } + void dump(std::ostream& str) const override; + void dumpJson(std::ostream& str) const override; }; class AstNotFoundModule final : public AstNodeModule { // A missing module declaration diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 2ccf9fbe6..06760ebf6 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -2048,6 +2048,16 @@ void AstModportVarRef::dumpJson(std::ostream& str) const { dumpJsonStr(str, "direction", direction().ascii()); dumpJsonGen(str); } +void AstModule::dump(std::ostream& str) const { + this->AstNodeModule::dump(str); + if (isChecker()) str << " [CHECKER]"; + if (isProgram()) str << " [PROGRAM]"; +} +void AstModule::dumpJson(std::ostream& str) const { + dumpJsonBoolFunc(str, isChecker); + dumpJsonBoolFunc(str, isProgram); + dumpJsonGen(str); +} void AstPin::dump(std::ostream& str) const { this->AstNode::dump(str); if (modVarp()) { diff --git a/src/verilog.y b/src/verilog.y index 37de26266..c19b23b94 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1211,7 +1211,7 @@ description: // ==IEEE: description | interface_declaration { } | program_declaration { } | package_declaration { } - | package_item { if ($1) PARSEP->unitPackage($1->fileline())->addStmtsp($1); } + | package_itemTop { if ($1) PARSEP->unitPackage($1->fileline())->addStmtsp($1); } | bind_directive { if ($1) PARSEP->unitPackage($1->fileline())->addStmtsp($1); } //UNSUP config_declaration { } // // Verilator only @@ -1282,12 +1282,33 @@ package_item: // ==IEEE: package_item | sigAttrScope { $$ = nullptr; } ; +package_itemTop: // ==IEEE: package_item + + package_or_generate_item_declNoChecker { $$ = $1; } + | checker_declaration + { PARSEP->rootp()->addModulesp($1); + $$ = nullptr; } + | anonymous_program { $$ = $1; } + | package_export_declaration { $$ = $1; } + | timeunits_declaration { $$ = $1; } + | sigAttrScope { $$ = nullptr; } + ; + package_or_generate_item_declaration: // ==IEEE: package_or_generate_item_declaration + package_or_generate_item_declNoChecker { $$ = $1; } + | checker_declaration + { $1->v3warn(E_UNSUPPORTED, "Unsupported: 'checker' below unit-level"); + PARSEP->rootp()->addModulesp($1); + $$ = nullptr; } + ; + +package_or_generate_item_declNoChecker: net_declaration { $$ = $1; } | data_declaration { $$ = $1; } | task_declaration { $$ = $1; } | function_declaration { $$ = $1; } - | checker_declaration { $$ = $1; } + // // IEEE checker_declaration excluded, to handle Top, see other rules + // // checker_declaration | dpi_import_export { $$ = $1; } | extern_constraint_declaration { $$ = $1; } | class_declaration { $$ = $1; } @@ -1759,7 +1780,7 @@ program_declaration: // IEEE: program_declaration + program_nonansi_h pgmFront: yPROGRAM lifetimeE idAny/*new_program*/ - { $$ = new AstModule{$3, *$3, true}; + { $$ = new AstModule{$3, *$3, AstModule::Program{}}; $$->lifetime($2); $$->inLibrary(PARSEP->inLibrary() || $$->fileline()->celldefineOn()); $$->modTrace(GRAMMARP->allTracingOn($$->fileline())); @@ -2813,11 +2834,15 @@ module_or_generate_item_declaration: // ==IEEE: module_or_generate_it package_or_generate_item_declaration { $$ = $1; } | genvar_declaration { $$ = $1; } | clocking_declaration { $$ = $1; } - | yDEFAULT yCLOCKING idAny/*new-clocking_identifier*/ ';' - { $$ = nullptr; BBUNSUP($1, "Unsupported: default clocking identifier"); } + | modDefaultClocking { $$ = $1; } | defaultDisable { $$ = $1; } ; +modDefaultClocking: // IEEE: part of module_or_generate_item_declaration/checker_or_... + yDEFAULT yCLOCKING idAny/*new-clocking_identifier*/ ';' + { $$ = nullptr; BBUNSUP($1, "Unsupported: default clocking identifier"); } + ; + defaultDisable: // IEEE: part of module_/checker_or_generate_item_declaration yDEFAULT yDISABLE yIFF expr/*expression_or_dist*/ ';' { $$ = new AstDefaultDisable{$1, $4}; } @@ -6321,7 +6346,7 @@ property_port_itemFront: // IEEE: part of property_port_item/sequence_port_item { VARDTYPE($2); } ; -property_port_itemAssignment: // IEEE: part of property_port_item/sequence_port_item/checker_port_direction +property_port_itemAssignment: // IEEE: part of property_port_item/sequence_port_item id variable_dimensionListE { $$ = VARDONEA($1, *$1, $2, nullptr); } | id variable_dimensionListE '=' property_actual_arg @@ -7145,19 +7170,60 @@ checker_declaration: // ==IEEE: part of checker_declaration checkerFront: // IEEE: part of checker_declaration yCHECKER idAny/*checker_identifier*/ - { BBUNSUP($1, "Unsupported: checker"); - // TODO should be AstChecker not AstModule - $$ = new AstModule{$2, *$2}; + { $$ = new AstModule{$2, *$2, AstModule::Checker{}}; $$->modTrace(GRAMMARP->allTracingOn($$->fileline())); $$->timeunit(PARSEP->timeLastUnit()); $$->unconnectedDrive(PARSEP->unconnectedDrive()); SYMP->pushNew($$); } + | checkerFront sigAttrScope { $$ = $1; } ; checker_port_listE: // IEEE: [ ( [ checker_port_list ] ) ] - // // checker_port_item is basically the same as property_port_item, minus yLOCAL:: - // // Want to bet 1800-2012 adds local to checkers? - property_port_listE { $$ = $1; } + /* empty */ { $$ = nullptr; } + | '(' ')' { $$ = nullptr; } + | '(' + /*mid*/ { VARRESET_LIST(PORT); GRAMMARP->m_pinAnsi = true; } + /*cont*/ checker_port_list ')' + { $$ = $3; } + ; + +checker_port_list: // ==IEEE: checker_port_list + checker_port_item { $$ = $1; } + | checker_port_list ',' checker_port_item { $$ = addNextNull($1, $3); } + ; + +checker_port_item: // IEEE: checker_port_item + checker_port_itemFront checker_port_itemAssignment { $$ = $2; } + ; + +checker_port_itemFront: // IEEE: part of checker_port_item + checker_port_directionE property_formal_typeNoDt + { VARDTYPE($2); } + // // data_type_or_implicit + | checker_port_directionE data_type + { VARDTYPE($2); GRAMMARP->m_typedPropertyPort = true; } + | checker_port_directionE yVAR data_type + { VARDTYPE($3); GRAMMARP->m_typedPropertyPort = true; } + | checker_port_directionE yVAR implicit_typeE + { VARDTYPE($3); } + | checker_port_directionE implicit_typeE + { VARDTYPE($2); } + ; + +checker_port_directionE: // IEEE: [ checker_port_direction ] + /* empty */ { VARIO(INPUT); } + | yINPUT { VARIO(INPUT); } + | yOUTPUT { VARIO(OUTPUT); } + ; + +checker_port_itemAssignment: // IEEE: part of checker_port_direction + id variable_dimensionListE + { $$ = new AstPort{CRELINE(), PINNUMINC(), *$1}; + $$->addNext(VARDONEA($1, *$1, $2, nullptr)); } + | id variable_dimensionListE '=' property_actual_arg + { $$ = new AstPort{CRELINE(), PINNUMINC(), *$1}; + $$->addNext(VARDONEA($1, *$1, $2, $4)); + BBUNSUP($3, "Unsupported: checker port variable default value"); } ; checker_or_generate_itemListE: // IEEE: [{ checker_or_generate_itemList }] @@ -7182,22 +7248,19 @@ checker_or_generate_item: // ==IEEE: checker_or_generate_item ; checker_or_generate_item_declaration: // ==IEEE: checker_or_generate_item_declaration - data_declaration - { $$ = $1; BBUNSUP($1, "Unsupported: checker data declaration"); } + data_declaration { $$ = $1; } | yRAND data_declaration { $$ = $2; BBUNSUP($1, "Unsupported: checker rand"); } | function_declaration { $$ = $1; } | checker_declaration - { $$ = nullptr; BBUNSUP($1, "Unsupported: recursive checker"); } + { $$ = nullptr; BBUNSUP($1, "Unsupported: recursive 'checker'"); } | assertion_item_declaration { $$ = $1; } | covergroup_declaration { $$ = $1; } // // IEEE deprecated: overload_declaration | genvar_declaration { $$ = $1; } | clocking_declaration { $$ = $1; } - | yDEFAULT yCLOCKING idAny/*clocking_identifier*/ ';' { } - { $$ = nullptr; BBUNSUP($1, "Unsupported: checker default clocking"); } - | defaultDisable - { $$ = nullptr; BBUNSUP($1, "Unsupported: checker default disable iff"); } + | modDefaultClocking { $$ = $1; } + | defaultDisable { $$ = $1; } | ';' { $$ = nullptr; } ; diff --git a/test_regress/t/t_checker.py b/test_regress/t/t_checker.py new file mode 100755 index 000000000..4df7b8036 --- /dev/null +++ b/test_regress/t/t_checker.py @@ -0,0 +1,18 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('simulator') + +test.compile(verilator_flags2=["--assert"]) + +test.execute() + +test.passes() diff --git a/test_regress/t/t_checker.v b/test_regress/t/t_checker.v new file mode 100644 index 000000000..61d8671d4 --- /dev/null +++ b/test_regress/t/t_checker.v @@ -0,0 +1,47 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc = 0; + + bit failure; + mutex check_bus(cyc, clk, failure); + + integer cyc_d1; + always @ (posedge clk) cyc_d1 <= cyc; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d cyc_d1=0x%0x exp=%x failure=%x\n", + $time, cyc, cyc_d1, $onehot0(cyc), failure); +`endif + cyc <= cyc + 1; + if (cyc < 3) begin + end + else if (cyc < 90) begin + if (failure !== !$onehot0(cyc)) $stop; + end + else if (cyc == 99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +checker mutex (input logic [31:0] sig, input bit clk, output bit failure); + logic [31:0] last_sig; + assert property (@(negedge clk) $onehot0(sig)) + failure = 1'b0; else failure = 1'b1; + assert property (@(negedge clk) sig == last_sig + 1); + always_ff @(posedge clk) last_sig <= sig; +endchecker diff --git a/test_regress/t/t_checker_top.py b/test_regress/t/t_checker_top.py new file mode 100755 index 000000000..06f5a0953 --- /dev/null +++ b/test_regress/t/t_checker_top.py @@ -0,0 +1,16 @@ +#!/usr/bin/env python3 +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2024 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +import vltest_bootstrap + +test.scenarios('linter') + +test.lint(verilator_flags2=["--assert"]) + +test.passes() diff --git a/test_regress/t/t_checker_top.v b/test_regress/t/t_checker_top.v new file mode 100644 index 000000000..2c127e82c --- /dev/null +++ b/test_regress/t/t_checker_top.v @@ -0,0 +1,11 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2025 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +// Not super-sensical to have checker without module, but useful for --lint-only + +checker check_equal (bit clk, int a, int b); + assert property (@(posedge clk) a == b); +endchecker diff --git a/test_regress/t/t_checker_unsup.out b/test_regress/t/t_checker_unsup.out index b4bec9b52..47f44ac75 100644 --- a/test_regress/t/t_checker_unsup.out +++ b/test_regress/t/t_checker_unsup.out @@ -1,44 +1,20 @@ -%Error-UNSUPPORTED: t/t_checker_unsup.v:31:4: Unsupported: checker +%Error-UNSUPPORTED: t/t_checker_unsup.v:31:12: Unsupported: 'checker' below unit-level 31 | checker checker_in_module; - | ^~~~~~~ + | ^~~~~~~~~~~~~~~~~ ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest -%Error-UNSUPPORTED: t/t_checker_unsup.v:37:4: Unsupported: checker +%Error-UNSUPPORTED: t/t_checker_unsup.v:37:12: Unsupported: 'checker' below unit-level 37 | checker checker_in_pkg; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:41:1: Unsupported: checker - 41 | checker Chk - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:44:8: Unsupported: checker data declaration - 44 | bit clk; - | ^~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:45:8: Unsupported: checker data declaration - 45 | bit in; - | ^~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:46:8: Unsupported: checker data declaration - 46 | bit rst; - | ^~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:47:4: Unsupported: checker rand - 47 | rand bit randed; + | ^~~~~~~~~~~~~~ +%Error-UNSUPPORTED: t/t_checker_unsup.v:41:29: Unsupported: checker port variable default value + 41 | checker Chk(input defaulted = 1'b0); + | ^ +%Error-UNSUPPORTED: t/t_checker_unsup.v:45:4: Unsupported: checker rand + 45 | rand bit randed; | ^~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:49:8: Unsupported: checker data declaration - 49 | int counter = 0; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:51:8: Unsupported: checker data declaration - 51 | int ival; - | ^~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:61:8: Unsupported: checker data declaration - 61 | int ival2; - | ^~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:69:4: Unsupported: checker default clocking - 69 | default clocking clk; +%Error-UNSUPPORTED: t/t_checker_unsup.v:67:4: Unsupported: default clocking identifier + 67 | default clocking clk; | ^~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:70:4: Unsupported: checker default disable iff - 70 | default disable iff rst; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:72:4: Unsupported: checker - 72 | checker ChkChk; - | ^~~~~~~ -%Error-UNSUPPORTED: t/t_checker_unsup.v:72:12: Unsupported: recursive checker - 72 | checker ChkChk; +%Error-UNSUPPORTED: t/t_checker_unsup.v:70:12: Unsupported: recursive 'checker' + 70 | checker ChkChk; | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_checker_unsup.v b/test_regress/t/t_checker_unsup.v index fb8c0baa4..7d755b94d 100644 --- a/test_regress/t/t_checker_unsup.v +++ b/test_regress/t/t_checker_unsup.v @@ -38,9 +38,7 @@ package Pkg; endchecker endpackage -checker Chk - // UNSUP (input clk, int in) - ; +checker Chk(input defaulted = 1'b0); bit clk; bit in; bit rst; diff --git a/test_regress/t/t_constraint_json_only.out b/test_regress/t/t_constraint_json_only.out index 0c6bc002f..2c356ebbd 100644 --- a/test_regress/t/t_constraint_json_only.out +++ b/test_regress/t/t_constraint_json_only.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"t","addr":"(F)","loc":"d,67:8,67:9","origName":"t","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"t","addr":"(F)","loc":"d,67:8,67:9","isChecker":false,"isProgram":false,"origName":"t","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"p","addr":"(G)","loc":"d,69:11,69:12","dtypep":"(H)","origName":"p","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"VAR","dtypeName":"Packet","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"INITIAL","name":"","addr":"(I)","loc":"d,71:4,71:11","isSuspendable":false,"needProcess":false, @@ -77,7 +77,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(SB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(SB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(TB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(SB)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_dump_json.out b/test_regress/t/t_dump_json.out index e3e5031a9..0f42f85bc 100644 --- a/test_regress/t/t_dump_json.out +++ b/test_regress/t/t_dump_json.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"t","addr":"(E)","loc":"e,7:8,7:9","origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"t","addr":"(E)","loc":"e,7:8,7:9","isChecker":false,"isProgram":false,"origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"PORT","name":"clk","addr":"(F)","loc":"e,9:4,9:7","exprp": []}, {"type":"VAR","name":"clk","addr":"(G)","loc":"e,11:10,11:13","dtypep":"UNLINKED","origName":"clk","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"NONE","varType":"PORT","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED", @@ -431,7 +431,7 @@ ]} ]} ],"activesp": []}, - {"type":"MODULE","name":"Test","addr":"(PB)","loc":"e,66:8,66:12","origName":"Test","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"Test","addr":"(PB)","loc":"e,66:8,66:12","isChecker":false,"isProgram":false,"origName":"Test","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"PORT","name":"out","addr":"(YG)","loc":"e,68:4,68:7","exprp": []}, {"type":"PORT","name":"clk","addr":"(ZG)","loc":"e,70:4,70:7","exprp": []}, @@ -540,7 +540,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(LI)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(LI)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(MI)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(LI)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_func_dotted_inl0.py b/test_regress/t/t_func_dotted_inl0.py index 3c2548ae7..9d666e421 100755 --- a/test_regress/t/t_func_dotted_inl0.py +++ b/test_regress/t/t_func_dotted_inl0.py @@ -19,7 +19,8 @@ test.compile(v_flags2=['--no-json-edit-nums', '+define+ATTRIBUTES', '+define+NOU if test.vlt_all: test.file_grep( out_filename, - r'{"type":"MODULE","name":"ma",.*"loc":"\w,84:[^"]*",.*"origName":"ma",.*,"modPublic":true') + r'{"type":"MODULE","name":"ma",.*"loc":"\w,84:[^"]*",.*"origName":"ma",.*,"modPublic":true' + ) test.file_grep( out_filename, r'{"type":"MODULE","name":"mb",.*"loc":"\w,99:[^"]*",.*"origName":"mb",.*"modPublic":true') diff --git a/test_regress/t/t_json_only_begin_hier.out b/test_regress/t/t_json_only_begin_hier.out index 467f43d45..9707df322 100644 --- a/test_regress/t/t_json_only_begin_hier.out +++ b/test_regress/t/t_json_only_begin_hier.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","origName":"test","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"test","addr":"(E)","loc":"d,22:8,22:12","isChecker":false,"isProgram":false,"origName":"test","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"N","addr":"(F)","loc":"d,24:12,24:13","dtypep":"(G)","origName":"N","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":true,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"GENVAR","dtypeName":"integer","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"BEGIN","name":"FOR_GENERATE","addr":"(H)","loc":"d,25:14,25:17","generate":true,"genfor":false,"implied":true,"needProcess":false,"unnamed":false,"genforp": [],"stmtsp": []}, @@ -23,7 +23,7 @@ {"type":"CELL","name":"submod_3","addr":"(S)","loc":"d,31:21,31:29","origName":"submod_3","recursive":false,"modp":"(K)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ]} ],"activesp": []}, - {"type":"MODULE","name":"submod","addr":"(K)","loc":"d,10:8,10:14","origName":"submod","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"submod","addr":"(K)","loc":"d,10:8,10:14","isChecker":false,"isProgram":false,"origName":"submod","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"BEGIN","name":"submod_gen","addr":"(T)","loc":"d,12:19,12:29","generate":true,"genfor":false,"implied":false,"needProcess":false,"unnamed":false,"genforp": [], "stmtsp": [ @@ -36,7 +36,7 @@ ]}, {"type":"CELL","name":"submod_l0","addr":"(AB)","loc":"d,19:13,19:22","origName":"submod_l0","recursive":false,"modp":"(Y)","pinsp": [],"paramsp": [],"rangep": [],"intfRefsp": []} ],"activesp": []}, - {"type":"MODULE","name":"submod2","addr":"(Y)","loc":"d,7:8,7:15","origName":"submod2","level":4,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],"stmtsp": [],"activesp": []} + {"type":"MODULE","name":"submod2","addr":"(Y)","loc":"d,7:8,7:15","isChecker":false,"isProgram":false,"origName":"submod2","level":4,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [],"stmtsp": [],"activesp": []} ],"filesp": [], "miscsp": [ {"type":"TYPETABLE","name":"","addr":"(C)","loc":"a,0:0,0:0","constraintRefp":"UNLINKED","emptyQueuep":"UNLINKED","queueIndexp":"UNLINKED","streamp":"UNLINKED","voidp":"UNLINKED", @@ -46,7 +46,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(BB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(CB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BB)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_json_only_debugcheck.out b/test_regress/t/t_json_only_debugcheck.out index e279ccb57..d5b880cbb 100644 --- a/test_regress/t/t_json_only_debugcheck.out +++ b/test_regress/t/t_json_only_debugcheck.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"(E)","stdPackagep":"UNLINKED","evalp":"(F)","evalNbap":"(G)","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(H)", "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(I)","loc":"d,11:8,11:9","origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"$root","addr":"(I)","loc":"d,11:8,11:9","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"clk","addr":"(J)","loc":"d,15:10,15:13","dtypep":"(K)","origName":"clk","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":true,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"clker","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"t.e","addr":"(L)","loc":"d,24:9,24:10","dtypep":"(M)","origName":"e","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"VAR","dtypeName":"my_t","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, @@ -2987,7 +2987,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(URB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(URB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"TOP","addr":"(VRB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(URB)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_json_only_first.out b/test_regress/t/t_json_only_first.out index c23a7530e..af1d36e8b 100644 --- a/test_regress/t/t_json_only_first.out +++ b/test_regress/t/t_json_only_first.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"t","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"origName":"t","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"q","addr":"(F)","loc":"d,15:22,15:23","dtypep":"(G)","origName":"q","isSc":false,"isPrimaryIO":false,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"clk","addr":"(H)","loc":"d,13:10,13:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, @@ -37,7 +37,7 @@ ]} ],"paramsp": [],"rangep": [],"intfRefsp": []} ],"activesp": []}, - {"type":"MODULE","name":"mod2","addr":"(X)","loc":"d,46:8,46:12","origName":"mod2","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mod2","addr":"(X)","loc":"d,46:8,46:12","isChecker":false,"isProgram":false,"origName":"mod2","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"clk","addr":"(FB)","loc":"d,48:10,48:13","dtypep":"(I)","origName":"clk","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"d","addr":"(Z)","loc":"d,49:16,49:17","dtypep":"(G)","origName":"d","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, @@ -50,7 +50,7 @@ {"type":"VARREF","name":"q","addr":"(JB)","loc":"d,53:13,53:14","dtypep":"(G)","access":"WR","varp":"(CB)","varScopep":"UNLINKED","classOrPackagep":"UNLINKED"} ],"timingControlp": [],"strengthSpecp": []} ],"activesp": []}, - {"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,31:8,31:12","origName":"mod1","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"mod1__W4","addr":"(M)","loc":"d,31:8,31:12","isChecker":false,"isProgram":false,"origName":"mod1","level":3,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"WIDTH","addr":"(KB)","loc":"d,32:15,32:20","dtypep":"(LB)","origName":"WIDTH","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"GPARAM","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":true,"isParam":true,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [], "valuep": [ @@ -93,7 +93,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(WB)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(WB)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(XB)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(WB)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_json_only_flat.out b/test_regress/t/t_json_only_flat.out index 91cdfc1a6..fec83ce8c 100644 --- a/test_regress/t/t_json_only_flat.out +++ b/test_regress/t/t_json_only_flat.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:9","origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"q","addr":"(G)","loc":"d,15:22,15:23","dtypep":"(H)","origName":"q","isSc":false,"isPrimaryIO":true,"direction":"OUTPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"WIRE","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"clk","addr":"(I)","loc":"d,13:10,13:13","dtypep":"(J)","origName":"clk","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"clker","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, @@ -146,7 +146,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(BD)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(BD)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(CD)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(BD)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_json_only_flat_no_inline_mod.out b/test_regress/t/t_json_only_flat_no_inline_mod.out index 147530c78..23e7e78cd 100644 --- a/test_regress/t/t_json_only_flat_no_inline_mod.out +++ b/test_regress/t/t_json_only_flat_no_inline_mod.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, @@ -39,7 +39,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(V)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(U)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_json_only_flat_pub_mod.out b/test_regress/t/t_json_only_flat_pub_mod.out index 147530c78..23e7e78cd 100644 --- a/test_regress/t/t_json_only_flat_pub_mod.out +++ b/test_regress/t/t_json_only_flat_pub_mod.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,11:8,11:11","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"i_clk","addr":"(G)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"top.i_clk","addr":"(I)","loc":"d,11:24,11:29","dtypep":"(H)","origName":"i_clk","isSc":false,"isPrimaryIO":false,"direction":"NONE","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, @@ -39,7 +39,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(U)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(V)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(U)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_json_only_flat_vlvbound.out b/test_regress/t/t_json_only_flat_vlvbound.out index 9c163a579..6200acfad 100644 --- a/test_regress/t/t_json_only_flat_vlvbound.out +++ b/test_regress/t/t_json_only_flat_vlvbound.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"(E)", "modulesp": [ - {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:21","origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"$root","addr":"(F)","loc":"d,7:8,7:21","isChecker":false,"isProgram":false,"origName":"$root","level":1,"modPublic":true,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"i_a","addr":"(G)","loc":"d,9:25,9:28","dtypep":"(H)","origName":"i_a","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"i_b","addr":"(I)","loc":"d,10:25,10:28","dtypep":"(H)","origName":"i_b","isSc":false,"isPrimaryIO":true,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":true,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, @@ -331,7 +331,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(WF)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(WF)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(XF)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(WF)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_json_only_output.out b/test_regress/t/t_json_only_output.out index d900c682c..aa1b3275a 100644 --- a/test_regress/t/t_json_only_output.out +++ b/test_regress/t/t_json_only_output.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","origName":"m","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"m","addr":"(E)","loc":"d,7:8,7:9","isChecker":false,"isProgram":false,"origName":"m","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"clk","addr":"(F)","loc":"d,8:10,8:13","dtypep":"(G)","origName":"clk","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []} ],"activesp": []} @@ -12,7 +12,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - {"type":"MODULE","name":"@CONST-POOL@","addr":"(H)","loc":"a,0:0,0:0","origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], + {"type":"MODULE","name":"@CONST-POOL@","addr":"(H)","loc":"a,0:0,0:0","isChecker":false,"isProgram":false,"origName":"@CONST-POOL@","level":0,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"NONE","inlinesp": [], "stmtsp": [ {"type":"SCOPE","name":"@CONST-POOL@","addr":"(I)","loc":"a,0:0,0:0","aboveScopep":"UNLINKED","aboveCellp":"UNLINKED","modp":"(H)","varsp": [],"blocksp": [],"inlinesp": []} ],"activesp": []} diff --git a/test_regress/t/t_json_only_tag.out b/test_regress/t/t_json_only_tag.out index 0c74a6e71..78ce2196e 100644 --- a/test_regress/t/t_json_only_tag.out +++ b/test_regress/t/t_json_only_tag.out @@ -1,6 +1,6 @@ {"type":"NETLIST","name":"$root","addr":"(B)","loc":"a,0:0,0:0","timeunit":"1ps","timeprecision":"1ps","typeTablep":"(C)","constPoolp":"(D)","dollarUnitPkgp":"UNLINKED","stdPackagep":"UNLINKED","evalp":"UNLINKED","evalNbap":"UNLINKED","dpiExportTriggerp":"UNLINKED","delaySchedulerp":"UNLINKED","nbaEventp":"UNLINKED","nbaEventTriggerp":"UNLINKED","topScopep":"UNLINKED", "modulesp": [ - {"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","origName":"m","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], + {"type":"MODULE","name":"m","addr":"(E)","loc":"d,12:8,12:9","isChecker":false,"isProgram":false,"origName":"m","level":2,"modPublic":false,"inLibrary":false,"dead":false,"recursiveClone":false,"recursive":false,"timeunit":"1ps","inlinesp": [], "stmtsp": [ {"type":"VAR","name":"clk_ip","addr":"(F)","loc":"d,14:11,14:17","dtypep":"(G)","origName":"clk_ip","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, {"type":"VAR","name":"rst_ip","addr":"(H)","loc":"d,15:11,15:17","dtypep":"(G)","origName":"rst_ip","isSc":false,"isPrimaryIO":false,"direction":"INPUT","isConst":false,"isPullup":false,"isPulldown":false,"isUsedClock":false,"isSigPublic":false,"isLatched":false,"isUsedLoopIdx":false,"noReset":false,"attrIsolateAssign":false,"attrFileDescr":false,"isDpiOpenArray":false,"isFuncReturn":false,"isFuncLocal":false,"attrClocker":"UNKNOWN","lifetime":"VSTATIC","varType":"PORT","dtypeName":"logic","isSigUserRdPublic":false,"isSigUserRWPublic":false,"isGParam":false,"isParam":false,"attrScBv":false,"attrSFormat":false,"ignorePostWrite":false,"ignoreSchedWrite":false,"sensIfacep":"UNLINKED","childDTypep": [],"delayp": [],"valuep": [],"attrsp": []}, @@ -91,7 +91,7 @@ ]}, {"type":"CONSTPOOL","name":"","addr":"(D)","loc":"a,0:0,0:0", "modulep": [ - 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