From b1ce6bd5cc42a85d8226915dcc85405fd6ca462a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 5 Nov 2009 19:57:31 -0500 Subject: [PATCH] Support "var" --- Changes | 2 +- bin/verilator | 14 ++++----- src/verilog.l | 2 +- src/verilog.y | 59 +++++++++++++++++++++++------------- test_regress/t/t_var_types.v | 5 +++ 5 files changed, 52 insertions(+), 30 deletions(-) diff --git a/Changes b/Changes index 5c402f84d..58b2bd1b2 100644 --- a/Changes +++ b/Changes @@ -5,7 +5,7 @@ indicates the contributor was also the author of the fix; Thanks! * Verilator 3.7** -*** Support byte, shortint, int, longint in variables, parameters and +*** Support byte, shortint, int, longint and var in variables, parameters and functions. *** Support void functions. diff --git a/bin/verilator b/bin/verilator index 8a42d7de7..00ff65097 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1700,13 +1700,13 @@ This section describes specific limitations for each language keyword. Fully supported. -=item int, shortint, longint, always, always_comb, always_ff, always_latch, -and, assign, begin, buf, byte, case, casex, casez, default, defparam, -do-while, else, end, endcase, endfunction, endgenerate, endmodule, -endspecify, endtask, final, for, function, generate, genvar, if, initial, -inout, input, integer, logic, localparam, macromodule, module, nand, -negedge, nor, not, or, output, parameter, posedge, reg, scalared, signed, -supply0, supply1, task, tri, vectored, while, wire, xnor, xor +=item always, always_comb, always_ff, always_latch, and, assign, begin, +buf, byte, case, casex, casez, default, defparam, do-while, else, end, +endcase, endfunction, endgenerate, endmodule, endspecify, endtask, final, +for, function, generate, genvar, if, initial, inout, input, int, integer, +localparam, logic, longint, macromodule, module, nand, negedge, nor, not, +or, output, parameter, posedge, reg, scalared, shortint, signed, supply0, +supply1, task, tri, var, vectored, while, wire, xnor, xor Generally supported. diff --git a/src/verilog.l b/src/verilog.l index f39fd4708..82669c786 100644 --- a/src/verilog.l +++ b/src/verilog.l @@ -379,6 +379,7 @@ escid \\[^ \t\f\r\n]+ "timeprecision" { FL; return yTIMEPRECISION; } "timeunit" { FL; return yTIMEUNIT; } "unique" { FL; return yUNIQUE; } + "var" { FL; return yVAR; } "void" { FL; return yVOID; } /* Generic unsupported warnings */ /* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */ @@ -445,7 +446,6 @@ escid \\[^ \t\f\r\n]+ "throughout" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "type" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "typedef" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } - "var" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "virtual" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "wait_order" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } "wildcard" { yyerrorf("Unsupported: SystemVerilog 2005 reserved word not implemented: %s",yytext); } diff --git a/src/verilog.y b/src/verilog.y index 5bc7d56f7..f862a2a6e 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -298,6 +298,7 @@ class AstSenTree; %token yTRUE "true" %token yUNIQUE "unique" %token yUNSIGNED "unsigned" +%token yVAR "var" %token yVECTORED "vectored" %token yVOID "void" %token yWHILE "while" @@ -650,16 +651,25 @@ port: // ==IEEE: port //UNSUP portDirNetE signingE rangeList '.' portSig '(' portAssignExprE ')' sigAttrListE { UNSUP } //UNSUP portDirNetE /*implicit*/ '.' portSig '(' portAssignExprE ')' sigAttrListE { UNSUP } // - portDirNetE data_type portSig variable_dimensionListE sigAttrListE { $$=$3; VARDTYPE($2); $$->addNextNull(VARDONEP($$,$4,$5)); } - //UNSUP portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE { $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); } - //UNSUP portDirNetE yVAR implicit_type portSig variable_dimensionListE sigAttrListE { $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); } - | portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE { $$=$4; VARDTYPE(GRAMMARP->addRange(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2), $3)); $$->addNextNull(VARDONEP($$,$5,$6)); } - | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE { $$=$2; /*VARDTYPE-same*/ $$->addNextNull(VARDONEP($$,$3,$4)); } + portDirNetE data_type portSig variable_dimensionListE sigAttrListE + { $$=$3; VARDTYPE($2); $$->addNextNull(VARDONEP($$,$4,$5)); } + | portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE + { $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); } + | portDirNetE yVAR implicit_type portSig variable_dimensionListE sigAttrListE + { $$=$4; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); } + | portDirNetE signingE rangeList portSig variable_dimensionListE sigAttrListE + { $$=$4; VARDTYPE(GRAMMARP->addRange(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2), $3)); $$->addNextNull(VARDONEP($$,$5,$6)); } + | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE + { $$=$2; /*VARDTYPE-same*/ $$->addNextNull(VARDONEP($$,$3,$4)); } // - | portDirNetE data_type portSig variable_dimensionListE sigAttrListE '=' constExpr { $$=$3; VARDTYPE($2); $$->addNextNull(VARDONEP($$,$4,$5)); $$->addNextNull(GRAMMARP->newVarInit($6,$$,$7)); } - //UNSUP portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE '=' constExpr { $$=$3; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); $$->addNextNull(GRAMMARP->newVarInit($7,$$,$8)); } - //UNSUP portDirNetE yVAR implicit_type portSig variable_dimensionListE sigAttrListE '=' constExpr { $$=$3; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); $$->addNextNull(GRAMMARP->newVarInit($7,$$,$8)); } - | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE '=' constExpr { $$=$3; /*VARDTYPE-same*/ $$->addNextNull(VARDONEP($$,$3,$4)); $$->addNextNull(GRAMMARP->newVarInit($5,$$,$6)); } + | portDirNetE data_type portSig variable_dimensionListE sigAttrListE '=' constExpr + { $$=$3; VARDTYPE($2); $$->addNextNull(VARDONEP($$,$4,$5)); $$->addNextNull(GRAMMARP->newVarInit($6,$$,$7)); } + | portDirNetE yVAR data_type portSig variable_dimensionListE sigAttrListE '=' constExpr + { $$=$3; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); $$->addNextNull(GRAMMARP->newVarInit($7,$$,$8)); } + | portDirNetE yVAR implicit_type portSig variable_dimensionListE sigAttrListE '=' constExpr + { $$=$3; VARDTYPE($3); $$->addNextNull(VARDONEP($$,$5,$6)); $$->addNextNull(GRAMMARP->newVarInit($7,$$,$8)); } + | portDirNetE /*implicit*/ portSig variable_dimensionListE sigAttrListE '=' constExpr + { $$=$3; /*VARDTYPE-same*/ $$->addNextNull(VARDONEP($$,$3,$4)); $$->addNextNull(GRAMMARP->newVarInit($5,$$,$6)); } ; portDirNetE: // IEEE: part of port, optional net type and/or direction @@ -855,8 +865,10 @@ port_declaration: // ==IEEE: port_declaration // // IEEE: ref_declaration port_directionReset port_declNetE data_type { VARDTYPE($3); } list_of_variable_decl_assignments { $$ = $5; } - //UNSUP port_directionReset port_declNetE yVAR data_type { VARDTYPE($4); } list_of_variable_decl_assignments { $$ = $6; } - //UNSUP port_directionReset port_declNetE yVAR implicit_type { VARDTYPE($4); } list_of_variable_decl_assignments { $$ = $6; } + | port_directionReset port_declNetE yVAR data_type { VARDTYPE($4); } + list_of_variable_decl_assignments { $$ = $6; } + | port_directionReset port_declNetE yVAR implicit_type { VARDTYPE($4); } + list_of_variable_decl_assignments { $$ = $6; } | port_directionReset port_declNetE signingE rangeList { VARDTYPE(GRAMMARP->addRange(new AstBasicDType($4->fileline(), LOGIC_IMPLICIT, $3),$4)); } list_of_variable_decl_assignments { $$ = $6; } | port_directionReset port_declNetE signing { VARDTYPE(new AstBasicDType($3, LOGIC_IMPLICIT, $3)); } @@ -871,8 +883,8 @@ tf_port_declaration: // ==IEEE: tf_port_declaration // port_directionReset data_type { VARDTYPE($2); } list_of_tf_variable_identifiers ';' { $$ = $4; } | port_directionReset implicit_type { VARDTYPE($2); } list_of_tf_variable_identifiers ';' { $$ = $4; } - //UNSUP port_directionReset yVAR data_type { VARDTYPE($3); } list_of_tf_variable_identifiers ';' { $$ = $5; } - //UNSUP port_directionReset yVAR implicit_type { VARDTYPE($3); } list_of_tf_variable_identifiers ';' { $$ = $5; } + | port_directionReset yVAR data_type { VARDTYPE($3); } list_of_tf_variable_identifiers ';' { $$ = $5; } + | port_directionReset yVAR implicit_type { VARDTYPE($3); } list_of_tf_variable_identifiers ';' { $$ = $5; } ; integer_atom_type: // ==IEEE: integer_atom_type @@ -1025,17 +1037,22 @@ data_declarationVar: // IEEE: part of data_declaration data_declarationVarFront: // IEEE: part of data_declaration // // implicit_type expanded into /*empty*/ or "signingE rangeList" - //UNSUP constE yVAR lifetimeE data_type { /*VARRESET-in-ddVar*/ VARDECL("var"); VARDTYPE(SPACED($1,$4)); } - //UNSUP constE yVAR lifetimeE { /*VARRESET-in-ddVar*/ VARDECL("var"); VARDTYPE($1); } - //UNSUP constE yVAR lifetimeE signingE rangeList { /*VARRESET-in-ddVar*/ VARDECL("var"); VARDTYPE(SPACED($1,SPACED($4,$5))); } + constE yVAR lifetimeE data_type { /*VARRESET-in-ddVar*/ VARDTYPE($4); } + | constE yVAR lifetimeE { /*VARRESET-in-ddVar*/ VARDTYPE(new AstBasicDType($2, LOGIC_IMPLICIT)); } + | constE yVAR lifetimeE signingE rangeList { /*VARRESET-in-ddVar*/ VARDTYPE(GRAMMARP->addRange(new AstBasicDType($2, LOGIC_IMPLICIT, $4),$5)); } // // // Expanded: "constE lifetimeE data_type" - /**/ data_type { /*VARRESET-in-ddVar*/ VARDTYPE($1); } + | /**/ data_type { /*VARRESET-in-ddVar*/ VARDTYPE($1); } | /**/ lifetime data_type { /*VARRESET-in-ddVar*/ VARDTYPE($2); } //UNSUP yCONST__ETC lifetimeE data_type { /*VARRESET-in-ddVar*/ VARDTYPE($3); } // // = class_new is in variable_decl_assignment ; +constE: // IEEE: part of data_declaration + /* empty */ { } + //UNSUP yCONST__ETC { UNSUP } + ; + implicit_type: // IEEE: part of *data_type_or_implicit // // Also expanded in data_declaration /* empty */ { $$ = NULL; } @@ -1929,15 +1946,15 @@ tf_port_itemFront: // IEEE: part of tf_port_item, which has the data type data_type { VARDTYPE($1); } | signingE rangeList { VARDTYPE(GRAMMARP->addRange(new AstBasicDType($2->fileline(), LOGIC_IMPLICIT, $1), $2)); } | signing { VARDTYPE(new AstBasicDType($1, LOGIC_IMPLICIT, $1)); } - //UNSUP yVAR data_type { VARDTYPE($2); } - //UNSUP yVAR implicit_type { VARDTYPE($2); } + | yVAR data_type { VARDTYPE($2); } + | yVAR implicit_type { VARDTYPE($2); } // | tf_port_itemDir /*implicit*/ { VARDTYPE(NULL); /*default_nettype-see spec*/ } | tf_port_itemDir data_type { VARDTYPE($2); } | tf_port_itemDir signingE rangeList { VARDTYPE(GRAMMARP->addRange(new AstBasicDType($3->fileline(), LOGIC_IMPLICIT, $2),$3)); } | tf_port_itemDir signing { VARDTYPE(new AstBasicDType($2, LOGIC_IMPLICIT, $2)); } - //UNSUP tf_port_itemDir yVAR data_type { VARDTYPE($3); } - //UNSUP tf_port_itemDir yVAR implicit_type { VARDTYPE($3); } + | tf_port_itemDir yVAR data_type { VARDTYPE($3); } + | tf_port_itemDir yVAR implicit_type { VARDTYPE($3); } ; tf_port_itemDir: // IEEE: part of tf_port_item, direction diff --git a/test_regress/t/t_var_types.v b/test_regress/t/t_var_types.v index 7ac3538b2..ebdf29256 100644 --- a/test_regress/t/t_var_types.v +++ b/test_regress/t/t_var_types.v @@ -27,6 +27,11 @@ module t (/*AUTOARG*/); //UNSUP real d_real; //UNSUP realtime d_realtime; + // Declarations using var + var byte v_b; + var [2:0] v_b3; + var signed [2:0] v_bs; + // verilator lint_off WIDTH localparam p_implicit = {96{1'b1}}; localparam [89:0] p_explicit = {96{1'b1}};