From b19dd49fc9ba204639a443250fff26ddf95d86e5 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 7 Sep 2009 15:56:20 -0400
Subject: [PATCH] Add test forgot to add earlier

---
 test_regress/t/t_var_rsvd.pl     | 18 ++++++++++++++++++
 test_regress/t/t_var_rsvd.v      | 23 +++++++++++++++++++++++
 test_regress/t/t_var_rsvd_bad.pl | 19 +++++++++++++++++++
 test_regress/t/t_var_rsvd_bad.v  | 18 ++++++++++++++++++
 4 files changed, 78 insertions(+)
 create mode 100755 test_regress/t/t_var_rsvd.pl
 create mode 100644 test_regress/t/t_var_rsvd.v
 create mode 100755 test_regress/t/t_var_rsvd_bad.pl
 create mode 100644 test_regress/t/t_var_rsvd_bad.v

diff --git a/test_regress/t/t_var_rsvd.pl b/test_regress/t/t_var_rsvd.pl
new file mode 100755
index 000000000..7058e622f
--- /dev/null
+++ b/test_regress/t/t_var_rsvd.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_var_rsvd.v b/test_regress/t/t_var_rsvd.v
new file mode 100644
index 000000000..1f3b0b5b0
--- /dev/null
+++ b/test_regress/t/t_var_rsvd.v
@@ -0,0 +1,23 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2005 by Wilson Snyder.
+
+// verilator lint_off SYMRSVDWORD
+
+module t (/*AUTOARG*/
+   // Inputs
+   bool
+   );
+
+   input bool;	// BAD
+
+   reg  vector;	// OK, as not public
+   reg  switch /*verilator public*/;	// Bad
+
+   initial begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
diff --git a/test_regress/t/t_var_rsvd_bad.pl b/test_regress/t/t_var_rsvd_bad.pl
new file mode 100755
index 000000000..a18f4edfa
--- /dev/null
+++ b/test_regress/t/t_var_rsvd_bad.pl
@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 fails=>$Self->{v3},
+	 expect=>
+q{%Error-SYMRSVDWORD: t/t_var_rsvd_bad.v:\d+: Symbol matches C\+\+ common word: 'bool'
+%Error-SYMRSVDWORD: t/t_var_rsvd_bad.v:\d+: Symbol matches C\+\+ reserved word: 'switch'
+%Error: Exiting due to.*},
+	 );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_var_rsvd_bad.v b/test_regress/t/t_var_rsvd_bad.v
new file mode 100644
index 000000000..48492614b
--- /dev/null
+++ b/test_regress/t/t_var_rsvd_bad.v
@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2005 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   bool
+   );
+
+   input bool;	// BAD
+
+   reg  vector;	// OK, as not public
+   reg  switch /*verilator public*/;	// Bad
+
+   initial $stop;
+
+endmodule