diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp
index cfa58e3ed..162b0b201 100644
--- a/src/V3Begin.cpp
+++ b/src/V3Begin.cpp
@@ -292,6 +292,14 @@ class BeginVisitor final : public VNVisitor {
             UINFO(9, "    rescope to " << nodep);
         }
     }
+    void visit(AstNodeFTaskRef* nodep) override {
+        UINFO(9, "   FTASKREF " << nodep);
+        if (m_namedScope != "" && nodep->inlinedDots() == "" && !m_ftaskp) {
+            nodep->inlinedDots(m_namedScope);
+            UINFO(9, "    rescope to " << nodep);
+        }
+        iterateChildren(nodep);
+    }
     void visit(AstScopeName* nodep) override {
         // If there's a %m in the display text, we add a special node that will contain the name()
         // Similar code in V3Inline
diff --git a/test_regress/t/t_interface_gen14.py b/test_regress/t/t_interface_gen14.py
new file mode 100755
index 000000000..c6e56559a
--- /dev/null
+++ b/test_regress/t/t_interface_gen14.py
@@ -0,0 +1,18 @@
+#!/usr/bin/env python3
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2025 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+import vltest_bootstrap
+
+test.scenarios('simulator')
+
+test.compile(verilator_flags2=["--binary"])
+
+test.execute()
+
+test.passes()
diff --git a/test_regress/t/t_interface_gen14.v b/test_regress/t/t_interface_gen14.v
new file mode 100644
index 000000000..c79823019
--- /dev/null
+++ b/test_regress/t/t_interface_gen14.v
@@ -0,0 +1,48 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+// SPDX-License-Identifier: CC0-1.0
+
+`define stop $stop
+`define checkd(gotv,expv) \
+  do if ((gotv) !== (expv)) begin \
+    $write("%%Error: %s:%0d:  got=%0d exp=%0d\n", \
+            `__FILE__,`__LINE__, (gotv), (expv)); \
+    `stop; \
+  end while(0);
+
+interface a_if #(parameter int a_param=0)();
+  logic[a_param-1:0] x;
+
+  function void to_if(input logic[a_param-1:0] x_in);
+    x = x_in;
+  endfunction
+  function logic[a_param-1:0] from_if();
+    return x;
+  endfunction
+endinterface
+
+module tb();
+  genvar a;
+
+  generate
+    for (a=1; a<3; a++) begin : gen_a
+      a_if #(.a_param(a)) a_if_a();
+      initial begin
+        #1;
+        a_if_a.to_if(a);
+      end
+    end
+  endgenerate
+
+  initial begin
+    #1;
+    #1;
+    `checkd(gen_a[1].a_if_a.from_if(), 'h1);
+    `checkd(gen_a[2].a_if_a.from_if(), 'h2);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+
+endmodule