From afb8428db4a3b8709c67abc30e37a318977a0a34 Mon Sep 17 00:00:00 2001 From: Krzysztof Bieganski Date: Sat, 7 Sep 2024 00:13:52 +0200 Subject: [PATCH] Support IEEE-compliant intra-assign delays (#3711) (#5441) --- src/V3AstNodeOther.h | 1 + src/V3AstNodes.cpp | 9 + src/V3ParseGrammar.cpp | 3 +- src/V3SchedTiming.cpp | 10 +- src/V3Timing.cpp | 177 +- src/V3Tristate.cpp | 5 +- src/verilog.y | 12 +- test_regress/t/t_net_delay.out | 34 +- test_regress/t/t_net_delay.v | 55 +- test_regress/t/t_timing_debug1.out | 510 +- test_regress/t/t_timing_intra_assign.out | 38 +- test_regress/t/t_timing_intra_assign.pl | 4 +- test_regress/t/t_timing_intra_assign.v | 19 +- test_regress/t/t_timing_osc.out | 11018 +-------------------- 14 files changed, 561 insertions(+), 11334 deletions(-) diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h index 0707ef238..d6ac1fd7e 100644 --- a/src/V3AstNodeOther.h +++ b/src/V3AstNodeOther.h @@ -3611,6 +3611,7 @@ public: }); } bool brokeLhsMustBeLvalue() const override { return true; } + AstDelay* getLhsNetDelay() const; AstAlways* convertToAlways(); }; diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 8416dbf49..7f3a15d2d 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -2899,6 +2899,15 @@ void AstCUse::dumpJson(std::ostream& str) const { dumpJsonGen(str); } +static AstDelay* getLhsNetDelayRecurse(const AstNodeExpr* const nodep) { + if (const AstNodeVarRef* const refp = VN_CAST(nodep, NodeVarRef)) { + if (refp->varp()->delayp()) return refp->varp()->delayp(); + } else if (const AstNodeSel* const selp = VN_CAST(nodep, NodeSel)) { + return getLhsNetDelayRecurse(selp->fromp()); + } + return nullptr; +} +AstDelay* AstAssignW::getLhsNetDelay() const { return getLhsNetDelayRecurse(lhsp()); } AstAlways* AstAssignW::convertToAlways() { const bool hasTimingControl = isTimingControl(); AstNodeExpr* const lhs1p = lhsp()->unlinkFrBack(); diff --git a/src/V3ParseGrammar.cpp b/src/V3ParseGrammar.cpp index 5938335eb..b4835bc80 100644 --- a/src/V3ParseGrammar.cpp +++ b/src/V3ParseGrammar.cpp @@ -226,8 +226,7 @@ AstVar* V3ParseGrammar::createVariable(FileLine* fileline, const string& name, nodep->ansi(m_pinAnsi); nodep->declTyped(m_varDeclTyped); nodep->lifetime(m_varLifetime); - nodep->delayp(m_netDelayp); - m_netDelayp = nullptr; + nodep->delayp(getNetDelay()); if (GRAMMARP->m_varDecl != VVarType::UNKNOWN) nodep->combineType(GRAMMARP->m_varDecl); if (GRAMMARP->m_varIO != VDirection::NONE) { nodep->declDirection(GRAMMARP->m_varIO); diff --git a/src/V3SchedTiming.cpp b/src/V3SchedTiming.cpp index d6d763c56..0532ba998 100644 --- a/src/V3SchedTiming.cpp +++ b/src/V3SchedTiming.cpp @@ -300,14 +300,8 @@ void transformForks(AstNetlist* const netlistp) { // If not a fork..join, copy. All write refs should've been handled by V3Fork bool passByValue = !m_forkp->joinType().join(); if (!varp->isFuncLocal()) { - if (VString::startsWith(varp->name(), "__Vintra")) { - // Pass it by value to the new function, as otherwise there are issues with - // -flocalize (see t_timing_intra_assign) - passByValue = true; - } else { - // Not func local. Its lifetime is longer than the forked process. Skip - return; - } + // Not func local. Its lifetime is longer than the forked process. Skip + return; } else if (!varp->user1()) { // Not declared before the fork. It cannot outlive the forked process return; diff --git a/src/V3Timing.cpp b/src/V3Timing.cpp index fb1517642..ff0514d40 100644 --- a/src/V3Timing.cpp +++ b/src/V3Timing.cpp @@ -445,6 +445,8 @@ class TimingControlVisitor final : public VNVisitor { // NODE STATE // Ast{Always,NodeCCall,Fork,NodeAssign}::user1() -> bool. Set true if the node has // been processed. + // AstAssignW::user1() -> bool. Set true if the assignment + // represents the net delay // AstSenTree::user1() -> AstVarScope*. Trigger scheduler assigned // to this sentree // Ast{NodeProcedure,CFunc,Begin}::user2() -> bool. Set true if process/task @@ -471,7 +473,9 @@ class TimingControlVisitor final : public VNVisitor { // Unique names V3UniqueNames m_dlyforkNames{"__Vdlyfork"}; // Names for temp AssignW vars - V3UniqueNames m_contAssignVarNames{"__VassignWtmp"}; // Names for temp AssignW vars + V3UniqueNames m_contAsgnTmpNames{"__VassignWtmp"}; // Names for temp AssignW vars + V3UniqueNames m_contAsgnGenNames{"__VassignWgen"}; // Continuous assign generation name + // generator V3UniqueNames m_intraValueNames{"__Vintraval"}; // Intra assign delay value var names V3UniqueNames m_intraIndexNames{"__Vintraidx"}; // Intra assign delay index var names V3UniqueNames m_intraLsbNames{"__Vintralsb"}; // Intra assign delay LSB var names @@ -493,47 +497,24 @@ class TimingControlVisitor final : public VNVisitor { SenExprBuilder* m_senExprBuilderp = nullptr; // Sens expression builder for current m_scope // METHODS - // Find net delay on the LHS of an assignment - AstDelay* getLhsNetDelayRecurse(const AstNodeExpr* const nodep) const { - if (const AstNodeVarRef* const refp = VN_CAST(nodep, NodeVarRef)) { - if (refp->varp()->delayp()) return refp->varp()->delayp()->unlinkFrBack(); - } else if (const AstSel* const selp = VN_CAST(nodep, Sel)) { - return getLhsNetDelayRecurse(selp->fromp()); - } - return nullptr; - } // Transform an assignment with an intra timing control into a timing control with the // assignment under it AstNode* factorOutTimingControl(AstNodeAssign* nodep) const { AstNode* stmtp = nodep; - AstDelay* delayp = getLhsNetDelayRecurse(nodep->lhsp()); - FileLine* const flp = nodep->fileline(); AstNode* const controlp = nodep->timingControlp(); - if (controlp) { - controlp->unlinkFrBack(); - if (auto* const assignDelayp = VN_CAST(controlp, Delay)) { - if (delayp) { - delayp->lhsp(new AstAdd{flp, delayp->lhsp()->unlinkFrBack(), - assignDelayp->lhsp()->unlinkFrBack()}); - VL_DO_DANGLING(assignDelayp->deleteTree(), nodep); - } else { - delayp = assignDelayp; - } - } - } - if (delayp) { - stmtp->replaceWith(delayp); + if (AstDelay* const delayp = VN_CAST(controlp, Delay)) { + stmtp->replaceWith(delayp->unlinkFrBack()); delayp->addStmtsp(stmtp); stmtp = delayp; - } - if (auto* const sensesp = VN_CAST(controlp, SenTree)) { - auto* const eventControlp = new AstEventControl{flp, sensesp, nullptr}; + } else if (AstSenTree* const sensesp = VN_CAST(controlp, SenTree)) { + AstEventControl* const eventControlp + = new AstEventControl{sensesp->fileline(), sensesp->unlinkFrBack(), nullptr}; stmtp->replaceWith(eventControlp); eventControlp->addStmtsp(stmtp); stmtp = eventControlp; - } else if (auto* const beginp = VN_CAST(controlp, Begin)) { + } else if (AstBegin* const beginp = VN_CAST(controlp, Begin)) { // Begin from V3AssertPre - stmtp->replaceWith(beginp); + stmtp->replaceWith(beginp->unlinkFrBack()); beginp->addStmtsp(stmtp); stmtp = beginp; } @@ -1062,58 +1043,106 @@ class TimingControlVisitor final : public VNVisitor { controlp->addHereThisAsNext( new AstAssign{flp, new AstVarRef{flp, newvscp, VAccess::WRITE}, valuep}); }; - // Create the intermediate select vars. Note: because 'foreach' proceeds in - // pre-order, and we replace indices in selects with variables, we cannot - // reach another select under the index position. This is exactly what - // we want as only the top level selects are LValues. As an example, - // this transforms 'x[a[i]][b[j]] = y' - // into 't1 = a[i]; t0 = b[j]; x[t1][t0] = y'. - nodep->lhsp()->foreach([&](AstSel* selp) { - if (VN_IS(selp->lsbp(), Const)) return; - replaceWithIntermediate(selp->lsbp(), m_intraLsbNames.get(nodep)); - // widthp should be const - }); - nodep->lhsp()->foreach([&](AstNodeSel* selp) { - if (VN_IS(selp->bitp(), Const)) return; - replaceWithIntermediate(selp->bitp(), m_intraIndexNames.get(nodep)); - }); + // NBAs with delays evaluate LHS indices immediately + if (inAssignDly) { + // Create the intermediate select vars. Note: because 'foreach' proceeds in pre-order, + // and we replace indices in selects with variables, we cannot reach another select + // under the index position. This is exactly what we want as only the top level selects + // are LValues. As an example, this transforms 'x[a[i]][b[j]] = y' into 't1 = a[i]; t0 + // = b[j]; x[t1][t0] = y'. + nodep->lhsp()->foreach([&](AstSel* selp) { + if (VN_IS(selp->lsbp(), Const)) return; + replaceWithIntermediate(selp->lsbp(), m_intraLsbNames.get(nodep)); + // widthp should be const + }); + nodep->lhsp()->foreach([&](AstNodeSel* selp) { + if (VN_IS(selp->bitp(), Const)) return; + replaceWithIntermediate(selp->bitp(), m_intraIndexNames.get(nodep)); + }); + } // Replace the RHS with an intermediate value var replaceWithIntermediate(nodep->rhsp(), m_intraValueNames.get(nodep)); } void visit(AstAssignW* nodep) override { - AstDelay* const netDelayp = getLhsNetDelayRecurse(nodep->lhsp()); - if (!netDelayp && !nodep->timingControlp()) return; - // This assignment will be converted to an always. In some cases this may generate an - // UNOPTFLAT, e.g.: assign #1 clk = ~clk. We create a temp var for the LHS of this - // assign, to disable the UNOPTFLAT warning for it. - // TODO: Find a way to do this without introducing this var. Perhaps make - // V3SchedAcyclic recognize awaits and prevent it from treating this kind of logic as - // cyclic - AstNodeExpr* const lhsp = nodep->lhsp()->unlinkFrBack(); - std::string varname; - if (auto* const refp = VN_CAST(lhsp, VarRef)) { - varname = m_contAssignVarNames.get(refp->name()); - } else { - varname = m_contAssignVarNames.get(lhsp); - } - auto* const tempvscp = m_scopep->createTemp(varname, lhsp->dtypep()); - tempvscp->varp()->delayp(netDelayp); FileLine* const flp = nodep->fileline(); + // Get the net delay unless this assignment was created for handling the net delay (user1) + AstDelay* const netDelayp = nodep->user1() ? nullptr : nodep->getLhsNetDelay(); + if (netDelayp) { + if (nodep->timingControlp()) { + // If this assignment has a delay, create another one to handle the net delay + AstVarScope* const newvscp + = createTemp(flp, m_contAsgnTmpNames.get(nodep), nodep->dtypep()); + AstAssignW* assignp = new AstAssignW{ + nodep->fileline(), nodep->lhsp()->unlinkFrBack(), + new AstVarRef{flp, newvscp, VAccess::READ}, netDelayp->cloneTree(false)}; + assignp->user1(true); + nodep->addNextHere(assignp); + nodep->lhsp(new AstVarRef{flp, newvscp, VAccess::WRITE}); + } else { + // Else just use this one with the net delay + nodep->timingControlp(netDelayp->cloneTree(false)); + } + } + if (!nodep->timingControlp()) return; + // There will be some circular logic here, suppress the warning for newly created vars flp->modifyWarnOff(V3ErrorCode::UNOPTFLAT, true); - tempvscp->fileline(flp); - tempvscp->varp()->fileline(flp); - // Remap the LHS to the new temp var - nodep->lhsp(new AstVarRef{flp, tempvscp, VAccess::WRITE}); + // Also suppress the warning for the LHS var, for cases like `assign #1 clk = ~clk;` + // TODO: Restore the warning for other, non-delayed drivers + nodep->lhsp()->foreach([](AstVarRef* refp) { + if (refp->access().isWriteOrRW()) { + refp->varp()->fileline()->modifyWarnOff(V3ErrorCode::UNOPTFLAT, true); + } + }); // Convert it to an always; the new assign with intra delay will be handled by // visit(AstNodeAssign*) AstAlways* const alwaysp = nodep->convertToAlways(); - visit(alwaysp); - // Put the LHS back in the AssignW; put the temp var on the RHS - nodep->lhsp(lhsp); - nodep->rhsp(new AstVarRef{flp, tempvscp, VAccess::READ}); - // Put the AssignW right after the always. Different order can produce UNOPTFLAT on the LHS - // var - alwaysp->addNextHere(nodep); + visit(alwaysp); // Visit now as we need to do some post-processing + VL_DO_DANGLING(nodep->deleteTree(), nodep); + // IEEE 1800-2023 10.3.3 - if the RHS value differs from the currently scheduled value to + // be assigned, the currently scheduled assignment is descheduled. To keep track if an + // assignment should be descheduled, each scheduled assignment event has a 'generation', + // and if at assignment time its generation differs from the current generation, it won't + // be performed + AstFork* const forkp = VN_AS(alwaysp->stmtsp(), Fork); + UASSERT_OBJ(forkp, alwaysp, "Fork should be there from convertToAlways()"); + AstBegin* const beginp = VN_AS(forkp->stmtsp(), Begin); + UASSERT_OBJ(beginp, alwaysp, "Begin should be there from convertToAlways()"); + AstAssign* const preAssignp = VN_AS(beginp->stmtsp(), Assign); + UASSERT_OBJ(preAssignp, alwaysp, "Pre-assign should be there from convertToAlways()"); + AstAssign* const postAssignp = VN_AS(preAssignp->nextp()->nextp(), Assign); + UASSERT_OBJ(postAssignp, alwaysp, "Post-assign should be there from convertToAlways()"); + // Increment generation and copy it to a local + AstVarScope* const generationVarp + = createTemp(flp, m_contAsgnGenNames.get(alwaysp), alwaysp->findUInt64DType()); + AstVarScope* const genLocalVarp + = createTemp(flp, generationVarp->varp()->name() + "__local", + alwaysp->findUInt64DType(), preAssignp); + preAssignp->addHereThisAsNext( + new AstAssign{flp, new AstVarRef{flp, generationVarp, VAccess::WRITE}, + new AstAdd{flp, new AstVarRef{flp, generationVarp, VAccess::READ}, + new AstConst{flp, 1}}}); + preAssignp->addHereThisAsNext( + new AstAssign{flp, new AstVarRef{flp, genLocalVarp, VAccess::WRITE}, + new AstVarRef{flp, generationVarp, VAccess::READ}}); + // If the current generation is same as the one saved in the local var, assign + beginp->addStmtsp( + new AstIf{flp, + new AstEq{flp, new AstVarRef{flp, generationVarp, VAccess::READ}, + new AstVarRef{flp, genLocalVarp, VAccess::READ}}, + postAssignp->unlinkFrBack()}); + // Save scheduled RHS value before delay + AstVarScope* const tmpVarp + = createTemp(flp, m_contAsgnTmpNames.get(alwaysp), preAssignp->rhsp()->dtypep()); + AstVarRef* const tmpAssignRhsp = VN_AS(preAssignp->lhsp(), VarRef)->cloneTree(false); + tmpAssignRhsp->access(VAccess::WRITE); + preAssignp->addNextHere( + new AstAssign{flp, new AstVarRef{flp, tmpVarp, VAccess::WRITE}, tmpAssignRhsp}); + // If the RHS is different from the currently scheduled value, schedule the new assignment + // The generation will increase, effectively 'descheduling' the previous assignment. + alwaysp->addStmtsp(new AstIf{flp, + new AstNeq{flp, preAssignp->rhsp()->cloneTree(false), + new AstVarRef{flp, tmpVarp, VAccess::READ}}, + forkp->unlinkFrBack()}); } void visit(AstDisableFork* nodep) override { if (hasFlags(m_procp, T_HAS_PROC)) return; diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp index 7472770b3..adb6fdc90 100644 --- a/src/V3Tristate.cpp +++ b/src/V3Tristate.cpp @@ -1247,7 +1247,10 @@ class TristateVisitor final : public TristateBaseVisitor { VL_RESTORER(m_alhs); VL_RESTORER(m_currentStrength); if (m_graphing) { - if (AstAssignW* assignWp = VN_CAST(nodep, AssignW)) addToAssignmentList(assignWp); + if (AstAssignW* assignWp = VN_CAST(nodep, AssignW)) { + if (assignWp->timingControlp() || assignWp->getLhsNetDelay()) return; + addToAssignmentList(assignWp); + } if (nodep->user2() & U2_GRAPHING) return; VL_RESTORER(m_logicp); diff --git a/src/verilog.y b/src/verilog.y index 0f265688e..f65dac85c 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -83,7 +83,8 @@ public: AstCase* m_caseAttrp = nullptr; // Current case statement for attribute adding AstNodeDType* m_varDTypep = nullptr; // Pointer to data type for next signal declaration AstNodeDType* m_memDTypep = nullptr; // Pointer to data type for next member declaration - AstDelay* m_netDelayp = nullptr; // Pointer to delay for next signal declaration + std::unique_ptr m_netDelayp = nullptr; // Pointer to delay for next signal + // declaration AstStrengthSpec* m_netStrengthp = nullptr; // Pointer to strength for next net declaration FileLine* m_instModuleFl = nullptr; // Fileline of module referenced for instantiations AstPin* m_instParamp = nullptr; // Parameters for instantiations @@ -211,7 +212,8 @@ public: if (m_varDTypep) VL_DO_CLEAR(m_varDTypep->deleteTree(), m_varDTypep = nullptr); m_varDTypep = dtypep; } - void setNetDelay(AstDelay* netDelayp) { m_netDelayp = netDelayp; } + void setNetDelay(AstDelay* netDelayp) { m_netDelayp.reset(netDelayp); } + AstDelay* getNetDelay() { return m_netDelayp.release(); } void setNetStrength(AstStrengthSpec* netStrengthp) { m_netStrengthp = netStrengthp; } void pinPush() { m_pinStack.push(m_pinNum); @@ -3045,8 +3047,10 @@ netSig: // IEEE: net_decl_assignment - one element from netId sigAttrListE { $$ = VARDONEA($1, *$1, nullptr, $2); } | netId sigAttrListE '=' expr - { $$ = VARDONEA($1, *$1, nullptr, $2); - auto* const assignp = new AstAssignW{$3, new AstParseRef{$1, VParseRefExp::PX_TEXT, *$1}, $4}; + { AstDelay* const delayp = GRAMMARP->getNetDelay(); + AstAssignW* const assignp = new AstAssignW{$3, new AstParseRef{$1, VParseRefExp::PX_TEXT, *$1}, $4, delayp}; + $$ = VARDONEA($1, *$1, nullptr, $2); + if (delayp) GRAMMARP->setNetDelay(delayp->cloneTree(false)); if (GRAMMARP->m_netStrengthp) assignp->strengthSpecp(GRAMMARP->m_netStrengthp->cloneTree(false)); AstNode::addNext($$, assignp); } | netId variable_dimensionList sigAttrListE diff --git a/test_regress/t/t_net_delay.out b/test_regress/t/t_net_delay.out index 40a84f0f0..2d09dd7e0 100644 --- a/test_regress/t/t_net_delay.out +++ b/test_regress/t/t_net_delay.out @@ -1,15 +1,35 @@ -%Warning-STMTDLY: t/t_net_delay.v:16:14: Ignoring delay on this statement due to --no-timing +%Warning-STMTDLY: t/t_net_delay.v:14:11: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 16 | wire[3:0] #4 val1 = half_cyc; - | ^ + 14 | always #2 clk = ~clk; + | ^ ... For warning description see https://verilator.org/warn/STMTDLY?v=latest ... Use "/* verilator lint_off STMTDLY */" and lint_on around source to disable this message. -%Warning-STMTDLY: t/t_net_delay.v:17:14: Ignoring delay on this statement due to --no-timing +%Warning-STMTDLY: t/t_net_delay.v:20:14: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' - 17 | wire[3:0] #4 val2; + 20 | wire[3:0] #3 val1; | ^ -%Warning-ASSIGNDLY: t/t_net_delay.v:20:11: Ignoring timing control on this assignment/primitive due to --no-timing +%Warning-STMTDLY: t/t_net_delay.v:21:14: Ignoring delay on this statement due to --no-timing + : ... note: In instance 't' + 21 | wire[3:0] #3 val2; + | ^ +%Warning-ASSIGNDLY: t/t_net_delay.v:22:14: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' - 20 | assign #4 val2 = half_cyc; + 22 | wire[3:0] #5 val3 = cyc; + | ^ +%Warning-STMTDLY: t/t_net_delay.v:23:14: Ignoring delay on this statement due to --no-timing + : ... note: In instance 't' + 23 | wire[3:0] #5 val4; + | ^ +%Warning-ASSIGNDLY: t/t_net_delay.v:24:14: Ignoring timing control on this assignment/primitive due to --no-timing + : ... note: In instance 't' + 24 | wire[3:0] #3 val5 = x, val6 = cyc; + | ^ +%Warning-ASSIGNDLY: t/t_net_delay.v:27:11: Ignoring timing control on this assignment/primitive due to --no-timing + : ... note: In instance 't' + 27 | assign #3 val2 = cyc; | ^ +%Warning-STMTDLY: t/t_net_delay.v:39:26: Ignoring delay on this statement due to --no-timing + : ... note: In instance 't' + 39 | always @(posedge clk) #1 begin + | ^ %Error: Exiting due to diff --git a/test_regress/t/t_net_delay.v b/test_regress/t/t_net_delay.v index 4d8190e6a..514504a6b 100644 --- a/test_regress/t/t_net_delay.v +++ b/test_regress/t/t_net_delay.v @@ -7,30 +7,47 @@ `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) -module t (/*AUTOARG*/ - // Inputs - clk - ); - input clk; +module t; + // verilator lint_off UNOPTFLAT + logic clk = 0; + // verilator lint_on UNOPTFLAT + always #2 clk = ~clk; - wire[3:0] #4 val1 = half_cyc; - wire[3:0] #4 val2; - reg[3:0] half_cyc = 0; + // verilator lint_off UNDRIVEN + wire[3:0] x; + // verilator lint_on UNDRIVEN + reg[3:0] cyc = 0; + wire[3:0] #3 val1; + wire[3:0] #3 val2; + wire[3:0] #5 val3 = cyc; + wire[3:0] #5 val4; + wire[3:0] #3 val5 = x, val6 = cyc; - assign #4 val2 = half_cyc; + assign val1 = cyc; + assign #3 val2 = cyc; + assign val4 = cyc; + assign val5 = cyc; - always @(clk) begin - if ($time > 0) half_cyc <= half_cyc + 1; -`ifdef TEST_VERBOSE - $strobe("[%0t] half_cyc=%0d, val1=%0d, val2=%0d", $time, half_cyc, val1, val2); -`endif - if (half_cyc >= 7) begin - `checkh(val1, half_cyc - 3); - `checkh(val2, half_cyc - 7); - end - if (half_cyc == 15) begin + always @(posedge clk) begin + if ($time > 0) cyc <= cyc + 1; + if (cyc == 15) begin $write("*-* All Finished *-*\n"); $finish; end end + + always @(posedge clk) #1 begin +`ifdef TEST_VERBOSE + $display("[%0t] cyc=%0d val1=%0d val2=%0d val3=%0d val4=%0d val5=%0d val6=%0d", + $time, cyc, val1, val2, val3, val4, val5, val6); +`endif + if (cyc >= 3) begin + `checkh(val1, cyc - 1); + `checkh(val2, cyc - 2); + `checkh(val3, 0); + `checkh(val4, 0); + `checkh(val5, cyc); + `checkh(val6, cyc - 1); + end + end endmodule diff --git a/test_regress/t/t_timing_debug1.out b/test_regress/t/t_timing_debug1.out index fae5ac2e7..38db58126 100644 --- a/test_regress/t/t_timing_debug1.out +++ b/test_regress/t/t_timing_debug1.out @@ -18,18 +18,24 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl -V{t#,#} 'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration --V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#} 'stl' region trigger index 2 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#} 'stl' region trigger index 2 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'stl' region trigger index 3 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___eval_stl -V{t#,#}+ Vt_timing_debug1___024root___stl_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___stl_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___stl_sequent__TOP__2 --V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 --V{t#,#}+ Vt_timing_debug1___024root___stl_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___stl_comb__TOP__2 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl +-V{t#,#} 'stl' region trigger index 1 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#} 'stl' region trigger index 2 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___eval_stl +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__stl -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__stl -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__stl @@ -39,8 +45,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): @@ -51,9 +57,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -81,27 +85,16 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 3: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 3: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 --V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -116,14 +109,24 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 @@ -149,7 +152,6 @@ -V{t#,#} Awaiting time 6: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 @@ -158,7 +160,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -167,6 +169,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -193,7 +203,6 @@ -V{t#,#} Awaiting time 7: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:17 @@ -230,7 +239,6 @@ -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 9: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:10 @@ -239,15 +247,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -258,10 +258,20 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -287,27 +297,17 @@ -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Delayed processes: -V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Awaiting time 11: Process waiting at t/t_timing_sched.v:13 -V{t#,#} Awaiting time 12: Process waiting at t/t_timing_sched.v:10 -V{t#,#} Awaiting time 13: Process waiting at t/t_timing_sched.v:17 -V{t#,#} Awaiting time 78: Process waiting at t/t_timing_sched.v:52 -V{t#,#} Resuming delayed processes -V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 --V{t#,#} Resuming: Process waiting at t/t_timing_sched.v:13 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -321,16 +321,20 @@ -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -372,7 +376,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:50 @@ -383,6 +387,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -453,15 +465,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -476,14 +480,24 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 @@ -517,7 +531,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -526,6 +540,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -596,15 +618,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -615,10 +629,20 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -654,7 +678,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -663,6 +687,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -697,7 +729,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -706,6 +738,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -776,15 +816,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -795,10 +827,20 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -834,7 +876,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -843,6 +885,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -914,18 +964,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#} 'act' region trigger index 5 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit @@ -945,16 +985,24 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -1032,7 +1080,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1041,6 +1089,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1111,15 +1167,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -1134,14 +1182,24 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 @@ -1175,7 +1233,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1184,6 +1242,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1254,7 +1320,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1263,6 +1329,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1296,15 +1370,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -1315,10 +1381,20 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1354,7 +1430,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1363,6 +1439,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1433,15 +1517,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -1452,10 +1528,20 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1491,7 +1577,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1500,6 +1586,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1536,20 +1630,12 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 5 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:17 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 5 is active: @(posedge t.clk2) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#} Ready processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:50 -V{t#,#} Ready processes waiting for @(posedge t.clk2): @@ -1560,16 +1646,20 @@ -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -1644,15 +1734,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -1667,14 +1749,24 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#} Committing processes waiting for @(posedge t.clk2): +-V{t#,#} - Process waiting at t/t_timing_sched.v:18 +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#} Committing processes waiting for @(posedge t.clk2): --V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba -V{t#,#}+ Vt_timing_debug1___024root___eval_nba -V{t#,#}+ Vt_timing_debug1___024root___nba_sequent__TOP__0 @@ -1708,7 +1800,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1717,6 +1809,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1787,15 +1887,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -1806,10 +1898,20 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1846,8 +1948,8 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1858,6 +1960,16 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1928,15 +2040,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -1947,10 +2051,20 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -1986,7 +2100,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act @@ -1995,6 +2109,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -2065,15 +2187,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 3 is active: @(posedge t.clk1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -2084,10 +2198,20 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0____Vfork_1__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba @@ -2123,15 +2247,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 1 is active: @([hybrid] __VassignWtmp_t.clk2__0) --V{t#,#}+ Vt_timing_debug1___024root___timing_commit --V{t#,#}+ Vt_timing_debug1___024root___timing_resume --V{t#,#}+ Vt_timing_debug1___024root___eval_act --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 --V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 --V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act --V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act --V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 5 is active: @(posedge t.clk2) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___timing_resume @@ -2145,16 +2261,20 @@ -V{t#,#} Suspending process waiting for @(posedge t.clk1) at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___eval_act -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1____Vfork_2__0 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 1 is active: @([hybrid] t.clk2 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#} 'act' region trigger index 2 is active: @([hybrid] t.c1) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk1): -V{t#,#} - Process waiting at t/t_timing_sched.v:18 -V{t#,#}+ Vt_timing_debug1___024root___timing_resume -V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__1 -V{t#,#}+ Vt_timing_debug1___024root___act_comb__TOP__2 -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act @@ -2198,7 +2318,7 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act --V{t#,#} 'act' region trigger index 0 is active: @([hybrid] __VassignWtmp_t.clk1__0) +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#} Committing processes waiting for @(posedge t.clk2): -V{t#,#} - Process waiting at t/t_timing_sched.v:50 @@ -2209,6 +2329,14 @@ -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act -V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act -V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act +-V{t#,#} 'act' region trigger index 0 is active: @([hybrid] t.clk1 or [hybrid] __VassignWtmp_h########__0 or [hybrid] __VassignWgen_h########__0) +-V{t#,#}+ Vt_timing_debug1___024root___timing_commit +-V{t#,#}+ Vt_timing_debug1___024root___timing_resume +-V{t#,#}+ Vt_timing_debug1___024root___eval_act +-V{t#,#}+ Vt_timing_debug1___024root___act_sequent__TOP__0 +-V{t#,#}+ Vt_timing_debug1___024root___eval_phase__act +-V{t#,#}+ Vt_timing_debug1___024root___eval_triggers__act +-V{t#,#}+ Vt_timing_debug1___024root___dump_triggers__act -V{t#,#} No triggers active -V{t#,#}+ Vt_timing_debug1___024root___timing_commit -V{t#,#}+ Vt_timing_debug1___024root___eval_phase__nba diff --git a/test_regress/t/t_timing_intra_assign.out b/test_regress/t/t_timing_intra_assign.out index fc870d925..ea22e3418 100644 --- a/test_regress/t/t_timing_intra_assign.out +++ b/test_regress/t/t_timing_intra_assign.out @@ -1,15 +1,25 @@ -val[0]=0 val[1]=0 val[2]=0 -val[0]=1 val[1]=0 val[2]=0 -val[0]=2 val[1]=0 val[2]=15 -val[0]=3 val[1]=0 val[2]=15 -val[0]=4 val[1]=1 val[2]=14 -val[0]=5 val[1]=1 val[2]=14 -val[0]=6 val[1]=2 val[2]=13 -val[0]=7 val[1]=4 val[2]=11 -val[0]=8 val[1]=7 val[2]=8 -val[0]=9 val[1]=7 val[2]=8 -val[0]=10 val[1]=7 val[2]=8 -val[0]=11 val[1]=7 val[2]=8 -val[0]=12 val[1]=7 val[2]=8 -val[0]=13 val[1]=7 val[2]=8 +[0] val[0]=0 val[1]=0 val[2]=0 net[0]=0 net[1]=0 +[10] val[0]=1 val[1]=0 val[2]=0 net[0]=0 net[1]=15 +[14] val[0]=1 val[1]=1 val[2]=0 net[0]=0 net[1]=15 +[16] val[0]=1 val[1]=1 val[2]=1 net[0]=0 net[1]=15 +[20] val[0]=2 val[1]=1 val[2]=1 net[0]=1 net[1]=14 +[24] val[0]=2 val[1]=2 val[2]=1 net[0]=1 net[1]=14 +[25] val[0]=3 val[1]=2 val[2]=1 net[0]=1 net[1]=14 +[29] val[0]=3 val[1]=3 val[2]=1 net[0]=2 net[1]=13 +[30] val[0]=4 val[1]=3 val[2]=1 net[0]=2 net[1]=13 +[34] val[0]=4 val[1]=4 val[2]=1 net[0]=3 net[1]=12 +[35] val[0]=5 val[1]=4 val[2]=1 net[0]=3 net[1]=12 +[39] val[0]=5 val[1]=5 val[2]=1 net[0]=4 net[1]=11 +[40] val[0]=6 val[1]=5 val[2]=1 net[0]=4 net[1]=11 +[44] val[0]=6 val[1]=6 val[2]=1 net[0]=5 net[1]=10 +[46] val[0]=6 val[1]=6 val[2]=6 net[0]=5 net[1]=10 +[50] val[0]=7 val[1]=6 val[2]=6 net[0]=6 net[1]=9 +[54] val[0]=7 val[1]=7 val[2]=6 net[0]=6 net[1]=9 +[56] val[0]=7 val[1]=7 val[2]=7 net[0]=6 net[1]=9 +[75] val[0]=8 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[76] val[0]=9 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[78] val[0]=10 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[79] val[0]=11 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[80] val[0]=12 val[1]=7 val[2]=7 net[0]=7 net[1]=8 +[82] val[0]=13 val[1]=7 val[2]=7 net[0]=7 net[1]=8 *-* All Finished *-* diff --git a/test_regress/t/t_timing_intra_assign.pl b/test_regress/t/t_timing_intra_assign.pl index 50cf99255..6a7c671d8 100755 --- a/test_regress/t/t_timing_intra_assign.pl +++ b/test_regress/t/t_timing_intra_assign.pl @@ -11,7 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); compile( - verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT"], + verilator_flags2 => ["--binary"], ); execute( @@ -19,7 +19,7 @@ execute( ); compile( - verilator_flags2 => ["--exe --main --timing -Wno-UNOPTFLAT -fno-localize"], + verilator_flags2 => ["--binary -fno-localize"], ); execute( diff --git a/test_regress/t/t_timing_intra_assign.v b/test_regress/t/t_timing_intra_assign.v index 35afe20a9..15f4f16fd 100644 --- a/test_regress/t/t_timing_intra_assign.v +++ b/test_regress/t/t_timing_intra_assign.v @@ -6,28 +6,35 @@ module t; logic[3:0] val[3]; + wire[3:0] #5 net[2]; logic[1:0] idx1 = 0; logic[1:0] idx2 = 0; logic[0:0] idx3 = 0; event e; - always @val[0] $write("val[0]=%0d val[1]=%0d val[2]=%0d\n", val[0], val[1], val[2]); + always @val $write("[%0t] val[0]=%0d val[1]=%0d val[2]=%0d net[0]=%0d net[1]=%0d\n", + $time, val[0], val[1], val[2], net[0], net[1]); - assign #10 {val[1], val[2]} = {val[0], 4'hf-val[0]}; + assign {net[0], net[1]} = {val[1], 4'hf-val[1]}; + assign #4 val[1] = val[0]; + assign #6 val[2] = val[0]; always #10 begin // always so we can use NBA val[0] = 1; #10 val[0] = 2; fork #5 val[0] = 3; join_none val[0] = #10 val[0] + 2; - val[idx1] <= #10 val[idx1] + 2; + val[0] <= #10 val[idx1] + 2; fork begin #5 val[0] = 5; - idx1 = 2; - idx2 = 3; - idx3 = 1; + idx1 = 0; + idx2 = 0; + idx3 = 0; #40 ->e; end join_none + idx1 = 2; + idx2 = 3; + idx3 = 1; val[idx1][idx2[idx3+:2]] = #20 1; @e val[0] = 8; fork begin diff --git a/test_regress/t/t_timing_osc.out b/test_regress/t/t_timing_osc.out index c5d5b92a2..b2c0182c3 100644 --- a/test_regress/t/t_timing_osc.out +++ b/test_regress/t/t_timing_osc.out @@ -46,11038 +46,44 @@ r3.82e-11 ; r0 = #38200 1& -#50000 -#76400 #88200 1# #89000 1% -#100000 -#114600 -#126400 #127200 0& -#138200 -#139000 -#150000 -#152800 -#164600 -#165400 -#176400 #177200 0# -#178000 -#188200 -#189000 -#191000 -#200000 -#202800 -#203600 -#214600 -#215400 -#216200 -#226400 -#227200 -#228000 -#229200 -#238200 -#239000 -#241000 -#241800 -#250000 -#252800 -#253600 -#254400 -#264600 -#265400 -#266200 -#267000 -#267400 -#276400 -#277200 -#278000 -#279200 -#280000 -#288200 -#289000 -#291000 -#291800 -#292600 -#300000 -#302800 -#303600 -#304400 -#305200 -#305600 -#314600 -#315400 -#316200 -#317000 -#317400 -#318200 -#326400 -#327200 -#328000 -#329200 -#330000 -#330800 -#338200 -#339000 -#341000 -#341800 -#342600 -#343400 -#343800 -#350000 -#352800 -#353600 -#354400 -#355200 -#355600 -#356000 -#356400 -#364600 -#365400 -#366200 -#367000 -#367400 -#368200 -#369000 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