diff --git a/Changes b/Changes index 04cfda00b..8a9220922 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,10 @@ contributors that suggested a given feature are shown in []. Thanks! Verilator 4.201 devel ========================== +**Major:** + +* Documentation has been rewritten into a book format. + **Minor:** * Add EOFNEWLINE warning when missing a newline at EOF. @@ -169,7 +173,7 @@ Verilator 4.102 2020-10-15 * Support # as a comment in -f files (#2497). [phantom-killua] * Support 'this' (#2585). [Rafal Kapuscik] * Support defines for FST tracing (#2592). [Markus Krause] -* Support |=> inside properties (#1292). [Peter Monsson] +* Support non-overapping implication inside properties (#1292). [Peter Monsson] * Fix timescale with --hierarchical (#2554). [Yutetsu TAKATSUKASA] * Fix cmake build with --hierarchical (#2560). [Yutetsu TAKATSUKASA] * Fix -G dropping public indication (#2561). [Andrew Goessling] @@ -195,7 +199,7 @@ Verilator 4.100 2020-09-07 * Support (with limitations) class extern, class extends, virtual class. * Support $urandom, $urandom_range without stability. * Support assume property. [Peter Monsson] -* Support |=> inside properties (#1292). [Peter Monsson] +* Support non-overapping implication inside properties (#1292). [Peter Monsson] * Fix false DECLFILENAME on black-boxed modules (#2430). [Philipp Wagner] * Fix naming of "id : begin" blocks. * Fix class constructor error on assignments to const. @@ -401,7 +405,7 @@ Verilator 4.026 2020-01-11 **Minor:** * Support bounded queues. -* Support implication operator "|->" in assertions. (#2069) [Peter Monsson] +* Support non-overlapping implication operator in assertions. (#2069) [Peter Monsson] * Support string compare, ato*, etc methods. (#1606) [Yutetsu TAKATSUKASA] * Support immediate cover statements. * Ignore `uselib to end-of-line. (#1634) [Frederic Antonin] @@ -1172,7 +1176,7 @@ Verilator 3.866 2014-11-15 * Add public enums. (#833) [Jonathon Donaldson] * Trace_off now operates on cells. (#826) [Lane Brooks] * Fix public parameters in unused packages. (#804) [Jonathon Donaldson] -* Fix select when partially out-of-bound. (#823) [Cliffort Wolf] +* Fix select when partially out-of-bound. (#823) [Clifford Wolf] * Fix generate unrolling with function call. (#830) [Steven Slatter] * Fix cast-to-size context-determined sizing. (#828) [Geoff Barrett] * Fix not tracing modules following primitives. (#837) [Jie Xu] @@ -1513,7 +1517,7 @@ Verilator 3.833 2012-04-15 **Minor:** * Support += and -= in standard for loops. (#463) [Alex Solomatnikov] -* Fix processing unused parametrized modules. (#469) (#470) [Alex Solomatnikov] +* Fix processing unused parameterized modules. (#469) (#470) [Alex Solomatnikov] * Add SELRANGE as warning instead of error. (#477) [Alex Solomatnikov] * Add readme.pdf and internal.pdf and doxygen. (#483) [by Jeremy Bennett] * Fix change detections on arrays. (#364) [John Stevenson, Alex Solomatnikov] @@ -1585,7 +1589,7 @@ Verilator 3.824 2011-10-25 **Minor:** * Fix "always @ (* )". (#403) (#404) [Walter Lavino] -* Add ASSIGNIN as suppressable error. [Jeremy Bennett] +* Add ASSIGNIN as suppressible error. [Jeremy Bennett] * Fix 3.823 constructor core dump on Debian. (#401) [Ahmed El-Mahmoudy] @@ -1667,7 +1671,7 @@ Verilator 3.811 2011-02-14 * Report error on duplicated or empty pins. (#321) [Christian Leber] * Report error on function call output tied to constant. [Bernard Deadman] -* Throw UNUSED/UNDRIVEN only once per net in a parametrized module. +* Throw UNUSED/UNDRIVEN only once per net in a parameterized module. * Fix internal error on functions called as SV tasks. [Bernard Deadman] * Fix internal error on non-inlined inout pins. [Jeff Winston] * Fix false BLKSEQ on non-unrolled for loop indexes. [Jeff Winston] @@ -1970,7 +1974,7 @@ Verilator 3.700 2009-01-08 * Line coverage now aggregates by hierarchy automatically. Previously this would be done inside SystemPerl, which was slower. * Minor performance improvements of Verilator compiler runtime. -* Coverage of each parametarized module is counted separately. [Bob Fredieu] +* Coverage of each parameterized module is counted separately. [Bob Fredieu] * Fix creating parameterized modules when no parameter values are changed. * Fix certain generate-if cells causing "clone" error. [Stephane Laurent] * Fix line coverage of public functions. [Soon Koh] @@ -2381,7 +2385,7 @@ Verilator 3.620 2006-10-04 Stable * Optimize variables set to constants within basic blocks for ~3%. * Default make no longer makes the docs; if you edit the documentation. sources, run "make info" to get them. -* Optimize additional boolean identities (a|a = a, etc.) +* Optimize additional Boolean identities (a|a = a, etc.) * Fix coredump when dotted cross-ref inside task call. [Eugene Weber] * Fix dotted variables in always sensitivity lists. [Allan Cochrane] diff --git a/MANIFEST.SKIP b/MANIFEST.SKIP index b46442e93..4a964bc40 100644 --- a/MANIFEST.SKIP +++ b/MANIFEST.SKIP @@ -42,6 +42,7 @@ docs/.*\.html$ docs/_build/ docs/clang-format.txt$ docs/doxygen-doc/.* +docs/spelling.txt examples/xml_py/copied/ examples/xml_py/graph.* sonar-project.properties diff --git a/Makefile.in b/Makefile.in index 1bc4b05d7..a2efb887d 100644 --- a/Makefile.in +++ b/Makefile.in @@ -51,7 +51,6 @@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_DATA = @INSTALL_DATA@ MAKEINFO = makeinfo POD2TEXT = pod2text -POD2LATEXFIX = $(srcdir)/src/pod2latexfix MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs PERL = @PERL@ @@ -111,14 +110,14 @@ SUBDIRS = docs src test_regress \ examples/make_protect_lib \ examples/xml_py \ -INFOS = verilator.txt verilator.html verilator.pdf +INFOS = verilator.html verilator.pdf INFOS_OLD = README README.html README.pdf # Files that can be generated, but should be up to date for a distribution. DISTDEP = info Makefile -DISTFILES_INC = $(INFOS) .gitignore \ +DISTFILES1 = $(INFOS) .gitignore \ *.in *.ac \ Artistic \ Changes \ @@ -137,9 +136,14 @@ DISTFILES_INC = $(INFOS) .gitignore \ docs/CONTRIBUTING.rst \ docs/CONTRIBUTORS \ docs/Makefile \ - docs/_static/verilator_logo.png \ + docs/_static/* \ + docs/bin/* \ + docs/gen/* \ + docs/guide/* \ docs/install.rst \ docs/internals.rst \ + docs/internals.rst \ + docs/verilated.dox \ docs/xml.rst \ install-sh configure *.pod \ include/*.[chv]* \ @@ -157,6 +161,8 @@ DISTFILES_INC = $(INFOS) .gitignore \ examples/*/.*ignore examples/*/Makefile* \ examples/*/*.[chv]* examples/*/vl_* \ examples/*/CMakeLists.txt \ + +DISTFILES2 = \ test_*/.*ignore test_*/Makefile* test_*/*.cpp \ test_*/*.pl test_*/*.v test_*/*.vc test_*/*.vh \ test_regress/*.pl \ @@ -195,8 +201,6 @@ INST_PROJ_BIN_FILES = \ bin/verilator_bin_dbg \ bin/verilator_coverage_bin_dbg \ -DISTFILES := $(DISTFILES_INC) - EXAMPLES_FIRST = \ examples/make_hello_c \ examples/make_hello_sc \ @@ -260,20 +264,14 @@ info: $(INFOS) %.1: ${srcdir}/bin/% pod2man $< $@ -verilator.txt: ${srcdir}/bin/verilator - $(POD2TEXT) $< $@ - -verilator.html: ${srcdir}/bin/verilator - pod2html $< >$@ +.PHONY: verilator.html +verilator.html: + $(MAKE) -C docs html # PDF needs DIST variables; but having configure.ac as dependency isn't detected -verilator.pdf: ${srcdir}/bin/verilator Makefile $(POD2LATEXFIX) - pod2latex --full --out verilator.tex $< - $(PERL) $(POD2LATEXFIX) "$(DISTTITLE)" "${DISTDATE}" < verilator.tex > verilator2.tex - mv verilator2.tex verilator.tex - pdflatex verilator.tex - pdflatex verilator.tex - -rm -f verilator.toc verilator.aux verilator.idx verilator.out +.PHONY: verilator.pdf +verilator.pdf: Makefile + $(MAKE) -C docs verilator.pdf # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg verilator_coverage_bin_dbg \ @@ -474,6 +472,10 @@ clang-format: PY_PROGRAMS = \ examples/xml_py/vl_file_copy \ examples/xml_py/vl_hier_graph \ + docs/guide/conf.py \ + docs/guide/vl_sphinx_extract \ + docs/guide/vl_sphinx_extract \ + docs/guide/vl_doxygen_filter \ src/astgen \ src/bisonpre \ src/config_rev \ @@ -564,6 +566,7 @@ clean mostlyclean distclean maintainer-clean:: rm -rf test_*/obj_dir rm -rf nodist/fuzzer/dictionary rm -rf nodist/obj_dir + rm -rf verilator.txt distclean maintainer-clean:: rm -f *.info* *.1 $(INFOS) $(INFOS_OLD) $(VL_INST_MAN_FILES) @@ -588,7 +591,8 @@ doxygen: dist-file-list: @echo "begin-dist-file-list:"; # Scripts look for this - @echo $(wildcard $(DISTFILES)) + @echo $(wildcard $(DISTFILES1)) + @echo $(wildcard $(DISTFILES2)) @echo "end-dist-file-list:"; # Scripts look for this ###################################################################### @@ -607,7 +611,12 @@ tag: # Don't depend on DISTFILES because there's no rule for "standards.info*". dist: $(DISTDEP) maintainer-copy -rm -fr $(DISTNAME) - for file in $(DISTFILES); do \ + for file in $(DISTFILES1); do \ + mkdir -p `dirname $(DISTNAME)/$$file` >/dev/null ; \ + ln $$file $(DISTNAME)/$$file \ + || { echo copying $$file instead; cp -p $$file $(DISTNAME)/$$file;}; \ + done; true; + for file in $(DISTFILES2); do \ mkdir -p `dirname $(DISTNAME)/$$file` >/dev/null ; \ ln $$file $(DISTNAME)/$$file \ || { echo copying $$file instead; cp -p $$file $(DISTNAME)/$$file;}; \ diff --git a/bin/verilator b/bin/verilator index 75d4bc395..59fb5e608 100755 --- a/bin/verilator +++ b/bin/verilator @@ -257,35 +257,14 @@ Verilog and SystemVerilog designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler. -Verilator is typically used as follows: - -1. The C executable is invoked with parameters similar to GCC, -Cadence Verilog-XL/NC-Verilog, or Synopsys VCS. C reads the -specified user's SystemVerilog code, lints it, optionally adds coverage and -waveform tracing support, and compiles the design into a source level C++ -or SystemC "model". The resulting model's C++ or SystemC code is output as -.cpp and .h files. This is referred to as "verilating" and the process is -"to verilate"; the output is a "verilated" model. - -2. For simulation, a small user written C++ wrapper file is required, the -"wrapper". This wrapper defines the C++ function `main()` which -instantiates the Verilated model as a C++/SystemC object. - -3. The user main wrapper, the files created by Verilator, a "runtime -library" provided by Verilator, and if applicable the SystemC libraries are -then compiled using a C++ compiler to create a simulation executable. - -4. The resulting executable will perform the actual simulation, during -"simulation runtime". - -To get started, jump down to the L section. +For documentation see L. =head1 ARGUMENT SUMMARY This is a short summary of the arguments to the "verilator" executable. -See L for the detailed descriptions of these -arguments. +See L for the detailed +descriptions of these arguments. =for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst" @@ -452,8 +431,9 @@ arguments. -y Directory to search for modules This is a short summary of the simulation runtime arguments, i.e. for the -final Verilated simulation runtime models. See L for the detailed description of these arguments. +final Verilated simulation runtime models. See +L for the detailed description of +these arguments. =for VL_SPHINX_EXTRACT "_build/gen/args_verilated.rst" @@ -471,5383 +451,6 @@ ARGUMENTS"> for the detailed description of these arguments. +verilator+version Show version and exit -=head1 VERILATION ARGUMENTS - -The following are the arguments that may be passed to the "verilator" -executable. - -=over 4 - -=item - -Specifies the Verilog file containing the top module to be Verilated. - -=item - -Used with --exe to specify optional C++ files to be linked in with the -Verilog code. The file path should either be absolute, or relative to -where the make will be executed from, or add to your makefile's VPATH the -appropriate directory to find the file. - -See also the -CFLAGS and -LDFLAGS options, which are useful when the C++ -files need special compiler flags. - -=item - -Specifies optional object or library files to be linked in with the Verilog -code, as a shorthand for -LDFLAGS "". The file path should either be -absolute, or relative to where the make will be executed from, or add to -your makefile's VPATH the appropriate directory to find the file. - -If any files are specified in this way, Verilator will include a make rule -that uses these files when linking the I executable. This -generally is only useful when used with the --exe option. - -=item +1364-1995ext+I - -=item +1364-2001ext+I - -=item +1364-2005ext+I - -=item +1800-2005ext+I - -=item +1800-2009ext+I - -=item +1800-2012ext+I - -=item +1800-2017ext+I - -Specifies the language standard to be used with a specific filename -extension, I. - -For compatibility with other simulators, see also the synonyms -C<+verilog1995ext+>I, C<+verilog2001ext+>I, and -C<+systemverilogext+>I. - -For any source file, the language specified by these options takes -precedence over any language specified by the C<--default-language> or -C<--language> options. - -These options take effect in the order they are encountered. Thus the -following would use Verilog 1995 for C and Verilog 2001 for C. - - verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v - -These flags are only recommended for legacy mixed language designs, as the -preferable option is to edit the code to repair new keywords, or add -appropriate C<`begin_keywords>. - -B C<`begin_keywords> is a SystemVerilog construct, which specifies -I the set of keywords to be recognized. This also controls some error -messages that vary between language standards. Note at present Verilator -tends to be overly permissive, e.g. it will accept many grammar and other -semantic extensions which might not be legal when set to an older standard. - -=item --assert - -Enable all assertions. - -=item --autoflush - -After every $display or $fdisplay, flush the output stream. This ensures -that messages will appear immediately but may reduce performance. For best -performance call "fflush(stdout)" occasionally in the C++ main loop. -Defaults to off, which will buffer output as provided by the normal C/C++ -standard library IO. - -=item --bbox-sys - -Black box any unknown $system task or function calls. System tasks will -simply become no-operations, and system functions will be replaced with -unsized zero. Arguments to such functions will be parsed, but not -otherwise checked. This prevents errors when linting in the presence of -company specific PLI calls. - -Using this argument will likely cause incorrect simulation. - -=item --bbox-unsup - -Black box some unsupported language features, currently UDP tables, the -cmos and tran gate primitives, deassign statements, and mixed edge errors. -This may enable linting the rest of the design even when unsupported -constructs are present. - -Using this argument will likely cause incorrect simulation. - -=item --bin I - -Rarely needed. Override the default filename for Verilator itself. When a -dependency (.d) file is created, this filename will become a source -dependency, such that a change in this binary will have make rebuild the -output files. - -=item --build - -After generating the SystemC/C++ code, Verilator will invoke the toolchain to -build the model library (and executable when C<--exe> is also used). Verilator -manages the build itself, and for this --build requires GNU Make to be -available on the platform. - -=item -CFLAGS I - -Add specified C compiler flag to the generated makefiles. For multiple -flags either pass them as a single argument with space separators quoted in -the shell (C<-CFLAGS "-a -b">), or use multiple -CFLAGS arguments -(C<-CFLAGS -a -CFLAGS -b>). - -When make is run on the generated makefile these will be passed to the C++ -compiler (g++/clang++/msvc++). - -=item --cc - -Specifies C++ without SystemC output mode; see also --sc. - -=item --cdc - -Permanently experimental. Perform some clock domain crossing checks and -issue related warnings (CDCRSTLOGIC) and then exit; if warnings other than -CDC warnings are needed make a second run with --lint-only. Additional -warning information is also written to the file {prefix}__cdc.txt. - -Currently only checks some items that other CDC tools missed; if you have -interest in adding more traditional CDC checks, please contact the authors. - -=item --clk I - -Sometimes it is quite difficult for Verilator to distinguish clock signals from -other data signals. Occasionally the clock signals can end up in the checking -list of signals which determines if further evaluation is needed. This will -heavily degrade the performance of a Verilated model. - -With --clk , user can specified root clock into the model, then -Verilator will mark the signal as clocker and propagate the clocker attribute -automatically to other signals derived from that. In this way, Verilator will -try to avoid taking the clocker signal into checking list. - -Note signal-name is specified by the RTL hierarchy path. For example, v.foo.bar. -If the signal is the input to top-module, the directly the signal name. If you -find it difficult to find the exact name, try to use C in -RTL file to mark the signal directly. - -If clock signals are assigned to vectors and then later used individually, -Verilator will attempt to decompose the vector and connect the single-bit -clock signals directly. This should be transparent to the user. - -=item --make I - -Generates a script for the specified build tool. - -Supported values are C for GNU Make and C for CMake. Both can be -specified together. If no build tool is specified, gmake is assumed. The -executable of gmake can be configured via environment variable "MAKE". - -When using --build Verilator takes over the responsibility of building the -model library/executable. For this reason --make cannot be specified when -using --build. - -=item --compiler I - -Enables workarounds for the specified C++ compiler, either C, -C, or C. Currently this does not change any performance tuning -flags, but it may in the future. - -=over 4 - -=item clang - -Tune for clang. This may reduce execution speed as it enables several -workarounds to avoid silly hard-coded limits in clang. This includes -breaking deep structures as for msvc as described below. - -=item gcc - -Tune for GNU C++, although generated code should work on almost any -compliant C++ compiler. Currently the default. - -=item msvc - -Tune for Microsoft Visual C++. This may reduce execution speed as it -enables several workarounds to avoid silly hard-coded limits in MSVC++. -This includes breaking deeply nested parenthesized expressions into -sub-expressions to avoid error C1009, and breaking deep blocks into -functions to avoid error C1061. - -=back - -=item --converge-limit I - -Rarely needed. Specifies the maximum number of runtime iterations before -creating a model failed to converge error. Defaults to 100. - -=item --coverage - -Enables all forms of coverage, alias for "--coverage-line --coverage-toggle ---coverage-user". - -=item --coverage-line - -Specifies basic block line coverage analysis code should be inserted. - -Coverage analysis adds statements at each code flow change point (e.g. at -branches). At each such branch a unique counter is incremented. At the -end of a test, the counters along with the filename and line number -corresponding to each counter are written into logs/coverage.dat. - -Verilator automatically disables coverage of branches that have a $stop in -them, as it is assumed $stop branches contain an error check that should -not occur. A /*verilator coverage_block_off*/ comment will perform a -similar function on any code in that block or below, or /*verilator -coverage_on/coverage_off*/ will disable coverage around lines of code. - -Note Verilator may over-count combinatorial (non-clocked) blocks when those -blocks receive signals which have had the UNOPTFLAT warning disabled; for -most accurate results do not disable this warning when using coverage. - -=item --coverage-max-width I - -Rarely needed. Specify the maximum bit width of a signal that is subject -to toggle coverage. Defaults to 256, as covering large vectors may greatly -slow coverage simulations. - -=item --coverage-toggle - -Specifies signal toggle coverage analysis code should be inserted. - -Every bit of every signal in a module has a counter inserted. The counter -will increment on every edge change of the corresponding bit. - -Signals that are part of tasks or begin/end blocks are considered local -variables and are not covered. Signals that begin with underscores, are -integers, or are very wide (>256 bits total storage across all dimensions) -are also not covered. - -Hierarchy is compressed, such that if a module is instantiated multiple -times, coverage will be summed for that bit across ALL instantiations of -that module with the same parameter set. A module instantiated with -different parameter values is considered a different module, and will get -counted separately. - -Verilator makes a minimally-intelligent decision about what clock domain -the signal goes to, and only looks for edges in that clock domain. This -means that edges may be ignored if it is known that the edge could never be -seen by the receiving logic. This algorithm may improve in the future. -The net result is coverage may be lower than what would be seen by looking -at traces, but the coverage is a more accurate representation of the -quality of stimulus into the design. - -There may be edges counted near time zero while the model stabilizes. It's -a good practice to zero all coverage just before releasing reset to prevent -counting such behavior. - -A /*verilator coverage_off/on */ comment pair can be used around signals -that do not need toggle analysis, such as RAMs and register files. - -=item --coverage-underscore - -Enable coverage of signals that start with an underscore. Normally, these -signals are not covered. See also --trace-underscore. - -=item --coverage-user - -Enables user inserted functional coverage. Currently, all functional -coverage points are specified using SVA which must be separately enabled -with --assert. - -For example, the following statement will add a coverage point, with -the comment "DefaultClock": - - DefaultClock: cover property (@(posedge clk) cyc==3); - -=item -DI=I - -Defines the given preprocessor symbol. Similar to +define, but does not -allow multiple definitions with a single option using plus signs. +define -is fairly standard across Verilog tools while -D is similar to GCC. - -=item --debug - -Select the debug executable of Verilator (if available), and enable more -internal assertions (equivalent to C<--debug-check>), debugging messages -(equivalent to C<--debugi 3>), intermediate form dump files (equivalent to -C<--dump-treei 3>), and leak to make node numbers unique (--debug-leak). - -Verilator will also abort() instead of exit() if there are any errors -detected. - -=item --debug-check - -Rarely needed. Enable internal debugging assertion checks, without -changing debug verbosity. Enabled automatically when --debug specified. - -=item --no-debug-leak - -In --debug mode, by default Verilator intentionally leaks AstNode instances -instead of freeing them, so that each node pointer is unique in the -resulting tree files and dot files. - -This option disables the leak. This may avoid out-of-memory errors -when Verilating large models in --debug mode. - -Outside of --debug mode, AstNode instances should never be leaked and this -option has no effect. - -=item --debugi I - -=item --debugi-I I - -Rarely needed - for developer use. Set internal debugging level globally -to the specified debug level (1-10) or set the specified Verilator source -file to the specified level (e.g. C<--debugi-V3Width 9>). Higher levels -produce more detailed messages. See --debug for other implications of -having debug on (at levels other than zero). - -=item --default-language I - -Select the language to be used by default when first processing each -Verilog file. The language value must be "1364-1995", "1364-2001", -"1364-2005", "1800-2005", "1800-2009", "1800-2012" or "1800-2017". - -Any language associated with a particular file extension (see the various -+Iext+ options) will be used in preference to the language specified -by --default-language. - -The --default-language flag is only recommended for legacy code using the -same language in all source files, as the preferable option is to edit the -code to repair new keywords, or add appropriate C<`begin_keywords>. For -legacy mixed language designs, the various +Iext+ options should be -used. - -If no language is specified, either by this flag or +Iext+ options, -then the latest SystemVerilog language (IEEE 1800-2017) is used. - -=item +define+I=I - -=item +define+I=I+I=I... - -Defines the given preprocessor symbol, or multiple symbols if separated by -plus signs. Similar to -D; +define is fairly standard across Verilog tools -while -D is similar to GCC. - -=item --dpi-hdr-only - -Only generate the DPI header file. This option has no effect on the name -or location of the emitted DPI header file, it is output in C<--Mdir> as it -would be without this option. - -=item --dump-defines - -With -E, suppress normal output, and instead print a list of all defines -existing at the end of pre-processing the input files. Similar to GCC "-dM" -option. This also gives you a way of finding out what is predefined in -Verilator using the command: - - touch foo.v ; verilator -E --dump-defines foo.v - -=item --dump-tree - -Rarely needed. Enable writing .tree debug files with dumping level 3, -which dumps the standard critical stages. For details on the format see -the Verilator Internals manual. --dump-tree is enabled automatically with ---debug, so "--debug --no-dump-tree" may be useful if the dump files are -large and not desired. - -=item --dump-treei I - -=item --dump-treei-I I - -Rarely needed - for developer use. Set internal tree dumping level -globally to a specific dumping level or set the specified Verilator source -file to the specified tree dumping level (e.g. C<--dump-treei-V3Order 9>). -Level 0 disables dumps and is equivalent to "--no-dump-tree". Level 9 -enables dumping of every stage. - -=item --dump-tree-addrids - -Rarely needed - for developer use. Replace AST node addresses with short -identifiers in tree dumps to enhance readability. Each unique pointer value -is mapped to a unique identifier, but note that this is not necessarily -unique per node instance as an address might get reused by a newly allocated -node after a node with the same address has been dumped then freed. - -=item -E - -Preprocess the source code, but do not compile, as with 'gcc -E'. Output -is written to standard out. Beware of enabling debugging messages, as they -will also go to standard out. - -=item --error-limit I - -After this number of errors are encountered during Verilator run, exit. -Warnings are not counted in this limit. Defaults to 50. - -Does not affect simulation runtime errors, for those see -+verilator+error+limit. - -=item --exe - -Generate an executable. You will also need to pass additional .cpp files on -the command line that implement the main loop for your simulation. - -=item -F I - -Read the specified file, and act as if all text inside it was specified as -command line parameters. Any relative paths are relative to the directory -containing the specified file. See also -f. Note -F is fairly standard -across Verilog tools. - -=item -f I - -Read the specified file, and act as if all text inside it was specified as -command line parameters. Any relative paths are relative to the current -directory. See also -F. Note -f is fairly standard across Verilog tools. - -The file may contain // comments which are ignored to the end of the line. -Any $VAR, $(VAR), or ${VAR} will be replaced with the specified environment -variable. - -=item -FI I - -Force include of the specified C++ header file. All generated C++ files -will insert a #include of the specified file before any other includes. The -specified file might be used to contain define prototypes of custom -VL_VPRINTF functions, and may need to include verilatedos.h as this file is -included before any other standard includes. - -=item --flatten - -Force flattening of the design's hierarchy, with all modules, tasks and -functions inlined. Typically used with C<--xml-only>. Note flattening -large designs may require significant CPU time, memory and storage. - -=item -GI=I - -Overwrites the given parameter of the toplevel module. The value is limited -to basic data literals: - -=over 4 - -=item Verilog integer literals - -The standard Verilog integer literals are supported, so values like 32'h8, -2'b00, 4 etc. are allowed. Care must be taken that the single quote (I') is -properly escaped in an interactive shell, e.g., as -GWIDTH=8\'hx. - -=item C integer literals - -It is also possible to use C integer notation, including hexadecimal (0x..), -octal (0..) or binary (0b..) notation. - -=item Double literals - -Double literals must be one of the following styles: - - contains a dot (.) (e.g. 1.23) - - contains an exponent (e/E) (e.g. 12e3) - - contains p/P for hexadecimal floating point in C99 (e.g. 0x123.ABCp1) - -=item Strings - -Strings must be in double quotes (""). They must be escaped properly on the -command line, e.g. as -GSTR="\"My String\"" or -GSTR='"My String"'. - -=back - -=item --gate-stmts I - -Rarely needed. Set the maximum number of statements that may be present in -an equation for the gate substitution optimization to inline that equation. - -=item --gdb - -Run Verilator underneath an interactive GDB (or VERILATOR_GDB environment -variable value) session. See also --gdbbt. - -=item --gdbbt - -If --debug is specified, run Verilator underneath a GDB process and print a -backtrace on exit, then exit GDB immediately. Without --debug or if GDB -doesn't seem to work, this flag is ignored. Intended for easy creation of -backtraces by users; otherwise see the --gdb flag. - -=item --generate-key - -Generate a true-random key suitable for use with --protect-key, print it, -and exit immediately. - -=item --getenv I - -If the variable is declared in the environment, print it and exit -immediately. Otherwise, if it's built into Verilator (e.g. VERILATOR_ROOT), -print that and exit immediately. Otherwise, print a newline and exit -immediately. This can be useful in makefiles. See also -V, and the various -*.mk files. - -=item --help - -Displays this message and program version and exits. - -=item --hierarchical - -Enable hierarchical Verilation otherwise /*verilator hier_block*/ metacomment -is ignored. -See L. - -=item -II - -See -y. - -=item --if-depth I - -Rarely needed. Set the depth at which the IFDEPTH warning will fire, -defaults to 0 which disables this warning. - -=item +incdir+I - -See -y. - -=item --inhibit-sim - -Rarely needed. Create a "inhibitSim(bool)" function to enable and disable -evaluation. This allows an upper level testbench to disable modules that -are not important in a given simulation, without needing to recompile or -change the SystemC modules instantiated. - -=item --inline-mult I - -Tune the inlining of modules. The default value of 2000 specifies that up -to 2000 new operations may be added to the model by inlining, if more than -this number of operations would result, the module is not inlined. Larger -values, or a value < 1 will inline everything, will lead to longer compile -times, but potentially faster simulation speed. This setting is ignored -for very small modules; they will always be inlined, if allowed. - -=item -j - -Specify the level of parallelism for --build. must be a positive -integer specifying the maximum number of parallel build jobs, or can be -omitted. When is omitted, the build will not try to limit the number of -parallel build jobs but attempt to execute all independent build steps in -parallel. - -=item -LDFLAGS I - -Add specified C linker flags to the generated makefiles. For multiple -flags either pass them as a single argument with space separators quoted in -the shell (C<-LDFLAGS "-a -b">), or use multiple -LDFLAGS arguments -(C<-LDFLAGS -a -LDFLAGS -b>). - -When make is run on the generated makefile these will be passed to the C++ -linker (ld) *after* the primary file being linked. This flag is called --LDFLAGS as that's the traditional name in simulators; it's would have been -better called LDLIBS as that's the Makefile variable it controls. (In -Make, LDFLAGS is before the first object, LDLIBS after. -L libraries need -to be in the Make variable LDLIBS, not LDFLAGS.) - -=item --l2-name I - -Instead of using the module name when showing Verilog scope, use the name -provided. This allows simplifying some Verilator-embedded modeling -methodologies. Default is an l2-name matching the top module. The default -before 3.884 was "--l2-name v" - -For example, the program "module t; initial $display("%m"); endmodule" will -show by default "t". With "--l2-name v" it will print "v". - -=item --language I - -A synonym for C<--default-language>, for compatibility with other tools and -earlier versions of Verilator. - -=item +libext+I+I... - -Specify the extensions that should be used for finding modules. If for -example module I is referenced, look in I.I. Note +libext+ is -fairly standard across Verilog tools. Defaults to .v and .sv. - -=item --lint-only - -Check the files for lint violations only, do not create any other output. - -You may also want the -Wall option to enable messages that are considered -stylistic and not enabled by default. - -If the design is not to be completely Verilated see also the --bbox-sys and ---bbox-unsup options. - -=item -MAKEFLAGS - -When using --build, add the specified flag to the invoked make command line. -For multiple flags either pass them as a single argument with space separators -quoted in the shell (e.g. C<-MAKEFLAGS "-a -b">), or use multiple -MAKEFLAGS -arguments (e.g. C<-MAKEFLAGS -l -MAKEFLAGS -k>). Use of this option should not -be required for simple builds using the host toolchain. - -=item --max-num-width I - -Set the maximum number literal width (e.g. in 1024'd22 this it the 1024). -Defaults to 64K. - -=item --MMD -=item --no-MMD - -Enable/disable creation of .d dependency files, used for make dependency -detection, similar to gcc -MMD option. By default this option is enabled -for --cc or --sc modes. - -=item --MP - -When creating .d dependency files with --MMD, make phony targets. Similar -to gcc -MP option. - -=item --Mdir I - -Specifies the name of the Make object directory. All generated files will -be placed in this directory. If not specified, "obj_dir" is used. The -directory is created if it does not exist and the parent directories exist; -otherwise manually create the Mdir before calling Verilator. - -=item --mod-prefix I - -Specifies the name to prepend to all lower level classes. Defaults to -the same as --prefix. - -=item --no-clk I - -Prevent the specified signal from being marked as clock. See C<--clk>. - -=item --no-decoration - -When creating output Verilated code, minimize comments, white space, symbol -names and other decorative items, at the cost of greatly reduced -readability. This may assist C++ compile times. This will not typically -change the ultimate model's performance, but may in some cases. - -=item --no-pins64 - -Backward compatible alias for "--pins-bv 33". - -=item --no-relative-cfuncs - -Disable 'this->' references in generated functions, and instead Verilator -will generate absolute references starting from 'vlTOPp->'. This prevents -V3Combine from merging functions from multiple instances of the same -module, so it can grow the instruction stream. - -This is a work around for old compilers. Don't set this if your C++ -compiler supports __restrict__ properly, as GCC 4.5.x and newer do. For -older compilers, test if this switch gives you better performance or not. - -Compilers which don't honor __restrict__ will suspect that 'this->' -references and 'vlTOPp->' references may alias, and may write slow code -with extra loads and stores to handle the (imaginary) aliasing. Using only -'vlTOPp->' references allows these old compilers to produce tight code. - -=item --no-skip-identical -=item --skip-identical - -Rarely needed. Disables or enables skipping execution of Verilator if all -source files are identical, and all output files exist with newer dates. -By default this option is enabled for --cc or --sc modes only. - -=item +notimingchecks - -Ignored for compatibility with other simulators. - -=item -O0 - -Disables optimization of the model. - -=item -O3 - -Enables slow optimizations for the code Verilator itself generates (as -opposed to "-CFLAGS -O3" which effects the C compiler's optimization. -O3 -may improve simulation performance at the cost of compile time. This currently -sets --inline-mult -1. - -=item -OI - -Rarely needed. Enables or disables a specific optimizations, with the -optimization selected based on the letter passed. A lowercase letter -disables an optimization, an upper case letter enables it. This is -intended for debugging use only; see the source code for version-dependent -mappings of optimizations to -O letters. - -=item -o I - -Specify the name for the final executable built if using --exe. Defaults -to the --prefix if not specified. - -=item --no-order-clock-delay - -Rarely needed. Disables a bug fix for ordering of clock enables with -delayed assignments. This flag should only be used when suggested by the -developers. - -=item --output-split I - -Enables splitting the output .cpp files into multiple outputs. When a C++ -file exceeds the specified number of operations, a new file will be created -at the next function boundary. In addition, if the total output code size -exceeds the specified value, VM_PARALLEL_BUILDS will be set to 1 by default -in the generated make files, making parallel compilation possible. Using ---output-split should have only a trivial impact on model performance. But -can greatly improve C++ compilation speed. The use of I (set for you -if present at configure time) is also more effective with this option. - -This option is on by default with a value of 20000. To disable, pass with a -value of 0. - -=item --output-split-cfuncs I - -Enables splitting functions in the output .cpp files into multiple functions. -When a generated function exceeds the specified number of operations, a new -function will be created. With --output-split, this will enable the C++ -compiler to compile faster, at a small loss in performance that gets worse with -decreasing split values. Note that this option is stronger than --output-split -in the sense that --output-split will not split inside a function. - -Defaults to the value of --output-split, unless explicitly specified. - -=item --output-split-ctrace I - -Similar to --output-split-cfuncs, enables splitting trace functions in the -output .cpp files into multiple functions. - -Defaults to the value of --output-split, unless explicitly specified. - -=item -P - -With -E, disable generation of `line markers and blank lines, similar to -GCC -P flag. - -=item --pins64 - -Backward compatible alias for "--pins-bv 65". Note that's a 65, not a 64. - -=item --pins-bv I - -Specifies SystemC inputs/outputs of greater than or equal to I bits -wide should use sc_bv's instead of uint32/vluint64_t's. The default is -"--pins-bv 65", and the value must be less than or equal to 65. Versions -before Verilator 3.671 defaulted to "--pins-bv 33". The more sc_bv is -used, the worse for performance. Use the "/*verilator sc_bv*/" attribute -to select specific ports to be sc_bv. - -=item --pins-sc-uint - -Specifies SystemC inputs/outputs of greater than 2 bits wide should use -sc_uint between 2 and 64. When combined with the "--pins-sc-biguint" -combination, it results in sc_uint being used between 2 and 64 and -sc_biguint being used between 65 and 512. - -=item --pins-sc-biguint - -Specifies SystemC inputs/outputs of greater than 65 bits wide should use -sc_biguint between 65 and 512, and sc_bv from 513 upwards. When combined -with the "--pins-sc-uint" combination, it results in sc_uint being used -between 2 and 64 and sc_biguint being used between 65 and 512. - -=item --pins-uint8 - -Specifies SystemC inputs/outputs that are smaller than the --pins-bv -setting and 8 bits or less should use uint8_t instead of uint32_t. -Likewise pins of width 9-16 will use uint16_t instead of uint32_t. - -=item --pipe-filter I - -Rarely needed. Verilator will spawn the specified command as a subprocess -pipe, to allow the command to perform custom edits on the Verilog code -before it reaches Verilator. - -Before reading each Verilog file, Verilator will pass the file name to the -subprocess' stdin with 'read ""'. The filter may then read the file -and perform any filtering it desires, and feeds the new file contents back to -Verilator on stdout by first emitting a line defining the length in bytes of -the filtered output 'Content-Length: ', followed by the new filtered -contents. Output to stderr from the filter feeds through to Verilator's stdout -and if the filter exits with non-zero status Verilator terminates. See the -t/t_pipe_filter test for an example. - -To debug the output of the filter, try using the -E option to see -preprocessed output. - -=item --pp-comments - -With -E, show comments in preprocessor output. - -=item --prefix I - -Specifies the name of the top level class and makefile. Defaults to V -prepended to the name of the --top switch, or V prepended to the first -Verilog filename passed on the command line. - -=item --prof-cfuncs - -Modify the created C++ functions to support profiling. The functions will -be minimized to contain one "basic" statement, generally a single always -block or wire statement. (Note this will slow down the executable by ~5%.) -Furthermore, the function name will be suffixed with the basename of the -Verilog module and line number the statement came from. This allows gprof -or oprofile reports to be correlated with the original Verilog source -statements. See also L. - -=item --prof-threads - -Enable gantt chart data collection for threaded builds. - -Verilator will record the start and end time of each macro-task across a -number of calls to eval. (What is a macro-task? See the Verilator internals -document.) - -When profiling is enabled, the simulation runtime will emit a blurb of -profiling data in non-human-friendly form. The C script -will transform this into a nicer visual format and produce some related -statistics. - -=item --protect-key I - -Specifies the private key for --protect-ids. For best security this key -should be 16 or more random bytes, a reasonable secure choice is the output -of C. Typically, a key would be created by the -user once for a given protected design library, then every Verilator run -for subsequent versions of that library would be passed the same ---protect-key. Thus, if the input Verilog is similar between library -versions (Verilator runs), the Verilated code will likewise be mostly -similar. - -If --protect-key is not specified and a key is needed, Verilator will -generate a new key for every Verilator run. As the key is not saved, this -is best for security, but means every Verilator run will give vastly -different output even for identical input, perhaps harming compile times -(and certainly thrashing any I). - -=item --protect-ids - -Hash any private identifiers (variable, module, and assertion block names -that are not on the top level) into hashed random-looking identifiers, -resulting after compilation in protected library binaries that expose less -design information. This hashing uses the provided or default ---protect-key, see important details there. - -Verilator will also create a {prefix}__idmap.xml file which contains the -mapping from the hashed identifiers back to the original identifiers. This -idmap file is to be kept private, and is to assist mapping any simulation -runtime design assertions, coverage, or trace information, which will -report the hashed identifiers, back to the original design's identifier -names. - -Using DPI imports/exports is allowed and generally relatively safe in terms -of information disclosed, which is limited to the DPI function prototyptes. -Use of the VPI is not recommended as many design details may be exposed, -and an INSECURE warning will be issued. - -=item --protect-lib I - -Produces C++, Verilog wrappers and a Makefile which can in turn produce a -DPI library which can be used by Verilator or other simulators along with -the corresponding Verilog wrapper. The Makefile will build both a static -and dynamic version of the library named libI.a and libI.so -respectively. This is done because some simulators require a dynamic -library, but the static library is arguably easier to use if possible. ---protect-lib implies --protect-ids. - -This allows for the secure delivery of sensitive IP without the need for -encrypted RTL (i.e. IEEE P1735). See examples/make_protect_lib in the -distribution for a demonstration of how to build and use the DPI library. - -When using --protect-lib it is advised to also use C<--timescale-override -/1fs> to ensure the model has a time resolution that is always compatible -with the time precision of the upper instantiating module. - -=item --private - -Opposite of --public. Is the default; this option exists for backwards -compatibility. - -=item --public - -This is only for historical debug use. Using it may result in -mis-simulation of generated clocks. - -Declares all signals and modules public. This will turn off signal -optimizations as if all signals had a /*verilator public*/ comments and -inlining. This will also turn off inlining as if all modules had a -/*verilator public_module*/, unless the module specifically enabled it with -/*verilator inline_module*/. - -=item --public-flat-rw - -Declares all variables, ports and wires public as if they had /*verilator -public_flat_rw @ ()*/ comments. This will -make them VPI accessible by their flat name, but not turn off module -inlining. This is particularly useful in combination with --vpi. This may -also in some rare cases result in mis-simulation of generated clocks. -Instead of this global switch, marking only those signals that need -public_flat_rw is typically significantly better performing. - -=item -pvalue+I=I - -Overwrites the given parameter(s) of the toplevel module. See -G for a -detailed description. - -=item --quiet-exit - -When exiting due to an error, do not display the "Exiting due to Errors" -nor "Command Failed" messages. - -=item --relative-includes - -When a file references an include file, resolve the filename relative to -the path of the referencing file, instead of relative to the current -directory. - -=item --report-unoptflat - -Extra diagnostics for UNOPTFLAT warnings. This includes for each loop, the -10 widest variables in the loop, and the 10 most fanned out variables in -the loop. These are candidates for splitting into multiple variables to -break the loop. - -In addition produces a GraphViz DOT file of the entire strongly connected -components within the source associated with each loop. This is produced -irrespective of whether --dump-tree is set. Such graphs may help in -analyzing the problem, but can be very large indeed. - -Various commands exist for viewing and manipulating DOT files. For example -the I command can be used to convert a DOT file to a PDF for -printing. For example: - - dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot - -will generate a PDF Vt_unoptflat_simple_2_35_unoptflat.dot.pdf from the DOT -file. - -As an alternative, the I command can be used to view DOT files -interactively: - - xdot Vt_unoptflat_simple_2_35_unoptflat.dot - -=item --rr - -Run Verilator and record with rr. See: rr-project.org. - -=item --savable - -Enable including save and restore functions in the generated model. - -The user code must create a VerilatedSerialize or VerilatedDeserialze -object then calling the << or >> operators on the generated model and any -other data the process needs saved/restored. These functions are not -thread safe, and are typically called only by a main thread. - -For example: - - void save_model(const char* filenamep) { - VerilatedSave os; - os.open(filenamep); - os << main_time; // user code must save the timestamp, etc - os << *topp; - } - void restore_model(const char* filenamep) { - VerilatedRestore os; - os.open(filenamep); - os >> main_time; - os >> *topp; - } - -=item --sc - -Specifies SystemC output mode; see also --cc. - -=item --stats - -Creates a dump file with statistics on the design in {prefix}__stats.txt. - -=item --stats-vars - -Creates more detailed statistics, including a list of all the variables by -size (plain --stats just gives a count). See --stats, which is implied by -this. - -=item --structs-packed - -Converts all unpacked structures to packed structures and issues a UNPACKED -warning. Currently this is the default and --no-structs-packed will not -work. Specifying this option allows for forward compatibility when a -future version of Verilator no longer always packs unpacked structures. - -=item -sv - -Specifies SystemVerilog language features should be enabled; equivalent to -"--language 1800-2017". This option is selected by default, it exists for -compatibility with other simulators. - -=item +systemverilogext+I - -A synonym for C<+1800-2017ext+>I. - -=item --threads I - -=item --no-threads - -With --threads 0 or --no-threads, the default, the generated model is not -thread safe. With --threads 1, the generated model is single threaded but -may run in a multithreaded environment. With --threads N, where N >= 2, the -model is generated to run multithreaded on up to N threads. See -L. - -=item --threads-dpi all - -=item --threads-dpi none - -=item --threads-dpi pure - -When using --threads, controls which DPI imported tasks and functions are -considered thread safe. - -With --threads-dpi all, enable Verilator to assume all DPI imports are -threadsafe, and to use thread-local storage for communication with DPI, -potentially improving performance. Any DPI libraries need appropriate -mutexes to avoid undefined behavior. - -With --threads-dpi none, Verilator assume DPI imports are not thread safe, -and Verilator will serialize calls to DPI imports by default, potentially -harming performance. - -With --threads-dpi pure, the default, Verilator assumes DPI pure imports -are threadsafe, but non-pure DPI imports are not. - -=item --threads-max-mtasks I - -Rarely needed. When using --threads, specify the number of mtasks the -model is to be partitioned into. If unspecified, Verilator approximates a -good value. - -=item --timescale I/I - -Sets default timescale, timeunit and timeprecision for when `timescale does -not occur before a given module. Default is "1ps/1ps" (to match SystemC). -This is overridden by C<--timescale-override>. - -=item --timescale-override I/I - -=item --timescale-override /I - -Overrides all `timescales in sources. The timeunit may be left empty to -specify only to override the timeprecision, e.g. "/1fs". - -The time precision must be consistent with SystemC's -sc_set_time_resolution, or the C++ code instantiating the Verilated module. -As 1fs is the finest time precision it may be desirable to always use a -precision of 1fs. - -=item --top I - -=item --top-module I - -When the input Verilog contains more than one top level module, specifies -the name of the Verilog module to become the top level module, and sets the -default for --prefix if not explicitly specified. This is not needed with -standard designs with only one top. See also the MULTITOP warning section. - -=item --trace - -Adds waveform tracing code to the model using VCD format. This overrides -C<--trace-fst>. - -Verilator will generate additional {prefix}__Trace*.cpp files that will -need to be compiled. In addition verilated_vcd_sc.cpp (for SystemC traces) -or verilated_vcd_c.cpp (for both) must be compiled and linked in. If using -the Verilator generated Makefiles, these files will be added to the source -file lists for you. If you are not using the Verilator Makefiles, you will -need to add these to your Makefile manually. - -Having tracing compiled in may result in some small performance losses, -even when tracing is not turned on during model execution. - -See also C<--trace-threads>. - -=item --trace-coverage - -With --trace and --coverage-*, enable tracing to include a traced signal -for every --coverage-line or --coverage-user inserted coverage point, to -assist in debugging coverage items. Note --coverage-toggle does not get -additional signals added, as the original signals being toggle-analyzed are -already visible. - -The added signal will be a 32-bit value which will increment on each -coverage occurrence. Due to this, this option may greatly increase trace -file sizes and reduce simulation speed. - -=item --trace-depth I - -Specify the number of levels deep to enable tracing, for example ---trace-level 1 to only see the top level's signals. Defaults to the -entire model. Using a small number will decrease visibility, but greatly -improve simulation performance and trace file size. - -=item --trace-fst - -Enable FST waveform tracing in the model. This overrides C<--trace>. -See also C<--trace-threads>. - -=item --trace-max-array I - -Rarely needed. Specify the maximum array depth of a signal that may be -traced. Defaults to 32, as tracing large arrays may greatly slow traced -simulations. - -=item --trace-max-width I - -Rarely needed. Specify the maximum bit width of a signal that may be -traced. Defaults to 256, as tracing large vectors may greatly slow traced -simulations. - -=item --no-trace-params - -Disable tracing of parameters. - -=item --trace-structs - -Enable tracing to show the name of packed structure, union, and packed -array fields, rather than a single combined packed bus. Due to VCD file -format constraints this may result in significantly slower trace times and -larger trace files. - -=item --trace-threads I - -Enable waveform tracing using separate threads. This is typically faster in -simulation runtime but uses more total compute. This option is independent of, -and works with, both C<--trace> and C<--trace-fst>. Different trace formats can -take advantage of more trace threads to varying degrees. Currently VCD tracing -can utilize at most --trace-threads 1, and FST tracing can utilize at most ---trace-threads 2. This overrides C<--no-threads>. - -=item --trace-underscore - -Enable tracing of signals that start with an underscore. Normally, these -signals are not output during tracing. See also --coverage-underscore. - -=item -UI - -Undefines the given preprocessor symbol. - -=item --unroll-count I - -Rarely needed. Specifies the maximum number of loop iterations that may be -unrolled. See also BLKLOOPINIT warning. - -=item --unroll-stmts I - -Rarely needed. Specifies the maximum number of statements in a loop for -that loop to be unrolled. See also BLKLOOPINIT warning. - -=item --unused-regexp I - -Rarely needed. Specifies a simple regexp with * and ? that if a signal -name matches will suppress the UNUSED warning. Defaults to "*unused*". -Setting it to "" disables matching. - -=item -V - -Shows the verbose version, including configuration information compiled -into Verilator. (Similar to perl -V.) See also --getenv. - -=item -v I - -Read the filename as a Verilog library. Any modules in the file may be -used to resolve instances in the top level module, else ignored. Note -v -is fairly standard across Verilog tools. - -=item --no-verilate - -When using --build, disable generation of C++/SystemC code, and execute only -the build. This can be useful for rebuilding Verilated code produced by a -previous invocation of Verilator. - -=item +verilog1995ext+I - -=item +verilog2001ext+I - -Synonyms for C<+1364-1995ext+>I and C<+1364-2001ext+>I respectively - -=item --version - -Displays program version and exits. - -=item --vpi - -Enable use of VPI and linking against the verilated_vpi.cpp files. - -=item --waiver-output - -Generate a waiver file which contains all waiver statements to suppress the -warnings emitted during this Verilator run. This in particular is useful as -a starting point for solving linter warnings or suppressing them -systematically. - -The generated file is in the Verilator Configuration format, see -L, and can directly be consumed by Verilator. The -standard file extension is .vlt. - -=item -Wall - -Enable all code style warnings, including code style warnings that are -normally disabled by default. Equivalent to "-Wwarn-lint -Wwarn-style". -Excludes some specialty warnings, i.e. IMPERFECTSCH. - -=item -Werror-I - -Promote the specified warning message into an error message. This is -generally to discourage users from violating important site-wide rules, for -example C<-Werror-NOUNOPTFLAT>. - -=item -Wfuture-I - -Rarely needed. Suppress unknown Verilator comments or warning messages -with the given message code. This is used to allow code written with -pragmas for a later version of Verilator to run under a older version; add --Wfuture- arguments for each message code or comment that the new version -supports which the older version does not support. - -=item -Wno-I - -Disable the specified warning/error message. This will override any lint_on -directives in the source, i.e. the warning will still not be printed. - -=item -Wno-context - -Disable showing the suspected context of the warning message by quoting the -source text at the suspected location. This can be used to appease tools which -process the warning messages but may get confused by lines from the original -source. - -=item -Wno-fatal - -When warnings are detected, print them, but do not terminate Verilator. - -Having warning messages in builds is sloppy. It is strongly recommended -you cleanup your code, use inline lint_off, or use -Wno-... flags rather -than using this option. - -=item -Wno-lint - -Disable all lint related warning messages, and all style warnings. This is -equivalent to "-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE --Wno-CASEOVERLAP -Wno-CASEX -Wno-CASTCONST -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS --Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY --Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED --Wno-WIDTH" plus the list shown for Wno-style. - -It is strongly recommended you cleanup your code rather than using this -option, it is only intended to be use when running test-cases of code -received from third parties. - -=item -Wno-style - -Disable all code style related warning messages (note by default they are -already disabled). This is equivalent to "-Wno-DECLFILENAME -Wno-DEFPARAM --Wno-EOFNEWLINE -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY --Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED --Wno-VARHIDDEN". - -=item -Wpedantic - -Warn on any construct demanded by IEEE, and disable all Verilator -extensions that may interfere with IEEE compliance to the standard defined -with --default-language (etc). Similar to GCC's -Wpedantic. Rarely used, -and intended only for strict compliance tests. - -=item -Wwarn-I - -Enables the specified warning message. - -=item -Wwarn-lint - -Enable all lint related warning messages (note by default they are already -enabled), but do not affect style messages. This is equivalent to -"-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE --Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASTCONST -Wwarn-CASEWITHX -Wwarn-CMPCONST --Wwarn-COLONPLUS -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN --Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH". - -=item -Wwarn-style - -Enable all code style related warning messages. This is equivalent to -"-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-EOFNEWLINE --Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN --Wwarn-UNUSED -Wwarn-VARHIDDEN". - -=item --x-assign 0 - -=item --x-assign 1 - -=item --x-assign fast (default) - -=item --x-assign unique - -Controls the two-state value that is substituted when an explicit X value is -encountered in the source. C<--x-assign fast>, the default, converts all Xs to -whatever is best for performance. C<--x-assign 0> converts all Xs to 0s, and -is also fast. C<--x-assign 1> converts all Xs to 1s, this is nearly as fast as -0, but more likely to find reset bugs as active high logic will fire. Using -C<--x-assign unique> will result in all explicit Xs being replaced by a -constant value determined at runtime. The value is determined by calling a -function at initialization time. This enables randomization of Xs with -different seeds on different executions. This method is the slowest, but safest -for finding reset bugs. - -If using --x-assign unique, you may want to seed your random number generator -such that each regression run gets a different randomization sequence. The -simplest is to use the +verilator+seed runtime option. Alternatively use the -system's srand48() or for Windows srand() function to do this. You'll probably -also want to print any seeds selected, and code to enable rerunning with that -same seed so you can reproduce bugs. - -B This option applies only to values which are explicitly written as -X in the Verilog source code. Initial values of clocks are set to 0 unless ---x-initial-edge is specified. Initial values of all other state holding -variables are controlled with --x-initial. - -=item --x-initial 0 - -=item --x-initial fast - -=item --x-initial unique (default) - -Controls the two-state value that is used to initialize variables that are -not otherwise initialized. - -C<--x-initial 0>, initializes all otherwise uninitialized variables to zero. - -C<--x-initial unique>, the default, initializes variables using a function, -which determines the value to use each initialization. This gives greatest -flexibility and allows finding reset bugs. See L. - -C<--x-initial fast>, is best for performance, and initializes all variables to -a state Verilator determines is optimal. This may allow further code -optimizations, but will likely hide any code bugs relating to missing -resets. - -B This option applies only to initial values of variables. Initial -values of clocks are set to 0 unless --x-initial-edge is specified. - -=item --x-initial-edge - -Enables emulation of event driven simulators which generally trigger an -edge on a transition from X to 1 (C) or X to 0 (C). Thus -the following code, where C is uninitialized would set C to -C<1'b1> when C is first set to zero: - - reg res_n = 1'b0; - - always @(negedge rst_n) begin - if (rst_n == 1'b0) begin - res_n <= 1'b1; - end - end - - -In Verilator, by default, uninitialized clocks are given a value of zero, -so the above C block would not trigger. - -While it is not good practice, there are some designs that rely on X -E 0 triggering a C, particularly in reset sequences. Using ---x-initial-edge with Verilator will replicate this behavior. It will also -ensure that X E 1 triggers a C. - -B Some users have reported that using this option can affect -convergence, and that it may be necessary to use --converge-limit to -increase the number of convergence iterations. This may be another -indication of problems with the modeled design that should be addressed. - -=item --xml-only - -Create XML output only, do not create any other output. - -The XML format is intended to be used to leverage Verilator's parser and -elaboration to feed to other downstream tools. Be aware that the XML format -is still evolving; there will be some changes in future versions. - -=item --xml-output I - -Filename for XML output file. Using this option automatically sets ---xml-only. - -=item -y I - -Add the directory to the list of directories that should be searched for -include files or libraries. The three flags -y, +incdir and -I have -similar effect; +incdir and +y are fairly standard across Verilog tools while --I is used by many C++ compilers. - -Verilator defaults to the current directory ("-y .") and any specified ---Mdir, though these default paths are used after any user specified -directories. This allows '-y "$(pwd)"' to be used if absolute filenames -are desired for error messages instead of relative filenames. - -=back - - -=head1 SIMULATION RUNTIME ARGUMENTS - -The following are the arguments that may be passed to a Verilated -executable, provided that executable calls Verilated::commandArgs(). - -All simulation runtime arguments begin with +verilator, so that the user's -executable may skip over all +verilator arguments when parsing its command -line. - -=over 4 - -=item +verilator+debug - -Enable simulation runtime debugging. Equivalent to +verilator+debugi+4. - -=item +verilator+debugi+I - -Enable simulation runtime debugging at the provided level. - -=item +verilator+error+limit+I - -Set number of non-fatal errors (e.g. assertion failures) before exiting -simulation runtime. Also affects number of $stop calls needed before -exit. Defaults to 1. - -=item +verilator+help - -Display help and exit. - -=item +verilator+prof+threads+file+I - -When a model was Verilated using --prof-threads, sets the simulation runtime -filename to dump to. Defaults to "profile_threads.dat". - -=item +verilator+prof+threads+start+I - -When a model was Verilated using --prof-threads, the simulation runtime will -wait until $time is at this value (expressed in units of the time -precision), then start the profiling warmup, then capturing. Generally this -should be set to some time that is well within the normal operation of the -simulation, i.e. outside of reset. If 0, the dump is disabled. Defaults to -1. - -=item +verilator+prof+threads+window+I - -When a model was Verilated using --prof-threads, after $time reaches -+verilator+prof+threads+start, Verilator will warm up the profiling for -this number of eval() calls, then will capture the profiling of this number -of eval() calls. Defaults to 2, which makes sense for a -single-clock-domain module where it's typical to want to capture one -posedge eval() and one negedge eval(). - -=item +verilator+rand+reset+I - -When a model was Verilated using "-x-initial unique", sets the simulation -runtime initialization technique. 0 = Reset to zeros. 1 = Reset to -all-ones. 2 = Randomize. See L. - -=item +verilator+seed+I - -For $random and "-x-initial unique", set the simulation runtime random seed -value. If zero or not specified picks a value from the system random -number generator. - -=item +verilator+noassert - -Disable assert checking per runtime argument. This is the same as calling -"Verilated::assertOn(false)" in the model. - -=item +verilator+V - -Shows the verbose version, including configuration information. - -=item +verilator+version - -Displays program version and exits. - -=back - - -=head1 EXAMPLE C++ EXECUTION - -We'll compile this example into C++. For an extended and commented version -of what this C++ code is doing, see examples/make_tracing_c/sim_main.cpp. - - mkdir test_our - cd test_our - - cat >our.v <<'EOF' - module our; - initial begin $display("Hello World"); $finish; end - endmodule - EOF - - cat >sim_main.cpp <<'EOF' - #include "Vour.h" - #include "verilated.h" - int main(int argc, char** argv, char** env) { - VerilatedContext* contextp = new VerilatedContext; - contextp->commandArgs(argc, argv); - Vour* top = new Vour{contextp}; - while (!contextp->gotFinish()) { top->eval(); } - delete top; - delete contextp; - return 0; - } - EOF - -Next we need Verilator installed. See the README in the source kit for -various ways to install or point to Verilator binaries. In brief, if you -installed Verilator using the package manager of your operating system, or -did a "make install" to place Verilator into your default path, you do not -need anything special in your environment, and should not have -VERILATOR_ROOT set. However, if you installed Verilator from sources and -want to run Verilator out of where you compiled Verilator, you need to -point to the kit: - - # See above; don't do this if using an OS-distributed Verilator - export VERILATOR_ROOT=/path/to/where/verilator/was/installed - export PATH=$VERILATOR_ROOT/bin:$PATH - -Now we run Verilator on our little example. - - verilator -Wall --cc our.v --exe --build sim_main.cpp - -We can see the source code under the "obj_dir" directory. See the FILES -section below for descriptions of some of the files that were created. - - ls -l obj_dir - -(Verilator included a default compile rule and link rule, since we used ---exe and passed a .cpp file on the Verilator command line. Verilator also -then used C to build a final executable, since we used --build. You -can also write your own compile rules, and run make yourself as we'll show -in the SYSTEMC section. - -And now we run it: - - obj_dir/Vour - -And we get as output: - - Hello World - - our.v:2: Verilog $finish - -Really, you're better off writing a Makefile to do all this for you. Then, -when your source changes it will automatically run all of these steps; to -aid this Verilator can create a makefile dependency file. See the examples -directory in the distribution. - - -=head1 EXAMPLE SYSTEMC EXECUTION - -This is an example similar to the above, but using SystemC. - - mkdir test_our_sc - cd test_our_sc - - cat >our.v <<'EOF' - module our (clk); - input clk; // Clock is required to get initial activation - always @(posedge clk) - begin $display("Hello World"); $finish; end - endmodule - EOF - - cat >sc_main.cpp <<'EOF' - #include "Vour.h" - int sc_main(int argc, char** argv) { - Verilated::commandArgs(argc, argv); - sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true}; - Vour* top = new Vour{"top"}; - top->clk(clk); - while (!Verilated::gotFinish()) { sc_start(1, SC_NS); } - delete top; - return 0; - } - EOF - -See the README in the source kit for various ways to install or point to -Verilator binaries. In brief, if you installed Verilator using the package -manager of your operating system, or did a "make install" to place -Verilator into your default path, you do not need anything special in your -environment, and should not have VERILATOR_ROOT set. However, if you -installed Verilator from sources and want to run Verilator out of where you -compiled Verilator, you need to point to the kit: - - # See above; don't do this if using an OS-distributed Verilator - export VERILATOR_ROOT=/path/to/where/verilator/was/installed - export PATH=$VERILATOR_ROOT/bin:$PATH - -Now we run Verilator on our little example. - - verilator -Wall --sc our.v - -We then can compile it - - make -j -C obj_dir -f Vour.mk Vour__ALL.a - make -j -C obj_dir -f Vour.mk ../sc_main.o verilated.o - -And link with SystemC. Note your path to the libraries may vary, -depending on the operating system. - - cd obj_dir - export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists - export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH - # Might be needed if SystemC 2.3.0 - export SYSTEMC_CXX_FLAGS=-pthread - - g++ -L$SYSTEMC_LIBDIR ../sc_main.o Vour__ALL.a verilated.o \ - -o Vour -lsystemc - -And now we run it - - cd .. - obj_dir/Vour - -And we get the same output as the C++ example: - - Hello World - - our.v:2: Verilog $finish - -Really, you're better off using a Makefile to do all this for you. Then, -when your source changes it will automatically run all of these steps. See -the examples directory in the distribution. - - -=head1 EVALUATION LOOP - -When using SystemC, evaluation of the Verilated model is managed by the SystemC -kernel, and for the most part can be ignored. When using C++, the user -must call eval(), or eval_step() and eval_end_step(). - -1. When there is a single design instantiated at the C++ level that needs -to evaluate within a given context, just call designp->eval(). - -2. When there are multiple designs instantiated at the C++ level that need -to evaluate within a context, call first_designp->eval_step() then -->eval_step() on all other designs. Then call ->eval_end_step() on the -first design then all other designs. If there is only a single design, you -would call eval_step() then eval_end_step(); in fact eval() described above -is just a wrapper which calls these two functions. - -When eval() is called Verilator looks for changes in clock signals and -evaluates related sequential always blocks, such as computing always_ff @ -(posedge...) outputs. Then Verilator evaluates combinatorial logic. - -Note combinatorial logic is not computed before sequential always blocks -are computed (for speed reasons). Therefore it is best to set any non-clock -inputs up with a separate eval() call before changing clocks. - -Alternatively, if all always_ff statements use only the posedge of clocks, -or all inputs go directly to always_ff statements, as is typical, then you -can change non-clock inputs on the negative edge of the input clock, which -will be faster as there will be fewer eval() calls. - -For more information on evaluation, see docs/internals.rst in the -distribution. - - -=head1 BENCHMARKING & OPTIMIZATION - -For best performance, run Verilator with the "-O3 --x-assign fast --x-initial -fast --noassert" flags. The -O3 flag will require longer time to run -Verilator, and "--x-assign fast --x-initial fast" may increase the risk of -reset bugs in trade for performance; see the above documentation for these -flags. - -If using Verilated multithreaded, use C to ensure you are using -non-conflicting hardware resources. See L. - -Minor Verilog code changes can also give big wins. You should not have any -UNOPTFLAT warnings from Verilator. Fixing these warnings can result in -huge improvements; one user fixed their one UNOPTFLAT warning by making a -simple change to a clock latch used to gate clocks and gained a 60% -performance improvement. - -Beyond that, the performance of a Verilated model depends mostly on your -C++ compiler and size of your CPU's caches. Experience shows that large models -are often limited by the size of the instruction cache, and as such reducing -code size if possible can be beneficial. - -The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT, OPT_FAST, -OPT_SLOW and OPT_GLOBAL variables to control optimization. You can set these -when compiling the output of Verilator with Make, for example: - - make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a - -OPT_FAST specifies optimization flags for those parts of the model that are on -the fast path. This is mostly code that is executed every cycle. OPT_SLOW -applies to slow-path code, which executes rarely, often only once at the -beginning or end of simulation. Note that OPT_SLOW is ignored if -VM_PARALLEL_BUILDS is not 1, in which case all generated code will be compiled -in a single compilation unit using OPT_FAST. See also the C<--output-split> -option. The OPT_GLOBAL variable applies to common code in the runtime library -used by Verilated models (shipped in $VERILATOR_ROOT/include). Additional C++ -files passed on the verilator command line use OPT_FAST. The OPT variable -applies to all compilation units in addition to the specific OPT_* variables -described above. - -You can also use the -CFLAGS and/or -LDFLAGS options on the verilator command -line to pass flags directly to the compiler or linker. - -The default values of the OPT_* variables are chosen to yield good simulation -speed with reasonable C++ compilation times. To this end, OPT_FAST is set to -"-Os" by default. Higher optimization such as "-O2" or "-O3" may help (though -often they provide only a very small performance benefit), but compile times -may be excessively large even with medium sized designs. Compilation times can -be improved at the expense of simulation speed by reducing optimization, for -example with OPT_FAST="-O0". Often good simulation speed can be achieved with -OPT_FAST="-O1 -fstrict-aliasing" but with improved compilation times. Files -controlled by OPT_SLOW have little effect on performance and therefore OPT_SLOW -is empty by default (equivalent to "-O0") for improved compilation speed. In -common use-cases there should be little benefit in changing OPT_SLOW. -OPT_GLOBAL is set to "-Os" by default and there should rarely be a need to -change it. As the runtime library is small in comparison to a lot of Verilated -models, disabling optimization on the runtime library should not have a -serious effect on overall compilation time, but may have detrimental effect on -simulation speed, especially with tracing. In addition to the above, for best -results use OPT="-march=native", the latest Clang compiler (about 10% faster -than GCC), and link statically. - -Generally the answer to which optimization level gives the best user experience -depends on the use case and some experimentation can pay dividends. For a -speedy debug cycle during development, especially on large designs where C++ -compilation speed can dominate, consider using lower optimization to get to an -executable faster. For throughput oriented use cases, for example regressions, -it is usually worth spending extra compilation time to reduce total CPU time. - -If you will be running many simulations on a single model, you can investigate -profile guided optimization. With GCC, using -fprofile-arcs, then --fbranch-probabilities will yield another 15% or so. - -Modern compilers also support link-time optimization (LTO), which can help -especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in both -compilation and link. Note LTO may cause excessive compile times on large -designs. - -Unfortunately, using the optimizer with SystemC files can result in compilation -taking several minutes. (The SystemC libraries have many little inlined -functions that drive the compiler nuts.) - -If you are using your own makefiles, you may want to compile the Verilated -code with -DVL_INLINE_OPT=inline. This will inline functions, however this -requires that all cpp files be compiled in a single compiler run. - -You may uncover further tuning possibilities by profiling the Verilog code. -Use Verilator's --prof-cfuncs, then GCC's -g -pg. You can then run -either oprofile or gprof to see where in the C++ code the time is spent. -Run the gprof output through verilator_profcfunc and it will tell you what -Verilog line numbers on which most of the time is being spent. - -When done, please let the author know the results. We like to keep tabs on -how Verilator compares, and may be able to suggest additional improvements. - - -=head1 FILES - -All output files are placed in the output directory specified with the -C<--Mdir> option, or "obj_dir" if not specified. - -Verilator creates the following files in the output directory: - -For --make gmake, it creates: - - {prefix}.mk // Make include file for compiling - {prefix}_classes.mk // Make include file with class names - {prefix}_hier.mk // Make file for hierarchy blocks - {prefix}_hierMkArgs.f // Arguments for hierarchical Verilation. - -For --make cmake, it creates: - - {prefix}.cmake // CMake include script for compiling - {prefix}_hierCMakeArgs.f // Arguments for hierarchical Verilation. - -For -cc and -sc mode, it also creates: - - {prefix}.cpp // Top level C++ file - {prefix}.h // Top level header - {prefix}__Slow{__n}.cpp // Constructors and infrequent cold routines - {prefix}{__n}.cpp // Additional top C++ files (--output-split) - {prefix}{each_verilog_module}.cpp // Lower level internal C++ files - {prefix}{each_verilog_module}.h // Lower level internal header files - {prefix}{each_verilog_module}{__n}.cpp // Additional lower C++ files (--output-split) - -For --hierarchy mode, it creates: - {prefix}__hierVer.d // Make dependencies of the top module in the - hierarchical Verilation - {prefix}__hier.dir/ // Directory to store .dot, .vpp, .tree of the - top module in the hierarchical Verilation - V{hier_block}/ // Directory to Verilate each hierarchy block - -In certain debug and other modes, it also creates: - - {prefix}.xml // XML tree information (--xml) - {prefix}__Dpi.cpp // DPI import and export wrappers - {prefix}__Dpi.h // DPI import and export declarations - {prefix}__Inlines.h // Inline support functions - {prefix}__Syms.cpp // Global symbol table C++ - {prefix}__Syms.h // Global symbol table header - {prefix}__Trace__Slow{__n}.cpp // Wave file generation code (--trace) - {prefix}__Trace{__n}.cpp // Wave file generation code (--trace) - {prefix}__cdc.txt // Clock Domain Crossing checks (--cdc) - {prefix}__stats.txt // Statistics (--stats) - {prefix}__idmap.txt // Symbol demangling (--protect-ids) - -It also creates internal files that can be mostly ignored: - - {mod_prefix}_{each_verilog_module}{__n}.vpp // Pre-processed verilog - {prefix}__ver.d // Make dependencies (-MMD) - {prefix}__verFiles.dat // Timestamps for skip-identical - {prefix}{misc}.dot // Debugging graph files (--debug) - {prefix}{misc}.tree // Debugging files (--debug) - -After running Make, the C++ compiler may produce the following: - - verilated{misc}.d // Intermediate dependencies - verilated{misc}.o // Intermediate objects - {mod_prefix}{misc}.d // Intermediate dependencies - {mod_prefix}{misc}.o // Intermediate objects - {prefix} // Final executable (w/--exe argument) - {prefix}__ALL.a // Library of all Verilated objects - {prefix}__ALL.cpp // Include of all code for single compile - {prefix}{misc}.d // Intermediate dependencies - {prefix}{misc}.o // Intermediate objects - - -=head1 ENVIRONMENT - -=over 4 - -=item LD_LIBRARY_PATH - -A generic Linux/OS variable specifying what directories have shared object -(.so) files. This path should include SystemC and any other shared objects -needed at simulation runtime. - -=item MAKE - -Names the executable of the make command invoked when using the --build option. -Some operating systems may require "gmake" to this variable to launch GNU make. -If this variable is not specified, "make" is used. - -=item OBJCACHE - -Optionally specifies a caching or distribution program to place in front of -all runs of the C++ compiler. For example, "ccache". If using distcc or -icecc/icecream, they would generally be run under cache; see the -documentation for those programs. If OBJCACHE is not set, and at configure -time ccache was present, ccache will be used as a default. - -=item SYSTEMC - -Deprecated. Used only if SYSTEMC_INCLUDE or SYSTEMC_LIBDIR is not set. If -set, specifies the directory containing the SystemC distribution. If not -specified, it will come from a default optionally specified at configure -time (before Verilator was compiled). - -=item SYSTEMC_ARCH - -Deprecated. Used only if SYSTEMC_LIBDIR is not set. Specifies the -architecture name used by the SystemC kit. This is the part after the dash -in the lib-{...} directory name created by a 'make' in the SystemC -distribution. If not set, Verilator will try to intuit the proper setting, -or use the default optionally specified at configure time (before Verilator -was compiled). - -=item SYSTEMC_CXX_FLAGS - -Specifies additional flags that are required to be passed to GCC when -building the SystemC model. System 2.3.0 may need this set to "-pthread". - -=item SYSTEMC_INCLUDE - -If set, specifies the directory containing the systemc.h header file. If -not specified, it will come from a default optionally specified at -configure time (before Verilator was compiled), or computed from -SYSTEMC/include. - -=item SYSTEMC_LIBDIR - -If set, specifies the directory containing the libsystemc.a library. If not -specified, it will come from a default optionally specified at configure -time (before Verilator was compiled), or computed from -SYSTEMC/lib-SYSTEMC_ARCH. - -=item VERILATOR_BIN - -If set, specifies an alternative name of the C binary. May be -used for debugging and selecting between multiple operating system builds. - -=item VERILATOR_COVERAGE_BIN - -If set, specifies an alternative name of the C. -May be used for debugging and selecting between multiple operating system -builds. - -=item VERILATOR_GDB - -If set, the command to run when using the --gdb option, such as "ddd". If -not specified, it will use "gdb". - -=item VERILATOR_ROOT - -Specifies the directory containing the distribution kit. This is used to -find the executable, Perl library, and include files. If not specified, it -will come from a default optionally specified at configure time (before -Verilator was compiled). It should not be specified if using a pre-compiled -Verilator package as the hard-coded value should be correct. - -=back - - -=head1 CONNECTING TO C++ - -Verilator creates a I.h and I.cpp file for the top level -module, together with additional .h and .cpp files for internals. See the -examples directory in the kit for examples. - -After the model is created, there will be a I.mk file that may -be used with Make to produce a I__ALL.a file with all required -objects in it. This is then linked with the user's C++ main loop to -create the simulation executable. - -The user must write the C++ main loop of the simulation. Here is a simple -example: - - #include // Defines common routines - #include // Need std::cout - #include "Vtop.h" // From Verilating "top.v" - - Vtop *top; // Instantiation of module - - vluint64_t main_time = 0; // Current simulation time - // This is a 64-bit integer to reduce wrap over issues and - // allow modulus. This is in units of the timeprecision - // used in Verilog (or from --timescale-override) - - double sc_time_stamp() { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does - } - - int main(int argc, char** argv) { - Verilated::commandArgs(argc, argv); // Remember args - - top = new Vtop; // Create instance - - top->reset_l = 0; // Set some inputs - - while (!Verilated::gotFinish()) { - if (main_time > 10) { - top->reset_l = 1; // Deassert reset - } - if ((main_time % 10) == 1) { - top->clk = 1; // Toggle clock - } - if ((main_time % 10) == 6) { - top->clk = 0; - } - top->eval(); // Evaluate model - cout << top->out << endl; // Read a output - main_time++; // Time passes... - } - - top->final(); // Done simulating - // // (Though this example doesn't get here) - delete top; - } - -Note signals are read and written as member variables of the model. -You call the eval() method to evaluate the model. When the simulation is -complete call the final() method to execute any SystemVerilog final blocks, -and complete any assertions. See L. - - -=head1 CONNECTING TO SYSTEMC - -Verilator will convert the top level module to a SC_MODULE. This module -will plug directly into a SystemC netlist. - -The SC_MODULE gets the same pinout as the Verilog module, with the -following type conversions: Pins of a single bit become bool. Pins 2-32 -bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or -vluint64_t's depending on the --no-pins64 switch. Wider pins become sc_bv's. -(Uints simulate the fastest so are used where possible.) - -Lower modules are not pure SystemC code. This is a feature, as using the -SystemC pin interconnect scheme everywhere would reduce performance by an -order of magnitude. - - -=head1 DIRECT PROGRAMMING INTERFACE (DPI) - -Verilator supports SystemVerilog Direct Programming Interface import and -export statements. Only the SystemVerilog form ("DPI-C") is supported, not -the original Synopsys-only DPI. - -=head2 DPI Example - -In the SYSTEMC example above, if you wanted to import C++ functions into -Verilog, put in our.v: - - import "DPI-C" function int add (input int a, input int b); - - initial begin - $display("%x + %x = %x", 1, 2, add(1,2)); - endtask - -Then after Verilating, Verilator will create a file Vour__Dpi.h with the -prototype to call this function: - - extern int add(int a, int b); - -From the sc_main.cpp file (or another .cpp file passed to the Verilator -command line, or the link), you'd then: - - #include "svdpi.h" - #include "Vour__Dpi.h" - int add(int a, int b) { return a+b; } - -=head2 DPI System Task/Functions - -Verilator extends the DPI format to allow using the same scheme to -efficiently add system functions. Simply use a dollar-sign prefixed system -function name for the import, but note it must be escaped. - - export "DPI-C" function integer \$myRand; - - initial $display("myRand=%d", $myRand()); - -Going the other direction, you can export Verilog tasks so they can be -called from C++: - - export "DPI-C" task publicSetBool; - - task publicSetBool; - input bit in_bool; - var_bool = in_bool; - endtask - -Then after Verilating, Verilator will create a file Vour__Dpi.h with the -prototype to call this function: - - extern void publicSetBool(svBit in_bool); - -From the sc_main.cpp file, you'd then: - - #include "Vour__Dpi.h" - publicSetBool(value); - -Or, alternatively, call the function under the design class. This isn't -DPI compatible but is easier to read and better supports multiple designs. - - #include "Vour__Dpi.h" - Vour::publicSetBool(value); - // or top->publicSetBool(value); - -Note that if the DPI task or function accesses any register or net within the -RTL, it will require a scope to be set. This can be done using the standard -functions within svdpi.h, after the module is instantiated, but before the -task(s) and/or function(s) are called. - -For example, if the top level module is instantiated with the name "dut" and -the name references within tasks are all hierarchical (dotted) names with -respect to that top level module, then the scope could be set with - - #include "svdpi.h" - ... - svSetScope(svGetScopeFromName("TOP.dut")); - -(Remember that Verilator adds a "TOP" to the top of the module hierarchy.) - -Scope can also be set from within a DPI imported C function that has been -called from Verilog by querying the scope of that function. See the -sections on DPI Context Functions and DPI Header Isolation below and the -comments within the svdpi.h header for more information. - -=head2 DPI Imports that access signals - -If a DPI import accesses a signal through the VPI Verilator will not be -able to know what variables are accessed and may schedule the code -inappropriately. Ideally pass the values as inputs/outputs so the VPI is -not required. Alternatively a workaround is to use a non-inlined task as a -wrapper: - - logic din; - - // This DPI function will read "din" - import "DPI-C" context function void dpi_that_accesses_din(); - - always @(...) - dpi_din_args(din); - - task dpi_din_args(input din); - /* verilator no_inline_task */ - dpi_that_accesses_din(); - endtask - -=head2 DPI Display Functions - -Verilator allows writing $display like functions using this syntax: - - import "DPI-C" function void - \$my_display(input string formatted /*verilator sformat*/ ); - -The /*verilator sformat*/ indicates that this function accepts a $display -like format specifier followed by any number of arguments to satisfy the -format. - -=head2 DPI Context Functions - -Verilator supports IEEE DPI Context Functions. Context imports pass the -simulator context, including calling scope name, and filename and line -number to the C code. For example, in Verilog: - - import "DPI-C" context function int dpic_line(); - initial $display("This is line %d, again, line %d\n", `line, dpic_line()); - -This will call C++ code which may then use the svGet* functions to read -information, in this case the line number of the Verilog statement that -invoked the dpic_line function: - - int dpic_line() { - // Get a scope: svScope scope = svGetScope(); - - const char* scopenamep = svGetNameFromScope(scope); - assert(scopenamep); - - const char* filenamep = ""; - int lineno = 0; - if (svGetCallerInfo(&filenamep, &lineno)) { - printf("dpic_line called from scope %s on line %d\n", - scopenamep, lineno); - return lineno; - } else { - return 0; - } - } - -See the IEEE Standard for more information. - -=head2 DPI Header Isolation - -Verilator places the IEEE standard header files such as svdpi.h into a -separate include directory, vltstd (VeriLaTor STandarD). When compiling -most applications $VERILATOR_ROOT/include/vltstd would be in the include -path along with the normal $VERILATOR_ROOT/include. However, when -compiling Verilated models into other simulators which have their own -svdpi.h and similar standard files with different contents, the vltstd -directory should not be included to prevent picking up incompatible -definitions. - -=head2 Public Functions - -Instead of DPI exporting, there's also Verilator public functions, which -are slightly faster, but less compatible. - - -=head1 VERIFICATION PROCEDURAL INTERFACE (VPI) - -Verilator supports a very limited subset of the VPI. This subset allows -inspection, examination, value change callbacks, and depositing of values -to public signals only. - -VPI is enabled with the verilator --vpi switch. - -To access signals via the VPI, Verilator must be told exactly which signals -are to be accessed. This is done using the Verilator public pragmas -documented below. - -Verilator has an important difference from an event based simulator; signal -values that are changed by the VPI will not immediately propagate their -values, instead the top level header file's eval() method must be called. -Normally this would be part of the normal evaluation (i.e. the next clock -edge), not as part of the value change. This makes the performance of VPI -routines extremely fast compared to event based simulators, but can confuse -some test-benches that expect immediate propagation. - -Note the VPI by its specified implementation will always be much slower -than accessing the Verilator values by direct reference -(structure->module->signame), as the VPI accessors perform lookup in -functions at simulation runtime requiring at best hundreds of instructions, -while the direct references are evaluated by the compiler and result in -only a couple of instructions. - -For signal callbacks to work the main loop of the program must call -VerilatedVpi::callValueCbs(). - -=head2 VPI Example - -In the below example, we have readme marked read-only, and writeme which if -written from outside the model will have the same semantics as if it -changed on the specified clock edge. - - cat >our.v <<'EOF' - module our (input clk); - reg readme /*verilator public_flat_rd*/; - reg writeme /*verilator public_flat_rw @(posedge clk) */; - initial $finish; - endmodule - EOF - -There are many online tutorials and books on the VPI, but an example that -accesses the above signal "readme" would be: - - cat >sim_main.cpp <<'<eval(); - VerilatedVpi::callValueCbs(); // For signal callbacks - read_and_check(); - } - delete top; - return 0; - } - EOF - - -=head1 CROSS COMPILATION - -Verilator supports cross-compiling Verilated code. This is generally used -to run Verilator on a Linux system and produce C++ code that is then compiled -on Windows. - -Cross compilation involves up to three different OSes. The build system is -where you configured and compiled Verilator, the host system where you run -Verilator, and the target system where you compile the Verilated code and -run the simulation. - -Currently, Verilator requires the build and host system type to be the -same, though the target system type may be different. To support this, -./configure and make Verilator on the build system. Then, run Verilator on -the host system. Finally, the output of Verilator may be compiled on the -different target system. - -To support this, none of the files that Verilator produces will reference -any configure generated build-system specific files, such as config.h -(which is renamed in Verilator to config_build.h to reduce confusion.) The -disadvantage of this approach is that include/verilatedos.h must -self-detect the requirements of the target system, rather than using -configure. - -The target system may also require edits to the Makefiles, the simple -Makefiles produced by Verilator presume the target system is the same type -as the build system. - -=head2 CMake - -Verilator can be run using CMake, which takes care of both running -Verilator and compiling the output. There is a CMake example in the -examples/ directory. The following is a minimal CMakeLists.txt that -would build the code listed in "EXAMPLE C++ EXECUTION": - - project(cmake_example) - find_package(verilator HINTS $ENV{VERILATOR_ROOT}) - add_executable(Vour sim_main.cpp) - verilate(Vour SOURCES our.v) - -find_package will automatically find an installed copy of Verilator, or use -a local build if VERILATOR_ROOT is set. - -It is recommended to use CMake >= 3.12 and the Ninja generator, though -other combinations should work. To build with CMake, change to the folder -containing CMakeLists.txt and run: - - mkdir build - cd build - cmake -GNinja .. - ninja - -Or to build with your system default generator: - - mkdir build - cd build - cmake .. - cmake --build . - -If you're building the example you should have an executable to run: - - ./Vour - -The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and -VERILATOR_BIN to the appropriate values, and also creates a verilate() -function. verilate() will automatically create custom commands to run -Verilator and add the generated C++ sources to the target specified. - - verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name] - [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE] - [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...] - [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...]) - -Lowercase and ... should be replaced with arguments, the uppercase parts -delimit the arguments and can be passed in any order, or left out entirely -if optional. - -verilate(target ...) can be called multiple times to add other verilog -modules to an executable or library target. - -When generating Verilated SystemC sources, you should also include the -SystemC include directories and link to the SystemC libraries. - -Verilator's CMake support provides a convenience function to automatically -find and link to the SystemC library. It can be used as: - - verilator_link_systemc(target) - -where target is the name of your target. - -The search paths can be configured by setting some variables: - -- The variables SYSTEMC_INCLUDE and SYSTEMC_LIBDIR to give a direct path to -the SystemC include an library path. - -- SYSTEMC_ROOT to set the installation prefix of an installed SystemC - library. - -- SYSTEMC to set the installation prefix of an installed SystemC library - (same as above). - -- When using Accellera's SystemC with CMake support, a CMake target is -available that simplifies the above steps. This will only work if the -SystemC installation can be found by CMake. This can be configured by -setting the CMAKE_PREFIX_PATH variable during CMake configuration. - -Don't forget to set the same C++ standard for the Verilated sources as the -SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS environment -variable. - -=over 4 - -=item target - -Name of a target created by add_executable or add_library. - -=item SOURCES - -List of Verilog files to Verilate. Must have at least one file. - -=item PREFIX - -Optional. Sets the Verilator output prefix. Defaults to the name of the -first source file with a "V" prepended. Must be unique in each call to -verilate(), so this is necessary if you build a module multiple times with -different parameters. Must be a valid C++ identifier, i.e. contains no -white space and only characters A-Z, a-z, 0-9 or _. - -=item TOP_MODULE - -Optional. Sets the name of the top module. Defaults to the name of the -first file in the SOURCES array. - -=item TRACE - -Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS --trace". - -=item TRACE_FST - -Optional. Enables FST tracing if present, equivalent to "VERILATOR_ARGS --trace-fst". - -=item SYSTEMC - -Optional. Enables SystemC mode, defaults to C++ if not specified. - -=item COVERAGE - -Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS --coverage" - -=item INCLUDE_DIRS - -Optional. Sets directories that Verilator searches (same as -y). - -=item OPT_SLOW - -Optional. Set compiler flags for the slow path. You may want to reduce the -optimization level to improve compile times with large designs. - -=item OPT_FAST - -Optional. Set compiler flags for the fast path. - -=item OPT_GLOBAL - -Optional. Set compiler flags for the common runtime library used by Verilated -models. - -=item DIRECTORY - -Optional. Set the verilator output directory. It is preferable to use the -default, which will avoid collisions with other files. - -=item VERILATOR_ARGS - -Optional. Extra arguments to Verilator. Do not specify --Mdir or --prefix -here, use DIRECTORY or PREFIX. - -=back - -=head1 HIERARCHICAL VERILATION - -Large designs may take long (e.g. 10+ minutes) and huge memory (e.g. 100+GB) -to Verilate. One workaround is hierarchical Verilation, it is to Verilate -each moderate size of building blocks and finally combine the building blocks. -The building block will be called "hierarchy block" later. - -The current hierarchical Verilation is based on protect-lib. Each hierarchy -block is Verilated to protect-lib. User modules of the hierarchy blocks will see -a tiny wrapper generated by protect-lib instead of the actual design. - -=head2 Usage - -All user need to do is mark moderate size of module as hierarchy block and pass ---hierarchical option to verilator command. -There are two ways to mark a module: - - a) Write /* verilator hier_block */ metacomment in HDL code - See L for more detail. - b) add hier_block line in the configuration file. - See C in L for example. - -You don't have to take care of hierarchical blocks when compiling -Verilated C++ code. You can compile as usual. - make -C obj_dir -f Vtop_module_name.mk - -See also "Overlapping Verilation and compilation" to get executable quickly. - -=head2 Limitations - -Because hierarchy blocks are Verilated to protect-lib, they have some - limitations such as: - - The block cannot be accessed using dot (.) from upper module. - Signals in the block cannot be traced. - Modport cannot be used at the hirarchical block boundary. - -On the other hand, the following usage is supported. - - - Nested hierarchy block. A hierarchy block may instantiate other - hierarchy blocks. - - Parameterized hierarchy block. Parameters of a hierarchy block can be - overridden using #(.param_name(value)) construct. - -The simulation speed may not be as fast as flat Verilation, in which -all modules are globally scheduled. - -=head2 Overlapping Verilation and compilation - -Verilator needs to run N + 2 times in hierarchical Verilation, where N is -the number of hierarchy blocks. -1 of 2 is for the top module which refers wrappers of all other hierarchy -blocks. -The other 1 of 2 is the initial run that searches modules marked with -/*verilator hier_block*/ metacomment and creates a plan and write in -(prefix)_hier.mk. -This initial run internally invokes other N + 1 runs, so you don't have -to care about these N + 1 times of run. - -If -j option is specified, Verilation for hierarchy blocks -runs in parallel. - -If --build option is also specified, C++ compilation also runs as soon as -a hierarchy block is Verilated. C++ compilation and Verilation for -other hierarchy blocks run simultaneously. - -=head1 MULTITHREADING - -Verilator supports multithreaded simulation models. - -With --no-threads, the default, the model is not thread safe, and any use -of more than one thread calling into one or even different Verilated models -may result in unpredictable behavior. This gives the highest single thread -performance. - -With --threads 1, the generated model is single threaded, however the -support libraries are multithread safe. This allows different -instantiations of model(s) to potentially each be run under a different -thread. All threading is the responsibility of the user's C++ testbench. - -With --threads N, where N is at least 2, the generated model will be -designed to run in parallel on N threads. The thread calling eval() -provides one of those threads, and the generated model will create and -manage the other N-1 threads. It's the client's responsibility not to -oversubscribe the available CPU cores. Under CPU oversubscription, the -Verilated model should not livelock nor deadlock, however, you can expect -performance to be far worse than it would be with proper ratio of -threads and CPU cores. - -The remainder of this section describe behavior with --threads 1 or ---threads N (not --no-threads). - -VL_THREADED is defined when compiling a threaded Verilated module, causing -the Verilated support classes become threadsafe. - -The thread used for constructing a model must be the same thread that -calls eval() into the model, this is called the "eval thread". The thread -used to perform certain global operations such as saving and tracing must -be done by a "main thread". In most cases the eval thread and main thread -are the same thread (i.e. the user's top C++ testbench runs on a single -thread), but this is not required. - -The --trace-threads options can be used to produce trace dumps using multiple -threads. If --trace-threads is set without --threads, then --trace-threads will -imply --threads 1, i.e.: the support libraries will be thread safe. - -With --trace-threads 0, trace dumps are produced on the main thread. This again -gives the highest single thread performance. - -With --trace-threads N, where N is at least 1, N additional threads will be -created and managed by the trace files (e.g.: VerilatedVcdC or VerilatedFstC), -to generate the trace dump. The main thread will be released to proceed with -execution as soon as possible, though some blocking of the main thread is still -necessary while capturing the trace. Different trace formats can utilize a -various number of threads. See the --trace-threads option. - -When running a multithreaded model, the default Linux task scheduler often -works against the model, by assuming threads are short lived, and thus -often schedules threads using multiple hyperthreads within the same -physical core. For best performance use the C program to (when the -threading count fits) select unique physical cores on the same socket. The -same applies for --trace-threads as well. - -As an example, if a model was Verilated with "--threads 4", we consult - - egrep 'processor|physical id|core id' /proc/cpuinfo - -To select cores 0, 1, 2, and 3 that are all located on the same socket (0) -but different physical cores. (Also useful is "numactl --hardware", or -C but those doesn't show Hyperthreading cores.) Then we execute - - numactl -m 0 -C 0,1,2,3 -- verilated_executable_name - -This will limit memory to socket 0, and threads to cores 0, 1, 2, 3, -(presumably on socket 0) optimizing performance. Of course this must be -adjusted if you want another simulator using e.g. socket 1, or if you -Verilated with a different number of threads. To see what CPUs are -actually used, use --prof-threads. - -=head2 Multithreaded Verilog and Library Support - -$display/$stop/$finish are delayed until the end of an eval() call in order -to maintain ordering between threads. This may result in additional tasks -completing after the $stop or $finish. - -=over 4 - -If using --coverage, the coverage routines are fully thread safe. - -If using --dpi, Verilator assumes pure DPI imports are thread safe, -balancing performance versus safety. See --threads-dpi. - -If using --savable, the save/restore classes are not multithreaded and -must be called only by the eval thread. - -If using --sc, the SystemC kernel is not thread safe, therefore the eval -thread and main thread must be the same. - -If using --trace, the tracing classes must be constructed and called from -the main thread. - -If using --vpi, since SystemVerilog VPI was not architected by IEEE to be -multithreaded, Verilator requires all VPI calls are only made from the main -thread. - -=back - - -=head1 CONFIGURATION FILES - -In addition to the command line, warnings and other features may be -controlled by configuration files, typically named with the .vlt extension -(what makes it a configuration file is the `verilator_config directive). An -example: - - `verilator_config - lint_off -rule WIDTH - lint_off -rule CASEX -file "silly_vendor_code.v" - -This disables WIDTH warnings globally, and CASEX for a specific file. - -Configuration files are fed through the normal Verilog preprocessor prior to -parsing, so `ifdefs, `defines, and comments may be used as if it were normal -Verilog code. - -Note that file or line-specific configuration only applies to files read -after the configuration file. It is therefore recommended to pass the -configuration file to Verilator as the first file. - -The grammar of configuration commands is as follows: - -=over 4 - -=item `verilator_config - -Take remaining text and treat it as Verilator configuration commands. - -=item coverage_on [-file "" [-lines [ - ]]] - -=item coverage_off [-file "" [-lines [ - ]]] - -Enable/disable coverage for the specified filename (or wildcard with '*' or -'?', or all files if omitted) and range of line numbers (or all lines if -omitted). Often used to ignore an entire module for coverage analysis -purposes. - -=item lint_on [-rule ] [-file "" [-lines [ - ]]] - -=item lint_off [-rule ] [-file "" [-lines [ - ]]] - -=item lint_off [-rule ] [-file ""] [-match ""] - -Enable/disables the specified lint warning, in the specified filename (or -wildcard with '*' or '?', or all files if omitted) and range of line -numbers (or all lines if omitted). - -With lint_off using '*' will override any lint_on directives in the source, -i.e. the warning will still not be printed. - -If the -rule is omitted, all lint warnings (see list in -Wno-lint) are -enabled/disabled. This will override all later lint warning enables for -the specified region. - -If -match is set the linter warnings are matched against this (wildcard) -string and are waived in case they match and iff rule and file (with wildcard) -also match. - -In previous versions -rule was named -msg. The latter is deprecated, but -still works with a deprecation info, it may be removed in future versions. - -=item tracing_on [-file "" [-lines [ - ]]] - -=item tracing_off [-file "" [-lines [ - ]]] - -Enable/disable waveform tracing for all future signals declared in the -specified filename (or wildcard with '*' or '?', or all files if omitted) -and range of line numbers (or all lines if omitted). - -For tracing_off, instances below any module in the files/ranges specified -will also not be traced. - -=item clock_enable -module "" -var "" - -Indicate the signal is used to gate a clock, and the user takes responsibility -for insuring there are no races related to it. - -Same as /*verilator clock_enable*/, see L for -more information and an example. - -=item clocker -module "" [-task ""] -var "" - -=item clocker -module "" [-function ""] -var "" - -=item no_clocker -module "" [-task ""] -var "" - -=item no_clocker -module "" [-function ""] -var "" - -Indicate the signal is used as clock or not. This information is used by -Verilator to mark the signal as clocker and propagate the clocker attribute -automatically to derived signals. See C<--clk> for more information. - -Same as /*verilator clocker*/, see L for more -information. - -=item coverage_block_off -module "" -block "" - -=item coverage_block_off -file "" -line - -Specifies the entire begin/end block should be ignored for coverage -analysis purposes. Can either be specified as a named block or as a -filename and line number. - -Same as /*verilator coverage_block_off*/, see L for more information. - -=item full_case -file "" -lines - -=item parallel_case -file "" -lines - -Same as "//synopsys full_case" and "//synopsys parallel_case". When -these synthesis directives are discovered, Verilator will either -formally prove the directive to be true, or failing that, will insert -the appropriate code to detect failing cases at simulation runtime and -print an "Assertion failed" error message. - -=item hier_block -module "" - -Specifies that the module is a unit of hierarchical Verilation. -Note that the setting is ignored unless --hierachical option is specified. -See L for more information. - -=item inline -module "" - -Specifies the module may be inlined into any modules that use this module. -Same as /*verilator inline_module*/, and see that under L for more information. - -=item isolate_assignments -module "" [-task ""] -var "" - -=item isolate_assignments -module "" [-function ""] -var "" - -=item isolate_assignments -module "" -function "" - -Used to indicate the assignments to this signal in any blocks should be -isolated into new blocks. When there is a large combinatorial block that -is resulting in a UNOPTFLAT warning, attaching this to the signal causing -a false loop may clear up the problem. - -Same as /* verilator isolate_assignments */, see L for more information. - -=item no_inline -module "" - -Specifies the module should not be inlined into any modules that use this -module. Same as /*verilator no_inline_module*/, and see that under -L for more information. - -=item no_inline [-module ""] -task "" - -=item no_inline [-module ""] -function "" - -Specify the function or task should not be inlined into where it is -used. This may reduce the size of the final executable when a task is -used a very large number of times. For this flag to work, the task -and tasks below it must be pure; they cannot reference any variables -outside the task itself. - -Same as /*verilator no_inline_task*/, see L -for more information. - -=item public [-module ""] [-task/-function ""] - -var "" - -=item public_flat [-module ""] [-task/-function ""] - -var "" - -=item public_flat_rd [-module ""] [-task/-function ""] - -var "" - -=item public_flat_rw [-module ""] [-task/-function ""] - -var "" "@(edge)" - -Sets the variable to be public. Same as /*verilator public*/ or -/*verilator public_flat*/ etc, see those under L -for more information. - -=item sc_bv -module "" [-task ""] -var "" - -=item sc_bv -module "" [-function ""] -var "" - -Sets the port to be of sc_bv> type, instead of bool, vluint32_t or -vluint64_t. Same as /*verilator sc_bv*/, see that under L for more information. - -=item sformat [-module ""] [-task ""] -var "" - -=item sformat [-module ""] [-function ""] -var "" - -Must be applied to the final argument of type "input string" of a function or -task to indicate the function or task should pass all remaining arguments -through $sformatf. This allows creation of DPI functions with $display like -behavior. See the test_regress/t/t_dpi_display.v file for an example. - -Same as /*verilator sformat*/, see L for more -information. - -=item split_var [-module ""] [-task ""] -var "" - -=item split_var [-module ""] [-function ""] -var "" - -Break the variable into multiple pieces typically to resolve UNOPTFLAT -performance issues. Typically the variables to attach this to are -recommended by Verilator itself, see UNOPTFLAT. - -Same as /*verilator split_var*/, see L for more -information. - -=back - - -=head1 LANGUAGE STANDARD SUPPORT - -=head2 Verilog 2001 (IEEE 1364-2001) Support - -Verilator supports most Verilog 2001 language features. This includes -signed numbers, "always @*", generate statements, multidimensional arrays, -localparam, and C-style declarations inside port lists. - -=head2 Verilog 2005 (IEEE 1364-2005) Support - -Verilator supports most Verilog 2005 language features. This includes the -`begin_keywords and `end_keywords compiler directives, $clog2, and the -uwire keyword. - -=head2 SystemVerilog 2005 (IEEE 1800-2005) Support - -Verilator supports ==? and !=? operators, ++ and -- in some contexts, -$bits, $countbits, $countones, $error, $fatal, $info, $isunknown, $onehot, -$onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit, byte, -chandle, const, do-while, enum, export, final, import, int, interface, -logic, longint, modport, package, program, shortint, struct, time, typedef, -union, var, void, priority case/if, and unique case/if. - -It also supports .name and .* interconnection. - -Verilator partially supports concurrent assert and cover statements; see -the enclosed coverage tests for the syntax which is allowed. - -=head2 SystemVerilog 2012 (IEEE 1800-2012) Support - -Verilator implements a full SystemVerilog 2012 preprocessor, including -function call-like preprocessor defines, default define arguments, -`__FILE__, `__LINE__ and `undefineall. - -Verilator currently has some support for SystemVerilog synthesis -constructs. As SystemVerilog features enter common usage they are added; -please file a bug if a feature you need is missing. - -=head2 SystemVerilog 2017 (IEEE 1800-2017) Support - -Verilator supports the 2017 "for" loop constructs, and several minor -cleanups made in 1800-2017. - -=head2 Verilog AMS Support - -Verilator implements a very small subset of Verilog AMS (Verilog Analog and -Mixed-Signal Extensions) with the subset corresponding to those VMS -keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009 -languages. - -AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS". - -At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt, -string, and wreal. - -=head2 Synthesis Directive Assertion Support - -With the --assert switch, Verilator reads any "//synopsys full_case" or -"//synopsys parallel_case" directives. The same applies to any -"//ambit synthesis", "//cadence" or "//pragma" directives of the same form. - -When these synthesis directives are discovered, Verilator will either -formally prove the directive to be true, or failing that, will insert the -appropriate code to detect failing cases at simulation runtime and print an -"Assertion failed" error message. - -Verilator likewise also asserts any "unique" or "priority" SystemVerilog -keywords on case statement, as well as "unique" on if statements. -However, "priority if" is currently simply ignored. - - -=head1 LANGUAGE EXTENSIONS - -The following additional constructs are the extensions Verilator supports -on top of standard Verilog code. Using these features outside of comments -or `ifdef's may break other tools. - -=over 4 - -=item `__FILE__ - -The __FILE__ define expands to the current filename as a string, like C++'s -__FILE__. This was incorporated into to the 1800-2009 standard (but -supported by Verilator since 2006!) - -=item `__LINE__ - -The __LINE__ define expands to the current filename as a string, like C++'s -__LINE__. This was incorporated into to the 1800-2009 standard (but -supported by Verilator since 2006!) - -=item `error I - -This will report an error when encountered, like C++'s #error. - -=item $c(I, ...); - -The string will be embedded directly in the output C++ code at the point -where the surrounding Verilog code is compiled. It may either be a -standalone statement (with a trailing ; in the string), or a function that -returns up to a 32-bit number (without a trailing ;). This can be used to -call C++ functions from your Verilog code. - -String arguments will be put directly into the output C++ code. Expression -arguments will have the code to evaluate the expression inserted. Thus to -call a C++ function, $c("func(",a,")") will result in 'func(a)' in the -output C++ code. For input arguments, rather than hard-coding variable -names in the string $c("func(a)"), instead pass the variable as an -expression $c("func(",a,")"). This will allow the call to work inside -Verilog functions where the variable is flattened out, and also enable -other optimizations. - -If you will be reading or writing any Verilog variables inside the C++ -functions, the Verilog signals must be declared with /*verilator public*/. - -You may also append an arbitrary number to $c, generally the width of the -output. [signal_32_bits = $c32("...");] This allows for compatibility with -other simulators which require a differently named PLI function name for -each different output width. - -=item $display, $write, $fdisplay, $fwrite, $sformat, $swrite - -Format arguments may use C fprintf sizes after the % escape. Per the -Verilog standard, %x prints a number with the natural width, and %0x prints -a number with minimum width. Verilator extends this so %5x prints 5 digits -per the C standard (this is unspecified in Verilog, but was incorporated -into the 1800-2009). - -=item `coverage_block_off - -Specifies the entire begin/end block should be ignored for coverage -analysis. Must be inside a code block, e.g. within a begin/end pair. -Same as /* verilator coverage_block_off */ and C in -L. - -=item `systemc_header - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the output .h file's header. Must be placed as a -module item, e.g. directly inside a module/endmodule pair. Despite the name -of this macro, this also works in pure C++ code. - -=item `systemc_ctor - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the C++ class constructor. Must be placed as a -module item, e.g. directly inside a module/endmodule pair. Despite the name -of this macro, this also works in pure C++ code. - -=item `systemc_dtor - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the C++ class destructor. Must be placed as a -module item, e.g. directly inside a module/endmodule pair. Despite the name -of this macro, this also works in pure C++ code. - -=item `systemc_interface - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the C++ class interface. Must be placed as a module -item, e.g. directly inside a module/endmodule pair. Despite the name of -this macro, this also works in pure C++ code. - -=item `systemc_imp_header - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the header of all files for this C++ class -implementation. Must be placed as a module item, e.g. directly inside a -module/endmodule pair. Despite the name of this macro, this also works in -pure C++ code. - -=item `systemc_implementation - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into a single file of the C++ class implementation. Must -be placed as a module item, e.g. directly inside a module/endmodule -pair. Despite the name of this macro, this also works in pure C++ code. - -If you will be reading or writing any Verilog variables in the C++ -functions, the Verilog signals must be declared with /*verilator public*/. -See also the public task feature; writing an accessor may result in cleaner -code. - -=item `SYSTEMVERILOG - -The SYSTEMVERILOG, SV_COV_START and related standard defines are set by -default when --language is 1800-*. - -=item `VERILATOR - -=item `verilator - -=item `verilator3 - -The VERILATOR, verilator and verilator3 defines are set by default so you -may `ifdef around tool specific constructs. - -=item `verilator_config - -Take remaining text up to the next `verilog mode switch and treat it as -Verilator configuration commands. - -=item `verilog - -Switch back to processing Verilog code after a `systemc_... mode switch. -The Verilog code returns to the last language mode specified with -`begin_keywords, or SystemVerilog if none was specified. - -=item /*verilator clock_enable*/ - -Used after a signal declaration to indicate the signal is used to gate a -clock, and the user takes responsibility for insuring there are no races -related to it. (Typically by adding a latch, and running static timing -analysis.) For example: - - reg enable_r /*verilator clock_enable*/; - wire gated_clk = clk & enable_r; - always_ff @(posedge clk) - enable_r <= enable_early; - -The clock_enable attribute will cause the clock gate to be ignored in the -scheduling algorithm, sometimes required for correct clock behavior, and -always improving performance. It's also a good idea to enable the -IMPERFECTSCH warning, to ensure all clock enables are properly recognized. - -Same as C in configuration files, see L for more information. - -=item /*verilator clocker*/ - -=item /*verilator no_clocker*/ - -Used after a signal declaration to indicate the signal is used as clock or -not. This information is used by Verilator to mark the signal as clocker -and propagate the clocker attribute automatically to derived signals. See -C<--clk> for more information. - -Same as C and C in configuration files, see -L for more information. - -=item /*verilator coverage_block_off*/ - -Specifies the entire begin/end block should be ignored for coverage -analysis purposes. - -Same as C in configuration files, see -L for more information. - -=item /*verilator coverage_off*/ - -Specifies that following lines of code should have coverage disabled. -Often used to ignore an entire module for coverage analysis purposes. - -=item /*verilator coverage_on*/ - -Specifies that following lines of code should have coverage re-enabled (if -appropriate --coverage flags are passed) after being disabled earlier with -/*verilator coverage_off*/. - -=item /*verilator hier_block*/ - -Specifies that the module is a unit of hierarchical Verilation. -This metacomment must be between - "module module_name(...);" and "endmodule". -The module will not be inlined nor uniquified for each instance in -hierarchical Verilation. -Note that the metacomment is ignored unless --hierachical option is specified. - -See L for more information. - -=item /*verilator inline_module*/ - -Specifies the module the comment appears in may be inlined into any modules -that use this module. This is useful to speed up simulation runtime. Note -if using "--public" that signals under inlined submodules will be named -I__DOT__I as C++ does not allow "." in signal names. - -Same as C in configuration files, see L -for more information. - -=item /*verilator isolate_assignments*/ - -Used after a signal declaration to indicate the assignments to this signal -in any blocks should be isolated into new blocks. When there is a large -combinatorial block that is resulting in a UNOPTFLAT warning, attaching -this to the signal causing a false loop may clear up the problem. - -IE, with the following - - reg splitme /* verilator isolate_assignments*/; - // Note the placement of the semicolon above - always_comb begin - if (....) begin - splitme = ....; - other assignments - end - end - -Verilator will internally split the block that assigns to "splitme" into -two blocks: - -It would then internally break it into (sort of): - - // All assignments excluding those to splitme - always_comb begin - if (....) begin - other assignments - end - end - // All assignments to splitme - always_comb begin - if (....) begin - splitme = ....; - end - end - -Same as C in configuration files, see -L for more information. - -=item /*verilator lint_off I*/ - -Disable the specified warning message for any warnings following the comment. - -=item /*verilator lint_on I*/ - -Re-enable the specified warning message for any warnings following the comment. - -=item /*verilator lint_restore*/ - -After a /*verilator lint_save*/, pop the stack containing lint message -state. Often this is useful at the bottom of include files. - -=item /*verilator lint_save*/ - -Push the current state of what lint messages are turned on or turned off to -a stack. Later meta-comments may then lint_on or lint_off specific -messages, then return to the earlier message state by using /*verilator -lint_restore*/. For example: - - // verilator lint_save - // verilator lint_off SOME_WARNING - ... // code needing SOME_WARNING turned off - // verilator lint_restore - -If SOME_WARNING was on before the lint_off, it will now be restored to on, -and if it was off before the lint_off it will remain off. - -=item /*verilator no_inline_module*/ - -Specifies the module the comment appears in should not be inlined into any -modules that use this module. - -Same as C in configuration files, see L for more information. - -=item /*verilator no_inline_task*/ - -Used in a function or task variable definition section to specify the -function or task should not be inlined into where it is used. This may -reduce the size of the final executable when a task is used a very large -number of times. For this flag to work, the task and tasks below it must -be pure; they cannot reference any variables outside the task itself. - -Same as C in configuration files, see L for more information. - -=item /*verilator public*/ (parameter) - -Used after a parameter declaration to indicate the emitted C code should -have the parameter values visible. Due to C++ language restrictions, this -may only be used on 64-bit or narrower integral enumerations. - - parameter [2:0] PARAM /*verilator public*/ = 2'b0; - -=item /*verilator public*/ (typedef enum) - -Used after an enum typedef declaration to indicate the emitted C code -should have the enum values visible. Due to C++ language restrictions, this -may only be used on 64-bit or narrower integral enumerations. - - typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/; - -=item /*verilator public*/ (variable) - -Used after an input, output, register, or wire declaration to indicate the -signal should be declared so that C code may read or write the value of the -signal. This will also declare this module public, otherwise use -/*verilator public_flat*/. - -Instead of using public variables, consider instead making a DPI or public -function that accesses the variable. This is nicer as it provides an -obvious entry point that is also compatible across simulators. - -Same as C in configuration files, see L -for more information. - -=item /*verilator public*/ (task/function) - -Used inside the declaration section of a function or task declaration to -indicate the function or task should be made into a C++ function, public to -outside callers. Public tasks will be declared as a void C++ function, -public functions will get the appropriate non-void (bool, uint32_t, etc) -return type. Any input arguments will become C++ arguments to the -function. Any output arguments will become C++ reference arguments. Any -local registers/integers will become function automatic variables on the -stack. - -Wide variables over 64 bits cannot be function returns, to avoid exposing -complexities. However, wide variables can be input/outputs; they will be -passed as references to an array of 32-bit numbers. - -Generally, only the values of stored state (flops) should be written, as -the model will NOT notice changes made to variables in these functions. -(Same as when a signal is declared public.) - -You may want to use DPI exports instead, as it's compatible with other -simulators. - -Same as C in configuration files, see L -for more information. - -=item /*verilator public_flat*/ (variable) - -Used after an input, output, register, or wire declaration to indicate the -signal should be declared so that C code may read or write the value of the -signal. This will not declare this module public, which means the name of -the signal or path to it may change based upon the module inlining which -takes place. - -Same as C in configuration files, see L for more information. - -=item /*verilator public_flat_rd*/ (variable) - -Used after an input, output, register, or wire declaration to indicate the -signal should be declared public_flat (see above), but read-only. - -Same as C in configuration files, see L for more information. - -=item /*verilator public_flat_rw @() */ (variable) - -Used after an input, output, register, or wire declaration to indicate the -signal should be declared public_flat_rd (see above), and also writable, -where writes should be considered to have the timing specified by the given -sensitivity edge list. Set for all variables, ports and wires using the ---public-flat-rw switch. - -Same as C in configuration files, see L for more information. - -=item /*verilator public_module*/ - -Used after a module statement to indicate the module should not be inlined -(unless specifically requested) so that C code may access the module. -Verilator automatically sets this attribute when the module contains any -public signals or `systemc_ directives. Also set for all modules when -using the --public switch. - -Same as C in configuration files, see L -for more information. - -=item /*verilator sc_clock*/ - -Deprecated and ignored. Previously used after an input declaration to -indicate the signal should be declared in SystemC as a sc_clock instead of -a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 and -later do not require clock pins to be sc_clocks and this is no longer -needed and is ignored. - -=item /*verilator sc_bv*/ - -Used after a port declaration. It sets the port to be of sc_bv> -type, instead of bool, vluint32_t or vluint64_t. This may be useful if the -port width is parameterized and the instantiating C++ code wants to always -have a sc_bv so it can accept any width. In general you should avoid using -this attribute when not necessary as with increasing usage of sc_bv the -performance decreases significantly. - -Same as C in configuration files, see L -for more information. - -=item /*verilator sformat*/ - -Attached to the final argument of type "input string" of a function or task to -indicate the function or task should pass all remaining arguments through -$sformatf. This allows creation of DPI functions with $display like behavior. -See the test_regress/t/t_dpi_display.v file for an example. - -Same as C in configuration files, see L -for more information. - -=item /*verilator split_var*/ - -Attached to a variable or a net declaration to break the variable into -multiple pieces typically to resolve UNOPTFLAT performance issues. -Typically the variables to attach this to are recommended by Verilator -itself, see UNOPTFLAT below. - -For example, Verilator will internally convert a variable with the -metacomment such as: - - logic [7:0] x [0:1] /*verilator split_var*/; - -To: - - logic [7:0] x__BRA__0__KET__ /*verilator split_var*/; - logic [7:0] x__BRA__1__KET__ /*verilator split_var*/; - -Note that the generated packed variables retain the split_var metacomment -because they may be split into further smaller pieces according to the -access patterns. - -This only supports unpacked arrays, packed arrays, and packed structs of -integer types (reg, logic, bit, byte, int...); otherwise if a split was -requested but cannot occur a SPLITVAR warning is issued. Splitting large -arrays may slow down the Verilation speed, so use this only on variables -that require it. - -Same as C in configuration files, see L -for more information. - -=item /*verilator tag */ - -Attached after a variable or structure member to indicate opaque (to -Verilator) text that should be passed through to the XML output as a tag, -for use by downstream applications. - -=item /*verilator tracing_off*/ - -Disable waveform tracing for all future signals that are declared in this -module, or instances below this module. Often this is placed just after a -primitive's module statement, so that the entire module and instances below -it are not traced. - -=item /*verilator tracing_on*/ - -Re-enable waveform tracing for all future signals or instances that are -declared. - -=back - - -=head1 LANGUAGE LIMITATIONS - -There are some limitations and lack of features relative to the major -closed-source simulators, by intent. - -=head2 Synthesis Subset - -Verilator supports the Synthesis subset with other verification constructs -being added over time. Verilator also simulates events as Synopsys's Design -Compiler would; namely given a block of the form: - - always @(x) y = x & z; - -This will recompute y when there is even a potential for change in x or a -change in z, that is when the flops computing x or z evaluate (which is -what Design Compiler will synthesize.) A compliant simulator would only -calculate y if x changes. We recommend using always_comb to make the code -run the same everywhere. Also avoid putting $displays in combo blocks, as -they may print multiple times when not desired, even on compliant -simulators as event ordering is not specified. - -=head2 Signal Naming - -To avoid conflicts with C symbol naming, any character in a signal name -that is not alphanumeric nor a single underscore will be replaced by __0hh -where hh is the hex code of the character. To avoid conflicts with -Verilator's internal symbols, any double underscore are replaced with -___05F (5F is the hex code of an underscore.) - -=head2 Bind - -Verilator only supports "bind" to a target module name, not an instance -path. - -=head2 Class - -Verilator class support is limited but in active development. Verilator -supports members, and methods. Verilator does not support class static -members, class extend, or class parameters. - -=head2 Dotted cross-hierarchy references - -Verilator supports dotted references to variables, functions and tasks in -different modules. The portion before the dot must have a constant value; -for example a[2].b is acceptable, while a[x].b is generally not. - -References into generated and arrayed instances use the instance names -specified in the Verilog standard; arrayed instances are named -{instanceName}[{instanceNumber}] in Verilog, which becomes -{instanceName}__BRA__{instanceNumber}__KET__ inside the generated C++ code. - -=head2 Latches - -Verilator is optimized for edge sensitive (flop based) designs. It will -attempt to do the correct thing for latches, but most performance -optimizations will be disabled around the latch. - -=head2 Structures and Unions - -Presently Verilator only supports packed structs and packed unions. Rand -and randc tags on members are simply ignored. All structures and unions -are represented as a single vector, which means that generating one member -of a structure from blocking, and another from non-blocking assignments is -unsupported. - -=head2 Time - -All delays (#) are ignored, as they are in synthesis. - -=head2 Unknown states - -Verilator is mostly a two state simulator, not a four state simulator. -However, it has two features which uncover most initialization bugs -(including many that a four state simulator will miss.) - -Identity comparisons (=== or !==) are converted to standard ==/!= when neither -side is a constant. This may make the expression yield a different result -compared to a four state simulator. An === comparison to X will always be -false, so that Verilog code which checks for uninitialized logic will not fire. - -Assigning X to a variable will actually assign a constant value as -determined by the --x-assign switch. This allows runtime randomization, -thus if the value is actually used, the random value should cause -downstream errors. Integers also get randomized, even though the Verilog -2001 specification says they initialize to zero. Note however that -randomization happens at initialization time and hence during a single -simulation run, the same constant (but random) value will be used every -time the assignment is executed. - -All variables, depending on --x-initial setting, are typically randomly -initialized using a function. By running several random simulation runs -you can determine that reset is working correctly. On the first run, have the -function initialize variables to zero. On the second, have it initialize -variables to one. On the third and following runs have it initialize them -randomly. If the results match, reset works. (Note this is what the -hardware will really do.) In practice, just setting all variables to one -at startup finds most problems (since typically control signals are -active-high). - ---x-assign applies to variables explicitly initialized or assigned an -X. Uninitialized clocks are initialized to zero, while all other state -holding variables are initialized to a random value. Event driven -simulators will generally trigger an edge on a transition from X to 1 -(C) or X to 0 (C). However, by default, since clocks are -initialized to zero, Verilator will not trigger an initial negedge. Some -code (particularly for reset) may rely on X->0 triggering an edge. The ---x-initial-edge switch enables this behavior. Comparing runs with and -without this switch will find such problems. - - -=head2 Tri/Inout - -Verilator converts some simple tristate structures into two state. Pullup, -pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are -also supported. Simple comparisons with === 1'bz are also supported. - -An assignment of the form: - - inout driver; - wire driver = (enable) ? output_value : 1'bz; - -Will be converted to - - input driver; // Value being driven in from "external" drivers - output driver__en; // True if driven from this module - output driver__out; // Value being driven from this module - -External logic will be needed to combine these signals with any external -drivers. - -Tristate drivers are not supported inside functions and tasks; an inout -there will be considered a two state variable that is read and written -instead of a four state variable. - -=head2 Functions & Tasks - -All functions and tasks will be inlined (will not become functions in C.) -The only support provided is for simple statements in tasks (which may -affect global variables). - -Recursive functions and tasks are not supported. All inputs and outputs -are automatic, as if they had the Verilog 2001 "automatic" keyword -prepended. (If you don't know what this means, Verilator will do what you -probably expect -- what C does. The default behavior of Verilog is -different.) - -=head2 Generated Clocks - -Verilator attempts to deal with generated and gated clocks correctly, -however some cases cause problems in the scheduling algorithm which is -optimized for performance. The safest option is to have all clocks as -primary inputs to the model, or wires directly attached to primary inputs. -For proper behavior clock enables may also need the /*verilator -clock_enable*/ attribute. - -=head2 Gate Primitives - -The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are -directly converted to behavioral equivalents. The 3-state and MOS gate -primitives are not supported. Tables are not supported. - -=head2 Specify blocks - -All specify blocks and timing checks are ignored. All min:typ:max delays -use the typical value. - -=head2 Array Initialization - -When initializing a large array, you need to use non-delayed assignments. -Verilator will tell you when this needs to be fixed; see the BLKLOOPINIT -error for more information. - -=head2 Array Out of Bounds - -Writing a memory element that is outside the bounds specified for the array -may cause a different memory element inside the array to be written -instead. For power-of-2 sized arrays, Verilator will give a width warning -and the address. For non-power-of-2-sizes arrays, index 0 will be written. - -Reading a memory element that is outside the bounds specified for the array -will give a width warning and wrap around the power-of-2 size. For -non-power-of-2 sizes, it will return a unspecified constant of the -appropriate width. - -=head2 Assertions - -Verilator is beginning to add support for assertions. Verilator currently -only converts assertions to simple "if (...) error" statements, and -coverage statements to increment the line counters described in the -coverage section. - -Verilator does not support SEREs yet. All assertion and coverage -statements must be simple expressions that complete in one cycle. - -=head2 Encrypted Verilog - -Open source simulators like Verilator are unable to use encrypted RTL -(i.e. IEEE P1735). Talk to your IP vendor about delivering IP blocks -via Verilator's --protect-lib feature. - -=head2 Language Keyword Limitations - -This section describes specific limitations for each language keyword. - -=over 4 - -=item `__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords, -`begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords, -`endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor, -`systemc_dtor, `systemc_header, `systemc_imp_header, -`systemc_implementation, `systemc_interface, `undef, `verilog - -Fully supported. - -=item always, always_comb, always_ff, always_latch, and, assign, begin, -buf, byte, case, casex, casez, default, defparam, do-while, else, end, -endcase, endfunction, endgenerate, endmodule, endspecify, endtask, final, -for, function, generate, genvar, if, initial, inout, input, int, integer, -localparam, logic, longint, macromodule, module, nand, negedge, nor, not, -or, output, parameter, posedge, reg, scalared, shortint, signed, supply0, -supply1, task, time, tri, typedef, var, vectored, while, wire, xnor, xor - -Generally supported. - -=item ++, -- operators - -Increment/decrement can only be used as standalone statements or in certain -limited cases. - -=item '{} operator - -Assignment patterns with order based, default, constant integer (array) or -member identifier (struct/union) keys are supported. Data type keys and -keys which are computed from a constant expression are not supported. - -=item `uselib - -Uselib, a vendor specific library specification method, is ignored along -with anything following it until the end of that line. - -=item cast operator - -Casting is supported only between simple scalar types, signed and unsigned, -not arrays nor structs. - -=item chandle - -Treated as a "longint"; does not yet warn about operations that are -specified as illegal on chandles. - -=item disable - -Disable statements may be used only if the block being disabled is a block -the disable statement itself is inside. This was commonly used to provide -loop break and continue functionality before SystemVerilog added the break -and continue keywords. - -=item inside - -Inside expressions may not include unpacked array traversal or $ as an -upper bound. Case inside and case matches are also unsupported. - -=item interface - -Interfaces and modports, including with generated data types are supported. -Generate blocks around modports are not supported, nor are virtual -interfaces nor unnamed interfaces. - -=item shortreal - -Short floating point (shortreal) numbers are converted to real. Most other -simulators either do not support float, or convert likewise. - -=item specify specparam - -All specify blocks and timing checks are ignored. - -=item uwire - -Verilator does not perform warning checking on uwires, it treats the uwire -keyword as if it were the normal wire keyword. - -=item $bits, $countbits, $countones, $error, $fatal, $finish, $info, -$isunknown, $onehot, $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, -$time, $unsigned, $warning. - -Generally supported. - -=item $dump/$dumpports and related - -$dumpfile or $dumpports will create a VCD or FST file (which is based on -the --trace argument given when the model was Verilated). This will take -effect starting at the next eval() call. If you have multiple Verilated -designs under the same C model, then this will dump signals only from the -design containing the $dumpvars. - -$dumpvars and $dumpports module identifier is ignored; the traced instances -will always start at the top of the design. The levels argument is also -ignored, use tracing_on/tracing_off pragmas instead. - -$dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename argument -is ignored, only a single trace file may be active at once. - -$dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and -$dumplimit/$dumpportlimit are currently ignored. - -=item $exit, $finish, $stop - -The rarely used optional parameter to $finish and $stop is ignored. $exit -is aliased to $finish. - -=item $fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, -$fscanf, $fwrite, $fscanf, $sscanf - -Generally supported. - -=item $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, -$setup, $setuphold, $skew, $timeskew, $width - -All specify blocks and timing checks are ignored. - -=item $random, $urandom, $urandom_range - -Use +verilator+seed argument to set the seed if there is no $random or -$urandom optional argument to set the seed. There is one random seed per C -thread, not per module for $random, nor per object for random stability of -$urandom/$urandom_range. - -=item $readmemb, $readmemh - -Read memory commands should work properly. Note Verilator and the Verilog -specification does not include support for readmem to multi-dimensional -arrays. - -=item $test$plusargs, $value$plusargs - -Supported, but the instantiating C++/SystemC testbench must call - - Verilated::commandArgs(argc, argv); - -to register the command line before calling $test$plusargs or -$value$plusargs. - -=back - - -=head1 ERRORS AND WARNINGS - -Warnings may be disabled in three ways. First, when the warning is -printed it will include a warning code. Simply surround the offending -line with a lint_off/lint_on pair: - - // verilator lint_off UNSIGNED - if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop; - // verilator lint_on UNSIGNED - -Second, warnings may be disabled using a configuration file with a lint_off -command. This is useful when a script is suppressing warnings and the -Verilog source should not be changed. - -Warnings may also be globally disabled by invoking Verilator with the -C<-Wno-I> switch. This should be avoided, as it removes all -checking across the designs, and prevents other users from compiling your -code without knowing the magic set of disables needed to successfully -compile your design. - -=head2 Error and Warning Format - -Warnings and errors printed by Verilator always match this regular -expression: - - %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.* - -Errors and warning start with a percent sign (historical heritage from -Digital Equipment Corporation). Some errors or warning have a code -attached, with meanings described below. Some errors also have a filename, -line number and optional column number (starting at column 1 to match GCC). - -Following the error message, Verilator will typically show the user's -source code corresponding to the error, prefixed by the line number and a " -| ". Following this is typically an arrow and ~ pointing at the error on -the source line directly above. - -=head2 List of all warnings - -=over 4 - -=item ALWCOMBORDER - -Warns that an always_comb block has a variable which is set after it is -used. This may cause simulation-synthesis mismatches, as not all -simulators allow this ordering. - - always_comb begin - a = b; - b = 1; - end - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item ASSIGNIN - -Error that an assignment is being made to an input signal. This is almost -certainly a mistake, though technically legal. - - input a; - assign a = 1'b1; - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item ASSIGNDLY - -Warns that you have an assignment statement with a delayed time in front of -it, for example: - - a <= #100 b; - assign #100 a = b; - -Ignoring this warning may make Verilator simulations differ from other -simulators, however at one point this was a common style so disabled by -default as a code style warning. - -=item BLKANDNBLK - -BLKANDNBLK is an error that a variable comes from a mix of blocking and -non-blocking assignments. - -This is not illegal in SystemVerilog, but a violation of good coding -practice. Verilator reports this as an error, because ignoring this warning -may make Verilator simulations differ from other simulators. - -It is generally safe to disable this error (with a "// verilator lint_off -BLKANDNBLK" metacomment or the -Wno-BLKANDNBLK option) when one of the -assignments is inside a public task, or when the blocking and non-blocking -assignments have non-overlapping bits and structure members. - -Generally, this is caused by a register driven by both combo logic and a -flop: - - logic [1:0] foo; - always @(posedge clk) foo[0] <= ... - always_comb foo[1] = ... - -Simply use a different register for the flop: - - logic [1:0] foo; - always @(posedge clk) foo_flopped[0] <= ... - always_comb foo[0] = foo_flopped[0]; - always_comb foo[1] = ... - -Or, this may also avoid the error: - - logic [1:0] foo /*verilator split_var*/; - -=item BLKSEQ - -This indicates that a blocking assignment (=) is used in a sequential -block. Generally non-blocking/delayed assignments (<=) are used in -sequential blocks, to avoid the possibility of simulator races. It can be -reasonable to do this if the generated signal is used ONLY later in the -same block, however this style is generally discouraged as it is error -prone. - - always @(posedge clk) foo = ... - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item BLKLOOPINIT - -This indicates that the initialization of an array needs to use non-delayed -assignments. This is done in the interest of speed; if delayed assignments -were used, the simulator would have to copy large arrays every cycle. (In -smaller loops, loop unrolling allows the delayed assignment to work, though -it's a bit slower than a non-delayed assignment.) Here's an example - - always @(posedge clk) - if (~reset_l) begin - for (i=0; i<`ARRAY_SIZE; i++) begin - array[i] = 0; // Non-delayed for verilator - end - -This message is only seen on large or complicated loops because Verilator -generally unrolls small loops. You may want to try increasing ---unroll-count (and occasionally --unroll-stmts) which will raise the small -loop bar to avoid this error. - -=item BOUNDED - -This indicates that bounded queues (e.g. "var name[$ : 3]") are -unsupported. - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item BSSPACE - -Warns that a backslash is followed by a space then a newline. Likely the -intent was to have a backslash directly followed by a newline (e.g. when -making a `define) and there's accidentally white space at the end of the -line. If the space is not accidental, suggest removing the backslash in -the code as it serves no function. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASEINCOMPLETE - -Warns that inside a case statement there is a stimulus pattern for which -there is no case item specified. This is bad style, if a case is -impossible, it's better to have a "default: $stop;" or just "default: ;" so -that any design assumption violations will be discovered in simulation. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASEOVERLAP - -Warns that inside a case statement you have case values which are detected -to be overlapping. This is bad style, as moving the order of case values -will cause different behavior. Generally the values can be respecified to -not overlap. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASEWITHX - -Warns that a case statement contains a constant with a C. Verilator is -two-state so interpret such items as always false. Note a common error is -to use a C in a case or casez statement item; often what the user -instead intended is to use a casez with C. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASEX - -Warns that it is simply better style to use casez, and C in place of -C's. See -L - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASTCONST - -Warns that a dynamic cast ($cast) is unnecessary as the $cast will always -succeed or fail. If it will always fail, the $cast is useless. If it will -always succeed a static cast may be preferred. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. On other simulators, not fixing CASTCONST may result in -decreased performance. - -=item CDCRSTLOGIC - -With --cdc only, warns that asynchronous flop reset terms come from other -than primary inputs or flopped outputs, creating the potential for reset -glitches. - -=item CLKDATA - -Warns that clock signal is mixed used with/as data signal. The checking for -this warning is enabled only if user has explicitly marked some signal as -clocker using command line option or in-source meta comment (see C<--clk>). - -The warning can be disabled without affecting the simulation result. But it -is recommended to check the warning as this may degrade the performance of -the Verilated model. - -=item CMPCONST - -Warns that you are comparing a value in a way that will always be constant. -For example "X > 1" will always be true when X is a single bit wide. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item COLONPLUS - -Warns that a :+ is seen. Likely the intent was to use +: to select a range -of bits. If the intent was a range that is explicitly positive, suggest -adding a space, e.g. use ": +". - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item COMBDLY - -Warns that you have a delayed assignment inside of a combinatorial block. -Using delayed assignments in this way is considered bad form, and may lead -to the simulator not matching synthesis. If this message is suppressed, -Verilator, like synthesis, will convert this to a non-delayed assignment, -which may result in logic races or other nasties. See -L - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item CONTASSREG - -Error that a continuous assignment is setting a reg. According to IEEE -Verilog, but not SystemVerilog, a wire must be used as the target of -continuous assignments. - -This error is only reported when "--language 1364-1995", "--language -1364-2001", or "--language 1364-2005" is used. - -Ignoring this error will only suppress the lint check, it will simulate -correctly. - -=item DECLFILENAME - -Warns that a module or other declaration's name doesn't match the filename -with path and extension stripped that it is declared in. The filename a -modules/interfaces/programs is declared in should match the name of the -module etc. so that -y directory searching will work. This warning is -printed for only the first mismatching module in any given file, and -v -library files are ignored. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item DEFPARAM - -Warns that the "defparam" statement was deprecated in Verilog 2001 and all -designs should now be using the #(...) format to specify parameters. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item DETECTARRAY - -Error when Verilator tries to deal with a combinatorial loop that could not be -flattened, and which involves a datatype which Verilator cannot handle, such -as an unpacked struct or a large unpacked array. This typically occurs when --Wno-UNOPTFLAT has been used to override an UNOPTFLAT warning (see below). - -The solution is to break the loop, as described for UNOPTFLAT. - -=item DIDNOTCONVERGE - -Error at simulation runtime when model did not properly settle. - -Verilator sometimes has to evaluate combinatorial logic multiple times, -usually around code where a UNOPTFLAT warning was issued, but disabled. -For example: - - always_comb b = ~a; - always_comb a = b - -This code will toggle forever, and thus to prevent an infinite loop, the -executable will give the didn't converge error. - -To debug this, first review any UNOPTFLAT warnings that were ignored. -Though typically it is safe to ignore UNOPTFLAT (at a performance cost), at -the time of issuing a UNOPTFLAT Verilator did not know if the logic would -eventually converge and assumed it would. - -Next, run Verilator with --prof-cfuncs. Run make on the generated files -with "CPP_FLAGS=-DVL_DEBUG", to allow enabling simulation runtime debug -messages. Rerun the test. Now just before the convergence error you -should see additional output similar to this: - - CHANGE: filename.v:1: b - CHANGE: filename.v:2: a - -This means that signal b and signal a keep changing, inspect the code that -modifies these signals. Note if many signals are getting printed then most -likely all of them are oscillating. It may also be that e.g. "a" may be -oscillating, then "a" feeds signal "c" which then is also reported as -oscillating. - -One way DIDNOTCONVERGE may occur is flops are built out of gate primitives. -error. Verilator does not support building flops or latches out of gate -primitives, and any such code must change to use behavioral constructs -(e.g. always_ff and always_latch). - -Finally, rare, more difficult cases can be debugged like a "C" program; -either enter GDB and use its tracing facilities, or edit the generated C++ -code to add appropriate prints to see what is going on. - -=item ENDLABEL - -Warns that a label attached to a "end"-something statement does not match -the label attached to the block start. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item EOFNEWLINE - -Warns that a file does not end in a newline. POSIX defines that a line -must end in newline, as otherwise for example 'cat' of the file may produce -undesirable results. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item GENCLK - -Deprecated and no longer used as a warning. Used to indicate that the -specified signal was is generated inside the model, and also being used as -a clock. - -=item HIERBLOCK - -Warns that the top module is marked as a hierarchy block -by hier_block metacomment, which is not legal. This setting on the top module will be ignored. -=item IFDEPTH - -Warns that if/if else statements have exceeded the depth specified with ---if-depth, as they are likely to result in slow priority encoders. Statements -below unique and priority if statements are ignored. Solutions include -changing the code to a case statement, or a SystemVerilog 'unique if' or -'priority if'. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item IGNOREDRETURN - -Warns that a non-void function is being called as a task, and hence the -return value is being ignored. - -This warning is required by IEEE. The portable way to suppress this warning -(in SystemVerilog) is to use a void cast, e.g. - - void'(function_being_called_as_task()); - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item IMPERFECTSCH - -Warns that the scheduling of the model is not absolutely perfect, and some -manual code edits may result in faster performance. This warning defaults -to off, is not part of -Wall, and must be turned on explicitly before the -top module statement is processed. - -=item IMPLICIT - -Warns that a wire is being implicitly declared (it is a single bit wide -output from a sub-module.) While legal in Verilog, implicit declarations -only work for single bit wide signals (not buses), do not allow using a -signal before it is implicitly declared by an instance, and can lead to -dangling nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode -for Emacs, available from L - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item IMPORTSTAR - -Warns that an "import I::*" statement is in $unit scope. This -causes the imported symbols to pollute the global namespace, defeating much -of the purpose of having a package. Generally "import ::*" should only be -used inside a lower scope such as a package or module. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item IMPURE - -Warns that a task or function that has been marked with /*verilator -no_inline_task*/ references variables that are not local to the task. -Verilator cannot schedule these variables correctly. - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item INCABSPATH - -Warns that an `include filename specifies an absolute path. This means the -code will not work on any other system with a different file system layout. -Instead of using absolute paths, relative paths (preferably without any -directory specified whatsoever) should be used, and +incdir used on the -command line to specify the top include source directories. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item INFINITELOOP - -Warns that a while or for statement has a condition that is always true. -and thus results in an infinite loop if the statement ever executes. - -This might be unintended behavior if the loop body contains statements that -in other simulators would make time pass, which Verilator is ignoring -due to e.g. STMTDLY warnings being disabled. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly (i.e. hang due to the infinite loop). - -=item INITIALDLY - -Warns that you have a delayed assignment inside of an initial or final -block. If this message is suppressed, Verilator will convert this to a -non-delayed assignment. See also the COMBDLY warning. - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item INSECURE - -Warns that the combination of options selected may be defeating the attempt -to protect/obscure identifiers or hide information in the model. Correct -the options provided, or inspect the output code to see if the information -exposed is acceptable. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item LATCH - -Warns that a signal is not assigned in all control paths of a combinational -always block, resulting in the inference of a latch. For intentional -latches, consider using the always_latch (SystemVerilog) keyword instead. -The warning may be disabled with a lint_off pragma around the always block. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item LITENDIAN - -Warns that a packed vector is declared with little endian bit numbering -(i.e. [0:7]). Big endian bit numbering is now the overwhelming standard, -and little numbering is now thus often due to simple oversight instead of -intent. - -Also warns that an instance is declared with little endian range -(i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE the -bits will likely be backwards from what you expect (i.e. instance [0] will -connect to signal bit [N-1] not bit [0]). - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item MODDUP - -Warns that a module has multiple definitions. Generally this indicates a -coding error, or a mistake in a library file and it's good practice to have -one module per file (and only put each file once on the command line) to -avoid these issues. For some gate level netlists duplicates are sometimes -unavoidable, and MODDUP should be disabled. - -Ignoring this warning will cause the more recent module definition to be -discarded. - -=item MULTIDRIVEN - -Warns that the specified signal comes from multiple always blocks. This is -often unsupported by synthesis tools, and is considered bad style. It will -also cause longer simulation runtimes due to reduced optimizations. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item MULTITOP - -Warns that there are multiple top level modules, that is modules not -instantiated by any other module, and both modules were put on the command -line (not in a library). Three likely cases: - -1. A single module is intended to be the top. This warning then occurs -because some low level instance is being read in, but is not really needed -as part of the design. The best solution for this situation is to ensure -that only the top module is put on the command line without any flags, and -all remaining library files are read in as libraries with -v, or are -automatically resolved by having filenames that match the module names. - -2. A single module is intended to be the top, the name of it is known, and -all other modules should be ignored if not part of the design. The best -solution is to use the --top option to specify the top module's name. All -other modules that are not part of the design will be for the most part -ignored (they must be clean in syntax and their contents will be removed as -part of the Verilog module elaboration process.) - -3. Multiple modules are intended to be design tops, e.g. when linting a -library file. As multiple modules are desired, disable the MULTITOP -warning. All input/outputs will go uniquely to each module, with any -conflicting and identical signal names being made unique by adding a prefix -based on the top module name followed by __02E (a Verilator-encoded ASCII -".'). This renaming is done even if the two modules' signals seem -identical, e.g. multiple modules with a "clk" input. - -=item NOLATCH - -Warns that no latch was detected in an always_latch block. The warning may -be disabled with a lint_off pragma around the always block, but recoding -using a regular always may be more appropriate. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item NULLPORT - -Warns that a null port was detected in the module definition port list. Null -ports are empty placeholders, i.e. either one ore more commas at the beginning -or the end of a module port list, or two or more consecutive commas in the -middle of a module port list. A null port cannot be accessed within the module, -but when instantiating the module by port order, it is treated like a regular -port and any wire connected to it is left unconnected. -This is considered a warning because this feature is rarely used, and is mostly -the result of a typing error such as a dangling comma at the end of a port list. - -=item PINCONNECTEMPTY - -Warns that an instance has a pin which is connected to .pin_name(), -e.g. not another signal, but with an explicit mention of the pin. It may -be desirable to disable PINCONNECTEMPTY, as this indicates intention to -have a no-connect. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item PINMISSING - -Warns that a module has a pin which is not mentioned in an instance. If a -pin is not missing it should still be specified on the instance declaration -with a empty connection, using "(.pin_name())". - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item PINNOCONNECT - -Warns that an instance has a pin which is not connected to another signal. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item PINNOTFOUND - -Warns that an instance port or Parameter was not found in the module being -instanciated. Please note that Verilator raises these errors also on instances -that should be disabled by generate/if/endgenerate constructs: - - module a; - localparam A=1; - generate - if (A==0) begin - b b_inst1 (.x(1'b0)); // nonexistent port - b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter - end - endgenerate - endmodule - - module b; - endmodule - -In the example above, b is instantiated with a port named x, but module b has -no such port. In the next line, b is instantiated again with -a nonexistent parameter PX. Technically, this code is incorrect because of -this, but other tools may ignore it because module b is not instantiated -due to the generate/if condition being false. - -It is possible to disable the error above using: -/* verilator lint_off PINNOTFOUND */ - -=item PKGNODECL - -Error that a package/class appears to have been referenced that has not yet -been declared. According to IEEE 1800-2017 26.3 all packages must be -declared before being used. - -=item PROCASSWIRE - -Error that a procedural assignment is setting a wire. According to IEEE, a -var/reg must be used as the target of procedural assignments. - -=item RANDC - -Warns that the 'randc' keyword is currently unsupported, and that it is -being converted to 'rand'. - -=item REALCVT - -Warns that a real number is being implicitly rounded to an integer, with -possible loss of precision. - -=item REDEFMACRO - -Warns that you have redefined the same macro with a different value, for -example: - - `define MACRO def1 - //... - `define MACRO otherdef - -The best solution is to use a different name for the second macro. If this -is not possible, add a undef to indicate the code is overriding the value: - - `define MACRO def1 - //... - `undef MACRO - `define MACRO otherdef - -=item SELRANGE - -Warns that a selection index will go out of bounds: - - wire vec[6:0]; - initial out = vec[7]; // There is no 7 - -Verilator will assume zero for this value, instead of X. Note that in some -cases this warning may be false, when a condition upstream or downstream of -the access means the access out of bounds will never execute or be used. - - wire vec[6:0]; - initial begin - seven = 7; - ... - if (seven != 7) out = vec[seven]; // Never will use vec[7] - -=item SHORTREAL - -Warns that Verilator does not support "shortreal" and they will be -automatically promoted to "real". The recommendation is to replace any -"shortreal" in the code with "real", as "shortreal" is not widely supported -across industry tools. - -Ignoring this warning may make Verilator simulations differ from other -simulators, if the increased precision of real affects your model or DPI -calls. - -=item SPLITVAR - -Warns that a variable with a C metacomment was not split. -Some possible reasons for this are: - -* The datatype of the variable is not supported for splitting. (e.g. is a -real). - -* The access pattern of the variable can not be determined -statically. (e.g. is accessed as a memory). - -* The index of the array exceeds the array size. - -* The variable is accessed from outside using dotted reference. -(e.g. top.instance0.variable0 = 1). - -* The variable is not declared in a module, but in a package or an -interface. - -* The variable is a parameter, localparam, genvar, or queue. - -* The variable is tristate or bidirectional. (e.g. inout or ref). - -=item STMTDLY - -Warns that you have a statement with a delayed time in front of it, for -example: - - #100 $finish; - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item SYMRSVDWORD - -Warning that a symbol matches a C++ reserved word and using this as a symbol -name would result in odd C++ compiler errors. You may disable this warning, -but the symbol will be renamed by Verilator to avoid the conflict. - -=item SYNCASYNCNET - -Warns that the specified net is used in at least two different always -statements with posedge/negedges (i.e. a flop). One usage has the signal -in the sensitivity list and body, probably as an async reset, and the other -usage has the signal only in the body, probably as a sync reset. Mixing -sync and async resets is usually a mistake. The warning may be disabled -with a lint_off pragma around the net, or either flopped block. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item TASKNSVAR - -Error when a call to a task or function has an inout from that task tied to -a non-simple signal. Instead connect the task output to a temporary signal -of the appropriate width, and use that signal to set the appropriate -expression as the next statement. For example: - - task foo(inout sig); ... endtask - always @* begin - foo(bus_we_select_from[2]); // Will get TASKNSVAR error - end - -Change this to: - - reg foo_temp_out; - always @* begin - foo(foo_temp_out); - bus_we_select_from[2] = foo_temp_out; - end - -Verilator doesn't do this conversion for you, as some more complicated -cases would result in simulator mismatches. - -=item TICKCOUNT - -Warns that the number of ticks to delay a $past variable is greater than -10. At present Verilator effectively creates a flop for each delayed -signals, and as such any large counts may lead to large design size -increases. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item TIMESCALEMOD - -Warns that `timescale is used in some but not all modules. Recommend using ---timescale argument, or in front of all modules use: - - `include "timescale.vh" - -Then in that file set the timescale. - -It may be disabled similar to other warnings. Ignoring this warning may -result in a module having an unexpected timescale. - -IEEE recommends this be an error, for that behavior use --Werror-TIMESCALEMOD. - -=item UNDRIVEN - -Warns that the specified signal has no source. Verilator is fairly -liberal in the usage calculations; making a signal public, or setting only -a single array element marks the entire signal as driven. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item UNOPT - -Warns that due to some construct, optimization of the specified signal or -block is disabled. The construct should be cleaned up to improve -simulation performance. - -A less obvious case of this is when a module instantiates two submodules. -Inside submodule A, signal I is input and signal O is output. Likewise in -submodule B, signal O is an input and I is an output. A loop exists and a -UNOPT warning will result if AI & AO both come from and go to combinatorial -blocks in both submodules, even if they are unrelated always blocks. This -affects performance because Verilator would have to evaluate each submodule -multiple times to stabilize the signals crossing between the modules. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item UNOPTFLAT - -Warns that due to some construct, optimization of the specified signal is -disabled. The signal reported includes a complete scope to the signal; it -may be only one particular usage of a multiply instantiated block. The -construct should be cleaned up to improve simulation performance; two times -better performance may be possible by fixing these warnings. - -Unlike the UNOPT warning, this occurs after flattening the netlist, and -indicates a more basic problem, as the less obvious case described under -UNOPT does not apply. - -Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by -synthesis which analyzes interconnection per-bit, but is circular to -simulation which analyzes per-bus: - - wire [2:0] x = {x[1:0], shift_in}; - -This statement needs to be evaluated multiple times, as a change in -"shift_in" requires "x" to be computed 3 times before it becomes stable. -This is because a change in "x" requires "x" itself to change value, which -causes the warning. - -For significantly better performance, split this into 2 separate signals: - - wire [2:0] xout = {x[1:0], shift_in}; - -and change all receiving logic to instead receive "xout". Alternatively, -change it to - - wire [2:0] x = {xin[1:0], shift_in}; - -and change all driving logic to instead drive "xin". - -With this change this assignment needs to be evaluated only once. These -sort of changes may also speed up your traditional event driven simulator, -as it will result in fewer events per cycle. - -The most complicated UNOPTFLAT path we've seen was due to low bits of a bus -being generated from an always statement that consumed high bits of the -same bus processed by another series of always blocks. The fix is the -same; split it into two separate signals generated from each block. - -Occasionally UNOPTFLAT may be indicated when there is a true circulation. -e.g. if trying to implement a flop or latch using individual gate -primitives. If UNOPTFLAT is suppressed the code may get a DIDNOTCONVERGE -error. Verilator does not support building flops or latches out of gate -primitives, and any such code must change to use behavioral constructs -(e.g. always_ff and always_latch). - -Another way to resolve this warning is to add a C metacomment -described above. This will cause the variable to be split internally, -potentially resolving the conflict. If you run with --report-unoptflat -Verilator will suggest possible candidates for C. - -The UNOPTFLAT warning may also be due to clock enables, identified from the -reported path going through a clock gating instance. To fix these, use the -clock_enable meta comment described above. - -The UNOPTFLAT warning may also occur where outputs from a block of logic -are independent, but occur in the same always block. To fix this, use the -isolate_assignments meta comment described above. - -To assist in resolving UNOPTFLAT, the option C<--report-unoptflat> can be -used, which will provide suggestions for variables that can be split up, -and a graph of all the nodes connected in the loop. See the L -section for more details. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item UNOPTTHREADS - -Warns that the thread scheduler was unable to partition the design to fill -the requested number of threads. - -One workaround is to request fewer threads with C<--threads>. - -Another possible workaround is to allow more MTasks in the simulation -runtime, by increasing the value of --threads-max-mtasks. More MTasks will -result in more communication and synchronization overhead at simulation -runtime; the scheduler attempts to minimize the number of MTasks for this -reason. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item UNPACKED - -Warns that unpacked structs and unions are not supported. - -Ignoring this warning will make Verilator treat the structure as packed, -which may make Verilator simulations differ from other simulators. This -downgrading may also result what would normally be a legal unpacked -struct/array inside an unpacked struct/array becoming an illegal unpacked -struct/array inside a packed struct/array. - -=item UNSIGNED - -Warns that you are comparing a unsigned value in a way that implies it is -signed, for example "X < 0" will always be false when X is unsigned. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item UNSUPPORTED - -UNSUPPORTED is an error that the construct might be legal according to IEEE -but is not currently supported. - -This error may be ignored with --bbox-unsup, however this will make the -design simulate incorrectly; see the details under --bbox-unsup. - -=item UNUSED - -Warns that the specified signal or parameter is never used/consumed. -Verilator is fairly liberal in the usage calculations; making a signal -public, a signal matching --unused-regexp ("*unused*") or accessing only a -single array element marks the entire signal as used. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -A recommended style for unused nets is to put at the bottom of a file code -similar to the following: - - wire _unused_ok = &{1'b0, - sig_not_used_a, - sig_not_used_yet_b, // To be fixed - 1'b0}; - -The reduction AND and constant zeros mean the net will always be zero, so -won't use simulation runtime. The redundant leading and trailing zeros avoid -syntax errors if there are no signals between them. The magic name -"unused" (-unused-regexp) is recognized by Verilator and suppresses -warnings; if using other lint tools, either teach it to the tool to ignore -signals with "unused" in the name, or put the appropriate lint_off around the -wire. Having unused signals in one place makes it easy to find what is unused, -and reduces the number of lint_off pragmas, reducing bugs. - -=item USERINFO, USERWARN, USERERROR, USERFATAL - -A SystemVerilog elaboration-time assertion print was executed. - -=item VARHIDDEN - -Warns that a task, function, or begin/end block is declaring a variable by -the same name as a variable in the upper level module or begin/end block -(thus hiding the upper variable from being able to be used.) Rename the -variable to avoid confusion when reading the code. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item WIDTH - -Warns that based on width rules of Verilog, two operands have different -widths. Verilator generally can intuit the common usages of widths, and -you shouldn't need to disable this message like you do with most lint -programs. Generally other than simple mistakes, you have two solutions: - -If it's a constant 0 that's 32 bits or less, simply leave it -unwidthed. Verilator considers zero to be any width needed. - -Concatenate leading zeros when doing arithmetic. In the statement - - wire [5:0] plus_one = from[5:0] + 6'd1 + carry[0]; - -The best fix, which clarifies intent and will also make all tools happy is: - - wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0, carry[0]}; - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item WIDTHCONCAT - -Warns that based on width rules of Verilog, a concatenate or replication -has an indeterminate width. In most cases this violates the Verilog rule -that widths inside concatenates and replicates must be sized, and should be -fixed in the code. - - wire [63:0] concat = {1, 2}; - -An example where this is technically legal (though still bad form) is: - - parameter PAR = 1; - wire [63:0] concat = {PAR, PAR}; - -The correct fix is to either size the 1 ("32'h1"), or add the width to the -parameter definition ("parameter [31:0]"), or add the width to the -parameter usage ("{PAR[31:0],PAR[31:0]}". - -=back - -The following describes the less obvious errors: - -=over 4 - -=item Internal Error - -This error should never occur first, though may occur if earlier warnings -or error messages have corrupted the program. If there are no other -warnings or errors, submit a bug report. - -=item Unsupported: .... - -This error indicates that you are using a Verilog language construct -that is not yet supported in Verilator. See the Limitations chapter. - -=back - - -=head1 DEPRECATIONS - -The following deprecated items are scheduled for future removal: - -=over 4 - -=item C++11 compiler support - -Verilator currently requires C++11 or newer compilers. Verilator will -require C++14 or newer compilers for both compiling Verilator and compiling -Verilated models no sooner than January 2022. - -=item --no-relative-cfuncs - -The --no-relative-cfuncs option is not be required by any C++11 compliant -compiler and is planned for removal no sooner than July 2021. - -=item --inhibit-sim - -The --inhibit-sim option is planned for removal no sooner than July 2021. - -=item Configuration File -msg - -The -msg argument to lint_off has been replaced with -rule. -msg is -planned for removal no sooner than January 2021. - -=item XML locations - -The XML C attribute has been replaced with C. C is planned -for removal no sooner than January 2021. - -=back - - -=head1 FAQ/FREQUENTLY ASKED QUESTIONS - -=over 4 - -=item Can I contribute? - -Please contribute! Just submit a pull request, or raise an issue to discuss -if looking for something to help on. For more information see our -contributor agreement. - -=item How widely is Verilator used? - -Verilator is used by many of the largest silicon design companies, and all the -way down to college projects. Verilator is one of the "big 4" simulators, -meaning one of the 4 main SystemVerilog simulators available, namely the -commercial products Synopsys VCS (tm), Mentor Questa/ModelSim (tm), Cadence -Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. The -three commercial offerings are often collectively called the "big 3" -simulators. - -=item Does Verilator run under Windows? - -Yes, using Cygwin. Verilated output also compiles under Microsoft Visual -C++, but this is not tested every release. - -=item Can you provide binaries? - -You can install Verilator via the system package manager (apt, yum, etc.) on -many Linux distributions, including Debian, Ubuntu, SuSE, Fedora, and others. -These packages are provided by the Linux distributions and generally will lag -the version of the mainline Verilator repository. If no binary package is -available for your distribution, how about you set one up? Please contact the -authors for assistance. - -=item How can it be faster than (name-a-big-3-closed-source-simulator)? - -Generally, the implied part of the question is "... with all of the -manpower they can put into developing it." - -Most simulators have to be compliant with the complete IEEE 1364 (Verilog) and -IEEE 1800 (SystemVerilog) standards, meaning they have to be event driven. -This prevents them from being able to reorder blocks and make netlist-style -optimizations, which are where most of the gains come from. - -You should not be scared by non-compliance. Your synthesis tool isn't -compliant with the whole standard to start with, so your simulator need not be -either. Verilator is closer to the synthesis interpretation, so this is a good -thing for getting working silicon. - -=item Will Verilator output remain under my own license? - -Yes, it's just like using GCC on your programs; this is why Verilator uses -the "GNU *Lesser* Public License Version 3" instead of the more typical -"GNU Public License". See the licenses for details, but in brief, if you -change Verilator itself or the header files Verilator includes, you must -make the source code available under the GNU Lesser Public License. -However, Verilator output (the Verilated code) only "include"s the licensed -files, and so you are NOT required to release any output from Verilator. - -You also have the option of using the Perl Artistic License, which again -does not require you to release your Verilog or generated code, and also -allows you to modify Verilator for internal use without distributing the -modified version. But please contribute back to the community! - -One limit is that you cannot under either license release a commercial -Verilog simulation product incorporating Verilator without making the -source code available. - -As is standard with Open Source, contributions back to Verilator will be -placed under the Verilator copyright and LGPL/Artistic license. Small test -cases will be released into the public domain so they can be used anywhere, -and large tests under the LGPL/Artistic, unless requested otherwise. - -=item Why is running Verilator (to create a model) so slow? - -Verilator needs more memory than the resulting simulator will require, as -Verilator internally creates all of the state of the resulting generated -simulator in order to optimize it. If it takes more than a few minutes or -so (and you're not using --debug since debug mode is disk bound), see if your -machine is paging; most likely you need to run it on a machine with more -memory. Very large designs are known to have topped 16GB resident set size. - -=item How do I generate waveforms (traces) in C++? - -See the next question for tracing in SystemC mode. - -A. Add the --trace switch to Verilator, and in your top level C code, call -Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to -enable traces, same as with any Verilog simulator. See -C. - -B. Or, for finer-grained control, or C++ files with multiple Verilated -modules you may also create the trace purely from C++. Create a -VerilatedVcdC object, and in your main loop call "trace_object->dump(time)" -every time step, and finally call "trace_object->close()". You also need -to compile verilated_vcd_c.cpp and add it to your link, preferably by -adding the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule. -This is done for you if using the Verilator --exe flag. Note you can also -call ->trace on multiple Verilated objects with the same trace file if you -want all data to land in the same output file. - - #include "verilated_vcd_c.h" - ... - int main(int argc, char** argv, char** env) { - ... - Verilated::traceEverOn(true); - VerilatedVcdC* tfp = new VerilatedVcdC; - topp->trace(tfp, 99); // Trace 99 levels of hierarchy - tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); - ... - while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { - main_time += #; - tfp->dump(main_time); - } - tfp->close(); - } - -=item How do I generate waveforms (traces) in SystemC? - -A. Add the --trace switch to Verilator, and in your top level sc_main, call -Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to -enable traces, same as with any Verilog simulator, see the non-SystemC -example in C. This will trace only the module -containing the $dumpvar. - -B. Or, you may create a trace purely from SystemC, which may trace all -Verilated designs in the SystemC model. Create a VerilatedVcdSc object as -you would create a normal SystemC trace file. For an example, see the call -to VerilatedVcdSc in the examples/make_tracing_sc/sc_main.cpp file of the -distribution, and below. - -Alternatively you may use the C++ trace mechanism described in the previous -question, note the timescale and timeprecision will be inherited from your -SystemC settings. - -You also need to compile verilated_vcd_sc.cpp and verilated_vcd_c.cpp and -add them to your link, preferably by adding the dependencies in -$(VK_GLOBAL_OBJS) to your Makefile's link rule. This is done for you if -using the Verilator --exe flag. - -Note you can also call ->trace on multiple Verilated objects with the same -trace file if you want all data to land in the same output file. - -When using SystemC 2.3, the SystemC library must have been built with the -experimental simulation phase callback based tracing disabled. This is -disabled by default when building SystemC with its configure based build -system, but when building SystemC with CMake, you must pass --DENABLE_PHASE_CALLBACKS_TRACING=OFF to disable this feature. - - #include "verilated_vcd_sc.h" - ... - int main(int argc, char** argv, char** env) { - ... - Verilated::traceEverOn(true); - VerilatedVcdSc* tfp = new VerilatedVcdSc; - topp->trace(tfp, 99); // Trace 99 levels of hierarchy - tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); - ... - sc_start(1); - ... - tfp->close(); - } - -=item How do I generate FST waveforms (traces) in C++? - -FST is a trace file format developed by GTKWave. Verilator provides basic FST -support. To dump traces in FST format, add the --trace-fst switch to Verilator -and either A. use $dumpfile/$dumpvars in Verilog as described in the VCD -example above, or B. in C++ change the include described in the VCD example -above: - - #include "verilated_fst_c.h" - VerilatedFstC* tfp = new VerilatedFstC; - -Note that currently supporting both FST and VCD in a single simulation is -impossible, but such requirement should be rare. You can however ifdef -around the trace format in your C++ main loop, and select VCD or FST at -build time, should you require. - -=item How do I generate FST waveforms (aka dumps or traces) in SystemC? - -FST is a trace file format developed by GTKWave. Verilator provides basic FST -support. To dump traces in FST format, add the --trace-fst switch to Verilator -and either A. use $dumpfile/$dumpvars in Verilog as described in the FST -example above, or B. in C++ change the include described in the FST example -above: - - #include "verilated_fst_sc.h" - VerilatedFstSc* tfp = new VerilatedFstSc; - -Note that currently supporting both FST and VCD in a single simulation is -impossible, but such requirement should be rare. You can however ifdef -around the trace format in your C++ main loop, and select VCD or FST at -build time, should you require. - -=item How do I view waveforms (aka dumps or traces)? - -Verilator creates standard VCD (Value Change Dump) and FST files. VCD files -are viewable with the open source GTKWave (recommended) or Dinotrace (legacy) -programs, or any of the many closed-source offerings; FST is supported only by -GTKWave. - -=item How do I reduce the size of large waveform (trace) files? - -First, instead of calling VerilatedVcdC->open at the beginning of time, -delay calling it until the time stamp where you want tracing to begin. -Likewise you can also call VerilatedVcdC->open before the end of time -(perhaps a short period after you detect a verification error). - -Next, add /*verilator tracing_off*/ to any very low level modules you never -want to trace (such as perhaps library cells). Finally, use the ---trace-depth option to limit the depth of tracing, for example ---trace-depth 1 to see only the top level signals. - -Also be sure you write your trace files to a local solid-state drive, -instead of to a network drive. Network drives are generally far slower. - -You can also consider using FST tracing instead of VCD. FST dumps are a -fraction of the size of the equivalent VCD. FST tracing can be slower than -VCD tracing, but it might be the only option if the VCD file size is -prohibitively large. - -=item How do I do coverage analysis? - -Verilator supports both block (line) coverage and user inserted functional -coverage. - -First, run verilator with the --coverage option. If you are using your own -makefile, compile the model with the GCC flag -DVM_COVERAGE (if using -the makefile provided by Verilator, it will do this for you). - -At the end of your test, call VerilatedCov::write passing the name of the -coverage data file (typically "logs/coverage.dat"). - -Run each of your tests in different directories. Each test will create a -logs/coverage.dat file. - -After running all of your tests, execute the verilator_coverage tool. The -verilator_coverage tool reads the logs/coverage.dat file(s), and creates an -annotated source code listing showing code coverage details. - -For an example, after running 'make test' in the Verilator distribution, -see the examples/make_tracing_c/logs directory. Grep for lines starting -with '%' to see what lines Verilator believes need more coverage. - -Info files can be written by verilator_coverage for import to C. -This enables use of C for HTML reports and importing reports to -sites such as L. - -=item Where is the translate_off command? (How do I ignore a construct?) - -Translate on/off pragmas are generally a bad idea, as it's easy to have -mismatched pairs, and you can't see what another tool sees by just -preprocessing the code. Instead, use the preprocessor; Verilator defines -the "VERILATOR" define for you, so just wrap the code in an ifndef region: - - `ifndef VERILATOR - Something_Verilator_Dislikes; - `endif - -Most synthesis tools similarly define SYNTHESIS for you. - -=item Why do I get "unexpected C" or "unexpected C" errors? - -The words C, C, C, C, and others are reserved keywords -in SystemVerilog. Older Verilog code might use these as identifiers. You -should change your code to not use them to ensure it works with newer -tools. Alternatively, surround them by the Verilog 2005/SystemVerilog -begin_keywords pragma to indicate Verilog 2001 code. - - `begin_keywords "1364-2001" - integer bit; initial bit = 1; - `end_keywords - -If you want the whole design to be parsed as Verilog 2001, please see the -C<--default-language> option. - -=item How do I prevent my assertions from firing during reset? - -Call Verilated::assertOn(false) before you first call the model, then turn -it back on after reset. It defaults to true. When false, all assertions -controlled by --assert are disabled. - -=item Why do I get "undefined reference to `sc_time_stamp()'"? - -In 4.200 and later, using the timeInc function is recommended instead. See -the "CONNECTING TO C++" examples. Some linkers (MSVC++) still require -sc_time_stamp() to be defined, either define this with ("double -sc_time_stamp() { return 0; }") or compile the Verilated code with --DVL_TIME_CONTEXT. - -Prior to Verilator 4.200, the sc_time_stamp function needs to be defined in -C++ (non SystemC) to return the current simulation time. - -=item Why do I get "undefined reference to `VL_RAND_RESET_I' or `Verilated::...'"? - -You need to link your compiled Verilated code against the verilated.cpp -file found in the include directory of the Verilator kit. This is one -target in the $(VK_GLOBAL_OBJS) make variable, which should be part of your -Makefile's link rule. If you use --exe, this is done for you. - -=item Is the PLI supported? - -Only somewhat. More specifically, the common PLI-ish calls $display, -$finish, $stop, $time, $write are converted to C++ equivalents. You can -also use the "import DPI" SystemVerilog feature to call C code (see the -chapter above). There is also limited VPI access to public signals. - -If you want something more complex, since Verilator emits standard C++ -code, you can simply write your own C++ routines that can access and modify -signal values without needing any PLI interface code, and call it with -$c("{any_c++_statement}"). - -=item How do I make a Verilog module that contain a C++ object? - -You need to add the object to the structure that Verilator creates, then -use $c to call a method inside your object. The -test_regress/t/t_extend_class files show an example of how to do this. - -=item How do I get faster build times? - -When running make pass the make variable VM_PARALLEL_BUILDS=1 so that -builds occur in parallel. Note this is now set by default if an output -file was large enough to be split due to the --output-split option. - -Verilator emits any infrequently executed "cold" routines into separate -__Slow.cpp files. This can accelerate compilation as optimization can be -disabled on these routines. See the OPT_FAST and OPT_SLOW make variables -and the BENCHMARKING & OPTIMIZATION section of the manual. - -Use a recent compiler. Newer compilers tend to be faster. - -Compile in parallel on many machines and use caching; see the web for the -ccache, distcc and icecream packages. ccache will skip GCC runs between -identical source builds, even across different users. If ccache was -installed when Verilator was built it is used, or see OBJCACHE environment -variable to override this. Also see the --output-split option. - -To reduce the compile time of classes that use a Verilated module (e.g. a -top CPP file) you may wish to add /*verilator no_inline_module*/ to your -top level module. This will decrease the amount of code in the model's -Verilated class, improving compile times of any instantiating top level C++ -code, at a relatively small cost of execution performance. - -=item Why do so many files need to recompile when I add a signal? - -Adding a new signal requires the symbol table to be recompiled. Verilator -uses one large symbol table, as that results in 2-3 less assembly -instructions for each signal access. This makes the execution time 10-15% -faster, but can result in more compilations when something changes. - -=item How do I access Verilog functions/tasks in C? - -Use the SystemVerilog Direct Programming Interface. You write a Verilog -function or task with input/outputs that match what you want to call in -with C. Then mark that function as a DPI export function. See the DPI -chapter in the IEEE Standard. - -=item How do I access C++ functions/tasks in Verilog? - -Use the SystemVerilog Direct Programming Interface. You write a Verilog -function or task with input/outputs that match what you want to call in -with C. Then mark that function as a DPI import function. See the DPI -chapter in the IEEE Standard. - -=item How do I access signals in C? - -The best thing to do is to make a SystemVerilog "export DPI" task or function -that accesses that signal, as described in the DPI chapter in the manual -and DPI tutorials on the web. This will allow Verilator to better optimize -the model and should be portable across simulators. - -If you really want raw access to the signals, declare the signals you will -be accessing with a /*verilator public*/ comment before the closing -semicolon. Then scope into the C++ class to read the value of the signal, -as you would any other member variable. - -Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t), -16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or -64-bit unsigned long longs (uint64_t) that fits the width of the signal. -Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for -1 to 64 bits, and the compiler will properly up-convert smaller entities. -Note even signed ports are declared as unsigned; you must sign extend -yourself to the appropriate signal width. - -Signals wider than 64 bits are stored as an array of 32-bit uint32_t's. -Thus to read bits 31:0, access signal[0], and for bits 63:32, access -signal[1]. Unused bits (for example bit numbers 65-96 of a 65-bit vector) -will always be zero. If you change the value you must make sure to pack -zeros in the unused bits or core-dumps may result, because Verilator strips -array bound checks where it believes them to be unnecessary to improve -performance. - -In the SYSTEMC example above, if you had in our.v: - - input clk /*verilator public*/; - // Note the placement of the semicolon above - -From the sc_main.cpp file, you'd then: - - #include "Vour.h" - #include "Vour_our.h" - cout << "clock is " << top->our->clk << endl; - -In this example, clk is a bool you can read or set as any other variable. -The value of normal signals may be set, though clocks shouldn't be changed -by your code or you'll get strange results. - -=item Should a module be in Verilog or SystemC? - -Sometimes there is a block that just interconnects instances, and have a -choice as to if you write it in Verilog or SystemC. Everything else being -equal, best performance is when Verilator sees all of the design. So, look -at the hierarchy of your design, labeling instances as to if they are -SystemC or Verilog. Then: - -A module with only SystemC instances below must be SystemC. - -A module with a mix of Verilog and SystemC instances below must be -SystemC. (As Verilator cannot connect to lower-level SystemC instances.) - -A module with only Verilog instances below can be either, but for best -performance should be Verilog. (The exception is if you have a design that -is instantiated many times; in this case Verilating one of the lower -modules and instantiating that Verilated instances multiple times into a -SystemC module *may* be faster.) - -=back - - -=head1 BUGS - -First, check the L section. - -Next, try the --debug switch. This will enable additional internal -assertions, and may help identify the problem. - -Finally, reduce your code to the smallest possible routine that exhibits -the bug. Even better, create a test in the test_regress/t directory, as -follows: - - cd test_regress - cp -p t/t_EXAMPLE.pl t/t_BUG.pl - cp -p t/t_EXAMPLE.v t/t_BUG.v - -There are many hints on how to write a good test in the driver.pl -documentation which can be seen by running: - - cd $VERILATOR_ROOT # Need the original distribution kit - test_regress/driver.pl --help - -Edit t/t_BUG.pl to suit your example; you can do anything you want in the -Verilog code there; just make sure it retains the single clk input and no -outputs. Now, the following should fail: - - cd $VERILATOR_ROOT # Need the original distribution kit - cd test_regress - t/t_BUG.pl # Run on Verilator - t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator - t/t_BUG.pl --vcs # Run on VCS simulator - t/t_BUG.pl --nc|--iv|--ghdl # Likewise on other simulators - -The test driver accepts a number of options, many of which mirror the main -Verilator option. For example the previous test could have been run with -debugging enabled. The full set of test options can be seen by running -driver.pl --help as shown above. - -Finally, report the bug using the bug tracker at -L. The bug will become publicly visible; if -this is unacceptable, mail the bug report to C. - - -=head1 HISTORY - -Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group -at Digital Equipment Corporation. The Verilog code that was converted -to C was then merged with a C based CPU model of the Alpha processor -and simulated in a C based environment called CCLI. - -In 1995 Verilator started being used also for Multimedia and Network -Processor development inside Digital. Duane Galbi took over active -development of Verilator, and added several performance enhancements. -CCLI was still being used as the shell. - -In 1998, through the efforts of existing DECies, mainly Duane Galbi, -Digital graciously agreed to release the source code. (Subject to the -code not being resold, which is compatible with the GNU Public -License.) - -In 2001, Wilson Snyder took the kit, and added a SystemC mode, and -called it Verilator2. This was the first packaged public release. - -In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from -scratch in C++. This added many optimizations, yielding about a 2-5x -performance gain. - -In 2009, major SystemVerilog and DPI language support was added. - -In 2018, Verilator 4.000 was released with multithreaded support. - -Currently, various language features and performance enhancements are added -as the need arises. Verilator is now about 3x faster than in 2002, and is -faster than most (if not every) other simulator. - - -=head1 AUTHORS - -When possible, please instead report bugs to L. - -Wilson Snyder - -Major concepts by Paul Wasson, Duane Galbi, John Coiner and Jie Xu. - - -=head1 CONTRIBUTORS - -Many people have provided ideas and other assistance with Verilator. - -Verilator is receiving major development support from the CHIPS Alliance. - -Previous major corporate sponsors of Verilator, by providing significant -contributions of time or funds included include Atmel Corporation, Cavium -Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., -Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune -Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc., -and SiCortex Inc. - -The people who have contributed major functionality are Byron Bradley, -Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd -Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, and Wilson Snyder. -Major testers included Jeff Dutton, Jonathon Donaldson, Ralf Karge, David -Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van -Cauwenberghe, Gene Weber, and Clifford Wolf. - -Some of the people who have provided ideas, and feedback for Verilator -include: David Addison, Nikana Anastasiadis, Vasu Arasanipalai, Jens Arm, -Tariq B. Ahmad, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew -Barr, Geoff Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael -Berman, Jean Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof -Bieganski, David Binderman, Piotr Binkowski, Johan Bjork, David Black, -Tymoteusz Blazejczyk, Daniel Bone, Morten Borup Petersen, Gregg Bouchard, -Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Charlie -Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, -Tony Bybell, Iru Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal -Casey, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark, -Ryan Clarke, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean -Cross, George Cuan, Joe DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh -Das, Maarten De Braekeleer, Bernard Deadman, Alberto Del Rio, John Demme, -Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny -Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Sebastian Dressler, -Alex Duller, Jeff Dutton, Tomas Dzetkulic, Richard E George, Edgar -E. Iglesias, Usuario Eda, Charles Eddleston, Chandan Egbert, Jan Egil Ruud, -Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Charles Eric -LaForest, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein, -Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner, -Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl, -Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Andrew -Goessling, Amir Gonnen, Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner, -Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil -Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto, -Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry, Stephen -Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki -Honda, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath, Jae -Hossell, Kuoping Hsu, Alan Hunter, James Hutchinson, Anderson Ignacio da -Silva, Jamie Iles, Thomas J Whatson, Ben Jackson, Mark Jackson Pulver, -Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong, Iztok -Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike -Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, -Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf -Karge, Dan Katz, Sol Katzman, Ian Kennedy, Michael Killough, Jonathan -Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot -Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, -Will Korteland, Wojciech Koszek, Varun Koyyalagunta, Markus Krause, David -Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok, Ed Lander, Steve -Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor -Lesik, John Li, Eivind Liland, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul -Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan -Lussier, Fred Ma, Duraid Madina, Odd Magne Reitan, Affe Mao, Julien -Margetts, Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Yves -Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot Mednick, -Wim Michiels, Miodrag Milanovic, Peter Monsson, Sean Moore, Dennis -Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris -Nalbantis, Peter Nelson, Bob Newgard, Paul Nitza, Yossi Nivin, Pete Nixon, -Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz, -Aleksander Osman, Don Owen, James Pallister, Vassilis Papaefstathiou, Brad -Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Cody Piersall, -Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter, -Niranjan Prabhu, Usha Priyadharshini, Prateek Puri, Marshal Qiao, Nandu -Raj, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Frederic -Requin, Dustin Richmond, Samuel Riedel, Eric Rippey, Oleg Rodionov, Ludwig -Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Denis -Rystsov, John Sanguinetti, Galen Seitz, Joseph Shaker, Salman Sheikh, Yu -Sheng Lin, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan -Shupei, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim -Snyder, Wilson Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, -Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson, -Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki, -Howard Su, Emerson Suguimoto, Gene Sullivan, Wai Sum Mong, Qingyao Sun, -Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Thierry Tambe, -Drew Taussig, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede, -Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, -Viktor Tomov, Steve Tong, Alex Torregrosa, Michael Tresidder, David Turner, -Neil Turton, Cong Van Nguyen, Hans Van Antwerpen, Jan Van Winkel, Sebastien -Van Cauwenberghe, Laurens van Dam, Leendert van Doorn, Srini Vemuri, Yuri -Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan -Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene -Weber, David Welch, Martin Whitaker, Marco Widmer, Leon Wildman, Daniel -Wilkerson, Gerald Williams, Trevor Williams, Jeff Winston, Joshua Wise, -Clifford Wolf, Tobias Wolfel, Johan Wouters, Paul Wright, Junyi Xi, Ding -Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke Yang, Amir Yazdanbakhsh, and -Keyi Zhang. - -Thanks to them, and all those we've missed including above, or wished to -remain anonymous. - - =head1 DISTRIBUTION The latest version is available from L. @@ -5869,7 +472,7 @@ L, L, L, L, L which is the source for this document, -and docs/internals.rst in the distribution. +and L for detailed documentation. =cut diff --git a/bin/verilator_coverage b/bin/verilator_coverage index 8093ad94a..e6ecbb77a 100755 --- a/bin/verilator_coverage +++ b/bin/verilator_coverage @@ -160,122 +160,27 @@ verilator_coverage - Verilator coverage analyzer Verilator_coverage processes Verilated model-generated coverage reports. -With --annotate, it reads the specified coverage data file and generates -annotated source code with coverage metrics annotated. If multiple -coverage points exist on the same source code line, additional lines will -be inserted to report the additional points. +For documentation see L. -Additional Verilog-XL-style standard arguments specify the search paths -necessary to find the source code that the coverage analysis was performed -on. +=head1 ARGUMENT SUMMARY -To filter those items to be included in coverage, you may read -logs/coverage.dat into an editor and do a M-x keep-lines to include only -those statistics of interest and save to a new .dat file. + Specify input data filename, default "coverage.dat" + --annotate Directory name for source annotation. + --annotate-all All files should be shown. + --annotate-min Minimum occurrence count for uncovered. + --help Displays this message and version and exits. + --rank Compute relative importance of tests. + --unlink With --write, unlink all inputs + --version Displays program version and exits. + --write Write aggregate coverage results. + --write-info Write lcov .info. -For Verilog conditions that should never occur, either add a $stop -statement to the appropriate statement block, or see the Verilator -documentation on "// verilator coverage_off" and "coverage_off". This will -remove the coverage points after the model is re-Verilated. - -=head1 ARGUMENTS - -=over 4 - -=item I - -Specify input data file. May be repeated to read multiple inputs. If no -data file is specified, by default coverage.dat is read. - -=item --annotate I - -Specifies the directory name that source files with annotated coverage data -should be written to. - -=item --annotate-all - -Specifies all files should be shown. By default, only those source files -which have low coverage are written to the output directory. - -=item --annotate-min I - -Specifies the minimum occurrence count that should be flagged if the -coverage point does not include a specified threshold. Defaults to 10. - -=item --help - -Displays this message and program version and exits. - -=item --rank - -Print an experimental report listing the relative importance of each test -in covering all of the coverage points. The report shows "Covered" which -indicates the number of points that test covers; a test is considered to -cover a point if it has a bucket count of at least 1. The "rank" column has -a higher number t indicate the test is more important, and rank 0 means the -test does not need to be run to cover the points. "RankPts" indicates the -number of coverage points this test will contribute to overall coverage if -all tests are run in the order of highest to lowest rank. - -=item --unlink - -When using --write to combine coverage data, unlink all input files after -the output has been created. - -=item --version - -Displays program version and exits. - -=item --write I - -Specifies the aggregate coverage results, summed across all the files, -should be written to the given filename in verilator_coverage data format. -This is useful in scripts to combine many sequential runs into one master -coverage file. - -=item --write-info I - -Specifies the aggregate coverage results, summed across all the files, -should be written to the given filename in C .info format. -This may be used to use C to aggregate or generate reports. - -The info format loses data compared to the Verilator coverage data format; -the info will all forms of coverage converted to line style coverage, and -if there are multiple coverage points on a single line, the minimum -coverage across those points will be used to report coverage of the line. - -=back - -=head1 VERILOG ARGUMENTS - -The following arguments are compatible with GCC, VCS and most Verilog -programs. - -=over 4 - -=item +libext+I+I... - -Defines the extensions for Verilog files. - -=item +define+I+I -=item -DI=I - -Defines the given variable. - -=item +incdir+I -=item -II - -Specifies a directory for finding include files. - -=item -f I - -Specifies a file containing additional command line arguments. - -=item -y I - -Specifies a module search directory. - -=back + +libext+I+I... Extensions for Verilog files. + +define+I+I Defines the given variable. + -DI=I Defines the given variable. + +incdir+I Add directory for finding include files. + -II Add directory for finding include files. + -y I Specifies module search directory. =head1 DISTRIBUTION @@ -288,16 +193,14 @@ Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -=head1 AUTHORS - -Wilson Snyder - =head1 SEE ALSO C, C L which is the source for this document. +and L for detailed documentation. + =cut ###################################################################### diff --git a/bin/verilator_difftree b/bin/verilator_difftree index 4b181318f..52b03d6bb 100755 --- a/bin/verilator_difftree +++ b/bin/verilator_difftree @@ -223,6 +223,8 @@ Wilson Snyder C +and L for detailed documentation. + =cut ###################################################################### diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 701a08788..2251d9f6a 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -535,83 +535,19 @@ verilator_gantt - Create Gantt chart of multi-threaded execution =head1 SYNOPSIS -Creates a visual representation to help analyze Verilator multithreaded -simulation performance, by showing when each macro-task starts and ends, -and showing when each thread is busy or idle. +Verilator_gantt creates a visual representation to help analyze Verilator +multithreaded simulation performance, by showing when each macro-task +starts and ends, and showing when each thread is busy or idle. -The generated Gantt chart has time on the X-axis. Times shown are to the -scale printed, i.e. a certain about of time for each character width. The -Y-axis shows threads, each thread's execution is shown on one line. That -line shows "[" at the position in time when it executes. +For documentation see L. -Following the "[" is the CPU number the task executed on, followed by zero -or more "-" to make the width of the characters match the scaled execution -time, followed by a "]". If the scale is too small, the CPU number and -mtask number will not be printed. If the scale is very small, a "&" -indicates multiple mtasks started at that time position. +=head1 ARGUMENT SUMMARY -Also creates a value change dump (VCD) format dump file which may be viewed -in a waveform viewer (e.g. C). See below. - -=head1 USAGE - - Build with --prof-threads. - - Run a sim with +verilator+prof+threads+window 2. - - This will create profile_threads.dat. - - Then run: - - verilator_gantt profile_threads.dat - - The report will be printed on standard output, this also generates - profile_threads.vcd - - View profile_threads.vcd in a waveform viewer. - -=head1 VCD SIGNALS - -In waveforms there are the following signals. Most signals the "decimal" -format will remove the leading zeros and make the traces easier to read. - -parallelism: The number of mtasks active at this time, for best performance -this will match the thread count. You may want to use an "analog step" -format to view this signal. - -cpu#_thread: For the given CPU number, the thread number executing. - -mtask#_cpu; For the given mtask id, the CPU it is executing on. - -thread#_mtask: For the given thread number, the mtask id executing. - -=head1 ARGUMENTS - -=over 4 - -=item I - -The filename to read data from, defaults to "profile_threads.dat". - -=item --help - -Displays this message and program version and exits. - -=item --scale I - -On the X-axis of the generated Gantt chart, each character represents this -many time units. (On x86, time units are rdtsc ticks.) Defaults to 0, -which will automatically compute a reasonable scale where no two mtasks -need to fit into same character width's worth of scaled time. - -=item --no-vcd - -=item --vcd I - -Set output filename for vcd dump, or disable. Default is -verilator_gantt.vcd. - -=back + Filename to read data from, default "profile_threads.dat". + --help Displays this message and program version and exits. + --scale I Number of characters per time step. + --no-vcd Do not create a VCD file. + --vcd Set output filename for vcd dump, default "verilator_gantt.vcd." =head1 DISTRIBUTION @@ -624,14 +560,12 @@ Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -=head1 AUTHORS - -Wilson Snyder - =head1 SEE ALSO C +and L for detailed documentation. + =cut ###################################################################### diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index c8a29be83..8dade5ef3 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -214,15 +214,12 @@ the functions are then transformed, assuming the user used Verilator's --prof-cfuncs, and a report printed showing the percentage of time, etc, in each Verilog block. -=head1 ARGUMENTS +For documentation see L. -=over 4 +=head1 ARGUMENT SUMMARY -=item --help - -Displays this message and program version and exits. - -=back + Input file (gprof.out) + --help Display this help =head1 DISTRIBUTION @@ -235,14 +232,12 @@ Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -=head1 AUTHORS - -Wilson Snyder - =head1 SEE ALSO C +and L for detailed documentation. + =cut ###################################################################### diff --git a/ci/docker/buildenv/README.rst b/ci/docker/buildenv/README.rst index 2dd2c7215..5e7110c84 100644 --- a/ci/docker/buildenv/README.rst +++ b/ci/docker/buildenv/README.rst @@ -1,4 +1,3 @@ -================================ Verilator Build Docker Container ================================ @@ -52,7 +51,7 @@ top of a repository: Rebuilding -========== +---------- To rebuild the Verilator-buildenv docker image, run: diff --git a/ci/docker/run/README.rst b/ci/docker/run/README.rst index c635a9546..ccd5709a7 100644 --- a/ci/docker/run/README.rst +++ b/ci/docker/run/README.rst @@ -1,4 +1,3 @@ -===================================== Verilator Executable Docker Container ===================================== @@ -60,7 +59,7 @@ You can also use the container to build Verilator at a specific commit: Internals -========= +--------- The Dockerfile builds Verilator and removes the tree when completed to reduce the image size. The entrypoint is set as a wrapper script diff --git a/docs/CONTRIBUTING.rst b/docs/CONTRIBUTING.rst index 47f1ede39..d6cfd2fc3 100644 --- a/docs/CONTRIBUTING.rst +++ b/docs/CONTRIBUTING.rst @@ -1,4 +1,3 @@ -========================= Contributing to Verilator ========================= @@ -9,7 +8,7 @@ contributions flow more efficiently. Did you find a bug? -=================== +------------------- - Please **Ensure the bug was not already reported** by searching `Verilator Issues `__. @@ -26,7 +25,7 @@ Did you find a bug? Did you write a patch that fixes a bug? -======================================= +--------------------------------------- - Please `Open a new issue `__. @@ -72,7 +71,7 @@ Did you write a patch that fixes a bug? Do you have questions? -====================== +---------------------- - Please see FAQ section and rest of the `Verilator manual `__, or `Verilator @@ -83,7 +82,7 @@ Do you have questions? Code of Conduct -=============== +--------------- - Our contributors and participants pledge to make participation in our project and our community a positive experience for everyone. We follow diff --git a/docs/Makefile b/docs/Makefile index 609b67b19..e9488273f 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -5,24 +5,25 @@ # # Code available from: https://verilator.org # -#***************************************************************************** -# # Copyright 2003-2021 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # -#****************************************************************************/ +###################################################################### # # This file is intended only to be called from the top-level Verilator Makefile. -#### Start of system configuration section. #### - -DOXYGEN = doxygen RST2HTML = rst2html +PYTHON3 = python3 +DOXYGEN = doxygen +SPHINXOPTS ?= -c guide +SPHINXBUILD ?= sphinx-build + +SOURCEDIR = . +BUILDDIR = _build -#### End of system configuration section. #### ###################################################################### .SUFFIXES: @@ -30,9 +31,49 @@ RST2HTML = rst2html default: @echo "error: make not supported here, run 'make docs' from Verilator top-level" +###################################################################### +# Intermediate rules + +vl-extract: ../bin/verilator ../Changes + mkdir -p _build/gen + $(PYTHON3) bin/vl_sphinx_extract ../bin/verilator + sed 's/`/\&96;/g' < ../Changes > _build/gen/Changes + +###################################################################### +# HTML + +htmled: + $(MAKE) vl-extract + $(MAKE) html + $(PYTHON3) bin/vl_sphinx_fix _build + +server: htmled + cd _build/html && $(PYTHON3) -m http.server + %.html: %.rst $(RST2HTML) $< $@ +###################################################################### +# PDF + +.PHONY: verilator.pdf + +verilator.pdf: pdf +pdf: + $(MAKE) vl-extract + $(MAKE) latex + $(PYTHON3) bin/vl_sphinx_fix _build + $(MAKE) -C _build/latex + cp _build/latex/verilator.pdf .. + +###################################################################### + +html latex clean linkcheck spelling:: + $(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) + +help: + @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) + clean mostlyclean distclean maintainer-clean:: rm -f $(SCRIPTS) *.tmp rm -f *.aux *.cp *.cps *.dvi *.fn *.fns *.ky *.kys *.log @@ -42,9 +83,3 @@ clean mostlyclean distclean maintainer-clean:: distclean maintainer-clean:: rm -f *.info* *.1 *.html *.pdf $(INFOS) - rm -f Makefile - -.PHONY: doxygen - -doxygen: - $(DOXYGEN) doxygen.config diff --git a/docs/_static/fig_gantt_min.png b/docs/_static/fig_gantt_min.png new file mode 100644 index 000000000..d17345eb3 Binary files /dev/null and b/docs/_static/fig_gantt_min.png differ diff --git a/docs/_static/verilator_192_150_min.png b/docs/_static/verilator_192_150_min.png new file mode 100644 index 000000000..978e7fe16 Binary files /dev/null and b/docs/_static/verilator_192_150_min.png differ diff --git a/docs/_static/verilator_32x32_min.png b/docs/_static/verilator_32x32_min.png new file mode 100644 index 000000000..98733ba07 Binary files /dev/null and b/docs/_static/verilator_32x32_min.png differ diff --git a/docs/bin/vl_sphinx_extract b/docs/bin/vl_sphinx_extract new file mode 100755 index 000000000..068ad8b35 --- /dev/null +++ b/docs/bin/vl_sphinx_extract @@ -0,0 +1,63 @@ +#!/usr/bin/env python3 +# pylint: disable=C0112,C0114,C0116,C0301,R0903 +# -*- Python -*- See copyright, etc below +###################################################################### + +import argparse +import re + +####################################################################### + +class VlSphinxExtract: + debug = 0 + SkipBasenames = {} + + def process(self, filename): + with open(filename) as fhr: + fhw = None + for line in fhr: + # =for VL_SPHINX_EXTRACT "file_to_write_to" + match = re.search(r'VL_SPHINX_EXTRACT +"([^"]+)"', line) + if match: + outname = match.group(1) + print("Writing %s" % outname) + fhw = open(outname, "w") + fhw.write( + ".. comment: generated by vl_sphinx_extract from " + + filename + "\n") + fhw.write(".. code-block::\n") + elif re.match(r'^[=a-zA-Z0-9_]', line): + fhw = None + elif fhw: + fhw.write(line) + + +####################################################################### + +parser = argparse.ArgumentParser( + allow_abbrev=False, + formatter_class=argparse.RawDescriptionHelpFormatter, + description="""Read a file and extract documentation data.""", + epilog= + """ Copyright 2021-2021 by Wilson Snyder. This package is free software; +you can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") + +parser.add_argument('--debug', + action='store_const', + const=9, + help='enable debug') +parser.add_argument('path', help='path to extract from') +Args = parser.parse_args() + +o = VlSphinxExtract() +o.debug = Args.debug +o.process(Args.path) + +###################################################################### +# Local Variables: +# compile-command: "./vl_sphinx_extract --debug ../../bin/verilator" +# End: diff --git a/docs/bin/vl_sphinx_fix b/docs/bin/vl_sphinx_fix new file mode 100755 index 000000000..cedbc0d63 --- /dev/null +++ b/docs/bin/vl_sphinx_fix @@ -0,0 +1,79 @@ +#!/usr/bin/env python3 +# pylint: disable=C0112,C0114,C0116,C0301,R0903 +# -*- Python -*- See copyright, etc below +###################################################################### + +import argparse +import os +import re + +####################################################################### + + +class VlSphinxFix: + debug = 0 + SkipBasenames = {} + + def process(self, path): + if os.path.isdir(path): + for basefile in os.listdir(path): + file = os.path.join(path, basefile) + if ((basefile != ".") and (basefile != "..") + and basefile not in self.SkipBasenames + and not os.path.islink(file)): + self.process(file) + elif re.search(r'\.(html|tex)$', path): + self._edit(path) + + def _edit(self, filename): + is_html = re.search(r'\.(html)$', filename) + with open(filename) as fhr: + origfile = fhr.read() + wholefile = origfile + # Option doesn't like spaces, so we use + # :option:`/*verilator&32;metacomment*/` + wholefile = re.sub(r'verilator-32-', r'verilator-', wholefile) + if is_html: + wholefile = re.sub(r'&32;', r' ', wholefile) + wholefile = re.sub(r'&96;', r'`', wholefile) + else: + wholefile = re.sub(r'&32;', r' ', wholefile) + wholefile = re.sub(r'&96;', r'`', wholefile) + if wholefile != origfile: + if self.debug: + print("Edit %s" % filename) + tempname = filename + ".tmp" + with open(tempname, "w") as fhw: + fhw.write(wholefile) + os.rename(tempname, filename) + + +####################################################################### + +parser = argparse.ArgumentParser( + allow_abbrev=False, + formatter_class=argparse.RawDescriptionHelpFormatter, + description="""Post-process Sphinx HTML.""", + epilog= + """ Copyright 2021-2021 by Wilson Snyder. This package is free software; +you can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") + +parser.add_argument('--debug', + action='store_const', + const=9, + help='enable debug') +parser.add_argument('path', help='path to edit') +Args = parser.parse_args() + +o = VlSphinxFix() +o.debug = Args.debug +o.process(Args.path) + +###################################################################### +# Local Variables: +# compile-command: "./vl_sphinx_fix --debug _build" +# End: diff --git a/docs/gen/ex_USERERROR_faulty.rst b/docs/gen/ex_USERERROR_faulty.rst new file mode 100644 index 000000000..fdd1a5978 --- /dev/null +++ b/docs/gen/ex_USERERROR_faulty.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: sv + + $error("User elaboration-time error"); diff --git a/docs/gen/ex_USERERROR_msg.rst b/docs/gen/ex_USERERROR_msg.rst new file mode 100644 index 000000000..386c97e57 --- /dev/null +++ b/docs/gen/ex_USERERROR_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: + + %Warning-USERERROR: example.v:1:7 User elaboration-time error diff --git a/docs/gen/ex_USERFATAL_faulty.rst b/docs/gen/ex_USERFATAL_faulty.rst new file mode 100644 index 000000000..2900b81b7 --- /dev/null +++ b/docs/gen/ex_USERFATAL_faulty.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: sv + + $fatal(0, "User elaboration-time fatal"); diff --git a/docs/gen/ex_USERFATAL_msg.rst b/docs/gen/ex_USERFATAL_msg.rst new file mode 100644 index 000000000..29fc57c93 --- /dev/null +++ b/docs/gen/ex_USERFATAL_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: + + %Warning-USERFATAL: example.v:1:7 User elaboration-time fatal diff --git a/docs/gen/ex_USERINFO_faulty.rst b/docs/gen/ex_USERINFO_faulty.rst new file mode 100644 index 000000000..ab9701e08 --- /dev/null +++ b/docs/gen/ex_USERINFO_faulty.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: sv + + $info("User elaboration-time info"); diff --git a/docs/gen/ex_USERINFO_msg.rst b/docs/gen/ex_USERINFO_msg.rst new file mode 100644 index 000000000..c30d89ec3 --- /dev/null +++ b/docs/gen/ex_USERINFO_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: + + -Info: example.v:1:7 User elaboration-time info diff --git a/docs/gen/ex_USERWARN_faulty.rst b/docs/gen/ex_USERWARN_faulty.rst new file mode 100644 index 000000000..fc2fb53fa --- /dev/null +++ b/docs/gen/ex_USERWARN_faulty.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: sv + + $warning("User elaboration-time warning"); diff --git a/docs/gen/ex_USERWARN_msg.rst b/docs/gen/ex_USERWARN_msg.rst new file mode 100644 index 000000000..e54250fdd --- /dev/null +++ b/docs/gen/ex_USERWARN_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: + + %Warning-USERWARN: example.v:1:7 User elaboration-time warning diff --git a/docs/gen/ex_VARHIDDEN_faulty.rst b/docs/gen/ex_VARHIDDEN_faulty.rst new file mode 100644 index 000000000..b982e6c90 --- /dev/null +++ b/docs/gen/ex_VARHIDDEN_faulty.rst @@ -0,0 +1,8 @@ +.. comment: generated by t_var_bad_hide_docs +.. code-block:: sv + :linenos: + :emphasize-lines: 2 + + module t; + integer t; //<--- Warning ('t' hidden by module 't') + endmodule diff --git a/docs/gen/ex_VARHIDDEN_msg.rst b/docs/gen/ex_VARHIDDEN_msg.rst new file mode 100644 index 000000000..08d7a5b9a --- /dev/null +++ b/docs/gen/ex_VARHIDDEN_msg.rst @@ -0,0 +1,5 @@ +.. comment: generated by t_var_bad_hide_docs +.. code-block:: + + %Warning-VARHIDDEN: example.v:2:12 Declaration of signal hides declaration in upper scope: 't' + example.v:1:8 ... Location of original declaration diff --git a/docs/gen/ex_WIDTH_1_faulty.rst b/docs/gen/ex_WIDTH_1_faulty.rst new file mode 100644 index 000000000..0121e66ac --- /dev/null +++ b/docs/gen/ex_WIDTH_1_faulty.rst @@ -0,0 +1,8 @@ +.. comment: generated by t_lint_width_docs_bad +.. code-block:: sv + :linenos: + :emphasize-lines: 3 + + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = array[rd_addr]; //<--- Warning diff --git a/docs/gen/ex_WIDTH_1_fixed.rst b/docs/gen/ex_WIDTH_1_fixed.rst new file mode 100644 index 000000000..11a33b7d0 --- /dev/null +++ b/docs/gen/ex_WIDTH_1_fixed.rst @@ -0,0 +1,5 @@ +.. comment: generated by t_lint_width_docs_bad +.. code-block:: sv + :emphasize-lines: 1 + + wire int rd_value = array[{1'b0, rd_addr}]; //<--- Fixed diff --git a/docs/gen/ex_WIDTH_1_msg.rst b/docs/gen/ex_WIDTH_1_msg.rst new file mode 100644 index 000000000..276a8ffc6 --- /dev/null +++ b/docs/gen/ex_WIDTH_1_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_lint_width_docs_bad +.. code-block:: + + %Warning-WIDTH: example.v:3:29 Bit extraction of array[4:0] requires 3 bit index, not 2 bits. diff --git a/docs/guide/changes.rst b/docs/guide/changes.rst new file mode 100644 index 000000000..439aaae79 --- /dev/null +++ b/docs/guide/changes.rst @@ -0,0 +1,16 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +**************** +Revision History +**************** + +.. COMMENT above header must use ### so there is an extra level of headers + here so the index won't show the huge list of revisions when clicking on + "Revision History" in the sidebar. + +Changes are contained in the :file:`Changes` file of the distribution, and +also summarized below. To subscribe to new versions see `Verilator +Announcements `_. + +.. include:: ../_build/gen/Changes diff --git a/docs/guide/conf.py b/docs/guide/conf.py new file mode 100644 index 000000000..1a94aa6b1 --- /dev/null +++ b/docs/guide/conf.py @@ -0,0 +1,221 @@ +# pylint: disable=E402 +# +# Configuration file for Verilator's Sphinx documentation builder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +# +# This file only contains overridden options. For a full list: +# https://www.sphinx-doc.org/en/master/usage/configuration.html +# +# ---------------------------------------------------------------------- +# -- Path setup + +from datetime import datetime +import os +import re +import shutil +import sys +sys.path.insert(0, os.path.abspath('./_ext')) + +import sphinx_rtd_theme + + +def get_vlt_version(): + filename = "../../src/config_rev.h" + with open(filename) as fh: + for line in fh: + match = re.search(r'= "([a-z0-9.]+)', line) + if match: + return match.group(1) + return "unknown" + + +# ---------------------------------------------------------------------- +# -- Project information + +project = 'Verilator' +copyright = '2021 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0' +author = 'Wilson Snyder' + +# The master toctree document. +master_doc = "guide/index" + +version = get_vlt_version() +release = get_vlt_version() + +rst_prolog = """ +.. role:: vlopt(option) +""" + +# ---------------------------------------------------------------------- +# -- General configuration + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +# To install: +# sudo install enchant +# sudo pip3 install sphinx sphinx_rtd_theme breathe sphinxcontrib-spelling +# We keep this list empty for now to avoid needing dependencies +extensions = [] +# extensions = ['breathe', 'sphinxcontrib.spelling'] + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +# This pattern also affects html_static_path and html_extra_path. +exclude_patterns = [ + '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst' +] + +# Warn about refs +nitpicky = True +nitpicky_ignore = [] + +# Number figures for referencing +numfig = True + +# The name of the Pygments (syntax highlighting) style to use. +pygments_style = "sphinx" + +# The suffix(es) of source filenames. +# You can specify multiple suffix as a list of string: +source_suffix = [".rst"] + +# Add any paths that contain templates here, relative to this directory. +templates_path = ['_templates'] + +# Date format to ISO +today_fmt = datetime.now().strftime("%F") + +# If true, `todo` and `todoList` produce output, else they produce nothing. +todo_include_todos = True + +# TODO could use this for internals<->guide references +# intersphinx_mapping = { 'sphinx': ('https://sphinx-doc.org/', None), } + +# ---------------------------------------------------------------------- +# -- Options for HTML output + +# html_baseurl = + +html_domain_indices = False + +html_logo = "../_static/verilator_192_150_min.png" + +html_theme = 'sphinx_rtd_theme' +html_theme_path = [sphinx_rtd_theme.get_html_theme_path()] + +html_theme_options = { + 'analytics_id': 'G-D27B0C9QEB', + 'logo_only': True, + 'style_nav_header_background': "#45acf8", # Default is #2980B9 + # 'canonical_url': +} + +html_context = { + 'display_github': True, + 'github_user': 'verilator', + 'github_repo': 'verilator', + 'github_version': 'master/docs/user/', +} + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = ['../_static'] + +# If true, "Created using Sphinx" is shown in the HTML footer. Default is True. +html_show_sphinx = False + +html_use_index = False + +html_favicon = "../_static/verilator_32x32_min.png" + +# Custom sidebar templates, maps document names to template names. +# html_sidebars + +# Add any extra paths that contain custom files (such as robots.txt or +# .htaccess) here, relative to this directory. These files are copied +# directly to the root of the documentation. +# html_extra_path = [] + +# Additional templates that should be rendered to pages, maps page names to +# template names. +# html_additional_pages = {} + +# ---------------------------------------------------------------------- +# -- Options for Latex output + +latex_logo = "../_static/verilator_logo.png" + +latex_elements = { + 'extraclassoptions': 'openany,oneside', + 'papersize': 'letterpaper', + 'makeindex': '', + 'printindex': '', + # 'pointsize': '10pt', + # 'preamble': '', +} + +# Grouping the document tree into LaTeX files. List of tuples +# (source start file, target name, title, +# author, documentclass [howto, manual, or own class]). +# latex_documents = [ +# ( +# master_doc, +# "Verilog-to-Routing.tex", +# "Verilog-to-Routing Documentation", +# "VTR Developers", +# "manual", +# ), +# ] + +# For "manual" documents, if this is true, then toplevel headings are parts, +# not chapters. +# latex_use_parts = False + +# If true, show page references after internal links. +# latex_show_pagerefs = False + +# If true, show URL addresses after external links. +# latex_show_urls = False + +latex_domain_indices = False + +# ---------------------------------------------------------------------- +# -- Options for manual page output + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +# man_pages = [(master_doc, "verilog-to-routing", "Verilog-to-Routing Documentation", [author], 1)] + +# If true, show URL addresses after external links. +# man_show_urls = False + +# ---------------------------------------------------------------------- +# -- Options for spelling + +spelling_word_list_filename = ['spelling.txt'] +spelling_ignore_contributor_names = True + +# ---------------------------------------------------------------------- +# -- Options for doxygen + +#if shutil.which("doxygen"): +# breathe_projects = { +# "verilated": "../_build/doxygen/verilated/xml", +# } +# breathe_default_project = "verilated" +# +# if not os.environ.get("SKIP_DOXYGEN", None) == "True": +# for prjname, prjdir in breathe_projects.items(): +# print("Generating doxygen files for {}...".format(prjname)) +# os.makedirs(prjdir, exist_ok=True) +# cmd = "cd ../_doxygen && doxygen {}.dox".format(prjname) +# subprocess.call(cmd, shell=True) +# else: +# for prjname, prjdir in breathe_projects.items(): +# assert os.path.exists(prjdir) == True, "Regenerate doxygen XML for {}".format(prjname) + +breathe_projects = {"verilated": "_build/doxygen/verilated/xml/"} +breathe_default_project = "verilated" +breathe_default_members = ('members') diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst new file mode 100644 index 000000000..720ecb8c1 --- /dev/null +++ b/docs/guide/connecting.rst @@ -0,0 +1,451 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Connecting: + +****************************** +Connecting to Verilated Models +****************************** + +.. _Connecting to C++: + +Connecting to C++ +================= + +Verilator creates a :file:`{prefix}.h` and :file:`{prefix}.cpp` file for +the top level module, together with additional .h and .cpp files for +internals. See the :file:`examples` directory in the kit for examples. See +:ref:`Files Read/Written` for information on all the files it writes. + +After the model is created, there will be a :file:`{prefix}.mk` file that +may be used with Make to produce a :file:`{prefix}__ALL.a` file with all +required objects in it. + +The user must write a C++ wrapper and main loop for the simulation, to link +with the Verilated model. Here is a simple example: + +.. code-block:: C++ + + #include // Defines common routines + #include // Need std::cout + #include "Vtop.h" // From Verilating "top.v" + + Vtop *top; // Instantiation of module + + vluint64_t main_time = 0; // Current simulation time + // This is a 64-bit integer to reduce wrap over issues and + // allow modulus. This is in units of the timeprecision + // used in Verilog (or from --timescale-override) + + double sc_time_stamp() { // Called by $time in Verilog + return main_time; // converts to double, to match + // what SystemC does + } + + int main(int argc, char** argv) { + Verilated::commandArgs(argc, argv); // Remember args + + top = new Vtop; // Create instance + + top->reset_l = 0; // Set some inputs + + while (!Verilated::gotFinish()) { + if (main_time > 10) { + top->reset_l = 1; // Deassert reset + } + if ((main_time % 10) == 1) { + top->clk = 1; // Toggle clock + } + if ((main_time % 10) == 6) { + top->clk = 0; + } + top->eval(); // Evaluate model + cout << top->out << endl; // Read a output + main_time++; // Time passes... + } + + top->final(); // Done simulating + // // (Though this example doesn't get here) + delete top; + } + + +Note signals are read and written as member variables of the model. You +call the :code:`eval()` method to evaluate the model. When the simulation +is complete call the :code:`final()` method to execute any SystemVerilog +final blocks, and complete any assertions. See :ref:`Evaluation Loop`. + + +Connecting to SystemC +===================== + +Verilator will convert the top level module to a SC_MODULE. This module +will attach directly into a SystemC netlist as an instantiation. + +The SC_MODULE gets the same pinout as the Verilog module, with the +following type conversions: Pins of a single bit become bool. Pins 2-32 +bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or +vluint64_t's depending on the :vlopt:`--no-pins64` option. Wider pins +become sc_bv's. (Uints simulate the fastest so are used where possible.) + +Lower modules are not pure SystemC code. This is a feature, as using the +SystemC pin interconnect scheme everywhere would reduce performance by an +order of magnitude. + + +Direct Programming Interface (DPI) +================================== + +Verilator supports SystemVerilog Direct Programming Interface import and +export statements. Only the SystemVerilog form ("DPI-C") is supported, not +the original Synopsys-only DPI. + +DPI Example +----------- + +In the SYSTEMC example above, if you wanted to import C++ functions into +Verilog, put in our.v: + +.. code-block:: + + import "DPI-C" function int add (input int a, input int b); + + initial begin + $display("%x + %x = %x", 1, 2, add(1,2)); + endtask + +Then after Verilating, Verilator will create a file Vour__Dpi.h with the +prototype to call this function: + +.. code-block:: C++ + + extern int add(int a, int b); + +From the sc_main.cpp file (or another .cpp file passed to the Verilator +command line, or the link), you'd then: + +.. code-block:: C++ + + #include "svdpi.h" + #include "Vour__Dpi.h" + int add(int a, int b) { return a+b; } + + +DPI System Task/Functions +------------------------- + +Verilator extends the DPI format to allow using the same scheme to +efficiently add system functions. Simply use a dollar-sign prefixed system +function name for the import, but note it must be escaped. + +.. code-block:: sv + + export "DPI-C" function integer \$myRand; + + initial $display("myRand=%d", $myRand()); + +Going the other direction, you can export Verilog tasks so they can be +called from C++: + +.. code-block:: sv + + export "DPI-C" task publicSetBool; + + task publicSetBool; + input bit in_bool; + var_bool = in_bool; + endtask + +Then after Verilating, Verilator will create a file Vour__Dpi.h with the +prototype to call this function: + +.. code-block:: C++ + + extern void publicSetBool(svBit in_bool); + +From the sc_main.cpp file, you'd then: + +.. code-block:: C++ + + #include "Vour__Dpi.h" + publicSetBool(value); + +Or, alternatively, call the function under the design class. This isn't +DPI compatible but is easier to read and better supports multiple designs. + +.. code-block:: C++ + + #include "Vour__Dpi.h" + Vour::publicSetBool(value); + // or top->publicSetBool(value); + +Note that if the DPI task or function accesses any register or net within +the RTL, it will require a scope to be set. This can be done using the +standard functions within svdpi.h, after the module is instantiated, but +before the task(s) and/or function(s) are called. + +For example, if the top level module is instantiated with the name "dut" +and the name references within tasks are all hierarchical (dotted) names +with respect to that top level module, then the scope could be set with + +.. code-block:: C++ + + #include "svdpi.h" + ... + svSetScope(svGetScopeFromName("TOP.dut")); + +(Remember that Verilator adds a "TOP" to the top of the module hierarchy.) + +Scope can also be set from within a DPI imported C function that has been +called from Verilog by querying the scope of that function. See the +sections on DPI Context Functions and DPI Header Isolation below and the +comments within the svdpi.h header for more information. + + +DPI Imports that access signals +------------------------------- + +If a DPI import accesses a signal through the VPI Verilator will not be +able to know what variables are accessed and may schedule the code +inappropriately. Ideally pass the values as inputs/outputs so the VPI is +not required. Alternatively a workaround is to use a non-inlined task as a +wrapper: + +.. code-block:: + + logic din; + + // This DPI function will read "din" + import "DPI-C" context function void dpi_that_accesses_din(); + + always @(...) + dpi_din_args(din); + + task dpi_din_args(input din); + /* verilator no_inline_task */ + dpi_that_accesses_din(); + endtask + + +DPI Display Functions +--------------------- + +Verilator allows writing $display like functions using this syntax: + +.. code-block:: + + import "DPI-C" function void + \$my_display(input string formatted /*verilator sformat*/ ); + +The :option:`/*verilator&32;sformat*/` metacomment indicates that this +function accepts a $display like format specifier followed by any number of +arguments to satisfy the format. + + +DPI Context Functions +--------------------- + +Verilator supports IEEE DPI Context Functions. Context imports pass the +simulator context, including calling scope name, and filename and line +number to the C code. For example, in Verilog: + +.. code-block:: + + import "DPI-C" context function int dpic_line(); + initial $display("This is line %d, again, line %d\n", `line, dpic_line()); + +This will call C++ code which may then use the svGet\* functions to read +information, in this case the line number of the Verilog statement that +invoked the dpic_line function: + +.. code-block:: C++ + + int dpic_line() { + // Get a scope: svScope scope = svGetScope(); + + const char* scopenamep = svGetNameFromScope(scope); + assert(scopenamep); + + const char* filenamep = ""; + int lineno = 0; + if (svGetCallerInfo(&filenamep, &lineno)) { + printf("dpic_line called from scope %s on line %d\n", + scopenamep, lineno); + return lineno; + } else { + return 0; + } + } + +See the IEEE Standard for more information. + + +DPI Header Isolation +-------------------- + +Verilator places the IEEE standard header files such as svdpi.h into a +separate include directory, vltstd (VeriLaTor STandarD). When compiling +most applications $VERILATOR_ROOT/include/vltstd would be in the include +path along with the normal $VERILATOR_ROOT/include. However, when +compiling Verilated models into other simulators which have their own +svdpi.h and similar standard files with different contents, the vltstd +directory should not be included to prevent picking up incompatible +definitions. + + +Public Functions +---------------- + +Instead of DPI exporting, there's also Verilator public functions, which +are slightly faster, but less compatible. + + +Verification Procedural Interface (VPI) +======================================= + +Verilator supports a limited subset of the VPI. This subset allows +inspection, examination, value change callbacks, and depositing of values +to public signals only. + +VPI is enabled with the Verilator :vlopt:`--vpi` option. + +To access signals via the VPI, Verilator must be told exactly which signals +are to be accessed. This is done using the Verilator public pragmas +documented below. + +Verilator has an important difference from an event based simulator; signal +values that are changed by the VPI will not immediately propagate their +values, instead the top level header file's :code:`eval()` method must be +called. Normally this would be part of the normal evaluation (i.e. the +next clock edge), not as part of the value change. This makes the +performance of VPI routines extremely fast compared to event based +simulators, but can confuse some test-benches that expect immediate +propagation. + +Note the VPI by its specified implementation will always be much slower +than accessing the Verilator values by direct reference +(structure->module->signame), as the VPI accessors perform lookup in +functions at simulation runtime requiring at best hundreds of instructions, +while the direct references are evaluated by the compiler and result in +only a couple of instructions. + +For signal callbacks to work the main loop of the program must call +:code:`VerilatedVpi::callValueCbs()`. + + +.. _VPI Example: + +VPI Example +----------- + +In the below example, we have readme marked read-only, and writeme which if +written from outside the model will have the same semantics as if it +changed on the specified clock edge. + +.. code-block:: bash + + cat >our.v <<'EOF' + module our (input clk); + reg readme /*verilator public_flat_rd*/; + reg writeme /*verilator public_flat_rw @(posedge clk) */; + initial $finish; + endmodule + EOF + +There are many online tutorials and books on the VPI, but an example that +accesses the above signal "readme" would be: + +.. code-block:: bash + + cat >sim_main.cpp <<'<eval(); + VerilatedVpi::callValueCbs(); // For signal callbacks + read_and_check(); + } + delete top; + return 0; + } + EOF + + +.. _Evaluation Loop: + +Wrappers and Model Evaluation Loop +================================== + +When using SystemC, evaluation of the Verilated model is managed by the +SystemC kernel, and for the most part can be ignored. When using C++, the +user must call :code:`eval()`, or :code:`eval_step()` and +:code:`eval_end_step()`. + +1. When there is a single design instantiated at the C++ level that needs +to evaluate within a given context, call :code:`designp->eval()`. + +2. When there are multiple designs instantiated at the C++ level that need +to evaluate within a context, call :code:`first_designp->eval_step()` then +:code:`->eval_step()` on all other designs. Then call +:code:`->eval_end_step()` on the first design then all other designs. If +there is only a single design, you would call :code:`eval_step()` then +:code:`eval_end_step()`; in fact :code:`eval()` described above is just a +wrapper which calls these two functions. + +When :code:`eval()` (or :code:`eval_step()`) is called Verilator looks for +changes in clock signals and evaluates related sequential always blocks, +such as computing always_ff @ (posedge...) outputs. Then Verilator +evaluates combinatorial logic. + +Note combinatorial logic is not computed before sequential always blocks +are computed (for speed reasons). Therefore it is best to set any non-clock +inputs up with a separate :code:`eval()` call before changing clocks. + +Alternatively, if all always_ff statements use only the posedge of clocks, +or all inputs go directly to always_ff statements, as is typical, then you +can change non-clock inputs on the negative edge of the input clock, which +will be faster as there will be fewer :code:`eval()` calls. + +For more information on evaluation, see :file:`docs/internals.rst` in the +distribution. + + +Verilated and VerilatedContext +============================== + +Multiple Verilated models may be part of the same simulation context, that +is share a VPI interface, sense of time, and common settings. This common +simulation context information is stored in a ``VerilatedContext`` +structure. If a ``VerilatedContext`` is not created prior to creating a +model, a default global one is created automatically. + +The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call +shown above, simply call VerilatedContext methods using the default global +VerilatedContext. (Technically they operate on the last one used by a +given thread.) If you are using multiple simulation contexts you should +not use the Verilated:: methods, and instead always use VerilatedContext +methods called on the appropriate VerilatedContext object. + +For methods available under Verilated and VerilatedContext see +:file:`include/verilated.h` in the distribution. diff --git a/docs/guide/contributing.rst b/docs/guide/contributing.rst new file mode 100644 index 000000000..d3d091bae --- /dev/null +++ b/docs/guide/contributing.rst @@ -0,0 +1,68 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +******************************* +Contributing and Reporting Bugs +******************************* + +Announcements +============= + +To get notified of new releases and other important announcements, go to +`Verilator announcement repository +`__ and follow the +instructions there. + + +Reporting Bugs +============== + +First, check the :ref:`Language Limitations` section. + +Next, try the :vlopt:`--debug` option. This will enable additional +internal assertions, and may help identify the problem. + +Finally, reduce your code to the smallest possible routine that exhibits +the bug. Even better, create a test in the :file:`test_regress/t` +directory, as follows: + +.. code-block:: bash + + cd test_regress + cp -p t/t_EXAMPLE.pl t/t_BUG.pl + cp -p t/t_EXAMPLE.v t/t_BUG.v + +There are many hints on how to write a good test in the +:file:`test_regress/driver.pl` documentation which can be seen by running: + +.. code-block:: bash + + cd $VERILATOR_ROOT # Need the original distribution kit + test_regress/driver.pl --help + +Edit :file:`t/t_BUG.pl` to suit your example; you can do anything you want +in the Verilog code there; just make sure it retains the single clk input +and no outputs. Now, the following should fail: + +.. code-block:: bash + + cd $VERILATOR_ROOT # Need the original distribution kit + cd test_regress + t/t_BUG.pl # Run on Verilator + t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator + t/t_BUG.pl --vcs # Run on VCS simulator + t/t_BUG.pl --nc|--iv|--ghdl # Likewise on other simulators + +The test driver accepts a number of options, many of which mirror the main +Verilator options. For example the previous test could have been run with +debugging enabled. The full set of test options can be seen by running +:command:`driver.pl --help` as shown above. + +Finally, report the bug at `Verilator Issues +`_. The bug will become publicly visible; if +this is unacceptable, mail the bug report to ``wsnyder@wsnyder.org``. + + +.. Contributing +.. ============ +.. include:: ../CONTRIBUTING.rst diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst new file mode 100644 index 000000000..c38cb8515 --- /dev/null +++ b/docs/guide/contributors.rst @@ -0,0 +1,155 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +************************ +Contributors and Origins +************************ + +Authors +======= + +When possible, please instead report bugs at `Verilator Issues +`_. + +Primary author is Wilson Snyder . + +Major concepts by Paul Wasson, Duane Galbi, John Coiner and Jie Xu. + + +Contributors +============ + +Many people have provided ideas and other assistance with Verilator. + +Verilator is receiving major development support from the `CHIPS Alliance +`_. + +Previous major corporate sponsors of Verilator, by providing significant +contributions of time or funds included include: Atmel Corporation, Cavium +Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., +Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune +Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc., +and SiCortex Inc. + +The people who have contributed major functionality are: Byron Bradley, +Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd +Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, and Wilson Snyder. +Major testers included Jeff Dutton, Jonathon Donaldson, Ralf Karge, David +Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van +Cauwenberghe, Gene Weber, and Clifford Wolf. + +Some of the people who have provided ideas, and feedback for Verilator +include: David Addison, Nikana Anastasiadis, Vasu Arasanipalai, Jens Arm, +Tariq B. Ahmad, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew +Barr, Geoff Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael +Berman, Jean Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof +Bieganski, David Binderman, Piotr Binkowski, Johan Bjork, David Black, +Tymoteusz Blazejczyk, Daniel Bone, Morten Borup Petersen, Gregg Bouchard, +Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Charlie +Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, +Tony Bybell, Iru Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal +Casey, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark, +Ryan Clarke, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean +Cross, George Cuan, Joe DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh +Das, Maarten De Braekeleer, Bernard Deadman, Alberto Del Rio, John Demme, +Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny +Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Sebastian Dressler, +Alex Duller, Jeff Dutton, Tomas Dzetkulic, Richard E George, Edgar +E. Iglesias, Usuario Eda, Charles Eddleston, Chandan Egbert, Jan Egil Ruud, +Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Charles Eric +LaForest, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein, +Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner, +Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl, +Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Andrew +Goessling, Amir Gonnen, Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner, +Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil +Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto, +Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry, Stephen +Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki +Honda, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath, Jae +Hossell, Kuoping Hsu, Alan Hunter, James Hutchinson, Anderson Ignacio da +Silva, Jamie Iles, Thomas J Whatson, Ben Jackson, Mark Jackson Pulver, +Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong, Iztok +Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike +Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, +Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf +Karge, Dan Katz, Sol Katzman, Ian Kennedy, Michael Killough, Jonathan +Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot +Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, +Will Korteland, Wojciech Koszek, Varun Koyyalagunta, Markus Krause, David +Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok, Ed Lander, Steve +Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor +Lesik, John Li, Eivind Liland, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul +Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan +Lussier, Fred Ma, Duraid Madina, Odd Magne Reitan, Affe Mao, Julien +Margetts, Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Yves +Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot Mednick, +Wim Michiels, Miodrag Milanovic, Peter Monsson, Sean Moore, Dennis +Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris +Nalbantis, Peter Nelson, Bob Newgard, Paul Nitza, Yossi Nivin, Pete Nixon, +Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz, +Aleksander Osman, Don Owen, James Pallister, Vassilis Papaefstathiou, Brad +Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Cody Piersall, +Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter, +Niranjan Prabhu, Usha Priyadharshini, Prateek Puri, Marshal Qiao, Nandu +Raj, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Frederic +Requin, Dustin Richmond, Samuel Riedel, Eric Rippey, Oleg Rodionov, Ludwig +Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Denis +Rystsov, John Sanguinetti, Galen Seitz, Joseph Shaker, Salman Sheikh, Yu +Sheng Lin, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan +Shupei, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim +Snyder, Wilson Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, +Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson, +Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki, +Howard Su, Emerson Suguimoto, Gene Sullivan, Wai Sum Mong, Qingyao Sun, +Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Thierry Tambe, +Drew Taussig, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede, +Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, +Viktor Tomov, Steve Tong, Alex Torregrosa, Michael Tresidder, David Turner, +Neil Turton, Cong Van Nguyen, Hans Van Antwerpen, Jan Van Winkel, Sebastien +Van Cauwenberghe, Laurens van Dam, Leendert van Doorn, Srini Vemuri, Yuri +Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan +Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene +Weber, David Welch, Martin Whitaker, Marco Widmer, Leon Wildman, Daniel +Wilkerson, Gerald Williams, Trevor Williams, Jeff Winston, Joshua Wise, +Clifford Wolf, Tobias Wolfel, Johan Wouters, Paul Wright, Junyi Xi, Ding +Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke Yang, Amir Yazdanbakhsh, and +Keyi Zhang. + +Thanks to them, and all those we've missed including above, or wished to +remain anonymous. + +Historical Origins +================== + +Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at +Digital Equipment Corporation. The Verilog code that was converted to C +was then merged with a C based CPU model of the Alpha processor and +simulated in a C based environment called CCLI. + +In 1995 Verilator started being used also for Multimedia and Network +Processor development inside Digital. Duane Galbi took over active +development of Verilator, and added several performance enhancements. CCLI +was still being used as the shell. + +In 1998, through the efforts of existing DECies, mainly Duane Galbi, +Digital graciously agreed to release the source code. (Subject to the code +not being resold, which is compatible with the GNU Public License.) + +In 2001, Wilson Snyder took the kit, and added a SystemC mode, and called +it Verilator2. This was the first packaged public release. + +In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from +scratch in C++. This added many optimizations, yielding about a 2-5x +performance gain. + +In 2009, major SystemVerilog and DPI language support was added. + +In 2018, Verilator 4.000 was released with multithreaded support. + +In 2019, Verilator joined the `CHIPS Alliance +`_. + +Currently, various language features and performance enhancements are added +as the need arises. Verilator is now about 3x faster than in 2002, and is +faster than most (if not every) other simulator. diff --git a/docs/guide/copyright.rst b/docs/guide/copyright.rst new file mode 100644 index 000000000..e00dc420a --- /dev/null +++ b/docs/guide/copyright.rst @@ -0,0 +1,19 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +********* +Copyright +********* + +The latest version of Verilator is available from `https://verilator.org +`_. + +Copyright 2003-2021 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify the Verilator internals under the terms +of either the GNU Lesser General Public License Version 3 or the Perl +Artistic License Version 2.0. + +All Verilog and C++/SystemC code quoted within this documentation file are +released as Creative Commons Public Domain (CC0). Many example files and +test files are likewise released under CC0 into effectively the Public +Domain as described in the files themselves. diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst new file mode 100644 index 000000000..ddb7546db --- /dev/null +++ b/docs/guide/deprecations.rst @@ -0,0 +1,28 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +Deprecations +============ + +The following deprecated items are scheduled for future removal: + +C++11 compiler support + Verilator currently requires C++11 or newer compilers. Verilator will + require C++14 or newer compilers for both compiling Verilator and + compiling Verilated models no sooner than January 2022. + +No-Relative-Cfuncs Option + The :vlopt:`--no-relative-cfuncs` option is not be required by any C++11 + compliant compiler and is planned for removal no sooner than July 2021. + +Inhibit-Sim Option + The :vlopt:`--inhibit-sim` option is planned for removal no sooner than + July 2021. + +Configuration File -msg + The :vlopt:`lint_off` "-msg" option has been replaced with the "-rule" + option. "-msg" is planned for removal no sooner than January 2021. + +XML locations + The XML "fl" attribute has been replaced with the "loc" attribute. "fl" + is planned for removal no sooner than January 2021. diff --git a/docs/guide/environment.rst b/docs/guide/environment.rst new file mode 100644 index 000000000..f52fe0a41 --- /dev/null +++ b/docs/guide/environment.rst @@ -0,0 +1,93 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +Environment +=========== + +This section describes the environment variables used by Verilator and +associated programs. + +.. option:: LD_LIBRARY_PATH + + A generic Linux/OS variable specifying what directories have shared + object (.so) files. This path should include SystemC and any other + shared objects needed at simulation runtime. + +.. option:: MAKE + + Names the executable of the make command invoked when using the + :vlopt:`--build` option. Some operating systems may require "gmake" to + this variable to launch GNU make. If this variable is not specified, + "make" is used. + +.. option:: OBJCACHE + + Optionally specifies a caching or distribution program to place in front + of all runs of the C++ compiler. For example, "ccache". If using + :command:`distcc` or :command:`icecc`/:command:`icecream`, they would + generally be run under :command:`ccache`; see the documentation for + those programs. If OBJCACHE is not set, and at configure time ccache + was present, ccache will be used as a default. + +.. option:: SYSTEMC + + Deprecated. Used only if :option:`SYSTEMC_INCLUDE` or + :option:`SYSTEMC_LIBDIR` is not set. If set, specifies the directory + containing the SystemC distribution. If not specified, it will come + from a default optionally specified at configure time (before Verilator + was compiled). + +.. option:: SYSTEMC_ARCH + + Deprecated. Used only if :option:`SYSTEMC_LIBDIR` is not set. + Specifies the architecture name used by the SystemC kit. This is the + part after the dash in the "lib-{...}" directory name created by a + :command:`make` in the SystemC distribution. If not set, Verilator will + try to intuit the proper setting, or use the default optionally + specified at configure time (before Verilator was compiled). + +.. option:: SYSTEMC_CXX_FLAGS + + Specifies additional flags that are required to be passed to GCC when + building the SystemC model. System 2.3.0 may need this set to + "-pthread". + +.. option:: SYSTEMC_INCLUDE + + If set, specifies the directory containing the systemc.h header file. If + not specified, it will come from a default optionally specified at + configure time (before Verilator was compiled), or computed from + SYSTEMC/include. + +.. option:: SYSTEMC_LIBDIR + + If set, specifies the directory containing the libsystemc.a library. If + not specified, it will come from a default optionally specified at + configure time (before Verilator was compiled), or computed from + SYSTEMC/lib-SYSTEMC_ARCH. + +.. option:: VERILATOR_BIN + + If set, specifies an alternative name of the ``verilator`` binary. May + be used for debugging and selecting between multiple operating system + builds. + +.. option:: VERILATOR_COVERAGE_BIN + + If set, specifies an alternative name of the ``verilator_coverage`` + binary. May be used for debugging and selecting between multiple + operating system builds. + +.. option:: VERILATOR_GDB + + If set, the command to run when using the :vlopt:`--gdb` option, such as + "ddd". If not specified, it will use "gdb". + +.. option:: VERILATOR_ROOT + + Specifies the directory containing the distribution kit. This is used + to find the executable, Perl library, and include files. If not + specified, it will come from a default optionally specified at configure + time (before Verilator was compiled). It should not be specified if + using a pre-compiled Verilator package as the hard-coded value should be + correct. See :ref:`Installation`. diff --git a/docs/guide/example_cc.rst b/docs/guide/example_cc.rst new file mode 100644 index 000000000..1894c2074 --- /dev/null +++ b/docs/guide/example_cc.rst @@ -0,0 +1,92 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Example C++ Execution: + +Example C++ Execution +===================== + +We'll compile this example into C++. For an extended and commented version +of what this C++ code is doing, see +:file:`examples/make_tracing_c/sim_main.cpp` in the distribution. + +.. include:: example_common_install.rst + +Now, let's create an example Verilog, and C++ wrapper file: + +.. code-block:: bash + + mkdir test_our + cd test_our + + cat >our.v <<'EOF' + module our; + initial begin $display("Hello World"); $finish; end + endmodule + EOF + + cat >sim_main.cpp <<'EOF' + #include "Vour.h" + #include "verilated.h" + int main(int argc, char** argv, char** env) { + VerilatedContext* contextp = new VerilatedContext; + contextp->commandArgs(argc, argv); + Vour* top = new Vour{contextp}; + while (!contextp->gotFinish()) { top->eval(); } + delete top; + delete contextp; + return 0; + } + EOF + +Now we run Verilator on our little example. + +.. code-block:: bash + + verilator -Wall --cc --exe --build sim_main.cpp our.v + +Breaking this command down: + +#. :vlopt:`-Wall` so Verilator has stronger lint warnings + enabled. + +#. :vlopt:`--cc` to get C++ output (versus e.g. SystemC + or only linting). + +#. :vlopt:`--exe`, along with our :command:`sim_main.cpp` wrapper file, so + the build will create an executable instead of only a library. + +#. :vlopt:`--build` so Verilator will call make itself. This is we don't + need to manually call make as a separate step. You can also write your + own compile rules, and run make yourself as we show in :ref:`Example + SystemC Execution`.) + +#. An finally, :command:`our.v` which is our SystemVerilog design file. + +Once Verilator completes we can see the generated C++ code under the +:file:`obj_dir` directory. + +.. code-block:: bash + + ls -l obj_dir + +(See :ref:`Files Read/Written` for descriptions of some of the files that +were created.) + +And now we run it: + +.. code-block:: bash + + obj_dir/Vour + +And we get as output: + +.. code-block:: bash + + Hello World + - our.v:2: Verilog $finish + +Really, you're better off using a Makefile to run the steps for you so when +your source changes it will automatically run all of the appropriate steps. +To aid this Verilator can create a makefile dependency file. For examples +that do this see the :file:`examples` directory in the distribution. diff --git a/docs/guide/example_common_install.rst b/docs/guide/example_common_install.rst new file mode 100644 index 000000000..4a7795344 --- /dev/null +++ b/docs/guide/example_common_install.rst @@ -0,0 +1,18 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +First you need Verilator installed, see :ref:`Installation`. In brief, if +you installed Verilator using the package manager of your operating system, +or did a :command:`make install` to place Verilator into your default path, +you do not need anything special in your environment, and should not have +VERILATOR_ROOT set. However, if you installed Verilator from sources and +want to run Verilator out of where you compiled Verilator, you need to +point to the kit: + +.. code-block:: bash + + # See above; don't do this if using an OS-distributed Verilator + export VERILATOR_ROOT=/path/to/where/verilator/was/installed + export PATH=$VERILATOR_ROOT/bin:$PATH + + diff --git a/docs/guide/example_dist.rst b/docs/guide/example_dist.rst new file mode 100644 index 000000000..493e3d204 --- /dev/null +++ b/docs/guide/example_dist.rst @@ -0,0 +1,40 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Examples in the Distribution: + +Examples in the Distribution +============================ + +See the ``examples/`` directory that is part of the distribution, and +is installed (in a OS-specific place, often in e.g. +``/usr/local/share/verilator/examples``). These examples include: + +examples/make_hello_c + Example GNU-make simple Verilog->C++ conversion +examples/make_hello_sc + Example GNU-make simple Verilog->SystemC conversion +examples/make_tracing_c + Example GNU-make Verilog->C++ with tracing +examples/make_tracing_sc + Example GNU-make Verilog->SystemC with tracing +examples/make_protect_lib + Example using --protect-lib +examples/cmake_hello_c + Example building make_hello_c with CMake +examples/cmake_hello_sc + Example building make_hello_sc with CMake +examples/cmake_tracing_c + Example building make_tracing_c with CMake +examples/cmake_tracing_sc + Example building make_tracing_sc with CMake +examples/cmake_protect_lib + Example building make_protect_lib with CMake + +To run an example copy the example to a new directory and run it. + +:: + + cp -rp {path_to}/examples/make_hello_c make_hello_c + cd make_hello_c + make diff --git a/docs/guide/example_sc.rst b/docs/guide/example_sc.rst new file mode 100644 index 000000000..4e982f3b3 --- /dev/null +++ b/docs/guide/example_sc.rst @@ -0,0 +1,73 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Example SystemC Execution: + +Example SystemC Execution +========================= + +This is an example similar to the :ref:`Example C++ Execution`, but using +SystemC. We'll also explicitly run make. + +.. include:: example_common_install.rst + +Now, let's create an example Verilog, and SystemC wrapper file: + +.. code-block:: bash + + mkdir test_our_sc + cd test_our_sc + + cat >our.v <<'EOF' + module our (clk); + input clk; // Clock is required to get initial activation + always @(posedge clk) + begin $display("Hello World"); $finish; end + endmodule + EOF + + cat >sc_main.cpp <<'EOF' + #include "Vour.h" + int sc_main(int argc, char** argv) { + Verilated::commandArgs(argc, argv); + sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true}; + Vour* top = new Vour{"top"}; + top->clk(clk); + while (!Verilated::gotFinish()) { sc_start(1, SC_NS); } + delete top; + return 0; + } + EOF + +Now we run Verilator on our little example: + +.. code-block:: bash + + verilator -Wall --sc --exe sc_main.cpp our.v + +This example does not use --build, therefore we need to explicitly compile +it: + +.. code-block:: bash + + make -j -C obj_dir -f Vour.mk Vour + +And now we run it: + +.. code-block:: bash + + obj_dir/Vour + +And we get, after the SystemC banner, the same output as the C++ example: + +.. code-block:: bash + + SystemC 2.3.3-Accellera + + Hello World + - our.v:4: Verilog $finish + +Really, you're better off using a Makefile to run the steps for you so when +your source changes it will automatically run all of the appropriate steps. +For examples that do this see the :file:`examples` directory in the +distribution. diff --git a/docs/guide/examples.rst b/docs/guide/examples.rst new file mode 100644 index 000000000..83b94f770 --- /dev/null +++ b/docs/guide/examples.rst @@ -0,0 +1,22 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Examples: + +======== +Examples +======== + +This section covers the following examples: + +* :ref:`Example C++ Execution` +* :ref:`Example SystemC Execution` +* :ref:`Examples in the Distribution` + +.. toctree:: + :maxdepth: 1 + :hidden: + + example_cc.rst + example_sc.rst + example_dist.rst diff --git a/docs/guide/exe_sim.rst b/docs/guide/exe_sim.rst new file mode 100644 index 000000000..bd805aab8 --- /dev/null +++ b/docs/guide/exe_sim.rst @@ -0,0 +1,89 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Simulation Runtime Arguments: + +Simulation Runtime Arguments +============================ + +The following are the arguments that may be passed to a Verilated +executable, provided that executable calls +:code:`Verilated::commandArgs()`. + +All simulation runtime arguments begin with "+verilator", so that the +user's executable may skip over all "+verilator" arguments when parsing its +command line. + +Summary: + + .. include:: ../_build/gen/args_verilated.rst + + +.. option:: +verilator+debug + + Enable simulation runtime debugging. Equivalent to + :vlopt:`+verilator+debugi+4 <+verilator+debugi+\>`. + +.. option:: +verilator+debugi+ + + Enable simulation runtime debugging at the provided level. + +.. option:: +verilator+error+limit+ + + Set number of non-fatal errors (e.g. assertion failures) before exiting + simulation runtime. Also affects number of $stop calls needed before + exit. Defaults to 1. + +.. option:: +verilator+help + + Display help and exit. + +.. option:: +verilator+prof+threads+file+ + + When a model was Verilated using :vlopt:`--prof-threads`, sets the + simulation runtime filename to dump to. Defaults to + :file:`profile_threads.dat`. + +.. option:: +verilator+prof+threads+start+ + + When a model was Verilated using :vlopt:`--prof-threads`, the simulation + runtime will wait until $time is at this value (expressed in units of + the time precision), then start the profiling warmup, then + capturing. Generally this should be set to some time that is well within + the normal operation of the simulation, i.e. outside of reset. If 0, the + dump is disabled. Defaults to 1. + +.. option:: +verilator+prof+threads+window+ + + When a model was Verilated using :vlopt:`--prof-threads`, after $time + reaches :vlopt:`+verilator+prof+threads+start+\`, Verilator will + warm up the profiling for this number of eval() calls, then will capture + the profiling of this number of eval() calls. Defaults to 2, which + makes sense for a single-clock-domain module where it's typical to want + to capture one posedge eval() and one negedge eval(). + +.. option:: +verilator+rand+reset+ + + When a model was Verilated using :vlopt:`--x-initial unique + <--x-initial>`, sets the simulation runtime initialization technique. 0 + = Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See + :ref:`Unknown States`. + +.. option:: +verilator+seed+ + + For $random and :vlopt:`--x-initial unique <--x-initial>`, set the + simulation runtime random seed value. If zero or not specified picks a + value from the system random number generator. + +.. option:: +verilator+noassert + + Disable assert checking per runtime argument. This is the same as + calling :code:`Verilated::assertOn(false)` in the model. + +.. option:: +verilator+V + + Shows the verbose version, including configuration information. + +.. option:: +verilator+version + + Displays program version and exits. diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst new file mode 100644 index 000000000..060d80d2d --- /dev/null +++ b/docs/guide/exe_verilator.rst @@ -0,0 +1,1623 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +verilator Arguments +=================== + +The following are the arguments that may be passed to the "verilator" +executable. + +Summary: + + .. include:: ../_build/gen/args_verilator.rst + + +.. option:: + + Specifies the Verilog file containing the top module to be Verilated. + +.. option:: + + Used with :vlopt:`--exe` to specify optional C++ files to be linked in + with the Verilog code. The file path should either be absolute, or + relative to where the make will be executed from, or add to your + makefile's VPATH the appropriate directory to find the file. + + See also :vlopt:`-CFLAGS` and :vlopt:`-LDFLAGS` options, which are + useful when the C++ files need special compiler flags. + +.. option:: + + Specifies optional object or library files to be linked in with the + Verilog code, as a shorthand for :vlopt:`-LDFLAGS \ + <-LDFLAGS>`. The file path should either be absolute, or relative to + where the make will be executed from, or add to your makefile's VPATH + the appropriate directory to find the file. + + If any files are specified in this way, Verilator will include a make + rule that uses these files when linking the module's executable. This + generally is only useful when used with the :vlopt:`--exe` option. + +.. option:: +1364-1995ext+ + +.. option:: +1364-2001ext+ + +.. option:: +1364-2005ext+ + +.. option:: +1800-2005ext+ + +.. option:: +1800-2009ext+ + +.. option:: +1800-2012ext+ + +.. option:: +1800-2017ext+ + + Specifies the language standard to be used with a specific filename + extension, . + + For compatibility with other simulators, see also the synonyms + :vlopt:`+verilog1995ext+\`, :vlopt:`+verilog2001ext+\`, and + :vlopt:`+systemverilogext+\`. + + For any source file, the language specified by these options takes + precedence over any language specified by the + :vlopt:`--default-language` or :vlopt:`--language` options. + + These options take effect in the order they are encountered. Thus the + following would use Verilog 1995 for ``a.v`` and Verilog 2001 for + ``b.v``: + + .. code-block:: bash + + verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v + + These options are only recommended for legacy mixed language designs, as + the preferable option is to edit the code to repair new keywords, or add + appropriate ```begin_keywords``. + + .. note:: + + ```begin_keywords`` is a SystemVerilog construct, which specifies + *only* the set of keywords to be recognized. This also controls some + error messages that vary between language standards. Note at present + Verilator tends to be overly permissive, e.g. it will accept many + grammar and other semantic extensions which might not be legal when + set to an older standard. + +.. option:: --assert + + Enable all assertions. + +.. option:: --autoflush + + After every $display or $fdisplay, flush the output stream. This + ensures that messages will appear immediately but may reduce + performance. For best performance call :code:`fflush(stdout)` + occasionally in the C++ main loop. Defaults to off, which will buffer + output as provided by the normal C/C++ standard library IO. + +.. option:: --bbox-sys + + Black box any unknown $system task or function calls. System tasks will + simply become no-operations, and system functions will be replaced with + unsized zero. Arguments to such functions will be parsed, but not + otherwise checked. This prevents errors when linting in the presence of + company specific PLI calls. + + Using this argument will likely cause incorrect simulation. + +.. option:: --bbox-unsup + + Black box some unsupported language features, currently UDP tables, the + cmos and tran gate primitives, deassign statements, and mixed edge + errors. This may enable linting the rest of the design even when + unsupported constructs are present. + + Using this argument will likely cause incorrect simulation. + +.. option:: --bin + + Rarely needed. Override the default filename for Verilator itself. + When a dependency (.d) file is created, this filename will become a + source dependency, such that a change in this binary will have make + rebuild the output files. + +.. option:: --build + + After generating the SystemC/C++ code, Verilator will invoke the + toolchain to build the model library (and executable when :vlopt:`--exe` + is also used). Verilator manages the build itself, and for this --build + requires GNU Make to be available on the platform. + +.. option:: -CFLAGS + + Add specified C compiler argument to the generated makefiles. For + multiple flags either pass them as a single argument with space + separators quoted in the shell (:command:`-CFLAGS "-a -b"`), or use + multiple -CFLAGS options (:command:`-CFLAGS -a -CFLAGS -b`). + + When make is run on the generated makefile these will be passed to the + C++ compiler (g++/clang++/msvc++). + +.. option:: --cc + + Specifies C++ without SystemC output mode; see also :vlopt:`--sc` + option. + +.. option:: --cdc + + Permanently experimental. Perform some clock domain crossing checks and + issue related warnings (CDCRSTLOGIC) and then exit; if warnings other + than CDC warnings are needed make a second run with + :vlopt:`--lint-only`. Additional warning information is also written to + the file :file:`__cdc.txt`. + + Currently only checks some items that other CDC tools missed; if you + have interest in adding more traditional CDC checks, please contact the + authors. + +.. option:: --clk + + Sometimes it is quite difficult for Verilator to distinguish clock + signals from other data signals. Occasionally the clock signals can end + up in the checking list of signals which determines if further + evaluation is needed. This will heavily degrade the performance of a + Verilated model. + + With :vlopt:`--clk`, the specified signal-name is taken as a root clock + into the model, then Verilator will mark the signal as clocker and + propagate the clocker attribute automatically to other signals derived + from that. In this way, Verilator will try to avoid taking the clocker + signal into checking list. + + Note signal-name is specified by the RTL hierarchy path. For example, + v.foo.bar. If the signal is the input to top-module, the directly the + signal name. If you find it difficult to find the exact name, try to use + a :option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the + signal directly. + + If clock signals are assigned to vectors and then later used + individually, Verilator will attempt to decompose the vector and connect + the single-bit clock signals directly. This should be transparent to + the user. + +.. option:: --make + + Generates a script for the specified build tool. + + Supported values are ``gmake`` for GNU Make and ``cmake`` for CMake. + Both can be specified together. If no build tool is specified, gmake is + assumed. The executable of gmake can be configured via environment + variable "MAKE". + + When using :vlopt:`--build` Verilator takes over the responsibility of + building the model library/executable. For this reason :option:`--make` + cannot be specified when using :vlopt:`--build`. + +.. option:: --compiler + + Enables workarounds for the specified C++ compiler (list below). + Currently this does not change any performance tuning options, but it may + in the future. + + clang + Tune for clang. This may reduce execution speed as it enables several + workarounds to avoid silly hard-coded limits in clang. This includes + breaking deep structures as for msvc as described below. + + gcc + Tune for GNU C++, although generated code should work on almost any + compliant C++ compiler. Currently the default. + + msvc + Tune for Microsoft Visual C++. This may reduce execution speed as it + enables several workarounds to avoid silly hard-coded limits in + MSVC++. This includes breaking deeply nested parenthesized + expressions into sub-expressions to avoid error C1009, and breaking + deep blocks into functions to avoid error C1061. + +.. option:: --converge-limit + + Rarely needed. Specifies the maximum number of runtime iterations + before creating a model failed to converge error. Defaults to 100. + +.. option:: --coverage + + Enables all forms of coverage, alias for :vlopt:`--coverage-line` + :vlopt:`--coverage-toggle` :vlopt:`--coverage-user`. + +.. option:: --coverage-line + + Enables basic block line coverage analysis. See :ref:`Line Coverage`. + +.. option:: --coverage-max-width + + Rarely needed. Specify the maximum bit width of a signal that is + subject to toggle coverage. Defaults to 256, as covering large vectors + may greatly slow coverage simulations. + +.. option:: --coverage-toggle + + Enables adding signal toggle coverage. See :ref:`Toggle Coverage`. + +.. option:: --coverage-underscore + + Enable coverage of signals that start with an underscore. Normally, + these signals are not covered. See also :vlopt:`--trace-underscore` + option. + +.. option:: --coverage-user + + Enables adding user inserted functional coverage. See :ref:`User Coverage`. + +.. option:: -D= + + Defines the given preprocessor symbol. Similar to :vlopt:`+define + <+define+>`, but does not allow multiple definitions with a single + option using plus signs. "+define" is fairly standard across Verilog + tools while "-D" is similar to :command:`gcc -D`. + +.. option:: --debug + + Run under debug. + + * Select the debug executable of Verilator (if available), this + generally is a less-optimized binary with symbols present (so GDB can be used on it). + * Enable debugging messages (equivalent to :vlopt:`--debugi 3 <--debugi>`). + * Enable internal assertions (equivalent to :vlopt:`--debug-check`). + * Enable intermediate form dump files (equivalent to :vlopt:`--dump-treei 3 + <--dump-treei>`). + * Leak to make node numbers unique (equivalent to :vlopt:`--debug-leak + <--no-debug-leak>`. + * Call abort() instead of exit() if there are any errors (so GDB can see + the program state). + +.. option:: --debug-check + + Rarely needed. Enable internal debugging assertion checks, without + changing debug verbosity. Enabled automatically with :vlopt:`--debug` + option. + +.. option:: --no-debug-leak + + In :vlopt:`--debug` mode, by default Verilator intentionally leaks + AstNode instances instead of freeing them, so that each node pointer is + unique in the resulting tree files and dot files. + + This option disables the leak. This may avoid out-of-memory errors when + Verilating large models in :vlopt:`--debug` mode. + + Outside of :vlopt:`--debug` mode, AstNode instances should never be + leaked and this option has no effect. + +.. option:: --debugi + + Rarely needed - for developer use. Set internal debugging level + globally to the specified debug level (1-10). Higher levels produce more + detailed messages. + +.. option:: --debugi- + + Rarely needed - for developer use. Set the specified Verilator source + file to the specified level (e.g. :vlopt:`--debugi-V3Width 9 + <--debugi>`). Higher levels produce more detailed messages. See + :vlopt:`--debug` for other implications of enabling debug. + +.. option:: --default-language + + Select the language to be used by default when first processing each + Verilog file. The language value must be "VAMS", "1364-1995", + "1364-2001", "1364-2001-noconfig", "1364-2005", "1800-2005", + "1800-2009", "1800-2012", "1800-2017", or "1800+VAMS". + + Any language associated with a particular file extension (see the + various +*\ ext+ options) will be used in preference to the + language specified by :vlopt:`--default-language`. + + The :vlopt:`--default-language` is only recommended for legacy code + using the same language in all source files, as the preferable option is + to edit the code to repair new keywords, or add appropriate + :code:`\`begin_keywords`. For legacy mixed language designs, the various + ``+ext+`` options should be used. + + If no language is specified, either by this option or ``+ext+`` + options, then the latest SystemVerilog language (IEEE 1800-2017) is + used. + +.. option:: +define+= + +.. option:: +define+=[+=][...] + + Defines the given preprocessor symbol, or multiple symbols if separated + by plus signs. Similar to :vlopt:`-D <-D>`; +define is fairly + standard across Verilog tools while :vlopt:`-D <-D>` is similar to + :command:`gcc -D`. + +.. option:: --dpi-hdr-only + + Only generate the DPI header file. This option has no effect on the + name or location of the emitted DPI header file, it is output in + :vlopt:`--Mdir` as it would be without this option. + +.. option:: --dump-defines + + With :vlopt:`-E`, suppress normal output, and instead print a list of + all defines existing at the end of pre-processing the input + files. Similar to GCC "-dM" option. This also gives you a way of finding + out what is predefined in Verilator using the command: + + .. code-block:: bash + + touch foo.v ; verilator -E --dump-defines foo.v + +.. option:: --dump-tree + + Rarely needed. Enable writing .tree debug files with dumping level 3, + which dumps the standard critical stages. For details on the format see + the Verilator Internals manual. :vlopt:`--dump-tree` is enabled + automatically with :vlopt:`--debug`, so :vlopt:`--debug --no-dump-tree + <--dump-tree>` may be useful if the dump files are large and not + desired. + +.. option:: --dump-treei + +.. option:: --dump-treei- + + Rarely needed - for developer use. Set internal tree dumping level + globally to a specific dumping level or set the specified Verilator + source file to the specified tree dumping level (e.g. + :vlopt:`--dump-treei-V3Order 9 <--dump-treei>`). Level 0 disables dumps + and is equivalent to :vlopt:`--no-dump-tree <--dump-tree>`. Level 9 + enables dumping of every stage. + +.. option:: --dump-tree-addrids + + Rarely needed - for developer use. Replace AST node addresses with + short identifiers in tree dumps to enhance readability. Each unique + pointer value is mapped to a unique identifier, but note that this is + not necessarily unique per node instance as an address might get reused + by a newly allocated node after a node with the same address has been + dumped then freed. + +.. option:: -E + + Preprocess the source code, but do not compile, similar to C++ + preprocessing using :command:`gcc -E`. Output is written to standard + out. Beware of enabling debugging messages, as they will also go to + standard out. + + See also :vlopt:`--dump-defines`, :vlopt:`-P`, and + :vlopt:`--pp-comments` options. + +.. option:: --error-limit + + After this number of errors are encountered during Verilator run, exit. + Warnings are not counted in this limit. Defaults to 50. + + Does not affect simulation runtime errors, for those see + :vlopt:`+verilator+error+limit+\`. + +.. option:: --exe + + Generate an executable. You will also need to pass additional .cpp + files on the command line that implement the main loop for your + simulation. + +.. option:: -F + + Read the specified file, and act as if all text inside it was specified + as command line arguments. Any relative paths are relative to the + directory containing the specified file. See also :vlopt:`-f` + option. Note :option:`-F` is fairly standard across Verilog tools. + +.. option:: -f + + Read the specified file, and act as if all text inside it was specified + as command line arguments. Any relative paths are relative to the + current directory. See also :vlopt:`-F` option. Note :option:`-f` is + fairly standard across Verilog tools. + + The file may contain :code:`//` comments which are ignored to the end of + the line. Any :code:`$VAR`, :code:`$(VAR)`, or :code:`${VAR}` will be + replaced with the specified environment variable. + +.. option:: -FI + + Force include of the specified C++ header file. All generated C++ files + will insert a #include of the specified file before any other + includes. The specified file might be used to contain define prototypes + of custom :code:`VL_VPRINTF` functions, and may need to include + :file:`verilatedos.h` as this file is included before any other standard + includes. + +.. option:: --flatten + + Force flattening of the design's hierarchy, with all modules, tasks and + functions inlined. Typically used with :vlopt:`--xml-only`. Note + flattening large designs may require significant CPU time, memory and + storage. + +.. option:: -G= + + Overwrites the given parameter of the toplevel module. The value is + limited to basic data literals: + + Verilog integer literals + The standard Verilog integer literals are supported, so values like + 32'h8, 2'b00, 4 etc. are allowed. Care must be taken that the single + quote (I') is properly escaped in an interactive shell, e.g., + as :code:`-GWIDTH=8'hx`. + + C integer literals + It is also possible to use C integer notation, including hexadecimal + (0x..), octal (0..) or binary (0b..) notation. + + Double literals + Double literals must be one of the following styles: + - contains a dot (.) (e.g. 1.23) + - contains an exponent (e/E) (e.g. 12e3) + - contains p/P for hexadecimal floating point in C99 (e.g. 0x123.ABCp1) + + Strings + Strings must be in double quotes (""). They must be escaped properly + on the command line, e.g. as :code:`-GSTR="\"My String\""` or + :code:`-GSTR='"My String"'`. + +.. option:: --gate-stmts + + Rarely needed. Set the maximum number of statements that may be present + in an equation for the gate substitution optimization to inline that + equation. + +.. option:: --gdb + + Run Verilator underneath an interactive GDB (or VERILATOR_GDB + environment variable value) session. See also :vlopt:`--gdbbt` option. + +.. option:: --gdbbt + + If :vlopt:`--debug` is specified, run Verilator underneath a GDB process + and print a backtrace on exit, then exit GDB immediately. Without + :vlopt:`--debug` or if GDB doesn't seem to work, this flag is ignored. + Intended for easy creation of backtraces by users; otherwise see the + :vlopt:`--gdb` option. + +.. option:: --generate-key + + Generate a true-random key suitable for use with :vlopt:`--protect-key`, + print it, and exit immediately. + +.. option:: --getenv + + If the variable is declared in the environment, print it and exit + immediately. Otherwise, if it's built into Verilator + (e.g. VERILATOR_ROOT), print that and exit immediately. Otherwise, print + a newline and exit immediately. This can be useful in makefiles. See + also :vlopt:`-V`, and the various :file:`*.mk` files. + +.. option:: --help + + Displays this message and program version and exits. + +.. option:: --hierarchical + + Enable hierarchical Verilation otherwise + :option:`/*verilator&32;hier_block*/` metacomment is ignored. See + :ref:`Hierarchical Verilation`. + +.. option:: -I + + See :vlopt:`-y`. + +.. option:: --if-depth + + Rarely needed. Set the depth at which the IFDEPTH warning will fire, + defaults to 0 which disables this warning. + +.. option:: +incdir+ + + See :vlopt:`-y`. + +.. option:: --inhibit-sim + + Rarely needed and deprecated. Create a :code:`inhibitSim(bool)` + function to enable and disable evaluation. This allows an upper level + testbench to disable modules that are not important in a given + simulation, without needing to recompile or change the SystemC modules + instantiated. + +.. option:: --inline-mult + + Tune the inlining of modules. The default value of 2000 specifies that up + to 2000 new operations may be added to the model by inlining, if more than + this number of operations would result, the module is not inlined. Larger + values, or a value < 1 will inline everything, will lead to longer compile + times, but potentially faster simulation speed. This setting is ignored + for very small modules; they will always be inlined, if allowed. + +.. option:: -j [] + + Specify the level of parallelism for :vlopt:`--build`. The must + be a positive integer specifying the maximum number of parallel build + jobs, or can be omitted. When is omitted, the build will not try + to limit the number of parallel build jobs but attempt to execute all + independent build steps in parallel. + +.. option:: -LDFLAGS + + Add specified C linker arguments to the generated makefiles. For multiple + flags either pass them as a single argument with space separators quoted + in the shell (``-LDFLAGS "-a -b"``), or use multiple -LDFLAGS arguments + (``-LDFLAGS -a -LDFLAGS -b``). + + When make is run on the generated makefile these will be passed to the + C++ linker (ld) **after** the primary file being linked. This flag is + called :vlopt:`-LDFLAGS` as that's the traditional name in simulators; + it's would have been better called LDLIBS as that's the Makefile + variable it controls. (In Make, LDFLAGS is before the first object, + LDLIBS after. -L libraries need to be in the Make variable LDLIBS, not + LDFLAGS.) + +.. option:: --l2-name + + Instead of using the module name when showing Verilog scope, use the + name provided. This allows simplifying some Verilator-embedded modeling + methodologies. Default is an l2-name matching the top module. The + default before Verilator 3.884 was ``--l2-name v``. + + For example, the program :code:`module t; initial $display("%m"); + endmodule` will show by default "t". With ``--l2-name v`` it will print + "v". + +.. option:: --language + + A synonym for :vlopt:`--default-language`, for compatibility with other + tools and earlier versions of Verilator. + +.. option:: +libext+[+][...] + + Specify the extensions that should be used for finding modules. If for + example module "my" is referenced, look in :file:`my.`. Note + "+libext+" is fairly standard across Verilog tools. Defaults to + ".v+.sv". + +.. option:: --lint-only + + Check the files for lint violations only, do not create any other + output. + + You may also want the :vlopt:`-Wall` option to enable messages that are + considered stylistic and not enabled by default. + + If the design is not to be completely Verilated see also the + :vlopt:`--bbox-sys` and :vlopt:`--bbox-unsup` options. + +.. option:: -MAKEFLAGS + + When using :vlopt:`--build`, add the specified argument to the invoked + make command line. For multiple flags either pass them as a single + argument with space separators quoted in the shell (e.g. ``-MAKEFLAGS + "-a -b"``), or use multiple -MAKEFLAGS arguments + (e.g. ``-MAKEFLAGS -l -MAKEFLAGS -k``). Use of this option should not be + required for simple builds using the host toolchain. + +.. option:: --max-num-width + + Set the maximum number literal width (e.g. in 1024'd22 this it the + 1024). Defaults to 64K. + +.. option:: --MMD =item --no-MMD + + Enable/disable creation of .d dependency files, used for make dependency + detection, similar to gcc -MMD option. By default this option is + enabled for :vlopt:`--cc` or :vlopt:`--sc` modes. + +.. option:: --MP + + When creating .d dependency files with :vlopt:`--MMD` option, make phony + targets. Similar to :command:`gcc -MP` option. + +.. option:: --Mdir + + Specifies the name of the Make object directory. All generated files + will be placed in this directory. If not specified, "obj_dir" is used. + The directory is created if it does not exist and the parent directories + exist; otherwise manually create the Mdir before calling Verilator. + +.. option:: --mod-prefix + + Specifies the name to prepend to all lower level classes. Defaults to + the same as :vlopt:`--prefix`. + +.. option:: --no-clk + + Prevent the specified signal from being marked as clock. See + :vlopt:`--clk`. + +.. option:: --no-decoration + + When creating output Verilated code, minimize comments, white space, + symbol names and other decorative items, at the cost of greatly reduced + readability. This may assist C++ compile times. This will not typically + change the ultimate model's performance, but may in some cases. + +.. option:: --no-pins64 + + Backward compatible alias for :vlopt:`--pins-bv 33 <--pins-bv>`. + +.. option:: --no-relative-cfuncs + + Deprecated. + +.. option:: --no-skip-identical =item --skip-identical + + Rarely needed. Disables or enables skipping execution of Verilator if + all source files are identical, and all output files exist with newer + dates. By default this option is enabled for :vlopt:`--cc` or + :vlopt:`--sc` modes only. + +.. option:: +notimingchecks + + Ignored for compatibility with other simulators. + +.. option:: -O0 + + Disables optimization of the model. + +.. option:: -O3 + + Enables slow optimizations for the code Verilator itself generates (as + opposed to :vlopt:`-CFLAGS -O3 <-CFLAGS>` which effects the C compiler's + optimization. :vlopt:`-O3` may improve simulation performance at the + cost of compile time. This currently sets :vlopt:`--inline-mult -1 + <--inline-mult>`. + +.. option:: -O + + Rarely needed. Enables or disables a specific optimizations, with the + optimization selected based on the letter passed. A lowercase letter + disables an optimization, an upper case letter enables it. This is + intended for debugging use only; see the source code for + version-dependent mappings of optimizations to -O letters. + +.. option:: -o + + Specify the name for the final executable built if using :vlopt:`--exe`. + Defaults to the :vlopt:`--prefix` if not specified. + +.. option:: --no-order-clock-delay + + Rarely needed. Disables a bug fix for ordering of clock enables with + delayed assignments. This option should only be used when suggested by + the developers. + +.. option:: --output-split + + Enables splitting the output .cpp files into multiple outputs. When a + C++ file exceeds the specified number of operations, a new file will be + created at the next function boundary. In addition, if the total output + code size exceeds the specified value, VM_PARALLEL_BUILDS will be set to + 1 by default in the generated make files, making parallel compilation + possible. Using :vlopt:`--output-split` should have only a trivial + impact on model performance. But can greatly improve C++ compilation + speed. The use of "ccache" (set for you if present at configure time) is + also more effective with this option. + + This option is on by default with a value of 20000. To disable, pass with a + value of 0. + +.. option:: --output-split-cfuncs + + Enables splitting functions in the output .cpp files into multiple + functions. When a generated function exceeds the specified number of + operations, a new function will be created. With + :vlopt:`--output-split`, this will enable the C++ compiler to compile + faster, at a small loss in performance that gets worse with decreasing + split values. Note that this option is stronger than + :vlopt:`--output-split` in the sense that :vlopt:`--output-split` will + not split inside a function. + + Defaults to the value of :vlopt:`--output-split`, unless explicitly + specified. + +.. option:: --output-split-ctrace + + Similar to :vlopt:`--output-split-cfuncs`, enables splitting trace + functions in the output .cpp files into multiple functions. + + Defaults to the value of :vlopt:`--output-split`, unless explicitly + specified. + +.. option:: -P + + With :vlopt:`-E`, disable generation of :code:`&96;line` markers and + blank lines, similar to :command:`gcc -P`. + +.. option:: --pins64 + + Backward compatible alias for :vlopt:`--pins-bv 65 <--pins-bv>`. Note + that's a 65, not a 64. + +.. option:: --pins-bv + + Specifies SystemC inputs/outputs of greater than or equal to + bits wide should use sc_bv's instead of uint32/vluint64_t's. The + default is "--pins-bv 65", and the value must be less than or equal + to 65. Versions before Verilator 3.671 defaulted to "--pins-bv 33". + The more sc_bv is used, the worse for performance. Use the + :option:`/*verilator&32;sc_bv*/` metacomment to select specific ports to + be sc_bv. + +.. option:: --pins-sc-uint + + Specifies SystemC inputs/outputs of greater than 2 bits wide should use + sc_uint between 2 and 64. When combined with the + :vlopt:`--pins-sc-biguint` combination, it results in sc_uint being used + between 2 and 64 and sc_biguint being used between 65 and 512. + +.. option:: --pins-sc-biguint + + Specifies SystemC inputs/outputs of greater than 65 bits wide should use + sc_biguint between 65 and 512, and sc_bv from 513 upwards. When + combined with the :vlopt:`--pins-sc-uint` combination, it results in + sc_uint being used between 2 and 64 and sc_biguint being used between 65 + and 512. + +.. option:: --pins-uint8 + + Specifies SystemC inputs/outputs that are smaller than the + :vlopt:`--pins-bv` setting and 8 bits or less should use uint8_t instead + of uint32_t. Likewise pins of width 9-16 will use uint16_t instead of + uint32_t. + +.. option:: --pipe-filter + + Rarely needed. Verilator will spawn the specified command as a + subprocess pipe, to allow the command to perform custom edits on the + Verilog code before it reaches Verilator. + + Before reading each Verilog file, Verilator will pass the file name to + the subprocess' stdin with :code:`read ""`. The filter may + then read the file and perform any filtering it desires, and feeds the + new file contents back to Verilator on stdout by first emitting a line + defining the length in bytes of the filtered output + :code:`Content-Length: `, followed by the new filtered + contents. Output to stderr from the filter feeds through to Verilator's + stdout and if the filter exits with non-zero status Verilator + terminates. See the file:`t/t_pipe_filter` test for an example. + + To debug the output of the filter, try using the :vlopt:`-E` option to + see preprocessed output. + +.. option:: --pp-comments + + With :vlopt:`-E`, show comments in preprocessor output. + +.. option:: --prefix + + Specifies the name of the top level class and makefile. Defaults to V + prepended to the name of the :vlopt:`--top` option, or V prepended to + the first Verilog filename passed on the command line. + +.. option:: --prof-cfuncs + + Modify the created C++ functions to support profiling. The functions + will be minimized to contain one "basic" statement, generally a single + always block or wire statement. (Note this will slow down the + executable by ~5%.) Furthermore, the function name will be suffixed + with the basename of the Verilog module and line number the statement + came from. This allows gprof or oprofile reports to be correlated with + the original Verilog source statements. See :ref:`Profiling`. + +.. option:: --prof-threads + + Enable gantt chart data collection for threaded builds. See :ref:`Thread + Profiling`. + +.. option:: --protect-key + + Specifies the private key for :vlopt:`--protect-ids`. For best security + this key should be 16 or more random bytes, a reasonable secure choice + is the output of :command:`verilator --generate-key` . Typically, a key + would be created by the user once for a given protected design library, + then every Verilator run for subsequent versions of that library would + be passed the same :vlopt:`--protect-key`. Thus, if the input Verilog is + similar between library versions (Verilator runs), the Verilated code + will likewise be mostly similar. + + If :vlopt:`--protect-key` is not specified and a key is needed, + Verilator will generate a new key for every Verilator run. As the key is + not saved, this is best for security, but means every Verilator run will + give vastly different output even for identical input, perhaps harming + compile times (and certainly thrashing any "ccache"). + +.. option:: --protect-ids + + Hash any private identifiers (variable, module, and assertion block + names that are not on the top level) into hashed random-looking + identifiers, resulting after compilation in protected library binaries + that expose less design information. This hashing uses the provided or + default :vlopt:`--protect-key`, see important details there. + + Verilator will also create a :file:`__idmap.xml` file which + contains the mapping from the hashed identifiers back to the original + identifiers. This idmap file is to be kept private, and is to assist + mapping any simulation runtime design assertions, coverage, or trace + information, which will report the hashed identifiers, back to the + original design's identifier names. + + Using DPI imports/exports is allowed and generally relatively safe in + terms of information disclosed, which is limited to the DPI function + prototyptes. Use of the VPI is not recommended as many design details + may be exposed, and an INSECURE warning will be issued. + +.. option:: --protect-lib + + Produces C++, Verilog wrappers and a Makefile which can in turn produce + a DPI library which can be used by Verilator or other simulators along + with the corresponding Verilog wrapper. The Makefile will build both a + static and dynamic version of the library named :file:`lib.a` and + :file:`lib.so` respectively. This is done because some simulators + require a dynamic library, but the static library is arguably easier to + use if possible. :vlopt:`--protect-lib` implies :vlopt:`--protect-ids`. + + This allows for the secure delivery of sensitive IP without the need for + encrypted RTL (i.e. IEEE P1735). See :file:`examples/make_protect_lib` + in the distribution for a demonstration of how to build and use the DPI + library. + + When using :vlopt:`--protect-lib` it is advised to also use + :vlopt:`--timescale-override /1fs <--timescale-override>` to ensure the + model has a time resolution that is always compatible with the time + precision of the upper instantiating module. + +.. option:: --private + + Opposite of :vlopt:`--public`. Is the default; this option exists for + backwards compatibility. + +.. option:: --public + + This is only for historical debug use. Using it may result in + mis-simulation of generated clocks. + + Declares all signals and modules public. This will turn off signal + optimizations as if all signals had a :option:`/*verilator&32;public*/` + metacomments and inlining. This will also turn off inlining as if all + modules had a :option:`/*verilator&32;public_module*/`, unless the + module specifically enabled it with + :option:`/*verilator&32;inline_module*/`. + +.. option:: --public-flat-rw + + Declares all variables, ports and wires public as if they had + :code:`/*verilator public_flat_rw @ + ()*/` metacomments. This will make them + VPI accessible by their flat name, but not turn off module inlining. + This is particularly useful in combination with :vlopt:`--vpi`. This may + also in some rare cases result in mis-simulation of generated clocks. + Instead of this global option, marking only those signals that need + public_flat_rw is typically significantly better performing. + +.. option:: -pvalue+= + + Overwrites the given parameter(s) of the toplevel module. See :vlopt:`-G + <-G>` for a detailed description. + +.. option:: --quiet-exit + + When exiting due to an error, do not display the "Exiting due to Errors" + nor "Command Failed" messages. + +.. option:: --relative-includes + + When a file references an include file, resolve the filename relative to + the path of the referencing file, instead of relative to the current + directory. + +.. option:: --report-unoptflat + + Extra diagnostics for UNOPTFLAT warnings. This includes for each loop, + the 10 widest variables in the loop, and the 10 most fanned out + variables in the loop. These are candidates for splitting into multiple + variables to break the loop. + + In addition produces a GraphViz DOT file of the entire strongly + connected components within the source associated with each loop. This + is produced irrespective of whether :vlopt:`--dump-tree` is set. Such + graphs may help in analyzing the problem, but can be very large indeed. + + Various commands exist for viewing and manipulating DOT files. For + example the "dot" command can be used to convert a DOT file to a PDF for + printing. For example: + + .. code-block:: bash + + dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot + + will generate a PDF :file:`Vt_unoptflat_simple_2_35_unoptflat.dot.pdf` + from the DOT file. + + As an alternative, the :command:`xdot` command can be used to view DOT + files interactively: + + .. code-block:: bash + + xdot Vt_unoptflat_simple_2_35_unoptflat.dot + +.. option:: --rr + + Run Verilator and record with the :command:`rr` command. See: + rr-project.org. + +.. option:: --savable + + Enable including save and restore functions in the generated model. See + :ref:`Save/Restore`. + +.. option:: --sc + + Specifies SystemC output mode; see also :vlopt:`--cc` option. + +.. option:: --stats + + Creates a dump file with statistics on the design in + :file:`__stats.txt`. + +.. option:: --stats-vars + + Creates more detailed statistics, including a list of all the variables + by size (plain :vlopt:`--stats` just gives a count). See + :vlopt:`--stats`, which is implied by this. + +.. option:: --structs-packed + + Converts all unpacked structures to packed structures and issues a + UNPACKED warning. Currently this is the default and + :vlopt:`--no-structs-packed <--structs-packed>` will not work. + Specifying this option allows for forward compatibility when a future + version of Verilator no longer always packs unpacked structures. + +.. option:: -sv + + Specifies SystemVerilog language features should be enabled; equivalent + to :vlopt:`--language 1800-2017 <--language>`. This option is selected + by default, it exists for compatibility with other simulators. + +.. option:: +systemverilogext+ + + A synonym for :vlopt:`+1800-2017ext+\`. + +.. option:: --threads + +.. option:: --no-threads + + With "--threads 0" or "--no-threads", the default, the generated model + is not thread safe. With "--threads 1", the generated model is single + threaded but may run in a multithreaded environment. With "--threads N", + where N >= 2, the model is generated to run multithreaded on up to N + threads. See :ref:`Multithreading`. + +.. option:: --threads-dpi all + +.. option:: --threads-dpi none + +.. option:: --threads-dpi pure + + When using :vlopt:`--threads`, controls which DPI imported tasks and + functions are considered thread safe. + + With "--threads-dpi all", + Enable Verilator to assume all DPI imports are threadsafe, and to use + thread-local storage for communication with DPI, potentially improving + performance. Any DPI libraries need appropriate mutexes to avoid + undefined behavior. + + With "--threads-dpi none", + Verilator assume DPI imports are not thread safe, and Verilator will + serialize calls to DPI imports by default, potentially harming + performance. + + With "--threads-dpi pure", the default, + Verilator assumes DPI pure imports are threadsafe, but non-pure DPI + imports are not. + +.. option:: --threads-max-mtasks + + Rarely needed. When using :vlopt:`--threads`, specify the number of + mtasks the model is to be partitioned into. If unspecified, Verilator + approximates a good value. + +.. option:: --timescale / + + Sets default timescale, timeunit and timeprecision for when "`timescale" + does not occur before a given module. Default is "1ps/1ps" (to match + SystemC). This is overridden by :vlopt:`--timescale-override`. + +.. option:: --timescale-override / + +.. option:: --timescale-override / + + Overrides all "\`timescale"s in sources. The timeunit may be left empty + to specify only to override the timeprecision, e.g. "/1fs". + + The time precision must be consistent with SystemC's + "sc_set_time_resolution()", or the C++ code instantiating the Verilated + module. As "1fs" is the finest time precision it may be desirable to + always use a precision of "1fs". + +.. option:: --top + +.. option:: --top-module + + When the input Verilog contains more than one top level module, + specifies the name of the Verilog module to become the top level module, + and sets the default for :vlopt:`--prefix` if not explicitly specified. + This is not needed with standard designs with only one top. See also + :option:`MULTITOP` warning. + +.. option:: --trace + + Adds waveform tracing code to the model using VCD format. This overrides + :vlopt:`--trace-fst`. + + Verilator will generate additional :file:`__Trace*.cpp` files + that will need to be compiled. In addition :file:`verilated_vcd_sc.cpp` + (for SystemC traces) or :file:`verilated_vcd_c.cpp` (for both) must be + compiled and linked in. If using the Verilator generated Makefiles, + these files will be added to the source file lists for you. If you are + not using the Verilator Makefiles, you will need to add these to your + Makefile manually. + + Having tracing compiled in may result in some small performance losses, + even when tracing is not turned on during model execution. + + See also :vlopt:`--trace-threads` option. + +.. option:: --trace-coverage + + With :vlopt:`--trace` and ``--coverage-*``, enable tracing to include a + traced signal for every :vlopt:`--coverage-line` or + :vlopt:`--coverage-user`\ -inserted coverage point, to assist in + debugging coverage items. Note :vlopt:`--coverage-toggle` does not get + additional signals added, as the original signals being toggle-analyzed + are already visible. + + The added signal will be a 32-bit value which will increment on each + coverage occurrence. Due to this, this option may greatly increase trace + file sizes and reduce simulation speed. + +.. option:: --trace-depth + + Specify the number of levels deep to enable tracing, for example + :vlopt:`--trace-depth 1 <--trace-depth>` to only see the top level's + signals. Defaults to the entire model. Using a small number will + decrease visibility, but greatly improve simulation performance and + trace file size. + +.. option:: --trace-fst + + Enable FST waveform tracing in the model. This overrides + :vlopt:`--trace`. See also :vlopt:`--trace-threads` option. + +.. option:: --trace-max-array *depth* + + Rarely needed. Specify the maximum array depth of a signal that may be + traced. Defaults to 32, as tracing large arrays may greatly slow traced + simulations. + +.. option:: --trace-max-width *width* + + Rarely needed. Specify the maximum bit width of a signal that may be + traced. Defaults to 256, as tracing large vectors may greatly slow + traced simulations. + +.. option:: --no-trace-params + + Disable tracing of parameters. + +.. option:: --trace-structs + + Enable tracing to show the name of packed structure, union, and packed + array fields, rather than a single combined packed bus. Due to VCD file + format constraints this may result in significantly slower trace times + and larger trace files. + +.. option:: --trace-threads *threads* + + Enable waveform tracing using separate threads. This is typically faster + in simulation runtime but uses more total compute. This option is + independent of, and works with, both :vlopt:`--trace` and + :vlopt:`--trace-fst`. Different trace formats can take advantage of + more trace threads to varying degrees. Currently VCD tracing can utilize + at most "--trace-threads 1", and FST tracing can utilize at most + "--trace-threads 2". This overrides :vlopt:`--no-threads` . + +.. option:: --trace-underscore + + Enable tracing of signals that start with an underscore. Normally, these + signals are not output during tracing. See also + :vlopt:`--coverage-underscore` option. + +.. option:: -U + + Undefines the given preprocessor symbol. + +.. option:: --unroll-count + + Rarely needed. Specifies the maximum number of loop iterations that may be + unrolled. See also :option:`BLKLOOPINIT` warning. + +.. option:: --unroll-stmts *statements* + + Rarely needed. Specifies the maximum number of statements in a loop for + that loop to be unrolled. See also :option:`BLKLOOPINIT` warning. + +.. option:: --unused-regexp *regexp* + + Rarely needed. Specifies a simple regexp with \* and ? that if a signal + name matches will suppress the UNUSED warning. Defaults to + "\*unused\*". Setting it to "" disables matching. + +.. option:: -V + + Shows the verbose version, including configuration information compiled + into Verilator. (Similar to :command:`perl -V`.) See also + :vlopt:`--getenv` option. + +.. option:: -v *filename* + + Read the filename as a Verilog library. Any modules in the file may be + used to resolve instances in the top level module, else ignored. Note + "-v" is fairly standard across Verilog tools. + +.. option:: --no-verilate + + When using :vlopt:`--build`, disable generation of C++/SystemC code, and + execute only the build. This can be useful for rebuilding Verilated code + produced by a previous invocation of Verilator. + +.. option:: +verilog1995ext+ + + Synonym for :vlopt:`+1364-1995ext+\`. + +.. option:: +verilog2001ext+ + + Synonym for :vlopt:`+1364-2001ext+\`. + +.. option:: --version + + Displays program version and exits. + +.. option:: --vpi + + Enable use of VPI and linking against the :file:`verilated_vpi.cpp` files. + +.. option:: --waiver-output *filename* + + Generate a waiver file which contains all waiver statements to suppress + the warnings emitted during this Verilator run. This in particular is + useful as a starting point for solving linter warnings or suppressing + them systematically. + + The generated file is in the Verilator Configuration format, see + :ref:`Configuration Files`, and can directly be consumed by + Verilator. The standard file extension is ".vlt". + +.. option:: -Wall + + Enable all code style warnings, including code style warnings that are + normally disabled by default. Equivalent to :vlopt:`-Wwarn-lint` + :vlopt:`-Wwarn-style`. Excludes some specialty warnings, + i.e. IMPERFECTSCH. + +.. option:: -Werror- + + Promote the specified warning message into an error message. This is + generally to discourage users from violating important site-wide rules, + for example "-Werror-NOUNOPTFLAT". + +.. option:: -Wfuture- + + Rarely needed. Suppress unknown Verilator comments or warning messages + with the given message code. This is used to allow code written with + pragmas for a later version of Verilator to run under a older version; + add "-Wfuture-" arguments for each message code or comment that the new + version supports which the older version does not support. + +.. option:: -Wno- + + Disable the specified warning/error message. This will override any + lint_on directives in the source, i.e. the warning will still not be + printed. + +.. option:: -Wno-context + + Disable showing the suspected context of the warning message by quoting + the source text at the suspected location. This can be used to appease + tools which process the warning messages but may get confused by lines + from the original source. + +.. option:: -Wno-fatal + + When warnings are detected, print them, but do not terminate Verilator. + + Having warning messages in builds can be sloppy. It is recommended you + cleanup your code, use inline lint_off, or use ``-Wno-...`` options + rather than using this option. + +.. option:: -Wno-lint + + Disable all lint related warning messages, and all style warnings. This is + equivalent to ``-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE + -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASTCONST -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS + -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY + -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED + -Wno-WIDTH`` plus the list shown for Wno-style. + + It is strongly recommended you cleanup your code rather than using this + option, it is only intended to be use when running test-cases of code + received from third parties. + +.. option:: -Wno-style + + Disable all code style related warning messages (note by default they are + already disabled). This is equivalent to ``-Wno-DECLFILENAME -Wno-DEFPARAM + -Wno-EOFNEWLINE -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY + -Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED + -Wno-VARHIDDEN``. + +.. option:: -Wpedantic + + Warn on any construct demanded by IEEE, and disable all Verilator + extensions that may interfere with IEEE compliance to the standard + defined with :vlopt:`--default-language` (etc). Similar to + :command:`gcc -Wpedantic`. Rarely used, and intended only for strict + compliance tests. + +.. option:: -Wwarn- + + Enables the specified warning message. + +.. option:: -Wwarn-lint + + Enable all lint related warning messages (note by default they are already + enabled), but do not affect style messages. This is equivalent to + ``-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE + -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASTCONST -Wwarn-CASEWITHX -Wwarn-CMPCONST + -Wwarn-COLONPLUS -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN + -Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH``. + +.. option:: -Wwarn-style + + Enable all code style related warning messages. This is equivalent to + ``-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-EOFNEWLINE + -Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN + -Wwarn-UNUSED -Wwarn-VARHIDDEN``. + +.. option:: --x-assign 0 + +.. option:: --x-assign 1 + +.. option:: --x-assign fast (default) + +.. option:: --x-assign unique + + Controls the two-state value that is substituted when an explicit X + value is encountered in the source. "--x-assign fast", the default, + converts all Xs to whatever is best for performance. "--x-assign 0" + converts all Xs to 0s, and is also fast. "--x-assign 1" converts all Xs + to 1s, this is nearly as fast as 0, but more likely to find reset bugs + as active high logic will fire. Using "--x-assign unique" will result in + all explicit Xs being replaced by a constant value determined at + runtime. The value is determined by calling a function at initialization + time. This enables randomization of Xs with different seeds on different + executions. This method is the slowest, but safest for finding reset + bugs. + + If using "--x-assign unique", you may want to seed your random number + generator such that each regression run gets a different randomization + sequence. The simplest is to use the :vlopt:`+verilator+seed+\` + runtime option. Alternatively use the system's :code:`srand48()` or for + Windows :code:`srand()` function to do this. You'll probably also want + to print any seeds selected, and code to enable rerunning with that same + seed so you can reproduce bugs. + + .. note:: + + This option applies only to values which are explicitly written as X + in the Verilog source code. Initial values of clocks are set to 0 + unless `--x-initial-edge` is specified. Initial values of all other + state holding variables are controlled with `--x-initial`. + +.. option:: --x-initial 0 + +.. option:: --x-initial fast + +.. option:: --x-initial unique (default) + + Controls the two-state value that is used to initialize variables that + are not otherwise initialized. + + "--x-initial 0", + initializes all otherwise uninitialized variables to zero. + + "--x-initial unique", the default, + initializes variables using a function, which determines the value to + use each initialization. This gives greatest flexibility and allows + finding reset bugs. See :ref:`Unknown states`. + + "--x-initial fast", + is best for performance, and initializes all variables to a state + Verilator determines is optimal. This may allow further code + optimizations, but will likely hide any code bugs relating to missing + resets. + + .. note:: + + This option applies only to initial values of variables. Initial + values of clocks are set to 0 unless :vlopt:`--x-initial-edge` is + specified. + +.. option:: --x-initial-edge + + Enables emulation of event driven simulators which generally trigger an + edge on a transition from X to 1 (posedge) or X to 0 (negedge). Thus the + following code, where :code:`rst_n` is uninitialized would set + :code:`res_n` to :code:`1'b1` when :code:`rst_n` is first set to zero: + + .. code-block:: sv + + reg res_n = 1'b0; + + always @(negedge rst_n) begin + if (rst_n == 1'b0) begin + res_n <= 1'b1; + end + end + + In Verilator, by default, uninitialized clocks are given a value of + zero, so the above :code:`always` block would not trigger. + + While it is not good practice, there are some designs that rely on X + rarr 0 triggering a negedge, particularly in reset sequences. Using + :vlopt:`--x-initial-edge` with Verilator will replicate this + behavior. It will also ensure that X rarr 1 triggers a posedge. + + .. note:: + + Using this option can affect convergence, andit may be necessary to + use :vlopt:`--converge-limit` to increase the number of convergence + iterations. This may be another indication of problems with the + modeled design that should be addressed. + +.. option:: --xml-only + + Create XML output only, do not create any other output. + + The XML format is intended to be used to leverage Verilator's parser and + elaboration to feed to other downstream tools. Be aware that the XML + format is still evolving; there will be some changes in future versions. + +.. option:: --xml-output + + Filename for XML output file. Using this option automatically sets + :vlopt:`--xml-only`. + +.. option:: -y + + Add the directory to the list of directories that should be searched for + include files or libraries. The three flags :vlopt:`-y`, + :vlopt:`+incdir+\` and :vlopt:`-I\` have similar effect; + :vlopt:`+incdir+\` and :vlopt:`-y` are fairly standard across + Verilog tools while :vlopt:`-I\` is used by many C++ compilers. + + Verilator defaults to the current directory "-y ." and any specified + :vlopt:`--Mdir`, though these default paths are used after any user + specified directories. This allows '-y "$(pwd)"' to be used if absolute + filenames are desired for error messages instead of relative filenames. + + +.. _Configuration Files: + +Configuration Files +=================== + +In addition to the command line, warnings and other features for the +:command:`verilator` command may be controlled with configuration files, +typically named with the .vlt extension (what makes it a configuration file +is the :option:`\`verilator_config` directive). An example: + +.. code-block:: sv + + `verilator_config + lint_off -rule WIDTH + lint_off -rule CASEX -file "silly_vendor_code.v" + +This disables WIDTH warnings globally, and CASEX for a specific file. + +Configuration files are fed through the normal Verilog preprocessor prior +to parsing, so "\`ifdef", "\`define", and comments may be used as if the +configuration file was normal Verilog code. + +Note that file or line-specific configuration only applies to files read +after the configuration file. It is therefore recommended to pass the +configuration file to Verilator as the first file. + +The grammar of configuration commands is as follows: + +.. option:: `verilator_config + + Take remaining text and treat it as Verilator configuration commands. + +.. option:: coverage_on [-file "" [-lines [ - ]]] + +.. option:: coverage_off [-file "" [-lines [ - ]]] + + Enable/disable coverage for the specified filename (or wildcard with + '\*' or '?', or all files if omitted) and range of line numbers (or all + lines if omitted). Often used to ignore an entire module for coverage + analysis purposes. + +.. option:: clock_enable -module "" -var "" + + Indicate the signal is used to gate a clock, and the user takes + responsibility for insuring there are no races related to it. + + Same as :option:`/*verilator&32;clock_enable*/` metacomment. + +.. option:: clocker -module "" [-task ""] -var "" + +.. option:: clocker -module "" [-function ""] -var "" + +.. option:: no_clocker -module "" [-task ""] -var "" + +.. option:: no_clocker -module "" [-function ""] -var "" + + Indicate the signal is used as clock or not. This information is used by + Verilator to mark the signal as clocker and propagate the clocker + attribute automatically to derived signals. See :vlopt:`--clk`. + + Same as :option:`/*verilator&32;clocker*/` metacomment. + +.. option:: coverage_block_off -module "" -block "" + +.. option:: coverage_block_off -file "" -line + + Specifies the entire begin/end block should be ignored for coverage + analysis purposes. Can either be specified as a named block or as a + filename and line number. + + Same as :option:`/*verilator&32;coverage_block_off*/` metacomment. + +.. option:: full_case -file "" -lines + +.. option:: parallel_case -file "" -lines + + Same as :code:`//synopsys full_case` and :code:`//synopsys + parallel_case`. When these synthesis directives are discovered, + Verilator will either formally prove the directive to be true, or + failing that, will insert the appropriate code to detect failing cases + at simulation runtime and print an "Assertion failed" error message. + +.. option:: hier_block -module "" + + Specifies that the module is a unit of hierarchical Verilation. Note + that the setting is ignored unless the :vlopt:`--hierarchical` option is + specified. See :ref:`Hierarchical Verilation`. + +.. option:: inline -module "" + + Specifies the module may be inlined into any modules that use this + module. Same as :option:`/*verilator&32;inline_module*/` metacomment. + +.. option:: isolate_assignments -module "" [-task ""] -var "" + +.. option:: isolate_assignments -module "" [-function ""] -var "" + +.. option:: isolate_assignments -module "" -function "" + + Used to indicate the assignments to this signal in any blocks should be + isolated into new blocks. When there is a large combinatorial block + that is resulting in an UNOPTFLAT warning, attaching this to the signal + causing a false loop may clear up the problem. + + Same as :option:`/*verilator&32;isolate_assignments*/` metacomment. + +.. option:: no_inline -module "" + + Specifies the module should not be inlined into any modules that use + this module. Same as :option:`/*verilator&32;no_inline_module*/` + metacomment. + +.. option:: no_inline [-module ""] -task "" + +.. option:: no_inline [-module ""] -function "" + + Specify the function or task should not be inlined into where it is + used. This may reduce the size of the final executable when a task is + used a very large number of times. For this flag to work, the task and + tasks below it must be pure; they cannot reference any variables outside + the task itself. + + Same as :option:`/*verilator&32;no_inline_task*/` metacomment. + +.. option:: lint_on [-rule ] [-file "" [-lines [ - ]]] + +.. option:: lint_off [-rule ] [-file "" [-lines [ - ]]] + +.. option:: lint_off [-rule ] [-file ""] [-match ""] + + Enable/disables the specified lint warning, in the specified filename + (or wildcard with '\*' or '?', or all files if omitted) and range of + line numbers (or all lines if omitted). + + With lint_off using "\*" will override any lint_on directives in the + source, i.e. the warning will still not be printed. + + If the -rule is omitted, all lint warnings (see list in + :vlopt:`-Wno-lint`) are enabled/disabled. This will override all later + lint warning enables for the specified region. + + If -match is set the linter warnings are matched against this (wildcard) + string and are waived in case they match and iff rule and file (with + wildcard) also match. + + In previous versions -rule was named -msg. The latter is deprecated, but + still works with a deprecation info, it may be removed in future + versions. + +.. option:: public [-module ""] [-task/-function ""] -var "" + +.. option:: public_flat [-module ""] [-task/-function ""] -var "" + +.. option:: public_flat_rd [-module ""] [-task/-function ""] -var "" + +.. option:: public_flat_rw [-module ""] [-task/-function ""] -var "" "@(edge)" + + Sets the variable to be public. Same as + :option:`/*verilator&32;public*/` or + :option:`/*verilator&32;public_flat*/`, etc, metacomments. See + e.g. :ref:`VPI Example`. + +.. option:: sc_bv -module "" [-task ""] -var "" + +.. option:: sc_bv -module "" [-function ""] -var "" + + Sets the port to be of :code:`sc_bv<{width}>` type, instead of bool, + vluint32_t or vluint64_t. Same as :option:`/*verilator&32;sc_bv*/` + metacomment. + +.. option:: sformat [-module ""] [-task ""] -var "" + +.. option:: sformat [-module ""] [-function ""] -var "" + + Must be applied to the final argument of type :code:`input string` of a + function or task to indicate the function or task should pass all + remaining arguments through $sformatf. This allows creation of DPI + functions with $display like behavior. See the + :file:`test_regress/t/t_dpi_display.v` file for an example. + + Same as :option:`/*verilator&32;sformat*/` metacomment. + +.. option:: split_var [-module ""] [-task ""] -var "" + +.. option:: split_var [-module ""] [-function ""] -var "" + + Break the variable into multiple pieces typically to resolve UNOPTFLAT + performance issues. Typically the variables to attach this to are + recommended by Verilator itself, see :option:`UNOPTFLAT`. + + Same as :option:`/*verilator&32;split_var*/` metacomment. + +.. option:: tracing_on [-file "" [-lines [ - ]]] + +.. option:: tracing_off [-file "" [-lines [ - ]]] + + Enable/disable waveform tracing for all future signals declared in the + specified filename (or wildcard with '\*' or '?', or all files if + omitted) and range of line numbers (or all lines if omitted). + + For tracing_off, instances below any module in the files/ranges + specified will also not be traced. + diff --git a/docs/guide/exe_verilator_coverage.rst b/docs/guide/exe_verilator_coverage.rst new file mode 100644 index 000000000..41eba66cf --- /dev/null +++ b/docs/guide/exe_verilator_coverage.rst @@ -0,0 +1,114 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +verilator_coverage +================== + +Verilator_coverage processes Verilated model-generated coverage reports. + +With --annotate, it reads the specified coverage data file and generates +annotated source code with coverage metrics annotated. If multiple +coverage points exist on the same source code line, additional lines will +be inserted to report the additional points. + +Additional Verilog-XL-style standard arguments specify the search paths +necessary to find the source code that the coverage analysis was performed +on. + +To filter those items to be included in coverage, you may read +logs/coverage.dat into an editor and do a M-x keep-lines to include only +those statistics of interest and save to a new .dat file. + +For Verilog conditions that should never occur, either add a $stop +statement to the appropriate statement block, or see +:option:`/*verilator&32;coverage_off*/`. This will remove the coverage +points after the model is re-Verilated. + +For an overview of use of verilator_coverage, see :ref:`Coverage Analysis`. + + +verilator_coverage Example Usage +-------------------------------- + +.. + + verilator_coverage --help + verilator_coverage --version + + verilator_coverage --annotate + + verilator_coverage -write merged.dat -read ... + + verilator_coverage -write-info merged.info -read ... + + +verilator_coverage Arguments +---------------------------- + +.. program:: verilator_coverage + +.. option:: + +Specifies the input coverage data file. Multiple filenames may be provided +to read multiple inputs. If no data file is specified, by default +"coverage.dat" will be read. + +.. option:: --annotate + +Specifies the directory name that source files with annotated coverage data +should be written to. + +.. option:: --annotate-all + +Specifies all files should be shown. By default, only those source files +which have low coverage are written to the output directory. + +.. option:: --annotate-min + +Specifies if the coverage point does not include the count number of +coverage hits, then the coverage point will be considered above the +threashold, and the coverage report will put a "%" to indicate the coverage +is not sufficient. Defaults to 10. + +.. option:: --help + +Displays a help summary, the program version, and exits. + +.. option:: --rank + +Prints an experimental report listing the relative importance of each test +in covering all of the coverage points. The report shows "Covered" which +indicates the number of points that test covers; a test is considered to +cover a point if it has a bucket count of at least 1. The "rank" column has +a higher number t indicate the test is more important, and rank 0 means the +test does not need to be run to cover the points. "RankPts" indicates the +number of coverage points this test will contribute to overall coverage if +all tests are run in the order of highest to lowest rank. + +.. option:: --unlink + +With :option:`--write`, unlink all input files after the output +has been successfully created. + +.. option:: --version + +Displays program version and exits. + +.. option:: --write + +Specifies the aggregate coverage results, summed across all the files, +should be written to the given filename in verilator_coverage data format. +This is useful for use in scripts to combine many coverage data files +(likely generated from random test runs) into one master coverage file. + +.. option:: --write-info + +Specifies the aggregate coverage results, summed across all the files, +should be written to the given filename in :command:`lcov` .info format. +This may be used to feed into :command:`lcov` to aggregate or generate +reports. + +The info format loses data compared to the Verilator coverage data format; +the info will all forms of coverage converted to line style coverage, and +if there are multiple coverage points on a single line, the minimum +coverage across those points will be used to report coverage of the line. diff --git a/docs/guide/exe_verilator_gantt.rst b/docs/guide/exe_verilator_gantt.rst new file mode 100644 index 000000000..ea660c09a --- /dev/null +++ b/docs/guide/exe_verilator_gantt.rst @@ -0,0 +1,76 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +verilator_gantt +=============== + +Verilator_gantt creates a visual representation to help analyze Verilator +multithreaded simulation performance, by showing when each macro-task +starts and ends, and showing when each thread is busy or idle. + +For an overview of use of verilator_gantt, see :ref:`Profiling`. + +Gantt Chart Contents +-------------------- + +The generated Gantt chart has time on the X-axis. Times shown are to the +scale printed, i.e. a certain about of time for each character width. The +Y-axis shows threads, each thread's execution is shown on one line. That +line shows "[" at the position in time when it executes. + +Following the "[" is the CPU number the task executed on, followed by zero +or more "-" to make the width of the characters match the scaled execution +time, followed by a "]". If the scale is too small, the CPU number and +mtask number will not be printed. If the scale is very small, a "&" +indicates multiple mtasks started at that time position. + +Also creates a value change dump (VCD) format dump file which may be viewed +in a waveform viewer (e.g. C). See below. + +Gantt Chart VCD Signals +----------------------- + +In waveforms there are the following signals. Most signals the "decimal" +format will remove the leading zeros and make the traces easier to read. + +parallelism + The number of mtasks active at this time, for best performance this will + match the thread count. You may want to use an "analog step" format to + view this signal. + +cpu#_thread + For the given CPU number, the thread number executing. + +mtask#_cpu + For the given mtask id, the CPU it is executing on. + +thread#_mtask + For the given thread number, the mtask id executing. + +verilator_gantt Arguments +------------------------- + +.. program:: verilator_gantt + +.. option:: + +The filename to read data from, defaults to "profile_threads.dat". + +.. option:: --help + +Displays a help summary, the program version, and exits. + +.. option:: --scale + +Sets the number of time units per character on the X-axis of the generated +Gantt chart. (On x86, time units are rdtsc ticks.) Defaults to 0, which +will automatically compute a reasonable scale where no two mtasks need to +fit into same character width's worth of scaled time. + +.. option:: --no-vcd + +Disables creating a .vcd file. + +.. option:: --vcd + +Sets the output filename for vcd dump. Default is "verilator_gantt.vcd". diff --git a/docs/guide/exe_verilator_profcfuncs.rst b/docs/guide/exe_verilator_profcfuncs.rst new file mode 100644 index 000000000..f3ac26b81 --- /dev/null +++ b/docs/guide/exe_verilator_profcfuncs.rst @@ -0,0 +1,25 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +verilator_profcfuncs +==================== + +Verilator_profcfunc reads a profile report created by gprof. The names of +the functions are then transformed, assuming the user used Verilator's +--prof-cfuncs, and a report printed showing the percentage of time, etc, in +each Verilog block. + +For an overview of use of verilator_profcfuncs, see :ref:`Profiling`. + +verilator_profcfuncs Arguments +------------------------------ + +.. program:: verilator_profcfuncs + +.. option:: + +The :command:`gprof`-generated filename to read data from. Typically "gprof.out". + +.. option:: --help + +Displays a help summary, the program version, and exits. diff --git a/docs/guide/executables.rst b/docs/guide/executables.rst new file mode 100644 index 000000000..e9c3fc700 --- /dev/null +++ b/docs/guide/executables.rst @@ -0,0 +1,19 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +********************************* +Executable and Argument Reference +********************************* + +This section describes the executables that are part of Verilator, and the +options to each executable. + +.. toctree:: + :maxdepth: 1 + :hidden: + + exe_verilator.rst + exe_verilator_coverage.rst + exe_verilator_gantt.rst + exe_verilator_profcfuncs.rst + exe_sim.rst diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst new file mode 100644 index 000000000..d88490afe --- /dev/null +++ b/docs/guide/extensions.rst @@ -0,0 +1,492 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +******************* +Language Extensions +******************* + +The following additional constructs are the extensions Verilator supports +on top of standard Verilog code. Using these features outside of comments +or "`ifdef`"'s may break other tools. + +.. option:: `__FILE__ + + The :option:`\`__FILE__` define expands to the current filename as a + string, like C++'s __FILE__. This Verilator feature added in 2006 was + incorporated into the IEEE 1800-2009 standard. + +.. option:: `__LINE__ + + The :option:`\`__LINE__` define expands to the current filename as a + string, like C++'s __LINE__. This Verilator feature added in 2006 was + incorporated into the IEEE 1800-2009 standard. + +.. option:: `error [string] + + This will report an error when encountered, like C++'s #error. + +.. option:: $c([string], ...); + + The string will be embedded directly in the output C++ code at the point + where the surrounding Verilog code is compiled. It may either be a + standalone statement (with a trailing ; in the string), or a function + that returns up to a 32-bit number (without a trailing ;). This can be + used to call C++ functions from your Verilog code. + + String arguments will be put directly into the output C++ code. + Expression arguments will have the code to evaluate the expression + inserted. Thus to call a C++ function, :code:`$c("func(",a,")")` will + result in :code:`func(a)` in the output C++ code. For input arguments, + rather than hard-coding variable names in the string + :code:`$c("func(a)")`, instead pass the variable as an expression + ::code:`$c("func(",a,")")`. This will allow the call to work inside + Verilog functions where the variable is flattened out, and also enable + other optimizations. + + If you will be reading or writing any Verilog variables inside the C++ + functions, the Verilog signals must be declared with + :option:`/*verilator&32;public*/` metacomments. + + You may also append an arbitrary number to $c, generally the width of + the output; :code:`signal_32_bits = $c32("...");`. This allows for + compatibility with other simulators which require a differently named + PLI function name for each different output width. + +.. option:: $display, $write, $fdisplay, $fwrite, $sformat, $swrite + + Format arguments may use C fprintf sizes after the % escape. Per the + Verilog standard, %x prints a number with the natural width, and %0x + prints a number with minimum width. Verilator extends this so %5x + prints 5 digits per the C standard (this is unspecified in Verilog, but + was incorporated into the 1800-2009). + +.. option:: `coverage_block_off + + Specifies the entire begin/end block should be ignored for coverage + analysis. Must be inside a code block, e.g. within a begin/end pair. + Same as :option:`coverage_block_off` in :ref:`Configuration Files`. + +.. option:: `systemc_header + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the output .h file's header. Must be placed as a module + item, e.g. directly inside a module/endmodule pair. Despite the name of + this macro, this also works in pure C++ code. + +.. option:: `systemc_ctor + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the C++ class constructor. Must be placed as a module + item, e.g. directly inside a module/endmodule pair. Despite the name of + this macro, this also works in pure C++ code. + +.. option:: `systemc_dtor + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the C++ class destructor. Must be placed as a module + item, e.g. directly inside a module/endmodule pair. Despite the name of + this macro, this also works in pure C++ code. + +.. option:: `systemc_interface + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the C++ class interface. Must be placed as a module item, + e.g. directly inside a module/endmodule pair. Despite the name of this + macro, this also works in pure C++ code. + +.. option:: `systemc_imp_header + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the header of all files for this C++ class implementation. + Must be placed as a module item, e.g. directly inside a module/endmodule + pair. Despite the name of this macro, this also works in pure C++ code. + +.. option:: `systemc_implementation + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into a single file of the C++ class implementation. Must be + placed as a module item, e.g. directly inside a module/endmodule + pair. Despite the name of this macro, this also works in pure C++ code. + + If you will be reading or writing any Verilog variables in the C++ + functions, the Verilog signals must be declared with a + :option:`/*verilator&32;public*/` metacomment. See also the public task + feature; writing an accessor may result in cleaner code. + +.. option:: `SYSTEMVERILOG + + The SYSTEMVERILOG, SV_COV_START and related standard defines are set by + default when :vlopt:`--language <--language>` is "1800-\*". + +.. option:: `VERILATOR + +.. option:: `verilator + +.. option:: `verilator3 + + The VERILATOR, verilator and verilator3 defines are set by default so + you may "\`ifdef" around tool specific constructs. + +.. option:: `verilator_config + + Take remaining text up to the next :option:`\`verilog` mode switch and + treat it as Verilator configuration commands. See :ref:`Configuration Files`. + +.. option:: `verilog + + Switch back to processing Verilog code after a + :option:`\`systemc_... <\`systemc_header>` mode switch. The Verilog + code returns to the last language mode specified with + "\`begin_keywords", or SystemVerilog if none was specified. + +.. option:: /*verilator&32;clock_enable*/ + + Used after a signal declaration to indicate the signal is used to gate a + clock, and the user takes responsibility for insuring there are no races + related to it. (Typically by adding a latch, and running static timing + analysis.) For example: + + .. code-block:: sv + + reg enable_r /*verilator clock_enable*/; + wire gated_clk = clk & enable_r; + always_ff @(posedge clk) + enable_r <= enable_early; + + The clock_enable attribute will cause the clock gate to be ignored in + the scheduling algorithm, sometimes required for correct clock behavior, + and always improving performance. It's also a good idea to enable the + :option:`IMPERFECTSCH` warning, to ensure all clock enables are properly + recognized. + + Same as :option:`clock_enable` configuration file option. + +.. option:: /*verilator&32;clocker*/ + +.. option:: /*verilator&32;no_clocker*/ + + Used after a signal declaration to indicate the signal is used as clock + or not. This information is used by Verilator to mark the signal as + clocker and propagate the clocker attribute automatically to derived + signals. See :vlopt:`--clk`. + + Same as :option:`clocker` and :option:`no_clocker` in configuration + files. + +.. option:: /*verilator&32;coverage_block_off*/ + + Specifies the entire begin/end block should be ignored for coverage + analysis purposes. + + Same as :option:`coverage_block_off` configuration file option. + +.. option:: /*verilator&32;coverage_off*/ + + Specifies that following lines of code should have coverage disabled. + Often used to ignore an entire module for coverage analysis purposes. + +.. option:: /*verilator&32;coverage_on*/ + + Specifies that following lines of code should have coverage re-enabled + (if appropriate :vlopt:`--coverage` flags are passed) after being + disabled earlier with :option:`/*verilator&32;coverage_off*/`. + + +.. _verilator_hier_block: + +.. option:: /*verilator&32;hier_block*/ + + Specifies that the module is a unit of hierarchical Verilation. This + metacomment must be between :code:`module module_name(...);` and + :code:`endmodule`. The module will not be inlined nor uniquified for + each instance in hierarchical Verilation. Note that the metacomment is + ignored unless the :vlopt:`--hierarchical` option is specified. + + See :ref:`Hierarchical Verilation`. + +.. option:: /*verilator&32;inline_module*/ + + Specifies the module the comment appears in may be inlined into any + modules that use this module. This is useful to speed up simulation + runtime. Note if using :vlopt:`--public` that signals under inlined + submodules will be named :code:`{submodule}__DOT__{subsignal}` as C++ + does not allow "." in signal names. + + Same as :option:`inline` configuration file option. + +.. option:: /*verilator&32;isolate_assignments*/ + + Used after a signal declaration to indicate the assignments to this + signal in any blocks should be isolated into new blocks. When there is + a large combinatorial block that is resulting in an ``UNOPTFLAT`` + warning, attaching this to the signal causing a false loop may clear up + the problem. + + IE, with the following: + + .. code-block:: sv + + reg splitme /* verilator isolate_assignments*/; + // Note the placement of the semicolon above + always_comb begin + if (....) begin + splitme = ....; + other assignments + end + end + + Verilator will internally split the block that assigns to "splitme" into + two blocks: + + It would then internally break it into (sort of): + + .. code-block:: sv + + // All assignments excluding those to splitme + always_comb begin + if (....) begin + other assignments + end + end + // All assignments to splitme + always_comb begin + if (....) begin + splitme = ....; + end + end + + Same as :option:`isolate_assignments` configuration file option. + +.. option:: /*verilator&32;lint_off */ + + Disable the specified warning message for any warnings following the + comment. + +.. option:: /*verilator&32;lint_on */ + + Re-enable the specified warning message for any warnings following the + comment. + +.. option:: /*verilator&32;lint_restore*/ + + After a :code:`/*verilator&32;lint_save*/`, pop the stack containing lint + message state. Often this is useful at the bottom of include files. + +.. option:: /*verilator&32;lint_save*/ + + Push the current state of what lint messages are turned on or turned off + to a stack. Later meta-comments may then lint_on or lint_off specific + messages, then return to the earlier message state by using + :code:`/*verilator&32;lint_restore*/`. For example: + + .. code-block:: sv + + // verilator lint_save + // verilator lint_off WIDTH + ... // code needing WIDTH turned off + // verilator lint_restore + + If WIDTH was on before the lint_off, it will now be restored to on, and + if it was off before the lint_off it will remain off. + +.. option:: /*verilator&32;no_inline_module*/ + + Specifies the module the comment appears in should not be inlined into + any modules that use this module. + + Same as :option:`no_inline` configuration file option. + +.. option:: /*verilator&32;no_inline_task*/ + + Used in a function or task variable definition section to specify the + function or task should not be inlined into where it is used. This may + reduce the size of the final executable when a task is used a very large + number of times. For this flag to work, the task and tasks below it + must be pure; they cannot reference any variables outside the task + itself. + + Same as :option:`no_inline` configuration file option. + +.. option:: /*verilator&32;public*/ (on parameter) + + Used after a parameter declaration to indicate the emitted C code should + have the parameter values visible. Due to C++ language restrictions, + this may only be used on 64-bit or narrower integral enumerations. + + .. code-block:: sv + + parameter [2:0] PARAM /*verilator public*/ = 2'b0; + +.. option:: /*verilator&32;public*/ (on typedef enum) + + Used after an enum typedef declaration to indicate the emitted C code + should have the enum values visible. Due to C++ language restrictions, + this may only be used on 64-bit or narrower integral enumerations. + + .. code-block:: sv + + typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/; + +.. option:: /*verilator&32;public*/ (on variable) + + Used after an input, output, register, or wire declaration to indicate + the signal should be declared so that C code may read or write the value + of the signal. This will also declare this module public, otherwise use + :code:`/*verilator&32;public_flat*/`. + + Instead of using public variables, consider instead making a DPI or + public function that accesses the variable. This is nicer as it + provides an obvious entry point that is also compatible across + simulators. + + Same as :option:`public` configuration file option. + +.. option:: /*verilator&32;public*/ (on task/function) + + Used inside the declaration section of a function or task declaration to + indicate the function or task should be made into a C++ function, public + to outside callers. Public tasks will be declared as a void C++ + function, public functions will get the appropriate non-void (bool, + uint32_t, etc) return type. Any input arguments will become C++ + arguments to the function. Any output arguments will become C++ + reference arguments. Any local registers/integers will become function + automatic variables on the stack. + + Wide variables over 64 bits cannot be function returns, to avoid + exposing complexities. However, wide variables can be input/outputs; + they will be passed as references to an array of 32-bit numbers. + + Generally, only the values of stored state (flops) should be written, as + the model will NOT notice changes made to variables in these functions. + (Same as when a signal is declared public.) + + You may want to use DPI exports instead, as it's compatible with other + simulators. + + Same as :option:`public` configuration file option. + +.. option:: /*verilator&32;public_flat*/ (on variable) + + Used after an input, output, register, or wire declaration to indicate + the signal should be declared so that C code may read or write the value + of the signal. This will not declare this module public, which means + the name of the signal or path to it may change based upon the module + inlining which takes place. + + Same as :option:`public_flat` configuration file option. + +.. option:: /*verilator&32;public_flat_rd*/ (on variable) + + Used after an input, output, register, or wire declaration to indicate + the signal should be declared public_flat (see above), but read-only. + + Same as :option:`public_flat_rd` configuration file option. + +.. option:: /*verilator&32;public_flat_rw @()*/ (on variable) + + Used after an input, output, register, or wire declaration to indicate + the signal should be declared public_flat_rd (see above), and also + writable, where writes should be considered to have the timing specified + by the given sensitivity edge list. Set for all variables, ports and + wires using the :vlopt:`--public-flat-rw` option. + + Same as :option:`public_flat_rw` configuration file option. + +.. option:: /*verilator&32;public_module*/ + + Used after a module statement to indicate the module should not be + inlined (unless specifically requested) so that C code may access the + module. Verilator automatically sets this attribute when the module + contains any public signals or \`systemc_ directives. Also set for all + modules when using the :vlopt:`--public` option. + + Same as :option:`public` configuration file option. + +.. option:: /*verilator&32;sc_clock*/ + + Deprecated and ignored. Previously used after an input declaration to + indicate the signal should be declared in SystemC as a sc_clock instead + of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 + and later do not require clock pins to be sc_clocks and this is no + longer needed and is ignored. + +.. option:: /*verilator&32;sc_bv*/ + + Used after a port declaration. It sets the port to be of + :code:`sc_bv<{width}>` type, instead of bool, vluint32_t or vluint64_t. + This may be useful if the port width is parameterized and the + instantiating C++ code wants to always have a sc_bv so it can accept any + width. In general you should avoid using this attribute when not + necessary as with increasing usage of sc_bv the performance decreases + significantly. + + Same as :option:`sc_bv` configuration file option. + +.. option:: /*verilator&32;sformat*/ + + Attached to the final argument of type "input string" of a function or + task to indicate the function or task should pass all remaining + arguments through $sformatf. This allows creation of DPI functions with + $display like behavior. See the :file:`test_regress/t/t_dpi_display.v` + file for an example. + + Same as :option:`sformat` configuration file option. + +.. option:: /*verilator&32;split_var*/ + + Attached to a variable or a net declaration to break the variable into + multiple pieces typically to resolve ``UNOPTFLAT`` performance issues. + Typically the variables to attach this to are recommended by Verilator + itself, see :option:`UNOPTFLAT`. + + For example, Verilator will internally convert a variable with the + metacomment such as: + + .. code-block:: sv + + logic [7:0] x [0:1] /*verilator split_var*/; + + To: + + .. code-block:: sv + + logic [7:0] x__BRA__0__KET__ /*verilator split_var*/; + logic [7:0] x__BRA__1__KET__ /*verilator split_var*/; + + Note that the generated packed variables retain the split_var + metacomment because they may be split into further smaller pieces + according to the access patterns. + + This only supports unpacked arrays, packed arrays, and packed structs of + integer types (reg, logic, bit, byte, int...); otherwise if a split was + requested but cannot occur a SPLITVAR warning is issued. Splitting + large arrays may slow down the Verilation speed, so use this only on + variables that require it. + + Same as :option:`split_var` configuration file option. + +.. option:: /*verilator&32;tag */ + + Attached after a variable or structure member to indicate opaque (to + Verilator) text that should be passed through to the XML output as a tag, + for use by downstream applications. + +.. option:: /*verilator&32;tracing_off*/ + + Disable waveform tracing for all future signals that are declared in + this module, or instances below this module. Often this is placed just + after a primitive's module statement, so that the entire module and + instances below it are not traced. + +.. option:: /*verilator&32;tracing_on*/ + + Re-enable waveform tracing for all future signals or instances that are + declared. + + diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst new file mode 100644 index 000000000..ca99d5e7e --- /dev/null +++ b/docs/guide/faq.rst @@ -0,0 +1,495 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +****************************** +FAQ/Frequently Asked Questions +****************************** + +.. Extra heading level here so sidebar index looks nice + +Questions +========= + +Can I contribute? +""""""""""""""""" + +Please contribute! Just submit a pull request, or raise an issue to +discuss if looking for something to help on. For more information see our +contributor agreement. + + +How widely is Verilator used? +""""""""""""""""""""""""""""" + +Verilator is used by many of the largest silicon design companies, large +organizations such as CERN, and even by college student projects. + +Verilator is one of the "big 4" simulators, meaning one of the 4 main +SystemVerilog simulators available, namely the closed-source products Synopsys +VCS (tm), Mentor Questa/ModelSim (tm), Cadence +Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. +The three closed-source offerings are often collectively called the "big 3" +simulators. + + +Does Verilator run under Windows? +""""""""""""""""""""""""""""""""" + +Yes, using Cygwin. Verilated output also compiles under Microsoft Visual +C++, but this is not tested every release. + + +Can you provide binaries? +""""""""""""""""""""""""" + +You can install Verilator via the system package manager (apt, yum, etc.) +on many Linux distributions, including Debian, Ubuntu, SuSE, RedHat, and +others. These packages are provided by the Linux distributions and +generally will lag the version of the mainline Verilator repository. If no +binary package is available for your distribution, how about you set one +up? + + +How can it be faster than (name-a-big-3-closed-source-simulator)? +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Generally, the implied part of the question is "... with all of the +manpower they can put into developing it." + +Most simulators have to be compliant with the complete IEEE 1364 (Verilog) +and IEEE 1800 (SystemVerilog) standards, meaning they have to be event +driven. This prevents them from being able to reorder blocks and make +netlist-style optimizations, which are where most of the gains come from. + +You should not be scared by non-compliance. Your synthesis tool isn't +compliant with the whole standard to start with, so your simulator need not +be either. Verilator is closer to the synthesis interpretation, so this is +a good thing for getting working silicon. + + +Will Verilator output remain under my own license/copyright? +"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Yes, it's just like using GCC on your programs; this is why Verilator uses +the "GNU **Lesser** Public License Version 3" instead of the more typical +"GNU Public License". See the licenses for details, but in brief, if you +change Verilator itself or the header files Verilator includes, you must +make the source code available under the GNU Lesser Public License. +However, Verilator output (the Verilated code) only "include"s the licensed +files, and so you are **not** required to open-source release any output +from Verilator. + +You also have the option of using the Perl Artistic License, which again +does not require you to release your Verilog or generated code, and also +allows you to modify Verilator for internal use without distributing the +modified version. But please contribute back to the community! + +One limit is that you cannot under either license release a closed-source +Verilog simulation product incorporating Verilator. That is you can have a +commercial product, but must make the source code available. + +As is standard with Open Source, contributions back to Verilator will be +placed under the Verilator copyright and LGPL/Artistic license. Small test +cases will be released into the public domain so they can be used anywhere, +and large tests under the LGPL/Artistic, unless requested otherwise. + + +Why is running Verilator (to create a model) so slow? +""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Verilator may require more memory than the resulting simulator will +require, as Verilator internally creates all of the state of the resulting +generated simulator in order to optimize it. If it takes more than a few +minutes or so (and you're not using :vlopt:`--debug` since debug mode is +disk bound), see if your machine is paging; most likely you need to run it +on a machine with more memory. Very large designs are known to have topped +64 GB resident set size. Alternatively, see :ref:`Hierarchical Verilation`. + + +How do I generate waveforms (traces) in C++? +"""""""""""""""""""""""""""""""""""""""""""" + +See also the next question for tracing in SystemC mode. + +A. Pass the :vlopt:`--trace` option to Verilator, and in your top level C + code, call ``Verilated::traceEverOn(true)``. Then you may use + ``$dumpfile`` and ``$dumpvars`` to enable traces, same as with any + Verilog simulator. See ``examples/make_tracing_c`` in the distribution. + +B. Or, for finer-grained control, or C++ files with multiple Verilated + modules you may also create the trace purely from C++. Create a + VerilatedVcdC object, and in your main loop call + ``trace_object->dump(time)`` every time step, and finally call + ``trace_object->close()``. + + .. code-block:: C++ + :emphasize-lines: 1,5-8,12 + + #include "verilated_vcd_c.h" + ... + int main(int argc, char** argv, char** env) { + ... + Verilated::traceEverOn(true); + VerilatedVcdC* tfp = new VerilatedVcdC; + topp->trace(tfp, 99); // Trace 99 levels of hierarchy + tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); + ... + while (Verilated::time() < sim_time && !Verilated::gotFinish()) { + Verilated::timeInc(1); + tfp->dump(main_time); + } + tfp->close(); + } + +You also need to compile :file:`verilated_vcd_c.cpp` and add it to your +link, preferably by adding the dependencies in your Makefile's +:code:`$(VK_GLOBAL_OBJS)` link rule. This is done for you if using the +Verilator :vlopt:`--exe` option. + +you can call :code:`trace_object->trace()` on multiple Verilated objects +with the same trace file if you want all data to land in the same output +file. + + +How do I generate waveforms (traces) in SystemC? +"""""""""""""""""""""""""""""""""""""""""""""""" + +A. Pass the :vlopt:`--trace` option to Verilator, and in your top level + :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`. Then you + may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, same as + with any Verilog simulator, see the non-SystemC example in + :file:`examples/make_tracing_c`. This will trace only the module + containing the :code:`$dumpvar`. + +B. Or, you may create a trace purely from SystemC, which may trace all + Verilated designs in the SystemC model. Create a VerilatedVcdSc object + as you would create a normal SystemC trace file. For an example, see + the call to ``VerilatedVcdSc`` in the + :file:`examples/make_tracing_sc/sc_main.cpp` file of the distribution, + and below. + +C. Alternatively you may use the C++ trace mechanism described in the + previous question, note the timescale and timeprecision will be + inherited from your SystemC settings. + + .. code-block:: C++ + :emphasize-lines: 1,5-8 + + #include "verilated_vcd_sc.h" + ... + int main(int argc, char** argv, char** env) { + ... + Verilated::traceEverOn(true); + VerilatedVcdSc* tfp = new VerilatedVcdSc; + topp->trace(tfp, 99); // Trace 99 levels of hierarchy + tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); + ... + sc_start(1); + ... + tfp->close(); + } + + + +You also need to compile :file:`verilated_vcd_sc.cpp` and +:file:`verilated_vcd_c.cpp` and add them to your link, preferably by adding +the dependencies in your Makefile's :code:`$(VK_GLOBAL_OBJS)` link rule. +This is done for you if using the Verilator :vlopt:`--exe` option. + +You can call :code:`->trace()` on multiple Verilated objects with the same +trace file if you want all data to land in the same output file. + +When using SystemC 2.3, the SystemC library must have been built with the +experimental simulation phase callback based tracing disabled. This is +disabled by default when building SystemC with its configure based build +system, but when building SystemC with CMake, you must pass +``-DENABLE_PHASE_CALLBACKS_TRACING=OFF`` to disable this feature. + + +How do I generate FST waveforms (traces) in C++ or SystemC? +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +FST is a trace file format developed by GTKWave. Verilator provides basic +FST support. To dump traces in FST format, add the :vlopt:`--trace-fst` +option to Verilator and either A. use :code:`$dumpfile & $dumpvars` in +Verilog as described in the VCD example above, + +Or, in C++ change the include described in the VCD example above: + +.. code-block:: C++ + + #include "verilated_fst_c.h" + VerilatedFstC* tfp = new VerilatedFstC; + + +Or, in SystemC change the include described in the VCD example above: + +.. code-block:: C++ + + #include "verilated_fst_sc.h" + VerilatedFstC* tfp = new VerilatedFstSc; + + +Note that currently supporting both FST and VCD in a single simulation is +impossible, but such requirement should be rare. You can however ifdef +around the trace format in your C++ main loop, and select VCD or FST at +build time, should you require. + + +How do I view waveforms (aka dumps or traces)? +"""""""""""""""""""""""""""""""""""""""""""""" + +Verilator creates standard VCD (Value Change Dump) and FST files. VCD +files are viewable with the open source GTKWave (recommended) or Dinotrace +(legacy) programs, or any of the many closed-source offerings; FST is +supported only by GTKWave. + + +How do I speed up writing large waveform (trace) files? +""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +A. Instead of calling ``VerilatedVcdC->open`` or ``$dumpvars`` at the + beginning of time, delay calling it until the time stamp where you want + tracing to begin. + +B. Add the :option:`/*verilator&32;tracing_off*/` metacomment to any very + low level modules you never want to trace (such as perhaps library + cells). + +C. Use the :vlopt:`--trace-depth` option to limit the depth of tracing, for + example :vlopt:`--trace-depth 1 <--trace-depth>` to see only the top + level signals. + +D. You can also consider using FST tracing instead of VCD. FST dumps are a + fraction of the size of the equivalent VCD. FST tracing can be slower + than VCD tracing, but it might be the only option if the VCD file size + is prohibitively large. + +E. Be sure you write your trace files to a local solid-state drive, instead + of to a network drive. Network drives are generally far slower. + + +Where is the translate_off command? (How do I ignore a construct?) +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Translate on/off pragmas are generally a bad idea, as it's easy to have +mismatched pairs, and you can't see what another tool sees by just +preprocessing the code. Instead, use the preprocessor; Verilator defines +the ``\`VERILATOR`` define for you, so just wrap the code in an ifndef +region: + + .. code-block:: sv + :emphasize-lines: 1 + + `ifndef VERILATOR + Something_Verilator_Dislikes; + `endif + +Most synthesis tools similarly define SYNTHESIS for you. + + +Why do I get "unexpected 'do'" or "unexpected 'bit'" errors? +"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +The words \ ``do``\ , \ ``bit``\ , \ ``ref``\ , \ ``return``\ , and others +are reserved keywords in SystemVerilog. Older Verilog code might use these +as identifiers. You should change your code to not use them to ensure it +works with newer tools. Alternatively, surround them by the Verilog +2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code. + +.. code-block:: sv + :emphasize-lines: 1 + + `begin_keywords "1364-2001" + integer bit; initial bit = 1; + `end_keywords + + +If you want the whole design to be parsed as Verilog 2001, see the +:vlopt:`--default-language` option. + + +How do I prevent my assertions from firing during reset? +"""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Call :code:`Verilated::assertOn(false)` before you first call the model, +then turn it back on after reset. It defaults to true. When false, all +assertions controlled by :vlopt:`--assert` are disabled. + + +Why do I get "undefined reference to sc_time_stamp()? +""""""""""""""""""""""""""""""""""""""""""""""""""""" + +In Verilator 4.200 and later, using the timeInc function is recommended +instead. See the :ref:`Connecting to C++` examples. Some linkers (MSVC++) +still require :code:`sc_time_stamp()` to be defined, either define this +with :code:`double sc_time_stamp() { return 0; }` or compile the Verilated +code with :code:`-CFLAGS -DVL_TIME_CONTEXT`. + +Prior to Verilator 4.200, the :code:`sc_time_stamp()` function needs to be +defined in C++ (non SystemC) to return the current simulation time. + + +Why do I get "undefined reference to \`VL_RAND_RESET_I' or \`Verilated::...'"? +"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +You need to link your compiled Verilated code against the +:code:`verilated.cpp` file found in the include directory of the Verilator +kit. This is one target in the ``$(VK_GLOBAL_OBJS)`` make variable, which +should be part of your Makefile's link rule. If you use :vlopt:`--exe`, +this is done for you. + + +Is the PLI supported? +""""""""""""""""""""" + +Only somewhat. More specifically, the common PLI-ish calls $display, +$finish, $stop, $time, $write are converted to C++ equivalents. You can +also use the "import DPI" SystemVerilog feature to call C code (see the +chapter above). There is also limited VPI access to public signals. + +If you want something more complex, since Verilator emits standard C++ +code, you can simply write your own C++ routines that can access and modify +signal values without needing any PLI interface code, and call it with +$c("{any_c++_statement}"). + +See the :ref:`Connecting` section. + + +How do I make a Verilog module that contain a C++ object? +""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +You need to add the object to the structure that Verilator creates, then +use $c to call a method inside your object. The +:file:`test_regress/t/t_extend_class` files in the distribution show an +example of how to do this. + + +How do I get faster build times? +"""""""""""""""""""""""""""""""" + +* When running make, pass the make variable VM_PARALLEL_BUILDS=1 so that + builds occur in parallel. Note this is now set by default if an output + file was large enough to be split due to the :vlopt:`--output-split` + option. + +* Verilator emits any infrequently executed "cold" routines into separate + __Slow.cpp files. This can accelerate compilation as optimization can be + disabled on these routines. See the OPT_FAST and OPT_SLOW make variables + and :ref:`Benchmarking & Optimization`. + +* Use a recent compiler. Newer compilers tend to be faster. + +* Compile in parallel on many machines and use caching; see the web for the + ccache, distcc and icecream packages. ccache will skip GCC runs between + identical source builds, even across different users. If ccache was + installed when Verilator was built it is used, or see OBJCACHE + environment variable to override this. Also see the + :vlopt:`--output-split` option. + +* To reduce the compile time of classes that use a Verilated module (e.g. a + top CPP file) you may wish to add a + :option:`/*verilator&32;no_inline_module*/` metacomment to your top level + module. This will decrease the amount of code in the model's Verilated + class, improving compile times of any instantiating top level C++ code, + at a relatively small cost of execution performance. + +* Use :ref:`hierarchical verilation`. + + +Why do so many files need to recompile when I add a signal? +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Adding a new signal requires the symbol table to be recompiled. Verilator +uses one large symbol table, as that results in 2-3 less assembly +instructions for each signal access. This makes the execution time 10-15% +faster, but can result in more compilations when something changes. + + +How do I access Verilog functions/tasks in C? +""""""""""""""""""""""""""""""""""""""""""""" + +Use the SystemVerilog Direct Programming Interface. You write a Verilog +function or task with input/outputs that match what you want to call in +with C. Then mark that function as a DPI export function. See the DPI +chapter in the IEEE Standard. + + +How do I access C++ functions/tasks in Verilog? +""""""""""""""""""""""""""""""""""""""""""""""" + +Use the SystemVerilog Direct Programming Interface. You write a Verilog +function or task with input/outputs that match what you want to call in +with C. Then mark that function as a DPI import function. See the DPI +chapter in the IEEE Standard. + + +How do I access signals in C? +""""""""""""""""""""""""""""" + +The best thing to do is to make a SystemVerilog "export DPI" task or +function that accesses that signal, as described in the DPI chapter in the +manual and DPI tutorials on the web. This will allow Verilator to better +optimize the model and should be portable across simulators. + +If you really want raw access to the signals, declare the signals you will +be accessing with a :option:`/*verilator&32;public*/` metacomment before +the closing semicolon. Then scope into the C++ class to read the value of +the signal, as you would any other member variable. + +Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t), +16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or +64-bit unsigned long longs (uint64_t) that fits the width of the signal. +Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for +1 to 64 bits, and the compiler will properly up-convert smaller entities. +Note even signed ports are declared as unsigned; you must sign extend +yourself to the appropriate signal width. + +Signals wider than 64 bits are stored as an array of 32-bit uint32_t's. +Thus to read bits 31:0, access signal[0], and for bits 63:32, access +signal[1]. Unused bits (for example bit numbers 65-96 of a 65-bit vector) +will always be zero. If you change the value you must make sure to pack +zeros in the unused bits or core-dumps may result, because Verilator strips +array bound checks where it believes them to be unnecessary to improve +performance. + +In the SYSTEMC example above, if you had in our.v: + + .. code-block:: sv + + input clk /*verilator public*/; + // Note the placement of the semicolon above + +From the sc_main.cpp file, you'd then: + + .. code-block:: C++ + + #include "Vour.h" + #include "Vour_our.h" + cout << "clock is " << top->our->clk << endl; + + +In this example, clk is a bool you can read or set as any other variable. +The value of normal signals may be set, though clocks shouldn't be changed +by your code or you'll get strange results. + + +Should a module be in Verilog or SystemC? +""""""""""""""""""""""""""""""""""""""""" + +Sometimes there is a block that just interconnects instances, and have a +choice as to if you write it in Verilog or SystemC. Everything else being +equal, best performance is when Verilator sees all of the design. So, look +at the hierarchy of your design, labeling instances as to if they are +SystemC or Verilog. Then: + +* A module with only SystemC instances below must be SystemC. + +* A module with a mix of Verilog and SystemC instances below must be + SystemC. (As Verilator cannot connect to lower-level SystemC instances.) + +* A module with only Verilog instances below can be either, but for best + performance should be Verilog. (The exception is if you have a design + that is instantiated many times; in this case Verilating one of the lower + modules and instantiating that Verilated instances multiple times into a + SystemC module *may* be faster.) diff --git a/docs/guide/files.rst b/docs/guide/files.rst new file mode 100644 index 000000000..cc2dca400 --- /dev/null +++ b/docs/guide/files.rst @@ -0,0 +1,141 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +***** +Files +***** + +.. _Files in the Distribution: + +Files in the Git Tree +===================== + +The following is a summary of the files in the Git Tree (distribution) of +Verilator: + +:: + + Changes => Version history + README.rst => This document + bin/verilator => Compiler wrapper invoked to Verilate code + docs/ => Additional documentation + examples/ => Examples (see manual for descriptions) + include/ => Files that should be in your -I compiler path + include/verilated*.cpp => Global routines to link into your simulator + include/verilated*.h => Global headers + include/verilated.mk => Common Makefile + src/ => Translator source code + test_regress => Internal tests + + +.. _Files Read/Written: + +Files Read/Written +================== + +All output files are placed in the output directory specified with the +:vlopt:`--Mdir` option, or "obj_dir" if not specified. + +Verilator creates the following files in the output directory: + +For --cc/--sc, it creates: + +.. list-table:: + + * - *{prefix}*\ .cmake + - CMake include script for compiling (from --make cmake) + * - *{prefix}*\ .mk + - Make include file for compiling (from --make gmake) + * - *{prefix}*\ _classes.mk + - Make include file with class names (from --make gmake) + * - *{prefix}*\ _hier.mk + - Make file for hierarchy blocks (from --make gmake) + * - *{prefix|*\ _hierMkArgs.f + - Arguments for hierarchical Verilation (from --make gmake) + * - *{prefix}*\ _hierCMakeArgs.f + - Arguments for hierarchical Verilation (from --make cmake) + * - *{prefix}*\ .cpp + - Top level C++ file + * - *{prefix}{__n}*\ .cpp + - Additional top C++ files (from --output-split) + * - *{prefix}*\ .h + - Top level header + * - *{prefix}*\ __Slow\ *{__n}*\ .cpp + - Infrequent cold routines + * - *{prefix}*\ __Dpi.cpp + - DPI import and export wrappers (from --dpi) + * - *{prefix}*\ __Dpi.h + - DPI import and export declarations (from --dpi) + * - *{prefix}*\ __Inlines.h + - Inline support functions + * - *{prefix}*\ __Syms.cpp + - Global symbol table C++ + * - *{prefix}*\ __Syms.h + - Global symbol table header + * - *{prefix}*\ __Trace{__n}*\ .cpp + - Wave file generation code (from --trace) + * - *{prefix}*\ __Trace__Slow{__n}*\ .cpp + - Wave file generation code (from --trace) + * - *{prefix}{each_verilog_module}*\ .cpp + - Lower level internal C++ files + * - *{prefix}{each_verilog_module}*\ .h + - Lower level internal header files + * - *{prefix}{each_verilog_module}{__n}*\ .cpp + - Additional lower C++ files (from --output-split) + +For --hierarchy mode, it creates: + +.. list-table:: + + * - V\ *{hier_block}*\ / + - Directory to Verilate each hierarchy block (from --hierarchy) + * - *{prefix}*\ __hierVer.d + - Make dependencies of the top module (from --hierarchy) + * - *{prefix}*\ __hier.dir + - Directory to store .dot, .vpp, .tree of top module (from --hierarchy) + +In certain debug and other modes, it also creates: + +.. list-table:: + + * - *{prefix}*\ .xml + - XML tree information (from --xml) + * - *{prefix}*\ __cdc.txt + - Clock Domain Crossing checks (from --cdc) + * - *{prefix}*\ __stats.txt + - Statistics (from --stats) + * - *{prefix}*\ __idmap.txt + - Symbol demangling (from --protect-ids) + * - *{prefix}*\ __ver.d + - Make dependencies (from -MMD) + * - *{prefix}*\ __verFiles.dat + - Timestamps (from --skip-identical) + * - *{prefix}{misc}*\ .dot + - Debugging graph files (from --debug) + * - *{prefix}{misc}*\ .tree + - Debugging files (from --debug) + * - {mod_prefix}_{each_verilog_module}*{__n}*\ .vpp + - Pre-processed verilog (from --debug) + +After running Make, the C++ compiler may produce the following: + +.. list-table:: + + * - verilated{misc}*\ .d + - Intermediate dependencies + * - verilated{misc}*\ .o + - Intermediate objects + * - {mod_prefix}{misc}*\ .d + - Intermediate dependencies + * - {mod_prefix}{misc}*\ .o + - Intermediate objects + * - *{prefix}*\ + - Final executable (from --exe) + * - *{prefix}*\ __ALL.a + - Library of all Verilated objects + * - *{prefix}*\ __ALL.cpp + - Include of all code for single compile + * - *{prefix}{misc}*\ .d + - Intermediate dependencies + * - *{prefix}{misc}*\ .o + - Intermediate objects diff --git a/docs/guide/index.rst b/docs/guide/index.rst new file mode 100644 index 000000000..42c18b4c1 --- /dev/null +++ b/docs/guide/index.rst @@ -0,0 +1,37 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. toctree:: + :maxdepth: 2 + :caption: Getting Started + + overview.rst + examples.rst + install.rst + + +.. toctree:: + :maxdepth: 2 + :caption: User's Guide + + verilating.rst + connecting.rst + simulating.rst + contributing.rst + faq.rst + + +.. toctree:: + :maxdepth: 1 + :caption: Reference Guide + + languages.rst + extensions.rst + executables.rst + warnings.rst + files.rst + environment.rst + deprecations.rst + contributors.rst + changes.rst + copyright.rst diff --git a/docs/guide/install.rst b/docs/guide/install.rst new file mode 100644 index 000000000..7154315ce --- /dev/null +++ b/docs/guide/install.rst @@ -0,0 +1,321 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Installation: + +************ +Installation +************ + +This section discusses how to install Verilator. + +.. _Package Manager Quick Install: + +Package Manager Quick Install +============================= + +Using a distribution's package manager is the easiest way to get +started. (Note packages are unlikely to have the most recent version, so +:ref:`Git Install`, might be a better alternative.) To install as a +package: + +:: + + apt-get install verilator # On Ubuntu + + +.. _Git Install: + +Git Quick Install +================= + +Installing Verilator from Git provides the most flexibility. For additional +options and details see :ref:`Detailed Build Instructions` below. + +In brief, to install from git: + +:: + + # Prerequisites: + #sudo apt-get install git perl python3 make autoconf g++ flex bison ccache + #sudo apt-get install libgoogle-perftools-dev numactl perl-doc + #sudo apt-get install libfl2 # Ubuntu only (ignore if gives error) + #sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error) + #sudo apt-get install zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error) + + git clone https://github.com/verilator/verilator # Only first time + ## Note the URL above is not a page you can see with a browser, it's for git only + + # Every time you need to build: + unsetenv VERILATOR_ROOT # For csh; ignore error if on bash + unset VERILATOR_ROOT # For bash + cd verilator + git pull # Make sure git repository is up-to-date + git tag # See what versions exist + #git checkout master # Use development branch (e.g. recent bug fixes) + #git checkout stable # Use most recent stable release + #git checkout v{version} # Switch to specified release version + + autoconf # Create ./configure script + ./configure # Configure and create Makefile + make -j # Build Verilator itself + sudo make install + + +.. _Detailed Build Instructions: + +Detailed Build Instructions +=========================== + +This section describes details of the build process, and assumes you are +building from Git. For using a pre-built binary for your Linux +distribution, see instead :ref:`Package Manager Quick Install`. + + +OS Requirements +--------------- + +Verilator is developed and has primary testing on Ubuntu, with additional +testing on FreeBSD and Apple OS-X. Versions have also built on Redhat +Linux, HPUX and Solaris. It should run with minor porting on any +GNU/Linux-ish platform. Verilator also works on Windows under Cygwin, and +Windows under MinGW (gcc -mno-cygwin). Verilated output (not Verilator +itself) compiles under all the options above, plus using MSVC++. + + +Install Prerequisites +--------------------- + +To build or run Verilator you need these standard packages: + +:: + + sudo apt-get install git perl python3 make + sudo apt-get install g++ # Alternatively, clang + sudo apt-get install libgz # Non-Ubuntu (ignore if gives error) + sudo apt-get install libfl2 # Ubuntu only (ignore if gives error) + sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error) + sudo apt-get install zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error) + +To build or run the following are optional but should be installed for good +performance: + +:: + + sudo apt-get install ccache # If present at build, needed for run + sudo apt-get install libgoogle-perftools-dev numactl perl-doc + +To build Verilator you will need to install these packages; these do not +need to be present to run Verilator: + +:: + + sudo apt-get install git autoconf flex bison + +Those developing Verilator itself may also want these (see internals.rst): + +:: + + sudo apt-get install gdb graphviz cmake clang clang-format gprof lcov + sudo pip3 install sphinx sphinx_rtd_theme breathe + cpan install Pod::Perldoc + cpan install Parallel::Forker + + +Install SystemC +^^^^^^^^^^^^^^^ + +If you will be using SystemC (vs straight C++ output), download `SystemC +`__. Follow their +installation instructions. You will need to set the +:option:`SYSTEMC_INCLUDE` environment variable to point to the include +directory with ``systemc.h`` in it, and set the :option:`SYSTEMC_LIBDIR` +environment variable to point to the directory with ``libsystemc.a`` in it. + + +Install GTKWave +^^^^^^^^^^^^^^^ + +To make use of Verilator FST tracing you will want `GTKwave +`__ installed, however this is not +required at Verilator build time. + + +Obtain Sources +-------------- + +Get the sources from the git repository: (You need do this only once, +ever.) + +:: + + git clone https://github.com/verilator/verilator # Only first time + ## Note the URL above is not a page you can see with a browser, it's for git only + +Enter the checkout and determine what version/branch to use: + +:: + + cd verilator + git pull # Make sure we're up-to-date + git tag # See what versions exist + #git checkout master # Use development branch (e.g. recent bug fix) + #git checkout stable # Use most recent release + #git checkout v{version} # Switch to specified release version + + +Auto Configure +-------------- + +Create the configuration script: + +:: + + autoconf # Create ./configure script + + +Eventual Installation Options +----------------------------- + +Before configuring the build, you have to decide how you're going to +eventually install Verilator onto your system. Verilator will be compiling +the current value of the environment variables :option:`VERILATOR_ROOT`, +:option:`SYSTEMC_INCLUDE`, and :option:`SYSTEMC_LIBDIR` as defaults into +the executable, so they must be correct before configuring. + +These are the installation options: + + +1. Run-in-Place from VERILATOR_ROOT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Our personal favorite is to always run Verilator in-place from its Git +directory. This allows the easiest experimentation and upgrading, and +allows many versions of Verilator to co-exist on a system. + +:: + + export VERILATOR_ROOT=`pwd` # if your shell is bash + setenv VERILATOR_ROOT `pwd` # if your shell is csh + ./configure + # Running will use files from $VERILATOR_ROOT, so no install needed + +Note after installing (below steps), a calling program or shell must set +the environment variable :option:`VERILATOR_ROOT` to point to this Git +directory, then execute ``$VERILATOR_ROOT/bin/verilator``, which will find +the path to all needed files. + + +2. Install into a specific location +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +You may eventually be installing onto a project/company-wide "CAD" tools +disk that may support multiple versions of every tool. Tell configure the +eventual destination directory name. We recommend the destination location +include the Verilator version name: + +:: + + unset VERILATOR_ROOT # if your shell is bash + unsetenv VERILATOR_ROOT # if your shell is csh + # For the tarball, use the version number instead of git describe + ./configure --prefix /CAD_DISK/verilator/`git describe | sed "s/verilator_//"` + +Note after installing (below steps), if you use `modulecmd +`__, you'll want a module file like the +following: + +:: + + set install_root /CAD_DISK/verilator/{version-number-used-above} + unsetenv VERILATOR_ROOT + prepend-path PATH $install_root/bin + prepend-path MANPATH $install_root/man + prepend-path PKG_CONFIG_PATH $install_root/share/pkgconfig + + +3. Install into a Specific Path +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +You may eventually install Verilator into a specific installation prefix, +as most GNU tools support: + +:: + + unset VERILATOR_ROOT # if your shell is bash + unsetenv VERILATOR_ROOT # if your shell is csh + ./configure --prefix /opt/verilator-VERSION + +Then after installing (below steps) you will need to add +``/opt/verilator-VERSION/bin`` to your ``$PATH`` environment variable. + + +4. Install System Globally +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The final option is to eventually install Verilator globally, using +configure's default system paths: + +:: + + unset VERILATOR_ROOT # if your shell is bash + unsetenv VERILATOR_ROOT # if your shell is csh + ./configure + +Then after installing (below) the binaries should be in a location that is +already in your ``$PATH`` environment variable. + + +Configure +--------- + +The command to configure the package was described in the previous step. +Developers should configure to have more complete developer tests. +Additional packages may be required for these tests. + +:: + + export VERILATOR_AUTHOR_SITE=1 # Put in your .bashrc + ./configure --enable-longtests ...above options... + + +Compile +------- + +Compile Verilator: + +:: + + make -j + + +Test +---- + +Check the compilation by running self-tests: + +:: + + make test + + +Install +------- + +If you used any install option other than the `1. Run-in-Place from +VERILATOR_ROOT <#_1_run_in_place_from_verilator_root>`__ scheme, install +the files: + +:: + + make install + + +.. Docker Build Environment + +.. include:: ../../ci/docker/buildenv/README.rst + + +.. Docker Run Environment + +.. include:: ../../ci/docker/run/README.rst diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst new file mode 100644 index 000000000..f09abbd26 --- /dev/null +++ b/docs/guide/languages.rst @@ -0,0 +1,477 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +*************** +Input Languages +*************** + +This section describes the languages Verilator takes as input. See also +:ref:`Configuration Files`. + + +Language Standard Support +========================= + +Verilog 2001 (IEEE 1364-2001) Support +------------------------------------- + +Verilator supports most Verilog 2001 language features. This includes +signed numbers, "always @\*", generate statements, multidimensional arrays, +localparam, and C-style declarations inside port lists. + + +Verilog 2005 (IEEE 1364-2005) Support +------------------------------------- + +Verilator supports most Verilog 2005 language features. This includes the +\`begin_keywords and \`end_keywords compiler directives, $clog2, and the +uwire keyword. + + +SystemVerilog 2005 (IEEE 1800-2005) Support +------------------------------------------- + +Verilator supports ==? and !=? operators, ++ and -- in some contexts, +$bits, $countbits, $countones, $error, $fatal, $info, $isunknown, $onehot, +$onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit, byte, +chandle, const, do-while, enum, export, final, import, int, interface, +logic, longint, modport, package, program, shortint, struct, time, typedef, +union, var, void, priority case/if, and unique case/if. + +It also supports .name and .\* interconnection. + +Verilator partially supports concurrent assert and cover statements; see +the enclosed coverage tests for the syntax which is allowed. + +Verilator has limited support for class and related object-oriented +constructs. + + +SystemVerilog 2012 (IEEE 1800-2012) Support +------------------------------------------- + +Verilator implements a full SystemVerilog-compliant preprocessor, including +function call-like preprocessor defines, default define arguments, +\`__FILE__, \`__LINE__ and \`undefineall. + + +SystemVerilog 2017 (IEEE 1800-2017) Support +------------------------------------------- + +Verilator supports the 2017 "for" loop constructs, and several minor +cleanups IEEE made in 1800-2017. + + +Verilog AMS Support +------------------- + +Verilator implements a very small subset of Verilog AMS (Verilog Analog and +Mixed-Signal Extensions) with the subset corresponding to those VMS +keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009 +languages. + +AMS parsing is enabled with :vlopt:`--language VAMS <--language>` or +:vlopt:`--language 1800+VAMS <--language>`. + +At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt, +string, and wreal. + + +Synthesis Directive Assertion Support +------------------------------------- + +With the :vlopt:`--assert` option, Verilator reads any :code:`//synopsys +full_case` or :code:`//synopsys parallel_case` directives. The same +applies to any :code:`//ambit synthesis`, :code:`//cadence` or +:code:`//pragma` directives of the same form. + +When these synthesis directives are discovered, Verilator will either +formally prove the directive to be true, or failing that, will insert the +appropriate code to detect failing cases at simulation runtime and print an +"Assertion failed" error message. + +Verilator likewise also asserts any "unique" or "priority" SystemVerilog +keywords on case statement, as well as "unique" on if statements. However, +"priority if" is currently simply ignored. + + +.. _Language Limitations: + +Language Limitations +==================== + +This section describes the language limitations of Verilator. Many of these +restrictions are by intent. + +Synthesis Subset +---------------- + +Verilator supports the Synthesis subset with other verification constructs +being added over time. Verilator also simulates events as Synopsys's Design +Compiler would; namely given a block of the form: + +.. code-block:: sv + + always @(x) y = x & z; + +This will recompute y when there is even a potential for change in x or a +change in z, that is when the flops computing x or z evaluate (which is +what Design Compiler will synthesize.) A compliant simulator would only +calculate y if x changes. We recommend using always_comb to make the code +run the same everywhere. Also avoid putting $displays in combo blocks, as +they may print multiple times when not desired, even on compliant +simulators as event ordering is not specified. + + +Signal Naming +------------- + +To avoid conflicts with C symbol naming, any character in a signal name +that is not alphanumeric nor a single underscore will be replaced by __0hh +where hh is the hex code of the character. To avoid conflicts with +Verilator's internal symbols, any double underscore are replaced with +___05F (5F is the hex code of an underscore.) + + +Bind +---- + +sVerilator only supports bind to a target module name, not to an +instance path. + + +Class +----- + +Verilator class support is limited but in active development. Verilator +supports members, and methods. Verilator does not support class static +members, class extend, or class parameters. + + +Dotted cross-hierarchy references +--------------------------------- + +Verilator supports dotted references to variables, functions and tasks in +different modules. The portion before the dot must have a constant value; +for example a[2].b is acceptable, while a[x].b is generally not. + +References into generated and arrayed instances use the instance names +specified in the Verilog standard; arrayed instances are named +``{instanceName}[{instanceNumber}]`` in Verilog, which becomes +``{instanceName}__BRA__{instanceNumber}__KET__`` inside the generated C++ +code. + + +Latches +------- + +Verilator is optimized for edge sensitive (flop based) designs. It will +attempt to do the correct thing for latches, but most performance +optimizations will be disabled around the latch. + + +Structures and Unions +--------------------- + +Presently Verilator only supports packed structs and packed unions. Rand +and randc tags on members are simply ignored. All structures and unions +are represented as a single vector, which means that generating one member +of a structure from blocking, and another from non-blocking assignments is +unsupported. + + +Time +---- + +All delays (#) are ignored, as they are in synthesis. + + +.. _Unknown States: + +Unknown States +-------------- + +Verilator is mostly a two state simulator, not a four state simulator. +However, it has two features which uncover most initialization bugs +(including many that a four state simulator will miss.) + +Identity comparisons (=== or !==) are converted to standard ==/!= when +neither side is a constant. This may make the expression yield a different +result compared to a four state simulator. An === comparison to X will +always be false, so that Verilog code which checks for uninitialized logic +will not fire. + +Assigning X to a variable will actually assign a constant value as +determined by the :vlopt:`--x-assign` option. This allows runtime +randomization, thus if the value is actually used, the random value should +cause downstream errors. Integers also get randomized, even though the +Verilog 2001 specification says they initialize to zero. Note however that +randomization happens at initialization time and hence during a single +simulation run, the same constant (but random) value will be used every +time the assignment is executed. + +All variables, depending on :vlopt:`--x-initial` setting, are typically +randomly initialized using a function. By running several random +simulation runs you can determine that reset is working correctly. On the +first run, have the function initialize variables to zero. On the second, +have it initialize variables to one. On the third and following runs have +it initialize them randomly. If the results match, reset works. (Note +this is what the hardware will really do.) In practice, just setting all +variables to one at startup finds most problems (since typically control +signals are active-high). + +:vlopt:`--x-assign` applies to variables explicitly initialized or assigned +an X. Uninitialized clocks are initialized to zero, while all other state +holding variables are initialized to a random value. Event driven +simulators will generally trigger an edge on a transition from X to 1 +(posedge) or X to 0 (negedge). However, by default, since clocks are +initialized to zero, Verilator will not trigger an initial negedge. Some +code (particularly for reset) may rely on X->0 triggering an edge. The +:vlopt:`--x-initial-edge` option enables this behavior. Comparing runs with +and without this option will find such problems. + + +Tri/Inout +--------- + +Verilator converts some simple tristate structures into two state. Pullup, +pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are +also supported. Simple comparisons with :code:`=== 1'bz` are also +supported. + +An assignment of the form: + +.. code-block:: sv + + inout driver; + wire driver = (enable) ? output_value : 1'bz; + +Will be converted to: + +.. code-block:: sv + + input driver; // Value being driven in from "external" drivers + output driver__en; // True if driven from this module + output driver__out; // Value being driven from this module + +External logic will be needed to combine these signals with any external +drivers. + +Tristate drivers are not supported inside functions and tasks; an inout +there will be considered a two state variable that is read and written +instead of a four state variable. + + +Functions & Tasks +----------------- + +All functions and tasks will be inlined (will not become functions in C.) +The only support provided is for simple statements in tasks (which may +affect global variables). + +Recursive functions and tasks are not supported. All inputs and outputs +are automatic, as if they had the Verilog 2001 "automatic" keyword +prepended. (If you don't know what this means, Verilator will do what you +probably expect, what C does. The default behavior of Verilog is +different.) + + +Generated Clocks +---------------- + +Verilator attempts to deal with generated and gated clocks correctly, +however some cases cause problems in the scheduling algorithm which is +optimized for performance. The safest option is to have all clocks as +primary inputs to the model, or wires directly attached to primary inputs. +For proper behavior clock enables may also need the +:option:`/*verilator&32;clock_enable*/` metacomment. + + +Gate Primitives +--------------- + +The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are +directly converted to behavioral equivalents. The 3-state and MOS gate +primitives are not supported. Tables are not supported. + + +Specify blocks +-------------- + +All specify blocks and timing checks are ignored. All min:typ:max delays +use the typical value. + + +Array Initialization +-------------------- + +When initializing a large array, you need to use non-delayed assignments. +Verilator will tell you when this needs to be fixed; see the BLKLOOPINIT +error for more information. + + +Array Out of Bounds +------------------- + +Writing a memory element that is outside the bounds specified for the array +may cause a different memory element inside the array to be written +instead. For power-of-2 sized arrays, Verilator will give a width warning +and the address. For non-power-of-2-sizes arrays, index 0 will be written. + +Reading a memory element that is outside the bounds specified for the array +will give a width warning and wrap around the power-of-2 size. For +non-power-of-2 sizes, it will return a unspecified constant of the +appropriate width. + + +Assertions +---------- + +Verilator is beginning to add support for assertions. Verilator currently +only converts assertions to simple :code:`if (...) error` statements, and +coverage statements to increment the line counters described in the +coverage section. + +Verilator does not support SEREs yet. All assertion and coverage +statements must be simple expressions that complete in one cycle. + + +Encrypted Verilog +----------------- + +Open source simulators like Verilator are unable to use encrypted RTL +(i.e. IEEE P1735). Talk to your IP vendor about delivering IP blocks via +Verilator's :vlopt:`--protect-lib` feature. + + +Language Keyword Limitations +============================ + +This section describes specific limitations for each language keyword. + +.. Hack to get long definition list: +.. |cmdslong1| replace:: \`__FILE__, \`__LINE__, \`begin_keywords, + \`begin_keywords, \`begin_keywords, \`begin_keywords, \`begin_keywords, + \`define, \`else, \`elsif, \`end_keywords, \`endif, \`error, \`ifdef, + \`ifndef, \`include, \`line, \`systemc_ctor, \`systemc_dtor, + \`systemc_header, \`systemc_imp_header, \`systemc_implementation, + \`systemc_interface, \`undef, \`verilog + +|cmdslong1| + Fully supported. + + +.. Hack to get long definition list: + +.. |cmdslong2| replace:: always, always_comb, always_ff, always_latch, and, + assign, begin, buf, byte, case, casex, casez, default, defparam, + do-while, else, end, endcase, endfunction, endgenerate, endmodule, + endspecify, endtask, final, for, function, generate, genvar, if, + initial, inout, input, int, integer, localparam, logic, longint, + macromodule, module, nand, negedge, nor, not, or, output, parameter, + posedge, reg, scalared, shortint, signed, supply0, supply1, task, time, + tri, typedef, var, vectored, while, wire, xnor, xor + +|cmdslong2| + Generally supported. + +++, -- operators + Increment/decrement can only be used as standalone statements or in + certain limited cases. + +'{} operator + Assignment patterns with order based, default, constant integer (array) + or member identifier (struct/union) keys are supported. Data type keys + and keys which are computed from a constant expression are not supported. + +\`uselib + Uselib, a vendor specific library specification method, is ignored along + with anything following it until the end of that line. + +cast operator + Casting is supported only between simple scalar types, signed and + unsigned, not arrays nor structs. + +chandle + Treated as a "longint"; does not yet warn about operations that are + specified as illegal on chandles. + +disable + Disable statements may be used only if the block being disabled is a + block the disable statement itself is inside. This was commonly used to + provide loop break and continue functionality before SystemVerilog added + the break and continue keywords. + +inside + Inside expressions may not include unpacked array traversal or $ as an + upper bound. Case inside and case matches are also unsupported. + +interface + Interfaces and modports, including with generated data types are + supported. Generate blocks around modports are not supported, nor are + virtual interfaces nor unnamed interfaces. + +shortreal + Short floating point (shortreal) numbers are converted to real. Most + other simulators either do not support float, or convert likewise. + +specify specparam + All specify blocks and timing checks are ignored. + +uwire + Verilator does not perform warning checking on uwires, it treats the + uwire keyword as if it were the normal wire keyword. + +$bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed, $stime, $stop, $time, $unsigned, + Generally supported. + +$dump/$dumpports and related + $dumpfile or $dumpports will create a VCD or FST file (which is based on + the :vlopt:`--trace` option given when the model was Verilated). This + will take effect starting at the next eval() call. If you have multiple + Verilated designs under the same C model, then this will dump signals + only from the design containing the $dumpvars. + + $dumpvars and $dumpports module identifier is ignored; the traced + instances will always start at the top of the design. The levels argument + is also ignored, use tracing_on/tracing_off pragmas instead. + + $dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename + argument is ignored, only a single trace file may be active at once. + + $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and + $dumplimit/$dumpportlimit are currently ignored. + +$error, $fatal, $info, $warning. + Generally supported. + +$exit, $finish, $stop + The rarely used optional parameter to $finish and $stop is ignored. $exit + is aliased to $finish. + +$fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf + Generally supported. + +$fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, $setup, $setuphold, $skew, $timeskew, $width + All specify blocks and timing checks are ignored. + +$random, $urandom, $urandom_range + Use :vlopt:`+verilator+seed+\` runtime option to set the seed if + there is no $random nor $urandom optional argument to set the seed. + There is one random seed per C thread, not per module for $random, nor + per object for random stability of $urandom/$urandom_range. + +$readmemb, $readmemh + Read memory commands are supported. Note Verilator and the Verilog + specification does not include support for readmem to multi-dimensional + arrays. + +$test$plusargs, $value$plusargs + Supported, but the instantiating C++/SystemC wrapper must call + + .. code-block:: C++ + + Verilated::commandArgs(argc, argv); + + to register the command line before calling $test$plusargs or + $value$plusargs. diff --git a/docs/guide/overview.rst b/docs/guide/overview.rst new file mode 100644 index 000000000..2c60dd2b8 --- /dev/null +++ b/docs/guide/overview.rst @@ -0,0 +1,55 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +******** +Overview +******** + +Welcome to Verilator! + +The Verilator package converts Verilog [#]_ and SystemVerilog [#]_ hardware +description language (HDL) designs into a C++ or SystemC model that after +compiling can be executed. Verilator is not a traditional simulator, but a +compiler. + +Verilator is typically used as follows: + +1. The :command:`verilator` executable is invoked with parameters similar +to GCC, or other simulators such as Cadence Verilog-XL/NC-Verilog, or +Synopsys VCS. Verilator reads the specified SystemVerilog code, lints it, +optionally adds coverage and waveform tracing support, and compiles the +design into a source level multithreaded C++ or SystemC "model". The +resulting model's C++ or SystemC code is output as .cpp and .h files. This +is referred to as "Verilating" and the process is "to Verilate"; the output +is a "Verilated" model. + +2. For simulation, a small user written C++ wrapper file is required, the +"wrapper". This wrapper defines the C++ standard function "main()" which +instantiates the Verilated model as a C++/SystemC object. + +3. The user C++ wrapper, the files created by Verilator, a "runtime +library" provided by Verilator, and if applicable SystemC libraries are +then compiled using a C++ compiler to create a simulation executable. + +4. The resulting executable will perform the actual simulation, during +"simulation runtime". + +5. If appropriately enabled, the executable may also generate waveform +traces of the design that may be viewed. It may also create coverage +analysis data for post-analysis. + +The best place to get started is to try the :ref:`Examples`. + + +.. [#] Verilog is defined by the `Institute of Electrical and Electronics + Engineers (IEEE) Standard for Verilog Hardware Description + Language`, Std. 1364, released in 1995, 2001, and 2005. The + Verilator documentation uses the shorthand e.g. "IEEE 1394-2005" to + refer to the e.g. 2005 version of this standard. + +.. [#] SystemVerilog is defined by the `Institute of Electrical and + Electronics Engineers (IEEE) Standard for SystemVerilog - Unified + Hardware Design, Specification, and Verification Language`, Standard + 1800, released in 2005, 2009, 2012, and 2017. The Verilator + documentation uses the shorthand e.g. "IEEE 1800-2017" to refer to + the e.g. 2017 version of this standard. diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst new file mode 100644 index 000000000..e817dae4c --- /dev/null +++ b/docs/guide/simulating.rst @@ -0,0 +1,352 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Simulating: + +************************************ +Simulating (Verilated-Model Runtime) +************************************ + +This section describes items related to simulating, that using a Verilated +model's executable. For the runtime arguments to a simulated model, see +:ref:`Simulation Runtime Arguments`. + + +.. _Benchmarking & Optimization: + +Benchmarking & Optimization +=========================== + +For best performance, run Verilator with the :vlopt:`-O3` +:vlopt:`--x-assign fast <--x-assign>` :vlopt:`--x-initial fast +<--x-initial>` :vlopt:`--noassert <--assert>` options. The :vlopt:`-O3` +option will require longer time to run Verilator, and :vlopt:`--x-assign +fast <--x-assign>` :vlopt:`--x-initial fast <--x-assign>` may increase the +risk of reset bugs in trade for performance; see the above documentation +for these options. + +If using Verilated multithreaded, use ``numactl`` to ensure you are using +non-conflicting hardware resources. See :ref:`Multithreading`. + +Minor Verilog code changes can also give big wins. You should not have any +UNOPTFLAT warnings from Verilator. Fixing these warnings can result in +huge improvements; one user fixed their one UNOPTFLAT warning by making a +simple change to a clock latch used to gate clocks and gained a 60% +performance improvement. + +Beyond that, the performance of a Verilated model depends mostly on your +C++ compiler and size of your CPU's caches. Experience shows that large +models are often limited by the size of the instruction cache, and as such +reducing code size if possible can be beneficial. + +The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT, +OPT_FAST, OPT_SLOW and OPT_GLOBAL variables to control optimization. You +can set these when compiling the output of Verilator with Make, for +example: + +.. code-block:: bash + + make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a + +OPT_FAST specifies optimization options for those parts of the model that +are on the fast path. This is mostly code that is executed every +cycle. OPT_SLOW applies to slow-path code, which executes rarely, often +only once at the beginning or end of simulation. Note that OPT_SLOW is +ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code +will be compiled in a single compilation unit using OPT_FAST. See also the +Verilator :vlopt:`--output-split` option. The OPT_GLOBAL variable applies +to common code in the runtime library used by Verilated models (shipped in +$VERILATOR_ROOT/include). Additional C++ files passed on the verilator +command line use OPT_FAST. The OPT variable applies to all compilation +units in addition to the specific "OPT" variables described above. + +You can also use the :vlopt:`-CFLAGS` and/or :vlopt:`-LDFLAGS` options on +the verilator command line to pass arguments directly to the compiler or +linker. + +The default values of the "OPT" variables are chosen to yield good +simulation speed with reasonable C++ compilation times. To this end, +OPT_FAST is set to "-Os" by default. Higher optimization such as "-O2" or +"-O3" may help (though often they provide only a very small performance +benefit), but compile times may be excessively large even with medium sized +designs. Compilation times can be improved at the expense of simulation +speed by reducing optimization, for example with OPT_FAST="-O0". Often good +simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing" but +with improved compilation times. Files controlled by OPT_SLOW have little +effect on performance and therefore OPT_SLOW is empty by default +(equivalent to "-O0") for improved compilation speed. In common use-cases +there should be little benefit in changing OPT_SLOW. OPT_GLOBAL is set to +"-Os" by default and there should rarely be a need to change it. As the +runtime library is small in comparison to a lot of Verilated models, +disabling optimization on the runtime library should not have a serious +effect on overall compilation time, but may have detrimental effect on +simulation speed, especially with tracing. In addition to the above, for +best results use OPT="-march=native", the latest Clang compiler (about 10% +faster than GCC), and link statically. + +Generally the answer to which optimization level gives the best user +experience depends on the use case and some experimentation can pay +dividends. For a speedy debug cycle during development, especially on large +designs where C++ compilation speed can dominate, consider using lower +optimization to get to an executable faster. For throughput oriented use +cases, for example regressions, it is usually worth spending extra +compilation time to reduce total CPU time. + +If you will be running many simulations on a single model, you can +investigate profile guided optimization. With GCC, using GCC's +"-fprofile-arcs", then GCC's "-fbranch-probabilities" will yield another +15% or so. + +Modern compilers also support link-time optimization (LTO), which can help +especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in +both compilation and link. Note LTO may cause excessive compile times on +large designs. + +Unfortunately, using the optimizer with SystemC files can result in +compilation taking several minutes. (The SystemC libraries have many little +inlined functions that drive the compiler nuts.) + +If you are using your own makefiles, you may want to compile the Verilated +code with ``--MAKEFLAGS -DVL_INLINE_OPT=inline``. This will inline +functions, however this requires that all cpp files be compiled in a single +compiler run. + +You may uncover further tuning possibilities by profiling the Verilog code. +See :ref:`profiling`. + +When done optimizing, please let the author know the results. We like to +keep tabs on how Verilator compares, and may be able to suggest additional +improvements. + + +.. _Coverage Analysis: + +Coverage Analysis +================= + +Verilator supports adding code to the Verilated model to support +SystemVerilog code coverage. With :vlopt:`--coverage`, Verilator enables +all forms of coverage: + +* :ref:`User Coverage` +* :ref:`Line Coverage` +* :ref:`Toggle Coverage` + +When a model with coverage is executed, it will create a coverage file for +collection and later analysis, see :ref:`Coverage Collection`. + + +.. _User Coverage: + +Functional Coverage +------------------- + +With :vlopt:`--coverage` or :vlopt:`--coverage-user`, Verilator will +translate functional coverage points which the user has inserted manually +into the SystemVerilog design, into the Verilated model. + +Currently, all functional coverage points are specified using SystemVerilog +assertion syntax which must be separately enabled with :vlopt:`--assert`. + +For example, the following SystemVerilog statement will add a coverage +point, under the coverage name "DefaultClock": + +.. code-block:: sv + + DefaultClock: cover property (@(posedge clk) cyc==3); + + +.. _Line Coverage: + +Line Coverage +------------- + +With :vlopt:`--coverage` or :vlopt:`--coverage-line`, Verilator will +automatically add coverage analysis at each code flow change point (e.g. at +branches). At each such branch a unique counter is incremented. At the +end of a test, the counters along with the filename and line number +corresponding to each counter are written into the coverage file. + +Verilator automatically disables coverage of branches that have a $stop in +them, as it is assumed $stop branches contain an error check that should +not occur. A :option:`/*verilator&32;coverage_block_off*/` metacomment +will perform a similar function on any code in that block or below, or +:option:`/*verilator&32;coverage_off*/` and +:option:`/*verilator&32;coverage_on*/` will disable and enable coverage +respectively around a block of code. + +Verilator may over-count combinatorial (non-clocked) blocks when those +blocks receive signals which have had the UNOPTFLAT warning disabled; for +most accurate results do not disable this warning when using coverage. + + +.. _Toggle Coverage: + +Toggle Coverage +--------------- + +With :vlopt:`--coverage` or :vlopt:`--coverage-toggle`, Verilator will +automatically add toggle coverage analysis into the Verilated model. + +Every bit of every signal in a module has a counter inserted. The counter +will increment on every edge change of the corresponding bit. + +Signals that are part of tasks or begin/end blocks are considered local +variables and are not covered. Signals that begin with underscores (see +:vlopt:`--coverage-underscore`), are integers, or are very wide (>256 bits +total storage across all dimensions, see :vlopt:`--coverage-max-width`) are +also not covered. + +Hierarchy is compressed, such that if a module is instantiated multiple +times, coverage will be summed for that bit across **all** instantiations +of that module with the same parameter set. A module instantiated with +different parameter values is considered a different module, and will get +counted separately. + +Verilator makes a minimally-intelligent decision about what clock domain +the signal goes to, and only looks for edges in that clock domain. This +means that edges may be ignored if it is known that the edge could never be +seen by the receiving logic. This algorithm may improve in the future. +The net result is coverage may be lower than what would be seen by looking +at traces, but the coverage is a more accurate representation of the +quality of stimulus into the design. + +There may be edges counted near time zero while the model stabilizes. It's +a good practice to zero all coverage just before releasing reset to prevent +counting such behavior. + +A :option:`/*verilator&32;coverage_off*/` +:option:`/*verilator&32;coverage_on*/` metacomment pair can be used around +signals that do not need toggle analysis, such as RAMs and register files. + + +.. _Coverage Collection: + +Coverage Collection +------------------- + +When any coverage flag was used to Verilate, Verilator will add appropriate +coverage point insertions into the model and collect the coverage data. + +To get the coverage data from the model, in the user wrapper code, +typically at the end once a test passes, call +:code:`Verilated::coveragep()->write` with an argument of the filename for +the coverage data file to write coverage data to (typically +"logs/coverage.dat"). + +Run each of your tests in different directories, potentially in parallel. +Each test will create a :file:`logs/coverage.dat` file. + +After running all of the tests, execute the :command:`verilator_coverage` +command, passing arguments pointing to the filenames of all of the +individual coverage files. :command:`verilator_coverage` will reads the +:file:`logs/coverage.dat` file(s), and create an annotated source code +listing showing code coverage details. + +:command:`verilator_coverage` may also be used for test grading, that is +computing which tests are important to fully cover the design. + +For an example, see the :file:`examples/make_tracing_c/logs` directory. +Grep for lines starting with '%' to see what lines Verilator believes need +more coverage. + +Additional options of :command:`verilator_coverage` allow for merging of +coverage data files or other transformations. + +Info files can be written by verilator_coverage for import to +:command:`lcov`. This enables use of :command:`genhtml` for HTML reports +and importing reports to sites such as `https://codecov.io +`_. + + +.. _Profiling: + +Code Profiling +============== + +The Verilated model may be code-profiled using GCC or Clang's C++ profiling +mechanism. Verilator provides additional flags to help map the resulting +C++ profiling results back to the original Verilog code responsible for the +profiled C++ code functions. + +To use profiling: + +#. Use Verilator's :vlopt:`--prof-cfuncs`. +#. Use Verilator's :vlopt:`-CFLAGS "-g -pg" <-CFLAGS>` to pass the + profiling flags through to GCC/Clang. +#. Build and run the simulation model. +#. The model will create gmon.out. +#. Run :command:`gprof` to see where in the C++ code the time is spent. +#. Run the gprof output through the :command:`verilator_profcfunc` program + and it will tell you what Verilog line numbers on which most of the time + is being spent. + + +.. _Thread Profiling: + +Thread Profiling +================ + +When using multithreaded mode (:vlopt:`--threads`), it is useful to see +statistics and visualize how well the multiple CPUs are being utilized. + +With the :vlopt:`--prof-threads` option, Verilator will: + +* Add code to the Verilated model to record the start and end time of each + macro-task across a number of calls to eval. (What is a macro-task? See + the Verilator internals document (:file:`docs/internals.rst` in the + distribution.) + +* Add code to save profiling data in non-human-friendly form to the file + specified with :vlopt:`+verilator+prof+threads+file+\`. + +The :command:`verilator_gantt` program may then be run to transform the +saved profiling file into a nicer visual format and produce some related +statistics. + +.. figure:: ../_static/fig_gantt_min.png + + Example verilator_gantt output, as viewed with GTKWave. + + The parallelism shows the number of CPUs being used at a given moment. + + The cpu_thread section shows which thread is executing on each of the physical CPUs. + + The thread_mtask section shows which macro-task is running on a given thread. + +For more information see :command:`verilator_gantt`. + +.. _Save/Restore: + +Save/Restore +============ + +The intermediate state of a Verilated model may be saved, so that it may +later be restored. + +To enable this feature, use :vlopt:`--savable`. There are limitations in +what language features are supported along with :vlopt:`--savable`; if you +attempt to use an unsupported feature Verilator will throw an error. + +To use save/restore, the user wrapper code must create a VerilatedSerialize +or VerilatedDeserialze object then calling the :code:`<<` or :code:`>>` +operators on the generated model and any other data the process needs +saved/restored. These functions are not thread safe, and are typically +called only by a main thread. + +For example: + +.. code-block:: C++ + + void save_model(const char* filenamep) { + VerilatedSave os; + os.open(filenamep); + os << main_time; // user code must save the timestamp, etc + os << *topp; + } + void restore_model(const char* filenamep) { + VerilatedRestore os; + os.open(filenamep); + os >> main_time; + os >> *topp; + } diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst new file mode 100644 index 000000000..53810b67e --- /dev/null +++ b/docs/guide/verilating.rst @@ -0,0 +1,482 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +********** +Verilating +********** + +Verilator may be used in five major ways: + +* With the :vlopt:`--cc` or :vlopt:`--sc` options, Verilator will translate + the design into C++ or SystemC code respectively. See :ref:`C++ and + SystemC Generation`. + +* With the :vlopt:`--lint-only` option, Verilator will lint the design to + check for warnings but will not typically create any output files. + +* With the :vlopt:`--xml-only` option, Verilator will create XML output + that may be used to feed into other user-designed tools. See + :file:`docs/xml.rst` in the distribution. + +* With the :vlopt:`-E` option, Verilator will preprocess the code according + to IEEE preprocessing rules, and write the output to standard out. This + is useful to feed other tools, and to debug how "\`define" statements are + expanded. + + +.. _C++ and SystemC Generation: + +C++ and SystemC Generation +========================== + +Verilator will translate a SystemVerilog design into C++ with the +:vlopt:`--cc` option, or into SystemC with the :vlopt:`--sc` option. + +When using these options: + +#. Verilator reads the input Verilog code, determines all "top modules" that + is modules or programs that are not used as instances under other cells. + If :vlopt:`--top-module` is used, then that determines the top module and + all other top modules are removed, otherwise a :vlopt:`MULTITOP` warning + is given. + +#. Verilator writes the C++/SystemC code to output files into the + :vlopt:`--Mdir` option-specified directory, or defaults to "obj_dir". + The prefix is set with :vlopt:`--prefix`, or defaults to the name of the + top module. + +#. If :vlopt:`--exe` is used, Verilator creates makefiles to generate a + simulation executable, otherwise it creates makefiles to generate an + archive (.a) containing the objects. + +#. If :vlopt:`--build` option was used, it calls :ref:`GNU Make` or + :ref:`CMake` to build the model. + +Once a model is built it is then typically run, see :ref:`Simulating`. + + +.. _Hierarchical Verilation: + +Hierarchical Verilation +======================= + +Large designs may take long (e.g. 10+ minutes) and huge memory (e.g. 100+ +GB) to Verilate. In hierarchical mode, the user manually selects some +large lower-level hierarchy blocks to separate from the larger design. For +example a core may be the hierarchy block, and separated out of a +multi-core SoC. + +Verilator is run in hierarchical mode on the whole SoC. Verilator will +make two models, one for the CPU hierarchy block, and one for the SoC. The +Verialted code for the SoC will automatically call the CPU Verilated model. + +The current hierarchical Verilation is based on protect-lib. Each hierarchy +block is Verilated to a protect-lib. User modules of the hierarchy blocks +will see a tiny wrapper generated by protect-lib instead of the actual +design. + + +Usage +----- + +Users need to mark one or more moderate size module as hierarchy block(s). +There are two ways to mark a module: + +* Write :option:`/*verilator&32;hier_block*/` metacomment in HDL code. + +* Add a :option:`hier_block` line in a the :ref:`Configuration Files`. + +Then pass the :vlopt:`--hierarchical` option to Verilator + +Compilation is the same as when not using hierarchical mode. + +.. code-block:: bash + + make -C obj_dir -f Vtop_module_name.mk + + +Limitations +----------- + +Hierarchy blocks have some limitations including: + +* The hierarchy block cannot be accessed using dot (.) from upper module(s) + or other hierarchy blocks. + +* Signals in the block cannot be traced. + +* Modport cannot be used at the hierarchical block boundary. + +* The simulation speed is likely to not be as fast as flat Verilation, in + which all modules are globally scheduled. + +* Generated clocks may not work correctly if they are generated in the + hierarchical model and pass up into another hierarchical model or the top + module. + +But, the following usage is supported: + +* Nested hierarchy blocks. A hierarchy block may instantiate other + hierarchy blocks. + +* Parameterized hierarchy block. Parameters of a hierarchy block can be + overridden using :code:`#(.param_name(value))` construct. + + +.. _Overlapping Verilation and Compilation: + +Overlapping Verilation and Compilation +-------------------------------------- + +Verilator needs to run 2 + *N* times in hierarchical Verilation, where *N* +is the number of hierarchy blocks. One of the two is for the top module +which refers wrappers of all other hierarchy blocks. The second one of the +two is the initial run that searches modules marked with +:option:`/*verilator&32;hier_block*/` metacomment and creates a plan and +write in :file:`{prefix}_hier.mk`. This initial run internally invokes +other *N* + 1 runs, so you don't have to care about these *N* + 1 times of +run. The additional *N* is the Verilator run for each hierarchical block. + +If ::vlopt:`-j {jobs} <-j>` option is specified, Verilation for hierarchy +blocks runs in parallel. + +If :vlopt:`--build` option is specified, C++ compilation also runs as soon +as a hierarchy block is Verilated. C++ compilation and Verilation for other +hierarchy blocks run simultaneously. + + +Cross Compilation +================= + +Verilator supports cross-compiling Verilated code. This is generally used +to run Verilator on a Linux system and produce C++ code that is then compiled +on Windows. + +Cross compilation involves up to three different OSes. The build system is +where you configured and compiled Verilator, the host system where you run +Verilator, and the target system where you compile the Verilated code and +run the simulation. + +Currently, Verilator requires the build and host system type to be the +same, though the target system type may be different. To support this, +:command:`./configure` and make Verilator on the build system. Then, run +Verilator on the host system. Finally, the output of Verilator may be +compiled on the different target system. + +To support this, none of the files that Verilator produces will reference +any configure generated build-system specific files, such as +:file:`config.h` (which is renamed in Verilator to :file:`config_build.h` +to reduce confusion.) The disadvantage of this approach is that +:file:`include/verilatedos.h` must self-detect the requirements of the +target system, rather than using configure. + +The target system may also require edits to the Makefiles, the simple +Makefiles produced by Verilator presume the target system is the same type +as the build system. + + +.. _Multithreading: + +Multithreading +============== + +Verilator supports multithreaded simulation models. + +With :vlopt:`--no-threads`, the default, the model is not thread safe, and +any use of more than one thread calling into one or even different +Verilated models may result in unpredictable behavior. This gives the +highest single thread performance. + +With :vlopt:`--threads 1 <--threads>`, the generated model is single +threaded, however the support libraries are multithread safe. This allows +different instantiations of model(s) to potentially each be run under a +different thread. All threading is the responsibility of the user's C++ +testbench. + +With :vlopt:`--threads {N} <--threads>`, where N is at least 2, the +generated model will be designed to run in parallel on N threads. The +thread calling eval() provides one of those threads, and the generated +model will create and manage the other N-1 threads. It's the client's +responsibility not to oversubscribe the available CPU cores. Under CPU +oversubscription, the Verilated model should not livelock nor deadlock, +however, you can expect performance to be far worse than it would be with +proper ratio of threads and CPU cores. + +The remainder of this section describe behavior with :vlopt:`--threads 1 +<--threads>` or :vlopt:`--threads {N} <--threads>` (not +:vlopt:`--no-threads`). + +:code:`VL_THREADED` is defined in the C++ code when compiling a threaded +Verilated module, causing the Verilated support classes become threadsafe. + +The thread used for constructing a model must be the same thread that calls +:code:`eval()` into the model, this is called the "eval thread". The thread +used to perform certain global operations such as saving and tracing must +be done by a "main thread". In most cases the eval thread and main thread +are the same thread (i.e. the user's top C++ testbench runs on a single +thread), but this is not required. + +The :vlopt:`--trace-threads` options can be used to produce trace dumps +using multiple threads. If :vlopt:`--trace-threads` is set without +:vlopt:`--threads`, then :vlopt:`--trace-threads` will imply +:vlopt:`--threads 1 <--threads>`, i.e.: the support libraries will be +thread safe. + +With :vlopt:`--trace-threads 0 <--trace-threads>`, trace dumps are produced +on the main thread. This again gives the highest single thread performance. + +With :vlopt:`--trace-threads {N} <--trace-threads>`, where N is at least 1, +N additional threads will be created and managed by the trace files (e.g.: +VerilatedVcdC or VerilatedFstC), to generate the trace dump. The main +thread will be released to proceed with execution as soon as possible, +though some blocking of the main thread is still necessary while capturing +the trace. Different trace formats can utilize a various number of +threads. See the :vlopt:`--trace-threads` option. + +When running a multithreaded model, the default Linux task scheduler often +works against the model, by assuming threads are short lived, and thus +often schedules threads using multiple hyperthreads within the same +physical core. For best performance use the :command:`numactl` program to +(when the threading count fits) select unique physical cores on the same +socket. The same applies for :vlopt:`--trace-threads` as well. + +As an example, if a model was Verilated with :vlopt:`--threads 4 +<--threads>`, we consult: + +.. code-block:: bash + + egrep 'processor|physical id|core id' /proc/cpuinfo + +To select cores 0, 1, 2, and 3 that are all located on the same socket (0) +but different physical cores. (Also useful is :command:`numactl +--hardware`, or :command:`lscpu` but those doesn't show Hyperthreading +cores.) Then we execute: + +.. code-block:: bash + + numactl -m 0 -C 0,1,2,3 -- verilated_executable_name + +This will limit memory to socket 0, and threads to cores 0, 1, 2, 3, +(presumably on socket 0) optimizing performance. Of course this must be +adjusted if you want another simulator using e.g. socket 1, or if you +Verilated with a different number of threads. To see what CPUs are +actually used, use :vlopt:`--prof-threads`. + + +Multithreaded Verilog and Library Support +----------------------------------------- + +$display/$stop/$finish are delayed until the end of an eval() call in order +to maintain ordering between threads. This may result in additional tasks +completing after the $stop or $finish. + +If using :vlopt:`--coverage`, the coverage routines are fully thread safe. + +If using the DPI, Verilator assumes pure DPI imports are thread safe, +balancing performance versus safety. See :vlopt:`--threads-dpi`. + +If using :vlopt:`--savable`, the save/restore classes are not multithreaded +and must be called only by the eval thread. + +If using :vlopt:`--sc`, the SystemC kernel is not thread safe, therefore +the eval thread and main thread must be the same. + +If using :vlopt:`--trace`, the tracing classes must be constructed and +called from the main thread. + +If using :vlopt:`--vpi`, since SystemVerilog VPI was not architected by +IEEE to be multithreaded, Verilator requires all VPI calls are only made +from the main thread. + + +.. _GNU Make: + +GNU Make +======== + +Verilator defaults to creating GNU Make makefiles for the model. Verilator +will call make automatically when the :vlopt:'--build' option is used. + +If calling Verilator from a makefile, the :vlopt:'-MMD' option will create +a dependency file which will allow Make to only run Verilator if input +Verilog files change. + +.. _CMake: + +CMake +===== + +Verilator can be run using CMake, which takes care of both running +Verilator and compiling the output. There is a CMake example in the +examples/ directory. The following is a minimal CMakeLists.txt that would +build the code listed in :ref:`Example C++ Execution` + +.. code-block:: CMake + + project(cmake_example) + find_package(verilator HINTS $ENV{VERILATOR_ROOT}) + add_executable(Vour sim_main.cpp) + verilate(Vour SOURCES our.v) + +:code:`find_package` will automatically find an installed copy of +Verilator, or use a local build if VERILATOR_ROOT is set. + +It is recommended to use CMake >= 3.12 and the Ninja generator, though +other combinations should work. To build with CMake, change to the folder +containing CMakeLists.txt and run: + +.. code-block:: bash + + mkdir build + cd build + cmake -GNinja .. + ninja + +Or to build with your system default generator: + +.. code-block:: bash + + mkdir build + cd build + cmake .. + cmake --build . + +If you're building the example you should have an executable to run: + +.. code-block:: bash + + ./Vour + +The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and +VERILATOR_BIN to the appropriate values, and also creates a verilate() +function. verilate() will automatically create custom commands to run +Verilator and add the generated C++ sources to the target specified. + +Verilate in CMake +----------------- + +.. code-block:: CMake + + verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name] + [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE] + [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...] + [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...]) + +Lowercase and ... should be replaced with arguments, the uppercase parts +delimit the arguments and can be passed in any order, or left out entirely +if optional. + +verilate(target ...) can be called multiple times to add other Verilog +modules to an executable or library target. + +When generating Verilated SystemC sources, you should also include the +SystemC include directories and link to the SystemC libraries. + +.. describe:: target + + Name of a target created by add_executable or add_library. + +.. describe:: COVERAGE + + Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS + --coverage" + +.. describe:: DIRECTORY + + Optional. Set the verilator output directory. It is preferable to use + the default, which will avoid collisions with other files. + +.. describe:: INCLUDE_DIRS + + Optional. Sets directories that Verilator searches (same as -y). + +.. describe:: OPT_SLOW + + Optional. Set compiler options for the slow path. You may want to reduce + the optimization level to improve compile times with large designs. + +.. describe:: OPT_FAST + + Optional. Set compiler options for the fast path. + +.. describe:: OPT_GLOBAL + + Optional. Set compiler options for the common runtime library used by + Verilated models. + +.. describe:: PREFIX + + Optional. Sets the Verilator output prefix. Defaults to the name of the + first source file with a "V" prepended. Must be unique in each call to + verilate(), so this is necessary if you build a module multiple times + with different parameters. Must be a valid C++ identifier, i.e. contains + no white space and only characters A-Z, a-z, 0-9 or _. + +.. describe:: SOURCES + + List of Verilog files to Verilate. Must have at least one file. + +.. describe:: SYSTEMC + + Optional. Enables SystemC mode, defaults to C++ if not specified. + + When using Accellera's SystemC with CMake support, a CMake target is + available that simplifies the SystemC steps. This will only work if the + SystemC installation can be found by CMake. This can be configured by + setting the CMAKE_PREFIX_PATH variable during CMake configuration. + + Don't forget to set the same C++ standard for the Verilated sources as + the SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS + environment variable. + +.. describe:: TOP_MODULE + + Optional. Sets the name of the top module. Defaults to the name of the + first file in the SOURCES array. + +.. describe:: TRACE + + Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS + --trace". + +.. describe:: TRACE_FST + + Optional. Enables FST tracing if present, equivalent to "VERILATOR_ARGS + --trace-fst". + +.. describe:: VERILATOR_ARGS + + Optional. Extra arguments to Verilator. Do not specify :vlopt:`--Mdir` + or :vlopt:`--prefix` here, use DIRECTORY or PREFIX. + + +SystemC Link in CMake +--------------------- + +Verilator's CMake support provides a convenience function to automatically +find and link to the SystemC library. It can be used as: + +.. code-block:: CMake + + verilator_link_systemc(target) + +where target is the name of your target. + +The search paths can be configured by setting some variables: + +.. describe:: SYSTEMC_INCLUDE + + Sets the direct path to the SystemC includes. + +.. describe:: SYSTEMC_LIBDIR + + Sets the direct path to the SystemC libraries. + +.. describe:: SYSTEMC_ROOT + + Sets the installation prefix of an installed SystemC library. + +.. describe:: SYSTEMC + + Sets the installation prefix of an installed SystemC library. (Same as + SYSTEMC_ROOT). diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst new file mode 100644 index 000000000..2e79f4e62 --- /dev/null +++ b/docs/guide/warnings.rst @@ -0,0 +1,1585 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +******************* +Errors and Warnings +******************* + + +Disabling Warnings +================== + +Warnings may be disabled in multiple ways: + +#. Disable the warning in the source code. When the warning is printed it + will include a warning code. Simply surround the offending line with a + :code:`/*verilator&32;lint_off*/` and :code:`/*verilator&32;lint_on*/` + metacomment pair: + + .. code-block:: sv + + // verilator lint_off UNSIGNED + if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop; + // verilator lint_on UNSIGNED + +#. Disable the warning using :ref:`Configuration Files` with a + :option:`lint_off` command. This is useful when a script is suppressing + warnings and the Verilog source should not be changed. This method also + allows matching on the warning text. + + .. code-block:: sv + + lint_off -rule UNSIGNED -file "*/example.v" -line 1 + +#. Disable the warning globally invoking Verilator with the + :code:`-Wno-{warning-code}` option. This should be avoided, as it + removes all checking across the designs, and prevents other users from + compiling your code without knowing the magic set of disables needed to + successfully compile your design. + + +Error And Warning Format +======================== + +Warnings and errors printed by Verilator always match this regular +expression: + +.. code-block:: + + %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.* + + +Errors and warning start with a percent sign (historical heritage from +Digital Equipment Corporation). Some errors or warning have a code +attached, with meanings described below. Some errors also have a filename, +line number and optional column number (starting at column 1 to match GCC). + +Following the error message, Verilator will typically show the user's +source code corresponding to the error, prefixed by the line number and a " +| ". Following this is typically an arrow and ~ pointing at the error on +the source line directly above. + + +List Of Warnings +================ + +.. option:: Internal Error + + This error should never occur first, though may occur if earlier + warnings or error messages have corrupted the program. If there are no + other warnings or errors, submit a bug report. + + +.. option:: Unsupported: .... + + This error indicates that the code is using a Verilog language construct + that is not yet supported in Verilator. See the Limitations chapter. + + +.. option:: ALWCOMBORDER + + .. TODO better example + + Warns that an :code:`always_comb` block has a variable which is set + after it is used. This may cause simulation-synthesis mismatches, as + not all simulators allow this ordering. + + .. code-block:: sv + + always_comb begin + a = b; + b = 1; + end + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: ASSIGNDLY + + .. TODO better example + + Warns that the code has an assignment statement with a delayed time in + front of it, for example: + + .. code-block:: sv + + a <= #100 b; + assign #100 a = b; + + Ignoring this warning may make Verilator simulations differ from other + simulators, however at one point this was a common style so disabled by + default as a code style warning. + + +.. option:: ASSIGNIN + + .. TODO better example + + Error that an assignment is being made to an input signal. This is + almost certainly a mistake, though technically legal. + + .. code-block:: sv + + input a; + assign a = 1'b1; + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: BLKANDNBLK + + .. TODO better example + + BLKANDNBLK is an error that a variable comes from a mix of blocking and + non-blocking assignments. + + This is not illegal in SystemVerilog, but a violation of good coding + practice. Verilator reports this as an error, because ignoring this + warning may make Verilator simulations differ from other simulators. + + It is generally safe to disable this error (with a :code:`// verilator + lint_off BLKANDNBLK` metacomment or the :code:`-Wno-BLKANDNBLK` option) + when one of the assignments is inside a public task, or when the + blocking and non-blocking assignments have non-overlapping bits and + structure members. + + Generally, this is caused by a register driven by both combo logic and a + flop: + + .. code-block:: sv + + logic [1:0] foo; + always @(posedge clk) foo[0] <= ... + always_comb foo[1] = ... + + Simply use a different register for the flop: + + .. code-block:: sv + + logic [1:0] foo; + always @(posedge clk) foo_flopped[0] <= ... + always_comb foo[0] = foo_flopped[0]; + always_comb foo[1] = ... + + Or, this may also avoid the error: + + .. code-block:: sv + + logic [1:0] foo /*verilator split_var*/; + + +.. option:: BLKLOOPINIT + + .. TODO better example + + This indicates that the initialization of an array needs to use + non-delayed assignments. This is done in the interest of speed; if + delayed assignments were used, the simulator would have to copy large + arrays every cycle. (In smaller loops, loop unrolling allows the + delayed assignment to work, though it's a bit slower than a non-delayed + assignment.) Here's an example + + .. code-block:: sv + + always @(posedge clk) + if (~reset_l) + for (i=0; i<`ARRAY_SIZE; i++) + array[i] = 0; // Non-delayed for verilator + + + This message is only seen on large or complicated loops because + Verilator generally unrolls small loops. You may want to try increasing + :vlopt:`--unroll-count` (and occasionally :vlopt:`--unroll-stmts`) which + will raise the small loop bar to avoid this error. + + +.. option:: BLKSEQ + + .. TODO better example + + This indicates that a blocking assignment (=) is used in a sequential + block. Generally non-blocking/delayed assignments (<=) are used in + sequential blocks, to avoid the possibility of simulator races. It can + be reasonable to do this if the generated signal is used ONLY later in + the same block, however this style is generally discouraged as it is + error prone. + + .. code-block:: sv + + always @(posedge clk) foo = ...; //<--- Warning + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Other tools with similar warnings: Verible's always-ff-non-blocking, + "Use only non-blocking assignments inside 'always_ff' sequential + blocks." + + +.. option:: BSSPACE + + .. TODO better example + + Warns that a backslash is followed by a space then a newline. Likely the + intent was to have a backslash directly followed by a newline (e.g. when + making a "\`define") and there's accidentally white space at the end of + the line. If the space is not accidental, suggest removing the + backslash in the code as it serves no function. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASEINCOMPLETE + + .. TODO better example + + Warns that inside a case statement there is a stimulus pattern for which + there is no case item specified. This is bad style, if a case is + impossible, it's better to have a :code:`default: $stop;` or just + :code:`default: ;` so that any design assumption violations will be + discovered in simulation. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASEOVERLAP + + .. TODO better example + + Warns that inside a case statement has case values which are detected to + be overlapping. This is bad style, as moving the order of case values + will cause different behavior. Generally the values can be respecified + to not overlap. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASEWITHX + + .. TODO better example + + Warns that a case statement contains a constant with a ``x`` . + Verilator is two-state so interpret such items as always false. Note a + common error is to use a ``X`` in a case or casez statement item; often + what the user instead intended is to use a casez with ``?`` . + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASEX + + .. TODO better example + + Warns that it is simply better style to use casez, and "?" in place of + "x"'s. See + `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf + `_ + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASTCONST + + .. TODO better example + + Warns that a dynamic cast ($cast) is unnecessary as the $cast will + always succeed or fail. If it will always fail, the $cast is + useless. If it will always succeed a static cast may be preferred. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. On other simulators, not fixing CASTCONST may + result in decreased performance. + + +.. option:: CDCRSTLOGIC + + With :vlopt:`--cdc` only, warns that asynchronous flop reset terms come + from other than primary inputs or flopped outputs, creating the + potential for reset glitches. + + +.. option:: CLKDATA + + .. TODO better example + + Warns that clock signal is mixed used with/as data signal. The checking + for this warning is enabled only if user has explicitly marked some + signal as clocker using command line option or in-source meta comment + (see :vlopt:`--clk`). + + The warning can be disabled without affecting the simulation result. But + it is recommended to check the warning as this may degrade the + performance of the Verilated model. + + +.. option:: CMPCONST + + .. TODO better example + + Warns that the code is comparing a value in a way that will always be + constant. For example :code:`X > 1` will always be true when X is a + single bit wide. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: COLONPLUS + + Warns that a :code:`:+` is seen. Likely the intent was to use :code:`+:` + to select a range of bits. If the intent was a range that is explicitly + positive, suggest adding a space, e.g. use :code:`: +`. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: COMBDLY + + .. TODO better example + + Warns that there is a delayed assignment inside of a combinatorial + block. Using delayed assignments in this way is considered bad form, + and may lead to the simulator not matching synthesis. If this message + is suppressed, Verilator, like synthesis, will convert this to a + non-delayed assignment, which may result in logic races or other + nasties. See + `http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf + `_ + + Ignoring this warning may make Verilator simulations differ from other + simulators. + + +.. option:: CONTASSREG + + .. TODO better example + + Error that a continuous assignment is setting a reg. According to IEEE + Verilog, but not SystemVerilog, a wire must be used as the target of + continuous assignments. + + This error is only reported when :vlopt:`--language 1364-1995 + <--language>`, :vlopt:`--language 1364-2001 <--language>`, or + :vlopt:`--language 1364-2005 <--language>` is used. + + Ignoring this error will only suppress the lint check, it will simulate + correctly. + + +.. option:: DECLFILENAME + + .. TODO better example + + Warns that a module or other declaration's name doesn't match the + filename with path and extension stripped that it is declared in. The + filename a modules/interfaces/programs is declared in should match the + name of the module etc. so that :vlopt:`-y` option directory searching + will work. This warning is printed for only the first mismatching + module in any given file, and :vlopt:`-v` library files are ignored. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: DEFPARAM + + Warns that the :code:`defparam` statement was deprecated in Verilog 2001 + and all designs should now be using the :code:`#(...)` format to specify + parameters. + + Defparams may be defined far from the instantiation that is affected by + the defparam, affecting readability. Defparams have been formally + deprecated since IEEE 1800-2005 25.2 and may not work in future language + versions. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 5 + + module parameterized + #(parameter int MY_PARAM = 0); + endmodule + module upper; + defparam p0.MY_PARAM = 1; //<--- Warning + parameterized p0(); + endmodule + + Results in: + + .. code-block:: + + %Warning-DEFPARAM: example.v:5:15: defparam is deprecated (IEEE 1800-2017 C.4.1) + : ... Suggest use instantiation with #(.MY_PARAM(...etc...)) + + To repair use :code:`#(.PARAMETER(...))` syntax. Repaired Example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 6 + + module parameterized + #(parameter int MY_PARAM = 0); + endmodule + module upper + parameterized + #(.MY_PARAM(1)) //<--- Repaired + p0(); + endmodule + + Other tools with similar warnings: Veriable's forbid_defparam_rule. + + +.. option:: DETECTARRAY + + .. TODO better example + + Error when Verilator tries to deal with a combinatorial loop that could + not be flattened, and which involves a datatype which Verilator cannot + handle, such as an unpacked struct or a large unpacked array. This + typically occurs when :vlopt:`-Wno-UNOPTFLAT ` has been used + to override an UNOPTFLAT warning (see below). + + The solution is to break the loop, as described for UNOPTFLAT. + + +.. option:: DIDNOTCONVERGE + + Error at simulation runtime when model did not properly settle. + + Verilator sometimes has to evaluate combinatorial logic multiple times, + usually around code where a UNOPTFLAT warning was issued, but disabled. + + Faulty example: + + .. code-block:: sv + + always_comb b = ~a; + always_comb a = b + + This code will toggle forever, and thus to prevent an infinite loop, the + executable will give the didn't converge error. + + To debug this, first review any UNOPTFLAT warnings that were ignored. + Though typically it is safe to ignore UNOPTFLAT (at a performance cost), + at the time of issuing a UNOPTFLAT Verilator did not know if the logic + would eventually converge and assumed it would. + + Next, run Verilator with :vlopt:`--prof-cfuncs -CFLAGS -DVL_DEBUG + <--prof-cfuncs>`. Rerun the test. Now just before the convergence + error you should see additional output similar to this: + + .. code-block:: + + CHANGE: filename.v:1: b + CHANGE: filename.v:2: a + + This means that signal b and signal a keep changing, inspect the code + that modifies these signals. Note if many signals are getting printed + then most likely all of them are oscillating. It may also be that + e.g. "a" may be oscillating, then "a" feeds signal "c" which then is + also reported as oscillating. + + One way DIDNOTCONVERGE may occur is flops are built out of gate + primitives. error. Verilator does not support building flops or latches + out of gate primitives, and any such code must change to use behavioral + constructs (e.g. always_ff and always_latch). + + Finally, rare, more difficult cases can be debugged like a C++ program; + either enter :command:`gdb` and use its tracing facilities, or edit the + generated C++ code to add appropriate prints to see what is going on. + + +.. option:: ENDLABEL + + Warns that a label attached to a "end"-something statement does not + match the label attached to the block start. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + module mine; + endmodule : not_mine //<--- Warning + + Results in: + + .. code-block:: + + %Warning-ENDLABEL: example.v:2:13: End label 'not_mine' does not match begin label 'mine' + + To repair either fix the end label's name, or remove entirely. + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + module mine; + endmodule : mine //<--- Repaired + + Other tools with similar warnings: Verible's mismatched-labels, + "Begin/end block labels must match." or "Matching begin label is + missing." + + +.. option:: EOFNEWLINE + + Warns that a file does not end in a newline. POSIX defines that a line + must end in newline, as otherwise for example :command:`cat` with the + file as an argument may produce undesirable results. + + Repair by adding a newline to the end of the file. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Other tools with similar warnings: Verible's posix-eof, "File must end + with a newline." + + +.. option:: GENCLK + + Deprecated and no longer used as a warning. Used to indicate that the + specified signal was is generated inside the model, and also being used + as a clock. + + +.. option:: HIERBLOCK + + Warns that the top module is marked as a hierarchy block by the + :option:`/*verilator&32;hier_block*/` metacomment, which is not legal. + This setting on the top module will be ignored. + + +.. option:: IFDEPTH + + Warns that if/if else statements have exceeded the depth specified with + :vlopt:`--if-depth`, as they are likely to result in slow priority + encoders. Statements below unique and priority if statements are + ignored. Solutions include changing the code to a case statement, or a + SystemVerilog :code:`unique if` or :code:`priority if`. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: IGNOREDRETURN + + Warns that a non-void function is being called as a task, and hence the + return value is being ignored. This warning is required by IEEE. + + .. code-block:: sv + :linenos: + :emphasize-lines: 5 + + function int function_being_called_as_task; + return 1; + endfunction + + initial function_being_called_as_task(); //<--- Warning + + Results in: + + .. code-block:: + + %Warning-IGNOREDRETURN: example.v:5:9: Ignoring return value of non-void function (IEEE 1800-2017 13.4.1) + + The portable way to suppress this warning (in SystemVerilog) is to use a + void cast, for example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 5 + + function int function_being_called_as_task; + return 1; + endfunction + + initial void'(function_being_called_as_task()); //<--- Repaired + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: IMPERFECTSCH + + .. TODO better example + + Warns that the scheduling of the model is not absolutely perfect, and + some manual code edits may result in faster performance. This warning + defaults to off, is not part of -Wall, and must be turned on explicitly + before the top module statement is processed. + + +.. option:: IMPLICIT + + .. TODO better example + + Warns that a wire is being implicitly declared (it is a single bit wide + output from a sub-module.) While legal in Verilog, implicit + declarations only work for single bit wide signals (not buses), do not + allow using a signal before it is implicitly declared by an instance, + and can lead to dangling nets. A better option is the + :code:`/*AUTOWIRE*/` feature of Verilog-Mode for Emacs, available from + `https://www.veripool.org/verilog-mode + `_ + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + Other tools with similar warnings: Icarus Verilog's implicit, "warning: + implicit definition of wire '...'". + + +.. option:: IMPORTSTAR + + .. TODO better example + + Warns that an :code:`import {package}::*` statement is in $unit + scope. This causes the imported symbols to pollute the global namespace, + defeating much of the purpose of having a package. Generally + :code:`import ::*` should only be used inside a lower scope such as a + package or module. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: IMPURE + + .. TODO better example + + Warns that a task or function that has been marked with a + :option:`/*verilator&32;no_inline_task*/` metacomment, but it references + variables that are not local to the task. Verilator cannot schedule + these variables correctly. + + Ignoring this warning may make Verilator simulations differ from other + simulators. + + +.. option:: INCABSPATH + + .. TODO better example + + Warns that an "\`include" filename specifies an absolute path. This + means the code will not work on any other system with a different file + system layout. Instead of using absolute paths, relative paths + (preferably without any directory specified whatsoever) should be used, + and +incdir used on the command line to specify the top include source + directories. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: INFINITELOOP + + .. TODO better example + + Warns that a while or for statement has a condition that is always true. + and thus results in an infinite loop if the statement ever executes. + + This might be unintended behavior if the loop body contains statements + that in other simulators would make time pass, which Verilator is + ignoring due to e.g. ``STMTDLY`` warnings being disabled. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly (i.e. hang due to the infinite loop). + + +.. option:: INITIALDLY + + .. TODO better example + + Warns that the code has a delayed assignment inside of an initial or + final block. If this message is suppressed, Verilator will convert this + to a non-delayed assignment. See also :option:`COMBDLY`. + + Ignoring this warning may make Verilator simulations differ from other + simulators. + + +.. option:: INSECURE + + Warns that the combination of options selected may be defeating the + attempt to protect/obscure identifiers or hide information in the model. + Correct the options provided, or inspect the output code to see if the + information exposed is acceptable. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: LATCH + + .. TODO better example + + Warns that a signal is not assigned in all control paths of a + combinational always block, resulting in the inference of a latch. For + intentional latches, consider using the always_latch (SystemVerilog) + keyword instead. The warning may be disabled with a lint_off pragma + around the always block. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: LITENDIAN + + .. TODO better example + + Warns that a packed vector is declared with little endian bit numbering + (i.e. [0:7]). Big endian bit numbering is now the overwhelming + standard, and little numbering is now thus often due to simple oversight + instead of intent. + + Also warns that an instance is declared with little endian range + (i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE + the bits will likely be backwards from what people may expect + (i.e. instance [0] will connect to signal bit [N-1] not bit [0]). + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: MODDUP + + .. TODO better example + + Warns that a module has multiple definitions. Generally this indicates + a coding error, or a mistake in a library file and it's good practice to + have one module per file (and only put each file once on the command + line) to avoid these issues. For some gate level netlists duplicates + are sometimes unavoidable, and MODDUP should be disabled. + + Ignoring this warning will cause the more recent module definition to be + discarded. + + +.. option:: MULTIDRIVEN + + .. TODO better example + + Warns that the specified signal comes from multiple always blocks. This + is often unsupported by synthesis tools, and is considered bad style. + It will also cause longer simulation runtimes due to reduced + optimizations. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: MULTITOP + + .. TODO better example + + Warns that there are multiple top level modules, that is modules not + instantiated by any other module, and both modules were put on the + command line (not in a library). Three likely cases: + + 1. A single module is intended to be the top. This warning then occurs + because some low level instance is being read in, but is not really + needed as part of the design. The best solution for this situation is + to ensure that only the top module is put on the command line without + any flags, and all remaining library files are read in as libraries with + :vlopt:`-v`, or are automatically resolved by having filenames that + match the module names. + + 2. A single module is intended to be the top, the name of it is known, + and all other modules should be ignored if not part of the design. The + best solution is to use the :vlopt:`--top` option to specify the top module's + name. All other modules that are not part of the design will be for the + most part ignored (they must be clean in syntax and their contents will + be removed as part of the Verilog module elaboration process.) + + 3. Multiple modules are intended to be design tops, e.g. when linting a + library file. As multiple modules are desired, disable the MULTITOP + warning. All input/outputs will go uniquely to each module, with any + conflicting and identical signal names being made unique by adding a + prefix based on the top module name followed by __02E (a + Verilator-encoded ASCII "."). This renaming is done even if the two + modules' signals seem identical, e.g. multiple modules with a "clk" + input. + + +.. option:: NOLATCH + + .. TODO better example + + Warns that no latch was detected in an always_latch block. The warning + may be disabled with a lint_off pragma around the always block, but + recoding using a regular always may be more appropriate. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: NULLPORT + + Warns that a null port was detected in the module definition port + list. Null ports are empty placeholders, i.e. either one ore more commas + at the beginning or the end of a module port list, or two or more + consecutive commas in the middle of a module port list. A null port + cannot be accessed within the module, but when instantiating the module + by port order, it is treated like a regular port and any wire connected + to it is left unconnected. For example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + module a + (a_named_port, ); //<--- Warning + + This is considered a warning because null ports are rarely used, and is + mostly the result of a typing error such as a dangling comma at the end + of a port list. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + +.. option:: PINCONNECTEMPTY + + .. TODO better example + + Warns that an instance has a pin which is connected to + :code:`.pin_name()`, e.g. not another signal, but with an explicit + mention of the pin. It may be desirable to disable PINCONNECTEMPTY, as + this indicates intention to have a no-connect. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: PINMISSING + + .. TODO better example + + Warns that a module has a pin which is not mentioned in an instance. If + a pin is not missing it should still be specified on the instance + declaration with a empty connection, using :code:`(.pin_name())`. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + Other tools with similar warnings: Icarus Verilog's portbind, "warning: + Instantiating module ... with dangling impot port (...)". Slang's + unconnected-port, "port '...' has no connection". + + +.. option:: PINNOCONNECT + + .. TODO better example + + Warns that an instance has a pin which is not connected to another + signal. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: PINNOTFOUND + + Warns that an instance port or Parameter was not found in the module + being instantiated. Note that Verilator raises these errors also on + instances that should be disabled by generate/if/endgenerate constructs: + + .. code-block:: sv + :linenos: + :emphasize-lines: 5-6 + + module a; + localparam A=1; + generate + if (A==0) begin + b b_inst1 (.x(1'b0)); //<--- error nonexistent port + b #(.PX(1'b0)) b_inst2 (); //<--- error nonexistent parameter + end + endgenerate + endmodule + + module b; + endmodule + + In the example above, b is instantiated with a port named x, but module + b has no such port. In the next line, b is instantiated again with a + nonexistent parameter PX. Technically, this code is incorrect because of + this, but other tools may ignore it because module b is not instantiated + due to the generate/if condition being false. + + This error may be disabled with a lint_off PINNOTFOUND metacomment. + + +.. option:: PKGNODECL + + .. TODO better example + + Error that a package/class appears to have been referenced that has not + yet been declared. According to IEEE 1800-2017 26.3 all packages must + be declared before being used. + + +.. option:: PROCASSWIRE + + .. TODO better example + + Error that a procedural assignment is setting a wire. According to IEEE, + a var/reg must be used as the target of procedural assignments. + + +.. option:: RANDC + + Warns that the :code:`randc` keyword is currently unsupported, and that + it is being converted to :code:`rand`. + + +.. option:: REALCVT + + Warns that a real number is being implicitly rounded to an integer, with + possible loss of precision. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + int i; + i = 2.3; //<--- Warning + + Results in: + + .. code-block:: + + %Warning-REALCVT: example.v:2:5: Implicit conversion of real to integer + + If the code is correct, the portable way to suppress the warning is to + add a cast. This will express the intent and should avoid future + warnings on any linting tool. + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + int i; + i = int'(2.3); //<--- Repaired + + +.. option:: REDEFMACRO + + Warns that the code has redefined the same macro with a different value, + for example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 3 + + `define DUP def1 + //... + `define DUP def2 //<--- Warning + + Results in: + + .. code-block:: + + %Warning-REDEFMACRO: example.v:3:20: Redefining existing define: 'DUP', with different value: 'def1' + example.v:1:20: ... Location of previous definition, with value: 'def2' + + The best solution is to use a different name for the second macro. If + this is not possible, add a undef to indicate the code is overriding the + value. This will express the intent and should avoid future warnings on + any linting tool: + + .. code-block:: sv + + `define DUP def1 + //... + `undef DUP //<--- Repaired + `define DUP def2 + + Other tools with similar warnings: Icarus Verilog's macro-redefinition, + "warning: redefinition of macro ... from value '...' to '...'". Yosys's + "Duplicate macro arguments with name". + + +.. option:: SELRANGE + + Warns that a selection index will go out of bounds. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + wire vec[6:0]; + initial out = vec[7]; //<--- Warning (there is no [7]) + + Verilator will assume zero for this value, instead of X. Note that in + some cases this warning may be false, when a condition upstream or + downstream of the access means the access out of bounds will never + execute or be used. + + Repaired example: + + .. code-block:: sv + :linenos: + + wire vec[6:0]; + initial begin + index = 7; + ... + if (index < 7) out = vec[index]; // Never will use vec[7] + + Other tools with similar warnings: Icarus Verilog's select-range, + "warning: ... [...] is selecting before vector" or "is selecting before + vector". + + +.. option:: SHORTREAL + + Warns that Verilator does not support :code:`shortreal` and they will be + automatically promoted to :code:`real`. + + .. code-block:: sv + :linenos: + :emphasize-lines: 1 + + shortreal sig; //<--- Warning + + The recommendation is to replace any :code:`shortreal` in the code with + :code:`real`, as :code:`shortreal` is not widely supported across + industry tools. + + .. code-block:: sv + :linenos: + :emphasize-lines: 1 + + real sig; //<--- Repaired + + Ignoring this warning may make Verilator simulations differ from other + simulators, if the increased precision of real affects your model or DPI + calls. + + +.. option:: SPLITVAR + + Warns that a variable with a :option:`/*verilator&32;split_var*/` + metacomment was not split. Some possible reasons for this are: + + * The datatype of the variable is not supported for splitting. (e.g. is + a real). + + * The access pattern of the variable can not be determined + statically. (e.g. is accessed as a memory). + + * The index of the array exceeds the array size. + + * The variable is accessed from outside using dotted reference. + (e.g. top.instance0.variable0 = 1). + + * The variable is not declared in a module, but in a package or an + interface. + + * The variable is a parameter, localparam, genvar, or queue. + + * The variable is tristate or bidirectional. (e.g. inout or ref). + + +.. option:: STMTDLY + + Warns that the code has a statement with a delayed time in front of it. + + Ignoring this warning may make Verilator simulations differ from other + simulators. + + Faulty example: + + .. code-block:: sv + + #100 $finish; //<--- Warning + + +.. option:: SYMRSVDWORD + + Warning that a symbol matches a C++ reserved word and using this as a + symbol name would result in odd C++ compiler errors. You may disable + this warning, but the symbol will be renamed by Verilator to avoid the + conflict. + + +.. option:: SYNCASYNCNET + + .. TODO better example + + Warns that the specified net is used in at least two different always + statements with posedge/negedges (i.e. a flop). One usage has the + signal in the sensitivity list and body, probably as an async reset, and + the other usage has the signal only in the body, probably as a sync + reset. Mixing sync and async resets is usually a mistake. The warning + may be disabled with a lint_off pragma around the net, or either flopped + block. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: TASKNSVAR + + Error when a call to a task or function has an inout from that task tied + to a non-simple signal. Instead connect the task output to a temporary + signal of the appropriate width, and use that signal to set the + appropriate expression as the next statement. For example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 4 + + task foo(inout sig); ... endtask + // ... + always @* begin + foo(bus_we_select_from[2]); // Will get TASKNSVAR error + end + + Change this to: + + .. code-block:: sv + + task foo(inout sig); ... endtask + // ... + reg foo_temp_out; + always @* begin + foo(foo_temp_out); + bus_we_select_from[2] = foo_temp_out; + end + + Verilator doesn't do this conversion for you, as some more complicated + cases would result in simulator mismatches. + + +.. option:: TICKCOUNT + + Warns that the number of ticks to delay a $past variable is greater + than 10. At present Verilator effectively creates a flop for each + delayed signals, and as such any large counts may lead to large design + size increases. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: TIMESCALEMOD + + Warns that "\`timescale" is used in some but not all modules. + + This may be disabled similar to other warnings. Ignoring this warning + may result in a module having an unexpected timescale. + + IEEE recommends this be an error, for that behavior use + :vlopt:`-Werror-TIMESCALEMOD <-Werror-\>`. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 5 + + module mod1; + sub sub(); + endmodule + `timescale 1ns/1ns + module sub; //<--- Warning + endmodule + + Results in: + + .. code-block:: + + %Warning-TIMESCALEMOD: example.v:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.3) + + Recommend using :vlopt:`--timescale` argument, or in front of all + modules use: + + .. code-block:: sv + + `include "timescale.vh" + + Then in that file set the timescale. + + Other tools with similar warnings: Icarus Verilog's timescale, "warning: + Some design elements have no explicit time unit and/or time + precision. This may cause confusing timing results." Slang's: + "[WRN:PA0205] No timescale set for "..."". + + +.. option:: UNDRIVEN + + .. TODO better example + + Warns that the specified signal has no source. Verilator is fairly + liberal in the usage calculations; making a signal public, or setting + only a single array element marks the entire signal as driven. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Other tools with similar warnings: Odin's "[NETLIST] This output is + undriven (...) and will be removed". + + +.. option:: UNOPT + + .. TODO better example + + Warns that due to some construct, optimization of the specified signal + or block is disabled. The construct should be cleaned up to improve + simulation performance. + + A less obvious case of this is when a module instantiates two + submodules. Inside submodule A, signal I is input and signal O is + output. Likewise in submodule B, signal O is an input and I is an + output. A loop exists and a UNOPT warning will result if AI & AO both + come from and go to combinatorial blocks in both submodules, even if + they are unrelated always blocks. This affects performance because + Verilator would have to evaluate each submodule multiple times to + stabilize the signals crossing between the modules. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: UNOPTFLAT + + .. TODO better example + + Warns that due to some construct, optimization of the specified signal + is disabled. The signal reported includes a complete scope to the + signal; it may be only one particular usage of a multiply instantiated + block. The construct should be cleaned up to improve simulation + performance; two times better performance may be possible by fixing + these warnings. + + Unlike the ``UNOPT`` warning, this occurs after flattening the netlist, + and indicates a more basic problem, as the less obvious case described + under ``UNOPT`` does not apply. + + Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by + synthesis which analyzes interconnection per-bit, but is circular to + simulation which analyzes per-bus: + + .. code-block:: sv + + wire [2:0] x = {x[1:0], shift_in}; + + This statement needs to be evaluated multiple times, as a change in + :code:`shift_in` requires "x" to be computed 3 times before it becomes + stable. This is because a change in "x" requires "x" itself to change + value, which causes the warning. + + For significantly better performance, split this into 2 separate signals: + + .. code-block:: sv + + wire [2:0] xout = {x[1:0], shift_in}; + + and change all receiving logic to instead receive "xout". + Alternatively, change it to: + + .. code-block:: sv + + wire [2:0] x = {xin[1:0], shift_in}; + + and change all driving logic to instead drive "xin". + + With this change this assignment needs to be evaluated only once. These + sort of changes may also speed up your traditional event driven + simulator, as it will result in fewer events per cycle. + + The most complicated UNOPTFLAT path we've seen was due to low bits of a + bus being generated from an always statement that consumed high bits of + the same bus processed by another series of always blocks. The fix is + the same; split it into two separate signals generated from each block. + + Occasionally UNOPTFLAT may be indicated when there is a true + circulation. e.g. if trying to implement a flop or latch using + individual gate primitives. If UNOPTFLAT is suppressed the code may get + a DIDNOTCONVERGE error. Verilator does not support building flops or + latches out of gate primitives, and any such code must change to use + behavioral constructs (e.g. always_ff and always_latch). + + Another way to resolve this warning is to add a + :option:`/*verilator&32;split_var*/` metacomment described above. This + will cause the variable to be split internally, potentially resolving + the conflict. If you run with `--report-unoptflat` Verilator will + suggest possible candidates for :option:`/*verilator&32;split_var*/`. + + The UNOPTFLAT warning may also be due to clock enables, identified from + the reported path going through a clock gating instance. To fix these, + use the clock_enable meta comment described above. + + The UNOPTFLAT warning may also occur where outputs from a block of logic + are independent, but occur in the same always block. To fix this, use + the :option:`/*verilator&32;isolate_assignments*/` metacomment described + above. + + To assist in resolving UNOPTFLAT, the option :vlopt:`--report-unoptflat` + can be used, which will provide suggestions for variables that can be + split up, and a graph of all the nodes connected in the loop. See the + Arguments section for more details. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: UNOPTTHREADS + + .. TODO better example + + Warns that the thread scheduler was unable to partition the design to + fill the requested number of threads. + + One workaround is to request fewer threads with :vlopt:`--threads`. + + Another possible workaround is to allow more MTasks in the simulation + runtime, by increasing the value of :vlopt:`--threads-max-mtasks`. More + MTasks will result in more communication and synchronization overhead at + simulation runtime; the scheduler attempts to minimize the number of + MTasks for this reason. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: UNPACKED + + Warns that unpacked structs and unions are not supported. + + Ignoring this warning will make Verilator treat the structure as packed, + which may make Verilator simulations differ from other simulators. This + downgrading may also result what would normally be a legal unpacked + struct/array inside an unpacked struct/array becoming an illegal + unpacked struct/array inside a packed struct/array. + + +.. option:: UNSIGNED + + .. TODO better example + + Warns that the code is comparing a unsigned value in a way that implies + it is signed, for example "X < 0" will always be false when X is + unsigned. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: UNSUPPORTED + + Error that a construct might be legal according to IEEE but is not + currently supported by Verilator. + + This error may be ignored with :vlopt:`--bbox-unsup`, however this will + make the design simulate incorrectly; see the details under + :vlopt:`--bbox-unsup`. + + +.. option:: UNUSED + + .. TODO better example + + Warns that the specified signal or parameter is never used/consumed. + Verilator is fairly liberal in the usage calculations; making a signal + public, a signal matching the :vlopt:`--unused-regexp` option (default + "\*unused\*" or accessing only a single array element marks the entire + signal as used. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + A recommended style for unused nets is to put at the bottom of a file + code similar to the following: + + .. code-block:: sv + + wire _unused_ok = &{1'b0, + sig_not_used_a, + sig_not_used_yet_b, // To be fixed + 1'b0}; + + The reduction AND and constant zeros mean the net will always be zero, + so won't use simulation runtime. The redundant leading and trailing + zeros avoid syntax errors if there are no signals between them. The + magic name "unused" (controlled by :vlopt:`--unused-regexp` option) is + recognized by Verilator and suppresses warnings; if using other lint + tools, either teach it to the tool to ignore signals with "unused" in + the name, or put the appropriate lint_off around the wire. Having + unused signals in one place makes it easy to find what is unused, and + reduces the number of lint_off pragmas, reducing bugs. + + +.. option:: USERERROR + + A SystemVerilog elaboration-time assertion error was executed. + IEEE 1800-2017 20.11 requires this error. + + Faulty example: + + .. include:: ../../docs/gen/ex_USERERROR_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_USERERROR_msg.rst + + To resolve, examine the code and rectify the cause of the error. + + +.. option:: USERFATAL + + A SystemVerilog elaboration-time assertion fatal was executed. + IEEE 1800-2017 20.11 requires this error. + + Faulty example: + + .. include:: ../../docs/gen/ex_USERFATAL_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_USERFATAL_msg.rst + + To resolve, examine the code and rectify the cause of the fatal. + + +.. option:: USERINFO + + A SystemVerilog elaboration-time assertion print was executed. This is + not an error nor warning. IEEE 1800-2017 20.11 requires this behavior. + + Example: + + .. include:: ../../docs/gen/ex_USERINFO_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_USERINFO_msg.rst + + +.. option:: USERWARN + + A SystemVerilog elaboration-time assertion warning was executed. + IEEE 1800-2017 20.11 requires this warning. + + Faulty example: + + .. include:: ../../docs/gen/ex_USERWARN_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_USERWARN_msg.rst + + To resolve, examine the code and rectify the cause of the error. + + +.. option:: VARHIDDEN + + Warns that a task, function, or begin/end block is declaring a variable + by the same name as a variable in the upper level module or begin/end + block (thus hiding the upper variable from being able to be used.) + Rename the variable to avoid confusion when reading the code. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Faulty example: + + .. include:: ../../docs/gen/ex_VARHIDDEN_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_VARHIDDEN_msg.rst + + To resolve, rename the variable to a unique name. + + +.. option:: WIDTH + + Warns that based on width rules of Verilog: + + * Two operands have different widths, e.g. adding a 2-bit and 5-bit + number. + + * A part select has a different size then needed to index into the + packed or unpacked array (etc). + + Verilator for attempts to track the minimum width of unsized constants + and will suppress the warning when the minimum width is appropriate to + fit the required size. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + The recommendation is to fix these issues by: + + * Resizing the variable or constant. E.g. :code:`2'd2` instead of :code:`3'd2`. + + * Using :code:`'0` or :code:`'1`. + + * Using part select to narrow a variable. E.g. :code:`too_wide[1:0]`. + + * Using concatenate to widen a variable. E.g. :code:`{1'b1, too_narrow}`. + + * Using cast to resize a variable. E.g. :code:`23'(wrong_sized)`. + + For example this is a missized index: + + .. include:: ../../docs/gen/ex_WIDTH_1_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_WIDTH_1_msg.rst + + One possible fix: + + .. include:: ../../docs/gen/ex_WIDTH_1_fixed.rst + + +.. option:: WIDTHCONCAT + + Warns that based on width rules of Verilog, a concatenate or replication + has an indeterminate width. In most cases this violates the Verilog + rule that widths inside concatenates and replicates must be sized, and + should be fixed in the code. + + Faulty example: + + .. code-block:: sv + + wire [63:0] concat = {1, 2}; + + An example where this is technically legal (though still bad form) is: + + .. code-block:: sv + + parameter PAR = 1; + wire [63:0] concat = {PAR, PAR}; + + The correct fix is to either size the 1 (:code:`32'h1`), or add the + width to the parameter definition (:code:`parameter [31:0]`), or add the + width to the parameter usage (:code:`{PAR[31:0], PAR[31:0]}`). diff --git a/docs/install.rst b/docs/install.rst deleted file mode 100644 index f6f7a2031..000000000 --- a/docs/install.rst +++ /dev/null @@ -1,397 +0,0 @@ -|Logo| - -====================== -Verilator Installation -====================== - -.. contents:: - :depth: 3 - -Introduction -============ - -This discusses how to install Verilator. For more general information -please see `verilator.org `__. - - -Quick-start -=========== - - -Install From a Package Manager ------------------------------- - -Using a distribution's package manager is the easiest way to get -started. (Note packages are unlikely to have the most recent version, so -Git, below, maybe a better alternative.) To install as a package: - -:: - - apt-get install verilator - -If this works, skip down to `Running Verilator <#_running_verilator>`__. - - -Docker ------- - -Verilator is available in pre-built Docker containers. See -https://github.com/verilator/verilator/blob/master/ci/docker/run/README.rst - - -Git ---- - -Installing Verilator with Git provides the most flexibility. For -additional options and details see the additional sections below. In -brief: - -:: - - # Prerequisites: - #sudo apt-get install git make autoconf g++ flex bison - #sudo apt-get install libfl2 # Ubuntu only (ignore if gives error) - #sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error) - - git clone https://github.com/verilator/verilator # Only first time - ## Note the URL above is not a page you can see with a browser, it's for git only - - # Every time you need to build: - unsetenv VERILATOR_ROOT # For csh; ignore error if on bash - unset VERILATOR_ROOT # For bash - cd verilator - git pull # Make sure git repository is up-to-date - git tag # See what versions exist - #git checkout master # Use development branch (e.g. recent bug fixes) - #git checkout stable # Use most recent stable release - #git checkout v{version} # Switch to specified release version - - autoconf # Create ./configure script - ./configure - make - sudo make install - # Now see "man verilator" or online verilator.pdf's for the example tutorials - -If this works, skip down to `Running Verilator <#_running_verilator>`__. - - -Detailed Build Instructions -=========================== - -This section describes details of the build process, and assumes you are -building from Git or a tarball. For using a pre-built binary for your -Linux distribution, see instead `Install From a Package -Manager <#_install_from_a_package_manager>`__. - - -OS Requirements ---------------- - -Verilator is developed and has primary testing on Ubuntu, with additional -testing on FreeBSD and Apple OS-X. Versions have also built on Redhat -Linux, HPUX and Solaris. It should run with minor porting on any -GNU/Linux-ish platform. Verilator also works on Windows under Cygwin, and -Windows under MinGW (gcc -mno-cygwin). Verilated output (not Verilator -itself) compiles under all the options above, plus MSVC++. - - -Install Prerequisites ---------------------- - -To build or run Verilator you need these standard packages: - -:: - - sudo apt-get install perl python3 make - sudo apt-get install g++ # Alternatively, clang - sudo apt-get install libgz # Non-Ubuntu (ignore if gives error) - sudo apt-get install libfl2 libfl-dev zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error) - -To build or run the following are optional but should be installed for good -performance: - -:: - - sudo apt-get install ccache # If present at build, needed for run - sudo apt-get install libgoogle-perftools-dev numactl perl-doc - -To build Verilator you will need to install these packages; these do not -need to be present to run Verilator: - -:: - - sudo apt-get install git autoconf flex bison - -Those developing Verilator itself may also want these (see internals.rst): - -:: - - sudo apt-get install gdb asciidoctor graphviz cmake clang clang-format gprof lcov - cpan install Pod::Perldoc - cpan install Parallel::Forker - - -Install SystemC -~~~~~~~~~~~~~~~ - -If you will be using SystemC (vs straight C++ output), download `SystemC -`__. Follow their -installation instructions. You will need to set ``SYSTEMC_INCLUDE`` to -point to the include directory with ``systemc.h`` in it, and -``SYSTEMC_LIBDIR`` to points to the directory with ``libsystemc.a`` in -it. (Older installations may set ``SYSTEMC`` and ``SYSTEMC_ARCH`` instead.) - - -Install GTKWave -~~~~~~~~~~~~~~~ - -To make use of Verilator FST tracing you will want `GTKwave -`__ installed, however this is not -required at Verilator build time. - - -Obtain Sources --------------- - -You may use Git or a tarball for the sources. Git is the supported -option. (If using a historical build that uses a tarball, tarballs are -obtained from `Verilator Downloads -`__; we presume -you know how to use it, and is not described here.) - -Get the sources from the repository: (You need do this only once, ever.) - -:: - - git clone https://github.com/verilator/verilator # Only first time - ## Note the URL above is not a page you can see with a browser, it's for git only - -Enter the checkout and determine what version/branch to use: - -:: - - cd verilator - git pull # Make sure we're up-to-date - git tag # See what versions exist - #git checkout master # Use development branch (e.g. recent bug fix) - #git checkout stable # Use most recent release - #git checkout v{version} # Switch to specified release version - - -Auto Configure --------------- - -Create the configuration script: - -:: - - autoconf # Create ./configure script - - -Eventual Installation Options ------------------------------ - -Before configuring the build, you have to decide how you're going to -eventually install the kit. Verilator will be compiling the current value -of ``VERILATOR_ROOT``, ``SYSTEMC_INCLUDE``, and ``SYSTEMC_LIBDIR`` as -defaults into the executable, so they must be correct before configuring. - -These are the options: - - -1. Run-in-Place from VERILATOR_ROOT -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Our personal favorite is to always run Verilator in-place from its Git -directory. This allows the easiest experimentation and upgrading, and -allows many versions of Verilator to co-exist on a system. - -:: - - export VERILATOR_ROOT=`pwd` # if your shell is bash - setenv VERILATOR_ROOT `pwd` # if your shell is csh - ./configure - # Running will use files from $VERILATOR_ROOT, so no install needed - -Note after installing (below steps), a calling program or shell must set -the environment variable ``VERILATOR_ROOT`` to point to this Git directory, -then execute ``$VERILATOR_ROOT/bin/verilator``, which will find the path to -all needed files. - - -2. Install into a CAD Disk -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -You may eventually be installing onto a project/company-wide "CAD" tools -disk that may support multiple versions of every tool. Target the build to -a destination directory name that includes the Verilator version name: - -:: - - unset VERILATOR_ROOT # if your shell is bash - unsetenv VERILATOR_ROOT # if your shell is csh - # For the tarball, use the version number instead of git describe - ./configure --prefix /CAD_DISK/verilator/`git describe | sed "s/verilator_//"` - -Note after installing (below steps), if you use `modulecmd -`__, you'll want a module file like the -following: - -**modulecmd's verilator/version file.** - -:: - - set install_root /CAD_DISK/verilator/{version-number-used-above} - unsetenv VERILATOR_ROOT - prepend-path PATH $install_root/bin - prepend-path MANPATH $install_root/man - prepend-path PKG_CONFIG_PATH $install_root/share/pkgconfig - - -3. Install into a Specific Path -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -You may eventually install Verilator into a specific installation prefix, -as most GNU tools support: - -:: - - unset VERILATOR_ROOT # if your shell is bash - unsetenv VERILATOR_ROOT # if your shell is csh - ./configure --prefix /opt/verilator-VERSION - -Then after installing (below steps) you will need to add -``/opt/verilator-VERSION/bin`` to ``$PATH``. - - -4. Install System Globally -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The final option is to eventually install Verilator globally, using the -normal system paths: - -:: - - unset VERILATOR_ROOT # if your shell is bash - unsetenv VERILATOR_ROOT # if your shell is csh - ./configure - -Then after installing (below) the binary directories should already be -in your ``$PATH``. - - -Configure ---------- - -The command to configure the package was described in the previous step. -Developers should configure to have more complete developer tests. -Additional packages may be required for these tests. - -:: - - export VERILATOR_AUTHOR_SITE=1 # Put in your .bashrc - ./configure --enable-longtests ...above options... - - -Compile -------- - -Compile Verilator: - -:: - - make -j - - -Test ----- - -Check the compilation by running self-tests: - -:: - - make test - - -Install -------- - -If you used any but the `1. Run-in-Place from VERILATOR_ROOT -<#_1_run_in_place_from_verilator_root>`__ scheme, install to the -OS-standard place: - -:: - - make install - - -Running Verilator -================= - -To run Verilator, see the example sections in the `Verilator manual (HTML) -`__, or `Verilator manual (PDF) -`__. - -Also see the ``examples/`` directory that is part of the kit, and is -installed (in a OS-specific place, often in e.g. -``/usr/local/share/verilator/examples``). - -:: - - cd examples/make_hello_c - make - -Note if you did a ``make install`` above you should not have -``VERILATOR_ROOT`` set in your environment; it is built into the -executable. - - -Announcements -============= - -To get notified of new releases, go to `Verilator announcement repository -`__ and follow the -instructions there. - - -Directory Structure -=================== - -Some relevant files and directories in this package are as follows: - -:: - - Changes => Version history - README.rst => This document - bin/verilator => Compiler wrapper invoked to Verilate code - docs/ => Additional documentation - examples/make_hello_c => Example GNU-make simple Verilog->C++ conversion - examples/make_hello_sc => Example GNU-make simple Verilog->SystemC conversion - examples/make_tracing_c => Example GNU-make Verilog->C++ with tracing - examples/make_tracing_sc => Example GNU-make Verilog->SystemC with tracing - examples/make_protect_lib => Example using --protect-lib - examples/cmake_hello_c => Example building make_hello_c with CMake - examples/cmake_hello_sc => Example building make_hello_sc with CMake - examples/cmake_tracing_c => Example building make_tracing_c with CMake - examples/cmake_tracing_sc => Example building make_tracing_sc with CMake - examples/cmake_protect_lib => Example building make_protect_lib with CMake - include/ => Files that should be in your -I compiler path - include/verilated*.cpp => Global routines to link into your simulator - include/verilated*.h => Global headers - include/verilated.mk => Common Makefile - src/ => Translator source code - test_regress => Internal tests - -For files created after a design is Verilated, see the `Verilator manual -(HTML) `__, or `Verilator -manual (PDF) `__. - - -License -======= - -Copyright 2008-2021 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. - -.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png diff --git a/docs/internals.rst b/docs/internals.rst index af5923188..f40cce27b 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -1,8 +1,8 @@ |Logo| -=================== +******************* Verilator Internals -=================== +******************* .. contents:: :depth: 3 @@ -81,7 +81,7 @@ Key Classes Used in the Verilator Flow ``AstNode`` -~~~~~~~~~~~ +^^^^^^^^^^^ The AST is represented at the top level by the class ``AstNode``. This abstract class has derived classes for the individual components (e.g. @@ -115,7 +115,7 @@ pointer to the ``AstNode`` currently being processed. ``AstNVisitor`` -~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^ The passes are implemented by AST visitor classes. These are implemented by subclasses of the abstract class, ``AstNVisitor``. Each pass creates an @@ -124,7 +124,7 @@ the pass. ``V3Graph`` -~~~~~~~~~~~ +^^^^^^^^^^^ A number of passes use graph algorithms, and the class ``V3Graph`` is provided to represent those graphs. Graphs are directed, and algorithms are @@ -134,7 +134,7 @@ documentation of this class. ``V3GraphVertex`` -~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^ ``V3GraphVertex`` is the base class for vertices in a graph. Vertices have an associated ``fanout``, ``color`` and ``rank``, which may be used in @@ -156,7 +156,7 @@ in the form: ``V3GraphEdge`` -~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^ ``V3GraphEdge`` is the base class for directed edges between pairs of vertices. Edges have an associated ``weight`` and may also be made @@ -171,7 +171,7 @@ used in dot output. Typically users provided derived classes from ``V3GraphAlg`` -~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^ This is the base class for graph algorithms. It implements a ``bool`` method, ``followEdge`` which algorithms can use to decide whether an edge @@ -204,7 +204,7 @@ synchronization cost is not prohibitive with so few nodes. Partitioning -~~~~~~~~~~~~ +^^^^^^^^^^^^ Our partitioner is similar to the one Vivek Sarkar described in his 1989 paper *Partitioning and Scheduling Parallel Programs for Multiprocessors*. @@ -213,7 +213,7 @@ Let's define some terms: Par Factor -~~~~~~~~~~ +^^^^^^^^^^ The available parallelism or "par-factor" of a DAG is the total cost to execute all nodes, divided by the cost to execute the longest critical path @@ -223,7 +223,7 @@ synchronization are zero. Macro Task -~~~~~~~~~~ +^^^^^^^^^^ When the partitioner coarsens the graph, it combines nodes together. Each fine-grained node represents an atomic "task"; combined nodes in the @@ -235,7 +235,7 @@ ends.) Edge Contraction -~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^ Verilator's partitioner, like Sarkar's, primarily relies on "edge contraction" to coarsen the graph. It starts with one macro-task per atomic @@ -243,7 +243,7 @@ task and iteratively combines pairs of edge-connected macro-tasks. Local Critical Path -~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^ Each node in the graph has a "local" critical path. That's the critical path from the start of the graph to the start of the node, plus the node's @@ -263,7 +263,8 @@ it's not guaranteed to produce the best partition (which Sarkar proves is NP-hard). -Estimating Logic Costs ~~~~~~~~~~~~~~~~~~~~~~ +Estimating Logic Costs +^^^^^^^^^^^^^^^^^^^^^^ To compute the cost of any given path through the graph, Verilator estimates an execution cost for each task. Each macro-task has an execution @@ -284,7 +285,7 @@ runtime costs estimates. This is an area to improve. Scheduling Macro-Tasks at Runtime -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ After coarsening the graph, we must schedule the macro-tasks for runtime. Sarkar describes two options: you can dynamically schedule tasks @@ -306,7 +307,7 @@ fragmentation. Locating Variables for Best Spatial Locality -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ After scheduling all code, we attempt to locate variables in memory such that variables accessed by a single macro-task are close together in @@ -339,11 +340,11 @@ locality in serial mode; that is a possible area for improvement.) Improving Multithreaded Performance Further (a TODO list) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Wave Scheduling -^^^^^^^^^^^^^^^ +""""""""""""""" To allow the Verilated model to run in parallel with the testbench, it might be nice to support "wave" scheduling, in which work on a cycle begins @@ -355,7 +356,7 @@ however, it's probably the best bet for hiding testbench latency. Efficient Dynamic Scheduling -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""""""""""" To scale to more than a few threads, we may revisit a fully dynamic scheduler. For large (>16 core) systems it might make sense to dedicate an @@ -365,7 +366,7 @@ would not be prohibitive. Static Scheduling with Runtime Repack -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +""""""""""""""""""""""""""""""""""""" We could modify the static scheduling approach by gathering actual macro-task execution times at run time, and dynamically re-packing the @@ -377,7 +378,7 @@ or nonuniform competing memory traffic or whatever. Clock Domain Balancing -^^^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""""" Right now Verilator makes no attempt to balance clock domains across macro-tasks. For a multi-domain model, that could lead to bad gantt chart @@ -385,7 +386,7 @@ fragmentation. This could be improved if it's a real problem in practice. Other Forms of MTask Balancing -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""""""""""""" The largest source of runtime overhead is idle CPUs, which happens due to variance between our predicted runtime for each MTask and its actual @@ -406,7 +407,7 @@ option to scramble things. Performance Regression -^^^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""""" It would be nice if we had a regression of large designs, with some diversity of design styles, to test on both single- and multi-threaded @@ -415,7 +416,7 @@ evaluate the optimizations while minimizing the impact of parasitic noise. Per-Instance Classes -^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""" If we have multiple instances of the same module, and they partition differently (likely; we make no attempt to partition them the same) then @@ -631,7 +632,7 @@ and takes an argument type ``AstNode*``. Caution on Using Iterators When Child Changes -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Visitors often replace one node with another node; V3Width and V3Const are major examples. A visitor which is the parent of such a replacement @@ -700,7 +701,7 @@ that type (if it is of class ``SOMETYPE``, or a derived class of as that is faster.) -.. _Testing +.. _Testing: Testing ======= @@ -1152,9 +1153,9 @@ Generally what would you do to add a new feature? 4. If a new Ast type is needed, add it to V3AstNodes.h. Follow the convention described above about the AstNode type hierarchy. -5. Now you can run "test_regress/t/t_{new testcase}.pl --debug" and it'll +5. Now you can run "test_regress/t/t_.pl --debug" and it'll probably fail but you'll see a - test_regress/obj_dir/t_{newtestcase}/*.tree file which you can examine + "test_regress/obj_dir/t_/*.tree" file which you can examine to see if the parsing worked. See also the sections above on debugging. 6. Modify the later visitor functions to process the new feature as needed. @@ -1179,8 +1180,6 @@ Verilator ideally would support all of IEEE, and has the goal to get close to full support. However the following IEEE sections and features are not anticipated to be ever implemented for the reasons indicated. -.. list-table:: - IEEE 1800-2017 3.3 recursive modules Little/no tool support, and arguably not a good practice. IEEE 1800-2017 6.12 "shortreal" diff --git a/docs/spelling.txt b/docs/spelling.txt new file mode 100644 index 000000000..278dd6b76 --- /dev/null +++ b/docs/spelling.txt @@ -0,0 +1,850 @@ +ABCp +Accellera +Affe +Aleksander +Ami +Amir +Anastasiadis +Antonin +Antwerpen +Arasanipalai +Arjen +Asciidoc +Ashutosh +Atmel +Aurelien +Bagri +Baltazar +Bardsley +Benchmarking +Berman +Bhagavatula +Bhattacharyya +Binderman +Bleiweiss +Bogdan +Bouchard +Boumenot +Brej +Briquet +Brownlee +Buckenmaier +Bybell +CMake +Cai +Cavium +Cfuncs +Chandan +Chitlesh +Christophe +Cochrane +Cuan +Cygwin +DErrico +Da +Danilo +Dannoritzer +Das +Dcache +Deadman +Debacker +Defparams +Denio +Deprecations +Deroo +Dickol +Diez +Dimitris +Dinotrace +Djordjevic +Dobbie +Dockerfile +Donal +Doorn +Doxygen +Dressler +Duraid +Dutton +Dzetkulic +Eda +Eddleston +Egbert +Egil +Eiler +Eivind +El +Elbourne +Embecosm +Engstrom +Enzo +Eugen +Fabrizio +Fekete +Ferrandi +Flachs +Foletto +Forker +Francillon +Fredieu +GTKWave +Galbi +Gantt +Gartner +Gelinek +Geoff +Gernot +Gerst +Gielda +Gigerl +Gileadi +Giri +Gisselquist +Gladkikh +Goessling +Gonnen +Goorah +Gossner +Grobman +Gunter +Guo +Hao +Harboe +Hashimoto +Hayenga +Hewson +Hicamp +Hiroki +Holdsworth +Holme +Homebrew +Hornung +Hossell +Hsu +Hyperthreading +Iles +Inlines +Inout +Iru +Iztok +Jacko +Jae +Jalloq +Jankowski +Jannis +Jens +Jeras +Jiuyang +Joly +Jullien +Junji +Junyi +Kaalia +Kagen +Kahlich +Kahn +Kai +Kamendje +Kandadi +Kaplan +Karge +Katz +Katzman +Keren +Keyi +Kimmitt +Kindgren +Kirkham +Klnv +Koenig +Koh +Kolecki +Koonce +Korteland +Koszek +Kravitz +Krolnik +Kruse +Kumashikar +Kuoping +Kurachi +Laeufer +Laurens +Lavino +Leber +Leendert +Lesik +Liland +Liu +Lockhart +Longo +Lussier +MMD +MODDUP +MTasks +Madina +Magne +Mahesh +Mahmoudy +Makefile +Makefiles +Matveyenko +Maupin +Mdir +Mednick +Michiels +Microsystems +Milanovic +MinW +Mindspeed +Miodrag +ModelSim +Modport +Moinak +Mong +Muhlestein +Multithreaded +Multithreading +NOUNOPTFLAT +Nalbantis +Narayan +Nauticus +Newgard +Nikana +Niranjan +Nitza +Noack +Nodine +Oleg +Olof +Olofsson +Oyvind +PLI +Patricio +Petr +Piechotka +Piersall +Plunkett +Popov +Prabhat +Prabhu +Prateek +Pre +Preprocess +Priyadharshini +Pullup +Pulver +Puri +Questa +Ralf +Rapp +Redhat +Reitan +Renga +Requin +Rodionov +Rolfe +Roodselaar +Runtime +Ruud +Rystsov +STandarD +Salman +Sanguinetti +Sanjay +Scharrer +Seitz +Shankar +Shanshan +Sharad +Shareef +Sheng +Shi +Shinkarovsky +Shirakawa +Shuba +Slatter +SoC +Sobhan +Sokorac +Solaris +Solomatnikov +Srini +Stamness +Stephane +Stoddard +Stroebel +Strouble +Stucki +Su +Suguimoto +Sundararajan +Suse +Syms +Synopsys +SystemC +SystemVerilog +Takatsukasa +Tambe +Tariq +Tengstrand +Terpstra +Thiede +Thierry +Thyer +Tichelaar +Tomov +Topa +Tota +Tresidder +Tri +Tristate +Turton +UNOPTFLAT +Ubixum +Uints +Undefines +Unsized +Uselib +Usha +Usuario +VERILATOR +Vasu +Vdly +Vemumtab +Vemuri +Veriable +Verialted +Verilate +Verilated +Verilating +Verilation +Verilator +Verilog +Viktor +Vm +Vukobratovic +Wai +Wasson +Welch +Werror +Wfuture +Whatson +Wildman +Wim +Wno +Wojciech +Wolfel +Wouters +Wpedantic +Wwarn +XSim +Xcelium +Xiaoliang +Xuan +Xuanqi +Yazdanbakhsh +Yi +Yinan +Yosys +Yu +Zhang +abirkmanis +accessor +accessors +agrobman +al +ala +andit +ar +architected +args +arrarys +assertOn +async +ato +atoi +autoconf +autoflush +bXXXX +backend +backslashed +backtrace +backtraces +basename +bbox +biguint +biops +bitstoreal +blackbox +bokke +brancoliticus +buf +bufif +buildenv +bv +bvs +callValueCbs +casex +casez +casted +cb +ccache +cdc +ceil +celldefine +cerr +cfunc +cfuncs +chandle +chandles +changeDetect +chenguokai +clk +clocker +cmake +cmos +combinational +combinatorial +commandArgsPlusMatch +compilable +concat +concats +config +const +coredump +countbits +countones +cout +cpp +cpu +ctor +ctrace +cutable +cygwin +dM +da +dat +datadir +datafiles +ddd +deassign +debugi +defenv +defname +defparam +demangling +der +desassign +destructor +detections +dev +devel +dir +displayb +distcc +doxygen +dpiGetContext +dpic +dsvf +dtor +dumpall +dumpfile +dumplimit +dumpoff +dumpon +dumpportlimit +dumpports +dumpportsall +dumpportslimit +dumpportsoff +dumpportson +dumpvars +dut +dx +elab +elsif +endcase +endcelldefine +endfunction +endgenerate +endian +endif +endmodule +endprotect +endspecify +endtask +engr +entrypoint +enum +enums +env +envvar +eof +erroring +et +eval +exe +executables +expr +extern +fanin +fasttrace +fbranch +fclose +fdisplay +feedthrus +feof +ferror +fflush +fgetc +fgets +filesystem +filt +flto +flushCall +fopen +foreach +fprintf +fprofile +fread +frewind +fs +fscanf +fseek +fsiegle +fst +fstrict +ftell +fullskew +func +funcs +fwrite +gantt +gcc +gdb +genblk +genvar +genvars +getenv +getline +gmake +gmon +gotFinish +gprof +gtkwave +hdr +hdzhangdoc +hh +hier +hierCMakeArgs +hierMkArgs +hierVer +hx +hyperthreads +icecream +idmap +ifdef +ifdefed +iff +ifndef +impot +incdir +includer +inferfaces +inhibitSim +initializer +initializers +inits +inlined +inlining +inout +inouts +inserted +instantiation +instantiations +iostream +ish +isunbounded +isunknown +killua +lang +lcov +ld +len +libext +libgoogle +libsystemc +libtcmalloc +linkers +linter +linux +liu +livelock +ln +loc +localparam +localparams +logicals +longint +lsb +lvalue +lxt +macromodule +makefile +makefiles +manpages +metacomment +metacomments +mis +misconnected +misconversion +missized +mk +mno +modport +modports +msg +msvc +mtask +mtasks +mulithreaded +mult +multidim +multiinterfaces +multiline +multipling +multithread +multithreaded +multithreading +mutexes +mux +mysignal +namespace +nand +nanduraj +nasties +negedge +negedges +netlist +netlists +nettype +nmos +noassert +nochange +noconfig +nol +nonblocking +noprivate +noreturn +notif +nullptr +onehot +ooo +oprofile +oversubscription +param +parameterized +params +parens +pc +pdf +perf +perftools +picoChip +pinout +plusargs +pmos +poping +portbind +portlists +posedge +posix +postfix +pragma +pragmas +pre +precisions +predefines +prepend +prepended +preprocess +preprocessed +preprocessing +preprocessor +prerelease +prev +printf +printtimescale +profcfunc +profcfuncs +prototyptes +ps +pthread +pulldown +pulldowns +pullup +pvalue +pwd +qrq +radix +randc +rarr +rdtsc +reStructuredText +readme +readmem +readmemb +readmemh +realpath +realtime +recoding +recrem +redeclaring +regs +reloop +resetall +respecified +rr +rst +runtime +runtimes +rw +sVerilator +sc +scalared +sccanf +seg +setuphold +sformat +sformatf +shortint +shortreal +signame +sp +specparam +splitme +spp +sqrt +srcdir +srcfile +sscanf +stderr +stdin +stdout +stime +stmts +strcasecmp +stringification +stringified +stringify +struct +structs +subcell +subcells +subexpressions +submodule +submodules +sv +svBitVal +svBitVecVal +svGet +svLogicVal +svdpi +swrite +sys +systemc +testbench +threadsafe +threashold +timeInc +timeformat +timeprecision +timeskew +timeunit +tinshark +tm +tolower +toolchain +topcell +toplevel +toupper +traceEverOn +tran +treei +tri +tristate +tristates +trunc +txt +typ +typedef +typedefed +typedefs +typename +uint +un +undef +undefineall +undriven +ungetc +uniquified +unistd +unlink +unlinked +unopt +unoptflat +unoptimizable +unroller +unsized +unsup +untyped +urandom +uselib +uwire +uwires +vc +vcd +vcddiff +vcoverage +vec +ver +verFiles +verible +verilate +verilated +verilator +verilog +verilogmod +verimake +vl +vlopt +vlt +vltstd +vluint +vpi +vpiLeftRange +vpiModule +vpiSize +vpiSuppressVal +vpiTimeUnit +vpiType +vpm +vpp +warmup +waveforms +whitespace +widthed +wreal +writeb +writeme +writemem +writememb +writememh +xin +xml +xnor +xout +xuejiazidi +yanx +yurivict +zdave diff --git a/docs/verilated.dox b/docs/verilated.dox new file mode 100644 index 000000000..eba749428 --- /dev/null +++ b/docs/verilated.dox @@ -0,0 +1,42 @@ +PROJECT_NAME = "Verilog to Routing - ABC" +INPUT = ../../include +OUTPUT_DIRECTORY = _build/doxygen/verilated + +EXTRACT_ALL = NO +EXTRACT_LOCAL_CLASSES = NO +EXTRACT_PRIVATE = NO +EXTRACT_STATIC = YES +FULL_PATH_NAMES = NO +GENERATE_HTML = NO +GENERATE_LATEX = NO +GENERATE_XML = YES +HIDE_FRIEND_COMPOUNDS = YES +HIDE_IN_BODY_DOCS = YES +HIDE_UNDOC_CLASSES = YES +HIDE_UNDOC_MEMBERS = YES +INTERNAL_DOCS = NO +OPTIMIZE_OUTPUT_FOR_C = NO +RECURSIVE = NO +SHOW_INCLUDE_FILES = NO +WARN_IF_UNDOCUMENTED = NO + +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = YES +EXPAND_ONLY_PREDEF = YES +PREDEFINED = \ + "DOXYGEN=1" \ + "VL_ATTR_NORETURN=" \ + "VL_ATTR_PRINTF()=" \ + "VL_ATTR_WEAK=" \ + "VL_GUARDED_BY()=" \ + "VL_MT_SAFE=" \ + "VL_MT_SAFE_EXCLUDES()=" \ + "VL_MT_SAFE_POSTINIT=" \ + "VL_MT_UNSAFE=" \ + "VL_MT_UNSAFE_ONE=" \ + "VL_NOT_FINAL=" \ + "VL_PURE=" \ + "VL_REQUIRES()=" \ + "VL_THREAD_LOCAL=" \ + "__restrict=" \ + diff --git a/docs/xml.rst b/docs/xml.rst index a6aab1e0c..c145c5991 100644 --- a/docs/xml.rst +++ b/docs/xml.rst @@ -1,8 +1,8 @@ |Logo| -=========================== +*************************** Verilator XML Output Format -=========================== +*************************** Introduction ============ diff --git a/src/pod2latexfix b/src/pod2latexfix deleted file mode 100755 index 6cf21004e..000000000 --- a/src/pod2latexfix +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -###################################################################### -# -# Copyright 2002-2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -# -###################################################################### -# DESCRIPTION: Edits pod2latex output - -use warnings; - -my $Opt_DistTitle = $ARGV[0] or die "%Error: No disttitle specified,"; -my $Opt_DistDate = $ARGV[1] or die "%Error: No distdate specified,"; - -my $header = - ("\\usepackage[left=1.0in,right=1.0in,top=1.0in,bottom=1.0in]{geometry}\n" - ."\\usepackage[pdftex,bookmarks=true,bookmarksnumbered=true,hypertexnames=false,breaklinks=true,colorlinks=true,linkcolor=blue]{hyperref}\n" - ."\\usepackage{fancyhdr} \\pagestyle{fancy}\n" - ."\\usepackage{graphicx}\n" - ."\n" - ."\\setlength{\\parindent}{0pt} \\setlength{\\parskip}{\\baselineskip}\n" - ."\n" - ."\\title{\\includegraphics[width=6cm]{docs/_static/verilator_logo.png}\\\\ ${Opt_DistTitle}}\n" - ."\\date{${Opt_DistDate}}\n" - ."\\author{https:\/\/verilator.org}\n" - ."\\lhead[${Opt_DistTitle}]{${Opt_DistTitle}}\n" - ); - -foreach my $line () { - $line =~ s/(\\begin\{document\})/${header}$1/; - $line =~ s/(\\tableofcontents)/\\begin\{titlepage\} \\maketitle \\end\{titlepage\}\n$1/; - print "$line"; -} diff --git a/test_regress/driver.pl b/test_regress/driver.pl index c33ebb2bb..26ca19722 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -2388,6 +2388,74 @@ sub file_sed { $self->write_wholefile($outfilename, $contents); } +sub extract { + my $self = (ref $_[0]? shift : $Self); + my %param = (#in =>, + #out => + regexp => qr/.*/, + lineno_adjust => -9999, + lines => undef, #'#, #-#', + @_); + + my $temp_fn = $param{out}; + $temp_fn =~ s!.*/!!g; + $temp_fn = $self->{obj_dir} . "/" . $temp_fn; + + my @out; + my $emph = ""; + my $lineno = 0; + my $lineno_out = 0; + { + my $fh = IO::File->new("<$param{in}") or die "%Error: $! $param{in},"; + while (defined(my $line = $fh->getline)) { + ++$lineno; + if ($line =~ /$param{regexp}/ + && _lineno_match($lineno, $param{lines})) { + if ($line =~ m!t/[A-Za-z0-9_]+.v:(\d+):(\d+):!) { + my $lineno = $1; + my $col = $2; + $lineno += $param{lineno_adjust}; + $lineno = 1 if $lineno < 1; + $line =~ s!t/[A-Za-z0-9_]+.v:(\d+):(\d+):!example.v:${lineno}:${col}!; + } + push @out, " " . $line; + ++$lineno_out; + if ($line =~ /<--/) { + $emph .= "," if $emph; + $emph .= $lineno_out; + } + } + } + } + { + my $fhw = IO::File->new(">$temp_fn") or die "%Error: $! $temp_fn,"; + my $lang = ""; + $lang = " sv" if $param{in} =~ /\.s?vh?$/; + $fhw->print(".. comment: generated by " . $self->{name} . "\n"); + $fhw->print(".. code-block::${lang}\n"); + $fhw->print(" :linenos:\n") if $lang && $#out > 0; + $fhw->print(" :emphasize-lines: ${emph}\n") if $emph; + $fhw->print("\n"); + foreach my $line (@out) { + $fhw->print($line); + } + } + + $self->files_identical($temp_fn, $param{out}); +} + +sub _lineno_match { + my $lineno = shift; + my $lines = shift; + return 1 if !defined $lines; + if ($lines =~ /^(\d+)$/) { + return $1 == $lineno; + } elsif ($lines =~ /^(\d+)-(\d+)$/) { + return $1 <= $lineno && $2 >= $lineno; + } + return 0; +} + ####################################################################### ####################################################################### ####################################################################### diff --git a/test_regress/t/t_assert_comp_bad.pl b/test_regress/t/t_assert_comp_bad.pl index b9699fb8a..403e165d7 100755 --- a/test_regress/t/t_assert_comp_bad.pl +++ b/test_regress/t/t_assert_comp_bad.pl @@ -18,5 +18,45 @@ compile( expect_filename => $Self->{golden_filename}, ); +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_USERWARN_faulty.rst", + regexp => qr/\$warn.*User/); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_USERERROR_faulty.rst", + regexp => qr/\$error.*User/); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_USERINFO_faulty.rst", + regexp => qr/\$info.*User/); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_USERFATAL_faulty.rst", + regexp => qr/\$fatal.*User/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_USERWARN_msg.rst", + regexp => qr/USERWARN:.* User/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_USERERROR_msg.rst", + regexp => qr/USERERROR:.* User/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_USERINFO_msg.rst", + regexp => qr/-Info:.* User/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_USERFATAL_msg.rst", + regexp => qr/USERFATAL/); + ok(1); 1; diff --git a/test_regress/t/t_lint_width_docs_bad.out b/test_regress/t/t_lint_width_docs_bad.out new file mode 100644 index 000000000..132dc2e6d --- /dev/null +++ b/test_regress/t/t_lint_width_docs_bad.out @@ -0,0 +1,6 @@ +%Warning-WIDTH: t/t_lint_width_docs_bad.v:10:29: Bit extraction of array[4:0] requires 3 bit index, not 2 bits. + : ... In instance t + 10 | wire int rd_value = array[rd_addr]; + | ^ + ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_lint_width_docs_bad.pl b/test_regress/t/t_lint_width_docs_bad.pl new file mode 100755 index 000000000..1afe476b9 --- /dev/null +++ b/test_regress/t/t_lint_width_docs_bad.pl @@ -0,0 +1,36 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + verilator_flags2 => ["--lint-only"], + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_WIDTH_1_faulty.rst", + lines => "8-10"); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_WIDTH_1_msg.rst", + lineno_adjust => -7, + regexp => qr/Warning-WIDTH/); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_WIDTH_1_fixed.rst", + lines => "18"); + +ok(1); +1; diff --git a/test_regress/t/t_lint_width_docs_bad.v b/test_regress/t/t_lint_width_docs_bad.v new file mode 100644 index 000000000..1a99073a0 --- /dev/null +++ b/test_regress/t/t_lint_width_docs_bad.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = array[rd_addr]; //<--- Warning + + ok ok(); +endmodule + +module ok; + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = array[{1'b0, rd_addr}]; //<--- Fixed +endmodule; diff --git a/test_regress/t/t_var_bad_hide_docs.out b/test_regress/t/t_var_bad_hide_docs.out new file mode 100644 index 000000000..3ce6c7460 --- /dev/null +++ b/test_regress/t/t_var_bad_hide_docs.out @@ -0,0 +1,8 @@ +%Warning-VARHIDDEN: t/t_var_bad_hide_docs.v:8:12: Declaration of signal hides declaration in upper scope: 't' + 8 | integer t; + | ^ + t/t_var_bad_hide_docs.v:7:8: ... Location of original declaration + 7 | module t; + | ^ + ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_var_bad_hide_docs.pl b/test_regress/t/t_var_bad_hide_docs.pl new file mode 100755 index 000000000..f43bd4b48 --- /dev/null +++ b/test_regress/t/t_var_bad_hide_docs.pl @@ -0,0 +1,31 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_VARHIDDEN_faulty.rst", + regexp => qr/(module t|integer|endmodule)/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_VARHIDDEN_msg.rst", + lineno_adjust => -6, + regexp => qr/(var_bad_hide)/); + +ok(1); +1; diff --git a/test_regress/t/t_var_bad_hide_docs.v b/test_regress/t/t_var_bad_hide_docs.v new file mode 100644 index 000000000..964f69f5a --- /dev/null +++ b/test_regress/t/t_var_bad_hide_docs.v @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + integer t; //<--- Warning ('t' hidden by module 't') +endmodule diff --git a/test_regress/t/t_width_docs_bad.v b/test_regress/t/t_width_docs_bad.v new file mode 100644 index 000000000..13ed51756 --- /dev/null +++ b/test_regress/t/t_width_docs_bad.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = read_array[rd_addr]; //<--- Warning + + ok ok(); +endmodule + +module ok; + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = read_array[{1'b0, rd_addr}]; //<--- Fixed +endmodule;