diff --git a/test_regress/t/t_split_var_0.v b/test_regress/t/t_split_var_0.v
index 5a9fc1346..514fb6803 100644
--- a/test_regress/t/t_split_var_0.v
+++ b/test_regress/t/t_split_var_0.v
@@ -5,306 +5,313 @@
 
 // If split_var pragma is removed, UNOPTFLAT appears.
 
-module barshift_1d_unpacked #(parameter depth = 2, localparam width = 2**depth) (
-    input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
+module barshift_1d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
+   (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
 
-    localparam offset = -3;
-    logic [width-1:0] tmp[depth+offset:offset]; /*verilator split_var*/
-    generate
-        for(genvar i = 0; i < depth; ++i) begin
+   localparam OFFSET = -3;
+   logic [WIDTH-1:0] tmp[DEPTH+OFFSET:OFFSET]; /*verilator split_var*/
+   generate
+      for(genvar i = 0; i < DEPTH; ++i) begin
+         always_comb
+           if (shift[i]) begin
+              tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
+           end
+           else begin
+              tmp[i+1+OFFSET] = tmp[i+OFFSET];
+           end
+      end
+   endgenerate
+   assign tmp[0+OFFSET] = in;
+   assign out = tmp[DEPTH+OFFSET];
+endmodule
+
+
+module barshift_1d_unpacked_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
+   (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
+
+   localparam OFFSET = -3;
+   // almost same as above module, but tmp[smaller:bigger] here.
+   logic [WIDTH-1:0] tmp[OFFSET:DEPTH+OFFSET]; /*verilator split_var*/
+   generate
+      for(genvar i = 0; i < DEPTH; ++i) begin
+         always_comb
+           if (shift[i]) begin
+              tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
+           end
+           else begin
+              tmp[i+1+OFFSET] = tmp[i+OFFSET];
+           end
+      end
+   endgenerate
+   assign tmp[0+OFFSET] = in;
+   assign out = tmp[DEPTH+OFFSET];
+endmodule
+
+
+module barshift_1d_unpacked_struct0 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
+   (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
+
+   localparam OFFSET = 1;
+   typedef struct packed { logic [WIDTH-1:0] data; } data_type;
+   data_type tmp[DEPTH+OFFSET:OFFSET]; /*verilator split_var*/
+   generate
+      for(genvar i = 0; i < DEPTH; ++i) begin
+         always_comb
+           if (shift[i]) begin
+              tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
+           end
+           else begin
+              tmp[i+1+OFFSET] = tmp[i+OFFSET];
+           end
+      end
+   endgenerate
+   assign tmp[0+OFFSET] = in;
+   assign out = tmp[DEPTH+OFFSET];
+endmodule
+
+
+module barshift_2d_unpacked #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
+   (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
+
+   localparam OFFSET = 1;
+   localparam N = 3;
+   reg [WIDTH-1:0] tmp0[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+   reg [WIDTH-1:0] tmp1[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+   reg [WIDTH-1:0] tmp2[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1];
+   reg [WIDTH-1:0] tmp3[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+   reg [WIDTH-1:0] tmp4[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+   reg [WIDTH-1:0] tmp5[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1];
+   reg [WIDTH-1:0] tmp6[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+
+   reg [WIDTH-1:0] tmp7[DEPTH+OFFSET+1:OFFSET+1][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+   reg [WIDTH-1:0] tmp8[DEPTH+OFFSET+3:OFFSET-1][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+   reg [WIDTH-1:0] tmp9[DEPTH+OFFSET+3:OFFSET+3][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+   reg [WIDTH-1:0] tmp10[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+   // because tmp11 is not split for testing mixture usage of split_var and no-spliv_ar,
+   // UNOPTFLAT appears, but it's fine.
+   /*verilator lint_off UNOPTFLAT*/
+   reg [WIDTH-1:0] tmp11[-1:1][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1];
+   /*verilator lint_on UNOPTFLAT*/
+   reg [WIDTH-1:0] tmp12[-1:0][DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+   reg [WIDTH-1:0] tmp13[DEPTH+OFFSET:OFFSET][OFFSET:OFFSET+N-1]; /*verilator split_var*/
+
+   generate
+      for(genvar i = 0; i < DEPTH; ++i) begin
+         for(genvar j = OFFSET; j < N + OFFSET; ++j) begin
             always_comb
-            if (shift[i]) begin
-                tmp[i+1+offset] = {tmp[i+offset][(1 << i)-1:0], tmp[i+offset][width-1:(2**i)]};
-            end else begin
-                tmp[i+1+offset] = tmp[i+offset];
-            end
-        end
-    endgenerate
-    assign tmp[0+offset] = in;
-    assign out = tmp[depth+offset];
+              if (shift[i]) begin
+                 tmp0[i+1+OFFSET][j] = {tmp0[i+OFFSET][j][(1 << i)-1:0], tmp0[i+OFFSET][j][WIDTH-1:(2**i)]};
+              end
+              else begin
+                 tmp0[i+1+OFFSET][j] = tmp0[i+OFFSET][j];
+              end
+         end
+      end
+      for(genvar j = OFFSET; j < N + OFFSET; ++j) begin
+         assign tmp0[0 + OFFSET][j] = in;
+      end
+   endgenerate
+   assign tmp1 = tmp0;  // split both side
+   assign tmp2 = tmp1;  // split only rhs
+   assign tmp3 = tmp2;  // split only lhs
+   always_comb tmp4 = tmp3; // split both side
+   always_comb tmp5 = tmp4; // split only rhs
+   always_comb tmp6 = tmp5; // split only lhs
+
+   assign tmp7 = tmp6;
+   assign tmp8[DEPTH+OFFSET+1:OFFSET+1] = tmp7;
+   assign tmp9 = tmp8[DEPTH+OFFSET+1:OFFSET+1];
+   assign tmp10[DEPTH+OFFSET:OFFSET] = tmp9[DEPTH+OFFSET+3:OFFSET+3];
+   assign tmp11[1] = tmp10;
+   assign tmp11[-1] = tmp11[1];
+   assign tmp11[0] = tmp11[-1];
+   assign tmp12 = tmp11[0:1];
+   assign out = tmp12[1][DEPTH+OFFSET][OFFSET];
 endmodule
 
 
-module barshift_1d_unpacked_le #(parameter depth = 2, localparam width = 2**depth) (
-    input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
+module barshift_1d_unpacked_struct1 #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
+   (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
 
-    localparam offset = -3;
-    // almost same as above module, but tmp[smaller:bigger] here.
-    logic [width-1:0] tmp[offset:depth+offset]; /*verilator split_var*/
-    generate
-        for(genvar i = 0; i < depth; ++i) begin
-            always_comb
-            if (shift[i]) begin
-                tmp[i+1+offset] = {tmp[i+offset][(1 << i)-1:0], tmp[i+offset][width-1:(2**i)]};
-            end else begin
-                tmp[i+1+offset] = tmp[i+offset];
-            end
-        end
-    endgenerate
-    assign tmp[0+offset] = in;
-    assign out = tmp[depth+offset];
+   localparam OFFSET = 2;
+   typedef struct packed { int data; } data_type;
+   data_type tmp[DEPTH+OFFSET:OFFSET]; /*verilator split_var*/
+
+   localparam [32-WIDTH-1:0] pad = 0;
+   generate
+      for(genvar i = 0; i < DEPTH; ++i) begin
+         always_comb
+           if (shift[i]) begin
+              tmp[i+1+OFFSET] = {pad, tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
+           end
+           else begin
+              tmp[i+1+OFFSET] = tmp[i+OFFSET];
+           end
+      end
+   endgenerate
+   assign tmp[0+OFFSET] = {pad, in};
+   assign out = tmp[DEPTH+OFFSET][WIDTH-1:0];
 endmodule
 
 
+module barshift_2d_packed_array #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
+   (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
 
-module barshift_1d_unpacked_struct0 #(parameter depth = 2, localparam width = 2**depth) (
-    input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
+   localparam OFFSET = -2;
+   /*verilator lint_off LITENDIAN*/
+   reg [OFFSET:DEPTH+OFFSET][WIDTH-1:0] tmp; /*verilator split_var*/
+   /*verilator lint_on LITENDIAN*/
 
-    localparam offset = 1;
-    typedef struct packed { logic [width-1:0] data; } data_type;
-    data_type tmp[depth+offset:offset]; /*verilator split_var*/
-    generate
-        for(genvar i = 0; i < depth; ++i) begin
-            always_comb
-            if (shift[i]) begin
-                tmp[i+1+offset] = {tmp[i+offset][(1 << i)-1:0], tmp[i+offset][width-1:(2**i)]};
-            end else begin
-                tmp[i+1+offset] = tmp[i+offset];
-            end
-        end
-    endgenerate
-    assign tmp[0+offset] = in;
-    assign out = tmp[depth+offset];
+   generate
+      for(genvar i = 0; i < DEPTH; ++i) begin
+         always_comb
+           /*verilator lint_off ALWCOMBORDER*/
+           if (shift[i]) begin
+              tmp[i+1+OFFSET] = {tmp[i+OFFSET][(1 << i)-1:0], tmp[i+OFFSET][WIDTH-1:(2**i)]};
+           end
+           else begin
+              tmp[i+1+OFFSET][1:0]       = tmp[i+OFFSET][1:0];
+              tmp[i+1+OFFSET][WIDTH-1:2] = tmp[i+OFFSET][WIDTH-1:2];
+           end
+         /*verilator lint_on ALWCOMBORDER*/
+      end
+   endgenerate
+   assign tmp[0+OFFSET] = in;
+   assign out = tmp[DEPTH+OFFSET];
 endmodule
 
 
-module barshift_2d_unpacked #(parameter depth = 2, localparam width = 2**depth) (
-    input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
+module barshift_2d_packed_array_le #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
+   (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
 
-    localparam offset = 1;
-    localparam n = 3;
-    reg [width-1:0]tmp0[depth+offset:offset][offset:offset+n-1]; /*verilator split_var*/
-    reg [width-1:0]tmp1[depth+offset:offset][offset:offset+n-1]; /*verilator split_var*/
-    reg [width-1:0]tmp2[depth+offset:offset][offset:offset+n-1];
-    reg [width-1:0]tmp3[depth+offset:offset][offset:offset+n-1]; /*verilator split_var*/
-    reg [width-1:0]tmp4[depth+offset:offset][offset:offset+n-1]; /*verilator split_var*/
-    reg [width-1:0]tmp5[depth+offset:offset][offset:offset+n-1];
-    reg [width-1:0]tmp6[depth+offset:offset][offset:offset+n-1]; /*verilator split_var*/
+   localparam OFFSET = -2;
+   /*verilator lint_off LITENDIAN*/
+   reg [OFFSET:DEPTH+OFFSET][OFFSET:WIDTH-1+OFFSET] tmp; /*verilator split_var*/
+   /*verilator lint_on LITENDIAN*/
 
-    reg [width-1:0]tmp7[depth+offset+1:offset+1][offset:offset+n-1]; /*verilator split_var*/
-    reg [width-1:0]tmp8[depth+offset+3:offset-1][offset:offset+n-1]; /*verilator split_var*/
-    reg [width-1:0]tmp9[depth+offset+3:offset+3][offset:offset+n-1]; /*verilator split_var*/
-    reg [width-1:0]tmp10[depth+offset:offset][offset:offset+n-1]; /*verilator split_var*/
-    // because tmp11 is not split for testing mixture usage of split_var and no-spliv_ar,
-    // UNOPTFLAT appears, but it's fine.
-    /*verilator lint_off UNOPTFLAT*/
-    reg [width-1:0]tmp11[-1:1][depth+offset:offset][offset:offset+n-1];
-    /*verilator lint_on UNOPTFLAT*/
-    reg [width-1:0]tmp12[-1:0][depth+offset:offset][offset:offset+n-1]; /*verilator split_var*/
-    reg [width-1:0]tmp13[depth+offset:offset][offset:offset+n-1]; /*verilator split_var*/
-
-    generate
-        for(genvar i = 0; i < depth; ++i) begin
-            for(genvar j = offset; j < n + offset; ++j) begin
-                always_comb
-                    if (shift[i]) begin
-                        tmp0[i+1+offset][j] = {tmp0[i+offset][j][(1 << i)-1:0], tmp0[i+offset][j][width-1:(2**i)]};
-                    end else begin
-                        tmp0[i+1+offset][j] = tmp0[i+offset][j];
-                    end
-            end
-        end
-        for(genvar j = offset; j < n + offset; ++j) begin
-            assign tmp0[0 + offset][j] = in;
-        end
-    endgenerate
-    assign tmp1 = tmp0;  // split both side
-    assign tmp2 = tmp1;  // split only rhs
-    assign tmp3 = tmp2;  // split only lhs
-    always_comb tmp4 = tmp3; // split both side
-    always_comb tmp5 = tmp4; // split only rhs
-    always_comb tmp6 = tmp5; // split only lhs
-
-    assign tmp7 = tmp6;
-    assign tmp8[depth+offset+1:offset+1] = tmp7;
-    assign tmp9 = tmp8[depth+offset+1:offset+1];
-    assign tmp10[depth+offset:offset] = tmp9[depth+offset+3:offset+3];
-    assign tmp11[1] = tmp10;
-    assign tmp11[-1] = tmp11[1];
-    assign tmp11[0] = tmp11[-1];
-    assign tmp12 = tmp11[0:1];
-    assign out = tmp12[1][depth+offset][offset];
+   generate
+      for(genvar i = 0; i < DEPTH; ++i) begin
+         always_comb
+           /*verilator lint_off ALWCOMBORDER*/
+           if (shift[i]) begin
+              tmp[i+1+OFFSET] = {tmp[i+OFFSET][WIDTH-(2**i)+OFFSET:WIDTH-1+OFFSET], tmp[i+OFFSET][OFFSET:WIDTH-(2**i)-1+OFFSET]};
+           end
+           else begin  // actulally just tmp[i+1+OFFSET] = tmp[i+OFFSET]
+              tmp[i+1+OFFSET][0+OFFSET:2+OFFSET]  = tmp[i+OFFSET][0+OFFSET:2+OFFSET];
+              tmp[i+1+OFFSET][3+OFFSET]           = tmp[i+OFFSET][3+OFFSET];
+              {tmp[i+1+OFFSET][4+OFFSET],tmp[i+1+OFFSET][5+OFFSET]} = {tmp[i+OFFSET][4+OFFSET], tmp[i+OFFSET][5+OFFSET]};
+              {tmp[i+1+OFFSET][7+OFFSET],tmp[i+1+OFFSET][6+OFFSET]} = {tmp[i+OFFSET][7+OFFSET], tmp[i+OFFSET][6+OFFSET]};
+           end
+         /*verilator lint_on ALWCOMBORDER*/
+      end
+   endgenerate
+   assign tmp[0+OFFSET] = in;
+   assign out = tmp[DEPTH+OFFSET];
 endmodule
 
 
-module barshift_1d_unpacked_struct1 #(parameter depth = 2, localparam width = 2**depth) (
-    input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
+module barshift_1d_packed_struct #(localparam DEPTH = 3, localparam WIDTH = 2**DEPTH)
+   (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
 
-    localparam offset = 2;
-    typedef struct packed { int data; } data_type;
-    data_type tmp[depth+offset:offset]; /*verilator split_var*/
+   typedef struct packed {
+      logic [WIDTH-1:0] v0, v1, v2, v3;
+   } data_type;
+   wire data_type tmp; /*verilator split_var*/
 
-    localparam [32-width-1:0] pad = 0;
-    generate
-        for(genvar i = 0; i < depth; ++i) begin
-            always_comb
-            if (shift[i]) begin
-                tmp[i+1+offset] = {pad, tmp[i+offset][(1 << i)-1:0], tmp[i+offset][width-1:(2**i)]};
-            end else begin
-                tmp[i+1+offset] = tmp[i+offset];
-            end
-        end
-    endgenerate
-    assign tmp[0+offset] = {pad, in};
-    assign out = tmp[depth+offset][width-1:0];
+   assign tmp.v0 = in;
+   assign tmp.v1 = shift[0] == 1'b1 ? {tmp.v0[(1 << 0)-1:0], tmp.v0[WIDTH-1:2**0]} : tmp.v0;
+   assign tmp.v2 = shift[1] == 1'b1 ? {tmp.v1[(1 << 1)-1:0], tmp.v1[WIDTH-1:2**1]} : tmp.v1;
+   assign tmp.v3 = shift[2] == 1'b1 ? {tmp.v2[(1 << 2)-1:0], tmp.v2[WIDTH-1:2**2]} : tmp.v2;
+   assign out = tmp.v3;
 endmodule
 
 
-module barshift_2d_packed_array #(parameter depth = 2, localparam width = 2**depth) (
-    input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
+module barshift_bitslice #(parameter DEPTH = 2, localparam WIDTH = 2**DEPTH)
+   (input [WIDTH-1:0] in, input [DEPTH-1:0] shift, output [WIDTH-1:0] out);
 
-    localparam offset = -2;
-    /*verilator lint_off LITENDIAN*/
-    reg [offset:depth+offset][width-1:0] tmp; /*verilator split_var*/
-    /*verilator lint_on LITENDIAN*/
+   /*verilator lint_off LITENDIAN*/
+   wire [0:WIDTH*(DEPTH+1) - 1] tmp; /*verilator split_var*/
+   /*verilator lint_on LITENDIAN*/
 
-    generate
-        for(genvar i = 0; i < depth; ++i) begin
-            always_comb
-            /*verilator lint_off ALWCOMBORDER*/
-            if (shift[i]) begin
-                tmp[i+1+offset] = {tmp[i+offset][(1 << i)-1:0], tmp[i+offset][width-1:(2**i)]};
-            end else begin
-                tmp[i+1+offset][1:0]       = tmp[i+offset][1:0];
-                tmp[i+1+offset][width-1:2] = tmp[i+offset][width-1:2];
-            end
-            /*verilator lint_on ALWCOMBORDER*/
-        end
-    endgenerate
-    assign tmp[0+offset] = in;
-    assign out = tmp[depth+offset];
-endmodule
-
-
-module barshift_2d_packed_array_le #(parameter depth = 2, localparam width = 2**depth) (
-    input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
-
-    localparam offset = -2;
-    /*verilator lint_off LITENDIAN*/
-    reg [offset:depth+offset][offset:width-1+offset] tmp; /*verilator split_var*/
-    /*verilator lint_on LITENDIAN*/
-
-    generate
-        for(genvar i = 0; i < depth; ++i) begin
-            always_comb
-            /*verilator lint_off ALWCOMBORDER*/
-            if (shift[i]) begin
-                tmp[i+1+offset] = {tmp[i+offset][width-(2**i)+offset:width-1+offset], tmp[i+offset][offset:width-(2**i)-1+offset]};
-            end else begin  // actulally just tmp[i+1+offset] = tmp[i+offset]
-                tmp[i+1+offset][0+offset:2+offset]  = tmp[i+offset][0+offset:2+offset];
-                tmp[i+1+offset][3+offset]           = tmp[i+offset][3+offset];
-                {tmp[i+1+offset][4+offset],tmp[i+1+offset][5+offset]} = {tmp[i+offset][4+offset], tmp[i+offset][5+offset]};
-                {tmp[i+1+offset][7+offset],tmp[i+1+offset][6+offset]} = {tmp[i+offset][7+offset], tmp[i+offset][6+offset]};
-            end
-            /*verilator lint_on ALWCOMBORDER*/
-        end
-    endgenerate
-    assign tmp[0+offset] = in;
-    assign out = tmp[depth+offset];
-endmodule
-
-
-module barshift_1d_packed_struct #(localparam depth = 3, localparam width = 2**depth) (
-    input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
-
-    typedef struct packed {
-        logic [width-1:0] v0, v1, v2, v3;
-    } data_type;
-    wire data_type tmp; /*verilator split_var*/
-
-    assign tmp.v0 = in;
-    assign tmp.v1 = shift[0] == 1'b1 ? {tmp.v0[(1 << 0)-1:0], tmp.v0[width-1:2**0]} : tmp.v0;
-    assign tmp.v2 = shift[1] == 1'b1 ? {tmp.v1[(1 << 1)-1:0], tmp.v1[width-1:2**1]} : tmp.v1;
-    assign tmp.v3 = shift[2] == 1'b1 ? {tmp.v2[(1 << 2)-1:0], tmp.v2[width-1:2**2]} : tmp.v2;
-    assign out = tmp.v3;
-endmodule
-
-
-module barshift_bitslice #(parameter depth = 2, localparam width = 2**depth) (
-    input [width-1:0] in, input [depth-1:0] shift, output [width-1:0]out);
-
-    /*verilator lint_off LITENDIAN*/
-    wire [0:width*(depth+1) - 1] tmp; /*verilator split_var*/
-    /*verilator lint_on LITENDIAN*/
-
-    generate
-        for(genvar i = 0; i < depth; ++i) begin
-            always_comb
-            if (shift[i]) begin
-                tmp[width*(i+1):width*(i+1+1)-1] = {tmp[width*(i+1)-(1<<i):width*(i+1)-1], tmp[width*i:width*i+((width-1) - (2**i))]};
-            end else begin
-                tmp[width*(i+1):width*(i+1+1)-1] = tmp[width*i:width*(i+1)-1];
-            end
-        end
-    endgenerate
-    assign tmp[width*0:width*(0+1)-1] = in;
-    assign out = tmp[width*depth:width*(depth+1)-1];
+   generate
+      for(genvar i = 0; i < DEPTH; ++i) begin
+         always_comb
+           if (shift[i]) begin
+              tmp[WIDTH*(i+1):WIDTH*(i+1+1)-1] = {tmp[WIDTH*(i+1)-(1<<i):WIDTH*(i+1)-1], tmp[WIDTH*i:WIDTH*i+((WIDTH-1) - (2**i))]};
+           end
+           else begin
+              tmp[WIDTH*(i+1):WIDTH*(i+1+1)-1] = tmp[WIDTH*i:WIDTH*(i+1)-1];
+           end
+      end
+   endgenerate
+   assign tmp[WIDTH*0:WIDTH*(0+1)-1] = in;
+   assign out = tmp[WIDTH*DEPTH:WIDTH*(DEPTH+1)-1];
 endmodule
 
 
 module var_decl_with_init();
 
-    /*verilator lint_off LITENDIAN*/
-logic [-1:30] var0 = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; /* verilator split_var */
-logic [-1:30] var2; /* verilator split_var */
-    /*verilator lint_on LITENDIAN*/
-logic [30:-1] var1 = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; /* verilator split_var */
-logic [30:-1] var3; /* verilator split_var */
+   /*verilator lint_off LITENDIAN*/
+   logic [-1:30] var0 = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; /* verilator split_var */
+   logic [-1:30] var2; /* verilator split_var */
+   /*verilator lint_on LITENDIAN*/
+   logic [30:-1] var1 = {4'd0, 4'd1, 4'd2, 4'd3, 4'd4, 4'd5, 4'd6, 4'd7}; /* verilator split_var */
+   logic [30:-1] var3; /* verilator split_var */
 
-initial begin
-    var2[-1:2] = 4'd2;
-    var3[2:-1] = 4'd3;
-    $display("%x %x", var0, var1);
-    $display("%x %x", var2, var3);
-    var0[-1:5] = 7'd0;
-    var1[10:3] = 8'd2;
-end
+   initial begin
+      var2[-1:2] = 4'd2;
+      var3[2:-1] = 4'd3;
+      $display("%x %x", var0, var1);
+      $display("%x %x", var2, var3);
+      var0[-1:5] = 7'd0;
+      var1[10:3] = 8'd2;
+   end
 
 endmodule
 
 
 module t(/*AUTOARG*/ clk);
-    input clk;
-    localparam depth = 3;
-    localparam width = 2**depth;
-    localparam numsub = 9;
-    logic [width-1:0] in;
-    logic [width-1:0] out[0:numsub-1];
-    logic [depth-1:0] shift = 0;
+   input clk;
+   localparam DEPTH = 3;
+   localparam WIDTH = 2**DEPTH;
+   localparam NUMSUB = 9;
+   logic [WIDTH-1:0] in;
+   logic [WIDTH-1:0] out[0:NUMSUB-1];
+   logic [DEPTH-1:0] shift = 0;
 
-    // barrel shifter
-    barshift_1d_unpacked         #(.depth(depth)) shifter0(.in(in), .out(out[0]), .shift(shift));
-    barshift_1d_unpacked_le      #(.depth(depth)) shifter1(.in(in), .out(out[1]), .shift(shift));
-    barshift_1d_unpacked_struct0 #(.depth(depth)) shifter2(.in(in), .out(out[2]), .shift(shift));
-    barshift_2d_unpacked         #(.depth(depth)) shifter3(.in(in), .out(out[3]), .shift(shift));
-    barshift_1d_unpacked_struct1 #(.depth(depth)) shifter4(.in(in), .out(out[4]), .shift(shift));
-    barshift_2d_packed_array     #(.depth(depth)) shifter5(.in(in), .out(out[5]), .shift(shift));
-    barshift_2d_packed_array_le  #(.depth(depth)) shifter6(.in(in), .out(out[6]), .shift(shift));
-    barshift_1d_packed_struct                     shifter7(.in(in), .out(out[7]), .shift(shift));
-    barshift_bitslice            #(.depth(depth)) shifter8(.in(in), .out(out[8]), .shift(shift));
-    var_decl_with_init i_var_decl_with_init();
+   // barrel shifter
+   barshift_1d_unpacked         #(.DEPTH(DEPTH)) shifter0(.in(in), .out(out[0]), .shift(shift));
+   barshift_1d_unpacked_le      #(.DEPTH(DEPTH)) shifter1(.in(in), .out(out[1]), .shift(shift));
+   barshift_1d_unpacked_struct0 #(.DEPTH(DEPTH)) shifter2(.in(in), .out(out[2]), .shift(shift));
+   barshift_2d_unpacked         #(.DEPTH(DEPTH)) shifter3(.in(in), .out(out[3]), .shift(shift));
+   barshift_1d_unpacked_struct1 #(.DEPTH(DEPTH)) shifter4(.in(in), .out(out[4]), .shift(shift));
+   barshift_2d_packed_array     #(.DEPTH(DEPTH)) shifter5(.in(in), .out(out[5]), .shift(shift));
+   barshift_2d_packed_array_le  #(.DEPTH(DEPTH)) shifter6(.in(in), .out(out[6]), .shift(shift));
+   barshift_1d_packed_struct                     shifter7(.in(in), .out(out[7]), .shift(shift));
+   barshift_bitslice            #(.DEPTH(DEPTH)) shifter8(.in(in), .out(out[8]), .shift(shift));
+   var_decl_with_init i_var_decl_with_init();
 
-    assign in = 8'b10001110;
-    /*verilator lint_off LITENDIAN*/
-    logic [7:0] [7:0] exp = {
-        8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001,
-        8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101};
-    /*verilator lint_on LITENDIAN*/
-    always @(posedge clk) begin : always_block
-        automatic bit failed = 0;
-        $display("in:%b shift:%d exp:%b", in, shift, exp[7-shift]);
-        for (int i = 0; i < numsub; ++i) begin
-            if (out[i] != exp[7-shift]) begin
-                $display("Missmatch out[%d]:%b", i, out[i]);
-                failed = 1;
-            end
-        end
-        if (failed) $stop;
-        if (shift == 7) begin
-            $write("*-* All Finished *-*\n");
-            $finish;
-        end
-        shift <= shift + 1;
-    end
+   assign in = 8'b10001110;
+   /*verilator lint_off LITENDIAN*/
+   logic [7:0] [7:0] expc
+               = {8'b10001110, 8'b01000111, 8'b10100011, 8'b11010001,
+                  8'b11101000, 8'b01110100, 8'b00111010, 8'b00011101};
+   /*verilator lint_on LITENDIAN*/
+   always @(posedge clk) begin : always_block
+      automatic bit failed = 0;
+      $display("in:%b shift:%d expc:%b", in, shift, expc[7-shift]);
+      for (int i = 0; i < NUMSUB; ++i) begin
+         if (out[i] != expc[7-shift]) begin
+            $display("Missmatch out[%d]:%b", i, out[i]);
+            failed = 1;
+         end
+      end
+      if (failed) $stop;
+      if (shift == 7) begin
+         $write("*-* All Finished *-*\n");
+         $finish;
+      end
+      shift <= shift + 1;
+   end
 
 endmodule
diff --git a/test_regress/t/t_split_var_1_bad.out b/test_regress/t/t_split_var_1_bad.out
index 7085a600d..570ffb2bf 100644
--- a/test_regress/t/t_split_var_1_bad.out
+++ b/test_regress/t/t_split_var_1_bad.out
@@ -1,26 +1,26 @@
 %Warning-SPLITVAR: t/t_split_var_1_bad.v:7: Unexpected location for split_var pragma.
                                           : ... In instance t
-      /*verilator split_var*/ 
-      ^~~~~~~~~~~~~~~~~~~~~~~
+     /*verilator split_var*/ 
+     ^~~~~~~~~~~~~~~~~~~~~~~
                    ... Use "/* verilator lint_off SPLITVAR */" and lint_on around source to disable this message.
 %Warning-SPLITVAR: t/t_split_var_1_bad.v:33: Variable 'cannot_split' will not be split because index cannot be determined statically.
                                            : ... In instance t.i_sub0
-        rd_data = cannot_split[addr];
-                               ^~~~
+     rd_data = cannot_split[addr];
+                            ^~~~
 %Warning-SPLITVAR: t/t_split_var_1_bad.v:10: Pragma split_var is specified on a variable whose type is unsupported or public. Packed portion must be an aggregate type of bit or logic.
                                            : ... In instance t
-    real should_show_warning0;                 /*verilator split_var*/ 
-         ^~~~~~~~~~~~~~~~~~~~
+   real should_show_warning0;                 /*verilator split_var*/ 
+        ^~~~~~~~~~~~~~~~~~~~
 %Warning-SPLITVAR: t/t_split_var_1_bad.v:11: Pragma split_var is specified on a variable whose type is unsupported or public. Packed portion must be an aggregate type of bit or logic.
                                            : ... In instance t
-    string should_show_warning1[0:2];          /*verilator split_var*/ 
-           ^~~~~~~~~~~~~~~~~~~~
+   string should_show_warning1[0:2];          /*verilator split_var*/ 
+          ^~~~~~~~~~~~~~~~~~~~
 %Warning-SPLITVAR: t/t_split_var_1_bad.v:12: Pragma split_var is specified on a variable whose type is unsupported or public. Packed portion must be an aggregate type of bit or logic.
                                            : ... In instance t
-    wire   should_show_warning2;               /*verilator split_var*/ 
-           ^~~~~~~~~~~~~~~~~~~~
+   wire   should_show_warning2;               /*verilator split_var*/ 
+          ^~~~~~~~~~~~~~~~~~~~
 %Warning-SPLITVAR: t/t_split_var_1_bad.v:42: Variable 'cannot_split' will not be split because bit range cannot be determined statically.
                                            : ... In instance t.i_sub1
-        rd_data = cannot_split[addr];
-                              ^
+     rd_data = cannot_split[addr];
+                           ^
 %Error: Exiting due to
diff --git a/test_regress/t/t_split_var_1_bad.pl b/test_regress/t/t_split_var_1_bad.pl
index d476b3e5a..9beaea978 100755
--- a/test_regress/t/t_split_var_1_bad.pl
+++ b/test_regress/t/t_split_var_1_bad.pl
@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     fails => 1,
-    verilator_flags2 => ['--stats '],
+    verilator_flags2 => ['--stats'],
     expect_filename => $Self->{golden_filename},
 );
 
diff --git a/test_regress/t/t_split_var_1_bad.v b/test_regress/t/t_split_var_1_bad.v
index 8ede96633..7e964d5c6 100644
--- a/test_regress/t/t_split_var_1_bad.v
+++ b/test_regress/t/t_split_var_1_bad.v
@@ -4,41 +4,41 @@
 // without warranty, 2020 by Yutetsu TAKATSUKASA.
 
 module t();
-    /*stray pragma */ /*verilator split_var*/
+   /*stray pragma */ /*verilator split_var*/
 
-    // The following variables can not be splitted. will see warnings.
-    real should_show_warning0;                 /*verilator split_var*/
-    string should_show_warning1[0:2];          /*verilator split_var*/
-    wire   should_show_warning2;               /*verilator split_var*/
+   // The following variables can not be splitted. will see warnings.
+   real should_show_warning0;                 /*verilator split_var*/
+   string should_show_warning1[0:2];          /*verilator split_var*/
+   wire   should_show_warning2;               /*verilator split_var*/
 
-    logic [3:0] addr;
-    logic [7:0] rd_data0, rd_data1, rd_data2;
+   logic [3:0] addr;
+   logic [7:0] rd_data0, rd_data1, rd_data2;
 
-    sub0 i_sub0(.addr(addr), .rd_data(rd_data0));
-    sub1 i_sub1(.addr(addr), .rd_data(rd_data2));
+   sub0 i_sub0(.addr(addr), .rd_data(rd_data0));
+   sub1 i_sub1(.addr(addr), .rd_data(rd_data2));
 
-    initial begin
-        addr = 0;
-        addr = 1;
-        $finish;
-    end
+   initial begin
+      addr = 0;
+      addr = 1;
+      $finish;
+   end
 
 endmodule
 
 
 module sub0(input [3:0]addr, output logic [7:0] rd_data);
 
-    logic [7:0] cannot_split[0:15];  /*verilator split_var*/
-    always_comb
-        rd_data = cannot_split[addr];
+   logic [7:0] cannot_split[0:15];  /*verilator split_var*/
+   always_comb
+     rd_data = cannot_split[addr];
 
 endmodule
 
 
 module sub1(input [3:0]addr, output logic [7:0] rd_data);
 
-    logic [15:0] [7:0] cannot_split;  /*verilator split_var*/
-    always_comb
-        rd_data = cannot_split[addr];
+   logic [15:0] [7:0] cannot_split;  /*verilator split_var*/
+   always_comb
+     rd_data = cannot_split[addr];
 
 endmodule
diff --git a/test_regress/t/t_split_var_2_trace.out b/test_regress/t/t_split_var_2_trace.out
index 2ef18c824..399000f61 100644
--- a/test_regress/t/t_split_var_2_trace.out
+++ b/test_regress/t/t_split_var_2_trace.out
@@ -1,16 +1,17 @@
 $version Generated by VerilatedVcd $end
-$date Sat Jan 18 18:46:00 2020
+$date Sun Feb  9 18:25:53 2020
  $end
 $timescale   1ns $end
 
  $scope module top $end
   $var wire  1 #( clk $end
   $scope module t $end
+   $var wire 32 +( DEPTH [31:0] $end
+   $var wire 32 ;( NUMSUB [31:0] $end
+   $var wire 32 3( WIDTH [31:0] $end
    $var wire  1 #( clk $end
-   $var wire 32 +( depth [31:0] $end
-   $var wire 64 K( exp [63:0] $end
+   $var wire 64 K( expc [63:0] $end
    $var wire  8 C( in [7:0] $end
-   $var wire 32 ;( numsub [31:0] $end
    $var wire  8 %% out(0) [7:0] $end
    $var wire  8 &% out(1) [7:0] $end
    $var wire  8 '% out(2) [7:0] $end
@@ -21,7 +22,6 @@ $timescale   1ns $end
    $var wire  8 ,% out(7) [7:0] $end
    $var wire  8 -% out(8) [7:0] $end
    $var wire  3 C shift [2:0] $end
-   $var wire 32 3( width [31:0] $end
    $scope module always_block $end
     $var wire  1 q' failed $end
     $scope module unnamedblk1 $end
@@ -35,46 +35,47 @@ $timescale   1ns $end
     $var wire 32 ; var3 [30:-1] $end
    $upscope $end
    $scope module shifter0 $end
-    $var wire 32 +( depth [31:0] $end
+    $var wire 32 +( DEPTH [31:0] $end
+    $var wire 32 [( OFFSET [31:0] $end
+    $var wire 32 3( WIDTH [31:0] $end
     $var wire  8 C( in [7:0] $end
-    $var wire 32 [( offset [31:0] $end
     $var wire  8 K out [7:0] $end
     $var wire  3 C shift [2:0] $end
     $var wire  8 [ tmp(-1)[7:0] [7:0] $end
     $var wire  8 S tmp(-2)[7:0] [7:0] $end
     $var wire  8 C( tmp(-3)[7:0] [7:0] $end
     $var wire  8 K tmp(0)[7:0] [7:0] $end
-    $var wire 32 3( width [31:0] $end
    $upscope $end
    $scope module shifter1 $end
-    $var wire 32 +( depth [31:0] $end
+    $var wire 32 +( DEPTH [31:0] $end
+    $var wire 32 [( OFFSET [31:0] $end
+    $var wire 32 3( WIDTH [31:0] $end
     $var wire  8 C( in [7:0] $end
-    $var wire 32 [( offset [31:0] $end
     $var wire  8 c out [7:0] $end
     $var wire  3 C shift [2:0] $end
     $var wire  8 s tmp(-1)[7:0] [7:0] $end
     $var wire  8 k tmp(-2)[7:0] [7:0] $end
     $var wire  8 C( tmp(-3)[7:0] [7:0] $end
     $var wire  8 c tmp(0)[7:0] [7:0] $end
-    $var wire 32 3( width [31:0] $end
    $upscope $end
    $scope module shifter2 $end
-    $var wire 32 +( depth [31:0] $end
+    $var wire 32 +( DEPTH [31:0] $end
+    $var wire 32 c( OFFSET [31:0] $end
+    $var wire 32 3( WIDTH [31:0] $end
     $var wire  8 C( in [7:0] $end
-    $var wire 32 c( offset [31:0] $end
     $var wire  8 { out [7:0] $end
     $var wire  3 C shift [2:0] $end
     $var wire  8 C( tmp(1)[7:0] [7:0] $end
     $var wire  8 %! tmp(2)[7:0] [7:0] $end
     $var wire  8 -! tmp(3)[7:0] [7:0] $end
     $var wire  8 { tmp(4)[7:0] [7:0] $end
-    $var wire 32 3( width [31:0] $end
    $upscope $end
    $scope module shifter3 $end
-    $var wire 32 +( depth [31:0] $end
+    $var wire 32 +( DEPTH [31:0] $end
+    $var wire 32 +( N [31:0] $end
+    $var wire 32 c( OFFSET [31:0] $end
+    $var wire 32 3( WIDTH [31:0] $end
     $var wire  8 C( in [7:0] $end
-    $var wire 32 +( n [31:0] $end
-    $var wire 32 c( offset [31:0] $end
     $var wire  8 m% out [7:0] $end
     $var wire  3 C shift [2:0] $end
     $var wire  8 C( tmp0(1)(1)[7:0] [7:0] $end
@@ -257,12 +258,12 @@ $timescale   1ns $end
     $var wire  8 i# tmp9(7)(1)[7:0] [7:0] $end
     $var wire  8 q# tmp9(7)(2)[7:0] [7:0] $end
     $var wire  8 y# tmp9(7)(3)[7:0] [7:0] $end
-    $var wire 32 3( width [31:0] $end
    $upscope $end
    $scope module shifter4 $end
-    $var wire 32 +( depth [31:0] $end
+    $var wire 32 +( DEPTH [31:0] $end
+    $var wire 32 )+ OFFSET [31:0] $end
+    $var wire 32 3( WIDTH [31:0] $end
     $var wire  8 C( in [7:0] $end
-    $var wire 32 )+ offset [31:0] $end
     $var wire  8 #$ out [7:0] $end
     $var wire 24 9+ pad [23:0] $end
     $var wire  3 C shift [2:0] $end
@@ -270,41 +271,40 @@ $timescale   1ns $end
     $var wire 32 +$ tmp(3)[31:0] [31:0] $end
     $var wire 32 3$ tmp(4)[31:0] [31:0] $end
     $var wire 32 ;$ tmp(5)[31:0] [31:0] $end
-    $var wire 32 3( width [31:0] $end
    $upscope $end
    $scope module shifter5 $end
-    $var wire 32 +( depth [31:0] $end
+    $var wire 32 +( DEPTH [31:0] $end
+    $var wire 32 A+ OFFSET [31:0] $end
+    $var wire 32 3( WIDTH [31:0] $end
     $var wire  8 C( in [7:0] $end
-    $var wire 32 A+ offset [31:0] $end
     $var wire  8 C$ out [7:0] $end
     $var wire  3 C shift [2:0] $end
     $var wire 32 K$ tmp [31:0] $end
-    $var wire 32 3( width [31:0] $end
    $upscope $end
    $scope module shifter6 $end
-    $var wire 32 +( depth [31:0] $end
+    $var wire 32 +( DEPTH [31:0] $end
+    $var wire 32 A+ OFFSET [31:0] $end
+    $var wire 32 3( WIDTH [31:0] $end
     $var wire  8 C( in [7:0] $end
-    $var wire 32 A+ offset [31:0] $end
     $var wire  8 S$ out [7:0] $end
     $var wire  3 C shift [2:0] $end
     $var wire 32 [$ tmp [31:0] $end
-    $var wire 32 3( width [31:0] $end
    $upscope $end
    $scope module shifter7 $end
-    $var wire 32 +( depth [31:0] $end
+    $var wire 32 +( DEPTH [31:0] $end
+    $var wire 32 3( WIDTH [31:0] $end
     $var wire  8 C( in [7:0] $end
     $var wire  8 c$ out [7:0] $end
     $var wire  3 C shift [2:0] $end
     $var wire 32 k$ tmp [31:0] $end
-    $var wire 32 3( width [31:0] $end
    $upscope $end
    $scope module shifter8 $end
-    $var wire 32 +( depth [31:0] $end
+    $var wire 32 +( DEPTH [31:0] $end
+    $var wire 32 3( WIDTH [31:0] $end
     $var wire  8 C( in [7:0] $end
     $var wire  8 s$ out [7:0] $end
     $var wire  3 C shift [2:0] $end
     $var wire 32 {$ tmp [0:31] $end
-    $var wire 32 3( width [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end