From 1b985da2a18d3f781223f0142d41c16c36dff9d1 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 12 Mar 2021 15:52:35 -0500 Subject: [PATCH 001/110] devel release --- Changes | 3 +++ configure.ac | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index e09133c42..bc1d5c5df 100644 --- a/Changes +++ b/Changes @@ -2,6 +2,9 @@ Revision history for Verilator The contributors that suggested a given feature are shown in []. Thanks! +* Verilator 4.201 devel + + * Verilator 4.200 2021-03-12 ** Add simulation context (VerilatedContext) to allow multiple fully independent diff --git a/configure.ac b/configure.ac index 3d7c5ea55..702679ddb 100644 --- a/configure.ac +++ b/configure.ac @@ -7,7 +7,7 @@ #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[4.200 2021-03-12], +AC_INIT([Verilator],[4.201 devel], [https://verilator.org], [verilator],[https://verilator.org]) # When releasing, also update header of Changes file From 21e9794fd729fd455fbe6a5669f7f5cda92bd148 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 12 Mar 2021 16:06:47 -0500 Subject: [PATCH 002/110] Tests: Mark some tests lint only --- test_regress/t/t_interface_missing_bad.pl | 4 ++-- test_regress/t/t_lint_ifdepth_bad.pl | 2 +- test_regress/t/t_lint_implicit_def_bad.pl | 2 +- test_regress/t/t_lint_subout_bad.pl | 2 +- test_regress/t/t_randomize_method_bad.pl | 4 ++-- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/test_regress/t/t_interface_missing_bad.pl b/test_regress/t/t_interface_missing_bad.pl index 1362bf74f..a60503a1f 100755 --- a/test_regress/t/t_interface_missing_bad.pl +++ b/test_regress/t/t_interface_missing_bad.pl @@ -8,9 +8,9 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(simulator => 1); +scenarios(linter => 1); -compile( +lint( fails => 1, expect_filename => $Self->{golden_filename}, ); diff --git a/test_regress/t/t_lint_ifdepth_bad.pl b/test_regress/t/t_lint_ifdepth_bad.pl index 54a0ed3d1..76be13063 100755 --- a/test_regress/t/t_lint_ifdepth_bad.pl +++ b/test_regress/t/t_lint_ifdepth_bad.pl @@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(vlt_all => 1); +scenarios(vlt => 1); lint( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME --if-depth 10"], diff --git a/test_regress/t/t_lint_implicit_def_bad.pl b/test_regress/t/t_lint_implicit_def_bad.pl index 860de7fd2..24c0e4c87 100755 --- a/test_regress/t/t_lint_implicit_def_bad.pl +++ b/test_regress/t/t_lint_implicit_def_bad.pl @@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(vlt_all => 1); +scenarios(vlt => 1); compile( verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], diff --git a/test_regress/t/t_lint_subout_bad.pl b/test_regress/t/t_lint_subout_bad.pl index 1483c9cd2..88f90f1d4 100755 --- a/test_regress/t/t_lint_subout_bad.pl +++ b/test_regress/t/t_lint_subout_bad.pl @@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(vlt_all => 1); +scenarios(vlt => 1); compile( # No --lint-only as got compile error diff --git a/test_regress/t/t_randomize_method_bad.pl b/test_regress/t/t_randomize_method_bad.pl index 6ad7137de..66fa61649 100755 --- a/test_regress/t/t_randomize_method_bad.pl +++ b/test_regress/t/t_randomize_method_bad.pl @@ -8,9 +8,9 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -scenarios(simulator => 1); +scenarios(linter => 1); -compile( +lint( fails => $Self->{vlt_all}, expect_filename => $Self->{golden_filename}, ); From 404b323f8c59314b45017566cd21e584a7b7901c Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 12 Mar 2021 17:26:53 -0500 Subject: [PATCH 003/110] Internals: Remove some unnecessary typedefs. No functional change. --- include/verilated_fst_c.h | 7 ++----- include/verilated_threads.h | 3 +-- include/verilated_vpi.cpp | 3 +-- src/V3Active.cpp | 4 +--- src/V3Branch.cpp | 5 +---- src/V3Cdc.cpp | 3 +-- src/V3Class.cpp | 3 +-- src/V3Combine.cpp | 4 ++-- src/V3Config.cpp | 12 ++++-------- src/V3Coverage.cpp | 7 +++---- src/V3CoverageJoin.cpp | 5 +---- src/V3Delayed.cpp | 3 +-- src/V3EmitC.cpp | 7 +++---- src/V3EmitCSyms.cpp | 13 +++++-------- src/V3File.cpp | 9 +++------ src/V3FileLine.cpp | 5 ++--- src/V3FileLine.h | 4 +--- src/V3Gate.cpp | 10 +++------- src/V3Global.h | 4 ++-- src/V3Graph.cpp | 5 ++--- src/V3GraphDfa.cpp | 2 +- src/V3GraphStream.h | 3 +-- src/V3HierBlock.h | 1 - src/V3Inline.cpp | 4 +--- src/V3Inst.cpp | 3 +-- src/V3LifePost.cpp | 3 +-- src/V3LinkDot.cpp | 11 +++++------ src/V3LinkJump.cpp | 5 +---- src/V3LinkParse.cpp | 3 +-- src/V3Order.cpp | 12 +++++------- src/V3OrderGraph.h | 2 +- src/V3Param.cpp | 20 ++++++++------------ src/V3ParseImp.h | 4 ++-- src/V3ParseSym.h | 2 +- src/V3Partition.cpp | 8 +++----- src/V3Partition.h | 3 +-- src/V3Reloop.cpp | 5 +---- src/V3Scope.cpp | 7 +++---- src/V3Scoreboard.h | 6 ++---- src/V3Split.cpp | 35 +++++++++++++---------------------- src/V3SplitVar.cpp | 25 +++++++++---------------- src/V3StatsReport.cpp | 16 ++++++---------- src/V3String.h | 3 +-- src/V3TSP.cpp | 3 +-- src/V3Table.cpp | 6 ++---- src/V3Task.cpp | 6 ++---- src/V3Width.cpp | 6 +++--- 47 files changed, 116 insertions(+), 204 deletions(-) diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 64efe75c1..232905eea 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -43,12 +43,9 @@ private: //========================================================================= // FST specific internals - typedef std::map Code2SymbolType; - typedef std::map Local2FstDtype; - void* m_fst; - Code2SymbolType m_code2symbol; - Local2FstDtype m_local2fstdtype; + std::map m_code2symbol; + std::map m_local2fstdtype; std::list m_curScope; fstHandle* m_symbolp = nullptr; ///< same as m_code2symbol, but as an array char* m_strbuf = nullptr; ///< String buffer long enough to hold maxBits() chars diff --git a/include/verilated_threads.h b/include/verilated_threads.h index ded328b5b..c7ddc4467 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -252,7 +252,6 @@ public: class VlThreadPool final { // TYPES typedef std::vector ProfileTrace; - typedef std::set ProfileSet; // MEMBERS std::vector m_workers; // our workers @@ -266,7 +265,7 @@ class VlThreadPool final { // this is the only cost we pay in real-time during a profiling cycle. // Internal note: Globals may multi-construct, see verilated.cpp top. static VL_THREAD_LOCAL ProfileTrace* t_profilep; - ProfileSet m_allProfiles VL_GUARDED_BY(m_mutex); + std::set m_allProfiles VL_GUARDED_BY(m_mutex); VerilatedMutex m_mutex; public: diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 64b16fb83..2a9afdaeb 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -607,8 +607,7 @@ public: assertOneCheck(); VpioCbList& cbObjList = s().m_cbObjLists[cbValueChange]; bool called = false; - typedef std::unordered_set VpioVarSet; - VpioVarSet update; // set of objects to update after callbacks + std::unordered_set update; // set of objects to update after callbacks if (cbObjList.empty()) return called; const auto last = std::prev(cbObjList.end()); // prevent looping over newly added elements for (auto it = cbObjList.begin(); true;) { diff --git a/src/V3Active.cpp b/src/V3Active.cpp index b918b7249..c90016af5 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -77,10 +77,8 @@ public: class LatchDetectGraph final : public V3Graph { protected: - typedef std::vector VarRefVec; - LatchDetectGraphVertex* m_curVertexp; // Current latch detection graph vertex - VarRefVec m_outputs; // Vector of lvalues encountered on this pass + std::vector m_outputs; // Vector of lvalues encountered on this pass VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3Branch.cpp b/src/V3Branch.cpp index b4e6a2bf5..30560fb8e 100644 --- a/src/V3Branch.cpp +++ b/src/V3Branch.cpp @@ -42,13 +42,10 @@ private: // AstFTask::user1() -> int. Number of references AstUser1InUse m_inuser1; - // TYPES - typedef std::vector CFuncVec; - // STATE int m_likely; // Excuses for branch likely taken int m_unlikely; // Excuses for branch likely not taken - CFuncVec m_cfuncsp; // List of all tasks + std::vector m_cfuncsp; // List of all tasks // METHODS VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3Cdc.cpp b/src/V3Cdc.cpp index 9139c5eb5..29e3114b0 100644 --- a/src/V3Cdc.cpp +++ b/src/V3Cdc.cpp @@ -556,8 +556,7 @@ private: return; } // Fully computed - typedef std::set SenSet; - SenSet senouts; // List of all sensitivities for new signal + std::set senouts; // List of all sensitivities for new signal if (CdcLogicVertex* vvertexp = dynamic_cast(vertexp)) { if (vvertexp) {} // Unused } else if (CdcVarVertex* vvertexp = dynamic_cast(vertexp)) { diff --git a/src/V3Class.cpp b/src/V3Class.cpp index 7556bd19c..7c3b65bc7 100644 --- a/src/V3Class.cpp +++ b/src/V3Class.cpp @@ -37,8 +37,7 @@ private: AstScope* m_classScopep = nullptr; // Package moving scopes into AstScope* m_packageScopep = nullptr; // Class package scope AstNodeFTask* m_ftaskp = nullptr; // Current task - typedef std::vector> MoveVector; - MoveVector m_moves; + std::vector> m_moves; // NODE STATE // AstClass::user1() -> bool. True if iterated already diff --git a/src/V3Combine.cpp b/src/V3Combine.cpp index 687f8d602..f74364a4b 100644 --- a/src/V3Combine.cpp +++ b/src/V3Combine.cpp @@ -79,7 +79,7 @@ public: UINFO(4, " Remove " << oldfuncp << endl); } // Note: m_callMmap modified in loop, so not using equal_range. - for (CallMmap::iterator it = m_callMmap.find(oldfuncp); it != m_callMmap.end(); + for (auto it = m_callMmap.find(oldfuncp); it != m_callMmap.end(); it = m_callMmap.find(oldfuncp)) { AstCCall* callp = it->second; if (!callp->user3()) { // !already done @@ -173,7 +173,7 @@ private: // AstUser4InUse part of V3Hashed // STATE - typedef enum : uint8_t { STATE_IDLE, STATE_HASH, STATE_DUP } CombineState; + enum CombineState : uint8_t { STATE_IDLE, STATE_HASH, STATE_DUP }; VDouble0 m_statCombs; // Statistic tracking CombineState m_state = STATE_IDLE; // Major state AstNodeModule* m_modp = nullptr; // Current module diff --git a/src/V3Config.cpp b/src/V3Config.cpp index 40b7985d7..93b4ebecf 100644 --- a/src/V3Config.cpp +++ b/src/V3Config.cpp @@ -154,13 +154,10 @@ typedef V3ConfigWildcardResolver V3ConfigFTaskResolver; // Modules have tasks, variables, named blocks and properties class V3ConfigModule final { - typedef std::unordered_set StringSet; - typedef std::set PragmaSet; - V3ConfigFTaskResolver m_tasks; // Functions/tasks in module V3ConfigVarResolver m_vars; // Variables in module - StringSet m_coverageOffBlocks; // List of block names for coverage_off - PragmaSet m_modPragmas; // List of Pragmas for modules + std::unordered_set m_coverageOffBlocks; // List of block names for coverage_off + std::set m_modPragmas; // List of Pragmas for modules bool m_inline = false; // Whether to force the inline bool m_inlineValue = false; // The inline value (on/off) @@ -175,8 +172,7 @@ public: m_inline = m.m_inline; m_inlineValue = m.m_inlineValue; } - for (PragmaSet::const_iterator it = m.m_modPragmas.begin(); it != m.m_modPragmas.end(); - ++it) { + for (auto it = m.m_modPragmas.cbegin(); it != m.m_modPragmas.cend(); ++it) { m_modPragmas.insert(*it); } } @@ -198,7 +194,7 @@ public: AstNode* nodep = new AstPragma(modp->fileline(), type); modp->addStmtp(nodep); } - for (PragmaSet::const_iterator it = m_modPragmas.begin(); it != m_modPragmas.end(); ++it) { + for (auto it = m_modPragmas.cbegin(); it != m_modPragmas.cend(); ++it) { AstNode* nodep = new AstPragma(modp->fileline(), *it); modp->addStmtp(nodep); } diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index 161839acf..7ad84e8cb 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -40,9 +40,7 @@ class CoverageVisitor final : public AstNVisitor { private: // TYPES - typedef std::unordered_map VarNameMap; typedef std::set LinenoSet; - typedef std::unordered_map HandleLines; struct ToggleEnt { string m_comment; // Comment for coverage dump @@ -81,9 +79,10 @@ private: CheckState m_state; // State save-restored on each new coverage scope/block AstNodeModule* m_modp = nullptr; // Current module to add statement to bool m_inToggleOff = false; // In function/task etc - VarNameMap m_varnames; // Uniquification of inserted variable names + std::unordered_map m_varnames; // Uniquification of inserted variable names string m_beginHier; // AstBegin hier name for user coverage points - HandleLines m_handleLines; // All line numbers for a given m_stateHandle + std::unordered_map + m_handleLines; // All line numbers for a given m_stateHandle // METHODS VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3CoverageJoin.cpp b/src/V3CoverageJoin.cpp index 7d382d59c..48cf67fad 100644 --- a/src/V3CoverageJoin.cpp +++ b/src/V3CoverageJoin.cpp @@ -38,11 +38,8 @@ private: // AstUser4InUse In V3Hashed - // TYPES - typedef std::vector ToggleList; - // STATE - ToggleList m_toggleps; // List of of all AstCoverToggle's + std::vector m_toggleps; // List of of all AstCoverToggle's VDouble0 m_statToggleJoins; // Statistic tracking diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index 283b30923..553f38d59 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -97,8 +97,7 @@ private: typedef std::map, AstVar*> VarMap; VarMap m_modVarMap; // Table of new var names created under module VDouble0 m_statSharedSet; // Statistic tracking - typedef std::unordered_map ScopeVecMap; - ScopeVecMap m_scopeVecMap; // Next var number for each scope + std::unordered_map m_scopeVecMap; // Next var number for each scope // METHODS VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index c82d39dec..95942d878 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -77,14 +77,14 @@ public: char fmtLetter); void emitVarDecl(const AstVar* nodep, const string& prefixIfImp); - typedef enum : uint8_t { + enum EisWhich : uint8_t { EVL_CLASS_IO, EVL_CLASS_SIG, EVL_CLASS_TEMP, EVL_CLASS_PAR, EVL_CLASS_ALL, EVL_FUNC_ALL - } EisWhich; + }; void emitVarList(AstNode* firstp, EisWhich which, const string& prefixIfImp, string& sectionr); static void emitVarSort(const VarSortMap& vmap, VarVec* sortedp); void emitSortedVarList(const VarVec& anons, const VarVec& nonanons, const string& prefixIfImp); @@ -221,8 +221,7 @@ public: } }; void emitIntFuncDecls(AstNodeModule* modp, bool methodFuncs) { - typedef std::vector FuncVec; - FuncVec funcsp; + std::vector funcsp; for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) { if (const AstCFunc* funcp = VN_CAST(nodep, CFunc)) { diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 352b3292b..d0cfe9632 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -71,8 +71,6 @@ class EmitCSyms final : EmitCBaseVisitor { , m_modp{modp} , m_scopep{scopep} {} }; - typedef std::map ScopeFuncs; - typedef std::map ScopeVars; typedef std::map ScopeNames; typedef std::pair ScopeModPair; typedef std::pair ModVarPair; @@ -100,8 +98,8 @@ class EmitCSyms final : EmitCBaseVisitor { std::vector m_dpis; // DPI functions std::vector m_modVars; // Each public {mod,var} ScopeNames m_scopeNames; // Each unique AstScopeName - ScopeFuncs m_scopeFuncs; // Each {scope,dpi-export-func} - ScopeVars m_scopeVars; // Each {scope,public-var} + std::map m_scopeFuncs; // Each {scope,dpi-export-func} + std::map m_scopeVars; // Each {scope,public-var} ScopeNames m_vpiScopeCandidates; // All scopes for VPI ScopeNameHierarchy m_vpiScopeHierarchy; // The actual hierarchy of scopes int m_coverBins = 0; // Coverage bin number @@ -572,8 +570,7 @@ void EmitCSyms::emitScopeHier(bool destroy) { } } - for (ScopeNameHierarchy::const_iterator it = m_vpiScopeHierarchy.begin(); - it != m_vpiScopeHierarchy.end(); ++it) { + for (auto it = m_vpiScopeHierarchy.cbegin(); it != m_vpiScopeHierarchy.cend(); ++it) { for (ScopeNameList::const_iterator lit = it->second.begin(); lit != it->second.end(); ++lit) { string fromname = scopeSymString(it->first); @@ -734,7 +731,7 @@ void EmitCSyms::emitSymImp() { if (v3Global.dpi()) { m_ofpBase->puts("// Setup export functions\n"); m_ofpBase->puts("for (int __Vfinal=0; __Vfinal<2; __Vfinal++) {\n"); - for (ScopeFuncs::iterator it = m_scopeFuncs.begin(); it != m_scopeFuncs.end(); ++it) { + for (auto it = m_scopeFuncs.begin(); it != m_scopeFuncs.end(); ++it) { AstScopeName* scopep = it->second.m_scopep; AstCFunc* funcp = it->second.m_cfuncp; AstNodeModule* modp = it->second.m_modp; @@ -752,7 +749,7 @@ void EmitCSyms::emitSymImp() { } // It would be less code if each module inserted its own variables. // Someday. For now public isn't common. - for (ScopeVars::iterator it = m_scopeVars.begin(); it != m_scopeVars.end(); ++it) { + for (auto it = m_scopeVars.begin(); it != m_scopeVars.end(); ++it) { checkSplit(true); AstNodeModule* modp = it->second.m_modp; AstScope* scopep = it->second.m_scopep; diff --git a/src/V3File.cpp b/src/V3File.cpp index fbcd02eac..9edea35ea 100644 --- a/src/V3File.cpp +++ b/src/V3File.cpp @@ -328,10 +328,9 @@ void V3File::createMakeDir() { // VInFilterImp class VInFilterImp final { - typedef std::map FileContentsMap; typedef VInFilter::StrList StrList; - FileContentsMap m_contentsMap; // Cache of file contents + std::map m_contentsMap; // Cache of file contents bool m_readEof = false; // Received EOF on read #ifdef INFILTER_PIPE pid_t m_pid = 0; // fork() process id @@ -949,10 +948,8 @@ void V3OutCFile::putsGuard() { class VIdProtectImp final { // MEMBERS - typedef std::map IdMap; - IdMap m_nameMap; // Map of old name into new name - typedef std::unordered_set IdSet; - IdSet m_newIdSet; // Which new names exist + std::map m_nameMap; // Map of old name into new name + std::unordered_set m_newIdSet; // Which new names exist protected: // CONSTRUCTORS friend class VIdProtect; diff --git a/src/V3FileLine.cpp b/src/V3FileLine.cpp index 6f8f5073b..5c5449ed2 100644 --- a/src/V3FileLine.cpp +++ b/src/V3FileLine.cpp @@ -71,7 +71,7 @@ int FileLineSingleton::nameToNumber(const string& filename) { //! Experimental. Updated to also put out the language. void FileLineSingleton::fileNameNumMapDumpXml(std::ostream& os) { os << "\n"; - for (FileNameNumMap::const_iterator it = m_namemap.begin(); it != m_namemap.end(); ++it) { + for (auto it = m_namemap.cbegin(); it != m_namemap.cend(); ++it) { os << "second) << "\" filename=\"" << V3OutFormatter::quoteNameControls(it->first, V3OutFormatter::LA_XML) << "\" language=\"" << numberToLang(it->second).ascii() << "\"/>\n"; @@ -427,8 +427,7 @@ string FileLine::warnContext(bool secondary) const { } #ifdef VL_LEAK_CHECKS -typedef std::unordered_set FileLineCheckSet; -FileLineCheckSet fileLineLeakChecks; +std::unordered_set fileLineLeakChecks; void* FileLine::operator new(size_t size) { FileLine* objp = static_cast(::operator new(size)); diff --git a/src/V3FileLine.h b/src/V3FileLine.h index 983554aaf..fa77fdafa 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -38,10 +38,8 @@ class FileLine; //! This singleton class contains tables of data that are unchanging in each //! source file (each with its own unique filename number). class FileLineSingleton final { - // TYPES - typedef std::map FileNameNumMap; // MEMBERS - FileNameNumMap m_namemap; // filenameno for each filename + std::map m_namemap; // filenameno for each filename std::deque m_names; // filename text for each filenameno std::deque m_languages; // language for each filenameno // CONSTRUCTORS diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp index 3c1a92e9e..cb329f785 100644 --- a/src/V3Gate.cpp +++ b/src/V3Gate.cpp @@ -681,9 +681,9 @@ bool GateVisitor::elimLogicOkOutputs(GateLogicVertex* consumeVertexp, // Return true if can optimize // Return false if the consuming logic has an output signal that the // replacement logic has as an input - typedef std::unordered_set VarScopeSet; + // Use map to find duplicates between two lists - VarScopeSet varscopes; + std::unordered_set varscopes; // Replacement logic usually has shorter input list, so faster to build list based on it const GateVarRefList& rhsVarRefs = okVisitor.rhsVarRefs(); for (GateVarRefList::const_iterator it = rhsVarRefs.begin(); it != rhsVarRefs.end(); ++it) { @@ -901,10 +901,6 @@ void GateVisitor::optimizeElimVar(AstVarScope* varscp, AstNode* substp, AstNode* // Auxiliary hash class for GateDedupeVarVisitor class GateDedupeHash final : public V3HashedUserSame { -public: - // TYPES - typedef std::unordered_set NodeSet; - private: // NODE STATE // Ast*::user2p -> parent AstNodeAssign* for this rhsp @@ -919,7 +915,7 @@ private: AstUser5InUse m_inuser5; V3Hashed m_hashed; // Hash, contains rhs of assigns - NodeSet m_nodeDeleteds; // Any node in this hash was deleted + std::unordered_set m_nodeDeleteds; // Any node in this hash was deleted VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3Global.h b/src/V3Global.h index 693b213a3..8ec6ba819 100644 --- a/src/V3Global.h +++ b/src/V3Global.h @@ -105,8 +105,8 @@ class V3Global final { bool m_useRandomizeMethods = false; // Need to define randomize() class methods // Memory address to short string mapping (for debug) - typedef std::unordered_map PtrToIdMap; // The map type - PtrToIdMap m_ptrToId; // The actual 'address' <=> 'short string' bijection + std::unordered_map + m_ptrToId; // The actual 'address' <=> 'short string' bijection public: // Options diff --git a/src/V3Graph.cpp b/src/V3Graph.cpp index c4e28599d..2f6481943 100644 --- a/src/V3Graph.cpp +++ b/src/V3Graph.cpp @@ -325,8 +325,7 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) const { *logp << "\t\t rankdir=" << dotRankDir() << "];\n"; // List of all possible subgraphs - typedef std::multimap SubgraphMmap; - SubgraphMmap subgraphs; + std::multimap subgraphs; for (V3GraphVertex* vertexp = verticesBeginp(); vertexp; vertexp = vertexp->verticesNextp()) { string vertexSubgraph = (colorAsSubgraph && vertexp->color()) ? cvtToStr(vertexp->color()) : ""; @@ -340,7 +339,7 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) const { // Print vertices int n = 0; string subgr; - for (SubgraphMmap::const_iterator it = subgraphs.begin(); it != subgraphs.end(); ++it) { + for (auto it = subgraphs.cbegin(); it != subgraphs.cend(); ++it) { string vertexSubgraph = it->first; V3GraphVertex* vertexp = it->second; numMap[vertexp] = n; diff --git a/src/V3GraphDfa.cpp b/src/V3GraphDfa.cpp index 555c19d94..135187e3e 100644 --- a/src/V3GraphDfa.cpp +++ b/src/V3GraphDfa.cpp @@ -177,7 +177,7 @@ private: uint32_t hash = hashDfaOrigins(nfasWithInput); const auto eqrange = m_hashMap.equal_range(hash); - for (HashMap::iterator it = eqrange.first; it != eqrange.second; ++it) { + for (auto it = eqrange.first; it != eqrange.second; ++it) { DfaVertex* testp = it->second; if (compareDfaOrigins(nfasWithInput, testp)) { UINFO(9, " DFA match for set: " << testp << endl); diff --git a/src/V3GraphStream.h b/src/V3GraphStream.h index 84c6c3eec..4f62b50eb 100644 --- a/src/V3GraphStream.h +++ b/src/V3GraphStream.h @@ -81,12 +81,11 @@ private: }; typedef std::set ReadyVertices; - typedef std::map WaitingVertices; // MEMBERS VxHolderCmp m_vxHolderCmp; // Vertext comparison functor ReadyVertices m_readyVertices; // List of ready vertices - WaitingVertices m_waitingVertices; // List of waiting vertices + std::map m_waitingVertices; // List of waiting vertices typename ReadyVertices::iterator m_last; // Previously returned element GraphWay m_way; // FORWARD or REVERSE order of traversal diff --git a/src/V3HierBlock.h b/src/V3HierBlock.h index 7a7044b25..38caf5b8f 100644 --- a/src/V3HierBlock.h +++ b/src/V3HierBlock.h @@ -42,7 +42,6 @@ class V3HierBlock final { public: typedef std::vector GParams; typedef std::unordered_set HierBlockSet; - typedef std::unordered_set NodeModuleSet; private: // TYPES diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index e1ba954db..d4c57a51a 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -264,14 +264,12 @@ public: class InlineRelinkVisitor final : public AstNVisitor { private: - typedef std::unordered_set StringSet; - // NODE STATE // Input: // See InlineVisitor // STATE - StringSet m_renamedInterfaces; // Name of renamed interface variables + std::unordered_set m_renamedInterfaces; // Name of renamed interface variables AstNodeModule* m_modp; // Current module AstCell* m_cellp; // Cell being cloned diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index fb4d3625d..bbc466e0e 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -141,8 +141,7 @@ class InstDeModVarVisitor final : public AstNVisitor { // Expand all module variables, and save names for later reference private: // STATE - typedef std::map VarNameMap; - VarNameMap m_modVarNameMap; // Per module, name of cloned variables + std::map m_modVarNameMap; // Per module, name of cloned variables VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3LifePost.cpp b/src/V3LifePost.cpp index c578335c7..9aea9b950 100644 --- a/src/V3LifePost.cpp +++ b/src/V3LifePost.cpp @@ -150,8 +150,7 @@ private: LocMap m_writes; // VarScope write locations // Map each dly var to its AstAssignPost* node and the location thereof - typedef std::unordered_map PostLocMap; - PostLocMap m_assignposts; // AssignPost dly var locations + std::unordered_map m_assignposts; const V3Graph* m_mtasksGraphp = nullptr; // Mtask tracking graph std::unique_ptr m_checker; diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index e4be8719b..7a536434f 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -140,10 +140,7 @@ public: private: // TYPES - typedef std::multimap NameScopeSymMap; typedef std::unordered_map ScopeAliasMap; - typedef std::set> ImplicitNameSet; - typedef std::vector IfaceVarSyms; typedef std::vector> IfaceModSyms; static LinkDotState* s_errorThisp; // Last self, for error reporting only @@ -151,10 +148,12 @@ private: // MEMBERS VSymGraph m_syms; // Symbol table VSymEnt* m_dunitEntp; // $unit entry - NameScopeSymMap m_nameScopeSymMap; // Map of scope referenced by non-pretty textual name - ImplicitNameSet m_implicitNameSet; // For [module][signalname] if we can implicitly create it + std::multimap + m_nameScopeSymMap; // Map of scope referenced by non-pretty textual name + std::set> + m_implicitNameSet; // For [module][signalname] if we can implicitly create it std::array m_scopeAliasMap; // Map of aliases - IfaceVarSyms m_ifaceVarSyms; // List of AstIfaceRefDType's to be imported + std::vector m_ifaceVarSyms; // List of AstIfaceRefDType's to be imported IfaceModSyms m_ifaceModSyms; // List of AstIface+Symbols to be processed bool m_forPrimary; // First link bool m_forPrearray; // Compress cell__[array] refs diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp index 8308ffa1b..8a9547c3b 100644 --- a/src/V3LinkJump.cpp +++ b/src/V3LinkJump.cpp @@ -43,9 +43,6 @@ class LinkJumpVisitor final : public AstNVisitor { private: - // TYPES - typedef std::vector BlockStack; - // STATE AstNodeModule* m_modp = nullptr; // Current module AstNodeFTask* m_ftaskp = nullptr; // Current function/task @@ -53,7 +50,7 @@ private: bool m_loopInc = false; // In loop increment bool m_inFork = false; // Under fork int m_modRepeatNum = 0; // Repeat counter - BlockStack m_blockStack; // All begin blocks above current node + std::vector m_blockStack; // All begin blocks above current node // METHODS VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 60c73a5e5..e5913888f 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -45,12 +45,11 @@ private: // TYPES typedef std::map, AstTypedef*> ImplTypedefMap; - typedef std::unordered_set FileLineSet; // STATE AstVar* m_varp = nullptr; // Variable we're under ImplTypedefMap m_implTypedef; // Created typedefs for each - FileLineSet m_filelines; // Filelines that have been seen + std::unordered_set m_filelines; // Filelines that have been seen bool m_inAlways = false; // Inside an always AstNodeModule* m_valueModp = nullptr; // If set, move AstVar->valuep() initial values to this module diff --git a/src/V3Order.cpp b/src/V3Order.cpp index 4612cf44b..464f219c5 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -422,9 +422,6 @@ template class ProcessMoveBuildGraph { // TYPES typedef std::pair VxDomPair; - // Maps an (original graph vertex, domain) pair to a T_MoveVertex - // Not std::unordered_map, because std::pair doesn't provide std::hash - typedef std::map Var2Move; typedef std::unordered_map Logic2Move; public: @@ -446,7 +443,9 @@ private: V3Graph* m_outGraphp; // Output graph of T_MoveVertex's MoveVertexMaker* m_vxMakerp; // Factory class for T_MoveVertex's Logic2Move m_logic2move; // Map Logic to Vertex - Var2Move m_var2move; // Map Vars to Vertex + // Maps an (original graph vertex, domain) pair to a T_MoveVertex + // Not std::unordered_map, because std::pair doesn't provide std::hash + std::map m_var2move; public: // CONSTRUCTORS @@ -752,14 +751,13 @@ private: // processMTask* routines schedule threaded execution struct MTaskState { - typedef std::list Logics; AstMTaskBody* m_mtaskBodyp = nullptr; - Logics m_logics; + std::list m_logics; ExecMTask* m_execMTaskp = nullptr; MTaskState() = default; }; void processMTasks(); - typedef enum : uint8_t { LOGIC_INITIAL, LOGIC_SETTLE } InitialLogicE; + enum InitialLogicE : uint8_t { LOGIC_INITIAL, LOGIC_SETTLE }; void processMTasksInitial(InitialLogicE logic_type); string cfuncName(AstNodeModule* modp, AstSenTree* domainp, AstScope* scopep, diff --git a/src/V3OrderGraph.h b/src/V3OrderGraph.h index 69051b511..56e44bc99 100644 --- a/src/V3OrderGraph.h +++ b/src/V3OrderGraph.h @@ -300,7 +300,7 @@ public: //--- Following only under the move graph, not the main graph class OrderMoveVertex final : public V3GraphVertex { - typedef enum : uint8_t { POM_WAIT, POM_READY, POM_MOVED } OrderMState; + enum OrderMState : uint8_t { POM_WAIT, POM_READY, POM_MOVED }; OrderLogicVertex* m_logicp; OrderMState m_state; // Movement state diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 89df4b371..a067f2c35 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -72,8 +72,6 @@ class ParameterizedHierBlocks final { typedef std::map HierBlockModMap; typedef std::map> ParamConstMap; typedef std::map GParamsMap; // key:parameter name value:parameter - typedef std::map HierParamsMap; - typedef std::map ModParamsMap; // key:module name // MEMBERS // key:Original module name, value:HiearchyBlockOption* @@ -83,8 +81,9 @@ class ParameterizedHierBlocks final { // key:mangled module name, value:AstNodeModule* HierBlockModMap m_hierBlockMod; // Overridden parameters of the hierarchical block - HierParamsMap m_hierParams; - ModParamsMap m_modParams; // Parameter variables of hierarchical blocks + std::map m_hierParams; + std::map + m_modParams; // Parameter variables of hierarchical blocks // METHODS VL_DEBUG_FUNC; // Declare debug() @@ -243,11 +242,10 @@ class ParamProcessor final { explicit ModInfo(AstNodeModule* modp) : m_modp{modp} {} }; - typedef std::map ModNameMap; - ModNameMap m_modNameMap; // Hash of created module flavors by name + std::map m_modNameMap; // Hash of created module flavors by name - typedef std::map LongMap; - LongMap m_longMap; // Hash of very long names to unique identity number + std::map + m_longMap; // Hash of very long names to unique identity number int m_longId = 0; // All module names that are loaded from source code @@ -255,8 +253,7 @@ class ParamProcessor final { V3StringSet m_allModuleNames; typedef std::pair ValueMapValue; - typedef std::map ValueMap; - ValueMap m_valueMap; // Hash of node hash to (param value, name) + std::map m_valueMap; // Hash of node hash to (param value, name) int m_nextValue = 1; // Next value to use in m_valueMap AstNodeModule* m_modp = nullptr; // Current module being processed @@ -821,8 +818,7 @@ class ParamVisitor final : public AstNVisitor { string m_unlinkedTxt; // Text for AstUnlinkedRef std::deque m_cellps; // Cells left to process (in this module) - typedef std::multimap LevelModMap; - LevelModMap m_todoModps; // Modules left to process + std::multimap m_todoModps; // Modules left to process // METHODS VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3ParseImp.h b/src/V3ParseImp.h index d556d628e..a9477921c 100644 --- a/src/V3ParseImp.h +++ b/src/V3ParseImp.h @@ -37,9 +37,9 @@ class V3Lexer; //====================================================================== // Types (between parser & lexer) -typedef enum : uint8_t { uniq_NONE, uniq_UNIQUE, uniq_UNIQUE0, uniq_PRIORITY } V3UniqState; +enum V3UniqState : uint8_t { uniq_NONE, uniq_UNIQUE, uniq_UNIQUE0, uniq_PRIORITY }; -typedef enum : uint8_t { iprop_NONE, iprop_CONTEXT, iprop_PURE } V3ImportProperty; +enum V3ImportProperty : uint8_t { iprop_NONE, iprop_CONTEXT, iprop_PURE }; //============================================================================ // Member qualifiers diff --git a/src/V3ParseSym.h b/src/V3ParseSym.h index 8c8361c03..17ab5de56 100644 --- a/src/V3ParseSym.h +++ b/src/V3ParseSym.h @@ -40,7 +40,7 @@ private: VSymGraph m_syms; // Graph of symbol tree VSymEnt* m_symTableNextId = nullptr; // Symbol table for next lexer lookup (parser use only) VSymEnt* m_symCurrentp; // Active symbol table for additions/lookups - SymStack m_sympStack; // Stack of upper nodes with pending symbol tables + std::vector m_sympStack; // Stack of upper nodes with pending symbol tables public: // CONSTRUCTORS diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index d8a2c6e5b..fe3e761f0 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -166,8 +166,7 @@ private: vluint64_t m_generation = 0; // Mark each vertex with this number; // // confirm we only process each vertex once. bool m_slowAsserts; // Enable nontrivial asserts - typedef SortByValueMap PropCpPendSet; - PropCpPendSet m_pending; // Pending rescores + SortByValueMap m_pending; // Pending rescores public: // CONSTRUCTORS @@ -2040,8 +2039,7 @@ private: ReadyMTasks m_ready; // MTasks ready to be assigned next; all their // // dependencies are already assigned. - typedef std::vector MTaskVec; - MTaskVec m_prevMTask; // Previous mtask scheduled to each thread. + std::vector m_prevMTask; // Previous mtask scheduled to each thread. std::vector m_busyUntil; // Time each thread is occupied until public: @@ -2458,7 +2456,7 @@ void V3Partition::go(V3Graph* mtasksp) { sorted.insert(mtaskp); } uint32_t nextId = 1; - for (SortedMTaskSet::iterator it = sorted.begin(); it != sorted.end(); ++it) { + for (auto it = sorted.begin(); it != sorted.end(); ++it) { // We shouldn't perturb the sort order of the set, despite // changing the IDs, they should all just remain in the same // relative order. Confirm that: diff --git a/src/V3Partition.h b/src/V3Partition.h index 3405f1b7f..f8fc86b10 100644 --- a/src/V3Partition.h +++ b/src/V3Partition.h @@ -76,10 +76,9 @@ private: class PartPtrIdMap final { private: // TYPES - typedef std::unordered_map PtrMap; // MEMBERS mutable vluint64_t m_nextId = 0; - mutable PtrMap m_id; + mutable std::unordered_map m_id; public: // CONSTRUCTORS diff --git a/src/V3Reloop.cpp b/src/V3Reloop.cpp index 5fb63111e..d9b6aeabc 100644 --- a/src/V3Reloop.cpp +++ b/src/V3Reloop.cpp @@ -45,9 +45,6 @@ constexpr unsigned RELOOP_MIN_ITERS = 40; // Need at least this many loops to d class ReloopVisitor final : public AstNVisitor { private: - // TYPES - typedef std::vector AssVec; - // NODE STATE // AstCFunc::user1p -> Var* for temp var, 0=not set yet AstUser1InUse m_inuser1; @@ -57,7 +54,7 @@ private: VDouble0 m_statReItems; // Statistic tracking AstCFunc* m_cfuncp = nullptr; // Current block - AssVec m_mgAssignps; // List of assignments merging + std::vector m_mgAssignps; // List of assignments merging AstCFunc* m_mgCfuncp = nullptr; // Parent C function AstNode* m_mgNextp = nullptr; // Next node AstNodeSel* m_mgSelLp = nullptr; // Parent select, nullptr = idle diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp index 042181ff8..c7188841f 100644 --- a/src/V3Scope.cpp +++ b/src/V3Scope.cpp @@ -45,10 +45,8 @@ private: AstUser2InUse m_inuser2; // TYPES - typedef std::unordered_map PackageScopeMap; // These cannot be unordered unless make a specialized hashing pair (gcc-8) typedef std::map, AstVarScope*> VarScopeMap; - typedef std::set> VarRefScopeSet; // STATE, inside processing a single module AstNodeModule* m_modp = nullptr; // Current module @@ -57,9 +55,10 @@ private: AstCell* m_aboveCellp = nullptr; // Cell that instantiates this module AstScope* m_aboveScopep = nullptr; // Scope that instantiates this scope - PackageScopeMap m_packageScopes; // Scopes for each package + std::unordered_map m_packageScopes; // Scopes for each package VarScopeMap m_varScopes; // Varscopes created for each scope and var - VarRefScopeSet m_varRefScopes; // Varrefs-in-scopes needing fixup when done + std::set> + m_varRefScopes; // Varrefs-in-scopes needing fixup when done // METHODS VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3Scoreboard.h b/src/V3Scoreboard.h index f0370f59d..3584bf4a8 100644 --- a/src/V3Scoreboard.h +++ b/src/V3Scoreboard.h @@ -44,12 +44,11 @@ template Key2Val; typedef std::set KeySet; typedef std::map Val2Keys; // MEMBERS - Key2Val m_keys; // Map each key to its value. Not sorted. + std::unordered_map m_keys; // Map each key to its value. Not sorted. Val2Keys m_vals; // Map each value to its keys. Sorted. public: @@ -353,7 +352,6 @@ template NeedRescoreSet; class CmpElems final { public: bool operator()(const T_Elem* const& ap, const T_Elem* const& bp) const { @@ -365,7 +363,7 @@ private: typedef T_Score (*UserScoreFnp)(const T_Elem*); // MEMBERS - NeedRescoreSet m_unknown; // Elements with unknown scores + std::unordered_set m_unknown; // Elements with unknown scores SortedMap m_sorted; // Set of elements with known scores UserScoreFnp m_scoreFnp; // Scoring function bool m_slowAsserts; // Do some asserts that require extra lookups diff --git a/src/V3Split.cpp b/src/V3Split.cpp index 801a6cef7..af5b9921b 100644 --- a/src/V3Split.cpp +++ b/src/V3Split.cpp @@ -248,12 +248,9 @@ private: AstUser4InUse m_inuser4; protected: - // TYPES - typedef std::vector VStack; - // STATE string m_noReorderWhy; // Reason we can't reorder - VStack m_stmtStackps; // Current statements being tracked + std::vector m_stmtStackps; // Current statements being tracked SplitPliVertex* m_pliVertexp; // Element specifying PLI ordering V3Graph m_graph; // Scoreboard of var usages/dependencies bool m_inDly; // Inside ASSIGNDLY @@ -523,8 +520,7 @@ protected: // Reorder statements in the completed graph // Map the rank numbers into nodes they associate with - typedef std::multimap RankNodeMap; - RankNodeMap rankMap; + std::multimap rankMap; int currOrder = 0; // Existing sequence number of assignment for (AstNode* nextp = nodep; nextp; nextp = nextp->nextp()) { SplitLogicVertex* vvertexp = reinterpret_cast(nextp->user3p()); @@ -535,7 +531,7 @@ protected: // Is the current ordering OK? bool leaveAlone = true; int newOrder = 0; // New sequence number of assignment - for (RankNodeMap::const_iterator it = rankMap.begin(); it != rankMap.end(); ++it) { + for (auto it = rankMap.cbegin(); it != rankMap.cend(); ++it) { AstNode* nextp = it->second; if (++newOrder != nextp->user4()) leaveAlone = false; } @@ -544,7 +540,7 @@ protected: } else { AstNRelinker replaceHandle; // Where to add the list AstNode* newListp = nullptr; - for (RankNodeMap::const_iterator it = rankMap.begin(); it != rankMap.end(); ++it) { + for (auto it = rankMap.cbegin(); it != rankMap.cend(); ++it) { AstNode* nextp = it->second; UINFO(6, " New order: " << nextp << endl); if (nextp == nodep) { @@ -626,11 +622,10 @@ class IfColorVisitor final : public AstNVisitor { // MEMBERS ColorSet m_colors; // All colors in the original always block - typedef std::vector IfStack; - IfStack m_ifStack; // Stack of nested if-statements we're currently processing + std::vector m_ifStack; // Stack of nested if-statements we're currently processing - typedef std::unordered_map IfColorMap; - IfColorMap m_ifColors; // Map each if-statement to the set of colors (split blocks) + std::unordered_map + m_ifColors; // Map each if-statement to the set of colors (split blocks) // that will get a copy of that if-statement // CONSTRUCTORS @@ -657,7 +652,7 @@ private: UINFO(8, " SVL " << vertexp << " has color " << color << "\n"); // Record that all containing ifs have this color. - for (IfStack::const_iterator it = m_ifStack.begin(); it != m_ifStack.end(); ++it) { + for (auto it = m_ifStack.cbegin(); it != m_ifStack.cend(); ++it) { m_ifColors[*it].insert(color); } } @@ -686,8 +681,7 @@ class EmitSplitVisitor final : public AstNVisitor { const IfColorVisitor* m_ifColorp; // Digest of results of prior coloring // Map each color to our current place within the color's new always - typedef std::unordered_map LocMap; - LocMap m_addAfter; + std::unordered_map m_addAfter; AlwaysVec* m_newBlocksp; // Split always blocks we have generated @@ -794,8 +788,7 @@ private: }; class RemovePlaceholdersVisitor final : public AstNVisitor { - typedef std::unordered_set NodeSet; - NodeSet m_removeSet; // placeholders to be removed + std::unordered_set m_removeSet; // placeholders to be removed public: explicit RemovePlaceholdersVisitor(AstNode* nodep) { iterate(nodep); @@ -817,8 +810,7 @@ private: // Keys are original always blocks pending delete, // values are newly split always blocks pending insertion // at the same position as the originals: - typedef std::unordered_map ReplaceMap; - ReplaceMap m_replaceBlocks; + std::unordered_map m_replaceBlocks; // AstNodeIf* whose condition we're currently visiting AstNode* m_curIfConditional = nullptr; @@ -831,8 +823,7 @@ public: // Splice newly-split blocks into the tree. Remove placeholders // from newly-split blocks. Delete the original always blocks // that we're replacing. - for (ReplaceMap::iterator it = m_replaceBlocks.begin(); it != m_replaceBlocks.end(); - ++it) { + for (auto it = m_replaceBlocks.begin(); it != m_replaceBlocks.end(); ++it) { AstAlways* origp = it->first; for (AlwaysVec::iterator addme = it->second.begin(); addme != it->second.end(); ++addme) { @@ -851,7 +842,7 @@ protected: virtual void makeRvalueEdges(SplitVarStdVertex* vstdp) override { // Each 'if' depends on rvalues in its own conditional ONLY, // not rvalues in the if/else bodies. - for (VStack::const_iterator it = m_stmtStackps.begin(); it != m_stmtStackps.end(); ++it) { + for (auto it = m_stmtStackps.cbegin(); it != m_stmtStackps.cend(); ++it) { AstNodeIf* ifNodep = VN_CAST((*it)->nodep(), NodeIf); if (ifNodep && (m_curIfConditional != ifNodep)) continue; new SplitRVEdge(&m_graph, *it, vstdp); diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp index a6b33376b..262d15b08 100644 --- a/src/V3SplitVar.cpp +++ b/src/V3SplitVar.cpp @@ -334,12 +334,9 @@ public: // Found nodes for SplitPackedVarVisitor struct RefsInModule { - typedef std::set VarSet; - typedef std::set VarRefSet; - typedef std::set SelSet; - VarSet m_vars; - VarRefSet m_refs; - SelSet m_sels; + std::set m_vars; + std::set m_refs; + std::set m_sels; public: void add(AstVar* nodep) { m_vars.insert(nodep); } @@ -362,7 +359,7 @@ public: } void visit(AstNVisitor* visitor) { for (const auto& varp : m_vars) visitor->iterate(varp); - for (SelSet::iterator it = m_sels.begin(), it_end = m_sels.end(); it != it_end; ++it) { + for (auto it = m_sels.begin(), it_end = m_sels.end(); it != it_end; ++it) { // If m_refs includes VarRef from ArraySel, remove it // because the VarRef would not be visited in SplitPackedVarVisitor::visit(AstSel*). if (AstVarRef* refp = VN_CAST((*it)->fromp(), VarRef)) { @@ -375,7 +372,7 @@ public: UASSERT_OBJ(reinterpret_cast((*it)->op1p()) != 1, *it, "stale"); visitor->iterate(*it); } - for (VarRefSet::iterator it = m_refs.begin(), it_end = m_refs.end(); it != it_end; ++it) { + for (auto it = m_refs.begin(), it_end = m_refs.end(); it != it_end; ++it) { UASSERT_OBJ(reinterpret_cast((*it)->op1p()) != 1, *it, "stale"); visitor->iterate(*it); } @@ -871,13 +868,11 @@ class PackedVarRef final { bool m_dedupDone = false; static void dedupRefs(std::vector& refs) { // Use raw pointer to dedup - typedef std::map NodeIndices; - NodeIndices nodes; + std::map nodes; for (size_t i = 0; i < refs.size(); ++i) { nodes.emplace(refs[i].nodep(), i); } std::vector vect; vect.reserve(nodes.size()); - for (NodeIndices::const_iterator it = nodes.begin(), it_end = nodes.end(); it != it_end; - ++it) { + for (auto it = nodes.cbegin(), it_end = nodes.cend(); it != it_end; ++it) { vect.push_back(refs[it->second]); } refs.swap(vect); @@ -955,12 +950,11 @@ public: }; class SplitPackedVarVisitor final : public AstNVisitor, public SplitVarImpl { - typedef std::map PackedVarRefMap; AstNetlist* m_netp; AstNodeModule* m_modp = nullptr; // Current module (just for log) int m_numSplit = 0; // Total number of split variables // key:variable to be split. value:location where the variable is referenced. - PackedVarRefMap m_refs; + std::map m_refs; virtual void visit(AstNodeFTask* nodep) override { if (!cannotSplitTaskReason(nodep)) iterateChildren(nodep); } @@ -1163,8 +1157,7 @@ class SplitPackedVarVisitor final : public AstNVisitor, public SplitVarImpl { } // Do the actual splitting operation void split() { - for (PackedVarRefMap::iterator it = m_refs.begin(), it_end = m_refs.end(); it != it_end; - ++it) { + for (auto it = m_refs.begin(), it_end = m_refs.end(); it != it_end; ++it) { it->second.dedup(); AstVar* varp = it->first; UINFO(3, "In module " << m_modp->name() << " var " << varp->prettyNameQ() diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp index 530a06901..0c5d4b43f 100644 --- a/src/V3StatsReport.cpp +++ b/src/V3StatsReport.cpp @@ -49,8 +49,7 @@ class StatsReport final { void sumit() { // If sumit is set on a statistic, combine with others of same name - typedef std::multimap ByName; - ByName byName; + std::multimap byName; // * is always first for (auto& itr : s_allStats) { V3Statistic* repp = &itr; @@ -72,8 +71,7 @@ class StatsReport final { void stars() { // Find all stages size_t maxWidth = 0; - typedef std::multimap ByName; - ByName byName; + std::multimap byName; // * is always first for (const auto& itr : s_allStats) { const V3Statistic* repp = &itr; @@ -112,13 +110,11 @@ class StatsReport final { // Find all stages int stage = 0; size_t maxWidth = 0; - typedef std::vector Stages; - Stages stages; + std::vector stages; std::unordered_map stageInt; - typedef std::multimap ByName; - ByName byName; + std::multimap byName; // * is always first - for (StatColl::iterator it = s_allStats.begin(); it != s_allStats.end(); ++it) { + for (auto it = s_allStats.begin(); it != s_allStats.end(); ++it) { const V3Statistic* repp = &(*it); if (repp->stage() != "*" && repp->printit()) { if (maxWidth < repp->name().length()) maxWidth = repp->name().length(); @@ -144,7 +140,7 @@ class StatsReport final { string lastName = "__NONE__"; string lastCommaName = "__NONE__"; unsigned col = 0; - for (ByName::const_iterator it = byName.begin(); it != byName.end(); ++it) { + for (auto it = byName.cbegin(); it != byName.cend(); ++it) { const V3Statistic* repp = it->second; if (lastName != repp->name()) { lastName = repp->name(); diff --git a/src/V3String.h b/src/V3String.h index 60b4d03b2..b5e14cb3a 100644 --- a/src/V3String.h +++ b/src/V3String.h @@ -194,9 +194,8 @@ class VSpellCheck final { static constexpr unsigned LENGTH_LIMIT = 100; // Maximum string length to search // TYPES typedef unsigned int EditDistance; - typedef std::vector Candidates; // MEMBERS - Candidates m_candidates; // Strings we try to match + std::vector m_candidates; // Strings we try to match public: // CONSTRUCTORS VSpellCheck() = default; diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index f0666448d..ea33d5236 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -74,8 +74,7 @@ public: typedef TspVertexTmpl Vertex; // MEMBERS - typedef std::unordered_map VMap; - VMap m_vertices; // T_Key to Vertex lookup map + std::unordered_map m_vertices; // T_Key to Vertex lookup map // CONSTRUCTORS TspGraphTmpl() diff --git a/src/V3Table.cpp b/src/V3Table.cpp index 37ef613e1..6e35b8d10 100644 --- a/src/V3Table.cpp +++ b/src/V3Table.cpp @@ -77,8 +77,7 @@ private: // State cleared on each module AstNodeModule* m_modp = nullptr; // Current MODULE int m_modTables = 0; // Number of tables created in this module - typedef std::deque ModTableVector; - ModTableVector m_modTableVscs; // All tables created + std::deque m_modTableVscs; // All tables created // State cleared on each scope AstScope* m_scopep = nullptr; // Current SCOPE @@ -222,8 +221,7 @@ private: void createTableVars(AstNode* nodep) { // Create table for each output - typedef std::map NameCounts; - NameCounts namecounts; + std::map namecounts; for (const AstVarScope* outvscp : m_outVarps) { AstVar* outvarp = outvscp->varp(); FileLine* fl = nodep->fileline(); diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 8f0663b1e..02f1136b7 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -105,7 +105,6 @@ private: // TYPES typedef std::map, AstVarScope*> VarToScopeMap; typedef std::unordered_map FuncToClassMap; - typedef std::vector Initials; // MEMBERS VarToScopeMap m_varToScopeMap; // Map for Var -> VarScope mappings FuncToClassMap m_funcToClassMap; // Map for ctor func -> class @@ -114,7 +113,7 @@ private: AstClass* m_classp = nullptr; // Current class V3Graph m_callGraph; // Task call graph TaskBaseVertex* m_curVxp; // Current vertex we're adding to - Initials m_initialps; // Initial blocks to move + std::vector m_initialps; // Initial blocks to move public: // METHODS @@ -1470,8 +1469,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp) // Missing pin/expr? We return (pinvar, nullptr) // Extra pin/expr? We clean it up - typedef std::map NameToIndex; - NameToIndex nameToIndex; + std::map nameToIndex; V3TaskConnects tconnects; UASSERT_OBJ(nodep->taskp(), nodep, "unlinked"); diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 1c5bbdfc2..21cc16c4c 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -200,7 +200,6 @@ private: // TYPES typedef std::map, AstVar*> TableMap; typedef std::map PatVecMap; - typedef std::map DTypeQMap; // STATE WidthVP* m_vup = nullptr; // Current node state @@ -214,7 +213,8 @@ private: bool m_doGenerate; // Do errors later inside generate statement int m_dtTables = 0; // Number of created data type tables TableMap m_tableMap; // Created tables so can remove duplicates - DTypeQMap m_queueDTypeIndexed; // Queues with given index type + std::map + m_queueDTypeIndexed; // Queues with given index type // ENUMS enum ExtendRule : uint8_t { @@ -3336,7 +3336,7 @@ private: // which member each AstPatMember corresponds to before we can // determine the dtypep for that PatMember's value, and then // width the initial value appropriately. - typedef std::map PatMap; + using PatMap = std::map; PatMap patmap; { AstMemberDType* memp = vdtypep->membersp(); From 3a55600913c528c42f08a5de55b5b20676a4cbc4 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 12 Mar 2021 18:10:45 -0500 Subject: [PATCH 004/110] Internals: Restyle with C++11 using replacing typedef --- include/verilated.cpp | 2 +- include/verilated.h | 4 ++-- include/verilated_cov.cpp | 9 ++++----- include/verilated_heavy.h | 14 +++++++------- include/verilated_imp.h | 8 ++++---- include/verilated_threads.h | 6 +++--- include/verilated_trace.h | 4 ++-- include/verilated_vcd_c.h | 2 +- include/verilated_vpi.cpp | 6 +++--- src/V3Active.cpp | 2 +- src/V3Ast.h | 4 ++-- src/V3AstNodes.h | 6 +++--- src/V3Broken.cpp | 2 +- src/V3CUse.cpp | 2 +- src/V3Combine.cpp | 2 +- src/V3Config.cpp | 20 ++++++++++---------- src/V3Coverage.cpp | 2 +- src/V3Dead.cpp | 2 +- src/V3Delayed.cpp | 2 +- src/V3Descope.cpp | 2 +- src/V3EmitC.cpp | 6 +++--- src/V3EmitCSyms.cpp | 12 ++++++------ src/V3Error.h | 4 ++-- src/V3File.cpp | 2 +- src/V3File.h | 2 +- src/V3Gate.cpp | 2 +- src/V3Graph.h | 2 +- src/V3GraphAcyc.cpp | 6 +++--- src/V3GraphDfa.cpp | 4 ++-- src/V3GraphDfa.h | 2 +- src/V3GraphStream.h | 4 ++-- src/V3Hashed.h | 4 ++-- src/V3HierBlock.cpp | 6 +++--- src/V3HierBlock.h | 14 +++++++------- src/V3Inline.cpp | 4 ++-- src/V3LanguageWords.h | 4 ++-- src/V3Life.cpp | 4 ++-- src/V3LifePost.cpp | 2 +- src/V3LinkDot.cpp | 4 ++-- src/V3LinkLevel.cpp | 2 +- src/V3LinkLevel.h | 2 +- src/V3LinkParse.cpp | 2 +- src/V3Number.h | 4 ++-- src/V3Options.cpp | 2 +- src/V3Options.h | 10 +++++----- src/V3Order.cpp | 10 +++++----- src/V3Param.cpp | 18 +++++++++--------- src/V3ParseSym.h | 2 +- src/V3Partition.cpp | 26 +++++++++++++------------- src/V3Partition.h | 2 +- src/V3PartitionGraph.h | 2 +- src/V3PreProc.cpp | 4 ++-- src/V3Randomize.cpp | 4 ++-- src/V3Scope.cpp | 2 +- src/V3Scoreboard.h | 26 +++++++++++++------------- src/V3SenTree.h | 2 +- src/V3Simulate.h | 4 ++-- src/V3Split.cpp | 6 +++--- src/V3SplitVar.cpp | 14 +++++++------- src/V3Stats.cpp | 2 +- src/V3StatsReport.cpp | 2 +- src/V3String.h | 2 +- src/V3SymTable.h | 8 ++++---- src/V3TSP.cpp | 12 ++++++------ src/V3TSP.h | 2 +- src/V3Task.cpp | 6 +++--- src/V3Task.h | 4 ++-- src/V3Trace.cpp | 4 ++-- src/V3Tristate.cpp | 6 +++--- src/V3Waiver.h | 2 +- src/V3Width.cpp | 4 ++-- src/VlcOptions.h | 2 +- src/VlcPoint.h | 6 +++--- src/VlcSource.h | 8 ++++---- src/VlcTest.h | 4 ++-- src/config_build.h.in | 2 +- 76 files changed, 204 insertions(+), 205 deletions(-) diff --git a/include/verilated.cpp b/include/verilated.cpp index 0421b0438..3d3f8bddc 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -2556,7 +2556,7 @@ const char* Verilated::catName(const char* n1, const char* n2, const char* delim // Keeping these out of class Verilated to avoid having to include // in verilated.h (for compilation speed) -typedef std::list> VoidPCbList; +using VoidPCbList = std::list>; static struct { VerilatedMutex s_flushMutex; VoidPCbList s_flushCbs VL_GUARDED_BY(s_flushMutex); diff --git a/include/verilated.h b/include/verilated.h index 580cc2753..980beda10 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -569,10 +569,10 @@ public: // But for internal use only class VerilatedScope final { public: - typedef enum : vluint8_t { + enum Type : vluint8_t { SCOPE_MODULE, SCOPE_OTHER - } Type; // Type of a scope, currently module is only interesting + }; // Type of a scope, currently module is only interesting private: // Fastpath: VerilatedSyms* m_symsp = nullptr; ///< Symbol table diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index 85904d9d6..a4311e4fb 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -92,9 +92,9 @@ public: class VerilatedCovImp final : public VerilatedCovContext { private: // TYPES - typedef std::map ValueIndexMap; - typedef std::map IndexValueMap; - typedef std::deque ItemList; + using ValueIndexMap = std::map; + using IndexValueMap = std::map; + using ItemList = std::deque; // MEMBERS VerilatedMutex m_mutex; ///< Protects all members @@ -357,8 +357,7 @@ public: os << "# SystemC::Coverage-3\n"; // Build list of events; totalize if collapsing hierarchy - typedef std::map> EventMap; - EventMap eventCounts; + std::map> eventCounts; for (const auto& itemp : m_items) { std::string name; std::string hier; diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index cfc013b2c..6b0f52039 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -49,7 +49,7 @@ extern std::string VL_TO_STRING_W(int words, WDataInP obj); class VlURNG final { public: - typedef size_t result_type; + using result_type = size_t; static constexpr size_t min() { return 0; } static constexpr size_t max() { return 1ULL << 31; } size_t operator()() { return VL_MASK_I(31) & VL_RANDOM_I(32); } @@ -142,10 +142,10 @@ template std::string VL_TO_STRING(const VlWide& o template class VlQueue final { private: // TYPES - typedef std::deque Deque; + using Deque = std::deque; public: - typedef typename Deque::const_iterator const_iterator; + using const_iterator = typename Deque::const_iterator; private: // MEMBERS @@ -497,10 +497,10 @@ template std::string VL_TO_STRING(const VlQueue& obj) { template class VlAssocArray final { private: // TYPES - typedef std::map Map; + using Map = std::map; public: - typedef typename Map::const_iterator const_iterator; + using const_iterator = typename Map::const_iterator; private: // MEMBERS @@ -801,10 +801,10 @@ void VL_WRITEMEM_N(bool hex, int bits, const std::string& filename, template class VlUnpacked final { private: // TYPES - typedef std::array Array; + using Array = std::array; public: - typedef typename Array::const_iterator const_iterator; + using const_iterator = typename Array::const_iterator; private: // MEMBERS diff --git a/include/verilated_imp.h b/include/verilated_imp.h index 4c462d0f1..62a5671b8 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -80,7 +80,7 @@ public: /// This assumes no thread starts pushing the next tick until the previous has drained. /// If more aggressiveness is needed, a double-buffered scheme might work well. class VerilatedEvalMsgQueue final { - typedef std::multiset VerilatedThreadQueue; + using VerilatedThreadQueue = std::multiset; std::atomic m_depth; ///< Current depth of queue (see comments below) @@ -180,7 +180,7 @@ class VerilatedFpList final { std::size_t m_sz = 0; public: - typedef FILE* const* const_iterator; + using const_iterator = FILE* const*; explicit VerilatedFpList() {} const_iterator begin() const { return m_fp; } const_iterator end() const { return m_fp + m_sz; } @@ -398,8 +398,8 @@ protected: friend class VerilatedImp; // TYPES - typedef std::map, void*> UserMap; - typedef std::map ExportNameMap; + using UserMap = std::map, void*>; + using ExportNameMap = std::map; // MEMBERS // Nothing below here is save-restored; users expected to re-register appropriately diff --git a/include/verilated_threads.h b/include/verilated_threads.h index c7ddc4467..2231dded9 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -47,9 +47,9 @@ // VlMTaskVertex and VlThreadpool will work with multiple symbol table types. // Since the type is opaque to VlMTaskVertex and VlThreadPool, represent it // as a void* here. -typedef void* VlThrSymTab; +using VlThrSymTab = void*; -typedef void (*VlExecFnp)(bool, VlThrSymTab); +using VlExecFnp = void (*)(bool, VlThrSymTab); /// Track dependencies for a single MTask. class VlMTaskVertex final { @@ -251,7 +251,7 @@ public: class VlThreadPool final { // TYPES - typedef std::vector ProfileTrace; + using ProfileTrace = std::vector; // MEMBERS std::vector m_workers; // our workers diff --git a/include/verilated_trace.h b/include/verilated_trace.h index d5f9a5cb6..56d6373ca 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -114,8 +114,8 @@ public: //========================================================================= // Generic tracing internals - typedef void (*initCb_t)(void*, T_Derived*, uint32_t); // Type of init callbacks - typedef void (*dumpCb_t)(void*, T_Derived*); // Type of all but init callbacks + using initCb_t = void (*)(void*, T_Derived*, vluint32_t); // Type of init callbacks + using dumpCb_t = void (*)(void*, T_Derived*); // Type of all but init callbacks private: struct CallbackRecord { diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 37adbdd50..02431c9a0 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -76,7 +76,7 @@ private: std::vector m_suffixes; ///< VCD line end string codes + metadata const char* m_suffixesp; ///< Pointer to first element of above - typedef std::map NameMap; + using NameMap = std::map; NameMap* m_namemapp = nullptr; ///< List of names for the header void bufferResize(vluint64_t minsize); diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 2a9afdaeb..f788dabf3 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -456,7 +456,7 @@ public: //====================================================================== -typedef PLI_INT32 (*VerilatedPliCb)(struct t_cb_data*); +using VerilatedPliCb = PLI_INT32 (*)(struct t_cb_data*); class VerilatedVpiCbHolder final { // Holds information needed to call a callback @@ -502,8 +502,8 @@ class VerilatedVpiError; class VerilatedVpiImp final { enum { CB_ENUM_MAX_VALUE = cbAtEndOfSimTime + 1 }; // Maxium callback reason - typedef std::list VpioCbList; - typedef std::map, VerilatedVpiCbHolder> VpioTimedCbs; + using VpioCbList = std::list; + using VpioTimedCbs = std::map, VerilatedVpiCbHolder>; // All only medium-speed, so use singleton function VpioCbList m_cbObjLists[CB_ENUM_MAX_VALUE]; // Callbacks for each supported reason diff --git a/src/V3Active.cpp b/src/V3Active.cpp index c90016af5..221bada4f 100644 --- a/src/V3Active.cpp +++ b/src/V3Active.cpp @@ -211,7 +211,7 @@ private: AstActive* m_cActivep = nullptr; // For current scope, the SActive(combo) we're building SenTreeSet m_activeSens; // Sen lists for each active we've made - typedef std::unordered_map ActiveMap; + using ActiveMap = std::unordered_map; ActiveMap m_activeMap; // Map sentree to active, for folding. // METHODS diff --git a/src/V3Ast.h b/src/V3Ast.h index fa9e03d79..3c838d9c4 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -42,7 +42,7 @@ class VFlagBitPacked {}; class VFlagChildDType {}; // Used by parser.y to select constructor that sets childDType // Used as key for another map, needs operator<, hence not an unordered_set -typedef std::set MTaskIdSet; // Set of mtaskIds for Var sorting +using MTaskIdSet = std::set; // Set of mtaskIds for Var sorting //###################################################################### @@ -2468,7 +2468,7 @@ class AstNodeUOrStructDType VL_NOT_FINAL : public AstNodeDType { // A struct or union; common handling private: // TYPES - typedef std::map MemberNameMap; + using MemberNameMap = std::map; // MEMBERS string m_name; // Name from upper typedef, if any bool m_packed; diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index ae7a23f27..d47b7767a 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -296,7 +296,7 @@ public: class AstClass final : public AstNodeModule { // TYPES - typedef std::map MemberNameMap; + using MemberNameMap = std::map; // MEMBERS MemberNameMap m_members; // Members or method children AstClassPackage* m_classOrPackagep = nullptr; // Class package this is under @@ -4980,7 +4980,7 @@ class AstInitArray final : public AstNode { // Parents: ASTVAR::init() // Children: AstInitItem public: - typedef std::map KeyItemMap; + using KeyItemMap = std::map; private: KeyItemMap m_map; // Node value for each array index @@ -9180,7 +9180,7 @@ class AstTypeTable final : public AstNode { AstQueueDType* m_queueIndexp = nullptr; AstBasicDType* m_basicps[AstBasicDTypeKwd::_ENUM_MAX]; // - typedef std::map DetailedMap; + using DetailedMap = std::map; DetailedMap m_detailedMap; public: diff --git a/src/V3Broken.cpp b/src/V3Broken.cpp index 5df76d8e7..613b4cf2f 100644 --- a/src/V3Broken.cpp +++ b/src/V3Broken.cpp @@ -41,7 +41,7 @@ class BrokenTable VL_NOT_FINAL : public AstNVisitor { private: // MEMBERS // For each node, we keep if it exists or not. - typedef std::unordered_map NodeMap; // Performance matters (when --debug) + using NodeMap = std::unordered_map; // Performance matters (when --debug) static NodeMap s_nodes; // Set of all nodes that exist // BITMASK enum { FLAG_ALLOCATED = 0x01 }; // new() and not delete()ed diff --git a/src/V3CUse.cpp b/src/V3CUse.cpp index 8aa7c1513..3eb65f13e 100644 --- a/src/V3CUse.cpp +++ b/src/V3CUse.cpp @@ -40,7 +40,7 @@ class CUseState final { private: // MEMBERS AstNodeModule* m_modInsertp; // Current module to insert AstCUse under - typedef std::pair UseString; + using UseString = std::pair; std::map m_didUse; // What we already used // NODE STATE diff --git a/src/V3Combine.cpp b/src/V3Combine.cpp index f74364a4b..bb9c081aa 100644 --- a/src/V3Combine.cpp +++ b/src/V3Combine.cpp @@ -67,7 +67,7 @@ class CombCallVisitor final : CombBaseVisitor { // Find all CCALLS of each CFUNC, so that we can later rename them private: // NODE STATE - typedef std::multimap CallMmap; + using CallMmap = std::multimap; CallMmap m_callMmap; // Associative array of {function}{call} // METHODS public: diff --git a/src/V3Config.cpp b/src/V3Config.cpp index 93b4ebecf..c8b9f936d 100644 --- a/src/V3Config.cpp +++ b/src/V3Config.cpp @@ -33,7 +33,7 @@ // cache of resolved entities. Entities stored in this container need an update // function that takes a reference of this type to join multiple entities into one. template class V3ConfigWildcardResolver { - typedef std::map Map; + using Map = std::map; Map m_mapWildcard; // Wildcard strings to entities Map m_mapResolved; // Resolved strings to converged entities @@ -111,7 +111,7 @@ public: } }; -typedef V3ConfigWildcardResolver V3ConfigVarResolver; +using V3ConfigVarResolver = V3ConfigWildcardResolver; //###################################################################### // Function or task: Have variables and properties @@ -148,7 +148,7 @@ public: } }; -typedef V3ConfigWildcardResolver V3ConfigFTaskResolver; +using V3ConfigFTaskResolver = V3ConfigWildcardResolver; //###################################################################### // Modules have tasks, variables, named blocks and properties @@ -212,7 +212,7 @@ public: } }; -typedef V3ConfigWildcardResolver V3ConfigModuleResolver; +using V3ConfigModuleResolver = V3ConfigWildcardResolver; //###################################################################### // Files have: @@ -246,14 +246,14 @@ std::ostream& operator<<(std::ostream& os, const V3ConfigIgnoresLine& rhs) { // Some attributes are attached to entities of the occur on a fileline // and multiple attributes can be attached to a line -typedef std::bitset V3ConfigLineAttribute; +using V3ConfigLineAttribute = std::bitset; // File entity class V3ConfigFile final { - typedef std::map LineAttrMap; // Map line->bitset of attributes - typedef std::multiset IgnLines; // list of {line,code,on} - typedef std::pair WaiverSetting; // Waive code if string matches - typedef std::vector Waivers; // List of {code,wildcard string} + using LineAttrMap = std::map; // Map line->bitset of attributes + using IgnLines = std::multiset; // list of {line,code,on} + using WaiverSetting = std::pair; // Waive code if string matches + using Waivers = std::vector; // List of {code,wildcard string} LineAttrMap m_lineAttrs; // Atributes to line mapping IgnLines m_ignLines; // Ignore line settings @@ -338,7 +338,7 @@ public: } }; -typedef V3ConfigWildcardResolver V3ConfigFileResolver; +using V3ConfigFileResolver = V3ConfigWildcardResolver; //###################################################################### // Resolve modules and files in the design diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index 7ad84e8cb..d7aee3ee0 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -40,7 +40,7 @@ class CoverageVisitor final : public AstNVisitor { private: // TYPES - typedef std::set LinenoSet; + using LinenoSet = std::set; struct ToggleEnt { string m_comment; // Comment for coverage dump diff --git a/src/V3Dead.cpp b/src/V3Dead.cpp index f05ac9394..b08c5e78c 100644 --- a/src/V3Dead.cpp +++ b/src/V3Dead.cpp @@ -79,7 +79,7 @@ private: AstUser1InUse m_inuser1; // TYPES - typedef std::multimap AssignMap; + using AssignMap = std::multimap; // STATE AstNodeModule* m_modp = nullptr; // Current module diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index 553f38d59..db00cd2aa 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -94,7 +94,7 @@ private: bool m_inDly = false; // True in delayed assignments bool m_inLoop = false; // True in for loops bool m_inInitial = false; // True in initial blocks - typedef std::map, AstVar*> VarMap; + using VarMap = std::map, AstVar*>; VarMap m_modVarMap; // Table of new var names created under module VDouble0 m_statSharedSet; // Statistic tracking std::unordered_map m_scopeVecMap; // Next var number for each scope diff --git a/src/V3Descope.cpp b/src/V3Descope.cpp index c9aa2bc88..3e40fa3ee 100644 --- a/src/V3Descope.cpp +++ b/src/V3Descope.cpp @@ -42,7 +42,7 @@ private: AstUser1InUse m_inuser1; // TYPES - typedef std::multimap FuncMmap; + using FuncMmap = std::multimap; // STATE AstNodeModule* m_modp = nullptr; // Current module diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 95942d878..0a1416f1d 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -41,8 +41,8 @@ constexpr int EMITC_NUM_CONSTW class EmitCStmts VL_NOT_FINAL : public EmitCBaseVisitor { private: - typedef std::vector VarVec; - typedef std::map VarSortMap; // Map size class to VarVec + using VarVec = std::vector; + using VarSortMap = std::map; // Map size class to VarVec bool m_suppressSemi; AstVarRef* m_wideTempRefp; // Variable that _WW macros should be setting @@ -2957,7 +2957,7 @@ void EmitCStmts::emitVarSort(const VarSortMap& vmap, VarVec* sortedp) { } // MacroTask mode. Sort by MTask-affinity group first, size second. - typedef std::map MTaskVarSortMap; + using MTaskVarSortMap = std::map; MTaskVarSortMap m2v; for (VarSortMap::const_iterator it = vmap.begin(); it != vmap.end(); ++it) { int size_class = it->first; diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index d0cfe9632..cbdff09a8 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -71,11 +71,11 @@ class EmitCSyms final : EmitCBaseVisitor { , m_modp{modp} , m_scopep{scopep} {} }; - typedef std::map ScopeNames; - typedef std::pair ScopeModPair; - typedef std::pair ModVarPair; - typedef std::vector ScopeNameList; - typedef std::map ScopeNameHierarchy; + using ScopeNames = std::map; + using ScopeModPair = std::pair; + using ModVarPair = std::pair; + using ScopeNameList = std::vector; + using ScopeNameHierarchy = std::map; struct CmpName { bool operator()(const ScopeModPair& lhsp, const ScopeModPair& rhsp) const { return lhsp.first->name() < rhsp.first->name(); @@ -401,7 +401,7 @@ void EmitCSyms::emitSymHdr() { AstCFunc* funcp = itr.second.m_cfuncp; if (funcp->dpiExport()) { string cbtype = protect(v3Global.opt.prefix() + "__Vcb_" + funcp->cname() + "_t"); - types["typedef void (*" + cbtype + ") (" + cFuncArgs(funcp) + ");\n"] = 1; + types["using " + cbtype + " = void (*) (" + cFuncArgs(funcp) + ");\n"] = 1; } } for (const auto& i : types) puts(i.first); diff --git a/src/V3Error.h b/src/V3Error.h index 89e9878c1..1b8ff02ed 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -226,8 +226,8 @@ inline std::ostream& operator<<(std::ostream& os, const V3ErrorCode& rhs) { class V3Error final { // Base class for any object that wants debugging and error reporting - typedef std::set MessagesSet; - typedef void (*ErrorExitCb)(void); + using MessagesSet = std::set; + using ErrorExitCb = void (*)(void); private: static bool s_describedWarnings; // Told user how to disable warns diff --git a/src/V3File.cpp b/src/V3File.cpp index 9edea35ea..63920e061 100644 --- a/src/V3File.cpp +++ b/src/V3File.cpp @@ -328,7 +328,7 @@ void V3File::createMakeDir() { // VInFilterImp class VInFilterImp final { - typedef VInFilter::StrList StrList; + using StrList = VInFilter::StrList; std::map m_contentsMap; // Cache of file contents bool m_readEof = false; // Received EOF on read diff --git a/src/V3File.h b/src/V3File.h index 35df9efbe..b198a10b4 100644 --- a/src/V3File.h +++ b/src/V3File.h @@ -79,7 +79,7 @@ class VInFilterImp; class VInFilter final { public: // TYPES - typedef std::list StrList; + using StrList = std::list; private: VInFilterImp* m_impp; diff --git a/src/V3Gate.cpp b/src/V3Gate.cpp index cb329f785..913c6c645 100644 --- a/src/V3Gate.cpp +++ b/src/V3Gate.cpp @@ -37,7 +37,7 @@ #include #include -typedef std::list GateVarRefList; +using GateVarRefList = std::list; constexpr int GATE_DEDUP_MAX_DEPTH = 20; diff --git a/src/V3Graph.h b/src/V3Graph.h index 399a93982..1b03c8a7e 100644 --- a/src/V3Graph.h +++ b/src/V3Graph.h @@ -37,7 +37,7 @@ class OrderLogicVertex; // Most graph algorithms accept an arbitrary function that returns // True for those edges we should honor. -typedef bool (*V3EdgeFuncP)(const V3GraphEdge* edgep); +using V3EdgeFuncP = bool (*)(const V3GraphEdge* edgep); //============================================================================= // When the Graph represents a directional acyclical graph (DAG), following diff --git a/src/V3GraphAcyc.cpp b/src/V3GraphAcyc.cpp index f18a432f7..cd0663a5c 100644 --- a/src/V3GraphAcyc.cpp +++ b/src/V3GraphAcyc.cpp @@ -56,7 +56,7 @@ public: class GraphAcycEdge final : public V3GraphEdge { // userp() is always used to point to the head original graph edge private: - typedef std::list OrigEdgeList; // List of orig edges, see also GraphAcyc's decl + using OrigEdgeList = std::list; // List of orig edges, see also GraphAcyc's decl V3GraphEdge* origEdgep() const { OrigEdgeList* oEListp = static_cast(userp()); if (!oEListp) v3fatalSrc("No original edge associated with acyc edge " << this); @@ -89,8 +89,8 @@ struct GraphAcycEdgeCmp { // CLASSES class GraphAcyc final { private: - typedef std::list - OrigEdgeList; // List of orig edges, see also GraphAcycEdge's decl + using OrigEdgeList + = std::list; // List of orig edges, see also GraphAcycEdge's decl // GRAPH USERS // origGraph // GraphVertex::user() GraphAycVerted* New graph node diff --git a/src/V3GraphDfa.cpp b/src/V3GraphDfa.cpp index 135187e3e..a619c23d9 100644 --- a/src/V3GraphDfa.cpp +++ b/src/V3GraphDfa.cpp @@ -58,8 +58,8 @@ class GraphNfaToDfa final : GraphAlg<> { // Edges from DFA to DFA indicate a completed input transition private: // TYPES - typedef std::deque DfaStates; - typedef std::multimap HashMap; + using DfaStates = std::deque; + using HashMap = std::multimap; // MEMBERS uint32_t m_step; // Processing step, so we can avoid clearUser all the time diff --git a/src/V3GraphDfa.h b/src/V3GraphDfa.h index 1a102bf47..854a4074f 100644 --- a/src/V3GraphDfa.h +++ b/src/V3GraphDfa.h @@ -108,7 +108,7 @@ public: //============================================================================ /// Abstract type indicating a specific "input" to the NFA /// DFA assumes each .toInt() is unique -typedef VNUser DfaInput; +using DfaInput = VNUser; //============================================================================ // Edge types diff --git a/src/V3GraphStream.h b/src/V3GraphStream.h index 4f62b50eb..196aa60ef 100644 --- a/src/V3GraphStream.h +++ b/src/V3GraphStream.h @@ -80,7 +80,7 @@ private: VL_UNCOPYABLE(VxHolderCmp); }; - typedef std::set ReadyVertices; + using ReadyVertices = std::set; // MEMBERS VxHolderCmp m_vxHolderCmp; // Vertext comparison functor @@ -227,6 +227,6 @@ private: // GraphStreamUnordered is GraphStream using a plain pointer compare to // break ties in the graph order. This WILL return nodes in // nondeterministic order. -typedef GraphStream> GraphStreamUnordered; +using GraphStreamUnordered = GraphStream>; #endif // Guard diff --git a/src/V3Hashed.h b/src/V3Hashed.h index 9ee62f099..07bdcb7d4 100644 --- a/src/V3Hashed.h +++ b/src/V3Hashed.h @@ -50,8 +50,8 @@ class V3Hashed final : public VHashedBase { // TYPES public: - typedef std::multimap HashMmap; - typedef HashMmap::iterator iterator; + using HashMmap = std::multimap; + using iterator = HashMmap::iterator; private: // MEMBERS diff --git a/src/V3HierBlock.cpp b/src/V3HierBlock.cpp index 3dd3f730e..afa858503 100644 --- a/src/V3HierBlock.cpp +++ b/src/V3HierBlock.cpp @@ -240,7 +240,7 @@ class HierBlockUsageCollectVisitor final : public AstNVisitor { AstUser1InUse m_inuser1; // STATE - typedef std::unordered_set ModuleSet; + using ModuleSet = std::unordered_set; V3HierBlockPlan* const m_planp; AstModule* m_modp = nullptr; // The current module AstModule* m_hierBlockp = nullptr; // The nearest parent module that is a hierarchical block @@ -355,8 +355,8 @@ void V3HierBlockPlan::createPlan(AstNetlist* nodep) { } V3HierBlockPlan::HierVector V3HierBlockPlan::hierBlocksSorted() const { - typedef std::unordered_map> - ChildrenMap; + using ChildrenMap + = std::unordered_map>; ChildrenMap childrenOfHierBlock; HierVector sorted; diff --git a/src/V3HierBlock.h b/src/V3HierBlock.h index 38caf5b8f..b9fac2c58 100644 --- a/src/V3HierBlock.h +++ b/src/V3HierBlock.h @@ -40,13 +40,13 @@ class AstVar; class V3HierBlock final { public: - typedef std::vector GParams; - typedef std::unordered_set HierBlockSet; + using GParams = std::vector; + using HierBlockSet = std::unordered_set; private: // TYPES // Parameter name, stringified value - typedef std::vector> StrGParams; + using StrGParams = std::vector>; // MEMBERS const AstNodeModule* m_modp; // Hierarchical block module @@ -96,16 +96,16 @@ public: // Holds relashonship between AstNodeModule and V3HierBlock class V3HierBlockPlan final { - typedef std::unordered_map HierMap; + using HierMap = std::unordered_map; HierMap m_blocks; V3HierBlockPlan() = default; VL_UNCOPYABLE(V3HierBlockPlan); public: - typedef HierMap::iterator iterator; - typedef HierMap::const_iterator const_iterator; - typedef std::vector HierVector; + using iterator = HierMap::iterator; + using const_iterator = HierMap::const_iterator; + using HierVector = std::vector; VL_DEBUG_FUNC; // Declare debug() bool isHierBlock(const AstNodeModule* modp) const; diff --git a/src/V3Inline.cpp b/src/V3Inline.cpp index d4c57a51a..73a1c0332 100644 --- a/src/V3Inline.cpp +++ b/src/V3Inline.cpp @@ -69,12 +69,12 @@ private: AstNodeModule* m_modp = nullptr; // Current module VDouble0 m_statUnsup; // Statistic tracking - typedef std::vector ModVec; + using ModVec = std::vector; ModVec m_allMods; // All modules, in top-down order. // Within the context of a given module, LocalInstanceMap maps // from child modules to the count of each child's local instantiations. - typedef std::unordered_map LocalInstanceMap; + using LocalInstanceMap = std::unordered_map; // We keep a LocalInstanceMap for each module in the design std::unordered_map m_instances; diff --git a/src/V3LanguageWords.h b/src/V3LanguageWords.h index dfcd6f83f..c5b19317d 100644 --- a/src/V3LanguageWords.h +++ b/src/V3LanguageWords.h @@ -27,7 +27,7 @@ class V3LanguageWords final { // List of common reserved keywords private: - typedef std::map KeywordMap; + using KeywordMap = std::map; struct Singleton { KeywordMap s_kwdMap; // List of keywords, and what language applies Singleton() { init(); } @@ -36,7 +36,7 @@ private: }; public: - typedef KeywordMap::const_iterator const_iterator; + using const_iterator = KeywordMap::const_iterator; // METHODS static const_iterator begin() { return s().s_kwdMap.begin(); } static const_iterator end() { return s().s_kwdMap.end(); } diff --git a/src/V3Life.cpp b/src/V3Life.cpp index 356d50ebd..2b7dc0541 100644 --- a/src/V3Life.cpp +++ b/src/V3Life.cpp @@ -123,7 +123,7 @@ class LifeBlock final { // LIFE MAP // For each basic block, we'll make a new map of what variables that if/else is changing - typedef std::unordered_map LifeMap; + using LifeMap = std::unordered_map; LifeMap m_map; // Current active lifetime map for current scope LifeBlock* m_aboveLifep; // Upper life, or nullptr LifeState* m_statep; // Current global state @@ -278,7 +278,7 @@ private: // LIFE MAP // For each basic block, we'll make a new map of what variables that if/else is changing - typedef std::unordered_map LifeMap; + using LifeMap = std::unordered_map; // cppcheck-suppress memleak // cppcheck bug - it is deleted LifeBlock* m_lifep; // Current active lifetime map for current scope diff --git a/src/V3LifePost.cpp b/src/V3LifePost.cpp index 9aea9b950..c74ff31da 100644 --- a/src/V3LifePost.cpp +++ b/src/V3LifePost.cpp @@ -145,7 +145,7 @@ private: // Map each varscope to one or more locations where it's accessed. // These maps will not include any ASSIGNPOST accesses: - typedef std::unordered_map> LocMap; + using LocMap = std::unordered_map>; LocMap m_reads; // VarScope read locations LocMap m_writes; // VarScope write locations diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 7a536434f..0126b6e44 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -140,8 +140,8 @@ public: private: // TYPES - typedef std::unordered_map ScopeAliasMap; - typedef std::vector> IfaceModSyms; + using ScopeAliasMap = std::unordered_map; + using IfaceModSyms = std::vector>; static LinkDotState* s_errorThisp; // Last self, for error reporting only diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index 96ef55d56..fd118f4a9 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -171,7 +171,7 @@ void V3LinkLevel::wrapTopCell(AstNetlist* rootp) { UASSERT_OBJ(newmodp && newmodp->isTop(), rootp, "No TOP module found to insert under"); // Find all duplicate signal names (if multitop) - typedef std::unordered_set NameSet; + using NameSet = std::unordered_set; NameSet ioNames; NameSet dupNames; // For all modules, skipping over new top diff --git a/src/V3LinkLevel.h b/src/V3LinkLevel.h index 4f52f7a60..9c42e6700 100644 --- a/src/V3LinkLevel.h +++ b/src/V3LinkLevel.h @@ -27,7 +27,7 @@ class V3LinkLevel final { private: - typedef std::vector ModVec; + using ModVec = std::vector; static void timescaling(const ModVec& mods); static void wrapTopCell(AstNetlist* rootp); diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index e5913888f..6f95b8eda 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -44,7 +44,7 @@ private: AstUser2InUse m_inuser2; // TYPES - typedef std::map, AstTypedef*> ImplTypedefMap; + using ImplTypedefMap = std::map, AstTypedef*>; // STATE AstVar* m_varp = nullptr; // Variable we're under diff --git a/src/V3Number.h b/src/V3Number.h index 92693fcd8..248461947 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -312,8 +312,8 @@ public: // STATICS static int log2b(uint32_t num); - typedef V3Number& (*UniopFuncp)(V3Number&); - typedef V3Number& (*BiopFuncp)(V3Number&, V3Number&); + using UniopFuncp = V3Number& (*)(V3Number&); + using BiopFuncp = V3Number& (*)(V3Number&, V3Number&); // MATH // "this" is the output, as we need the output width before some computations diff --git a/src/V3Options.cpp b/src/V3Options.cpp index c54149d81..eb0ff8828 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -54,7 +54,7 @@ class V3OptionsImp final { public: // TYPES - typedef std::map> DirMap; // Directory listing + using DirMap = std::map>; // Directory listing // STATE std::list m_allArgs; // List of every argument encountered diff --git a/src/V3Options.h b/src/V3Options.h index 4db85011a..27c9b0126 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -152,8 +152,8 @@ inline bool operator==(const TraceFormat& lhs, const TraceFormat& rhs) { inline bool operator==(const TraceFormat& lhs, TraceFormat::en rhs) { return lhs.m_e == rhs; } inline bool operator==(TraceFormat::en lhs, const TraceFormat& rhs) { return lhs == rhs.m_e; } -typedef std::vector V3StringList; -typedef std::set V3StringSet; +using V3StringList = std::vector; +using V3StringSet = std::set; //###################################################################### @@ -161,7 +161,7 @@ typedef std::set V3StringSet; class V3HierarchicalBlockOption final { public: // key:parameter name, value:value (as string) - typedef std::map ParamStrMap; + using ParamStrMap = std::map; private: string m_origName; // module name @@ -178,7 +178,7 @@ public: const ParamStrMap params() const { return m_parameters; } }; -typedef std::map V3HierBlockOptSet; +using V3HierBlockOptSet = std::map; //###################################################################### // V3Options - Command line options @@ -187,7 +187,7 @@ class V3Options final { public: private: // TYPES - typedef std::map DebugSrcMap; + using DebugSrcMap = std::map; // MEMBERS (general options) V3OptionsImp* m_impp; // Slow hidden options diff --git a/src/V3Order.cpp b/src/V3Order.cpp index 464f219c5..b68138ade 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -136,8 +136,8 @@ private: const AstSenTree* m_domainp; // Domain all vertices belong to const AstScope* m_scopep; // Scope all vertices belong to - typedef std::pair DomScopeKey; - typedef std::map DomScopeMap; + using DomScopeKey = std::pair; + using DomScopeMap = std::map; static DomScopeMap s_dsMap; // Structure registered for each dom/scope pairing public: @@ -421,8 +421,8 @@ template class ProcessMoveBuildGraph { // works the same way for both cases. // TYPES - typedef std::pair VxDomPair; - typedef std::unordered_map Logic2Move; + using VxDomPair = std::pair; + using Logic2Move = std::unordered_map; public: class MoveVertexMaker VL_NOT_FINAL { @@ -729,7 +729,7 @@ private: void process(); void processCircular(); - typedef std::deque VertexVec; + using VertexVec = std::deque; void processInputs(); void processInputsInIterate(OrderEitherVertex* vertexp, VertexVec& todoVec); void processInputsOutIterate(OrderEitherVertex* vertexp, VertexVec& todoVec); diff --git a/src/V3Param.cpp b/src/V3Param.cpp index a067f2c35..113ace5c6 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -67,11 +67,11 @@ // Hierarchical block and parameter db (modules without parameter is also handled) class ParameterizedHierBlocks final { - typedef std::multimap HierBlockOptsByOrigName; - typedef HierBlockOptsByOrigName::const_iterator HierMapIt; - typedef std::map HierBlockModMap; - typedef std::map> ParamConstMap; - typedef std::map GParamsMap; // key:parameter name value:parameter + using HierBlockOptsByOrigName = std::multimap; + using HierMapIt = HierBlockOptsByOrigName::const_iterator; + using HierBlockModMap = std::map; + using ParamConstMap = std::map>; + using GParamsMap = std::map; // key:parameter name value:parameter // MEMBERS // key:Original module name, value:HiearchyBlockOption* @@ -232,10 +232,10 @@ class ParamProcessor final { // TYPES // Note may have duplicate entries - typedef std::deque> IfaceRefRefs; + using IfaceRefRefs = std::deque>; // STATE - typedef std::unordered_map CloneMap; + using CloneMap = std::unordered_map; struct ModInfo { AstNodeModule* m_modp; // Module with specified name CloneMap m_cloneMap; // Map of old-varp -> new cloned varp @@ -252,7 +252,7 @@ class ParamProcessor final { // Generated modules by this visitor is not included V3StringSet m_allModuleNames; - typedef std::pair ValueMapValue; + using ValueMapValue = std::pair; std::map m_valueMap; // Hash of node hash to (param value, name) int m_nextValue = 1; // Next value to use in m_valueMap @@ -261,7 +261,7 @@ class ParamProcessor final { // Database to get protect-lib wrapper that matches parameters in hierarchical Verilation ParameterizedHierBlocks m_hierBlocks; // Default parameter values key:parameter name, value:default value (can be nullptr) - typedef std::map DefaultValueMap; + using DefaultValueMap = std::map; // Default parameter values of hierarchical blocks std::map m_defaultParameterValues; diff --git a/src/V3ParseSym.h b/src/V3ParseSym.h index 17ab5de56..e73ede79f 100644 --- a/src/V3ParseSym.h +++ b/src/V3ParseSym.h @@ -32,7 +32,7 @@ class V3ParseSym final { // TYPES - typedef std::vector SymStack; + using SymStack = std::vector; private: // MEMBERS diff --git a/src/V3Partition.cpp b/src/V3Partition.cpp index fe3e761f0..3d443f4ca 100644 --- a/src/V3Partition.cpp +++ b/src/V3Partition.cpp @@ -247,7 +247,7 @@ private: // MEMBERS V3Graph m_graph; // A graph V3GraphVertex* m_vx[50]; // All vertices within the graph - typedef std::unordered_map CpMap; + using CpMap = std::unordered_map; CpMap m_cp; // Vertex-to-CP map CpMap m_seen; // Set of vertices we've seen @@ -353,7 +353,7 @@ public: class LogicMTask final : public AbstractLogicMTask { public: // TYPES - typedef std::list VxList; + using VxList = std::list; struct CmpLogicMTask { bool operator()(const LogicMTask* ap, const LogicMTask* bp) const { @@ -442,7 +442,7 @@ private: // our edge with them. The SortByValueMap supports iterating over // relatives in longest-to-shortest CP order. We rely on this ordering // in more than one place. - typedef SortByValueMap EdgeSet; + using EdgeSet = SortByValueMap; std::array m_edges; public: @@ -1035,9 +1035,9 @@ private: // TODO: might get a little more speed by making this a // std::unordered_set and defining hash and equal_to functors for the // SiblingMC: - typedef std::set SibSet; - typedef std::unordered_set SibpSet; - typedef std::unordered_map MTask2Sibs; + using SibSet = std::set; + using SibpSet = std::unordered_set; + using MTask2Sibs = std::unordered_map; // New CP information for mtaskp reflecting an upcoming merge struct NewCp { @@ -1756,10 +1756,10 @@ private: class PartFixDataHazards final { private: // TYPES - typedef std::set LogicMTaskSet; - typedef std::map TasksByRank; - typedef std::set OvvSet; - typedef std::unordered_map Olv2MTaskMap; + using LogicMTaskSet = std::set; + using TasksByRank = std::map; + using OvvSet = std::set; + using Olv2MTaskMap = std::unordered_map; // MEMBERS V3Graph* m_mtasksp; // Mtask graph @@ -2031,11 +2031,11 @@ private: uint32_t m_sandbagNumerator; // Numerator padding for est runtime uint32_t m_sandbagDenom; // Denomerator padding for est runtime - typedef std::unordered_map MTaskStateMap; + using MTaskStateMap = std::unordered_map; MTaskStateMap m_mtaskState; // State for each mtask. MTaskCmp m_mtaskCmp; // Comparison functor - typedef std::set ReadyMTasks; + using ReadyMTasks = std::set; ReadyMTasks m_ready; // MTasks ready to be assigned next; all their // // dependencies are already assigned. @@ -2449,7 +2449,7 @@ void V3Partition::go(V3Graph* mtasksp) { // order though, otherwise we break CmpLogicMTask for still-existing // EdgeSet's that haven't destructed yet. { - typedef std::set SortedMTaskSet; + using SortedMTaskSet = std::set; SortedMTaskSet sorted; for (V3GraphVertex* itp = mtasksp->verticesBeginp(); itp; itp = itp->verticesNextp()) { LogicMTask* mtaskp = dynamic_cast(itp); diff --git a/src/V3Partition.h b/src/V3Partition.h index f8fc86b10..12f58f830 100644 --- a/src/V3Partition.h +++ b/src/V3Partition.h @@ -26,7 +26,7 @@ #include class LogicMTask; -typedef std::unordered_map Vx2MTaskMap; +using Vx2MTaskMap = std::unordered_map; //************************************************************************* /// V3Partition takes the fine-grained logic graph from V3Order and diff --git a/src/V3PartitionGraph.h b/src/V3PartitionGraph.h index d824950ce..8bc4baf3f 100644 --- a/src/V3PartitionGraph.h +++ b/src/V3PartitionGraph.h @@ -40,7 +40,7 @@ public: class AbstractLogicMTask VL_NOT_FINAL : public AbstractMTask { public: // TYPES - typedef std::list VxList; + using VxList = std::list; // CONSTRUCTORS AbstractLogicMTask(V3Graph* graphp) : AbstractMTask{graphp} {} diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index d2cb6814f..c71070add 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -108,8 +108,8 @@ public: class V3PreProcImp final : public V3PreProc { public: // TYPES - typedef std::map DefinesMap; - typedef VInFilter::StrList StrList; + using DefinesMap = std::map; + using StrList = VInFilter::StrList; // debug() -> see V3PreShellImp::debug; use --debugi-V3PreShell diff --git a/src/V3Randomize.cpp b/src/V3Randomize.cpp index 3fb49c16f..1289b5a0d 100644 --- a/src/V3Randomize.cpp +++ b/src/V3Randomize.cpp @@ -39,8 +39,8 @@ private: // AstClass::user1() -> bool. Set true to indicate needs randomize processing AstUser1InUse m_inuser1; - typedef std::unordered_set DerivedSet; - typedef std::unordered_map BaseToDerivedMap; + using DerivedSet = std::unordered_set; + using BaseToDerivedMap = std::unordered_map; BaseToDerivedMap m_baseToDerivedMap; // Mapping from base classes to classes that extend them diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp index c7188841f..5363f3c6a 100644 --- a/src/V3Scope.cpp +++ b/src/V3Scope.cpp @@ -46,7 +46,7 @@ private: // TYPES // These cannot be unordered unless make a specialized hashing pair (gcc-8) - typedef std::map, AstVarScope*> VarScopeMap; + using VarScopeMap = std::map, AstVarScope*>; // STATE, inside processing a single module AstNodeModule* m_modp = nullptr; // Current module diff --git a/src/V3Scoreboard.h b/src/V3Scoreboard.h index 3584bf4a8..926453bc3 100644 --- a/src/V3Scoreboard.h +++ b/src/V3Scoreboard.h @@ -44,8 +44,8 @@ template KeySet; - typedef std::map Val2Keys; + using KeySet = std::set; + using Val2Keys = std::map; // MEMBERS std::unordered_map m_keys; // Map each key to its value. Not sorted. @@ -58,11 +58,11 @@ public: class const_iterator VL_NOT_FINAL { // TYPES public: - typedef const_iterator value_type; - typedef const_iterator reference; // See comment on operator*() - typedef void pointer; - typedef std::ptrdiff_t difference_type; - typedef std::bidirectional_iterator_tag iterator_category; + using value_type = const_iterator; + using reference = const_iterator; // See comment on operator*() + using pointer = void; + using difference_type = std::ptrdiff_t; + using iterator_category = std::bidirectional_iterator_tag; protected: friend class SortByValueMap; @@ -195,8 +195,8 @@ public: class iterator final : public const_iterator { public: // TYPES - typedef iterator value_type; - typedef iterator reference; + using value_type = iterator; + using reference = iterator; // pointer, difference_type, and iterator_category inherit from // const_iterator @@ -222,8 +222,8 @@ public: } }; - typedef std::reverse_iterator reverse_iterator; - typedef std::reverse_iterator const_reverse_iterator; + using reverse_iterator = std::reverse_iterator; + using const_reverse_iterator = std::reverse_iterator; // METHODS private: @@ -359,8 +359,8 @@ private: return cmp.operator()(*ap, *bp); } }; - typedef SortByValueMap SortedMap; - typedef T_Score (*UserScoreFnp)(const T_Elem*); + using SortedMap = SortByValueMap; + using UserScoreFnp = T_Score (*)(const T_Elem*); // MEMBERS std::unordered_set m_unknown; // Elements with unknown scores diff --git a/src/V3SenTree.h b/src/V3SenTree.h index a04d68b2f..501157652 100644 --- a/src/V3SenTree.h +++ b/src/V3SenTree.h @@ -48,7 +48,7 @@ private: }; // MEMBERS - typedef std::unordered_set Set; + using Set = std::unordered_set; Set m_trees; // Set of sensitive blocks, for folding. public: diff --git a/src/V3Simulate.h b/src/V3Simulate.h index 0112b8673..3fa35da56 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -60,8 +60,8 @@ public: ~SimStackNode() = default; }; -typedef std::deque ConstDeque; -typedef std::unordered_map ConstPile; +using ConstDeque = std::deque; +using ConstPile = std::unordered_map; class SimulateVisitor VL_NOT_FINAL : public AstNVisitor { // Simulate a node tree, returning value of variables diff --git a/src/V3Split.cpp b/src/V3Split.cpp index af5b9921b..4c8b1a60d 100644 --- a/src/V3Split.cpp +++ b/src/V3Split.cpp @@ -615,8 +615,8 @@ private: VL_UNCOPYABLE(ReorderVisitor); }; -typedef std::unordered_set ColorSet; -typedef std::vector AlwaysVec; +using ColorSet = std::unordered_set; +using AlwaysVec = std::vector; class IfColorVisitor final : public AstNVisitor { // MEMBERS @@ -752,7 +752,7 @@ protected: virtual void visit(AstNodeIf* nodep) override { const ColorSet& colors = m_ifColorp->colors(nodep); - typedef std::unordered_map CloneMap; + using CloneMap = std::unordered_map; CloneMap clones; for (unsigned int color : colors) { diff --git a/src/V3SplitVar.cpp b/src/V3SplitVar.cpp index 262d15b08..435d77b46 100644 --- a/src/V3SplitVar.cpp +++ b/src/V3SplitVar.cpp @@ -285,9 +285,9 @@ public: class UnpackRefMap final { public: - typedef std::map, AstNodeComparator> MapType; - typedef MapType::iterator MapIt; - typedef MapType::value_type::second_type::iterator SetIt; + using MapType = std::map, AstNodeComparator>; + using MapIt = MapType::iterator; + using SetIt = MapType::value_type::second_type::iterator; private: MapType m_map; @@ -379,10 +379,10 @@ public: } }; -typedef std::map SplitVarRefsMap; +using SplitVarRefsMap = std::map; class SplitUnpackedVarVisitor final : public AstNVisitor, public SplitVarImpl { - typedef std::set VarSet; + using VarSet = std::set; VarSet m_foundTargetVar; UnpackRefMap m_refs; AstNodeModule* m_modp = nullptr; @@ -879,8 +879,8 @@ class PackedVarRef final { } public: - typedef std::vector::iterator iterator; - typedef std::vector::const_iterator const_iterator; + using iterator = std::vector::iterator; + using const_iterator = std::vector::const_iterator; std::vector& lhs() { UASSERT(m_dedupDone, "cannot read before dedup()"); return m_lhs; diff --git a/src/V3Stats.cpp b/src/V3Stats.cpp index f155bba1d..1f8687bc5 100644 --- a/src/V3Stats.cpp +++ b/src/V3Stats.cpp @@ -34,7 +34,7 @@ class StatsVisitor final : public AstNVisitor { private: // NODE STATE/TYPES - typedef std::map NameMap; // Number of times a name appears + using NameMap = std::map; // Number of times a name appears // STATE string m_stage; // Name of the stage we are scanning diff --git a/src/V3StatsReport.cpp b/src/V3StatsReport.cpp index 0c5d4b43f..a57aacab2 100644 --- a/src/V3StatsReport.cpp +++ b/src/V3StatsReport.cpp @@ -32,7 +32,7 @@ class StatsReport final { // TYPES - typedef std::vector StatColl; + using StatColl = std::vector; // STATE std::ofstream& os; ///< Output stream diff --git a/src/V3String.h b/src/V3String.h index b5e14cb3a..e151fd758 100644 --- a/src/V3String.h +++ b/src/V3String.h @@ -193,7 +193,7 @@ class VSpellCheck final { static constexpr unsigned NUM_CANDIDATE_LIMIT = 10000; // Avoid searching huge netlists static constexpr unsigned LENGTH_LIMIT = 100; // Maximum string length to search // TYPES - typedef unsigned int EditDistance; + using EditDistance = unsigned int; // MEMBERS std::vector m_candidates; // Strings we try to match public: diff --git a/src/V3SymTable.h b/src/V3SymTable.h index 304a2f882..12c1e1ba3 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -36,12 +36,12 @@ class VSymEnt; //###################################################################### // Symbol table -typedef std::unordered_set VSymConstMap; +using VSymConstMap = std::unordered_set; class VSymEnt final { // Symbol table that can have a "superior" table for resolving upper references // MEMBERS - typedef std::multimap IdNameMap; + using IdNameMap = std::multimap; IdNameMap m_idNameMap; // Hash of variables by name AstNode* m_nodep; // Node that entry belongs to VSymEnt* m_fallbackp; // Table "above" this one in name scope, for fallback resolution @@ -60,7 +60,7 @@ class VSymEnt final { static constexpr int debug() { return 0; } // NOT runtime, too hot of a function #endif public: - typedef IdNameMap::const_iterator const_iterator; + using const_iterator = IdNameMap::const_iterator; const_iterator begin() const { return m_idNameMap.begin(); } const_iterator end() const { return m_idNameMap.end(); } @@ -280,7 +280,7 @@ public: class VSymGraph final { // Collection of symbol tables // TYPES - typedef std::vector SymStack; + using SymStack = std::vector; // MEMBERS VSymEnt* m_symRootp; // Root symbol table diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index ea33d5236..afd103a27 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -71,7 +71,7 @@ private: template class TspGraphTmpl : public V3Graph { public: // TYPES - typedef TspVertexTmpl Vertex; + using Vertex = TspVertexTmpl; // MEMBERS std::unordered_map m_vertices; // T_Key to Vertex lookup map @@ -151,7 +151,7 @@ public: std::unordered_set visited_set; EdgeCmp cmp; - typedef std::set PendingEdgeSet; + using PendingEdgeSet = std::set; // This is the set of pending edges from visited to unvisited // nodes. PendingEdgeSet pendingEdges(cmp); @@ -221,7 +221,7 @@ public: std::list odds = keysToVertexList(oddKeys); std::unordered_set unmatchedOdds; - typedef typename std::list::iterator VertexListIt; + using VertexListIt = typename std::list::iterator; for (VertexListIt it = odds.begin(); it != odds.end(); ++it) { outp->addVertex((*it)->key()); unmatchedOdds.insert(*it); @@ -246,7 +246,7 @@ public: // bidir edge will collide in the pendingEdges set here, but this // is OK, we'll ignore the direction on the edge anyway. EdgeCmp cmp; - typedef std::set PendingEdgeSet; + using PendingEdgeSet = std::set; PendingEdgeSet pendingEdges(cmp); for (VertexListIt it = odds.begin(); it != odds.end(); ++it) { @@ -408,7 +408,7 @@ void V3TSP::tspSort(const V3TSP::StateVec& states, V3TSP::StateVec* resultp) { } // Build the initial graph from the starting state set. - typedef TspGraphTmpl Graph; + using Graph = TspGraphTmpl; Graph graph; for (const auto& state : states) graph.addVertex(state); for (V3TSP::StateVec::const_iterator it = states.begin(); it != states.end(); ++it) { @@ -613,7 +613,7 @@ void V3TSP::selfTestStates() { } void V3TSP::selfTestString() { - typedef TspGraphTmpl Graph; + using Graph = TspGraphTmpl; Graph graph; graph.addVertex("0"); graph.addVertex("1"); diff --git a/src/V3TSP.h b/src/V3TSP.h index cb81103f7..956fb97d2 100644 --- a/src/V3TSP.h +++ b/src/V3TSP.h @@ -43,7 +43,7 @@ public: virtual ~TspStateBase() = default; }; -typedef std::vector StateVec; +using StateVec = std::vector; // Given an unsorted set of TspState's, sort them to minimize // the transition cost for walking the sorted list. diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 02f1136b7..7c8e6c76c 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -103,8 +103,8 @@ private: AstUser4InUse m_inuser4; // TYPES - typedef std::map, AstVarScope*> VarToScopeMap; - typedef std::unordered_map FuncToClassMap; + using VarToScopeMap = std::map, AstVarScope*>; + using FuncToClassMap = std::unordered_map; // MEMBERS VarToScopeMap m_varToScopeMap; // Map for Var -> VarScope mappings FuncToClassMap m_funcToClassMap; // Map for ctor func -> class @@ -385,7 +385,7 @@ private: IM_AFTER, // Pointing at last inserted stmt, insert after IM_WHILE_PRECOND // Pointing to for loop, add to body end }; - typedef std::map> DpiNames; + using DpiNames = std::map>; // STATE TaskStateVisitor* m_statep; // Common state between visitors diff --git a/src/V3Task.h b/src/V3Task.h index 03de4ea32..162801f16 100644 --- a/src/V3Task.h +++ b/src/V3Task.h @@ -27,8 +27,8 @@ //============================================================================ -typedef std::pair V3TaskConnect; // [port, pin-connects-to] -typedef std::vector V3TaskConnects; // [ [port, pin-connects-to] ... ] +using V3TaskConnect = std::pair; // [port, pin-connects-to] +using V3TaskConnects = std::vector; // [ [port, pin-connects-to] ... ] //============================================================================ diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp index bcbd89506..49ee14933 100644 --- a/src/V3Trace.cpp +++ b/src/V3Trace.cpp @@ -184,9 +184,9 @@ private: VDouble0 m_statUniqCodes; // Statistic tracking // All activity numbers applying to a given trace - typedef std::set ActCodeSet; + using ActCodeSet = std::set; // For activity set, what traces apply - typedef std::multimap TraceVec; + using TraceVec = std::multimap; // METHODS VL_DEBUG_FUNC; // Declare debug() diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp index b834c47ff..a4b7515d7 100644 --- a/src/V3Tristate.cpp +++ b/src/V3Tristate.cpp @@ -117,7 +117,7 @@ class TristateGraph final { // TYPES public: - typedef std::vector VarVec; + using VarVec = std::vector; private: // MEMBERS @@ -328,8 +328,8 @@ class TristateVisitor final : public TristateBaseVisitor { AstUser5InUse m_inuser5; // TYPES - typedef std::vector RefVec; - typedef std::unordered_map VarMap; + using RefVec = std::vector; + using VarMap = std::unordered_map; enum : uint8_t { U2_GRAPHING = 1, // bit[0] if did m_graphing visit U2_NONGRAPH = 2, // bit[1] if did !m_graphing visit diff --git a/src/V3Waiver.h b/src/V3Waiver.h index 8be22fbec..cff1df336 100644 --- a/src/V3Waiver.h +++ b/src/V3Waiver.h @@ -24,7 +24,7 @@ class V3Waiver final { // TYPES - typedef std::vector WaiverList; + using WaiverList = std::vector; static WaiverList s_waiverList; public: diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 21cc16c4c..babc99a49 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -198,8 +198,8 @@ public: class WidthVisitor final : public AstNVisitor { private: // TYPES - typedef std::map, AstVar*> TableMap; - typedef std::map PatVecMap; + using TableMap = std::map, AstVar*>; + using PatVecMap = std::map; // STATE WidthVP* m_vup = nullptr; // Current node state diff --git a/src/VlcOptions.h b/src/VlcOptions.h index 29b88f1e1..fc76f4b76 100644 --- a/src/VlcOptions.h +++ b/src/VlcOptions.h @@ -29,7 +29,7 @@ //###################################################################### // V3Options - Command line options -typedef std::set VlStringSet; +using VlStringSet = std::set; class VlcOptions final { // MEMBERS (general options) diff --git a/src/VlcPoint.h b/src/VlcPoint.h index f05dfecb2..8be685d2c 100644 --- a/src/VlcPoint.h +++ b/src/VlcPoint.h @@ -93,15 +93,15 @@ public: class VlcPoints final { private: // MEMBERS - typedef std::map NameMap; // Sorted by name (ordered) + using NameMap = std::map; // Sorted by name (ordered) NameMap m_nameMap; //< Name to point-number std::vector m_points; //< List of all points vluint64_t m_numPoints = 0; //< Total unique points public: // ITERATORS - typedef NameMap ByName; - typedef ByName::iterator iterator; + using ByName = NameMap; + using iterator = ByName::iterator; ByName::iterator begin() { return m_nameMap.begin(); } ByName::iterator end() { return m_nameMap.end(); } diff --git a/src/VlcSource.h b/src/VlcSource.h index 7cb274f35..f4ac07a6c 100644 --- a/src/VlcSource.h +++ b/src/VlcSource.h @@ -60,8 +60,8 @@ public: class VlcSource final { public: // TYPES - typedef std::map ColumnMap; // Map of {column} - typedef std::map LinenoMap; // Map of {lineno}{column} + using ColumnMap = std::map; // Map of {column} + using LinenoMap = std::map; // Map of {lineno}{column} private: // MEMBERS @@ -101,7 +101,7 @@ public: class VlcSources final { public: // TYPES - typedef std::map NameMap; + using NameMap = std::map; private: // MEMBERS @@ -109,7 +109,7 @@ private: public: // ITERATORS - typedef NameMap::iterator iterator; + using iterator = NameMap::iterator; NameMap::iterator begin() { return m_sources.begin(); } NameMap::iterator end() { return m_sources.end(); } diff --git a/src/VlcTest.h b/src/VlcTest.h index e2aa8adc0..7aa4cb77a 100644 --- a/src/VlcTest.h +++ b/src/VlcTest.h @@ -87,7 +87,7 @@ public: class VlcTests final { public: // TYPES - typedef std::vector ByName; + using ByName = std::vector; private: // MEMBERS @@ -95,7 +95,7 @@ private: public: // ITERATORS - typedef ByName::iterator iterator; + using iterator = ByName::iterator; ByName::iterator begin() { return m_tests.begin(); } ByName::iterator end() { return m_tests.end(); } diff --git a/src/config_build.h.in b/src/config_build.h.in index a43093249..528066ae1 100644 --- a/src/config_build.h.in +++ b/src/config_build.h.in @@ -67,7 +67,7 @@ #include // Avoid needing std:: prefixes on some very common items -typedef std::string string; +using string = std::string; using std::cout; using std::endl; using std::make_pair; From 689d5b509071d2e3d4ce0564b7d7bb81fc1b77a5 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 12 Mar 2021 18:17:49 -0500 Subject: [PATCH 005/110] Internals: Add std:: to make_pair. No functional change. --- include/verilated_cov.cpp | 2 +- src/V3AstNodes.cpp | 2 +- src/V3Class.cpp | 6 +++--- src/V3Config.cpp | 2 +- src/V3Delayed.cpp | 4 ++-- src/V3EmitCSyms.cpp | 28 ++++++++++++++-------------- src/V3LinkDot.cpp | 7 ++++--- src/V3LinkParse.cpp | 4 ++-- src/V3Order.cpp | 2 +- src/V3Param.cpp | 4 ++-- src/V3Scope.cpp | 4 ++-- src/V3Task.cpp | 10 +++++----- src/V3Width.cpp | 8 ++++---- src/VlcSource.h | 6 +++--- src/config_build.h.in | 1 - 15 files changed, 45 insertions(+), 45 deletions(-) diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index a4311e4fb..e94291dc6 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -395,7 +395,7 @@ public: cit->second.second += itemp->count(); cit->second.first = combineHier(oldhier, hier); } else { - eventCounts.emplace(name, make_pair(hier, itemp->count())); + eventCounts.emplace(name, std::make_pair(hier, itemp->count())); } } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index db091b09b..0575b1826 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -784,7 +784,7 @@ std::pair AstNodeDType::dimensions(bool includeBasic) { } break; } - return make_pair(packed, unpacked); + return std::make_pair(packed, unpacked); } int AstNodeDType::widthPow2() const { diff --git a/src/V3Class.cpp b/src/V3Class.cpp index 7c3b65bc7..a47b052d1 100644 --- a/src/V3Class.cpp +++ b/src/V3Class.cpp @@ -100,7 +100,7 @@ private: // Don't move now, or wouldn't keep interating the class // TODO move class statics too if (m_packageScopep && m_ftaskp && m_ftaskp->lifetime().isStatic()) { - m_moves.push_back(make_pair(nodep, m_packageScopep)); + m_moves.push_back(std::make_pair(nodep, m_packageScopep)); } } @@ -115,7 +115,7 @@ private: m_ftaskp = nodep; iterateChildren(nodep); if (m_packageScopep && nodep->lifetime().isStatic()) { - m_moves.push_back(make_pair(nodep, m_packageScopep)); + m_moves.push_back(std::make_pair(nodep, m_packageScopep)); } } } @@ -125,7 +125,7 @@ private: // Don't move now, or wouldn't keep interating the class // TODO move function statics only // if (m_classScopep) { - // m_moves.push_back(make_pair(nodep, m_classScopep)); + // m_moves.push_back(std::make_pair(nodep, m_classScopep)); //} } diff --git a/src/V3Config.cpp b/src/V3Config.cpp index c8b9f936d..eb02a0a72 100644 --- a/src/V3Config.cpp +++ b/src/V3Config.cpp @@ -292,7 +292,7 @@ public: m_lastIgnore.it = m_ignLines.begin(); } void addWaiver(V3ErrorCode code, const string& match) { - m_waivers.push_back(make_pair(code, match)); + m_waivers.push_back(std::make_pair(code, match)); } void applyBlock(AstNodeBlock* nodep) { diff --git a/src/V3Delayed.cpp b/src/V3Delayed.cpp index db00cd2aa..eaf5fb60d 100644 --- a/src/V3Delayed.cpp +++ b/src/V3Delayed.cpp @@ -133,7 +133,7 @@ private: AstVar* varp; AstNodeModule* addmodp = oldvarscp->scopep()->modp(); // We need a new AstVar, but only one for all scopes, to match the new AstVarScope - const auto it = m_modVarMap.find(make_pair(addmodp, name)); + const auto it = m_modVarMap.find(std::make_pair(addmodp, name)); if (it != m_modVarMap.end()) { // Created module's AstVar earlier under some other scope varp = it->second; @@ -149,7 +149,7 @@ private: VFlagBitPacked(), width); } addmodp->addStmtp(varp); - m_modVarMap.emplace(make_pair(addmodp, name), varp); + m_modVarMap.emplace(std::make_pair(addmodp, name), varp); } AstVarScope* varscp = new AstVarScope(oldvarscp->fileline(), oldvarscp->scopep(), varp); diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index cbdff09a8..fa7df71fc 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -217,12 +217,12 @@ class EmitCSyms final : EmitCBaseVisitor { // UINFO(9," scnameins sp "<name(), - ScopeVarData(scpSym, varBasePretty, varp, modp, scopep))); + std::make_pair(scpSym + " " + varp->name(), + ScopeVarData(scpSym, varBasePretty, varp, modp, scopep))); } } } @@ -288,21 +288,21 @@ class EmitCSyms final : EmitCBaseVisitor { string name_dedot = AstNode::dedotName(name); int timeunit = m_modp->timeunit().powerOfTen(); m_vpiScopeCandidates.insert( - make_pair(name, ScopeData(scopeSymString(name), name_dedot, timeunit, type))); + std::make_pair(name, ScopeData(scopeSymString(name), name_dedot, timeunit, type))); } } virtual void visit(AstScope* nodep) override { if (VN_IS(m_modp, Class)) return; // The ClassPackage is what is visible nameCheck(nodep); - m_scopes.emplace_back(make_pair(nodep, m_modp)); + m_scopes.emplace_back(std::make_pair(nodep, m_modp)); if (v3Global.opt.vpi() && !nodep->isTop()) { string name_dedot = AstNode::dedotName(nodep->shortName()); int timeunit = m_modp->timeunit().powerOfTen(); m_vpiScopeCandidates.insert( - make_pair(nodep->name(), ScopeData(scopeSymString(nodep->name()), name_dedot, - timeunit, "SCOPE_MODULE"))); + std::make_pair(nodep->name(), ScopeData(scopeSymString(nodep->name()), name_dedot, + timeunit, "SCOPE_MODULE"))); } } virtual void visit(AstScopeName* nodep) override { @@ -316,21 +316,21 @@ class EmitCSyms final : EmitCBaseVisitor { } if (nodep->dpiExport()) { UASSERT_OBJ(m_cfuncp, nodep, "ScopeName not under DPI function"); - m_scopeFuncs.insert( - make_pair(name + " " + m_cfuncp->name(), ScopeFuncData(nodep, m_cfuncp, m_modp))); + m_scopeFuncs.insert(std::make_pair(name + " " + m_cfuncp->name(), + ScopeFuncData(nodep, m_cfuncp, m_modp))); } else { if (m_scopeNames.find(nodep->scopeDpiName()) == m_scopeNames.end()) { m_scopeNames.insert( - make_pair(nodep->scopeDpiName(), - ScopeData(nodep->scopeDpiName(), nodep->scopePrettyDpiName(), - timeunit, "SCOPE_OTHER"))); + std::make_pair(nodep->scopeDpiName(), + ScopeData(nodep->scopeDpiName(), nodep->scopePrettyDpiName(), + timeunit, "SCOPE_OTHER"))); } } } virtual void visit(AstVar* nodep) override { nameCheck(nodep); iterateChildren(nodep); - if (nodep->isSigUserRdPublic()) m_modVars.emplace_back(make_pair(m_modp, nodep)); + if (nodep->isSigUserRdPublic()) m_modVars.emplace_back(std::make_pair(m_modp, nodep)); } virtual void visit(AstCoverDecl* nodep) override { // Assign numbers to all bins, so we know how big of an array to use diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 0126b6e44..a9a3210b8 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -407,18 +407,19 @@ public: void implicitOkAdd(AstNodeModule* nodep, const string& varname) { // Mark the given variable name as being allowed to be implicitly declared if (nodep) { - const auto it = m_implicitNameSet.find(make_pair(nodep, varname)); + const auto it = m_implicitNameSet.find(std::make_pair(nodep, varname)); if (it == m_implicitNameSet.end()) m_implicitNameSet.emplace(nodep, varname); } } bool implicitOk(AstNodeModule* nodep, const string& varname) { return nodep - && (m_implicitNameSet.find(make_pair(nodep, varname)) != m_implicitNameSet.end()); + && (m_implicitNameSet.find(std::make_pair(nodep, varname)) + != m_implicitNameSet.end()); } // Track and later recurse interface modules void insertIfaceModSym(AstIface* nodep, VSymEnt* symp) { - m_ifaceModSyms.push_back(make_pair(nodep, symp)); + m_ifaceModSyms.push_back(std::make_pair(nodep, symp)); } void computeIfaceModSyms(); diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 6f95b8eda..73af3f7ca 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -363,7 +363,7 @@ private: // a new type won't change every verilated module. AstTypedef* defp = nullptr; ImplTypedefMap::iterator it - = m_implTypedef.find(make_pair(nodep->containerp(), nodep->name())); + = m_implTypedef.find(std::make_pair(nodep->containerp(), nodep->name())); if (it != m_implTypedef.end()) { defp = it->second; } else { @@ -387,7 +387,7 @@ private: defp = new AstTypedef(nodep->fileline(), nodep->name(), nullptr, VFlagChildDType(), dtypep); m_implTypedef.insert( - make_pair(make_pair(nodep->containerp(), defp->name()), defp)); + std::make_pair(std::make_pair(nodep->containerp(), defp->name()), defp)); backp->addNextHere(defp); } } diff --git a/src/V3Order.cpp b/src/V3Order.cpp index b68138ade..b354a157d 100644 --- a/src/V3Order.cpp +++ b/src/V3Order.cpp @@ -158,7 +158,7 @@ public: } V3List& readyVertices() { return m_readyVertices; } static OrderMoveDomScope* findCreate(const AstSenTree* domainp, const AstScope* scopep) { - const DomScopeKey key = make_pair(domainp, scopep); + const DomScopeKey key = std::make_pair(domainp, scopep); const auto iter = s_dsMap.find(key); if (iter != s_dsMap.end()) { return iter->second; diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 113ace5c6..0ff23444c 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -323,7 +323,7 @@ class ParamProcessor final { num = it->second.first; } else { num = m_nextValue++; - m_valueMap[hash] = make_pair(num, key); + m_valueMap[hash] = std::make_pair(num, key); } return string("z") + cvtToStr(num); } @@ -712,7 +712,7 @@ class ParamProcessor final { longnamer += ("_" + paramSmallName(srcModp, pinp->modVarp()) + paramValueNumber(pinIrefp)); any_overridesr = true; - ifaceRefRefs.push_back(make_pair(portIrefp, pinIrefp)); + ifaceRefRefs.push_back(std::make_pair(portIrefp, pinIrefp)); if (portIrefp->ifacep() != pinIrefp->ifacep() // Might be different only due to param cloning, so check names too && portIrefp->ifaceName() != pinIrefp->ifaceName()) { diff --git a/src/V3Scope.cpp b/src/V3Scope.cpp index 5363f3c6a..4bde493f2 100644 --- a/src/V3Scope.cpp +++ b/src/V3Scope.cpp @@ -72,7 +72,7 @@ private: UASSERT_OBJ(it2 != m_packageScopes.end(), nodep, "Can't locate package scope"); scopep = it2->second; } - const auto it3 = m_varScopes.find(make_pair(nodep->varp(), scopep)); + const auto it3 = m_varScopes.find(std::make_pair(nodep->varp(), scopep)); UASSERT_OBJ(it3 != m_varScopes.end(), nodep, "Can't locate varref scope"); AstVarScope* varscp = it3->second; nodep->varScopep(varscp); @@ -271,7 +271,7 @@ private: nodep->attrClocker(VVarAttrClocker::CLOCKER_NO); } UASSERT_OBJ(m_scopep, nodep, "No scope for var"); - m_varScopes.emplace(make_pair(nodep, m_scopep), varscp); + m_varScopes.emplace(std::make_pair(nodep, m_scopep), varscp); m_scopep->addVarp(varscp); } } diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 7c8e6c76c..192e93b40 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -123,7 +123,7 @@ public: return scopep; } AstVarScope* findVarScope(AstScope* scopep, AstVar* nodep) { - const auto iter = m_varToScopeMap.find(make_pair(scopep, nodep)); + const auto iter = m_varToScopeMap.find(std::make_pair(scopep, nodep)); UASSERT_OBJ(iter != m_varToScopeMap.end(), nodep, "No scope for var"); return iter->second; } @@ -911,7 +911,7 @@ private: // as it's legal for the user to attach multiple tasks to one dpi cname const auto iter = m_dpiNames.find(nodep->cname()); if (iter == m_dpiNames.end()) { - m_dpiNames.emplace(nodep->cname(), make_pair(nodep, dpiproto)); + m_dpiNames.emplace(nodep->cname(), std::make_pair(nodep, dpiproto)); return false; } else if (iter->second.second != dpiproto) { nodep->v3error( @@ -1479,9 +1479,9 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp) for (AstNode* stmtp = taskStmtsp; stmtp; stmtp = stmtp->nextp()) { if (AstVar* portp = VN_CAST(stmtp, Var)) { if (portp->isIO()) { - tconnects.push_back(make_pair(portp, static_cast(nullptr))); + tconnects.push_back(std::make_pair(portp, static_cast(nullptr))); nameToIndex.insert( - make_pair(portp->name(), tpinnum)); // For name based connections + std::make_pair(portp->name(), tpinnum)); // For name based connections tpinnum++; if (portp->attrSFormat()) { sformatp = portp; @@ -1521,7 +1521,7 @@ V3TaskConnects V3Task::taskConnects(AstNodeFTaskRef* nodep, AstNode* taskStmtsp) } else { // By pin number if (ppinnum >= tpinnum) { if (sformatp) { - tconnects.push_back(make_pair(sformatp, static_cast(nullptr))); + tconnects.push_back(std::make_pair(sformatp, static_cast(nullptr))); tconnects[ppinnum].second = argp; tpinnum++; } else { diff --git a/src/V3Width.cpp b/src/V3Width.cpp index babc99a49..d0226f4e5 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -5814,7 +5814,7 @@ private: } AstVar* dimensionVarp(AstNodeDType* nodep, AstAttrType attrType, uint32_t msbdim) { // Return a variable table which has specified dimension properties for this variable - const auto pos = m_tableMap.find(make_pair(nodep, attrType)); + const auto pos = m_tableMap.find(std::make_pair(nodep, attrType)); if (pos != m_tableMap.end()) return pos->second; AstNodeArrayDType* vardtypep = new AstUnpackArrayDType(nodep->fileline(), nodep->findSigned32DType(), @@ -5836,7 +5836,7 @@ private: initp->addValuep(dimensionValue(nodep->fileline(), nodep, attrType, i)); } userIterate(varp, nullptr); // May have already done $unit so must do this var - m_tableMap.emplace(make_pair(nodep, attrType), varp); + m_tableMap.emplace(std::make_pair(nodep, attrType), varp); return varp; } uint64_t enumMaxValue(const AstNode* errNodep, const AstEnumDType* adtypep) { @@ -5861,7 +5861,7 @@ private: } AstVar* enumVarp(AstEnumDType* nodep, AstAttrType attrType, uint32_t msbdim) { // Return a variable table which has specified dimension properties for this variable - const auto pos = m_tableMap.find(make_pair(nodep, attrType)); + const auto pos = m_tableMap.find(std::make_pair(nodep, attrType)); if (pos != m_tableMap.end()) return pos->second; UINFO(9, "Construct Venumtab attr=" << attrType.ascii() << " max=" << msbdim << " for " << nodep << endl); @@ -5936,7 +5936,7 @@ private: if (values[i]) initp->addIndexValuep(i, values[i]); } userIterate(varp, nullptr); // May have already done $unit so must do this var - m_tableMap.emplace(make_pair(nodep, attrType), varp); + m_tableMap.emplace(std::make_pair(nodep, attrType), varp); return varp; } diff --git a/src/VlcSource.h b/src/VlcSource.h index f4ac07a6c..c8de073a1 100644 --- a/src/VlcSource.h +++ b/src/VlcSource.h @@ -84,11 +84,11 @@ public: // METHODS void incCount(int lineno, int column, vluint64_t count, bool ok) { LinenoMap::iterator lit = m_lines.find(lineno); - if (lit == m_lines.end()) lit = m_lines.insert(make_pair(lineno, ColumnMap())).first; + if (lit == m_lines.end()) lit = m_lines.insert(std::make_pair(lineno, ColumnMap())).first; ColumnMap& cmap = lit->second; ColumnMap::iterator cit = cmap.find(column); if (cit == cmap.end()) { - cit = cmap.insert(make_pair(column, VlcSourceCount(lineno, column))).first; + cit = cmap.insert(std::make_pair(column, VlcSourceCount(lineno, column))).first; } VlcSourceCount& sc = cit->second; sc.incCount(count, ok); @@ -123,7 +123,7 @@ public: if (iter != m_sources.end()) { return iter->second; } else { - iter = m_sources.insert(make_pair(name, VlcSource(name))).first; + iter = m_sources.insert(std::make_pair(name, VlcSource(name))).first; return iter->second; } } diff --git a/src/config_build.h.in b/src/config_build.h.in index 528066ae1..62ca75a08 100644 --- a/src/config_build.h.in +++ b/src/config_build.h.in @@ -70,7 +70,6 @@ using string = std::string; using std::cout; using std::endl; -using std::make_pair; //********************************************************************** //**** Configure-discovered library options From abcb9cc91bb28646b2161f6af6a5a738ec9b55c4 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 12 Mar 2021 19:18:23 -0500 Subject: [PATCH 006/110] Add VlWide to WDataInP. Part of coming commit. --- include/verilated_heavy.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index 6b0f52039..a3cb94441 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -111,6 +111,7 @@ public: const EData& operator[](size_t index) const { return m_storage[index]; }; EData& operator[](size_t index) { return m_storage[index]; }; operator WDataOutP() { return &m_storage[0]; } + operator WDataInP() const { return &m_storage[0]; } // METHODS const EData& at(size_t index) const { return m_storage[index]; } @@ -808,7 +809,7 @@ public: private: // MEMBERS - Array m_array; // State of the assoc array + Array m_array; // Contents of the packed array public: // CONSTRUCTORS From d1becbb793a2f9b2763f5d27296fc3fe5805063b Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 12 Mar 2021 23:05:56 -0500 Subject: [PATCH 007/110] Tests: Fix gmon file not always flushing --- test_regress/t/t_case_huge_prof.pl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/test_regress/t/t_case_huge_prof.pl b/test_regress/t/t_case_huge_prof.pl index 9e75c590c..8b7b293ed 100755 --- a/test_regress/t/t_case_huge_prof.pl +++ b/test_regress/t/t_case_huge_prof.pl @@ -34,6 +34,8 @@ sub dotest { check_finished => 1, ); + sleep 4; # Disk flush wait + my $gmon_path; $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); $gmon_path or error("Profiler did not create a gmon.out"); From b201b6257baa92fc16a85239c9098d592b50f5cb Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Mar 2021 10:22:32 -0500 Subject: [PATCH 008/110] Tests: Improve coverage when not expanding --- test_regress/t/t_case_66bits_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_case_write1_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_func_twocall_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_math_cond_huge_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_math_div_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_math_eq_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_math_red_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_math_shift_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_math_signed_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_math_vliw_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_mem_packed_noexpand.pl | 24 +++++++++++++++++++ test_regress/t/t_var_assign_landr_noexpand.pl | 24 +++++++++++++++++++ 12 files changed, 288 insertions(+) create mode 100755 test_regress/t/t_case_66bits_noexpand.pl create mode 100755 test_regress/t/t_case_write1_noexpand.pl create mode 100755 test_regress/t/t_func_twocall_noexpand.pl create mode 100755 test_regress/t/t_math_cond_huge_noexpand.pl create mode 100755 test_regress/t/t_math_div_noexpand.pl create mode 100755 test_regress/t/t_math_eq_noexpand.pl create mode 100755 test_regress/t/t_math_red_noexpand.pl create mode 100755 test_regress/t/t_math_shift_noexpand.pl create mode 100755 test_regress/t/t_math_signed_noexpand.pl create mode 100755 test_regress/t/t_math_vliw_noexpand.pl create mode 100755 test_regress/t/t_mem_packed_noexpand.pl create mode 100755 test_regress/t/t_var_assign_landr_noexpand.pl diff --git a/test_regress/t/t_case_66bits_noexpand.pl b/test_regress/t/t_case_66bits_noexpand.pl new file mode 100755 index 000000000..fae2f640f --- /dev/null +++ b/test_regress/t/t_case_66bits_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_case_66bits.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_case_write1_noexpand.pl b/test_regress/t/t_case_write1_noexpand.pl new file mode 100755 index 000000000..cadb667e6 --- /dev/null +++ b/test_regress/t/t_case_write1_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_case_write1.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_func_twocall_noexpand.pl b/test_regress/t/t_func_twocall_noexpand.pl new file mode 100755 index 000000000..001824bc6 --- /dev/null +++ b/test_regress/t/t_func_twocall_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_func_twocall.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_cond_huge_noexpand.pl b/test_regress/t/t_math_cond_huge_noexpand.pl new file mode 100755 index 000000000..0ae4e3ce4 --- /dev/null +++ b/test_regress/t/t_math_cond_huge_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_math_cond_huge.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_div_noexpand.pl b/test_regress/t/t_math_div_noexpand.pl new file mode 100755 index 000000000..4dbcba15c --- /dev/null +++ b/test_regress/t/t_math_div_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_math_div.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_eq_noexpand.pl b/test_regress/t/t_math_eq_noexpand.pl new file mode 100755 index 000000000..f8b2375c0 --- /dev/null +++ b/test_regress/t/t_math_eq_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_math_eq.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_red_noexpand.pl b/test_regress/t/t_math_red_noexpand.pl new file mode 100755 index 000000000..89e54c0c9 --- /dev/null +++ b/test_regress/t/t_math_red_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_math_red.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_shift_noexpand.pl b/test_regress/t/t_math_shift_noexpand.pl new file mode 100755 index 000000000..e8a59556b --- /dev/null +++ b/test_regress/t/t_math_shift_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_math_shift.v"); + +compile( + verilator_flags2 => ["-Wno-CLKDATA", '-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_signed_noexpand.pl b/test_regress/t/t_math_signed_noexpand.pl new file mode 100755 index 000000000..336d35594 --- /dev/null +++ b/test_regress/t/t_math_signed_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_math_signed.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_math_vliw_noexpand.pl b/test_regress/t/t_math_vliw_noexpand.pl new file mode 100755 index 000000000..fce202e04 --- /dev/null +++ b/test_regress/t/t_math_vliw_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_math_vliw.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_mem_packed_noexpand.pl b/test_regress/t/t_mem_packed_noexpand.pl new file mode 100755 index 000000000..d5fc2b5da --- /dev/null +++ b/test_regress/t/t_mem_packed_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_mem_packed.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_var_assign_landr_noexpand.pl b/test_regress/t/t_var_assign_landr_noexpand.pl new file mode 100755 index 000000000..cd058334d --- /dev/null +++ b/test_regress/t/t_var_assign_landr_noexpand.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_var_assign_landr.v"); + +compile( + verilator_flags2 => ['-Ox'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; From 67853e2f29c60e9691bfa93c50710e72242003aa Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Mar 2021 12:25:06 -0500 Subject: [PATCH 009/110] Tests: Add t_prof test. --- .../t/{t_case_huge_prof.pl => t_prof.pl} | 8 +- test_regress/t/t_prof.v | 73 +++++++++++++++++++ 2 files changed, 75 insertions(+), 6 deletions(-) rename test_regress/t/{t_case_huge_prof.pl => t_prof.pl} (86%) create mode 100644 test_regress/t/t_prof.v diff --git a/test_regress/t/t_case_huge_prof.pl b/test_regress/t/t_prof.pl similarity index 86% rename from test_regress/t/t_case_huge_prof.pl rename to test_regress/t/t_prof.pl index 8b7b293ed..d817c90af 100755 --- a/test_regress/t/t_case_huge_prof.pl +++ b/test_regress/t/t_prof.pl @@ -9,7 +9,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 scenarios(vlt_all => 1); -top_filename("t/t_case_huge.v"); if ($ENV{VERILATOR_TEST_NO_GPROF}) { skip("Skipping due to VERILATOR_TEST_NO_GPROF"); @@ -24,9 +23,6 @@ sub dotest { verilator_flags2 => ["--stats --prof-cfuncs -CFLAGS '-pg' -LDFLAGS '-pg'"], ); - file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10); - file_grep($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 10); - unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); setenv('GMON_OUT_PREFIX', "$Self->{obj_dir}/gmon.out"); @@ -34,8 +30,6 @@ sub dotest { check_finished => 1, ); - sleep 4; # Disk flush wait - my $gmon_path; $gmon_path = $_ foreach (glob "$Self->{obj_dir}/gmon.out.*"); $gmon_path or error("Profiler did not create a gmon.out"); @@ -48,6 +42,8 @@ sub dotest { check_finished => 0); file_grep("$Self->{obj_dir}/cfuncs.out", qr/Overall summary by/); + file_grep("$Self->{obj_dir}/cfuncs.out", qr/VLib + VL_POWSS_QQQ/); + file_grep("$Self->{obj_dir}/cfuncs.out", qr/VBlock + t_prof:/); } 1; diff --git a/test_regress/t/t_prof.v b/test_regress/t/t_prof.v new file mode 100644 index 000000000..ae605781c --- /dev/null +++ b/test_regress/t/t_prof.v @@ -0,0 +1,73 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + wire [63:0] result; + + Test test(/*AUTOINST*/ + // Outputs + .result (result[63:0]), + // Inputs + .clk (clk), + .cyc (cyc)); + + + reg [63:0] sum; + + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d result=%x\n",$time, cyc, result); +`endif + cyc <= cyc + 1; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc == 0) begin + // Setup + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d sum=%x\n",$time, cyc, sum); + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hfefad16f06ba6b1f + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test(/*AUTOARG*/ + // Outputs + result, + // Inputs + clk, cyc + ); + + input clk; + input int cyc; + output reg [63:0] result; + + logic [63:0] adder; + + always @(posedge clk) begin + adder = 0; + for (int i = 0; i < 1000; ++i) + adder += {32'h0, (cyc+i)} ** 3; + + result <= adder; + end +endmodule From 1b4a82acdeefbae5cd1262bf06fd735fc0059726 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Mar 2021 12:32:35 -0500 Subject: [PATCH 010/110] Verilated signals now use VlUnpacked in place of C arrays. (#2774) partial. --- Changes | 2 ++ src/V3AstNodes.cpp | 19 +++++-------------- src/V3EmitC.cpp | 42 ++++++++++++++++++------------------------ 3 files changed, 25 insertions(+), 38 deletions(-) diff --git a/Changes b/Changes index bc1d5c5df..b4f984768 100644 --- a/Changes +++ b/Changes @@ -4,6 +4,8 @@ The contributors that suggested a given feature are shown in []. Thanks! * Verilator 4.201 devel +**** Verilated signals now use VlWide and VlPacked in place of C arrays. + * Verilator 4.200 2021-03-12 diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 0575b1826..53341c960 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -635,6 +635,7 @@ string AstNodeDType::cType(const string& name, bool forFunc, bool isRef) const { } AstNodeDType::CTypeRecursed AstNodeDType::cTypeRecurse(bool compound) const { + // Legacy compound argument currently just passed through and unused CTypeRecursed info; const AstNodeDType* dtypep = this->skipRefp(); @@ -656,14 +657,9 @@ AstNodeDType::CTypeRecursed AstNodeDType::cTypeRecurse(bool compound) const { } else if (const auto* adtypep = VN_CAST_CONST(dtypep, UnpackArrayDType)) { if (adtypep->isCompound()) compound = true; const CTypeRecursed sub = adtypep->subDTypep()->cTypeRecurse(compound); - if (compound) { - info.m_type = "VlUnpacked<" + sub.m_type; - info.m_type += ", " + cvtToStr(adtypep->declRange().elements()); - info.m_type += ">"; - } else { - info.m_type = sub.m_type; - info.m_dims = "[" + cvtToStr(adtypep->declRange().elements()) + "]" + sub.m_dims; - } + info.m_type = "VlUnpacked<" + sub.m_type; + info.m_type += ", " + cvtToStr(adtypep->declRange().elements()); + info.m_type += ">"; } else if (const AstBasicDType* bdtypep = dtypep->basicp()) { // We don't print msb()/lsb() as multidim packed would require recursion, // and may confuse users as C++ data is stored always with bit 0 used @@ -687,12 +683,7 @@ AstNodeDType::CTypeRecursed AstNodeDType::cTypeRecurse(bool compound) const { } else if (dtypep->isQuad()) { info.m_type = "QData" + bitvec; } else if (dtypep->isWide()) { - if (compound) { - info.m_type = "VlWide<" + cvtToStr(dtypep->widthWords()) + ">"; - } else { - info.m_type += "WData" + bitvec; // []'s added later - info.m_dims = "[" + cvtToStr(dtypep->widthWords()) + "]"; - } + info.m_type = "VlWide<" + cvtToStr(dtypep->widthWords()) + ">" + bitvec; } } else { v3fatalSrc("Unknown data type in var type emitter: " << dtypep->prettyName()); diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 0a1416f1d..d231f37d5 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -104,6 +104,12 @@ public: : (nodep->isScQuad() ? "SQ" : "SI")); // clang-format on } + void emitDatap(AstNode* nodep) { + // When passing to a function with va_args the compiler doesn't + // know need a pointer so when wide, need to look inside VlWide + if (nodep->isWide()) puts(".data()"); + } + void emitOpName(AstNode* nodep, const string& format, AstNode* lhsp, AstNode* rhsp, AstNode* thsp); void emitDeclArrayBrackets(const AstVar* nodep) { @@ -376,9 +382,6 @@ public: iterateAndNextNull(nodep->bitp()); } puts(")"); - if (nodep->dtypep()->isWide()) { - puts(".data()"); // Access returned std::array as C array - } } virtual void visit(AstNodeCCall* nodep) override { if (AstCMethodCall* ccallp = VN_CAST(nodep, CMethodCall)) { @@ -415,12 +418,6 @@ public: comma = true; } puts(")"); - // if there is a return value that is wide convert to array - if (nodep->dtypep()->isWide() - && (VN_IS(nodep->fromp()->dtypep(), QueueDType) - || VN_IS(nodep->fromp()->dtypep(), DynArrayDType))) { - puts(".data()"); // Access returned std::array as C array - } // Some are statements some are math. if (nodep->isStatement()) puts(";\n"); UASSERT_OBJ(!nodep->isStatement() || VN_IS(nodep->dtypep(), VoidDType), nodep, @@ -653,7 +650,12 @@ public: putbs(", "); emitCvtPackStr(nodep->filenamep()); putbs(", "); - iterateAndNextNull(nodep->memp()); + { + const bool need_ptr = !VN_IS(nodep->memp()->dtypep(), AssocArrayDType); + if (need_ptr) puts(" &("); + iterateAndNextNull(nodep->memp()); + if (need_ptr) puts(")"); + } putbs(", "); if (nodep->lsbp()) { iterateAndNextNull(nodep->lsbp()); @@ -709,7 +711,6 @@ public: puts("VL_FREAD_I("); puts(cvtToStr(nodep->memp()->widthMin())); // Need real storage width putbs(","); - bool memory = false; uint32_t array_lo = 0; uint32_t array_size = 0; { @@ -719,7 +720,6 @@ public: } else if (VN_CAST(varrefp->varp()->dtypeSkipRefp(), BasicDType)) { } else if (const AstUnpackArrayDType* adtypep = VN_CAST(varrefp->varp()->dtypeSkipRefp(), UnpackArrayDType)) { - memory = true; array_lo = adtypep->lo(); array_size = adtypep->elementsConst(); } else { @@ -731,9 +731,9 @@ public: putbs(","); puts(cvtToStr(array_size)); putbs(", "); - if (!memory) puts("&("); + puts("&("); iterateAndNextNull(nodep->memp()); - if (!memory) puts(")"); + puts(")"); putbs(", "); iterateAndNextNull(nodep->filep()); putbs(", "); @@ -2193,17 +2193,11 @@ void EmitCStmts::displayEmit(AstNode* nodep, bool isScan) { if (func != "") { puts(func); } else if (argp) { - if (isScan) { - puts("&("); - } else if (fmt == '@') { - puts("&("); - } + bool addrof = isScan || (fmt == '@'); + if (addrof) puts("&("); iterate(argp); - if (isScan) { - puts(")"); - } else if (fmt == '@') { - puts(")"); - } + if (!addrof) emitDatap(argp); + if (addrof) puts(")"); } ofp()->indentDec(); } From ce79c4ebf948e4267af87b63a21c3e2a7ad5a4f6 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Mar 2021 12:47:19 -0500 Subject: [PATCH 011/110] Fix class unpacked-array compile error (#2774). --- Changes | 2 ++ include/verilated_heavy.h | 16 ++++++++++++++++ test_regress/t/t_class_format.out | 2 ++ test_regress/t/t_class_format.pl | 22 ++++++++++++++++++++++ test_regress/t/t_class_format.v | 31 +++++++++++++++++++++++++++++++ 5 files changed, 73 insertions(+) create mode 100644 test_regress/t/t_class_format.out create mode 100755 test_regress/t/t_class_format.pl create mode 100644 test_regress/t/t_class_format.v diff --git a/Changes b/Changes index b4f984768..e0740eebf 100644 --- a/Changes +++ b/Changes @@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Verilated signals now use VlWide and VlPacked in place of C arrays. +**** Fix class unpacked-array compile error (#2774). [Iru Cai] + * Verilator 4.200 2021-03-12 diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index a3cb94441..19df8b552 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -827,8 +827,24 @@ public: T_Value& operator[](size_t index) { return m_array[index]; }; const T_Value& operator[](size_t index) const { return m_array[index]; }; + + // Dumping. Verilog: str = $sformatf("%p", assoc) + std::string to_string() const { + std::string out = "'{"; + std::string comma; + for (int i = 0; i < T_Depth; ++i) { + out += comma + VL_TO_STRING(m_array[i]); + comma = ", "; + } + return out + "} "; + } }; +template +std::string VL_TO_STRING(const VlUnpacked& obj) { + return obj.to_string(); +} + //=================================================================== // Verilog class reference container // There are no multithreaded locks on this; the base variable must diff --git a/test_regress/t/t_class_format.out b/test_regress/t/t_class_format.out new file mode 100644 index 000000000..8005604fe --- /dev/null +++ b/test_regress/t/t_class_format.out @@ -0,0 +1,2 @@ +''{b:'h1, i:'h2a, carray4:'{'h0, 'h0, 'h0, 'h0} }' +*-* All Finished *-* diff --git a/test_regress/t/t_class_format.pl b/test_regress/t/t_class_format.pl new file mode 100755 index 000000000..03b63c1a0 --- /dev/null +++ b/test_regress/t/t_class_format.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_class_format.v b/test_regress/t/t_class_format.v new file mode 100644 index 000000000..a280d126b --- /dev/null +++ b/test_regress/t/t_class_format.v @@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +`ifdef verilator + `define stop $stop +`else + `define stop +`endif +`define checks(gotv,expv) do if ((gotv) != (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); + +class Cls; + bit b; + int i; + bit [15:0] carray4 [4]; +endclass + +module t (/*AUTOARG*/); + initial begin + Cls c; + c = new; + c.b = '1; + c.i = 42; + $display("'%p'", c); + + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule From e3788e871e593ac9360bd269bb15e9de32f8edf7 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Mar 2021 13:04:13 -0500 Subject: [PATCH 012/110] Fix unpacked-in-class array reference assignments --- src/V3AstNodes.cpp | 5 ++++- src/V3AstNodes.h | 4 ++-- src/V3LinkResolve.cpp | 2 +- src/V3Unknown.cpp | 4 ++-- test_regress/t/t_class_format.out | 2 +- test_regress/t/t_class_format.v | 5 +++++ 6 files changed, 15 insertions(+), 7 deletions(-) diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index 53341c960..c317b99ea 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -788,7 +788,7 @@ int AstNodeDType::widthPow2() const { } /// What is the base variable (or const) this dereferences? -AstNode* AstArraySel::baseFromp(AstNode* nodep) { +AstNode* AstArraySel::baseFromp(AstNode* nodep, bool overMembers) { // Else AstArraySel etc; search for the base while (nodep) { if (VN_IS(nodep, ArraySel)) { @@ -797,6 +797,9 @@ AstNode* AstArraySel::baseFromp(AstNode* nodep) { } else if (VN_IS(nodep, Sel)) { nodep = VN_CAST(nodep, Sel)->fromp(); continue; + } else if (overMembers && VN_IS(nodep, MemberSel)) { + nodep = VN_CAST(nodep, MemberSel)->fromp(); + continue; } // AstNodeSelPre stashes the associated variable under an ATTROF // of AstAttrType::VAR_BASE/MEMBER_BASE so it isn't constified diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index d47b7767a..5da14deca 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -1595,8 +1595,8 @@ public: virtual bool same(const AstNode* samep) const override { return true; } virtual int instrCount() const override { return widthInstrs(); } // Special operators - static AstNode* - baseFromp(AstNode* nodep); ///< What is the base variable (or const) this dereferences? + // Return base var (or const) nodep dereferences + static AstNode* baseFromp(AstNode* nodep, bool overMembers); }; class AstAssocSel final : public AstNodeSel { diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index f2f4c33a2..76339ebc2 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -218,7 +218,7 @@ private: // variable we're extracting from (to determine MSB/LSB/endianness/etc.) // So we replicate it in another node // Note that V3Param knows not to replace AstVarRef's under AstAttrOf's - AstNode* basefromp = AstArraySel::baseFromp(nodep); + AstNode* basefromp = AstArraySel::baseFromp(nodep, false); if (AstNodeVarRef* varrefp = VN_CAST(basefromp, NodeVarRef)) { // Maybe varxref - so need to clone nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::VAR_BASE, diff --git a/src/V3Unknown.cpp b/src/V3Unknown.cpp index 51ed39b09..5878a70c9 100644 --- a/src/V3Unknown.cpp +++ b/src/V3Unknown.cpp @@ -357,7 +357,7 @@ private: iterateChildren(nodep); if (!nodep->user1SetOnce()) { // Guard against reading/writing past end of bit vector array - AstNode* basefromp = AstArraySel::baseFromp(nodep); + AstNode* basefromp = AstArraySel::baseFromp(nodep, true); bool lvalue = false; if (const AstNodeVarRef* varrefp = VN_CAST(basefromp, NodeVarRef)) { lvalue = varrefp->access().isWriteOrRW(); @@ -405,7 +405,7 @@ private: if (!nodep->user1SetOnce()) { if (debug() == 9) nodep->dumpTree(cout, "-in: "); // Guard against reading/writing past end of arrays - AstNode* basefromp = AstArraySel::baseFromp(nodep->fromp()); + AstNode* basefromp = AstArraySel::baseFromp(nodep->fromp(), true); bool lvalue = false; if (const AstNodeVarRef* varrefp = VN_CAST(basefromp, NodeVarRef)) { lvalue = varrefp->access().isWriteOrRW(); diff --git a/test_regress/t/t_class_format.out b/test_regress/t/t_class_format.out index 8005604fe..36d844b8d 100644 --- a/test_regress/t/t_class_format.out +++ b/test_regress/t/t_class_format.out @@ -1,2 +1,2 @@ -''{b:'h1, i:'h2a, carray4:'{'h0, 'h0, 'h0, 'h0} }' +''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44} }' *-* All Finished *-* diff --git a/test_regress/t/t_class_format.v b/test_regress/t/t_class_format.v index a280d126b..9f2240814 100644 --- a/test_regress/t/t_class_format.v +++ b/test_regress/t/t_class_format.v @@ -23,6 +23,11 @@ module t (/*AUTOARG*/); c = new; c.b = '1; c.i = 42; + + c.carray4[0] = 16'h11; + c.carray4[1] = 16'h22; + c.carray4[2] = 16'h33; + c.carray4[3] = 16'h44; $display("'%p'", c); $write("*-* All Finished *-*\n"); From 9dcda6947dad1d405e057bc0b5b3c6c2b41a9960 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Mar 2021 13:39:29 -0500 Subject: [PATCH 013/110] Fix unpacked-in-class pattern assignment --- src/V3Slice.cpp | 4 +++- test_regress/t/t_class_format.out | 1 + test_regress/t/t_class_format.v | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/V3Slice.cpp b/src/V3Slice.cpp index 231eb5fbe..21a01f859 100644 --- a/src/V3Slice.cpp +++ b/src/V3Slice.cpp @@ -67,6 +67,8 @@ class SliceVisitor final : public AstNVisitor { nodep->v3error( nodep->prettyTypeName() << " is not an unpacked array, but is in an unpacked array context"); + } else { + V3Error::incErrors(); // Otherwise might infinite loop } m_assignError = true; return nodep->cloneTree(false); // Likely will cause downstream errors @@ -107,7 +109,7 @@ class SliceVisitor final : public AstNVisitor { : offset)); newp = new AstArraySel(nodep->fileline(), snodep->fromp()->cloneTree(false), leOffset); } else if (VN_IS(nodep, ArraySel) || VN_IS(nodep, NodeVarRef) || VN_IS(nodep, NodeSel) - || VN_IS(nodep, CMethodHard)) { + || VN_IS(nodep, CMethodHard) || VN_IS(nodep, MemberSel)) { UINFO(9, " cloneSel(" << elements << "," << offset << ") " << nodep << endl); int leOffset = !arrayp->rangep()->littleEndian() ? arrayp->rangep()->elementsConst() - 1 - offset diff --git a/test_regress/t/t_class_format.out b/test_regress/t/t_class_format.out index 36d844b8d..f620c0e3f 100644 --- a/test_regress/t/t_class_format.out +++ b/test_regress/t/t_class_format.out @@ -1,2 +1,3 @@ ''{b:'h1, i:'h2a, carray4:'{'h11, 'h22, 'h33, 'h44} }' +''{b:'h1, i:'h2a, carray4:'{'h911, 'h922, 'h933, 'h944} }' *-* All Finished *-* diff --git a/test_regress/t/t_class_format.v b/test_regress/t/t_class_format.v index 9f2240814..001a5284e 100644 --- a/test_regress/t/t_class_format.v +++ b/test_regress/t/t_class_format.v @@ -30,6 +30,9 @@ module t (/*AUTOARG*/); c.carray4[3] = 16'h44; $display("'%p'", c); + c.carray4 = '{16'h911, 16'h922, 16'h933, 16'h944}; + $display("'%p'", c); + $write("*-* All Finished *-*\n"); $finish; end From 6a189a1f8174bfa7c6829f1c0611092c5dbf2bc6 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Mar 2021 15:09:10 -0500 Subject: [PATCH 014/110] Fix exceeding command-line ar limit (#2834). --- Changes | 2 ++ include/verilated.mk.in | 28 ++++++++++++++++------------ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/Changes b/Changes index e0740eebf..841cb887d 100644 --- a/Changes +++ b/Changes @@ -8,6 +8,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix class unpacked-array compile error (#2774). [Iru Cai] +**** Fix exceeding command-line ar limit (#2834). [Yinan Xu] + * Verilator 4.200 2021-03-12 diff --git a/include/verilated.mk.in b/include/verilated.mk.in index 13930785d..89491d8a6 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -201,26 +201,30 @@ else VK_OBJS += $(VK_FAST_OBJS) $(VK_SLOW_OBJS) endif -# When archiving just objects (.o), single $(AR) run is enough. -# When merging objects (.o) and archives (.a), the following steps are taken. +fred.a: foo1.a foo2.a out.o + +# When archiving just objects (.o), use single $(AR) run +# 1. Make .tmp file with list of objects so don't exceed commend line +# When merging objects (.o) and archives (.a) additionally: # 1. Extract object files from .a # 2. Create a new archive from extracted .o and given .o %.a: - @echo "Archive $(AR) -cr $@ $^" - @if test $(words $(filter %.a,$^)) -eq 0; then \ - $(AR) -cr $@ $^; \ - $(RANLIB) $@; \ + $(info Archive $(AR) -rcs $@ $^) + $(file >$@.tmp) + $(foreach L, $(filter-out %.a,$^), $(file >>$@.tmp, $L)) + if test $(words $(filter %.a,$^)) -eq 0; then \ + $(AR) -rcs $@ @$@.tmp; \ else \ - $(RM) -rf $*__tmpdir; \ + $(RM) -rf $@.tmpdir; \ for archive in $(filter %.a,$^); do \ - mkdir -p $*__tmpdir/$$(basename $${archive}); \ - cd $*__tmpdir/$$(basename $${archive}); \ + mkdir -p $@.tmpdir/$$(basename $${archive}); \ + cd $@.tmpdir/$$(basename $${archive}); \ $(AR) -x ../../$${archive}; \ cd ../..; \ done; \ - $(AR) -cr $@ $(filter %.o,$^) $*__tmpdir/*/*.o; \ - $(RM) -rf $*__tmpdir; \ - fi + $(AR) -rcs $@ @$@.tmp $@.tmpdir/*/*.o; \ + fi \ + ; $(RM) -rf $@.tmp $@.tmpdir $(VM_PREFIX)__ALL.a: $(VK_OBJS) $(VM_HIER_LIBS) From 4261f72bd23343c737e800d7fd4a3f1e451734c3 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 13 Mar 2021 15:10:56 -0500 Subject: [PATCH 015/110] Fix exceeding command-line ar limit (#2834). --- include/verilated.mk.in | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/verilated.mk.in b/include/verilated.mk.in index 89491d8a6..51ac744d8 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -201,8 +201,6 @@ else VK_OBJS += $(VK_FAST_OBJS) $(VK_SLOW_OBJS) endif -fred.a: foo1.a foo2.a out.o - # When archiving just objects (.o), use single $(AR) run # 1. Make .tmp file with list of objects so don't exceed commend line # When merging objects (.o) and archives (.a) additionally: From e6b19d557e848ec0077f4847cd19ddf0f2a46660 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 14 Mar 2021 09:08:17 -0400 Subject: [PATCH 016/110] Fix false $dumpfile warning on model save (#2834). --- Changes | 2 ++ include/verilated.cpp | 8 ++++++-- include/verilated.h | 1 + src/V3EmitC.cpp | 2 +- 4 files changed, 10 insertions(+), 3 deletions(-) diff --git a/Changes b/Changes index 841cb887d..a39db2e05 100644 --- a/Changes +++ b/Changes @@ -10,6 +10,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix exceeding command-line ar limit (#2834). [Yinan Xu] +**** Fix false $dumpfile warning on model save (#2834). [Yinan Xu] + * Verilator 4.200 2021-03-12 diff --git a/include/verilated.cpp b/include/verilated.cpp index 3d3f8bddc..0ee5a46e6 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -2202,11 +2202,15 @@ void VerilatedContext::dumpfile(const std::string& flag) VL_MT_SAFE_EXCLUDES(m_t } std::string VerilatedContext::dumpfile() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) { const VerilatedLockGuard lock(m_timeDumpMutex); - if (VL_UNLIKELY(m_dumpfile.empty())) { + return m_dumpfile; +} +std::string VerilatedContext::dumpfileCheck() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex) { + const std::string out = dumpfile(); + if (VL_UNLIKELY(out.empty())) { VL_PRINTF_MT("%%Warning: $dumpvar ignored as not proceeded by $dumpfile\n"); return ""; } - return m_dumpfile; + return out; } void VerilatedContext::errorCount(int val) VL_MT_SAFE { const VerilatedLockGuard lock(m_mutex); diff --git a/include/verilated.h b/include/verilated.h index 980beda10..49997bcbc 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -529,6 +529,7 @@ public: // But for internal use only // Internal: $dumpfile void dumpfile(const std::string& flag) VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); std::string dumpfile() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); + std::string dumpfileCheck() const VL_MT_SAFE_EXCLUDES(m_timeDumpMutex); // Internal: --prof-threads related settings void profThreadsStart(vluint64_t flag) VL_MT_SAFE; diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index d231f37d5..0ea41997c 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -3523,7 +3523,7 @@ class EmitCTrace final : EmitCStmts { puts("if (VL_UNLIKELY(!__VlSymsp->__Vm_dumperp)) {\n"); puts("__VlSymsp->__Vm_dumperp = new " + v3Global.opt.traceClassLang() + "();\n"); puts("trace(__VlSymsp->__Vm_dumperp, 0, 0);\n"); - puts("std::string dumpfile = __VlSymsp->_vm_contextp__->dumpfile();\n"); + puts("std::string dumpfile = __VlSymsp->_vm_contextp__->dumpfileCheck();\n"); puts("__VlSymsp->__Vm_dumperp->open(dumpfile.c_str());\n"); puts("__VlSymsp->__Vm_dumping = true;\n"); puts("}\n"); From 50866e470ae76403a7274f7e7657962f0b87a078 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 14 Mar 2021 14:11:57 -0400 Subject: [PATCH 017/110] Commentary: Convert Changes to RST format --- .gitattributes | 1 + Changes | 5681 +++++++++++++++++++++------------------------ docs/CONTRIBUTORS | 8 +- 3 files changed, 2656 insertions(+), 3034 deletions(-) diff --git a/.gitattributes b/.gitattributes index ead49ad4d..d1eb3d5f4 100644 --- a/.gitattributes +++ b/.gitattributes @@ -1,4 +1,5 @@ *.v linguist-language=SystemVerilog *.vh linguist-language=SystemVerilog *.sv linguist-language=SystemVerilog +Changes linguist-language=reStructuredText nodist linguist-detectable=false diff --git a/Changes b/Changes index a39db2e05..b19a62339 100644 --- a/Changes +++ b/Changes @@ -1,3967 +1,3588 @@ -Revision history for Verilator +******************************* +Revision History and Change Log +******************************* -The contributors that suggested a given feature are shown in []. Thanks! +The changes in each Verilator version are described below. The +contributors that suggested a given feature are shown in []. Thanks! -* Verilator 4.201 devel -**** Verilated signals now use VlWide and VlPacked in place of C arrays. +Verilator 4.201 devel +========================== -**** Fix class unpacked-array compile error (#2774). [Iru Cai] +**Minor:** -**** Fix exceeding command-line ar limit (#2834). [Yinan Xu] +* Verilated signals now use VlWide and VlPacked in place of C arrays. +* Fix class unpacked-array compile error (#2774). [Iru Cai] +* Fix exceeding command-line ar limit (#2834). [Yinan Xu] +* Fix false $dumpfile warning on model save (#2834). [Yinan Xu] -**** Fix false $dumpfile warning on model save (#2834). [Yinan Xu] +Verilator 4.200 2021-03-12 +========================== -* Verilator 4.200 2021-03-12 +**Announcement:** -** Add simulation context (VerilatedContext) to allow multiple fully independent - models to be in the same process. Please see the updated examples. (#2660) +* --inhibit-sim is planned for deprecation, file a bug if this is still being used. -** Add context->time() and context->timeInc() API calls, to set simulation time. - These now are recommended in place of the legacy sc_time_stamp(). +**Major:** -**** Converted Asciidoc documentation into reStructuredText (RST) format. +* Add simulation context (VerilatedContext) to allow multiple fully independent + models to be in the same process. Please see the updated examples. (#2660) +* Add context->time() and context->timeInc() API calls, to set simulation time. + These now are recommended in place of the legacy sc_time_stamp(). -**** --inhibit-sim is planned for deprecation, file a bug if this is still being used. +**Minor:** -**** Fix range inheritance on port without data type (#2753). [Embedded Go] +* Converted Asciidoc documentation into reStructuredText (RST) format. +* Fix range inheritance on port without data type (#2753). [Embedded Go] +* Fix slice-assign overflow (#2803) (#2811). [David Turner] +* Fix interface array connection ordering broken in v4.110 (#2827). [Don Owen] +* Fix or-reduction on different scopes broken in 4.110 (#2828). [Yinan Xu] +* Fix MSVC++ compile error. (#2831) (#2833) [Drew Taussig] -**** Fix slice-assign overflow (#2803) (#2811). [David Turner] -**** Fix interface array connection ordering broken in v4.110 (#2827). [Don Owen] +Verilator 4.110 2021-02-25 +========================== -**** Fix or-reduction on different scopes broken in 4.110 (#2828). [Yinan Xu] +**Major:** -**** Fix MSVC++ compile error. (#2831) (#2833) [Drew Taussig] +* Optimize bit operations and others (#2186) (#2632) (#2633) (#2751) (#2800) [Yutetsu TAKATSUKASA] +**Minor:** + +* Support concat selection (#2721). +* Support struct scopes when dumping structs to VCD (#2776) [Alex Torregrosa] +* Generate SELRANGE for potentially unreachable code (#2625) (#2754) [Pierre-Henri Horrein] +* For --flatten, override inlining of public and no_inline modules (#2761) [James Hanlon] +* Fix little endian interface pin swizzling (#2475). [Don Owen] +* Fix range inheritance on port without data type (#2753). [Embedded Go] +* Fix TIMESCALE warnings on primitives (#2763). [Xuanqi] +* Fix to exclude strings from toggle coverage (#2766) (#2767) [Paul Wright] +* Fix $fread extra semicolon inside statements. [Leendert van Doorn] +* Fix class extends with VM_PARALLEL_BUILDS (#2775). [Iru Cai] +* Fix shifts by > 32 bit values (#2785). [qrq992] +* Fix examples not flushing vcd (#2787). [Richard E George] +* Fix little endian packed array pattern assignment (#2795). [Alex Torregrosa] -* Verilator 4.110 2021-02-25 -*** Optimize bit operations and others (#2186) (#2632) (#2633) (#2751) (#2800) [Yutetsu TAKATSUKASA] +Verilator 4.108 2021-01-10 +========================== -**** Support concat selection (#2721). +**Major:** -**** Support struct scopes when dumping structs to VCD (#2776) [Alex Torregrosa] +* Many VPI changes for IEEE compatibility, which may alter behavior from previous releases. +* Support randomize() class method and rand (#2607). [Krzysztof Bieganski] -**** Generate SELRANGE for potentially unreachable code (#2625) (#2754) [Pierre-Henri Horrein] +**Minor:** -**** For --flatten, override inlining of public and no_inline modules (#2761) [James Hanlon] +* Support $cast and new CASTCONST warning. +* Add --top option as alias of --top-module. +* Add LATCH and NOLATCH warnings (#1609) (#2740). [Julien Margetts] +* Remove Unix::Processors internal test dependency. +* Report UNUSED on parameters, localparam and genvars (#2627). [Charles Eric LaForest] +* Add error on real to non-real output pins (#2690). [Peter Monsson] +* Support package imports before parameters in interfaces (#2714). [James Hanlon] +* Support --sanitize in internal tests (#2705). [Yutetsu TAKATSUKASA] +* Fix passing parameter type instantiations by position number. +* Fix DPI open array handling issues. +* Fix error when dotted refers to missing module (#2095). [Alexander Grobman] +* Fix little endian packed array counting (#2499). [phantom-killua] +* Fix showing reference locations for BLKANDNBLK (#2170). [Yuri Victorovich] +* Fix genblk naming to match IEEE (#2686). [tinshark] +* Fix VPI memory word indexing (#2695). [Marlon James] +* Fix vpiLeftRange on little-endian memories (#2696). [Marlon James] +* Fix VPI module tree (#2704). [Todd Strader] +* Fix vpi_release_handle to be called implicitly per IEEE (#2706). +* Fix to allow inheriting 'VerilatedVcdFile' class. (#2720) [HyungKi Jeong] +* Fix $urandom_range maximum value (#2723). [Nandu Raj] +* Fix tracing empty sc module (#2729). +* Fix generate for unrolling to be signed (#2730). [yanx21] +* Fix to emit timescale in hierarchical blocks (#2735). [Yutetsu TAKATSUKASA] +* Fix to ignore coverage on real ports (#2741) (#2745). [Paul Wright] -**** Fix little endian interface pin swizzling (#2475). [Don Owen] -**** Fix range inheritance on port without data type (#2753). [Embedded Go] -**** Fix TIMESCALE warnings on primitives (#2763). [Xuanqi] +Verilator 4.106 2020-12-02 +========================== -**** Fix to exclude strings from toggle coverage (#2766) (#2767) [Paul Wright] +**Major:** + +* Change -sv option to select 1800-2017 instead of 1800-2005. + +**Minor:** + +* Check for proper 'local' and 'protected' (#2228). +* Support $random and $urandom seeds. +* Support $monitor and $strobe. +* Support complex function arguments. +* Support 'super'. +* Support 'with item.index'. +* Fix the default GNU Make executable name on FreeBSD (#2553). [Yuri Victorovich] +* Fix trace signal names getting hashed (#2643). [Barbara Gigerl] +* Fix unpacked array parameters near functions (#2639). [Anderson Ignacio da Silva] +* Fix access to non-overridden base class variable (#2654). [Tobias Rosenkranz] + + +Verilator 4.104 2020-11-14 +========================== + +**Minor:** + +* Support queue and associative array 'with' statements (#2616). +* Support queue slicing (#2326). +* Support associative array pattern assignments and defaults. +* Support static methods and typedefs in classes (#2615). [Krzysztof Bieganski] +* Add error on typedef referencing self (#2539). [Cody Piersall] +* With --debug, turn off address space layout randomization. +* Fix iteration over mutating list bug in VPI (#2588). [Kaleb Barrett] +* Fix cast width propagation (#2597). [flex-liu] +* Fix return from callValueCbs (#2589) (#2605). [Marlon James] +* Fix WIDTH warnings on comparisons with nullptr (#2602). [Rupert Swarbrick] +* Fix fault when $fgets, $sscanf, etc used with string (#2604). [Yutetsu TAKATSUKASA] +* Fix WIFEXITED missing from MinGW/MSYS2 (#2609). [Jean Berniolles] +* Fix queue poping wrong value when otherwise unused (#2512). [nanduraj1] +* Fix arrays of modport interfaces (#2614). [Thierry Tambe] +* Fix split_var internal error (#2640) (#2641). [Yutetsu TAKATSUKASA] + + +Verilator 4.102 2020-10-15 +========================== + +**Minor:** + +* Support const object new() assignments. +* Support # as a comment in -f files (#2497). [phantom-killua] +* Support 'this' (#2585). [Rafal Kapuscik] +* Support defines for FST tracing (#2592). [Markus Krause] +* Support |=> inside properties (#1292). [Peter Monsson] +* Fix timescale with --hierarchical (#2554). [Yutetsu TAKATSUKASA] +* Fix cmake build with --hierarchical (#2560). [Yutetsu TAKATSUKASA] +* Fix -G dropping public indication (#2561). [Andrew Goessling] +* Fix $urandom_range passed variable (#2563). [nanduraj1] +* Fix method calls to package class functions (#2565). [Peter Monsson] +* Fix class wide member display (#2567). [Nandu Raj P] +* Fix hierarchical references inside function (#2267) (#2572). [James Pallister] +* Fix flushCall for backward compatibility (#2580). [chenguokai] +* Fix preprocessor stringify of undefined macro. [Martin Whitaker] + + +Verilator 4.100 2020-09-07 +========================== + +**Major:** + +* C++11 or newer compilers are now required. +* SystemC 2.3.0 or newer (SYSTEMC_VERSION >= 20111121) is now required. +* Support hierarchical Verilation (#2206). [Yutetsu TAKATSUKASA] + +**Minor:** + +* Support (with limitations) class extern, class extends, virtual class. +* Support $urandom, $urandom_range without stability. +* Support assume property. [Peter Monsson] +* Support |=> inside properties (#1292). [Peter Monsson] +* Fix false DECLFILENAME on black-boxed modules (#2430). [Philipp Wagner] +* Fix naming of "id : begin" blocks. +* Fix class constructor error on assignments to const. +* Fix splitting eval functions with --output-split-cfuncs (#2368). [Geza Lore] +* Fix queues as class members (#2525). [nanduraj1] + + +Verilator 4.040 2020-08-15 +========================== + +**Announcement:** + +* Version 4.040 is planned to be the final version that will support + pre-C++11 compilers. Please move to C++11 or newer compilers. + +**Minor:** + +* Fix arrayed interfaces, broke in 4.038 (#2468). [Josh Redford] +* Support $stable, $rose and $fell. (#2148) (#2501) [Peter Monsson] +* Support simple function localparams (#2461). [James Hanlon] +* Miscellaneous parsing error changes towards UVM support. +* Fix arrayed interfaces (#2469). [Josh Redford] +* Fix protect lib VCS warning. (#2479) [Julien Margetts] +* Fix combining different-width parameters (#2484). [abirkmanis] +* Fix protect-lib without sequential logic (#2492). [Yutetsu TAKATSUKASA] +* Fix V3Unknown from running with flat XML output (#2494). [James Hanlon] +* Fix non-32 bit conversion to float (#2495). [dsvf] +* Fix casting non-self-determined subexpressions (#2493). [phantom-killua] +* Fix SystemC net names (#2500). [Edgar E. Iglesias] +* Fix build with Bison 3.7 and newer (#2505). [Rupert Swarbrick] +* Fix slice of unpacked array (#2506) (#2507). [Yutetsu TAKATSUKASA] + + +Verilator 4.038 2020-07-11 +========================== + +**Announcement:** + +* Versions 4.038 and 4.040 are planned to be the final versions that will + support pre-C++11 compilers. Please move to C++11 or newer compilers. + +**Minor:** + +* Support VPI access to parameters and localparam. [Ludwig Rogiers] +* Support parsing (not elaboration, yet) of UVM. +* Add new UNSUPPORTED error code to replace most previous Unsupported: messages. +* With --bbox-unsup continue parsing on many (not all) UVM constructs. +* Support for-loop increments with commas. +* Support $swrite with arbitrary arguments. +* Support $writememb (#2450). [Fan Shupei] +* Fix OS X, Free BSD, and -m32 portability issues. [Geza Lore] +* Fix to flush FST trace on termination due to $stop or assertion failure. +* Fix part select error when multipling by power-of-two (#2413). [Conor McCullough] +* Fix division exception (#2460) [Kuoping Hsu] + + +Verilator 4.036 2020-06-06 +========================== + +**Major:** + +* OPT_FAST is now -Os by default. See the BENCHMARKING & OPTIMIZATION part + of the manual if you experience issues with compilation speed. +* --output-split is now on by default. VM_PARALLEL_BUILDS is set by default + iff the --output-split caused an actual file split to + occur. --output-split-cfuncs and --output-split-ctrace now default to + the value of --output-split. These changes should improve build times of + medium and large designs with default options. User makefiles may require + changes. + +**Minor:** + +* Configure now enables SystemC if it is installed as a system headers, + e.g. with 'apt-get install systemc-dev'. +* Add --waiver-output flag that writes a verilator config file (.vlt) with + waivers to the warnings emitted during a Verilator run. +* Support verilator_coverage --write-info for lcov HTML reports. +* Line Coverage now tracks all statement lines, not just branch lines. +* The run-time library is now compiled with -Os by default. (#2369, #2373) +* Support multi channel descriptor I/O (#2190) [Stephen Henry] +* Support $countbits. (#2287) [Yossi Nivin] +* Support $isunbounded and parameter $. (#2104) +* Support unpacked array .sum and .product. +* Support prefix/postfix increment/decrement. (#2223) [Maciej Sobkowski] +* Fix FST tracing of little bit endian signals. [Geza Lore] +* Fix +: and -: on unpacked arrays. (#2304) [engr248] +* Fix $isunknown with constant Z's. +* Fix queues and dynamic array wide ops. (#2352) [Vassilis Papaefstathiou] + + +Verilator 4.034 2020-05-03 +========================== + +**Major:** + +* Support simplistic classes with many restrictions, see manual. (#377) +* Support IEEE time units and time precisions. (#234) + Includes `timescale, $printtimescale, $timeformat. + VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed + and the time precision must now match the SystemC time precision. To + get closer behavior to older versions, use e.g. --timescale-override + "1ps/1ps". +* Add --build to call make automatically. (#2249) [Yutetsu TAKATSUKASA] +* Configuring with ccache present now defaults to using it; see OBJCACHE. +* Fix DPI import/export to be standard compliant. (#2236) [Geza Lore] +* Add --trace-threads for general multithreaded tracing. (#2269) [Geza Lore] + +**Minor:** + +* Add --flatten for use with --xml-only. (#2270) [James Hanlon] +* Greatly improve FST/VCD dump performance (#2244) (#2246) (#2250) (#2257) [Geza Lore] +* Support $ferror, and $fflush without arguments. (#1638) +* Support event data type (with some restrictions). +* Support $root. (#2150) [Keyi Zhang] +* Add error if use SystemC 2.2 and earlier (pre-2011) as is deprecated. +* Fix build of fast path tracing code to use OPT_FAST. (#2245) [Geza Lore] +* Fix arrayed instances connecting to slices. (#2263) [Don/engr248] +* Fix error on unpacked connecting to packed. (#2288) [Joseph Shaker] +* Fix logical not optimization with empty begin. (#2291) [Baltazar Ortiz] +* Fix reduction OR on wide data, broke in v4.026. (#2300) [Jack Koenig] +* Fix clock enables with bit-extends. (#2299) [Marco Widmer] +* Fix MacOs Homebrew by removing default LIBS. (#2298) [Ryan Clarke] + + +Verilator 4.032 2020-04-04 +========================== + +**Minor:** + +* Add column numbers to errors and warnings. +* Add GCC 9-style line number prefix when showing source text for errors. +* Add setting VM_PARALLEL_BUILDS=1 when using --output-split. (#2185) +* Change --quiet-exit to also suppress 'Exiting due to N errors'. +* Suppress REALCVT for whole real numbers. +* Support split_var in vlt files. (#2219) [Marco Widmer] +* Fix parameter type redeclaring a type. (#2195) [hdzhangdoc] +* Fix VCD open with empty filename. (#2198) [Julius Baxter] +* Fix packages as enum base types. (#2202) [Driss Hafdi] +* Fix duplicate typedefs in generate for. (#2205) [hdzhangdoc] +* Fix MinW portability. (#2114) [Sean Cross] +* Fix assertions with unique case inside. (#2199) [hdzhangdoc] +* Fix implicit conversion of floats to wide integers. + + +Verilator 4.030 2020-03-08 +========================== + +**Major:** + +* Add split_var metacomment to assist UNOPTFLAT fixes. (#2066) [Yutetsu TAKATSUKASA] +* Support $dumpfile and $dumpvars. (#2126) [Alexander Grobman] +* Support dynamic arrays. (#379) + +**Minor:** + +* Add +verilator+noassert flag to disable assertion checking. [Tobias Wölfel] +* Add check for assertOn for asserts. (#2162) [Tobias Wölfel] +* Add --structs-packed for forward compatibility. +* Support $displayb/o/h, $writeb/o/h, etc. (#1637) +* Use gcc -Os in examples instead of -O2 for better average performance. +* Fix genblk naming with directly nested generate blocks. (#2176) [Alexander Grobman] +* Fix undeclared VL_SHIFTR_WWQ. (#2114) [Alex Solomatnikov] + + +Verilator 4.028 2020-02-08 +========================== + +**Major:** + +* Support attributes (public, isolate_assignments, etc.) in configuration files. +* Add -match to lint_off to waive warnings. [Philipp Wagner] + +**Minor:** + +* Link Verilator binary partially statically. (#2146) [Geza Lore] +* Verilation speed improvements (#2133) (#2138) [Geza Lore] +* Support libgoogle-perftools-dev's libtcmalloc if available. (#2137) [Geza Lore] +* Support $readmem/$writemem with assoc arrarys. (#2100) [agrobman] +* Support type(expression) operator and $typename. (#1650) +* Support left justified $display. (#2101) [Pieter Kapsenberg] +* Support string character access via indexing. +* Support enum.next(k) with constant k > 1. (#2125) [Tobias Rosenkranz] +* Support parameter access from arrays of interfaces. (#2155) [Todd Strader] +* Add parameter values in XML. #2110. [Pieter Kapsenberg] +* Add loc column location in XML (replaces fl). (#2122) [Pieter Kapsenberg] +* Add error on misused define. [Topa Tota] +* Add parameter to set maximum signal width. (#2082) [Øyvind Harboe] +* Add warning on genvar in normal for loop. (#2143) [yurivict] +* Fix VPI scope naming for public modules. [Nandu Raj] +* Fix FST tracing of enums inside structs. [fsiegle] +* Fix WIDTH warning on " in assertions. (#2069) [Peter Monsson] +* Support string compare, ato*, etc methods. (#1606) [Yutetsu TAKATSUKASA] +* Support immediate cover statements. +* Ignore `uselib to end-of-line. (#1634) [Frederic Antonin] +* Update FST trace API for better performance. +* Add vpiTimeUnit and allow to specify time as string. (#1636) [Stefan Wallentowitz] +* Add error when `resetall inside module (IEEE 2017-22.3). +* Add cleaner error on version control conflicts in sources. +* Fix little endian cell ranges. (#1631) [Julien Margetts] +* Fix queue issues (#1641) (#1643) [Peter Monsson, Stefan Wallentowitz] +* Fix strcasecmp for windows. (#1651) [Kuba Ober] +* Fix disable iff in assertions. Closes #1404. [Peter Monsson] +* Fix huge case statement performance. Closes #1644. [Julien Margetts] +* Fix tracing -1 index arrays. Closes #2090. [Yutetsu Takatsukasa] +* Fix expand optimization slowing --lint-only. Closes #2091. [Thomas Watts] +* Fix %{number}s with strings. #2093. [agrobman] +* Fix shebang breaking some shells. Closes #2067. [zdave] + + +Verilator 4.024 2019-12-08 +========================== + +**Major:** + +* Support associative arrays (excluding [*] and pattern assignments). (#544) +* Support queues (excluding {} notation and pattern assignments). (#545) + +**Minor:** + +* Add +verilator+error+limit to see more assertion errors. [Peter Monsson] +* Support string.toupper and string.tolower. +* Support $rewind and $ungetc. +* Support shortreal as real, with a SHORTREAL warning. +* Add -Wpedantic and -Wno-context for compliance testing. +* Add error on redefining preprocessor directives. [Piotr Binkowski] +* Support $value$plusargs float and shorts. (#1592) (#1619) [Garrett Smith] +* Fix gate lvalue optimization error. (#831) [Jonathon Donaldson, Driss Hafdi] +* Fix color assertion on empty if. (#1604) [Andrew Holme] +* Fix for loop missing initializer. (#1605) [Andrew Holme] +* Fix hang on concat error. (#1608) [Bogdan Vukobratovic] +* Fix VPI timed callbacks to be one-shot, pull5. [Matthew Ballance] +* Fix // in filenames. (#1610) [Peter Nelson] +* Fix $display("%p") to be closer to IEEE. +* Fix labels on functions with returns. (#1614) [Mitch Hayenga] +* Fix false unused message on __Vemumtab. (#2061) [Tobias Rosenkranz] +* Fix assertion on dotted parameter arrayed function. (#1620) [Rich Porter] +* Fix interface reference tracing. (#1595) [Todd Strader] +* Fix error on unpacked concatenations. (#1627) [Driss Hafdi] + + +Verilator 4.022 2019-11-10 +========================== + +**Major:** + +* Add --protect-lib. (#1490) [Todd Strader] +* Add cmake support. (#1363) [Patrick Stewart] + +**Minor:** + +* Examples have been renamed. +* Add --protect-ids to obscure information in objects. (#1521) [Todd Strader] +* Add --trace-coverage. +* Add --xml-output. +* Support multithreading on Windows. [Patrick Stewart] +* Suppress 'command failed' on normal errors. +* Support some unpacked arrays in parameters. (#1315) [Marshal Qiao] +* Add interface port visibility in traces. (#1594) [Todd Strader] +* Increase case duplicate/incomplete to 16 bit tables. (#1545) [Yossi Nivin] +* Support quoted arguments in -f files. (#1535) [Yves Mathieu] +* Optimize modulus by power-of-two constants, and masked conditionals. +* Fix detecting missing reg types. (#1570) [Jacko Dirks] +* Fix multithreaded yield behavior when no work. [Patrick Stewart] +* Fix bad-syntax crashes. (#1548, #1550-#1553, #1557-#1560, #1563, + #1573-#1577, #1579, #1582-#1591) [Eric Rippey] +* Fix false CMPCONST/UNSIGNED warnings on "inside". (#1581) [Mitch Hayenga] + + +Verilator 4.020 2019-10-06 +========================== + +**Minor:** + +* Add --public-flat-rw. (#1511) [Stefan Wallentowitz] +* Support $fseek, $ftell, $frewind. (#1496) [Howard Su] +* Support vpiModule. (#1469) [Stefan Wallentowitz] +* Make Syms file honor --output-split-cfuncs. (#1499) [Todd Strader] +* Fix make test with no VERILATOR_ROOT. (#1494) [Ahmed El-Mahmoudy] +* Fix error on multidimensional cells. (#1505) [Anderson Ignacio Da Silva] +* Fix config_rev revision detection on old versions. +* Fix false warning on backward indexing. (#1507) [Hao Shi] +* Fix vpiType accessor. (#1509) (#1510) [Stefan Wallentowitz] +* Fix ugly error on interface misuse. (#1525) [Bogdan Vukobratovic] +* Fix misc bad-syntax crashes. (#1529) (#1530) (#1531) (#1532) (#1533) [Eric Rippey] +* Fix case statements with strings. (#1536) [Philipp Wagner] +* Fix some coverage lost when multithreaded. (#2151) + + +Verilator 4.018 2019-08-29 +========================== + +**Major:** + +* When showing an error, show source code and offer suggestions of replacements. +* When showing an error, show the instance location. (#1305) [Todd Strader] + +**Minor:** + +* Add --rr. (#1481) [Todd Strader] +* Change MULTITOP to warning to help linting, see manual. +* Add XSim support to driver.pl. (#1493) [Todd Strader] +* Add --dpi-hdr-only. (#1491) [Todd Strader] +* Show included-from filenames in warnings. (#1439) [Todd Strader] +* Fix elaboration time errors. (#1429) [Udi Finkelstein] +* Fix not reporting some duplicate signals/ports. (#1462) [Peter Gerst] +* Fix not in array context on non-power-of-two slices. (#2027) [Yu Sheng Lin] +* Fix system compile flags injection. [Gianfranco Costamagna] +* Fix enum values not being sized based on parent. (#1442) [Dan Petrisko] +* Fix internal error on gate optimization of assign. (#1475) [Oyvind Harboe] + + + +Verilator 4.016 2019-06-16 +========================== + +**Minor:** + +* Add --quiet-exit. (#1436) [Todd Strader] +* Error continuation lines no longer have %Error prefix. +* Support logical equivalence operator <->. +* Support VerilatedFstC set_time_unit. (#1433) [Pieter Kapsenberg] +* Support deferred assertions. (#1449) [Charles Eddleston] +* Mark infrequently called functions with GCC cold attribute. +* Fix sign-compare warning in verilated.cpp. (#1437) [Sergey Kvachonok] +* Fix fault on $realtime with %t. (#1443) [Julien Margetts] +* Fix $display with string without %s. (#1441) [Denis Rystsov] +* Fix parameter function string returns. (#1441) [Denis Rystsov] +* Fix invalid XML output due to special chars. (#1444) [Kanad Kanhere] +* Fix performance when mulithreaded on 1 CPU. (#1455) [Stefan Wallentowitz] +* Fix type and real parameter issues (#1427) (#1456) (#1458) [Todd Strader] +* Fix build error on MinGW. (#1460) [Richard Myers] +* Fix not reporting some duplicate signals. (#1462) [Peter Gerst] +* Fix --savable invalid C++ on packed arrays. (#1465) [Alex Chadwick] +* Fix constant function return of function var. (#1467) [Roman Popov] + + +Verilator 4.014 2019-05-08 +========================== + +**Minor:** + +* Add --trace-fst-thread. +* Support '#' comments in $readmem. (#1411) [Frederick Requin] +* Support "'dx" constants. (#1423) [Udi Finkelstein] +* For FST tracing use LZ4 compression. [Tony Bybell] +* Add error when use parameters without value. (#1424) [Peter Gerst] +* Auto-extend and WIDTH warn on unsized X/Zs. (#1423) [Udi Finkelstein] +* Fix missing VL_SHIFTL_ errors. (#1412) (#1415) [Larry Lee] +* Fix MinGW GCC 6 printf formats. (#1413) [Sergey Kvachonok] +* Fix test problems when missing fst2vcd. (#1417) [Todd Strader] +* Fix GTKWave register warning. (#1421) [Pieter Kapsenberg] +* Fix FST enums not displaying. (#1426) [Danilo Ramos] +* Fix table compile error with multiinterfaces. (#1431) [Bogdan Vukobratovic] + + +Verilator 4.012 2019-03-23 +========================== + +**Minor:** + +* Add +verilator+seed. (#1396) [Stan Sokorac] +* Support $fread. [Leendert van Doorn] +* Support void' cast on functions called as tasks. (#1383) [Al Grant] +* Add IGNOREDRETURN warning. (#1383) +* Report PORTSHORT errors on concat constants. (#1400) [Will Korteland] +* Fix VERILATOR_GDB being ignored. (#2017) [Yu Sheng Lin] +* Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen] +* Fix MSVC compile error. (#1406) [Benjamin Gartner] +* Fix maintainer test when no Parallel::Forker. (#1977) [Enzo Chi] +* Fix +1364-1995ext flags applying too late. (#1384) [Al Grant] + + +Verilator 4.010 2019-01-27 +========================== + +**Minor:** + +* Removed --trace-lxt2, use --trace-fst instead. +* For --xml, add additional information. (#1372) [Jonathan Kimmitt] +* Add circular typedef error. (#1388) [Al Grant] +* Add unsupported for loops error. (#1986) [Yu Sheng Lin] +* Fix FST tracing of wide arrays. (#1376) [Aleksander Osman] +* Fix error when pattern assignment has too few elements. (#1378) [Viktor Tomov] +* Fix error when no modules in $unit. (#1381) [Al Grant] +* Fix missing too many digits warning. (#1380) [Jonathan Kimmitt] +* Fix uninitialized data in verFiles and unroller. (#1385) (#1386) [Al Grant] +* Fix internal error on xrefs into unrolled functions. (#1387) [Al Grant] +* Fix DPI export void compiler error. (#1391) [Stan Sokorac] + + +Verilator 4.008 2018-12-01 +========================== -**** Fix $fread extra semicolon inside statements. [Leendert van Doorn] +**Minor:** + +* Support "ref" and "const ref" pins and functions. (#1360) [Jake Longo] +* In --xml-only show the original unmodified names, and add module_files + and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere] +* Add CONTASSREG error on continuous assignments to regs. (#1369) [Peter Gerst] +* Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton] +* Add IMPORTSTAR warning on import::* inside $unit scope. +* Fix --trace-lxt2 compile error on MinGW. (#1990) [HyungKi Jeong] +* Fix hang on bad pattern keys. (#1364) [Matt Myers] +* Fix crash due to cygwin bug in getline. (#1349) [Affe Mao] +* Fix __Slow files getting compiled with OPT_FAST. (#1370) [Thomas Watts] -**** Fix class extends with VM_PARALLEL_BUILDS (#2775). [Iru Cai] -**** Fix shifts by > 32 bit values (#2785). [qrq992] +Verilator 4.006 2018-10-27 +========================== -**** Fix examples not flushing vcd (#2787). [Richard E George] +**Minor:** + +* Add --pp-comments. (#1988) [Robert Henry] +* Add --dump-defines. +* For --trace-fst, save enum decoding information. (#1358) [Sergi Granell] + (To visualize enumeration data you must use GTKwave 3.3.95 or newer.) +* For --trace-fst, instead of *.fst.hier, put data into *.fst. [Tony Bybell] +* Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong] +* Fix Windows .exe not found. (#1361) [Patrick Stewart] -**** Fix little endian packed array pattern assignment (#2795). [Alex Torregrosa] +Verilator 4.004 2018-10-06 +========================== -* Verilator 4.108 2021-01-10 +**Major:** -** Many VPI changes for IEEE compatibility, which may alter behavior from previous releases. +* Add GTKWave FST native tracing. (#1356) [Sergi Granell] + (Verilator developers need to pull the latest vcddiff.) -** Support randomize() class method and rand (#2607). [Krzysztof Bieganski] +**Minor:** -*** Support $cast and new CASTCONST warning. +* Support $past. [Dan Gisselquist] +* Support restrict. (#1350) [Clifford Wolf] +* Rename include/lxt2 to include/gtkwave. +* Fix replication of 64-bit signal change detects. +* Fix Mac OSX 10.13.6 / LLVM 9.1 compile issues. (#1348) [Kevin Kiningham] +* Fix MinGW compile issues. (#1979) [HyungKi Jeong] -*** Add --top option as alias of --top-module. -*** Add LATCH and NOLATCH warnings (#1609) (#2740). [Julien Margetts] +Verilator 4.002 2018-09-16 +========================== -**** Remove Unix::Processors internal test dependency. +**Major:** -**** Report UNUSED on parameters, localparam and genvars (#2627). [Charles Eric LaForest] +* This is a major release. Any patches may require major rework to apply. + [Thanks everyone] +* Add multithreaded model generation. +* Add runtime arguments. +* Add GTKWave LXT2 native tracing. (#1333) [Yu Sheng Lin] +* Note $random has new algorithm; results may vary vs. previous versions. -**** Add error on real to non-real output pins (#2690). [Peter Monsson] +**Minor:** -**** Support package imports before parameters in interfaces (#2714). [James Hanlon] +* Better optimize large always block splitting. (#1244) [John Coiner] +* Add new reloop optimization for repetitive assignment compression. +* Support string.atoi and similar methods. (#1289) [Joel Holdsworth] +* Fix internals to be C++ null-pointer-check clean. +* Fix internals to avoid 'using namespace std'. +* Fix Verilation performance issues. (#1316) [John Coiner] +* Fix clocker attributes to not propagate on concats. [John Coiner] +* Fix first clock edge and --x-initial-edge. (#1327) [Rupert Swarbrick] +* Fix compile error on tracing of string arrays. (#1338) [Iztok Jeras] +* Fix number parsing with newline after radix. (#1340) [George Cuan] +* Fix string ?: conditional type resolution. (#1345) [Iztok Jeras] +* Fix duplicate symbol error on generate tri. (#1347) [Tomas Dzetkulic] -**** Support --sanitize in internal tests (#2705). [Yutetsu TAKATSUKASA] -**** Fix passing parameter type instantiations by position number. +Verilator 3.926 2018-08-22 +========================== -**** Fix DPI open array handling issues. +**Minor:** -**** Fix error when dotted refers to missing module (#2095). [Alexander Grobman] +* Add OBJCACHE envvar support to examples and generated Makefiles. +* Change MODDUP errors to warnings. (#1969) [Marshal Qiao] +* Fix define argument stringification (`"), broke since 3.914. [Joe DErrico] +* Fix to ignore Unicode UTF-8 BOM sequences. (#1967) [HyungKi Jeong] +* Fix std:: build error. (#1322) +* Fix function inlining inside certain while loops. (#1330) [Julien Margetts] -**** Fix little endian packed array counting (#2499). [phantom-killua] -**** Fix showing reference locations for BLKANDNBLK (#2170). [Yuri Victorovich] +Verilator 3.924 2018-06-12 +========================== -**** Fix genblk naming to match IEEE (#2686). [tinshark] +**Minor:** -**** Fix VPI memory word indexing (#2695). [Marlon James] +* Renamed --profile-cfuncs to --prof-cfuncs. +* Report interface ports connected to wrong interface. (#1294) [Todd Strader] +* When tracing, use scalars on single bit arrays to appease vcddiff. +* Fix parsing "output signed" in V2K port list, msg2540. [James Jung] +* Fix parsing error on bad missing #. (#1308) [Dan Kirkham] +* Fix $clog2 to be in verilog 2005. (#1319) [James Hutchinson] -**** Fix vpiLeftRange on little-endian memories (#2696). [Marlon James] -**** Fix VPI module tree (#2704). [Todd Strader] +Verilator 3.922 2018-03-17 +========================== -**** Fix vpi_release_handle to be called implicitly per IEEE (#2706). +**Major:** -**** Fix to allow inheriting 'VerilatedVcdFile' class. (#2720) [HyungKi Jeong] +* Support IEEE 1800-2017 as default language. -**** Fix $urandom_range maximum value (#2723). [Nandu Raj] +**Minor:** -**** Fix tracing empty sc module (#2729). +* Support trig functions ($sin() etc). (#1281) [Patrick Stewart] +* Support calling system functions as tasks. (#1285) [Joel Holdsworth] +* Support assert properties. (#785) (#1290) [John Coiner, et al] +* Support $writememh. [John Coiner] +* Add --no-debug-leak to reduce memory use under debug. [John Coiner] +* Fix severe runtime performance bug in certain foreach loops. [John Coiner] +* On convergence errors, show activity. [John Coiner] +* Fix GCC 8.0 issues. (#1273) +* Fix pullup/pulldowns on bit selects. (#1274) [Rob Stoddard] +* Fix verilator_coverage --annotate-min. (#1284) [Tymoteusz Blazejczyk] +* Fix quoting of quoted arguments. [John Coiner] -**** Fix generate for unrolling to be signed (#2730). [yanx21] -**** Fix to emit timescale in hierarchical blocks (#2735). [Yutetsu TAKATSUKASA] +Verilator 3.920 2018-02-01 +========================== -**** Fix to ignore coverage on real ports (#2741) (#2745). [Paul Wright] +**Announcement:** +* Moving forward, use the git "stable" branch to track the latest release, + and git "v#.###" tags for specific releases. +**Minor:** + +* Support 'assume' similar to 'assert'. (#1269) [Dan Gisselquist] +* Remove c++filt. (#1265) [Stefan Wallentowitz] +* Fix tracing example file output. (#1268) [Enzo Chi] +* Fix gate optimization out of memory, add --gate-stmts. (#1260) [Alex Solomatnikov] +* Fix compile error on public real parameters by suppressing. (#1261) [Alex Solomatnikov] +* Fix input-only tristate comparisons. (#1267) [Alexis G] +* Fix missing edge type in xml output. (#1955) [Alexis G] +* Fix compile error with --public and interface bind. (#1264) [Alexis G] -* Verilator 4.106 2020-12-02 -** Change -sv option to select 1800-2017 instead of 1800-2005. +Verilator 3.918 2018-01-02 +========================== -*** Check for proper 'local' and 'protected' (#2228). +**Minor:** -*** Support $random and $urandom seeds. +* Workaround GCC/clang bug with huge compile times. (#1248) +* Support DPI open arrays. (#909) (#1245) [David Pierce, Victor Besyakov] +* Add INFINITELOOP warning. (#1254) [Alex Solomatnikov] +* Support > 64 bit decimal $display. +* Support DPI time and svLogicVal. [Victor Besyakov] + Note older version incorrectly assumed svBitVal even for logicals. +* Support string len() method. [Victor Besyakov] +* Add error if always_comb has sensitivity list. [Arjen Roodselaar] +* Fix SystemC 2.3.2 compile error. (#1251) [Tymoteusz Blazejczyk] +* Fix modport outputs being treated as inputs. (#1246) [Jeff Bush] +* Fix false ALWCOMBORDER on interface references. (#1247) [Josh Redford] +* Fix constant propagation across DPI imports of inout strings. [Victor Besyakov] +* Fix resolving inline nested interface names. (#1250) [Arjen Roodselaar] +* Fix GCC false warning on array bounds. (#2386) -*** Support $monitor and $strobe. -*** Support complex function arguments. +Verilator 3.916 2017-11-25 +========================== -*** Support 'super'. +**Minor:** -*** Support 'with item.index'. +* Support self-recursive modules. (#659) [Sean Moore, et al] +* Support $error/$warning in elaboration time blocks. +* Support $size/$bits/etc on type references. +* Add error when driving input-only modport. (#1110) [Trevor Elbourne] +* Add BSSPACE and COLONPLUS lint warnings. +* Detect MSB overflow when under VL_DEBUG. (#1238) [Junyi Xi] +* Add data types to --xml. [Rui Terra] +* Fix partial slicing with pattern assignments. (#991) [Johan Bjork] +* Fix false unused warning on interfaces. (#1241) [Laurens van Dam] +* Fix error on "unique case" with no cases. +* Fix MacOS portability. (#1232) [Jeff Bush] -**** Fix the default GNU Make executable name on FreeBSD (#2553). [Yuri Victorovich] -**** Fix trace signal names getting hashed (#2643). [Barbara Gigerl] +Verilator 3.914 2017-10-14 +========================== -**** Fix unpacked array parameters near functions (#2639). [Anderson Ignacio da Silva] +**Major:** -**** Fix access to non-overridden base class variable (#2654). [Tobias Rosenkranz] +* Add new examples/ directory with appropriate examples. This replaces the + old test_c and test_sc directories. +**Minor:** -* Verilator 4.104 2020-11-14 +* Add --getenv option for simplifying Makefiles. +* Add --x-initial option for specifying initial value assignment behavior. +* Add --no-relative-cfuncs and related default optimization. (#1224) [John Coiner] +* Add /*verilator tag*/ for XML extraction applications. [Chris Randall] +* The internal test_verilated test directory is moved to be part of test_regress. +* The experimental VL_THREADED setting (only, not normal mode) now requires C++11. +* Fix over-aggressive inlining. (#1223) [John Coiner] +* Fix Ubuntu 17.10 issues. (#1223 partial). [John Coiner] +* Fix compiler warning when WIDTH warning ignored on large compare. +* Fix memory leak in VerilatedVcd dumps. (#1222 partial) [Shareef Jalloq] +* Fix unnecessary Vdly variables. (#1224 partial) [John Coiner] +* Fix conditional slices and add related optimizations. +* Fix \`\` expansion of `defines. (#1225) (#1227) (#1228) [Odd Magne Reitan] +* Fix -E duplicating output. (#1226) [Odd Magne Reitan] +* Fix float-conversion warning. (#1229) [Robert Henry] +* Fix MacOS portability. (#1230) (#1231) [Jeff Bush] -*** Support queue and associative array 'with' statements (#2616). -*** Support queue slicing (#2326). +Verilator 3.912 2017-09-23 +========================== -*** Support associative array pattern assignments and defaults. +**Major:** -*** Support static methods and typedefs in classes (#2615). [Krzysztof Bieganski] +* Verilated headers no longer "use namespace std;" + User's code without "std::" prefixes may need "use namespace std;" to compile. -**** Report error on typedef referencing self (#2539). [Cody Piersall] +**Minor:** -**** With --debug, turn off address space layout randomization. +* Support or/and/xor array intrinsic methods. (#1210) [Mike Popoloski] +* Support package export. (#1217) [Usuario Eda] +* Support module port parameters without defaults. (#1213) [Mike Popoloski] +* Add performance information to --stats file. +* Simplify VL_CONST_W macro generation for faster compiles. +* Optimize improvements for Shift-And, and replication constructs. +* Fix ordering of arrayed cell wide connections. (#1202 partial) [Mike Popoloski] +* Fix LITENDIAN warning on arrayed cells. (#1202) [Mike Popoloski] +* Fix enum ranges without colons. (#1204) [Mike Popoloski] +* Fix GCC noreturn compile error. (#1209) [Mike Popoloski] +* Fix constant function default parameters. (#1211) [Mike Popoloski] +* Fix non-colon array of interface modports. (#1212) [Mike Popoloski] +* Fix .name connections on interfaces. (#1214) [Mike Popoloski] +* Fix wide array indices causing compile error. -**** Fix iteration over mutating list bug in VPI (#2588). [Kaleb Barrett] -**** Fix cast width propagation (#2597). [flex-liu] +Verilator 3.910 2017-09-07 +========================== -**** Fix return from callValueCbs (#2589) (#2605). [Marlon James] +**Major:** -**** Fix WIDTH warnings on comparisons with nullptr (#2602). [Rupert Swarbrick] +* SystemPerl mode (-sp-deprecated) has been removed. -**** Fix fault when $fgets, $sscanf, etc used with string (#2604). [Yutetsu TAKATSUKASA] +**Minor:** -**** Fix WIFEXITED missing from MinGW/MSYS2 (#2609). [Jean Berniolles] +* Update keyword warnings to include C++11 and others. -**** Fix queue poping wrong value when otherwise unused (#2512). [nanduraj1] -**** Fix arrays of modport interfaces (#2614). [Thierry Tambe] +Verilator 3.908 2017-08-28 +========================== -**** Fix split_var internal error (#2640) (#2641). [Yutetsu TAKATSUKASA] +**Minor:** +* Support x in $readmem. (#1180) [Arthur Kahlich] +* Support packed struct DPI imports. (#1190) [Rob Stoddard] +* Fix GCC 6 warnings. +* Fix compile error on unused VL_VALUEPLUSARGS_IW. (#1181) [Thomas J Whatson] +* Fix undefined VL_POW_WWI. [Clifford Wolf] +* Fix internal error on unconnected inouts. (#1187) [Rob Stoddard] -* Verilator 4.102 2020-10-15 -**** Support const object new() assignments. +Verilator 3.906 2017-06-22 +========================== -**** Support # as a comment in -f files (#2497). [phantom-killua] +**Minor:** -**** Support 'this' (#2585). [Rafal Kapuscik] +* Support set_time_unit/set_time_precision in C traces. (#1937) +* Fix extract of packed array with non-zero LSB. (#1172) [James Pallister] +* Fix shifts by more than 32-bit numbers. (#1174) [Clifford Wolf] +* Fix power operator on wide constants. (#761) [Clifford Wolf] +* Fix .* on interface pins. (#1176) [Maciej Piechotka] -**** Support defines for FST tracing (#2592). [Markus Krause] -**** Support |=> inside properties (#1292). [Peter Monsson] +Verilator 3.904 2017-05-30 +========================== -**** Fix timescale with --hierarchical (#2554). [Yutetsu TAKATSUKASA] +**Minor:** -**** Fix cmake build with --hierarchical (#2560). [Yutetsu TAKATSUKASA] +* Fix non-cutable ordering loops on clock arrays. (#1009) [Todd Strader] +* Support ports of array of reals. (#1154) [J Briquet] +* Support arrayed parameter overrides. (#1153) [John Stevenson] +* Support $value$plusargs with variables. (#1165) [Wesley Terpstra] +* Support modport access to un-modport objects. (#1161) [Todd Strader] +* Add stack trace when can't optimize function. (#1158) [Todd Strader] +* Add warning on mis-sized literal. (#1156) [Todd Strader] +* Fix interface functions returning wrong parameters. (#996) [Todd Strader] +* Fix non-arrayed cells with interface arrays. (#1153) [John Stevenson] +* Fix --assert with complex case statements. (#1164) [Enzo Chi] -**** Fix -G dropping public indication (#2561). [Andrew Goessling] -**** Fix $urandom_range passed variable (#2563). [nanduraj1] +Verilator 3.902 2017-04-02 +========================== -**** Fix method calls to package class functions (#2565). [Peter Monsson] +**Major:** -**** Fix class wide member display (#2567). [Nandu Raj P] +* Add -FI option to force includes. (#1916) [Amir Gonnen] +* Add --relative-includes. [Rob Stoddard] -**** Fix hierarchical references inside function (#2267) (#2572). [James Pallister] +**Minor:** -**** Fix flushCall for backward compatibility (#2580). [chenguokai] +* Add error on duplicate pattern assignments. (#1145) [Johan Bjork] +* Fix error on improperly widthed default function. (#984) [Todd Strader] +* Fix 2009 localparam syntax, msg2139. [Galen Seitz] +* Fix ugly interface-to-non-interface errors. (#1112) [Johan Bjork] +* Fix LDFLAGS and CFLAGS not preserving order. (#1130) [Olof Kindgren] +* Fix internal error on initializing parameter array. (#1131) [Jie Xu] +* Fix internal error on interface arrays. (#1135) [John Stevenson] +* Fix calling sformatf to display, and elab $displays. (#1139) [Johan Bjork] +* Fix realpath compile issue on MSVC++. (#1141) [Miodrag Milanovic] +* Fix missing error on interface size mismatch. (#1143) [Johan Bjork] +* Fix error on parameters with dotted references. (#1146) [Johan Bjork] +* Fix wreal not handling continuous assign. (#1150) [J Briquet] +* Fix nested structure parameter selects. (#1150) [J Briquet] -**** Fix preprocessor stringify of undefined macro. [Martin Whitaker] +Verilator 3.900 2017-01-15 +========================== -* Verilator 4.100 2020-09-07 +**Major:** -** C++11 or newer compilers are now required. +* Internal code changes for improved compatibility and performance. -** SystemC 2.3.0 or newer (SYSTEMC_VERSION >= 20111121) is now required. +**Minor:** -** Support hierarchical Verilation (#2206). [Yutetsu TAKATSUKASA] +* Support old-style $display($time). (#467) [John Demme] +* With --bbox-unsup, suppress desassign and mixed edges. (#1120) [Galen Seitz] +* Fix parsing sensitivity with &&. (#934) [Luke Yang] +* Fix internal error on double-for loop unrolling. (#1044) [Jan Egil Ruud] +* Fix internal error on unique casez with --assert. (#1117) [Enzo Chi] +* Fix bad code when tracing array of structs. (#1122) [Andrew Bardsley] -**** Support (with limitations) class extern, class extends, virtual class. -**** Support $urandom, $urandom_range without stability. +Verilator 3.890 2016-11-25 +========================== -**** Fix false DECLFILENAME on black-boxed modules (#2430). [Philipp Wagner] +**Minor:** -**** Fix naming of "id : begin" blocks. +* Honor --output-split on coverage constructors. (#1098) [Johan Bjork] +* Fix various issues when making outside of the kit. +* Fix flex 2.6.2 bug. (#1103) [Sergey Kvachonok] +* Fix error on bad interface name. (#1097) [Todd Strader] +* Fix error on referencing variable in parent. (#1099) [Ian Thompson] +* Fix type parameters with low optimization. (#1101) [Stefan Wallentowitz] -**** Fix class constructor error on assignments to const. -**** Fix splitting eval functions with --output-split-cfuncs (#2368). [Geza Lore] +Verilator 3.888 2016-10-14 +========================== -**** Fix queues as class members (#2525). [nanduraj1] +**Major:** -**** Add support for assume property. [Peter Monsson] +* Support foreach. (#1078) [Xuan Guo] -**** Add support for |=> inside properties (#1292). [Peter Monsson] +**Minor:** +* Add --no-decoration to remove output comments, msg2015. [Frederic Requin] +* If VM_PARALLEL_BUILDS=1, use OPT_FAST and OPT_SLOW. [Frederic Requin] + Set VM_DEFAULT_RULES=0 for old behavior. +* Add error on DPI functions > 32 bits. (#1898) [Elliot Mednick] +* Improve Verilation performance on internal strings. (#1896) [Johan Bjork] +* Improve Verilation performance on trace duplicates. (#1090) [Johan Bjork] +* Fix SystemC compiles with VPI. (#1081) [Arthur Kahlich] +* Fix error on wide numbers that represent shifts, msg1991. (#1088) [Mandy Xu] -* Verilator 4.040 2020-08-15 -** Version 4.040 is planned to be the final version that will - support pre-C++11 compilers. Please move to C++11 or newer compilers. +Verilator 3.886 2016-07-30 +========================== -*** Fix arrayed interfaces, broke in 4.038 (#2468). [Josh Redford] +**Minor:** -**** Support $stable, $rose and $fell. (#2148) (#2501) [Peter Monsson] +* Fix enum values of 11-16 bits wide using .next/.prev. (#1062) [Brian Flachs] +* Fix false warnings on non-power-2 enums using .next/.prev. +* Fix comparison of unpacked arrays. (#1071) [Andrew Bardsley] +* Fix compiler warning in GCC 6. [David Horton] -**** Support simple function localparams (#2461). [James Hanlon] -**** Miscellaneous parsing error changes towards UVM support. +Verilator 3.884 2016-05-18 +========================== -**** Fix arrayed interfaces (#2469). [Josh Redford] +**Major:** -**** Fix protect lib VCS warning. (#2479) [Julien Margetts] +* Support parameter type. (#376) [Alan Hunter, et al] +* Support command-line -G/+pvalue param overrides. (#1045) [Stefan Wallentowitz] +* Add --l2-name option for controlling "v" naming. +* The default l2 scope name is now the same as the top-level module. (#1050) + Use "--l2-name v" for the historical behavior. -**** Fix combining different-width parameters (#2484). [abirkmanis] +**Minor:** -**** Fix protect-lib without sequential logic (#2492). [Yutetsu TAKATSUKASA] +* Fix --output-split of constructors. (#1035) [Johan Bjork] +* Fix removal of empty packages, modules and cells. (#1034) [Johan Bjork] +* Fix core dump on Arch Linux/GCC 6.1.1. (#1058) [Jannis Harder] +* Fix $value$plusargs to string. (#1880) [Frederic Requin] -**** Fix V3Unknown from running with flat XML output (#2494). [James Hanlon] -**** Fix non-32 bit conversion to float (#2495). [dsvf] +Verilator 3.882 2016-03-01 +========================== -**** Fix casting non-self-determined subexpressions (#2493). [phantom-killua] +**Minor:** + +* Internal Verilation-time performance enhancements. (#1021) [Johan Bjork] +* Support inlining interfaces. (#1018) [Johan Bjork] +* Support SV strings to readmemh. (#1040) [Stefan Wallentowitz] +* Fix unrolling complicated for-loop bounds. (#677) [Johan Bjork] +* Fix stats file containing multiple unroll entries. (#1020) [Johan Bjork] +* Fix using short parameter names on negative params. (#1022) [Duraid Madina] +* Fix read-after-free error. (#1031) [Johan Bjork] +* Fix elaboration-time display warnings. (#1032) [Johan Bjork] +* Fix crash on very deep function trees. (#1028) [Jonathan Kimmitt] +* Fix slicing mix of big and little-endian. (#1033) [Geoff Barrett] +* Fix pattern assignment width propagation. (#1037) [Johan Bjork] -**** Fix SystemC net names (#2500). [Edgar E. Iglesias] -**** Fix build with Bison 3.7 and newer (#2505). [Rupert Swarbrick] +Verilator 3.880 2015-12-19 +========================== -**** Fix slice of unpacked array (#2506) (#2507). [Yutetsu TAKATSUKASA] +**Minor:** +* Support display %u, %v, %p, %z. (#989) [Johan Bjork] +* Fix real parameters causing bad module names. (#992) [Johan Bjork] +* Fix size-changing cast on packed struct. (#993) [Johan Bjork] +* Fix function calls on arrayed interface. (#994) [Johan Bjork] +* Fix arrayed interfaces. (#879) (#1001) [Todd Strader] +* Fix constant function assigned to packed structs. (#997) [Johan Bjork] +* Fix interface inside generate. (#998) [Johan Bjork] +* Fix $signed casts under generates. (#999) [Clifford Wolf] +* Fix genvar constant propagation. (#1003) [Johan Bjork] +* Fix parameter constant propagation from package. (#1004) [Johan Bjork] +* Fix array slicing of non-const indexes. (#1006) [Johan Bjork] +* Fix dotted generated array error. (#1005) [Jeff Bush, Johan Bjork] +* Fix error instead of warning on large concat. (#1865) [Paul Rolfe] +* Fix $bitstoreal constant propagation. (#1012) [Jonathan Kimmitt] +* Fix model restore crash. (#1013) [Jason McMullan] +* Fix arrayed instances to unpacked of same size. (#1015) [Varun Koyyalagunta] +* Fix slices of unpacked arrays with non-zero LSBs. +* Fix ternary operation with unpacked array. (#1017) [Varun Koyyalagunta]. + + +Verilator 3.878 2015-11-01 +========================== + +**Major:** -* Verilator 4.038 2020-07-11 +* Add --vpi flag, and fix VPI linkage. (#969) [Arthur Kahlich] +* Support genvar indexes into arrayed cells. (#517) [Todd Strader] +* Support $sformatf. (#977) [Johan Bjork] +* Support elaboration assertions. (#973) [Johan Bjork] +* Support $display with non-format arguments. (#467) [Jamey Hicks] -** Versions 4.038 and 4.040 are planned to be the final versions that will - support pre-C++11 compilers. Please move to C++11 or newer compilers. +**Minor:** + +* Add VerilatedScopeNameMap for introspection. (#966) [Todd Strader] +* Ignore %l in $display. (#983) [Todd Strader] +* Fix very long module names. (#937) [Todd Strader] +* Fix internal error on dotted refs into generates. (#958) [Jie Xu] +* Fix structure parameter constant propagation. (#968) [Todd Strader] +* Fix enum constant propagation. (#970) [Todd Strader] +* Fix mis-optimizing public DPI functions. (#963) [Wei Song] +* Fix package:scope.scope variable references. +* Fix $fwrite to constant stderr/stdout. (#961) [Wei Song] +* Fix struct.enum.name method calls. (#855) [Jonathon Donaldson] +* Fix dot indexing into arrayed inferfaces. (#978) [Johan Bjork] +* Fix crash in commandArgsPlusMatch. (#987) [Jamie Iles] +* Fix error message on missing interface. (#985) [Todd Strader] + + +Verilator 3.876 2015-08-12 +========================== + +**Minor:** + +* Add tracing_on, etc to vlt files. (#932) [Frederic Requin] +* Support extraction of enum bits. (#951) [Jonathon Donaldson] +* Fix MinGW compiler error. (#927) (#929) [Hans Tichelaar] +* Fix .c files to be treated as .cpp. (#930) [Jonathon Donaldson] +* Fix string-to-int space conversion. (#931) [Fabrizio Ferrandi] +* Fix dpi imports inside generates. [Michael Tresidder] +* Fix rounding in trace $timescale. (#946) [Frederic Requin] +* Fix $fopen with SV string. (#947) [Sven Stucki] +* Fix hashed error with typedef inside block. (#948) [Sven Stucki] +* Fix makefile with --coverage. (#953) [Eivind Liland] +* Fix coverage documentation. (#954) [Thomas J Whatson] +* Fix parameters with function parameter arguments. (#952) [Jie Xu] +* Fix size casts as second argument of cast item. (#950) [Jonathon Donaldson] + + +Verilator 3.874 2015-06-06 +========================== + +**Minor:** + +* Add pkg-config .pc file. (#919) [Stefan Wallentowitz] +* Fix installing missing manpages. (#908) [Ahmed El-Mahmoudy] +* Fix sign extension in large localparams. (#910) [Mike Thyer] +* Fix core dump in sync-async warnings. (#911) [Sebastian Dressler] +* Fix truncation warning with -pins-bv. (#912) [Alfonso Martinez] +* Fix Cygwin uint32 compile. (#914) [Matthew Barr] +* Fix preprocessing stringified newline escapes. (#915) [Anton Rapp] +* Fix part-select in constant function. (#916) [Andrew Bardsley] +* Fix width extension on mis-width ports. (#918) [Patrick Maupin] +* Fix width propagation on sized casts. (#925) [Jonathon Donaldson] +* Fix MSVC++ compiler error. (#927) [Hans Tichelaar] + + +Verilator 3.872 2015-04-05 +========================== + +**Minor:** + +* Add VerilatedVcdFile to allow real-time waveforms. (#890) [HyungKi Jeong] +* Add --clk and related optimizations. (#1840) [Jie Xu] +* Fix order of C style arrays. [Duraid Madina] +* Add --dump-treei-. (#894) [Jie Xu] +* Fix comma-instantiations with parameters. (#884) [Franck Jullien] +* Fix SystemC arrayed bit vectors. (#886) [David Poole] +* Fix compile error on MinGW. (#887) [HyungKi Jeong] + + +Verilator 3.870 2015-02-12 +========================== + +**Minor:** + +* Suppress COMBDLY when inside always_latch. (#864) [Iztok Jeras] +* Support cast operator with expression size. (#865) [Iztok Jeras] +* Add warning on slice selection out of bounds. (#875) [Cong Van Nguyen]. +* Fix member select error broke in 3.868. (#867) [Iztok Jeras] +* Fix $sccanf from string. (#866) [David Pierce] +* Fix VM_PARALLEL_BUILDS broke in 3.868. (#870) [Hiroki Honda] +* Fix non-ANSI modport instantiations. (#868) [Kevin Thompson] +* Fix UNOPTFLAT change detect on multidim arrays. (#872) [Andrew Bardsley] +* Fix slice connections of arrays to ports. (#880) [Varun Koyyalagunta] +* Fix mis-optimizing gate assignments in unopt blocks. (#881) [Mike Thyer] +* Fix sign extension of pattern members. (#882) [Iztok Jeras] +* Fix clang compile warnings. + + +Verilator 3.868 2014-12-20 +========================== + +**Major:** + +* New verilator_coverage program added to replace SystemPerl's vcoverage. +* PSL support was removed, please use System Verilog assertions. +* SystemPerl mode is deprecated and now untested. + +**Minor:** + +* Support enum.first/name and similar methods. (#460) (#848) +* Add 'string' printing and comparisons. (#746) (#747) etc. +* Inline C functions that are used only once. (#1838) [Jie Xu] +* Fix tracing SystemC signals with structures. (#858) [Eivind Liland] + Note that SystemC traces will no longer show the signals + in the wrapper, they can be seen one level further down. +* Add --stats-vars. (#851) [Jeremy Bennett] +* Fix bare generates in interfaces. (#789) [Bob Newgard] +* Fix underscores in real literals. (#863) [Jonathon Donaldson] + + +Verilator 3.866 2014-11-15 +========================== + +**Minor:** + +* Fix +define+A+B to define A and B to match other simulators. (#847) [Adam Krolnik] +* Add optimization of wires from arrayed cells. (#1831) [Jie Xu] +* Add optimization of operators between concats. (#1831) [Jie Xu] +* Add public enums. (#833) [Jonathon Donaldson] +* Trace_off now operates on cells. (#826) [Lane Brooks] +* Fix public parameters in unused packages. (#804) [Jonathon Donaldson] +* Fix select when partially out-of-bound. (#823) [Cliffort Wolf] +* Fix generate unrolling with function call. (#830) [Steven Slatter] +* Fix cast-to-size context-determined sizing. (#828) [Geoff Barrett] +* Fix not tracing modules following primitives. (#837) [Jie Xu] +* Fix trace overflow on huge arrays. (#834) [Geoff Barrett] +* Fix quoted comment slashes in defines. (#845) [Adam Krolnik] + + +Verilator 3.864 2014-09-21 +========================== + +**Minor:** + +* Support power operator with real. (#809) [Jonathon Donaldson] +* Improve verilator_profcfunc time attributions. [Jonathon Donaldson] +* Fix duplicate anonymous structures in $root. (#788) [Bob Newgard] +* Fix mis-optimization of bit-swap in wide signal. (#800) [Jie Xu] +* Fix error when tracing public parameters. (#722) [Jonathon Donaldson] +* Fix dpiGetContext in dotted scopes. (#740) [Geoff Barrett] +* Fix over-shift structure optimization error. (#803) [Jeff Bush] +* Fix optional parameter keyword in module #(). (#810) [Iztok Jeras] +* Fix $warning/$error multi-argument ordering. (#816) [Jonathon Donaldson] +* Fix clang warnings. (#818) [Iztok Jeras] +* Fix string formats under deep expressions. (#820) [Iztok Jeras] + + +Verilator 3.862 2014-06-10 +========================== + +**Minor:** + +* Using command line -Wno-{WARNING} now overrides file-local lint_on. +* Add -P to suppress `line and blanks with preprocessing. (#781) [Derek Lockhart] +* Support SV 2012 package import before port list. +* Change SYMRSVDWORD to print as warning rather than error. +* Fix seg-fault with variable of parameterized interface. (#692) [Jie Xu] +* Fix false name conflict on cells in generate blocks. (#749) [Igor Lesik] +* Fix pattern assignment to basic types. (#767) [Jie Xu] +* Fix pattern assignment to conditionals. (#769) [Jie Xu] +* Fix shift corner-cases. (#765) (#766) (#768) (#772) (#774) (#776) [Clifford Wolf] +* Fix C compiler interpreting signing. (#773) [Clifford Wolf] +* Fix late constant division by zero giving X error. (#775) [Clifford Wolf] +* Fix gate primitives with arrays and non-arrayed pins. +* Fix DETECTARRAY error on packed arrays. (#770) [Jie Xu] +* Fix ENDLABEL warnings on escaped identifiers. +* Fix string corruption. (#780) [Derek Lockhart] + + +Verilator 3.860 2014-05-11 +========================== + +**Major:** + +* PSL is no longer supported, please use System Verilog assertions. +* Support '{} assignment pattern on arrays. (#355) +* Support streaming operators. (#649) [Glen Gibb] +* Fix expression problems with -Wno-WIDTH. (#729) (#736) (#737) (#759) + Where WIDTH warnings were ignored this might result in different + warning messages and results, though it should better match the spec. + [Clifford Wolf] + +**Minor:** + +* Add --no-trace-params. +* Add assertions on 'unique if'. (#725) [Jeff Bush] +* Add PINCONNECTEMPTY warning. [Holger Waechtler] +* Support parameter arrays. (#683) [Jeremy Bennett] +* Documentation fixes. (#723) [Glen Gibb] +* Support {} in always sensitivity lists. (#745) [Igor Lesik] +* Fix begin_keywords "1800+VAMS". (#1806) +* Fix tracing of package variables and real arrays. +* Fix tracing of packed arrays without --trace-structs. (#742) [Jie Xu] +* Fix missing coverage line on else-if. (#727) [Sharad Bagri] +* Fix modport function import not-found error. +* Fix power operator calculation. (#730) (#735) [Clifford Wolf] +* Fix reporting struct members as reserved words. (#741) [Chris Randall] +* Fix change detection error on unions. (#758) [Jie Xu] +* Fix -Wno-UNOPTFLAT change detection with 64-bits. (#762) [Clifford Wolf] +* Fix shift-right optimization. (#763) [Clifford Wolf] +* Fix Mac OS-X test issues. [Holger Waechtler] +* Fix C++-2011 warnings. -*** Support VPI access to parameters and localparam. [Ludwig Rogiers] -*** Support parsing (not elaboration, yet) of UVM. +Verilator 3.856 2014-03-11 +========================== -**** Add new UNSUPPORTED error code to replace most previous Unsupported: messages. +**Minor:** -**** With --bbox-unsup continue parsing on many (not all) UVM constructs. +* Support case inside. (#708) [Jan Egil Ruud] +* Add parameters into trace files. (#706) [Alex Solomatnikov] +* Fix parsing "#0 'b0". (#256) +* Fix array bound checks on real variables. +* Fix --skip-identical mis-detecting on OS-X. (#707) +* Fix missing VL_SHIFTRS_IQI with WIDTH warning. (#714) [Fabrizio Ferrandi] +* Fix signed shift right optimization. (#715) [Fabrizio Ferrandi] +* Fix internal error on "input x =" syntax error. (#716) [Lane Brooks] +* Fix slice extraction from packed array. (#717) [Jan Egil Ruud] +* Fix inside statement EQWILD error. (#718) [Jan Egil Ruud] -**** Support for-loop increments with commas. -**** Support $swrite with arbitrary arguments. +Verilator 3.855 2014-01-18 +========================== -**** Support $writememb (#2450). [Fan Shupei] +**Minor:** -**** Fix OS X, Free BSD, and -m32 portability issues. [Geza Lore] +* Support modport import. (#696) [Jeremy Bennett] +* Add --trace-structs to show struct names. (#673) [Chris Randall] +* Fix tracing of packed structs. (#705) [Jie Xu] +* Fix --lint-only with MinGW. (#1813) [HyungKi Jeong] +* Fix some delayed assignments of typedefed unpacked arrays. +* Fix wire declarations with size and not range. (#466) [Alex Solomatnikov] +* Fix parameter pin vs. normal pin error. (#704) [Alex Solomatnikov] -**** Fix to flush FST trace on termination due to $stop or assertion failure. -**** Fix part select error when multipling by power-of-two (#2413). [Conor McCullough] +Verilator 3.854 2013-11-26 +========================== -**** Fix division exception (#2460) [Kuoping Hsu] +**Minor:** +* Add UNPACKED warning to convert unpacked structs. [Jeremy Bennett] +* Add --compiler clang to work around compiler bug. (#694) [Stefan Ludwig] +* Support vpi_get of vpiSuppressVal. (#687) [Varun Koyyalagunta] +* Support vpi_get_time. (#688) [Varun Koyyalagunta] +* Fix evaluation of chained parameter functions. (#684) [Ted Campbell] +* Fix enum value extension of '1. +* Fix multiple VPI variable callbacks. (#679) [Rich Porter] +* Fix vpi_get of vpiSize. (#680) [Rich Porter] +* Fix vpi_remove_cb inside callback. (#689) [Varun Koyyalagunta] +* Fix crash with coverage of structures. (#691) [Eivind Liland] +* Fix array assignment from const var. (#693) [Jie Xu] -* Verilator 4.036 2020-06-06 -** OPT_FAST is now -Os by default. See the BENCHMARKING & OPTIMIZATION part - of the manual if you experience issues with compilation speed. +Verilator 3.853 2013-09-30 +========================== -*** Configure now enables SystemC if it is installed as a system headers, - e.g. with 'apt-get install systemc-dev'. +**Minor:** -*** Add --waiver-output flag that writes a verilator config file (.vlt) with - waivers to the warnings emitted during a Verilator run. +* Add --no-order-clock-delay to work around #613. [Charlie Brej] -*** Support verilator_coverage --write-info for lcov HTML reports. - Line Coverage now tracks all statement lines, not just branch lines. -*** --output-split is now on by default. VM_PARALLEL_BUILDS is set by - default iff the --output-split caused an actual file split to occur. - --output-split-cfuncs and --output-split-ctrace now default to the - value of --output-split. These changes should improve build times of - medium and large designs with default options. User makefiles may - require changes. +Verilator 3.852 2013-09-29 +========================== -*** The run-time library is now compiled with -Os by default. (#2369, #2373) +**Minor:** -**** Support multi channel descriptor I/O (#2190) [Stephen Henry] +* Support named function and task arguments. [Chris Randall] +* Report SELRANGE warning for non-generate if. (#675) [Roland Kruse] +* Fix ordering of $fgetc. (#1808) [Frederic Requin] +* Fix --output-split-cfunc to count internal functions. [Chris Randall] +* Fix crash on 32-bit Ubuntu. (#670) [Mark Jackson Pulver] -**** Support $countbits. (#2287) [Yossi Nivin] -**** Support $isunbounded and parameter $. (#2104) +Verilator 3.851 2013-08-15 +========================== -**** Support unpacked array .sum and .product. +**Minor:** -**** Support prefix/postfix increment/decrement. (#2223) [Maciej Sobkowski] +* Fix ordering of clock enables with delayed assigns. (#613) [Jeremy Bennett] +* Fix vpi_iterate on memory words. (#655) [Rich Porter] +* Fix final duplicate declarations when non-inlined. (#661) [Charlie Brej] +* Fix interface ports with comma lists. (#1779) [Ed Lander] +* Fix parameter real conversion from integer. +* Fix clang warnings. (#668) [Yutetsu Takatsukasa] -**** Fix FST tracing of little bit endian signals. [Geza Lore] -**** Fix +: and -: on unpacked arrays. (#2304) [engr248] +Verilator 3.850 2013-06-02 +========================== -**** Fix $isunknown with constant Z's. +**Major:** -**** Fix queues and dynamic array wide ops. (#2352) [Vassilis Papaefstathiou] +* Support interfaces and modports. (#102) [Byron Bradley, Jeremy Bennett] +**Minor:** -* Verilator 4.034 2020-05-03 +* Duplicate clock gate optimization on by default. (#621) +* Fix arrayed input compile error. (#645) [Krzysztof Jankowski] +* Fix GCC version runtime changes. (#651) [Jeremy Bennett] +* Fix packed array select internal error. (#652) [Krzysztof Jankowski] -** Add simplistic class support with many restrictions, see manual. (#377) -** Support IEEE time units and time precisions. (#234) - Includes `timescale, $printtimescale, $timeformat. - VL_TIME_MULTIPLIER, VL_TIME_PRECISION, VL_TIME_UNIT have been removed - and the time precision must now match the SystemC time precision. To - get closer behavior to older versions, use e.g. --timescale-override - "1ps/1ps". +Verilator 3.847 2013-05-11 +========================== -** Add --build to call make automatically. (#2249) [Yutetsu TAKATSUKASA] +**Minor:** -** Configuring with ccache present now defaults to using it; see OBJCACHE. +* Add ALWCOMBORDER warning. [KC Buckenmaier] +* Add --pins-sc-uint and --pins-sc-biguint. (#638) [Alex Hornung] +* Support "signal[vec]++". +* Fix simulation error when inputs and MULTIDRIVEN. (#634) [Ted Campbell] +* Fix module resolution with __. (#631) [Jason McMullan] +* Fix packed array non-zero right index select crash. (#642) [Krzysztof Jankowski] +* Fix nested union crash. (#643) [Krzysztof Jankowski] -** Fix DPI import/export to be standard compliant. (#2236) [Geza Lore] -** Add --trace-threads for general multithreaded tracing. (#2269) [Geza Lore] +Verilator 3.846 2013-03-09 +========================== -*** Add --flatten for use with --xml-only. (#2270) [James Hanlon] +**Major:** -**** Greatly improve FST/VCD dump performance (#2244) (#2246) (#2250) (#2257) [Geza Lore] +* IEEE 1800-2012 is now the default language. This adds 4 new keywords + and updates the svdpi.h and vpi_user.h header files. +* Add --report-unoptflat. (#611) [Jeremy Bennett] -**** Support $ferror, and $fflush without arguments. (#1638) +**Minor:** -**** Support event data type (with some restrictions). +* Add duplicate clock gate optimization. (#1772) [Varun Koyyalagunta] + Disabled unless -OD or -O3 used, please try it as may get some + significant speedups. +* Support pattern assignment features. (#616) (#617) (#618) [Ed Lander] +* Support bind in $unit. (#602) [Ed Lander] +* Support '() sized casts. (#628) [Ed Lander] +* Fix wrong dot resolution under inlining. [Art Stamness] +* Fix DETECTARRAY on packed structures. (#610) [Jeremy Bennett] +* Fix LITENDIAN on unpacked structures. (#614) [Wai Sum Mong] +* Fix 32-bit OS VPI scan issue. (#615) [Jeremy Bennett, Rich Porter] +* Fix opening a VerilatedVcdC file multiple times. (#1774) [Frederic Requin] +* Fix UNOPTFLAT circular array bounds crossing. (#630) [Jie Xu] -**** Support $root. (#2150) [Keyi Zhang] -**** Add error if use SystemC 2.2 and earlier (pre-2011) as is deprecated. +Verilator 3.845 2013-02-04 +========================== -**** Fix build of fast path tracing code to use OPT_FAST. (#2245) [Geza Lore] +**Minor:** -**** Fix arrayed instances connecting to slices. (#2263) [Don/engr248] +* Fix nested packed arrays and struct. (#600) [Jeremy Bennett] + Packed arrays are now represented as a single linear vector in + Verilated models. This may affect packed arrays that are public or + accessed via the VPI. +* Support wires with data types. (#608) [Ed Lander] +* Support bind, to module names only. (#602) [Ed Lander] +* Support VPI product info, warning calls, etc. (#588) [Rick Porter] +* Support $left, $right and related functions. (#448) [Iztok Jeras] +* Support inside expressions. +* Define SYSTEMVERILOG, SV_COV_START and other IEEE mandated predefines. +* Fix pin width mismatch error. (#595) [Alex Solomatnikov] +* Fix implicit one bit parameter selection. (#603) [Jeremy Bennett] +* Fix signed/unsigned parameter misconversion. (#606) [Jeremy Bennett] +* Fix segfault on multidimensional dotted arrays. (#607) [Jie Xu] +* Fix per-bit array output connection error. (#414) [Jan Egil Ruud] +* Fix package logic var compile error. +* Fix enums with X values. -**** Fix error on unpacked connecting to packed. (#2288) [Joseph Shaker] -**** Fix logical not optimization with empty begin. (#2291) [Baltazar Ortiz] +Verilator 3.844 2013-01-09 +========================== -**** Fix reduction OR on wide data, broke in v4.026. (#2300) [Jack Koenig] +**Minor:** -**** Fix clock enables with bit-extends. (#2299) [Marco Widmer] +* Support "unsigned int" DPI import functions. (#1770) [Alex Lee] +* Fix package resolution of parameters. (#586) [Jeremy Bennett] +* Fix non-integer vpi_get_value. (#587) [Rich Porter] +* Fix task inlining under $display and case. (#589) (#598) [Holger Waechtler] +* Fix package import of non-localparam parameter. (#474) (#591) [Jeremy Bennett] +* Fix package import of package imports, partial #592. [Jeremy Bennett] +* Fix package import preventing local var. (#599) [Jeremy Bennett] +* Fix array extraction of implicit vars. (#601) [Joe Eiler] -**** Fix MacOs Homebrew by removing default LIBS. (#2298) [Ryan Clarke] +Verilator 3.843 2012-12-01 +========================== -* Verilator 4.032 2020-04-04 +**Minor:** -*** Add column numbers to errors and warnings. +* Add +1364-1995ext and similar language options. (#532) [Jeremy Bennett] +* Fix mis-optimized identical submodule subtract. (#581) [Charlie Brej] +* Fix crash on dotted references into dead modules. (#583) [Jeremy Bennett] +* Fix compile issues on MSVCC. (#571) (#577) [Amir Gonnen] +* Fix --debug overriding preceding --dump-treei. (#580) [Jeremy Bennett] -*** Add GCC 9-style line number prefix when showing source text for errors. -*** Add setting VM_PARALLEL_BUILDS=1 when using --output-split. (#2185) +Verilator 3.842 2012-11-03 +========================== -*** Change --quiet-exit to also suppress 'Exiting due to N errors'. +**Minor:** -**** Suppress REALCVT for whole real numbers. +* Add -x-initial-edge. (#570) [Jeremy Bennett] +* Fix parameter pins interspersed with cells broke in 3.840. [Bernard Deadman] +* Fix large shift error on large shift constants. [David Welch] +* Fix $display mangling on GCC 4.7 and speed up. (#1765) (#373) (#574) [R Diez] +* Fix array of struct references giving false error. (#566) [Julius Baxter] +* Fix missing var access functions when no DPI. (#572) [Amir Gonnen] +* Fix name collision on unnamed blocks. (#567) [Chandan Egbert] +* Fix name collision on task inputs. (#569) [Chandan Egbert] + + +Verilator 3.841 2012-09-03 +========================== -**** Support split_var in vlt files. (#2219) [Marco Widmer] +**Major:** -**** Fix parameter type redeclaring a type. (#2195) [hdzhangdoc] +* Add --savable to support model save/restore. [Jeremy Bennett] -**** Fix VCD open with empty filename. (#2198) [Julius Baxter] +**Minor:** -**** Fix packages as enum base types. (#2202) [Driss Hafdi] +* Support '{} assignment pattern on structures, part of #355. +* Fix double-deep parameter cell WIDTHs. (#541) [Hiroki Honda] +* Fix imports under multiple instantiated cells. (#542) [Alex Solomatnikov] +* Fix defparam in generate broke in 3.840. (#543) [Alex Solomatnikov] +* Fix duplicate begin error broke in 3.840. (#548) [Alex Solomatnikov] +* Fix triangle symbol resolution error broke in 3.840. (#550) [Ted Campbell] -**** Fix duplicate typedefs in generate for. (#2205) [hdzhangdoc] -**** Fix MinW portability. (#2114) [Sean Cross] +Verilator 3.840 2012-07-31 Beta +=============================== + +**Major:** -**** Fix assertions with unique case inside. (#2199) [hdzhangdoc] +* Rewrote tristate handling; supports tri0, tri1, tristate bit selects, + concatenates and pullup/pulldowns. (#395) (#56) (#54) (#51) + [Alex Solomatnikov, Lane Brooks, et al] +* Support packed structures and unions. (#181) + Note this was a major internal change that may lead to some instability. -**** Fix implicit conversion of floats to wide integers. +**Minor:** +* Support tri0 and tri1. (#462) [Alex Solomatnikov] +* Support nmos and pmos. (#488) [Alex Solomatnikov] +* Add INITIALDLY warning on initial assignments. (#478) [Alex Solomatnikov] +* Add PINMISSING and PINNOCONNECT lint checks. +* Add --converge-limit option. +* Fix generate operators not short circuiting. (#413) [by Jeremy Bennett] +* Fix parameters not supported in constant functions. (#474) [Alex Solomatnikov] +* Fix duplicate warnings/errors. (#516) [Alex Solomatnikov] +* Fix signed extending biops with WIDTH warning off. (#511) [Junji Hashimoto] +* Fix ITOD internal error on real conversions. (#491) [Alex Solomatnikov] +* Fix input and real loosing real data type. (#501) [Alex Solomatnikov] +* Fix imports causing symbol table error. (#490) [Alex Solomatnikov] +* Fix newlines in radix values. (#507) [Walter Lavino] +* Fix loop error message to report line. (#513) [Jeremy Bennett] +* Fix false UNUSED warning on file system calls. +* Fix GCC 4.7.0 compile warnings. (#530) [Jeremy Bennett] +* Fix svdpi.h compile error on Apple OS. +* Fix compile error under git submodules. (#534) [Aurelien Francillon] -* Verilator 4.030 2020-03-08 -** Add split_var metacomment to assist UNOPTFLAT fixes. (#2066) [Yutetsu TAKATSUKASA] +Verilator 3.833 2012-04-15 +========================== -** Add support for $dumpfile and $dumpvars. (#2126) [Alexander Grobman] +**Minor:** -** Add support for dynamic arrays. (#379) +* Support += and -= in standard for loops. (#463) [Alex Solomatnikov] +* Fix processing unused parametrized modules. (#469) (#470) [Alex Solomatnikov] +* Add SELRANGE as warning instead of error. (#477) [Alex Solomatnikov] +* Add readme.pdf and internal.pdf and doxygen. (#483) [by Jeremy Bennett] +* Fix change detections on arrays. (#364) [John Stevenson, Alex Solomatnikov] +* Fix signed array warning. (#456) [Alex Solomatnikov] +* Fix genvar and begin under generate. (#461) [Alex Solomatnikov] +* Fix real constant parameter functions. (#475) [Alex Solomatnikov] +* Fix and document --gdb option. (#454) [Jeremy Bennett] +* Fix OpenSolaris compile error. [Sanjay Singh] -*** Add +verilator+noassert flag to disable assertion checking. [Tobias Wölfel] -*** Add check for assertOn for asserts. (#2162) [Tobias Wölfel] +Verilator 3.832 2012-03-07 +========================== -*** Add --structs-packed for forward compatibility. +**Minor:** -*** Fix genblk naming with directly nested generate blocks. (#2176) [Alexander Grobman] +* Fix memory delayed assignments from multiple clock domains. [Andrew Ling] +* Support arrayed SystemC I/O pins. [Christophe Joly] +* Report MULTIDRIVEN on memories set in multiple clock domains. +* Report ENDLABEL on mismatching end labels. (#450) [Iztok Jeras] +* Fix expansion of back-slashed escaped macros. (#441) [Alberto Del Rio] +* Fix inheriting real and signed type across untyped parameters. +* Fix core dump with over 100 deep UNOPTFLAT. (#432) [Joe Eiler] +* Fix false command not found warning in makefiles. [Ruben Diez] +* Fix hang when functions inside begin block. [David Welch] +* Fix hang on recursive substitution `defines. (#443) [Alex Solomatnikov] -**** Implement $displayb/o/h, $writeb/o/h, etc. (#1637) -**** Use gcc -Os in examples instead of -O2 for better average performance. +Verilator 3.831 2012-01-20 +========================== -**** Fix undeclared VL_SHIFTR_WWQ. (#2114) [Alex Solomatnikov] +**Major:** +* Support SystemC 2.3.0 prerelease. This requires setting the new + SYSTEMC_INCLUDE and SYSTEMC_LIBDIR variables in place of now + deprecated SYSTEMC and SYSTEMC_ARCH. [Iztok Jeras] -* Verilator 4.028 2020-02-08 +**Minor:** -** Support attributes (public, isolate_assignments, etc.) in configuration files. +* Suppress VARHIDDEN on dpi import arguments. [Ruben Diez] +* Support "generate for (genvar i=0; ...". [David Kravitz] +* Fix dpi exports with > 32 bit but < 64 bit args. (#423) [Chandan Egbert] +* Fix array of instantiations with sub-range output. (#414) [Jeremy Bennett] +* Fix BLKSEQ warnings on variables declared inside always. [Ruben Diez] -** Add -match to lint_off to waive warnings. [Philipp Wagner] -*** Link Verilator binary partially statically. (#2146) [Geza Lore] +Verilator 3.830 2011-11-27 +========================== -*** Verilation speed improvements (#2133) (#2138) [Geza Lore] +**Major:** -*** Support libgoogle-perftools-dev's libtcmalloc if available. (#2137) [Geza Lore] +* With "--language VAMS" support a touch of Verilog AMS. [Holger Waechtler] -*** Support $readmem/$writemem with assoc arrarys. (#2100) [agrobman] +**Minor:** -**** Support type(expression) operator and $typename. (#1650) +* Add sc_bv attribute to force bit vectors. (#402) [by Stefan Wallentowitz] +* Search for user -y paths before default current directory. [Ruben Diez] +* Support constants in sensitivity lists. (#412) [Jeremy Bennett] +* Support $system. [Ruben Diez] +* Support $sscanf with %g. [Holger Waechtler] +* Indicate 'exiting due to errors' if errors, not warnings. [Ruben Diez] +* Fix bad result with if-else-return optimization. (#420) [Alex Solomatnikov] +* Fix reporting not found modules if generate-off. (#403) [Jeremy Bennett] +* Fix $display with %d following %g. [Holger Waechtler] -**** Support left justified $display. (#2101) [Pieter Kapsenberg] -**** Support string character access via indexing. +Verilator 3.824 2011-10-25 +========================== -**** Support enum.next(k) with constant k > 1. (#2125) [Tobias Rosenkranz] +**Minor:** -**** Support parameter access from arrays of interfaces. (#2155) [Todd Strader] +* Fix "always @ (* )". (#403) (#404) [Walter Lavino] +* Add ASSIGNIN as suppressable error. [Jeremy Bennett] +* Fix 3.823 constructor core dump on Debian. (#401) [Ahmed El-Mahmoudy] -**** Add parameter values in XML. #2110. [Pieter Kapsenberg] -**** Add loc column location in XML (replaces fl). (#2122) [Pieter Kapsenberg] +Verilator 3.823 2011-10-20 +========================== -**** Add error on misused define. [Topa Tota] +**Minor:** -**** Add parameter to set maximum signal width. (#2082) [Øyvind Harboe] +* Support $ceil, $floor, etc. [Alex Solomatnikov] +* Add configure options for cc warnings and extended tests. [Ruben Diez] +* Add -Wall reporting ASSIGNDLY on assignment delays. [Ruben Diez] +* Fix UNDRIVEN warnings inside DPI import functions. [Ruben Diez] +* Fix --help output to go to stderr, not stdout. (#397) [Ruben Diez] +* Fix DPI import output of 64 bits. (#398) [Mike Denio] +* Fix DPI import false BLKSEQ warnings. [Alex Solomatnikov] +* Fix MSVC compile warning with trunc/round. (#394) [Amir Gonnen] +* Fix autoconf and Makefile warnings. (#396) [Ruben Diez] -**** Add warning on genvar in normal for loop. (#2143) [yurivict] -**** Fix VPI scope naming for public modules. [Nandu Raj] +Verilator 3.821 2011-09-14 +========================== -**** Fix FST tracing of enums inside structs. [fsiegle] +**Minor:** -**** Fix WIDTH warning on " in assertions. (#2069) [Peter Monsson] +**Minor:** -*** Support string compare, ato*, etc methods. (#1606) [Yutetsu TAKATSUKASA] +* Support bit vectors > 64 bits wide in DPI import and exports. +* Fix out of memory on slice syntax error. (#354) [Alex Solomatnikov] +* Fix error on enum references to other packages. (#339) [Alex Solomatnikov] +* Fix DPI undeclared svBitVecVal compile error. (#346) [Chandan Egbert] +* Fix DPI bit vector compile errors. (#347) (#359) [Chandan Egbert] +* Fix CDCRSTLOGIC report showing endpoint flops without resets. +* Fix compiler warnings on SPARC. (#288) [Ahmed El-Mahmoudy] -**** Support immediate cover statements. -**** Ignore `uselib to end-of-line. (#1634) [Frederic Antonin] +Verilator 3.812 2011-04-06 +========================== -**** Update FST trace API for better performance. +**Minor:** -**** Add vpiTimeUnit and allow to specify time as string. (#1636) [Stefan Wallentowitz] +* Add --trace-max-width and --trace-max-array. (#319) [Alex Solomatnikov] +* Add --Wno-fatal to turn off abort on warnings. [by Stefan Wallentowitz] +* Support ${...} and $(...) env vars in .vc files. [by Stefan Wallentowitz] +* Support $bits(data_type). (#327) [Alex Solomatnikov] +* Support loop unrolling on width mismatches. (#333) [Joe Eiler] +* Support simple cast operators. (#335) [Alex Solomatnikov] +* Accelerate bit-selected inversions. +* Add error on circular parameter definitions. (#329) [Alex Solomatnikov] +* Fix concatenates and vectored bufif1. (#326) [Iztok Jeras] -**** Add error when `resetall inside module (IEEE 2017-22.3). -**** Add cleaner error on version control conflicts in sources. +Verilator 3.811 2011-02-14 +========================== -**** Fix little endian cell ranges. (#1631) [Julien Margetts] +**Minor:** -**** Fix queue issues (#1641) (#1643) [Peter Monsson, Stefan Wallentowitz] +* Report error on duplicated or empty pins. (#321) [Christian Leber] +* Report error on function call output tied to constant. [Bernard Deadman] +* Throw UNUSED/UNDRIVEN only once per net in a parametrized module. +* Fix internal error on functions called as SV tasks. [Bernard Deadman] +* Fix internal error on non-inlined inout pins. [Jeff Winston] +* Fix false BLKSEQ on non-unrolled for loop indexes. [Jeff Winston] +* Fix block comment not separating identifiers. (#311) [Gene Sullivan] +* Fix warnings to point to lowest net usage, not upper level ports. +* Fix error on constants connected to outputs. (#323) [Christian Leber] -**** Fix strcasecmp for windows. (#1651) [Kuba Ober] -**** Fix disable iff in assertions. Closes #1404. [Peter Monsson] +Verilator 3.810 2011-01-03 +========================== -**** Fix huge case statement performance. Closes #1644. [Julien Margetts] +**Major:** -**** Fix tracing -1 index arrays. Closes #2090. [Yutetsu Takatsukasa] +* Add limited support for VPI access to public signals, see docs. +* Add -F option to read relative option files. (#297) [Neil Hamilton] +* Support ++,--,+= etc as standalone statements. [Alex Solomatnikov] +* Add -Wall, -Wwarn-style, -Wno-style to enable code style warnings + that have been added to this release, and disabled by default: +* With --Wall, add BLKSEQ warning on blocking assignments in seq blocks. +* With --Wall, add DECLFILENAME warning on modules not matching filename. +* With --Wall, add DEFPARAM warning on deprecated defparam statements. +* With --Wall, add IFDEPTH warning on deep if statements. +* With --Wall, add INCABSPATH warning on `include with absolute paths. +* With --Wall, add SYNCASYNCNET warning on mixed sync/async reset nets. +* With --Wall, add UNDRIVEN warning on undriven nets. +* With --Wall, add UNUSED warning on unused nets. -**** Fix expand optimization slowing --lint-only. Closes #2091. [Thomas Watts] +**Minor:** -**** Fix %{number}s with strings. #2093. [agrobman] +* When running with VERILATOR_ROOT, optionally find binaries under bin. +* Suppress WIDTH warnings when adding/subtracting 1'b1. +* The VARHIDDEN warning is now disabled by default, use -Wall to enable. -**** Fix shebang breaking some shells. Closes #2067. [zdave] +Verilator 3.805 2010-11-02 +========================== -* Verilator 4.024 2019-12-08 +**Minor:** -** Support associative arrays (excluding [*] and pattern assignments). (#544) +* Add warning when directory contains spaces. (#1705) [Salman Sheikh] +* Fix wrong filename on include file errors. (#289) [Brad Parker] +* Fix segfault on SystemVerilog "output wire foo=0". (#291) [Joshua Wise] +* Fix DPI export name not found. (#1703) [Terry Chen] -** Support queues (excluding {} notation and pattern assignments). (#545) -*** Add +verilator+error+limit to see more assertion errors. [Peter Monsson] +Verilator 3.804 2010-09-20 +========================== + +**Minor:** + +* Support tracing/coverage of underscore signals. (#280) [by Jason McMullan] +* Increase define recursions before error. [Paul Liu] +* On core dump, print debug suggestions. +* Fix preprocessor \`\` of existing base define. (#283) [Usha Priyadharshini] + + +Verilator 3.803 2010-07-10 +========================== -*** Support string.toupper and string.tolower. +**Minor:** -*** Support $rewind and $ungetc. +* Fix preprocessor preservation of newlines across macro substitutions. +* Fix preprocessor stringification of nested macros. +* Fix some constant parameter functions causing crash. (#253) [Nick Bowler] +* Fix do {...} while() not requiring final semicolon. + + +Verilator 3.802 2010-05-01 +========================== -*** Support shortreal as real, with a SHORTREAL warning. +**Minor:** -**** Add -Wpedantic and -Wno-context for compliance testing. +* Support runtime access to public signal names. +* Add /*verilator public_flat_rw*/ for timing-specific public access. +* Fix word size to match uint64_t on -m64 systems. (#238) [Joe Eiler] +* Improve error handling on slices of arrays. (#226) [by Byron Bradley] +* Report errors when extra underscores used in meta-comments. +* Fix bit reductions on multi-packed dimensions. (#227) [by Byron Bradley] +* Fix removing $fscanf if assigned to unused var. (#248) [Ashutosh Das] +* Fix "make install" with configure outside srcdir. [Stefan Wallentowitz] +* Fix loop unroller out of memory; change --unroll-stmts. [Ashutosh Das] +* Fix trace files with empty modules crashing some viewers. +* Fix parsing single files > 2GB. [Jeffrey Short] +* Fix installing data files as non-executable. (#168) [by Ahmed El-Mahmoudy] -**** Add error on redefining preprocessor directives. [Piotr Binkowski] -**** Support $value$plusargs float and shorts. (#1592) (#1619) [Garrett Smith] +Verilator 3.801 2010-03-17 +========================== -**** Fix gate lvalue optimization error. (#831) [Jonathon Donaldson, Driss Hafdi] +**Minor:** -**** Fix color assertion on empty if. (#1604) [Andrew Holme] +* Support "break", "continue", "return". +* Support "`default_nettype none|wire". [Dominic Plunkett] +* Skip SystemC tests if not installed. [Iztok Jeras] +* Fix clock-gates with non-AND complex logic. (#220) [Ashutosh Das] +* Fix flushing VCD buffers on $stop. [Ashutosh Das] +* Fix Mac OS-X compile issues. (#217) [Joshua Wise, Trevor Williams] +* Fix make uninstall. (#216) [Iztok Jeras] +* Fix parameterized defines with empty arguments. -**** Fix for loop missing initializer. (#1605) [Andrew Holme] -**** Fix hang on concat error. (#1608) [Bogdan Vukobratovic] +Verilator 3.800 2010-02-07 +========================== -**** Fix VPI timed callbacks to be one-shot, pull5. [Matthew Ballance] +**Major application visible changes:** -**** Fix // in filenames. (#1610) [Peter Nelson] +* SystemPerl is no longer required for tracing. + Applications must use VerilatedVcdC class in place of SpTraceVcdC. +* SystemVerilog 1800-2009 is now the default language. + Thus "global" etc are now keywords. See the --language option. -**** Fix $display("%p") to be closer to IEEE. +**Major new features:** -**** Fix labels on functions with returns. (#1614) [Mitch Hayenga] +* Support SystemVerilog types "byte", "chandle", "int", "longint", + "shortint", "time", "var" and "void" in variables and functions. +* Support "program", "package", "import" and $unit. +* Support typedef and enum. [by Donal Casey] +* Support direct programming interface (DPI) "import" and "export". + Includes an extension to map user $system PLI calls to the DPI. +* Support assignments of multidimensional slices. (#170) [by Byron Bradley] +* Support multidimensional inputs/outputs. (#171) [by Byron Bradley] +* Support "reg [1:0][1:0][1:0]" and "reg x [3][2]". (#176) [Byron Bradley] +* Support declarations in loop initializers. (#172) [by Byron Bradley] +* Support $test$plusargs and $value$plusargs, but see the docs! +* Support $sformat and $swrite. +* Support 1800-2009 define defaults and `undefineall. +* Add -CFLAGS, -LDFLAGS, .a, .o, and .so options. +* Speed compiles by avoiding including the STL iostream header. + Application programs may need to include it themselves to avoid errors. +* Add experimental clock domain crossing checks. +* Add experimental --pipe-filter to filter all Verilog input. +* Add experimental config files to filter warnings outside of the source. +* Add VARHIDDEN warning when signal name hides module name. +* Support optional cell parenthesis. (#179) [by Byron Bradley] +* Support for-loop i++, ++i, i--, --i. (#175) [by Byron Bradley] +* Support 1800-2009 /*comments*/ in define values. +* Add Makefile VM_GLOBAL_FAST, listing objects needed to link executables. +* Add --bbox-unsup option to black-box unsupported UDP tables. +* Add -Wno-MODDUP option to allow duplicate modules. -**** Fix false unused message on __Vemumtab. (#2061) [Tobias Rosenkranz] +**Bug fixes:** -**** Fix assertion on dotted parameter arrayed function. (#1620) [Rich Porter] +* Fix implicit variable issues. (#196) (#201) [Byron Bradley] +* Fix 'for' variable typing. (#205) [by Byron Bradley] +* Fix tracing with --pins-bv 1. (#195) [Michael S] +* Fix MSVC++ 2008 compile issues. (#209) [Amir Gonnen] +* Fix MinGW compilation. (#184) (#214) [by Shankar Giri, Amir Gonnen] +* Fix Cygwin 1.7.x compiler error with uint32_t. (#204) [Ivan Djordjevic] +* Fix `define argument mis-replacing system task of same name. (#191) +* Fix Verilator core dump on wide integer divides. (#178) [Byron Bradley] +* Fix lint_off/lint_on meta comments on same line as warning. -**** Fix interface reference tracing. (#1595) [Todd Strader] -**** Fix error on unpacked concatenations. (#1627) [Driss Hafdi] +Verilator 3.720 2009-10-26 +========================== +**Major:** -* Verilator 4.022 2019-11-10 +* Support little endian bit vectors ("reg [0:2] x;"). +* Support division and modulus of > 64 bit vectors. [Gary Thomas] -** Add --protect-lib. (#1490) [Todd Strader] +**Minor:** -** Add cmake support. (#1363) [Patrick Stewart] +* Fix writing to out-of-bounds arrays writing element 0. +* Fix core dump with SystemVerilog var declarations under unnamed begins. +* Fix VCD files showing internal flattened hierarchy, broke in 3.714. +* Fix cell port connection to unsized integer causing false width warning. +* Fix erroring on strings with backslashed newlines. (#168) [Pete Nixon] -*** Examples have been renamed. -*** Add --protect-ids to obscure information in objects. (#1521) [Todd Strader] +Verilator 3.714 2009-09-18 +========================== -*** Add --trace-coverage. +**Major:** -*** Add --xml-output. +* Add --bbox-sys option to blackbox $system calls. -*** Support multithreading on Windows. [Patrick Stewart] +**Minor:** -*** Suppress 'command failed' on normal errors. +* Support generate for var++, var--, ++var, --var. +* Improved warning when "do" used as identifier. +* Don't require SYSTEMPERL_INCLUDE if SYSTEMPERL/src exists. [Gary Thomas] +* Fix deep defines causing flex scanner overflows. [Brad Dobbie] +* Fix preprocessing commas in deep parameterized macros. [Brad Dobbie] +* Fix tracing escaped dotted identifiers. (#107) +* Fix $display with uppercase %M. +* Fix --error-limit option being ignored. -*** Support some unpacked arrays in parameters. (#1315) [Marshal Qiao] -*** Add interface port visibility in traces. (#1594) [Todd Strader] +Verilator 3.713 2009-08-04 +========================== -**** Increase case duplicate/incomplete to 16 bit tables. (#1545) [Yossi Nivin] +**Minor:** -**** Support quoted arguments in -f files. (#1535) [Yves Mathieu] +* Support constant function calls for parameters. [many!] +* Support SystemVerilog "logic". (#101) [by Alex Duller] +* Name SYMRSVDWORD error, and allow disabling it. (#103) [Gary Thomas] +* Fix escaped preprocessor identifiers. (#106) [Nimrod Gileadi] -**** Optimize modulus by power-of-two constants, and masked conditionals. -**** Fix detecting missing reg types. (#1570) [Jacko Dirks] +Verilator 3.712 2009-07-14 +========================== -**** Fix multithreaded yield behavior when no work. [Patrick Stewart] +**Major:** -**** Fix bad-syntax crashes. (#1548, #1550-#1553, #1557-#1560, #1563, - #1573-#1577, #1579, #1582-#1591) [Eric Rippey] +* Patching SystemC is no longer required to trace sc_bvs. -**** Fix false CMPCONST/UNSIGNED warnings on "inside". (#1581) [Mitch Hayenga] +**Minor:** +* Add verilator --pins-uint8 option to use sc_in. +* Add verilator -V option, to show verbose version. +* Add BLKLOOPINIT error code, and describe --unroll-count. [Jeff Winston] +* Support zero-width constants in concatenations. [Jeff Winston] +* On WIDTH warnings, show variable name causing error. [Jeff Winston] -* Verilator 4.020 2019-10-06 -*** Add --public-flat-rw. (#1511) [Stefan Wallentowitz] +Verilator 3.711 2009-06-23 +========================== -*** Support $fseek, $ftell, $frewind. (#1496) [Howard Su] +**Minor:** -*** Support vpiModule. (#1469) [Stefan Wallentowitz] +* Support decimal constants of arbitrary widths. [Mark Marshall] +* Fix error on case statement with all duplicate items. (#99) [Gary Thomas] +* Fix segfault on unrolling for's with bad inits. (#90) [Andreas Olofsson] +* Fix tristates causing "Assigned pin is neither...". [by Lane Brooks] +* Fix compiler errors under Fedora release candidate 11. [Chitlesh Goorah] -**** Make Syms file honor --output-split-cfuncs. (#1499) [Todd Strader] -**** Fix make test with no VERILATOR_ROOT. (#1494) [Ahmed El-Mahmoudy] +Verilator 3.710 2009-05-19 +========================== -**** Fix error on multidimensional cells. (#1505) [Anderson Ignacio Da Silva] +**Major:** -**** Fix config_rev revision detection on old versions. +* Verilator is now licensed under LGPL v3 and/or Artistic v2.0. -**** Fix false warning on backward indexing. (#1507) [Hao Shi] +**Minor:** -**** Fix vpiType accessor. (#1509) (#1510) [Stefan Wallentowitz] +* `__FILE__ now expands to a string, per draft SystemVerilog 2010(ish). +* The front end parser has been re-factored to enable more SV parsing. + Code should parse the same, but minor parsing bugs may pop up. +* Verilator_includer is no longer installed twice. (#48) [Lane Brooks] +* Fix escaped identifiers with '.' causing conflicts. (#83) [J Baxter] +* Fix define formal arguments that contain newlines. (#84) [David A] -**** Fix ugly error on interface misuse. (#1525) [Bogdan Vukobratovic] -**** Fix misc bad-syntax crashes. (#1529) (#1530) (#1531) (#1532) (#1533) [Eric Rippey] +Verilator 3.703 2009-05-02 +========================== -**** Fix case statements with strings. (#1536) [Philipp Wagner] +**Minor:** -**** Fix some coverage lost when multithreaded. (#2151) +* Fix $clog2 calculation error with powers-of-2. (#81) [Patricio Kaplan] +* Fix error with tasks that have output first. (#78) [Andrea Foletto] +* Fix "cloning" error with -y/--top-module. (#76) [Dimitris Nalbantis] +* Fix segfault with error on bad --top-module. (#79) [Dimitris Nalbantis] +* Fix "redefining I" error with complex includes. [Duraid Madina] +* Fix GCC 4.3.2 compile warnings. -* Verilator 4.018 2019-08-29 +Verilator 3.702 2009-03-28 +========================== -** When showing an error, show source code and offer suggestions of replacements. +**Minor:** -** When showing an error, show the instance location. (#1305) [Todd Strader] +* Add --pins-bv option to use sc_bv for all ports. [Brian Small] +* Add SYSTEMPERL_INCLUDE envvar to assist RPM builds. [Chitlesh Goorah] +* Report errors when duplicate labels are used. (#72) [Vasu Kandadi] +* Fix the SC_MODULE name() to not include __PVT__. [Bob Fredieu] -*** Add --rr. (#1481) [Todd Strader] -*** Change MULTITOP to warning to help linting, see manual. +Verilator 3.701 2009-02-26 +========================== -*** Add XSim support to driver.pl. (#1493) [Todd Strader] +**Minor:** -**** Show included-from filenames in warnings. (#1439) [Todd Strader] +* Support repeat and forever statements. [Jeremy Bennett] +* Add --debugi- option, for internal debugging. [Dennis Muhlestein] +* Fix compile issues with GCC 4.3. (#47) [Lane Brooks] +* Fix VL_RANDom to better randomize bits. [Art Stamness] +* Fix error messages to consistently go to stderr. [Jeremy Bennett] +* Fix left associativity for ?: operators. -**** Fix elaboration time errors. (#1429) [Udi Finkelstein] -**** Fix not reporting some duplicate signals/ports. (#1462) [Peter Gerst] +Verilator 3.700 2009-01-08 +========================== -**** Fix not in array context on non-power-of-two slices. (#2027) [Yu Sheng Lin] +**Major:** -**** Fix system compile flags injection. [Gianfranco Costamagna] +* Support limited tristate inouts. Written by Lane Brooks, + under support by Ubixum Inc. This allows common pad ring and + tristate-mux structures to be Verilated. See the documentation for + more information on supported constructs. +* Add --coverage_toggle for toggle coverage analysis. + Running coverage now requires SystemPerl 1.301 or newer. +* Add /*verilator coverage_on/_off */ to bracket coverage regions. -**** Fix enum values not being sized based on parent. (#1442) [Dan Petrisko] +**Minor:** -**** Fix internal error on gate optimization of assign. (#1475) [Oyvind Harboe] +* Support posedge of bit-selected signals. (#45) [Rodney Sinclair] +* Optimize two-level shift and and/or trees, +23% on one test. +* Line coverage now aggregates by hierarchy automatically. + Previously this would be done inside SystemPerl, which was slower. +* Minor performance improvements of Verilator compiler runtime. +* Coverage of each parametarized module is counted separately. [Bob Fredieu] +* Fix creating parameterized modules when no parameter values are changed. +* Fix certain generate-if cells causing "clone" error. [Stephane Laurent] +* Fix line coverage of public functions. [Soon Koh] +* Fix SystemC 2.2 deprecated warnings about sensitive() and sc_start(). +* Fix arrayed variables under function not compiling. (#44) [Ralf Karge] +* Fix --output-split-cfuncs to also split trace code. [Niranjan Prabhu] +* Fix 'bad select range' warning missing some cases. (#43) [Lane Brooks] +* Fix internal signal names containing control characters (broke in 3.680). +* Fix compile error on Ubuntu 8.10. [Christopher Boumenot] +* Fix internal error on "output x; reg x = y;". +* Fix wrong result for read of delayed FSM signal. (#46) [Rodney Sinclair] -**** Add --dpi-hdr-only. (#1491) [Todd Strader] +Verilator 3.681 2008-11-12 +========================== -* Verilator 4.016 2019-06-16 +**Minor:** -*** Add --quiet-exit. (#1436) [Todd Strader] +* Support SystemVerilog unique and priority case. +* Include Verilog file's directory name in coverage reports. +* Fix 'for' under 'generate-for' causing error. (#38) [Rafael Shirakawa] +* Fix coverage hierarchy being backwards with inlining. [Vasu Arasanipalai] +* Fix GCC 4.3 compile error. (#35) [Lane Brooks] +* Fix MSVC compile error. (#42) [John Stroebel] -**** Error continuation lines no longer have %Error prefix. -**** Support logical equivalence operator <->. +Verilator 3.680 2008-10-08 +========================== -**** Support VerilatedFstC set_time_unit. (#1433) [Pieter Kapsenberg] +**Major:** -**** Support deferred assertions. (#1449) [Charles Eddleston] +* Support negative bit indexes. [Stephane Laurent] + Tracing negative indexes requires latest Verilog-Perl and SystemPerl. -**** Mark infrequently called functions with GCC cold attribute. +**Minor:** -**** Fix sign-compare warning in verilated.cpp. (#1437) [Sergey Kvachonok] +* Suppress width warnings between constant strings and wider vectors. + [Rodney Sinclair] +* Ignore SystemVerilog timeunit and timeprecision. +* Expand environment variables in -f input files. [Lawrence Butcher] +* Report error if port declaration is missing. (#32) [Guy-Armand Kamendje] +* Fix genvars causing link error when using --public. [Chris Candler] -**** Fix fault on $realtime with %t. (#1443) [Julien Margetts] -**** Fix $display with string without %s. (#1441) [Denis Rystsov] +Verilator 3.671 2008-09-19 +========================== -**** Fix parameter function string returns. (#1441) [Denis Rystsov] +**Major:** -**** Fix invalid XML output due to special chars. (#1444) [Kanad Kanhere] +* SystemC uint64_t pins are now the default instead of sc_bv<64>. + Use --no-pins64 for backward compatibility. +* Support SystemVerilog "cover property" statements. -**** Fix performance when mulithreaded on 1 CPU. (#1455) [Stefan Wallentowitz] +**Minor:** -**** Fix type and real parameter issues (#1427) (#1456) (#1458) [Todd Strader] +* When warnings are disabled on signals that are flattened out, disable + the warnings on the signal(s) that replace it. +* Add by-design and by-module subtotals to verilator_profcfunc. +* Add IMPERFECTSCH warning, disabled by default. +* Support coverage under SystemPerl 1.285 and newer. +* Support arbitrary characters in identifiers. [Stephane Laurent] +* Fix extra evaluation of pure combo blocks in SystemC output. +* Fix stack overflow on large ? : trees. [John Sanguinetti] -**** Fix build error on MinGW. (#1460) [Richard Myers] -**** Fix not reporting some duplicate signals. (#1462) [Peter Gerst] +Verilator 3.670 2008-07-23 +========================== -**** Fix --savable invalid C++ on packed arrays. (#1465) [Alex Chadwick] +**Major:** -**** Fix constant function return of function var. (#1467) [Roman Popov] +* Add --x-assign=fast option, and make it the default. + This chooses performance over reset debugging. See the manual. +* Add --autoflush, for flushing streams after $display. [Steve Tong] +* Add CASEWITHX lint warning and if disabled fix handling of casez with Xs. +**Minor:** -* Verilator 4.014 2019-05-08 +* Add $feof, $fgetc, $fgets, $fflush, $fscanf, $sscanf. [Holger Waechtler] +* Add $stime. [Holger Waechtler] +* Add $random. +* Add --Wfuture-, for improving forward compatibility. +* Add WIDTH warning to $fopen etc file descriptors. +* Fix verilator_includer not being installed properly. [Holger Waechtler] +* Fix IMPURE errors due to X-assignment temporary variables. [Steve Tong] +* Fix "lvalue" errors with public functions. (#25) [CY Wang] -*** Add --trace-fst-thread. -**** Support '#' comments in $readmem. (#1411) [Frederick Requin] +Verilator 3.665 2008-06-25 +========================== -**** Support "'dx" constants. (#1423) [Udi Finkelstein] +**Minor:** -**** For FST tracing use LZ4 compression. [Tony Bybell] +* Ignore "// verilator" comments alone on endif lines. [Rodney Sinclair] +* "Make install" now installs verilator_includer and verilator_profcfunc. +* Fix tracing missing changes on undriven public wires. [Rodney Sinclair] +* Fix syntax error when "`include `defname" is ifdefed. [John Dickol] +* Fix error when macro call has commas in concatenate. [John Dickol] +* Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett] +* Fix Makefile to find headers/libraries under prefix. [by Holger Waechtler] -**** Add error when use parameters without value. (#1424) [Peter Gerst] -**** Auto-extend and WIDTH warn on unsized X/Zs. (#1423) [Udi Finkelstein] +Verilator 3.664 2008-05-08 +========================== -**** Fix missing VL_SHIFTL_ errors. (#1412) (#1415) [Larry Lee] +**Minor:** -**** Fix MinGW GCC 6 printf formats. (#1413) [Sergey Kvachonok] +* Fix missing file in kit. -**** Fix test problems when missing fst2vcd. (#1417) [Todd Strader] -**** Fix GTKWave register warning. (#1421) [Pieter Kapsenberg] +Verilator 3.663 2008-05-07 +========================== -**** Fix FST enums not displaying. (#1426) [Danilo Ramos] +**Minor:** -**** Fix table compile error with multiinterfaces. (#1431) [Bogdan Vukobratovic] +* Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer] +* Fix compiler warnings under GCC 4.2.1. +* Fix preprocessor `else after series of `elsif. [Mark Nodine] +* Fix parameterized defines calling define with comma. [Joshua Wise] +* Fix comma separated list of primitives. [by Bryan Brady] -* Verilator 4.012 2019-03-23 +Verilator 3.662 2008-04-25 +========================== -*** Add +verilator+seed. (#1396) [Stan Sokorac] +**Minor:** -*** Support $fread. [Leendert van Doorn] +* Add Verilog 2005 $clog2() function. + This is useful in calculating bus-widths from parameters. +* Support /**/ comments in -f option files. [Stefan Thiede] +* Add error message when modules have duplicate names. [Stefan Thiede] +* Support defines terminated in EOF, though against spec. [Stefan Thiede] +* Support optional argument to $finish and $stop. [by Stefan Thiede] +* Support ranges on gate primitive instantiations. [Stefan Thiede] +* Ignore old standard(ish) Verilog-XL defines. [by Stefan Thiede] +* Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu] +* Fix "output reg name=expr;" syntax error. [Martin Scharrer] +* Fix multiple .v files being read in random order. [Stefan Thiede] +* Fix internal error when params get non-constants. [Johan Wouters] +* Fix bug introduced in 3.661 with parameterized defines. -*** Support void' cast on functions called as tasks. (#1383) [Al Grant] -*** Add IGNOREDRETURN warning. (#1383) +Verilator 3.661 2008-04-04 +========================== -**** Report PORTSHORT errors on concat constants. (#1400) [Will Korteland] +**Major:** -**** Fix VERILATOR_GDB being ignored. (#2017) [Yu Sheng Lin] +* The --enable-defenv configure option added in 3.660 is now the default. + This hard-codes a default for VERILATOR_ROOT etc in the executables. +* Add --language option for supporting older code. [Stefan Thiede] +* Add --top-module option to select between multiple tops. [Stefan Thiede] -**** Fix $value$plus$args missing verilated_heavy.h. [Yi-Chung Chen] +**Minor:** -**** Fix MSVC compile error. (#1406) [Benjamin Gartner] +* Unsized concatenates now give WIDTHCONCAT warnings. [Jonathan Kimmitt] + Previously they threw fatal errors, which in most cases is correct + according to spec, but can be incorrect in presence of parameter values. +* Support functions with "input integer". [Johan Wouters] +* Ignore delays attached to gate UDPs. [Stefan Thiede] +* Fix SystemVerilog parameterized defines with \`\` expansion, + and fix extra whitespace inserted on substitution. [Vladimir Matveyenko] +* Fix no-module include files on command line. [Stefan Thiede] +* Fix dropping of backslash quoted-quote at end of $display. +* Fix task output pin connected to non-variables. [Jonathan Kimmitt] +* Fix missing test_v in install datadir. [Holger Waechtler] +* Fix internal error after MSB < LSB error reported to user. [Stefan Thiede] -**** Fix maintainer test when no Parallel::Forker. (#1977) [Enzo Chi] -**** Fix +1364-1995ext flags applying too late. (#1384) [Al Grant] +Verilator 3.660 2008-03-23 +========================== +**Minor:** -* Verilator 4.010 2019-01-27 +* Support hard-coding VERILATOR_ROOT etc in the executables, + to enable easier use of Verilator RPMs. [Gunter Dannoritzer] +* Allow multiple .v files on command line. [Stefan Thiede] +* Convert re-defining macro error to warning. [Stefan Thiede] +* Add --error-limit option. [Stefan Thiede] +* Allow __ in cell names by quoting them in C. [Stefan Thiede] +* Fix genvar to be signed, so "< 0" works properly. [Niranjan Prabhu] +* Fix assignments to inputs inside functions/tasks. [Patricio Kaplan] +* Fix definitions in main file.v, referenced in library. [Stefan Thiede] +* Fix undefined assigns to be implicit warnings. [Stefan Thiede] -*** Removed --trace-lxt2, use --trace-fst instead. -**** For --xml, add additional information. (#1372) [Jonathan Kimmitt] +Verilator 3.658 2008-02-25 +========================== -**** Add circular typedef error. (#1388) [Al Grant] +**Minor:** -**** Add unsupported for loops error. (#1986) [Yu Sheng Lin] +* Fix unistd compile error in 3.657. [Patricio Kaplan, Jonathan Kimmitt] -**** Fix FST tracing of wide arrays. (#1376) [Aleksander Osman] -**** Fix error when pattern assignment has too few elements. (#1378) [Viktor Tomov] +Verilator 3.657 2008-02-20 +========================== -**** Fix error when no modules in $unit. (#1381) [Al Grant] +**Minor:** -**** Fix missing too many digits warning. (#1380) [Jonathan Kimmitt] +* Fix assignments of {a,b,c} = {c,b,a}. [Jonathan Kimmitt] +* Fix Perl warning with --lint-only. [by Ding Xiaoliang] +* Fix to avoid creating obj_dir with --lint-only. [Ding Xiaoliang] +* Fix parsing of always @(*). [Patricio Kaplan] -**** Fix uninitialized data in verFiles and unroller. (#1385) (#1386) [Al Grant] -**** Fix internal error on xrefs into unrolled functions. (#1387) [Al Grant] +Verilator 3.656 2008-01-18 +========================== -**** Fix DPI export void compiler error. (#1391) [Stan Sokorac] +**Minor:** +* Wide VL_CONST_W_#X functions are now made automatically. [Bernard Deadman] + In such cases, a new {prefix}__Inlines.h file will be built and included. +* Fix sign error when extracting from signed memory. [Peter Debacker] +* Fix tracing of SystemC w/o SystemPerl. [Bernard Deadman, Johan Wouters] -* Verilator 4.008 2018-12-01 -*** Support "ref" and "const ref" pins and functions. (#1360) [Jake Longo] +Verilator 3.655 2007-11-27 +========================== -*** In --xml-only show the original unmodified names, and add module_files - and cells similar to Verilog-Perl, msg2719. [Kanad Kanhere] +**Minor:** -**** Add CONTASSREG error on continuous assignments to regs. (#1369) [Peter Gerst] +* Support "#delay ;" with associated STMTDLY warning. +* Fix generate for loops with constant zero conditions. [Rodney Sinclair] +* Fix divide-by-zero errors in constant propagator. [Rodney Sinclair] +* Fix wrong result with obscure signed-shift underneath a "? :". +* Fix many internal memory leaks, and added leak detector. -**** Add PROCASSWIRE error on behavioral assignments to wires, msg2737. [Neil Turton] -**** Add IMPORTSTAR warning on import::* inside $unit scope. +Verilator 3.654 2007-10-18 +========================== -**** Fix --trace-lxt2 compile error on MinGW. (#1990) [HyungKi Jeong] +**Minor:** -**** Fix hang on bad pattern keys. (#1364) [Matt Myers] +* Don't exit early if many warnings but no errors are found. [Stan Mayer] +* Fix parsing module #(parameter x,y) declarations. [Oleg Rodionov] +* Fix parsing system functions with empty parens. [Oleg Rodionov] -**** Fix crash due to cygwin bug in getline. (#1349) [Affe Mao] -**** Fix __Slow files getting compiled with OPT_FAST. (#1370) [Thomas Watts] +Verilator 3.653 2007-08-01 +========================== +**Minor:** -* Verilator 4.006 2018-10-27 +* Support SystemVerilog ==? and !=? operators. +* Fix SC_LIBS missing from generated makefiles. [Ding Xiaoliang] -** Add --pp-comments. (#1988) [Robert Henry] -** Add --dump-defines. +Verilator 3.652 2007-06-21 +========================== -*** For --trace-fst, save enum decoding information. (#1358) [Sergi Granell] - (To visualize enumeration data you must use GTKwave 3.3.95 or newer.) +**Minor:** -*** For --trace-fst, instead of *.fst.hier, put data into *.fst. [Tony Bybell] +* Report as many warning types as possible before exiting. +* Support V2K portlists with "input a,b,...". [Mark Nodine] +* Support V2K function/task argument lists. +* Optimize constant $display arguments. +* Fix Preprocessor dropping some `line directives. [Mark Nodine] -**** Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong] -**** Fix Windows .exe not found. (#1361) [Patrick Stewart] +Verilator 3.651 2007-05-22 +========================== +**Major:** -* Verilator 4.004 2018-10-06 +* Add verilator_profcfunc utility. [Gene Weber] -** Add GTKWave FST native tracing. (#1356) [Sergi Granell] - (Verilator developers need to pull the latest vcddiff.) +**Minor:** -*** Support $past. [Dan Gisselquist] +* Treat modules within `celldefine and `endcelldefine as if in library. +* Support functions which return integers. [Mark Nodine] +* Warn if flex is not installed. [Ralf Karge] +* Ignore `protect and `endprotect. +* Fix empty case/endcase blocks. -*** Support restrict. (#1350) [Clifford Wolf] -*** Rename include/lxt2 to include/gtkwave. +Verilator 3.650 2007-04-20 +========================== -**** Fix replication of 64-bit signal change detects. +**Major:** -**** Fix Mac OSX 10.13.6 / LLVM 9.1 compile issues. (#1348) [Kevin Kiningham] +* Add --compiler msvc option. This is now required when Verilated code + is to be run through MSVC++. This also enables fixing MSVC++ error + C1061, blocks nested too deeply. [Ralf Karge] +* Add --lint-only option, to lint without creating other output. -**** Fix MinGW compile issues. (#1979) [HyungKi Jeong] +**Minor:** +* Add /*verilator lint_save*/ and /*verilator lint_restore*/ to allow + friendly control over re-enabling lint messages. [Gerald Williams] +* Support SystemVerilog .name and .* interconnect. +* Support while and do-while loops. +* Use $(LINK) instead of $(CXX) for Makefile link rules. [Gerald Williams] +* Add USER_CPPFLAGS and USER_LDFLAGS to Makefiles. [Gerald Williams] +* Fix compile errors under Windows MINGW compiler. [Gerald Williams] +* Fix dotted bit reference to local memory. [Eugene Weber] +* Fix 3.640 `verilog forcing IEEE 1364-1995 only. [David Hewson] -* Verilator 4.002 2018-09-16 -** This is a major release. Any patches may require major rework to apply. - [Thanks everyone] +Verilator 3.640 2007-03-12 +========================== -** Add multithreaded model generation. +**Minor:** -** Add runtime arguments. +* Support Verilog 2005 `begin_keywords and `end_keywords. +* Updated list of SystemVerilog keywords to correspond to IEEE 1800-2005. +* Add /*verilator public_flat*/. [Eugene Weber] +* Try all +libext's in the exact order given. [Michael Shinkarovsky] +* Fix elimination of public signals assigned to constants. [Eugene Weber] +* Fix internal error when public for loop has empty body. [David Addison] +* Fix "Loops detected" assertion when model exceeds 4GB. [David Hewson] +* Fix display %m names inside named blocks. -** Add GTKWave LXT2 native tracing. (#1333) [Yu Sheng Lin] -** Note $random has new algorithm; results may vary vs. previous versions. +Verilator 3.633 2007-02-07 +========================== -*** Better optimize large always block splitting. (#1244) [John Coiner] +**Minor:** -*** Add new reloop optimization for repetitive assignment compression. +* Add --trace-depth option for minimizing VCD file size. [Emerson Suguimoto] +* With VL_DEBUG, show wires causing convergence errors. [Mike Shinkarovsky] +* Fix isolate_assignments when many signals per always. [Mike Shinkarovsky] +* Fix isolate_assignments across task/func temporaries. [Mike Shinkarovsky] +* Fix $display's with array select followed by wide AND. [David Hewson] -*** Support string.atoi and similar methods. (#1289) [Joel Holdsworth] -**** Fix internals to be C++ null-pointer-check clean. +Verilator 3.632 2007-01-17 +========================== -**** Fix internals to avoid 'using namespace std'. +**Minor:** -**** Fix Verilation performance issues. (#1316) [John Coiner] +* Add /*verilator isolate_assignments*/ attribute. [Mike Shinkarovsky] -**** Fix clocker attributes to not propagate on concats. [John Coiner] -**** Fix first clock edge and --x-initial-edge. (#1327) [Rupert Swarbrick] +Verilator 3.631 2007-01-02 +========================== -**** Fix compile error on tracing of string arrays. (#1338) [Iztok Jeras] +**Major:** -**** Fix number parsing with newline after radix. (#1340) [George Cuan] +* Support standard NAME[#] for cells created by arraying or generate for. + This replaces the non-standard name__# syntax used in earlier versions. -**** Fix string ?: conditional type resolution. (#1345) [Iztok Jeras] +**Minor:** -**** Fix duplicate symbol error on generate tri. (#1347) [Tomas Dzetkulic] +* Fix again dotted references into generate cells. [David Hewson] + Verilator no longer accepts duplicated variables inside unique + generate blocks as this is illegal according to the specification. +* Fix $readmem* with filenames < 8 characters. [Emerson Suguimoto] -* Verilator 3.926 2018-08-22 +Verilator 3.630 2006-12-19 +========================== -**** Add OBJCACHE envvar support to examples and generated Makefiles. +**Major:** -**** Change MODDUP errors to warnings. (#1969) [Marshal Qiao] +* Support $readmemb and $readmemh. [Eugene Weber, Arthur Kahlich] -**** Fix define argument stringification (`"), broke since 3.914. [Joe DErrico] +**Minor:** -**** Fix to ignore Unicode UTF-8 BOM sequences. (#1967) [HyungKi Jeong] +* When dotted signal lookup fails, help the user by showing known scopes. +* Fix to reduce depth of priority encoded case statements. [Eugene Weber] +* Fix configure and compiling under Solaris. [Bob Farrell] +* Fix dotted references inside generated cells. [David Hewson] +* Fix missed split optimization points underneath other re-split blocks. -**** Fix std:: build error. (#1322) -**** Fix function inlining inside certain while loops. (#1330) [Julien Margetts] +Verilator 3.623 2006-12-05 +========================== +**Major:** -* Verilator 3.924 2018-06-12 +* Add --output-split-cfuncs for accelerating GCC compile. [Eugene Weber] -*** Renamed --profile-cfuncs to --prof-cfuncs. +**Minor:** -**** Report interface ports connected to wrong interface. (#1294) [Todd Strader] +* Add M32 make variable to support -m32 compiles. [Eugene Weber] +* Fix $signed mis-extending when input has a WIDTH violation. [Eugene Weber] -**** When tracing, use scalars on single bit arrays to appease vcddiff. -**** Fix parsing "output signed" in V2K port list, msg2540. [James Jung] +Verilator 3.622 2006-10-17 Stable +================================= -**** Fix parsing error on bad missing #. (#1308) [Dan Kirkham] +**Minor:** -**** Fix $clog2 to be in verilog 2005. (#1319) [James Hutchinson] +* Fix --skip-identical without --debug, broken in 3.621. [Andy Meier] -* Verilator 3.922 2018-03-17 +Verilator 3.621 2006-10-11 Beta +=============================== -** Support IEEE 1800-2017 as default language. +**Major:** -*** Support trig functions ($sin() etc). (#1281) [Patrick Stewart] +* Add /*verilator no_inline_task*/ to prevent over-expansion. [Eugene Weber] -*** Support calling system functions as tasks. (#1285) [Joel Holdsworth] +**Minor:** -*** Support assert properties. (#785) (#1290) [John Coiner, et al] +* Public functions now allow > 64 bit arguments. +* Remove .vpp intermediate files when not under --debug. +* Fix link error when using --exe with --trace. [Eugene Weber] +* Fix mis-optimization of wide concats with constants. +* Fix core dump on printing error when not under --debug. [Allan Cochrane] -*** Support $writememh. [John Coiner] -*** Add --no-debug-leak to reduce memory use under debug. [John Coiner] +Verilator 3.620 2006-10-04 Stable +================================= -**** Fix severe runtime performance bug in certain foreach loops. [John Coiner] +**Minor:** -**** On convergence errors, show activity. [John Coiner] +* Support simple inout task ports. [Eugene Weber] +* Allow overriding Perl, Flex and Bison versions. [by Robert Farrell] +* Optimize variables set to constants within basic blocks for ~3%. +* Default make no longer makes the docs; if you edit the documentation. + sources, run "make info" to get them. +* Optimize additional boolean identities (a|a = a, etc.) +* Fix coredump when dotted cross-ref inside task call. [Eugene Weber] +* Fix dotted variables in always sensitivity lists. [Allan Cochrane] -**** Fix GCC 8.0 issues. (#1273) -**** Fix pullup/pulldowns on bit selects. (#1274) [Rob Stoddard] +Verilator 3.610 2006-09-20 Stable +================================= -**** Fix verilator_coverage --annotate-min. (#1284) [Tymoteusz Blazejczyk] +**Minor:** -**** Fix quoting of quoted arguments. [John Coiner] +* Verilator now works under DJGPP (Pentium GCC). [John Stroebel] +* Add default define for VL_PRINTF. [John Stroebel] +* Removed coverage request variable; see Coverage limitations in docs. +* Fix DOS carriage returns in multiline defines. [Ralf Karge] +* Fix printf format warnings on 64-bit linux. -* Verilator 3.920 2018-02-01 +Verilator 3.602 2006-09-11 Stable +================================= -** Moving forward, use the git "stable" branch to track the latest release, - and git "v#.###" tags for specific releases. +**Minor:** -*** Support 'assume' similar to 'assert'. (#1269) [Dan Gisselquist] +* Fix function references under top inlined module. [David Hewson] -**** Fix tracing example file output. (#1268) [Enzo Chi] -**** Fix gate optimization out of memory, add --gate-stmts. (#1260) [Alex Solomatnikov] +Verilator 3.601 2006-09-06 Beta +=============================== -**** Fix compile error on public real parameters by suppressing. (#1261) [Alex Solomatnikov] +**Major:** -**** Fix input-only tristate comparisons. (#1267) [Alexis G] +* Add --inhibit-sim flag for environments using old __Vm_inhibitSim. +* Add `systemc_dtor for destructor extensions. [Allan Cochrane] +* Add -MP to make phony dependencies, ala GCC's. -**** Fix missing edge type in xml output. (#1955) [Alexis G] +**Minor:** -**** Fix compile error with --public and interface bind. (#1264) [Alexis G] +* Changed how internal functions are invoked to reduce aliasing. + Useful when using GCC's -O2 or -fstrict-aliasing, to gain another ~4%. +* Declare optimized lookup tables as 'static', to reduce D-Cache miss rate. +* Fix memory leak when destroying modules. [John Stroebel] +* Fix coredump when unused modules have unused cells. [David Hewson] +* Fix 3.600 internal error with arrayed instances. [David Hewson] +* Fix 3.600 internal error with non-unrolled function loops. [David Hewson] +* Fix $display %m name not matching Verilog name inside SystemC modules. -**** Remove c++filt. (#1265) [Stefan Wallentowitz] +Verilator 3.600 2006-08-28 Beta +=============================== -* Verilator 3.918 2018-01-02 +**Major:** -*** Workaround GCC/clang bug with huge compile times. (#1248) +* Support dotted cross-hierarchy variable and task references. -*** Support DPI open arrays. (#909) (#1245) [David Pierce, Victor Besyakov] +**Minor:** -*** Add INFINITELOOP warning. (#1254) [Alex Solomatnikov] +* Lint for x's in generate case statements. +* Fix line numbers being off by one when first file starts with newline. +* Fix naming of generate for blocks to prevent non-inline name conflict. +* Fix redundant statements remaining after table optimization. -**** Support > 64 bit decimal $display. -**** Support DPI time and svLogicVal. [Victor Besyakov] - Note older version incorrectly assumed svBitVal even for logicals. +Verilator 3.542 2006-08-11 Stable +================================= -**** Support string len() method. [Victor Besyakov] +**Minor:** -**** Add error if always_comb has sensitivity list. [Arjen Roodselaar] +* vl_finish and vl_fatal now print via VL_PRINTF rather then cerr/cout. +* Fix extraneous UNSIGNED warning when comparing genvars. [David Hewson] +* Fix extra white space in $display %c. [by David Addison] +* Fix missing VL_CONST_W_24X macro. [Bernard Deadman] -**** Fix SystemC 2.3.2 compile error. (#1251) [Tymoteusz Blazejczyk] -**** Fix modport outputs being treated as inputs. (#1246) [Jeff Bush] +Verilator 3.541 2006-07-05 Beta +=============================== -**** Fix false ALWCOMBORDER on interface references. (#1247) [Josh Redford] +**Minor:** -**** Fix constant propagation across DPI imports of inout strings. [Victor Besyakov] +* Add warning on changeDetect to arrayed structures. [David Hewson] +* Fix "// verilator lint_on" not re-enabling warnings. [David Hewson] +* Fix 3.540's multiple memory assignments to same block. [David Hewson] +* Fix non-zero start number for arrayed instantiations. [Jae Hossell] +* Fix GCC 4.0 header file warnings. -**** Fix resolving inline nested interface names. (#1250) [Arjen Roodselaar] -**** Fix GCC false warning on array bounds. (#2386) +Verilator 3.540 2006-06-27 Beta +=============================== +**Minor:** -* Verilator 3.916 2017-11-25 +* Optimize combo assignments that are used only once, ~5-25% faster. +* Optimize delayed assignments to memories inside loops, ~0-5% faster. +* Fix mis-width warning on bit selects of memories. [David Hewson] +* Fix mis-width warning on dead generate-if branches. [Jae Hossell] -*** Support self-recursive modules. (#659) [Sean Moore, et al] -*** Support $error/$warning in elaboration time blocks. +Verilator 3.533 2006-06-05 Stable +================================= -*** Support $size/$bits/etc on type references. +**Minor:** -*** Add error when driving input-only modport. (#1110) [Trevor Elbourne] +* Add PDF user manual, verilator.pdf. +* Fix delayed bit-selected arrayed assignments. [David Hewson] +* Fix execution path to Perl. [Shanshan Xu] +* Fix Bison compile errors in verilog.y. [by Ben Jackson] -*** Add BSSPACE and COLONPLUS lint warnings. -**** Detect MSB overflow when under VL_DEBUG. (#1238) [Junyi Xi] +Verilator 3.531 2006-05-10 Stable +================================= -**** Add data types to --xml. [Rui Terra] +**Minor:** -**** Fix partial slicing with pattern assignments. (#991) [Johan Bjork] +* Support $c routines which return 64 bit values. +* Fix `include `DEFINE. +* Fix Verilator core dump when have empty public function. [David.Hewson] -**** Fix false unused warning on interfaces. (#1241) [Laurens van Dam] -**** Fix error on "unique case" with no cases. +Verilator 3.530 2006-04-24 Stable +================================= -**** Fix MacOS portability. (#1232) [Jeff Bush] +**Major:** +* $time is now 64 bits. The macro VL_TIME_I is now VL_TIME_Q, but calls + the same sc_time_stamp() function to get the current time. -* Verilator 3.914 2017-10-14 -** Added new examples/ directory with appropriate examples. This replaces the - old test_c and test_sc directories. +Verilator 3.523 2006-03-06 Stable +================================= -*** Add --getenv option for simplifying Makefiles. +**Minor:** -*** Add --x-initial option for specifying initial value assignment behavior. +* Fix error line numbers being off due to multi-line defines. [Mat Zeno] +* Fix GCC sign extending (uint64_t)(a>>, $signed, $unsigned. [MANY!] +* Support multi-dimensional arrays. [Eugen Fekete] +* Support very limited Property Specification Language + (aka PSL or Sugar). The format and keywords are now very limited, but will + grow with future releases. The --assert switch enables this feature. +* With --assert, generate assertions for synthesis parallel_case and full_case. -**** Update keyword warnings to include C++11 and others. +**Minor:** +* Fix generate if's with empty if/else blocks. [Mat Zeno] +* Fix generate for cell instantiations with same name. [Mat Zeno] -* Verilator 3.908 2017-08-28 -**** Support x in $readmem. (#1180) [Arthur Kahlich] +Verilator 3.481 2005-10-12 Stable +================================= -**** Support packed struct DPI imports. (#1190) [Rob Stoddard] +**Minor:** -**** Fix GCC 6 warnings. +* Add /*verilator tracing_on/off*/ for waveform control. +* Fix split optimization reordering $display statements. -**** Fix compile error on unused VL_VALUEPLUSARGS_IW. (#1181) [Thomas J Whatson] -**** Fix undefined VL_POW_WWI. [Clifford Wolf] +Verilator 3.480 2005-09-27 Beta +=============================== -**** Fix internal error on unconnected inouts. (#1187) [Rob Stoddard] +**Major:** +* Allow coverage of flattened modules, and multiple points per line. + Coverage analysis requires SystemPerl 1.230 or newer. -* Verilator 3.906 2017-06-22 +**Minor:** -*** Support set_time_unit/set_time_precision in C traces. (#1937) +* Add preprocessor changes to support meta-comments. +* Optimize sequential assignments of different bits of same bus; ~5% faster. +* Optimize away duplicate lookup tables. +* Optimize wide concatenates into individual words. [Ralf Karge] +* Optimize local variables from delayed array assignments. -*** Fix extract of packed array with non-zero LSB. (#1172) [James Pallister] -*** Fix shifts by more than 32-bit numbers. (#1174) [Clifford Wolf] +Verilator 3.470 2005-09-06 Stable +================================= -*** Fix power operator on wide constants. (#761) [Clifford Wolf] +**Minor:** -*** Fix .* on interface pins. (#1176) [Maciej Piechotka] +* Optimize staging flops under reset blocks. +* Add '-Werror-...' to upgrade specific warnings to errors. +* Add GCC branch prediction hints on generated if statements. +* Fix bad simulation when same function called twice in same expression. +* Fix preprocessor substitution of quoted parameterized defines. -* Verilator 3.904 2017-05-30 +Verilator 3.464 2005-08-24 Stable +================================= -*** Fix non-cutable ordering loops on clock arrays. (#1009) [Todd Strader] +**Major:** -*** Support ports of array of reals. (#1154) [J Briquet] +* Add `systemc_imp_header, for use when using --output-split. +* Add --stats option to dump design statistics. -*** Support arrayed parameter overrides. (#1153) [John Stevenson] +**Minor:** -*** Support $value$plusargs with variables. (#1165) [Wesley Terpstra] +* Fix core dump with clock inversion optimizations. -**** Support modport access to un-modport objects. (#1161) [Todd Strader] -**** Add stack trace when can't optimize function. (#1158) [Todd Strader] +Verilator 3.463 2005-08-05 Stable +================================= -**** Add warning on mis-sized literal. (#1156) [Todd Strader] +**Minor:** -**** Fix interface functions returning wrong parameters. (#996) [Todd Strader] +* Fix case defaults when not last statement in case list. [Wim Michiels] -**** Fix non-arrayed cells with interface arrays. (#1153) [John Stevenson] -**** Fix --assert with complex case statements. (#1164) [Enzo Chi] +Verilator 3.462 2005-08-03 Stable +================================= +**Minor:** -* Verilator 3.902 2017-04-02 +* Fix reordering of delayed assignments to same memory index. [Wim Michiels] +* Fix compile error with Flex 2.5.1. [Jens Arm] +* Fix multiply-instantiated public tasks generating non-compilable code. -** Add -FI option to force includes. (#1916) [Amir Gonnen] -** Add --relative-includes. [Rob Stoddard] +Verilator 3.461 2005-07-28 Beta +=============================== -*** Add error on duplicate pattern assignments. (#1145) [Johan Bjork] +**Minor:** -**** Fix error on improperly widthed default function. (#984) [Todd Strader] +* Fix compile error with older versions of bison. [Jeff Dutton] -**** Fix 2009 localparam syntax, msg2139. [Galen Seitz] -**** Fix ugly interface-to-non-interface errors. (#1112) [Johan Bjork] +Verilator 3.460 2005-07-27 Beta +=============================== -**** Fix LDFLAGS and CFLAGS not preserving order. (#1130) [Olof Kindgren] +**Major:** -**** Fix internal error on initializing parameter array. (#1131) [Jie Xu] +* Add -output-split option to enable faster parallel GCC compiles. + To support --output-split, the makefiles now split VM_CLASSES + into VM_CLASSES_FAST and VM_CLASSES_SLOW. This may require a + change to local makefiles. +* Support -v argument to read library files. -**** Fix internal error on interface arrays. (#1135) [John Stevenson] +**Minor:** -**** Fix calling sformatf to display, and elab $displays. (#1139) [Johan Bjork] +* When issuing unoptimizable warning, show an example path. +* Internal tree dumps now indicate edit number that changed the node. +* Fix false warning when a clock is constant. +* Fix X/Z in decimal numbers. [Wim Michiels] +* Fix genvar statements in non-named generate blocks. +* Fix core dump when missing newline in `define. [David van der bokke] -**** Fix realpath compile issue on MSVC++. (#1141) [Miodrag Milanovic] -**** Fix missing error on interface size mismatch. (#1143) [Johan Bjork] +Verilator 3.450 2005-07-12 +========================== -**** Fix error on parameters with dotted references. (#1146) [Johan Bjork] +**Major:** -**** Fix wreal not handling continuous assign. (#1150) [J Briquet] +* $finish will no longer exit, but set Verilated::gotFinish(). + This enables support for final statements, and for other cleanup code. + If this is undesired, redefine the vl_user_finish routine. Top level + loops should use Verilated::gotFinish() as a exit condition for their + loop, and then call top->final(). To prevent a infinite loop, a double + $finish will still exit; this may be removed in future releases. +* Support SystemVerilog keywords $bits, $countones, $isunknown, + $onehot, $onehot0, always_comb, always_ff, always_latch, finish. -**** Fix nested structure parameter selects. (#1150) [J Briquet] +**Minor:** +* Fix "=== 1'bx" to always be false, instead of random. -* Verilator 3.900 2017-01-15 -** Internal code changes for improved compatibility and performance. +Verilator 3.440 2005-06-28 Stable +================================= -*** Support old-style $display($time). (#467) [John Demme] +**Major:** -**** With --bbox-unsup, suppress desassign and mixed edges. (#1120) [Galen Seitz] +* Add Verilog 2001 generate for/if/case statements. -**** Fix parsing sensitivity with &&. (#934) [Luke Yang] -**** Fix internal error on double-for loop unrolling. (#1044) [Jan Egil Ruud] -**** Fix internal error on unique casez with --assert. (#1117) [Enzo Chi] +Verilator 3.431 2005-06-24 Stable +================================= -**** Fix bad code when tracing array of structs. (#1122) [Andrew Bardsley] +**Minor:** +* Fix selection bugs introduced in 3.430 beta. -* Verilator 3.890 2016-11-25 -*** Honor --output-split on coverage constructors. (#1098) [Johan Bjork] +Verilator 3.430 2005-06-22 Beta +=============================== -**** Fix various issues when making outside of the kit. +**Minor:** -**** Fix flex 2.6.2 bug. (#1103) [Sergey Kvachonok] +* Add Verilog 2001 variable part selects [n+:m] and [n-:m]. [Wim Michiels] -**** Fix error on bad interface name. (#1097) [Todd Strader] -**** Fix error on referencing variable in parent. (#1099) [Ian Thompson] +Verilator 3.422 2005-06-10 Stable +================================= -**** Fix type parameters with low optimization. (#1101) [Stefan Wallentowitz] +**Minor:** +* Add Verilog 2001 power (**) operator. [Danny Ding] +* Fix crash and added error message when assigning to inputs. [Ralf Karge] +* Fix tracing of modules with public functions. -* Verilator 3.888 2016-10-14 -** Support foreach. (#1078) [Xuan Guo] +Verilator 3.421 2005-06-02 Beta +=============================== -*** Add --no-decoration to remove output comments, msg2015. [Frederic Requin] +**Minor:** -*** If VM_PARALLEL_BUILDS=1, use OPT_FAST and OPT_SLOW. [Frederic Requin] - Set VM_DEFAULT_RULES=0 for old behavior. +* Fix error about reserved word on non-public signals. +* Fix missing initialization compile errors in 3.420 beta. [Ralf Karge] -**** Add error on DPI functions > 32 bits. (#1898) [Elliot Mednick] -**** Fix SystemC compiles with VPI. (#1081) [Arthur Kahlich] +Verilator 3.420 2005-06-02 Beta +=============================== -**** Fix error on wide numbers that represent shifts, msg1991. (#1088) [Mandy Xu] +**Minor:** -**** Improve Verilation performance on internal strings. (#1896) [Johan Bjork] +* Performance improvements worth ~20% +* Add -x-assign options; ~5% faster if use -x-assign=0. +* Add error message when multiple defaults in case statement. +* Optimize shifts out of conditionals and if statements. +* Optimize local 'short' wires. +* Fix case defaults when not last statement in case list. [Ralf Karge] +* Fix crash when wire self-assigns x=x. +* Fix gate optimization with top-flattened modules. [Mahesh Kumashikar] -**** Improve Verilation performance on trace duplicates. (#1090) [Johan Bjork] +Verilator 3.411 2005-05-30 Stable +================================= -* Verilator 3.886 2016-07-30 +**Minor:** -**** Fix enum values of 11-16 bits wide using .next/.prev. (#1062) [Brian Flachs] +* Fix compile error in GCC 2.96. [Jeff Dutton] -**** Fix false warnings on non-power-2 enums using .next/.prev. -**** Fix comparison of unpacked arrays. (#1071) [Andrew Bardsley] +Verilator 3.410 2005-05-25 Beta +=============================== -**** Fix compiler warning in GCC 6. [David Horton] +**Major:** +* Allow functions and tasks to be declared public. + They will become public C++ functions, with appropriate C++ types. + This allows users to make public accessor functions/tasks, instead + of having to use public variables and `systemc_header hacks. -* Verilator 3.884 2016-05-18 +**Minor:** -** Support parameter type. (#376) [Alan Hunter, et al] +* Skip producing output files if all inputs are identical + This uses timestamps, similar to make. Disable with --no-skip-identical. +* Improved compile performance with large case statements. +* Fix internal error in V3Table. [Jeff Dutton] +* Fix compile error in GCC 2.96, and with SystemC 1.2. [Jeff Dutton] -** Support command-line -G/+pvalue param overrides. (#1045) [Stefan Wallentowitz] -*** The default l2 scope name is now the same as the top-level module. (#1050) - Use "--l2-name v" for the historical behavior. +Verilator 3.400 2005-04-29 Beta +=============================== -*** Add --l2-name option for controlling "v" naming. +**Major:** -**** Fix --output-split of constructors. (#1035) [Johan Bjork] +* Internal changes to support future clocking features. +* Verilog-Perl and SystemPerl are no longer required for C++ or SystemC + output. If you want tracing or coverage analysis, they are still needed. +* Add --sc to create pure SystemC output not requiring SystemPerl. +* Add --pins64 to create 64 bit SystemC outputs instead of sc_bv<64>. +* The --exe flag is now required to produce executables inside the makefile. + This was previously the case any time .cpp files were passed on the + command line. +* Add -O3 and --inline-mult for performance tuning. [Ralf Karge] + One experiment regained 5% performance, at a cost of 300% in compile time. -**** Fix removal of empty packages, modules and cells. (#1034) [Johan Bjork] +**Minor:** -**** Fix core dump on Arch Linux/GCC 6.1.1. (#1058) [Jannis Harder] +* Improved performance of large case/always statements with low fanin + by converting to internal lookup tables (ROMs). +* Initialize SystemC port names. [S Shuba] +* Add Doxygen comments to Verilated includes. +* Fix -cc pins 8 bits wide and less to be uint8_t instead of uint16_t. +* Fix crash when Mdir has same name as .v file. [Gernot Koch] +* Fix crash with size mismatches on case items. [Gernot Koch] -**** Fix $value$plusargs to string. (#1880) [Frederic Requin] +Verilator 3.340 2005-02-18 Stable +================================= -* Verilator 3.882 2016-03-01 +**Minor:** -**** Internal Verilation-time performance enhancements. (#1021) [Johan Bjork] +* Report misconnected pins across all modules, instead of just first error. +* Improved large netlist compile times. +* Fix over-active inlining, resulting in compile slowness. -**** Support inlining interfaces. (#1018) [Johan Bjork] -**** Support SV strings to readmemh. (#1040) [Stefan Wallentowitz] +Verilator 3.332 2005-01-27 +========================== -**** Fix unrolling complicated for-loop bounds. (#677) [Johan Bjork] +**Major:** -**** Fix stats file containing multiple unroll entries. (#1020) [Johan Bjork] +* Add -E preprocess only flag, similar to GCC. +* Add CMPCONSTLR when comparison is constant due to > or < with all ones. -**** Fix using short parameter names on negative params. (#1022) [Duraid Madina] +**Minor:** -**** Fix read-after-free error. (#1031) [Johan Bjork] +* Fix loss of first -f file argument, introduced in 3.331. -**** Fix elaboration-time display warnings. (#1032) [Johan Bjork] -**** Fix crash on very deep function trees. (#1028) [Jonathan Kimmitt] +Verilator 3.331 2005-01-18 +========================== -**** Fix slicing mix of big and little-endian. (#1033) [Geoff Barrett] +**Major:** -**** Fix pattern assignment width propagation. (#1037) [Johan Bjork] +* The Verilog::Perl preprocessor is now C++ code inside of Verilator. + This improves performance, makes compilation easier, and enables + some future features. +**Minor:** -* Verilator 3.880 2015-12-19 +* Support arrays of instantiations (non-primitives only). [Wim Michiels] +* Fix unlinked error with defparam. [Shawn Wang] -*** Support display %u, %v, %p, %z. (#989) [Johan Bjork] -**** Fix real parameters causing bad module names. (#992) [Johan Bjork] +Verilator 3.320 2004-12-10 +========================== -**** Fix size-changing cast on packed struct. (#993) [Johan Bjork] +**Major:** -**** Fix function calls on arrayed interface. (#994) [Johan Bjork] +* NEWS is now renamed Changes, to support CPAN indexing. +* If Verilator is passed a C file, create a makefile link rule. + This saves several user steps when compiling small projects. -**** Fix arrayed interfaces. (#879) (#1001) [Todd Strader] +**Minor:** -**** Fix constant function assigned to packed structs. (#997) [Johan Bjork] +* Add new COMBDLY warning in place of fatal error. [Shawn Wang] +* Fix mis-simulation with wide-arrays under bit selects. [Ralf Karge] +* Add NC Verilog as alternative to VCS for reference tests. +* Support implicit wire declarations on input-only signals. + (Dangerous, as leads to wires without drivers, but allowed by spec.) +* Fix compile warnings on Suse 9.1 -**** Fix interface inside generate. (#998) [Johan Bjork] -**** Fix $signed casts under generates. (#999) [Clifford Wolf] +Verilator 3.311 2004-11-29 +========================== -**** Fix genvar constant propagation. (#1003) [Johan Bjork] +**Major:** -**** Fix parameter constant propagation from package. (#1004) [Johan Bjork] +* Support implicit wire declarations (as a warning). [Shawn Wang] -**** Fix array slicing of non-const indexes. (#1006) [Johan Bjork] +**Minor:** -**** Fix dotted generated array error. (#1005) [Jeff Bush, Johan Bjork] +* Fix over-shift difference in Verilog vs C++. [Ralf Karge] -**** Fix error instead of warning on large concat. (#1865) [Paul Rolfe] -**** Fix $bitstoreal constant propagation. (#1012) [Jonathan Kimmitt] +Verilator 3.310 2004-11-15 +========================== -**** Fix model restore crash. (#1013) [Jason McMullan] +**Major:** -**** Fix arrayed instances to unpacked of same size. (#1015) [Varun Koyyalagunta] +* Support defparam. +* Support gate primitives: buf, not, and, nand, or, nor, xor, xnor. -**** Fix slices of unpacked arrays with non-zero LSBs. +**Minor:** -**** Fix ternary operation with unpacked array. (#1017) [Varun Koyyalagunta]. +* Ignore all specify blocks. -* Verilator 3.878 2015-11-01 +Verilator 3.302 2004-11-12 +========================== -** Add --vpi flag, and fix VPI linkage. (#969) [Arthur Kahlich] +**Minor:** -** Support genvar indexes into arrayed cells. (#517) [Todd Strader] +* Support NAND and NOR operators. +* Better warnings when port widths don't match. +* Fix internal error due to some port width mismatches. [Ralf Karge] +* Fix WIDTH warnings on modules that are only used + parameterized, not in 'default' state. +* Fix selection of SystemC library on cygwin systems. [Shawn Wang] +* Fix runtime bit-selection of parameter constants. -** Support $sformatf. (#977) [Johan Bjork] -*** Support elaboration assertions. (#973) [Johan Bjork] +Verilator 3.301 2004-11-04 +========================== -*** Support $display with non-format arguments. (#467) [Jamey Hicks] +**Minor:** -**** Add VerilatedScopeNameMap for introspection. (#966) [Todd Strader] +* Fix 64 bit [31:0] = {#{}} mis-simulation. [Ralf Karge] +* Fix shifts greater then word width mis-simulation. [Ralf Karge] +* Fix to work around GCC 2.96 negation bug. -**** Ignore %l in $display. (#983) [Todd Strader] -**** Fix very long module names. (#937) [Todd Strader] +Verilator 3.300 2004-10-21 +========================== -**** Fix internal error on dotted refs into generates. (#958) [Jie Xu] +**Major:** -**** Fix structure parameter constant propagation. (#968) [Todd Strader] +* New backend that eliminates most VL_ macros. + Improves performance 20%-50%, depending on frequency of use of signals + over 64 bits. GCC compile times with -O2 shrink by a factor of 10. -**** Fix enum constant propagation. (#970) [Todd Strader] +**Minor:** -**** Fix mis-optimizing public DPI functions. (#963) [Wei Song] +* Fix "setting unsigned int from signed value" warning. -**** Fix package:scope.scope variable references. -**** Fix $fwrite to constant stderr/stdout. (#961) [Wei Song] +Verilator 3.271 2004-10-21 +========================== -**** Fix struct.enum.name method calls. (#855) [Jonathon Donaldson] +**Minor:** -**** Fix dot indexing into arrayed inferfaces. (#978) [Johan Bjork] +* Fix "loops detected" error with some negedge clocks. +* Fix some output code spacing issues. -**** Fix crash in commandArgsPlusMatch. (#987) [Jamie Iles] -**** Fix error message on missing interface. (#985) [Todd Strader] +Verilator 3.270 2004-10-15 +========================== +**Minor:** -* Verilator 3.876 2015-08-12 +* Support Verilog 2001 parameters in module headers. [Ralf Karge] +* Faster code to support compilers not inlining all Verilated functions. +* Fix numeric fault when dividing by zero. -*** Add tracing_on, etc to vlt files. (#932) [Frederic Requin] -**** Support extraction of enum bits. (#951) [Jonathon Donaldson] -**** Fix MinGW compiler error. (#927) (#929) [Hans Tichelaar] +Verilator 3.260 2004-10-07 +========================== -**** Fix .c files to be treated as .cpp. (#930) [Jonathon Donaldson] +**Major:** -**** Fix string-to-int space conversion. (#931) [Fabrizio Ferrandi] +* Support Verilog 2001 named parameter instantiation. [Ralf Karge] -**** Fix dpi imports inside generates. [Michael Tresidder] +**Minor:** -**** Fix rounding in trace $timescale. (#946) [Frederic Requin] +* Return 1's when one bit wide extract indexes outside array bounds. +* Fix compile warnings on 64-bit operating systems. +* Fix incorrect dependency in .d file when setting VERILATOR_BIN. -**** Fix $fopen with SV string. (#947) [Sven Stucki] -**** Fix hashed error with typedef inside block. (#948) [Sven Stucki] +Verilator 3.251 2004-09-09 +========================== -**** Fix makefile with --coverage. (#953) [Eivind Liland] +**Minor:** -**** Fix coverage documentation. (#954) [Thomas J Whatson] +* Fix parenthesis overflow in Microsoft Visual C++ [Renga Sundararajan] -**** Fix parameters with function parameter arguments. (#952) [Jie Xu] -**** Fix size casts as second argument of cast item. (#950) [Jonathon Donaldson] +Verilator 3.250 2004-08-30 +========================== +**Major:** -* Verilator 3.874 2015-06-06 +* Support Microsoft Visual C++ [Renga Sundararajan] -*** Add pkg-config .pc file. (#919) [Stefan Wallentowitz] +**Minor:** -**** Fix installing missing manpages. (#908) [Ahmed El-Mahmoudy] +* SystemPerl 1.161+ is required. -**** Fix sign extension in large localparams. (#910) [Mike Thyer] -**** Fix core dump in sync-async warnings. (#911) [Sebastian Dressler] +Verilator 3.241 2004-08-17 +========================== -**** Fix truncation warning with -pins-bv. (#912) [Alfonso Martinez] +**Minor:** -**** Fix Cygwin uint32 compile. (#914) [Matthew Barr] +* Support ,'s to separate multiple assignments. [Paul Nitza] +* Fix shift sign extension problem using non-GCC compilers. -**** Fix preprocessing stringified newline escapes. (#915) [Anton Rapp] -**** Fix part-select in constant function. (#916) [Andrew Bardsley] +Verilator 3.240 2004-08-13 +========================== -**** Fix width extension on mis-width ports. (#918) [Patrick Maupin] +**Major:** -**** Fix width propagation on sized casts. (#925) [Jonathon Donaldson] +* Verilator now uses 64 bit math where appropriate. + Inputs and outputs of 33-64 bits wide to the C++ Verilated model must + now be uint64_t's; SystemC has not changed, they will remain sc_bv's. + This increases performance by ~ 9% on x86 machines, varying with how + frequently 33-64 bit signals occur. Signals 9-16 bits wide are now + stored as 16 bit shorts instead of longs, this aids cache packing. -**** Fix MSVC++ compiler error. (#927) [Hans Tichelaar] +**Minor:** +* Fix SystemC compile error with feedthrus. [Paul Nitza] +* Fix concat value error introduced in 3.230. -* Verilator 3.872 2015-04-05 -*** Add VerilatedVcdFile to allow real-time waveforms. (#890) [HyungKi Jeong] +Verilator 3.230 2004-08-10 +========================== -*** Add --clk and related optimizations. (#1840) [Jie Xu] +**Minor:** -*** Fix order of C style arrays. [Duraid Madina] +* Add coverage output to test_sp example, SystemPerl 1.160+ is required. +* Fix time 0 value of signals. [Hans Van Antwerpen] + Earlier versions would not evaluate some combinatorial signals + until posedge/negedge blocks had been activated. +* Fix wide constant inputs to public submodules [Hans Van Antwerpen] +* Fix wide signal width extension bug. + Only applies when width mismatch warnings were overridden. -**** Add --dump-treei-. (#894) [Jie Xu] -**** Fix comma-instantiations with parameters. (#884) [Franck Jullien] +Verilator 3.220 2004-06-22 +========================== -**** Fix SystemC arrayed bit vectors. (#886) [David Poole] +**Major:** -**** Fix compile error on MinGW. (#887) [HyungKi Jeong] +* Many waveform tracing changes: +* Tracing is now supported on C++ standalone simulations. [John Brownlee] +**Minor:** -* Verilator 3.870 2015-02-12 +* When tracing, SystemPerl 1.150 or newer is required. +* When tracing, Verilator must be called with the --trace switch. +* Add SystemPerl example to documentation. [John Brownlee] +* Various Cygwin compilation fixes. [John Brownlee] -**** Suppress COMBDLY when inside always_latch. (#864) [Iztok Jeras] -**** Support cast operator with expression size. (#865) [Iztok Jeras] +Verilator 3.210 2004-04-01 +========================== -**** Add warning on slice selection out of bounds. (#875) [Cong Van Nguyen]. +**Major:** -**** Fix member select error broke in 3.868. (#867) [Iztok Jeras] +* Compiler optimization switches have changed + See the BENCHMARKING section of the documentation. +* With Verilog-Perl 2.3 or newer, Verilator supports SystemVerilog + preprocessor extensions. -**** Fix $sccanf from string. (#866) [David Pierce] +**Minor:** -**** Fix VM_PARALLEL_BUILDS broke in 3.868. (#870) [Hiroki Honda] +* Add localparam. [Thomas Hawkins] +* Add warnings for SystemVerilog reserved words. -**** Fix non-ANSI modport instantiations. (#868) [Kevin Thompson] -**** Fix UNOPTFLAT change detect on multidim arrays. (#872) [Andrew Bardsley] +Verilator 3.203 2004-03-10 +========================== -**** Fix slice connections of arrays to ports. (#880) [Varun Koyyalagunta] +**Minor:** -**** Fix mis-optimizing gate assignments in unopt blocks. (#881) [Mike Thyer] +* Notes and repairs for Solaris. [Fred Ma] -**** Fix sign extension of pattern members. (#882) [Iztok Jeras] -**** Fix clang compile warnings. +Verilator 3.202 2004-01-27 +========================== +**Major:** -* Verilator 3.868 2014-12-20 +* The beta version is now the primary release. See below for many changes. + If you have many problems, you may wish to try release 3.125. +* Verilated::traceEverOn(true) must be called at time 0 if you will ever + turn on tracing (waveform dumping) of signals. Future versions will + need this switch to disable trace incompatible optimizations. -** New verilator_coverage program added to replace SystemPerl's vcoverage. +**Minor:** -** PSL support was removed, please use System Verilog assertions. +* Optimize common replication operations. +* Fix several tracing bugs -** SystemPerl mode is deprecated and now untested. -*** Support enum.first/name and similar methods. (#460) (#848) +Verilator 3.201-beta 2003-12-10 +========================== -*** Add 'string' printing and comparisons. (#746) (#747) etc. +**Major:** -*** Inline C functions that are used only once. (#1838) [Jie Xu] +* BETA VERSION, USE 3.124 for stable release! +* Version 3.2XX includes a all new back-end. + This includes automatic inlining, flattening of signals between + hierarchy, and complete ordering of statements. This results in + 60-300% execution speedups, though less pretty C++ output. Even + better results are possible using GCC 3.2.2 (part of Redhat 9.1), as + GCC has fixed some optimization problems which Verilator exposes. -*** Fix tracing SystemC signals with structures. (#858) [Eivind Liland] - Note that SystemC traces will no longer show the signals - in the wrapper, they can be seen one level further down. + If you are using `systemc_ctor, beware pointers to submodules are now + initialized after the constructor is called for a module, to avoid + segfaults, move statements that reference subcells into initial + statements. +* C++ Constructor that creates a verilog module may take a char* name. + This name will be used to prefix any $display %m arguments, so users may + distinguish between multiple Verilated modules in a single executable. -**** Add --stats-vars. (#851) [Jeremy Bennett] -**** Fix bare generates in interfaces. (#789) [Bob Newgard] +Verilator 3.125 2004-01-27 +========================== -**** Fix underscores in real literals. (#863) [Jonathon Donaldson] +**Minor:** +* Optimize bit replications -* Verilator 3.866 2014-11-15 -*** Fix +define+A+B to define A and B to match other simulators. (#847) [Adam Krolnik] +Verilator 3.124 2003-12-05 +========================== -*** Add optimization of wires from arrayed cells. (#1831) [Jie Xu] +**Major:** -*** Add optimization of operators between concats. (#1831) [Jie Xu] +* A optimized executable will be made by default, in addition to a debug + executable. Invoking Verilator with --debug will pick the debug version. -*** Add public enums. (#833) [Jonathon Donaldson] +**Minor:** -*** Trace_off now operates on cells. (#826) [Lane Brooks] +* Many minor invisible changes to support the next version. -**** Fix public parameters in unused packages. (#804) [Jonathon Donaldson] -**** Fix select when partially out-of-bound. (#823) [Cliffort Wolf] +Verilator 3.123 2003-11-10 +========================== -**** Fix generate unrolling with function call. (#830) [Steven Slatter] +**Minor:** -**** Fix cast-to-size context-determined sizing. (#828) [Geoff Barrett] +* Wide bus performance enhancements. +* Fix function call bug when width warning suppressed. [Leon Wildman] +* Fix __DOT__ compile problem with funcs in last revision. [Leon Wildman] -**** Fix not tracing modules following primitives. (#837) [Jie Xu] -**** Fix trace overflow on huge arrays. (#834) [Geoff Barrett] +Verilator 3.122 2003-10-29 +========================== -**** Fix quoted comment slashes in defines. (#845) [Adam Krolnik] +**Major:** +* Modules which are accessed from external code now must be marked with + /*verilator public_module*/ unless they already contain public signals. + To enforce this, private cell names now have a string prepended. -* Verilator 3.864 2014-09-21 +**Minor:** -*** Support power operator with real. (#809) [Jonathon Donaldson] +* Fix replicated function calls in one statement. [Robert A. Clark] +* Fix function call bug when width warning suppressed. [Leon Wildman] -**** Improve verilator_profcfunc time attributions. [Jonathon Donaldson] -**** Fix duplicate anonymous structures in $root. (#788) [Bob Newgard] +Verilator 3.121 2003-09-29 +========================== -**** Fix mis-optimization of bit-swap in wide signal. (#800) [Jie Xu] +**Minor:** -**** Fix error when tracing public parameters. (#722) [Jonathon Donaldson] +* Support multiplication over 32 bits. [Chris Boumenot] + Also improved speed of addition and subtraction over 32 bits. +* Detect bit selection out of range errors. +* Detect integer width errors. +* Fix width problems on function arguments. [Robert A. Clark] -**** Fix dpiGetContext in dotted scopes. (#740) [Geoff Barrett] -**** Fix over-shift structure optimization error. (#803) [Jeff Bush] +Verilator 3.120 2003-09-24 +========================== -**** Fix optional parameter keyword in module #(). (#810) [Iztok Jeras] +**Minor:** -**** Fix $warning/$error multi-argument ordering. (#816) [Jonathon Donaldson] +* $finish now exits the model (via vl_finish function). +* Support inputs/outputs in tasks. +* Support V2K "integer int = {INITIAL_VALUE};" +* Ignore floating point delay values. [Robert A. Clark] +* Ignore `celldefine, `endcelldefine, etc. [Robert A. Clark] +* Optimize reduction operators. +* Fix converting "\ooo" into octal values. +* Fix $display("%x"); -**** Fix clang warnings. (#818) [Iztok Jeras] -**** Fix string formats under deep expressions. (#820) [Iztok Jeras] +Verilator 3.112 2003-09-16 +========================== +**Minor:** -* Verilator 3.862 2014-06-10 +* Fix functions in continuous assignments. [Robert A. Clark] +* Fix inlining of modules with 2-level deep outputs. -*** Using command line -Wno-{WARNING} now overrides file-local lint_on. -*** Add -P to suppress `line and blanks with preprocessing. (#781) [Derek Lockhart] +Verilator 3.111 2003-09-15 +========================== -*** Support SV 2012 package import before port list. +**Minor:** -**** Change SYMRSVDWORD to print as warning rather than error. +* Fix declaration of functions before using that module. [Robert A. Clark] +* Fix module inlining bug with outputs. -**** Fix seg-fault with variable of parameterized interface. (#692) [Jie Xu] -**** Fix false name conflict on cells in generate blocks. (#749) [Igor Lesik] +Verilator 3.110 2003-09-12 +========================== -**** Fix pattern assignment to basic types. (#767) [Jie Xu] +**Major:** -**** Fix pattern assignment to conditionals. (#769) [Jie Xu] +* Support Verilog 2001 style input/output declarations. [Robert A. Clark] +* Support local vars in headers of function/tasks. [Leon Wildman] -**** Fix shift corner-cases. (#765) (#766) (#768) (#772) (#774) (#776) [Clifford Wolf] -**** Fix C compiler interpreting signing. (#773) [Clifford Wolf] +Verilator 3.109 2003-08-28 +========================== -**** Fix late constant division by zero giving X error. (#775) [Clifford Wolf] +**Major:** -**** Fix gate primitives with arrays and non-arrayed pins. +* Support local variables in named begin blocks. [Leon Wildman] -**** Fix DETECTARRAY error on packed arrays. (#770) [Jie Xu] -**** Fix ENDLABEL warnings on escaped identifiers. +Verilator 3.108 2003-08-11 +========================== -**** Fix string corruption. (#780) [Derek Lockhart] +**Major:** +* Support functions. -* Verilator 3.860 2014-05-11 +**Minor:** -** PSL is no longer supported, please use System Verilog assertions. +* Signals 8 bits and shorter are now stored as chars + instead of uint32_t's. This improves Dcache packing and + improves performance by ~7%. +* $display now usually results in a single VL_PRINT rather then many. +* Optimize conditionals (?:) -** Support '{} assignment pattern on arrays. (#355) -** Support streaming operators. (#649) [Glen Gibb] +Verilator 3.107 2003-07-15 +========================== -** Fix expression problems with -Wno-WIDTH. (#729) (#736) (#737) (#759) - Where WIDTH warnings were ignored this might result in different - warning messages and results, though it should better match the spec. - [Clifford Wolf] +**Major:** -*** Add --no-trace-params. +* --private and --l2name are now the default, + as this enables additional optimizations. + Use --noprivate or --nol2name to get the older behavior. -*** Add assertions on 'unique if'. (#725) [Jeff Bush] +**Minor:** -*** Add PINCONNECTEMPTY warning. [Holger Waechtler] +* Now support $display of binary and wide format data. +* Add detection of incomplete case statements, + and added related optimizations worth ~4%. +* Work around flex bug in Redhat 8.0. [Eugene Weber] +* Add some additional C++ reserved words. +* Additional constant optimizations, ~5% speed improvement. -*** Support parameter arrays. (#683) [Jeremy Bennett] -*** Fix begin_keywords "1800+VAMS". (#1806) +Verilator 3.106 2003-06-17 +========================== -**** Documentation fixes. (#723) [Glen Gibb] +**Major:** -**** Support {} in always sensitivity lists. (#745) [Igor Lesik] +* $c can now take multiple expressions as arguments. + For example $c("foo","bar(",32+1,");") will insert "foobar(33);" + This makes it easier to pass the values of signals. +* Several changes to support future versions that may have + signal-eliminating optimizations. Users should try to use these switch + on designs, they will become the default in later versions. +* Add --private switch and /*verilator public*/ metacomment. + This renames all signals so that compile errors will result if any + signals referenced by C++ code are missing a /*verilator public*/ + metacomment. +* With --l2name, the second level cell C++ cell is now named "v". + Previously it was named based on the name of the verilog code. This + means to get to signals, scope to "{topcell} ->v ->{mysignal}" instead + of "{topcell} ->{verilogmod}. {mysignal}". This allows different + modules to be substituted for the cell without requiring source + changes. -**** Fix tracing of package variables and real arrays. +**Minor:** -**** Fix tracing of packed arrays without --trace-structs. (#742) [Jie Xu] +* Several cleanups for Redhat 8.0. -**** Fix missing coverage line on else-if. (#727) [Sharad Bagri] -**** Fix modport function import not-found error. +Verilator 3.105 2003-05-08 +========================== -**** Fix power operator calculation. (#730) (#735) [Clifford Wolf] +**Minor:** -**** Fix reporting struct members as reserved words. (#741) [Chris Randall] +* Fix more GCC 3.2 errors. [David Black] -**** Fix change detection error on unions. (#758) [Jie Xu] -**** Fix -Wno-UNOPTFLAT change detection with 64-bits. (#762) [Clifford Wolf] +Verilator 3.104 2003-04-30 +========================== -**** Fix shift-right optimization. (#763) [Clifford Wolf] +**Major:** -**** Fix Mac OS-X test issues. [Holger Waechtler] +* Indicate direction of ports with VL_IN and VL_OUT. +* Allow $c32, etc, to specify width of the $c statement for VCS. +* Numerous performance improvements, worth about 25% -**** Fix C++-2011 warnings. +**Minor:** +* Fix false "indent underflow" error inside `systemc_ctor sections. +* Fix missing ordering optimizations when outputs also used internally. +* Assign constant cell pins in initial blocks rather then every cycle. +* Promote subcell's combo logic to sequential evaluation when possible. +* Fix GCC 3.2 compile errors. [Narayan Bhagavatula] -* Verilator 3.856 2014-03-11 -*** Support case inside. (#708) [Jan Egil Ruud] +Verilator 3.103 2003-01-28 +========================== -*** Add parameters into trace files. (#706) [Alex Solomatnikov] +**Minor:** -**** Fix parsing "#0 'b0". (#256) +* Fix missing model evaluation when clock generated several levels of + hierarchy across from where it is used as a clock. [Richard Myers] +* Fix sign-extension bug introduced in 3.102. -**** Fix array bound checks on real variables. -**** Fix --skip-identical mis-detecting on OS-X. (#707) +Verilator 3.102 2003-01-24 +========================== -**** Fix missing VL_SHIFTRS_IQI with WIDTH warning. (#714) [Fabrizio Ferrandi] +**Minor:** -**** Fix signed shift right optimization. (#715) [Fabrizio Ferrandi] +* Fix sign-extension of X/Z's ("32'hx") -**** Fix internal error on "input x =" syntax error. (#716) [Lane Brooks] -**** Fix slice extraction from packed array. (#717) [Jan Egil Ruud] +Verilator 3.101 2003-01-13 +========================== -**** Fix inside statement EQWILD error. (#718) [Jan Egil Ruud] +**Minor:** +* Fix 'parameter FOO=#'bXXXX' [Richard Myers] +* Allow spaces inside numbers ("32'h 1234") [Sam Gladstone] -* Verilator 3.855 2014-01-18 -*** Support modport import. (#696) [Jeremy Bennett] +Verilator 3.100 2002-12-23 +========================== -*** Add --trace-structs to show struct names. (#673) [Chris Randall] +**Major:** -**** Fix tracing of packed structs. (#705) [Jie Xu] +* Support for simple tasks w/o vars or I/O. [Richard Myers] -**** Fix --lint-only with MinGW. (#1813) [HyungKi Jeong] +**Minor:** -**** Fix some delayed assignments of typedefed unpacked arrays. +* Ignore DOS carriage returns in Linux files. [Richard Myers] -**** Fix wire declarations with size and not range. (#466) [Alex Solomatnikov] -**** Fix parameter pin vs. normal pin error. (#704) [Alex Solomatnikov] +Verilator 3.012 2002-12-18 +========================== +**Minor:** -* Verilator 3.854 2013-11-26 +* Fix parsing bug with casex statements containing case items + with bit extracts of parameters. [Richard Myers] +* Fix bug which could cause writes of non-power-of-2 sized arrays to + corrupt memory beyond the size of the array. [Dan Lussier] +* Fix bug which did not detect UNOPT problems caused by + submodules. See the description in the verilator man page. [John Deroo] +* Fix compile with threaded Perl. [Ami Keren] -*** Add UNPACKED warning to convert unpacked structs. [Jeremy Bennett] -*** Add --compiler clang to work around compiler bug. (#694) [Stefan Ludwig] +Verilator 3.010 2002-11-03 +========================== -**** Support vpi_get of vpiSuppressVal. (#687) [Varun Koyyalagunta] +**Major:** -**** Support vpi_get_time. (#688) [Varun Koyyalagunta] +* Support SystemC 2.0.1. SystemPerl version 1.130 or newer is required. -**** Fix evaluation of chained parameter functions. (#684) [Ted Campbell] +**Minor:** -**** Fix enum value extension of '1. +* Fix bug with inlined modules under other inlined modules. [Scott Bleiweiss] -**** Fix multiple VPI variable callbacks. (#679) [Rich Porter] -**** Fix vpi_get of vpiSize. (#680) [Rich Porter] +Verilator 3.005 2002-10-21 +========================== -**** Fix vpi_remove_cb inside callback. (#689) [Varun Koyyalagunta] +**Minor:** -**** Fix crash with coverage of structures. (#691) [Eivind Liland] +* Fix X's in case (not casex/z) to constant propagate correctly. +* Fix missing include. [Kurachi] -**** Fix array assignment from const var. (#693) [Jie Xu] +Verilator 3.004 2002-10-10 +========================== -* Verilator 3.853 2013-09-30 +**Minor:** -**** Add --no-order-clock-delay to work around #613. [Charlie Brej] +* Add /* verilator module_inline */ and associated optimizations. +* Allow /* verilator coverage_block_off */ in place of `coverage_block_off. + This prevents problems with Emacs AUTORESET. [Ray Strouble] +* Fix `coverage_block_off also disabling subsequent blocks. +* Fix unrolling of loops with multiple simple statements. +* Fix compile warnings on newer GCC. [Kurachi] +* Additional concatenation optimizations. -* Verilator 3.852 2013-09-29 +Verilator 3.003 2002-09-13 +========================== -*** Support named function and task arguments. [Chris Randall] +**Minor:** -*** Report SELRANGE warning for non-generate if. (#675) [Roland Kruse] +* Now compiles on Windows 2000 with Cygwin. +* Fix bug with pin assignments to wide memories. +* Optimize wire assignments to constants. -**** Fix ordering of $fgetc. (#1808) [Frederic Requin] -**** Fix --output-split-cfunc to count internal functions. [Chris Randall] +Verilator 3.002 2002-08-19 +========================== -**** Fix crash on 32-bit Ubuntu. (#670) [Mark Jackson Pulver] +**Major:** +* First public release of version 3. -* Verilator 3.851 2013-08-15 -*** Fix ordering of clock enables with delayed assigns. (#613) [Jeremy Bennett] +Verilator 3.000 2002-08-03 +========================== -*** Fix vpi_iterate on memory words. (#655) [Rich Porter] +**Major:** -**** Fix final duplicate declarations when non-inlined. (#661) [Charlie Brej] +* All new code base. Many changes too numerous to mention. -**** Fix interface ports with comma lists. (#1779) [Ed Lander] +**Minor:** -**** Fix parameter real conversion from integer. +* Approximately 4 times faster then Verilator 2. +* Support initial statements +* Support correct blocking/nonblocking assignments +* Support `defines across multiple modules +* Optimize call ordering, constant propagation, and dead code elimination. -**** Fix clang warnings. (#668) [Yutetsu Takatsukasa] +Verilator 2.1.8 2002-04-03 +========================== -* Verilator 3.850 2013-06-02 +**Major:** -** Support interfaces and modports. (#102) [Byron Bradley, Jeremy Bennett] +* All applications must now link against include/verilated.cpp -*** Duplicate clock gate optimization on by default. (#621) +**Minor:** -**** Fix arrayed input compile error. (#645) [Krzysztof Jankowski] +* Paths specified to verilator_make should be absolute, or be formed + to allow for execution in the object directory (prepend ../ to each path.) + This allows relative filenames for makes which hash and cache dependencies. +* Add warning when parameter constants are too large. [John Deroo] +* Add warning when x/?'s used in non-casez statements. +* Add warning when blocking assignments used in posedge blocks. [Dan Lussier] +* Split evaluation function into clocked and non-clocked, 20% perf gain. -**** Fix GCC version runtime changes. (#651) [Jeremy Bennett] -**** Fix packed array select internal error. (#652) [Krzysztof Jankowski] +Verilator 2.1.5 2001-12-01 +========================== +**Major:** -* Verilator 3.847 2013-05-11 +* Add coverage analysis. In conjunction with SystemC provide line + coverage reports, without SystemC, provide a hook to user written + accumulation function. See --coverage option of verilator_make. -*** Add ALWCOMBORDER warning. [KC Buckenmaier] +**Minor:** -*** Add --pins-sc-uint and --pins-sc-biguint. (#638) [Alex Hornung] +* Relaxed multiply range checking +* Support for constants up to 128 bits +* Randomize values used when assigning to X's. +* Add -guard option of internal testing. +* Changed indentation in emitted code to be automatically generated. +* Fix corruption of assignments of signal over 32 bits with non-0 lsb. -**** Support "signal[vec]++". -**** Fix simulation error when inputs and MULTIDRIVEN. (#634) [Ted Campbell] +Verilator 2.1.4 2001-11-16 +========================== -**** Fix module resolution with __. (#631) [Jason McMullan] +**Major:** -**** Fix packed array non-zero right index select crash. (#642) [Krzysztof Jankowski] +* Add $c("c_commands();"); for embedding arbitrary C code in Verilog. -**** Fix nested union crash. (#643) [Krzysztof Jankowski] +Verilator 2.1.3 2001-11-03 +========================== -* Verilator 3.846 2013-03-09 +**Major:** -** IEEE 1800-2012 is now the default language. This adds 4 new keywords - and updates the svdpi.h and vpi_user.h header files. +* Support for parameters. -*** Add --report-unoptflat. (#611) [Jeremy Bennett] -*** Add duplicate clock gate optimization. (#1772) [Varun Koyyalagunta] - Disabled unless -OD or -O3 used, please try it as may get some - significant speedups. +Verilator 2.1.2 2001-10-25 +========================== -*** Fix wrong dot resolution under inlining. [Art Stamness] +**Major:** -**** Support pattern assignment features. (#616) (#617) (#618) [Ed Lander] +* Verilog Errors now reference the .v file rather then the .vpp file. -**** Support bind in $unit. (#602) [Ed Lander] +**Minor:** -**** Support '() sized casts. (#628) [Ed Lander] +* Support strings in assignments: reg [31:0] foo = "STRG"; +* Support %m in format strings. Ripped out old $info support, use + Verilog-Perl's vpm program instead. +* Convert $stop to call of v_stop() which user can define. +* Fix bug where a==b==c would have wrong precedence rule. +* Fix bug where XNOR on odd-bit-widths (~^ or ^~) had bad value. -**** Fix DETECTARRAY on packed structures. (#610) [Jeremy Bennett] -**** Fix LITENDIAN on unpacked structures. (#614) [Wai Sum Mong] +Verilator 2.1.1 2001-05-17 +========================== -**** Fix 32-bit OS VPI scan issue. (#615) [Jeremy Bennett, Rich Porter] +**Major:** -**** Fix opening a VerilatedVcdC file multiple times. (#1774) [Frederic Requin] +* New test_sp directory for System-Perl (SystemC) top level instantiation + of the Verilated code, lower modules are still C++ code. (Experimental). +* New test_spp directory for Pure System-Perl (SystemC) where every module + is true SystemC code. (Experimental) -**** Fix UNOPTFLAT circular array bounds crossing. (#630) [Jie Xu] +**Minor:** +* Input ports are now loaded by pointer reference into the sub-cell. + This is faster on I-386 machines, as the stack must be used when there are + a large number of parameters. Also, this simplifies debugging as the value + of input ports exists for tracing. +* Many code cleanups towards standard C++ style conventions. -* Verilator 3.845 2013-02-04 -*** Fix nested packed arrays and struct. (#600) [Jeremy Bennett] - Packed arrays are now represented as a single linear vector in - Verilated models. This may affect packed arrays that are public or - accessed via the VPI. +Verilator 2.1.0 2001-05-08 +========================== -*** Support wires with data types. (#608) [Ed Lander] +**Minor:** -*** Support bind, to module names only. (#602) [Ed Lander] +* Many code cleanups towards standard C++ style conventions. -*** Support VPI product info, warning calls, etc. (#588) [Rick Porter] -*** Support $left, $right and related functions. (#448) [Iztok Jeras] +Version history lost +==================== -*** Support inside expressions. -*** Define SYSTEMVERILOG, SV_COV_START and other IEEE mandated predefines. +Verilator 1.8 1996-07-08 +======================== -**** Fix pin width mismatch error. (#595) [Alex Solomatnikov] +[Versions 0 to 1.8 were by Paul Wasson] +* Fix single bit in concat from instance output incorrect offset bug. -**** Fix implicit one bit parameter selection. (#603) [Jeremy Bennett] -**** Fix signed/unsigned parameter misconversion. (#606) [Jeremy Bennett] +Verilator 1.7 1996-05-20 +======================== -**** Fix segfault on multidimensional dotted arrays. (#607) [Jie Xu] +* Mask unused bits of DONTCAREs. -**** Fix per-bit array output connection error. (#414) [Jan Egil Ruud] -**** Fix package logic var compile error. +Verilator 1.6 1996-05-13 +======================== -**** Fix enums with X values. +* Add fasttrace script -* Verilator 3.844 2013-01-09 +Verilator 1.5 1996-01-09 +======================== -*** Support "unsigned int" DPI import functions. (#1770) [Alex Lee] +* Pass structure pointer into translated code, so multiple instances can use same functions. +* Fix static value concat on casex items. -*** Fix package resolution of parameters. (#586) [Jeremy Bennett] -**** Fix non-integer vpi_get_value. (#587) [Rich Porter] +Verilator 1.1 1995-03-30 +======================== -**** Fix task inlining under $display and case. (#589) (#598) [Holger Waechtler] +* Bug fixes, added verimake_partial script, performance improvements. -**** Fix package import of non-localparam parameter. (#474) (#591) [Jeremy Bennett] -**** Fix package import of package imports, partial #592. [Jeremy Bennett] +Verilator 1.0c 1994-09-30 +========================= -**** Fix package import preventing local var. (#599) [Jeremy Bennett] +* Initial release of Verilator -**** Fix array extraction of implicit vars. (#601) [Joe Eiler] +Verilator 0.0 1994-07-08 +======================== -* Verilator 3.843 2012-12-01 +* First code written. -*** Add +1364-1995ext and similar language options. (#532) [Jeremy Bennett] +.. ---------------------------------------------------------------------- -**** Fix mis-optimized identical submodule subtract. (#581) [Charlie Brej] - -**** Fix crash on dotted references into dead modules. (#583) [Jeremy Bennett] - -**** Fix compile issues on MSVCC. (#571) (#577) [Amir Gonnen] - -**** Fix --debug overriding preceding --dump-treei. (#580) [Jeremy Bennett] - - -* Verilator 3.842 2012-11-03 - -**** Add -x-initial-edge. (#570) [Jeremy Bennett] - -**** Fix parameter pins interspersed with cells broke in 3.840. [Bernard Deadman] - -**** Fix large shift error on large shift constants. [David Welch] - -**** Fix $display mangling on GCC 4.7 and speed up. (#1765) (#373) (#574) [R Diez] - -**** Fix array of struct references giving false error. (#566) [Julius Baxter] - -**** Fix missing var access functions when no DPI. (#572) [Amir Gonnen] - -**** Fix name collision on unnamed blocks. (#567) [Chandan Egbert] - -**** Fix name collision on task inputs. (#569) [Chandan Egbert] - - -* Verilator 3.841 2012-09-03 - -*** Add --savable to support model save/restore. [Jeremy Bennett] - -*** Support '{} assignment pattern on structures, part of #355. - -**** Fix double-deep parameter cell WIDTHs. (#541) [Hiroki Honda] - -**** Fix imports under multiple instantiated cells. (#542) [Alex Solomatnikov] - -**** Fix defparam in generate broke in 3.840. (#543) [Alex Solomatnikov] - -**** Fix duplicate begin error broke in 3.840. (#548) [Alex Solomatnikov] - -**** Fix triangle symbol resolution error broke in 3.840. (#550) [Ted Campbell] - - -* Verilator 3.840 2012-07-31 Beta - -** Rewrote tristate handling; supports tri0, tri1, tristate bit selects, - concatenates and pullup/pulldowns. (#395) (#56) (#54) (#51) - [Alex Solomatnikov, Lane Brooks, et al] - -** Support packed structures and unions. (#181) - Note this was a major internal change that may lead to some instability. - -*** Support tri0 and tri1. (#462) [Alex Solomatnikov] - -*** Support nmos and pmos. (#488) [Alex Solomatnikov] - -*** Add INITIALDLY warning on initial assignments. (#478) [Alex Solomatnikov] - -*** Add PINMISSING and PINNOCONNECT lint checks. - -*** Add --converge-limit option. - -*** Fix generate operators not short circuiting. (#413) [by Jeremy Bennett] - -*** Fix parameters not supported in constant functions. (#474) [Alex Solomatnikov] - -**** Fix duplicate warnings/errors. (#516) [Alex Solomatnikov] - -**** Fix signed extending biops with WIDTH warning off. (#511) [Junji Hashimoto] - -**** Fix ITOD internal error on real conversions. (#491) [Alex Solomatnikov] - -**** Fix input and real loosing real data type. (#501) [Alex Solomatnikov] - -**** Fix imports causing symbol table error. (#490) [Alex Solomatnikov] - -**** Fix newlines in radix values. (#507) [Walter Lavino] - -**** Fix loop error message to report line. (#513) [Jeremy Bennett] - -**** Fix false UNUSED warning on file system calls. - -**** Fix GCC 4.7.0 compile warnings. (#530) [Jeremy Bennett] - -**** Fix svdpi.h compile error on Apple OS. - -**** Fix compile error under git submodules. (#534) [Aurelien Francillon] - - -* Verilator 3.833 2012-04-15 - -*** Support += and -= in standard for loops. (#463) [Alex Solomatnikov] - -*** Fix processing unused parametrized modules. (#469) (#470) [Alex Solomatnikov] - -**** Add SELRANGE as warning instead of error. (#477) [Alex Solomatnikov] - -**** Add readme.pdf and internal.pdf and doxygen. (#483) [by Jeremy Bennett] - -**** Fix change detections on arrays. (#364) [John Stevenson, Alex Solomatnikov] - -**** Fix signed array warning. (#456) [Alex Solomatnikov] - -**** Fix genvar and begin under generate. (#461) [Alex Solomatnikov] - -**** Fix real constant parameter functions. (#475) [Alex Solomatnikov] - -**** Fix and document --gdb option. (#454) [Jeremy Bennett] - -**** Fix OpenSolaris compile error. [Sanjay Singh] - - -* Verilator 3.832 2012-03-07 - -*** Fix memory delayed assignments from multiple clock domains. [Andrew Ling] - -*** Support arrayed SystemC I/O pins. [Christophe Joly] - -*** Report MULTIDRIVEN on memories set in multiple clock domains. - -*** Report ENDLABEL on mismatching end labels. (#450) [Iztok Jeras] - -**** Fix expansion of back-slashed escaped macros. (#441) [Alberto Del Rio] - -**** Fix inheriting real and signed type across untyped parameters. - -**** Fix core dump with over 100 deep UNOPTFLAT. (#432) [Joe Eiler] - -**** Fix false command not found warning in makefiles. [Ruben Diez] - -**** Fix hang when functions inside begin block. [David Welch] - -**** Fix hang on recursive substitution `defines. (#443) [Alex Solomatnikov] - - -* Verilator 3.831 2012-01-20 - -** Support SystemC 2.3.0 prerelease. This requires setting the new - SYSTEMC_INCLUDE and SYSTEMC_LIBDIR variables in place of now - deprecated SYSTEMC and SYSTEMC_ARCH. [Iztok Jeras] - -**** Suppress VARHIDDEN on dpi import arguments. [Ruben Diez] - -**** Support "generate for (genvar i=0; ...". [David Kravitz] - -**** Fix dpi exports with > 32 bit but < 64 bit args. (#423) [Chandan Egbert] - -**** Fix array of instantiations with sub-range output. (#414) [Jeremy Bennett] - -**** Fix BLKSEQ warnings on variables declared inside always. [Ruben Diez] - - -* Verilator 3.830 2011-11-27 - -** With "--language VAMS" support a touch of Verilog AMS. [Holger Waechtler] - -*** Add sc_bv attribute to force bit vectors. (#402) [by Stefan Wallentowitz] - -**** Search for user -y paths before default current directory. [Ruben Diez] - -**** Support constants in sensitivity lists. (#412) [Jeremy Bennett] - -**** Support $system. [Ruben Diez] - -**** Support $sscanf with %g. [Holger Waechtler] - -**** Indicate 'exiting due to errors' if errors, not warnings. [Ruben Diez] - -**** Fix bad result with if-else-return optimization. (#420) [Alex Solomatnikov] - -**** Fix reporting not found modules if generate-off. (#403) [Jeremy Bennett] - -**** Fix $display with %d following %g. [Holger Waechtler] - - -* Verilator 3.824 2011-10-25 - -*** Fix "always @ (* )". (#403) (#404) [Walter Lavino] - -*** Add ASSIGNIN as suppressable error. [Jeremy Bennett] - -**** Fix 3.823 constructor core dump on Debian. (#401) [Ahmed El-Mahmoudy] - - -* Verilator 3.823 2011-10-20 - -*** Support $ceil, $floor, etc. [Alex Solomatnikov] - -*** Add configure options for cc warnings and extended tests. [Ruben Diez] - -*** Add -Wall reporting ASSIGNDLY on assignment delays. [Ruben Diez] - -*** Fix UNDRIVEN warnings inside DPI import functions. [Ruben Diez] - -*** Fix --help output to go to stderr, not stdout. (#397) [Ruben Diez] - -**** Fix DPI import output of 64 bits. (#398) [Mike Denio] - -**** Fix DPI import false BLKSEQ warnings. [Alex Solomatnikov] - -**** Fix MSVC compile warning with trunc/round. (#394) [Amir Gonnen] - -**** Fix autoconf and Makefile warnings. (#396) [Ruben Diez] - - -* Verilator 3.821 2011-09-14 - -**** Fix PowerPC runtime error. (#288) [Ahmed El-Mahmoudy] - -**** Fix internal error on integer casts. (#374) [Chandan Egbert] - - -* Verilator 3.820 2011-07-28 - -** Support 'real' numbers and related functions. - -*** Support 'const' variables in limited cases; similar to enums. [Alex Solomatnikov] - -*** Support disable for loop escapes. - -*** Support $fopen and I/O with integer instead of `verilator_file_descriptor. - -*** Support coverage in -cc and -sc output modes. [John Li] - Note this requires SystemPerl 1.338 or newer. - -**** Fix vpi_register_cb using bad s_cb_data. (#370) [by Thomas Watts] - -**** Fix $display missing leading zeros in %0d. (#367) [Alex Solomatnikov] - -**** Use 'vluint64_t' for SystemC instead of (same sized) 'uint64' for MSVC++. - - -* Verilator 3.813 2011-06-28 - -*** Support bit vectors > 64 bits wide in DPI import and exports. - -*** Fix out of memory on slice syntax error. (#354) [Alex Solomatnikov] - -**** Fix error on enum references to other packages. (#339) [Alex Solomatnikov] - -**** Fix DPI undeclared svBitVecVal compile error. (#346) [Chandan Egbert] - -**** Fix DPI bit vector compile errors. (#347) (#359) [Chandan Egbert] - -**** Fix CDCRSTLOGIC report showing endpoint flops without resets. - -**** Fix compiler warnings on SPARC. (#288) [Ahmed El-Mahmoudy] - - -* Verilator 3.812 2011-04-06 - -*** Add --trace-max-width and --trace-max-array. (#319) [Alex Solomatnikov] - -*** Add --Wno-fatal to turn off abort on warnings. [by Stefan Wallentowitz] - -**** Support ${...} and $(...) env vars in .vc files. [by Stefan Wallentowitz] - -**** Support $bits(data_type). (#327) [Alex Solomatnikov] - -**** Support loop unrolling on width mismatches. (#333) [Joe Eiler] - -**** Support simple cast operators. (#335) [Alex Solomatnikov] - -**** Accelerate bit-selected inversions. - -**** Add error on circular parameter definitions. (#329) [Alex Solomatnikov] - -**** Fix concatenates and vectored bufif1. (#326) [Iztok Jeras] - - -* Verilator 3.811 2011-02-14 - -**** Report errors on duplicated or empty pins. (#321) [Christian Leber] - -**** Report error on function call output tied to constant. [Bernard Deadman] - -**** Throw UNUSED/UNDRIVEN only once per net in a parametrized module. - -**** Fix internal error on functions called as SV tasks. [Bernard Deadman] - -**** Fix internal error on non-inlined inout pins. [Jeff Winston] - -**** Fix false BLKSEQ on non-unrolled for loop indexes. [Jeff Winston] - -**** Fix block comment not separating identifiers. (#311) [Gene Sullivan] - -**** Fix warnings to point to lowest net usage, not upper level ports. - -**** Fix error on constants connected to outputs. (#323) [Christian Leber] - - -* Verilator 3.810 2011-01-03 - -** Add limited support for VPI access to public signals, see docs. - -*** Add -F option to read relative option files. (#297) [Neil Hamilton] - -*** Support ++,--,+= etc as standalone statements. [Alex Solomatnikov] - -**** When running with VERILATOR_ROOT, optionally find binaries under bin. - -**** Suppress WIDTH warnings when adding/subtracting 1'b1. - -** Add -Wall, -Wwarn-style, -Wno-style to enable code style warnings - that have been added to this release, and disabled by default: - -*** With --Wall, add BLKSEQ warning on blocking assignments in seq blocks. - -*** With --Wall, add DECLFILENAME warning on modules not matching filename. - -*** With --Wall, add DEFPARAM warning on deprecated defparam statements. - -*** With --Wall, add IFDEPTH warning on deep if statements. - -*** With --Wall, add INCABSPATH warning on `include with absolute paths. - -*** With --Wall, add SYNCASYNCNET warning on mixed sync/async reset nets. - -*** With --Wall, add UNDRIVEN warning on undriven nets. - -*** With --Wall, add UNUSED warning on unused nets. - -*** The VARHIDDEN warning is now disabled by default, use -Wall to enable. - - -* Verilator 3.805 2010-11-02 - -**** Add warning when directory contains spaces. (#1705) [Salman Sheikh] - -**** Fix wrong filename on include file errors. (#289) [Brad Parker] - -**** Fix segfault on SystemVerilog "output wire foo=0". (#291) [Joshua Wise] - -**** Fix DPI export name not found. (#1703) [Terry Chen] - - -* Verilator 3.804 2010-09-20 - -*** Support tracing/coverage of underscore signals. (#280) [by Jason McMullan] - -**** Fix preprocessor `` of existing base define. (#283) [Usha Priyadharshini] - -**** Increase define recursions before error. [Paul Liu] - -**** On core dump, print debug suggestions. - - -* Verilator 3.803 2010-07-10 - -*** Fix preprocessor preservation of newlines across macro substitutions. - -**** Fix preprocessor stringification of nested macros. - -**** Fix some constant parameter functions causing crash. (#253) [Nick Bowler] - -**** Fix do {...} while() not requiring final semicolon. - - -* Verilator 3.802 2010-05-01 - -*** Support runtime access to public signal names. - -*** Add /*verilator public_flat_rw*/ for timing-specific public access. - -*** Fix word size to match uint64_t on -m64 systems. (#238) [Joe Eiler] - -**** Improve error handling on slices of arrays. (#226) [by Byron Bradley] - -**** Report errors when extra underscores used in meta-comments. - -**** Fix bit reductions on multi-packed dimensions. (#227) [by Byron Bradley] - -**** Fix removing $fscanf if assigned to unused var. (#248) [Ashutosh Das] - -**** Fix "make install" with configure outside srcdir. [Stefan Wallentowitz] - -**** Fix loop unroller out of memory; change --unroll-stmts. [Ashutosh Das] - -**** Fix trace files with empty modules crashing some viewers. - -**** Fix parsing single files > 2GB. [Jeffrey Short] - -**** Fix installing data files as non-executable. (#168) [by Ahmed El-Mahmoudy] - - -* Verilator 3.801 2010-03-17 - -*** Support "break", "continue", "return". - -*** Support "`default_nettype none|wire". [Dominic Plunkett] - -**** Skip SystemC tests if not installed. [Iztok Jeras] - -**** Fix clock-gates with non-AND complex logic. (#220) [Ashutosh Das] - -**** Fix flushing VCD buffers on $stop. [Ashutosh Das] - -**** Fix Mac OS-X compile issues. (#217) [Joshua Wise, Trevor Williams] - -**** Fix make uninstall. (#216) [Iztok Jeras] - -**** Fix parametrized defines with empty arguments. - - -* Verilator 3.800 2010-02-07 - -Application visible changes: - -** SystemPerl is no longer required for tracing. - Applications must use VerilatedVcdC class in place of SpTraceVcdC. - -** SystemVerilog 1800-2009 is now the default language. - Thus "global" etc are now keywords. See the --language option. - -New features: - -** Support SystemVerilog types "byte", "chandle", "int", "longint", - "shortint", "time", "var" and "void" in variables and functions. - -** Support "program", "package", "import" and $unit. - -** Support typedef and enum. [by Donal Casey] - -** Support direct programming interface (DPI) "import" and "export". - Includes an extension to map user $system PLI calls to the DPI. - -*** Support assignments of multidimensional slices. (#170) [by Byron Bradley] - -*** Support multidimensional inputs/outputs. (#171) [by Byron Bradley] - -*** Support "reg [1:0][1:0][1:0]" and "reg x [3][2]". (#176) [Byron Bradley] - -*** Support declarations in loop initializers. (#172) [by Byron Bradley] - -*** Support $test$plusargs and $value$plusargs, but see the docs! - -*** Support $sformat and $swrite. - -*** Support 1800-2009 define defaults and `undefineall. - -*** Add -CFLAGS, -LDFLAGS, .a, .o, and .so options. - -*** Speed compiles by avoiding including the STL iostream header. - Application programs may need to include it themselves to avoid errors. - -*** Add experimental clock domain crossing checks. - -*** Add experimental --pipe-filter to filter all Verilog input. - -*** Add experimental config files to filter warnings outside of the source. - -*** Add VARHIDDEN warning when signal name hides module name. - -**** Support optional cell parenthesis. (#179) [by Byron Bradley] - -**** Support for loop i++, ++i, i--, --i. (#175) [by Byron Bradley] - -**** Support 1800-2009 /*comments*/ in define values. - -**** Add Makefile VM_GLOBAL_FAST, listing objects needed to link executables. - -**** Add --bbox-unsup option to black-box unsupported UDP tables. - -**** Add -Wno-MODDUP option to allow duplicate modules. - -Bug fixes: - -**** Fix implicit variable issues. (#196) (#201) [Byron Bradley] - -**** Fix 'for' variable typing. (#205) [by Byron Bradley] - -**** Fix tracing with --pins-bv 1. (#195) [Michael S] - -**** Fix MSVC++ 2008 compile issues. (#209) [Amir Gonnen] - -**** Fix MinGW compilation. (#184) (#214) [by Shankar Giri, Amir Gonnen] - -**** Fix Cygwin 1.7.x compiler error with uint32_t. (#204) [Ivan Djordjevic] - -**** Fix `define argument mis-replacing system task of same name. (#191) - -**** Fix Verilator core dump on wide integer divides. (#178) [Byron Bradley] - -**** Fix lint_off/lint_on meta comments on same line as warning. - - -* Verilator 3.720 2009-10-26 - -** Support little endian bit vectors ("reg [0:2] x;"). - -** Support division and modulus of > 64 bit vectors. [Gary Thomas] - -*** Fix writing to out-of-bounds arrays writing element 0. - -**** Fix core dump with SystemVerilog var declarations under unnamed begins. - -**** Fix VCD files showing internal flattened hierarchy, broke in 3.714. - -**** Fix cell port connection to unsized integer causing false width warning. - -**** Fix erroring on strings with backslashed newlines. (#168) [Pete Nixon] - - -* Verilator 3.714 2009-09-18 - -** Add --bbox-sys option to blackbox $system calls. - -** Support generate for var++, var--, ++var, --var. - -*** Improved warning when "do" used as identifier. - -**** Don't require SYSTEMPERL_INCLUDE if SYSTEMPERL/src exists. [Gary Thomas] - -**** Fix deep defines causing flex scanner overflows. [Brad Dobbie] - -**** Fix preprocessing commas in deep parameterized macros. [Brad Dobbie] - -**** Fix tracing escaped dotted identifiers. (#107) - -**** Fix $display with uppercase %M. - -**** Fix --error-limit option being ignored. - - -* Verilator 3.713 2009-08-04 - -** Support constant function calls for parameters. [many!] - -*** Support SystemVerilog "logic". (#101) [by Alex Duller] - -*** Name SYMRSVDWORD error, and allow disabling it. (#103) [Gary Thomas] - -**** Fix escaped preprocessor identifiers. (#106) [Nimrod Gileadi] - - -* Verilator 3.712 2009-07-14 - -** Patching SystemC is no longer required to trace sc_bvs. - -*** Support zero-width constants in concatenations. [Jeff Winston] - -*** Add verilator --pins-uint8 option to use sc_in. - -*** Add verilator -V option, to show verbose version. - -*** On WIDTH warnings, show variable name causing error. [Jeff Winston] - -**** Add BLKLOOPINIT error code, and describe --unroll-count. [Jeff Winston] - - -* Verilator 3.711 2009-06-23 - -**** Support decimal constants of arbitrary widths. [Mark Marshall] - -**** Fix error on case statement with all duplicate items. (#99) [Gary Thomas] - -**** Fix segfault on unrolling for's with bad inits. (#90) [Andreas Olofsson] - -**** Fix tristates causing "Assigned pin is neither...". [by Lane Brooks] - -**** Fix compiler errors under Fedora release candidate 11. [Chitlesh Goorah] - - -* Verilator 3.710 2009-05-19 - -** Verilator is now licensed under LGPL v3 and/or Artistic v2.0. - -*** `__FILE__ now expands to a string, per draft SystemVerilog 2010(ish). - -**** The front end parser has been re-factored to enable more SV parsing. - Code should parse the same, but minor parsing bugs may pop up. - -**** Verilator_includer is no longer installed twice. (#48) [Lane Brooks] - -**** Fix escaped identifiers with '.' causing conflicts. (#83) [J Baxter] - -**** Fix define formal arguments that contain newlines. (#84) [David A] - - -* Verilator 3.703 2009-05-02 - -*** Fix $clog2 calculation error with powers-of-2. (#81) [Patricio Kaplan] - -**** Fix error with tasks that have output first. (#78) [Andrea Foletto] - -**** Fix "cloning" error with -y/--top-module. (#76) [Dimitris Nalbantis] - -**** Fix segfault with error on bad --top-module. (#79) [Dimitris Nalbantis] - -**** Fix "redefining I" error with complex includes. [Duraid Madina] - -**** Fix GCC 4.3.2 compile warnings. - - -* Verilator 3.702 2009-03-28 - -*** Add --pins-bv option to use sc_bv for all ports. [Brian Small] - -*** Add SYSTEMPERL_INCLUDE envvar to assist RPM builds. [Chitlesh Goorah] - -**** Report errors when duplicate labels are used. (#72) [Vasu Kandadi] - -**** Fix the SC_MODULE name() to not include __PVT__. [Bob Fredieu] - - -* Verilator 3.701 2009-02-26 - -** Support repeat and forever statements. [Jeremy Bennett] - -*** Add --debugi- option, for internal debugging. [Dennis Muhlestein] - -**** Fix compile issues with GCC 4.3. (#47) [Lane Brooks] - -**** Fix VL_RANDom to better randomize bits. [Art Stamness] - -**** Fix error messages to consistently go to stderr. [Jeremy Bennett] - -**** Fix left associativity for ?: operators. - - -* Verilator 3.700 2009-01-08 - -** Add limited support for tristate inouts. Written by Lane Brooks, - under support by Ubixum Inc. This allows common pad ring and - tristate-mux structures to be Verilated. See the documentation for - more information on supported constructs. - -** Add --coverage_toggle for toggle coverage analysis. - Running coverage now requires SystemPerl 1.301 or newer. - -*** Add /*verilator coverage_on/_off */ to bracket coverage regions. - -*** Optimize two-level shift and and/or trees, +23% on one test. - -*** Support posedge of bit-selected signals. (#45) [Rodney Sinclair] - -*** Line coverage now aggregates by hierarchy automatically. - Previously this would be done inside SystemPerl, which was slower. - -**** Minor performance improvements of Verilator compiler runtime. - -**** Coverage of each parametarized module is counted separately. [Bob Fredieu] - -**** Fix creating parameterized modules when no parameter values are changed. - -**** Fix certain generate-if cells causing "clone" error. [Stephane Laurent] - -**** Fix line coverage of public functions. [Soon Koh] - -**** Fix SystemC 2.2 deprecated warnings about sensitive() and sc_start(). - -**** Fix arrayed variables under function not compiling. (#44) [Ralf Karge] - -**** Fix --output-split-cfuncs to also split trace code. [Niranjan Prabhu] - -**** Fix 'bad select range' warning missing some cases. (#43) [Lane Brooks] - -**** Fix internal signal names containing control characters (broke in 3.680). - -**** Fix compile error on Ubuntu 8.10. [Christopher Boumenot] - -**** Fix internal error on "output x; reg x = y;". - -**** Fix wrong result for read of delayed FSM signal. (#46) [Rodney Sinclair] - - -* Verilator 3.681 2008-11-12 - -*** Add SystemVerilog unique and priority case. - -**** Include Verilog file's directory name in coverage reports. - -**** Fix 'for' under 'generate-for' causing error. (#38) [Rafael Shirakawa] - -**** Fix coverage hierarchy being backwards with inlining. [Vasu Arasanipalai] - -**** Fix GCC 4.3 compile error. (#35) [Lane Brooks] - -**** Fix MSVC compile error. (#42) [John Stroebel] - - -* Verilator 3.680 2008-10-08 - -** Support negative bit indexes. [Stephane Laurent] - Tracing negative indexes requires latest Verilog-Perl and SystemPerl. - -*** Suppress width warnings between constant strings and wider vectors. - [Rodney Sinclair] - -**** Ignore SystemVerilog timeunit and timeprecision. - -**** Expand environment variables in -f input files. [Lawrence Butcher] - -**** Report error if port declaration is missing. (#32) [Guy-Armand Kamendje] - -**** Fix genvars causing link error when using --public. [Chris Candler] - - -* Verilator 3.671 2008-09-19 - -** SystemC uint64_t pins are now the default instead of sc_bv<64>. - Use --no-pins64 for backward compatibility. - -*** Support SystemVerilog "cover property" statements. - -*** When warnings are disabled on signals that are flattened out, disable - the warnings on the signal(s) that replace it. - -*** Add by-design and by-module subtotals to verilator_profcfunc. - -*** Fix extra evaluation of pure combo blocks in SystemC output. - -**** Add IMPERFECTSCH warning, disabled by default. - -**** Support coverage under SystemPerl 1.285 and newer. - -**** Fix stack overflow on large ? : trees. [John Sanguinetti] - -**** Support arbitrary characters in identifiers. [Stephane Laurent] - - -* Verilator 3.670 2008-07-23 - -** Add --x-assign=fast option, and make it the default. - This chooses performance over reset debugging. See the manual. - -** Add --autoflush, for flushing streams after $display. [Steve Tong] - -** Add CASEWITHX lint warning and if disabled fix handling of casez with Xs. - -*** Add $feof, $fgetc, $fgets, $fflush, $fscanf, $sscanf. [Holger Waechtler] - -*** Add $stime. [Holger Waechtler] - -*** Add $random. - -*** Add --Wfuture-, for improving forward compatibility. - -**** Fix verilator_includer not being installed properly. [Holger Waechtler] - -**** Fix IMPURE errors due to X-assignment temporary variables. [Steve Tong] - -**** Fix "lvalue" errors with public functions. (#25) [CY Wang] - -**** Add WIDTH warning to $fopen etc file descriptors. - -**** Internal changes to how $displays get compiled and executed. - - -* Verilator 3.665 2008-06-25 - -**** Ignore "// verilator" comments alone on endif lines. [Rodney Sinclair] - -**** "Make install" now installs verilator_includer and verilator_profcfunc. - -**** Fix tracing missing changes on undriven public wires. [Rodney Sinclair] - -**** Fix syntax error when "`include `defname" is ifdefed. [John Dickol] - -**** Fix error when macro call has commas in concatenate. [John Dickol] - -**** Fix compile errors under Fedora 9, GCC 4.3.0. [by Jeremy Bennett] - -**** Fix Makefile to find headers/libraries under prefix. [by Holger Waechtler] - - -* Verilator 3.664 2008-05-08 - -**** Fix missing file in kit. - - -* Verilator 3.663 2008-05-07 - -**** Add DESTDIR to Makefiles to assist RPM construction. [Gunter Dannoritzer] - -**** Fix compiler warnings under GCC 4.2.1. - -**** Fix preprocessor `else after series of `elsif. [Mark Nodine] - -**** Fix parametrized defines calling define with comma. [Joshua Wise] - -**** Fix comma separated list of primitives. [by Bryan Brady] - - -* Verilator 3.662 2008-04-25 - -*** Add Verilog 2005 $clog2() function. - This is useful in calculating bus-widths from parameters. - -*** Support /**/ comments in -f option files. [Stefan Thiede] - -**** Add error message when modules have duplicate names. [Stefan Thiede] - -**** Support defines terminated in EOF, though against spec. [Stefan Thiede] - -**** Support optional argument to $finish and $stop. [by Stefan Thiede] - -**** Support ranges on gate primitive instantiations. [Stefan Thiede] - -**** Ignore old standard(ish) Verilog-XL defines. [by Stefan Thiede] - -**** Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu] - -**** Fix "output reg name=expr;" syntax error. [Martin Scharrer] - -**** Fix multiple .v files being read in random order. [Stefan Thiede] - -**** Fix internal error when params get non-constants. [Johan Wouters] - -**** Fix bug introduced in 3.661 with parametrized defines. - - -* Verilator 3.661 2008-04-04 - -*** The --enable-defenv configure option added in 3.660 is now the default. - This hard-codes a default for VERILATOR_ROOT etc in the executables. - -*** Add --language option for supporting older code. [Stefan Thiede] - -*** Add --top-module option to select between multiple tops. [Stefan Thiede] - -*** Unsized concatenates now give WIDTHCONCAT warnings. [Jonathan Kimmitt] - Previously they threw fatal errors, which in most cases is correct - according to spec, but can be incorrect in presence of parameter values. - -**** Support functions with "input integer". [Johan Wouters] - -**** Ignore delays attached to gate UDPs. [Stefan Thiede] - -**** Fix SystemVerilog parameterized defines with `` expansion, - and fix extra whitespace inserted on substitution. [Vladimir Matveyenko] - -**** Fix no-module include files on command line. [Stefan Thiede] - -**** Fix dropping of backslash quoted-quote at end of $display. - -**** Fix task output pin connected to non-variables. [Jonathan Kimmitt] - -**** Fix missing test_v in install datadir. [Holger Waechtler] - -**** Fix internal error after MSB < LSB error reported to user. [Stefan Thiede] - - -* Verilator 3.660 2008-03-23 - -*** Add support for hard-coding VERILATOR_ROOT etc in the executables, - to enable easier use of Verilator RPMs. [Gunter Dannoritzer] - -*** Allow multiple .v files on command line. [Stefan Thiede] - -*** Convert re-defining macro error to warning. [Stefan Thiede] - -*** Add --error-limit option. [Stefan Thiede] - -*** Allow __ in cell names by quoting them in C. [Stefan Thiede] - -**** Fix genvar to be signed, so "< 0" works properly. [Niranjan Prabhu] - -**** Fix assignments to inputs inside functions/tasks. [Patricio Kaplan] - -**** Fix definitions in main file.v, referenced in library. [Stefan Thiede] - -**** Fix undefined assigns to be implicit warnings. [Stefan Thiede] - - -* Verilator 3.658 2008-02-25 - -**** Fix unistd compile error in 3.657. [Patricio Kaplan, Jonathan Kimmitt] - - -* Verilator 3.657 2008-02-20 - -**** Fix assignments of {a,b,c} = {c,b,a}. [Jonathan Kimmitt] - -**** Fix Perl warning with --lint-only. [by Ding Xiaoliang] - -**** Avoid creating obj_dir with --lint-only. [Ding Xiaoliang] - -**** Fix parsing of always @(*). [Patricio Kaplan] - - -* Verilator 3.656 2008-01-18 - -**** Wide VL_CONST_W_#X functions are now made automatically. [Bernard Deadman] - In such cases, a new {prefix}__Inlines.h file will be built and included. - -**** Fixed sign error when extracting from signed memory. [Peter Debacker] - -**** Fixed tracing of SystemC w/o SystemPerl. [Bernard Deadman, Johan Wouters] - - -* Verilator 3.655 2007-11-27 - -*** Support "#delay ;" with associated STMTDLY warning. - -**** Fixed generate for loops with constant zero conditions. [Rodney Sinclair] - -**** Fixed divide-by-zero errors in constant propagator. [Rodney Sinclair] - -**** Fixed wrong result with obscure signed-shift underneath a "? :". - -**** Fixed many internal memory leaks, and added leak detector. - - -* Verilator 3.654 2007-10-18 - -**** Don't exit early if many warnings but no errors are found. [Stan Mayer] - -**** Fixed parsing module #(parameter x,y) declarations. [Oleg Rodionov] - -**** Fixed parsing system functions with empty parens. [Oleg Rodionov] - - -* Verilator 3.653 2007-08-01 - -**** Support SystemVerilog ==? and !=? operators. - -**** Fixed SC_LIBS missing from generated makefiles. [Ding Xiaoliang] - - -* Verilator 3.652 2007-06-21 - -**** Report as many warning types as possible before exiting. - -**** Support V2K portlists with "input a,b,...". [Mark Nodine] - -**** Support V2K function/task argument lists. - -**** Optimize constant $display arguments. - -**** Fixed Preprocessor dropping some `line directives. [Mark Nodine] - - -* Verilator 3.651 2007-05-22 - -*** Added verilator_profcfunc utility. [Gene Weber] - -*** Treat modules within `celldefine and `endcelldefine as if in library. - -*** Support functions which return integers. [Mark Nodine] - -**** Warn if flex is not installed. [Ralf Karge] - -**** Ignore `protect and `endprotect. - -**** Allow empty case/endcase blocks. - - -* Verilator 3.650 2007-04-20 - -** Add --compiler msvc option. This is now required when Verilated code - is to be run through MSVC++. This also enables fixing MSVC++ error - C1061, blocks nested too deeply. [Ralf Karge] - -** Add --lint-only option, to lint without creating other output. - -*** Add /*verilator lint_save*/ and /*verilator lint_restore*/ to allow - friendly control over re-enabling lint messages. [Gerald Williams] - -*** Support SystemVerilog .name and .* interconnect. - -*** Support while and do-while loops. - -*** Use $(LINK) instead of $(CXX) for Makefile link rules. [Gerald Williams] - -*** Add USER_CPPFLAGS and USER_LDFLAGS to Makefiles. [Gerald Williams] - -**** Fixed compile errors under Windows MINGW compiler. [Gerald Williams] - -**** Fixed dotted bit reference to local memory. [Eugene Weber] - -**** Fixed 3.640 `verilog forcing IEEE 1364-1995 only. [David Hewson] - - -* Verilator 3.640 2007-03-12 - -*** Support Verilog 2005 `begin_keywords and `end_keywords. - -*** Updated list of SystemVerilog keywords to correspond to IEEE 1800-2005. - -*** Add /*verilator public_flat*/. [Eugene Weber] - -**** Try all +libext's in the exact order given. [Michael Shinkarovsky] - -**** Fixed elimination of public signals assigned to constants. [Eugene Weber] - -**** Fixed internal error when public for loop has empty body. [David Addison] - -**** Fixed "Loops detected" assertion when model exceeds 4GB. [David Hewson] - -**** Fixed display %m names inside named blocks. - - -* Verilator 3.633 2007-02-07 - -*** Add --trace-depth option for minimizing VCD file size. [Emerson Suguimoto] - -*** With VL_DEBUG, show wires causing convergence errors. [Mike Shinkarovsky] - -**** Fixed isolate_assignments when many signals per always. [Mike Shinkarovsky] - -**** Fixed isolate_assignments across task/func temporaries. [Mike Shinkarovsky] - -**** Fixed $display's with array select followed by wide AND. [David Hewson] - - -* Verilator 3.632 2007-01-17 - -*** Add /*verilator isolate_assignments*/ attribute. [Mike Shinkarovsky] - - -* Verilator 3.631 2007-01-02 - -** Support standard NAME[#] for cells created by arraying or generate for. - This replaces the non-standard name__# syntax used in earlier versions. - -**** Fixed again dotted references into generate cells. [David Hewson] - Verilator no longer accepts duplicated variables inside unique - generate blocks as this is illegal according to the specification. - -**** Fixed $readmem* with filenames < 8 characters. [Emerson Suguimoto] - - -* Verilator 3.630 2006-12-19 - -** Support $readmemb and $readmemh. [Eugene Weber, Arthur Kahlich] - -*** Fixed configure and compiling under Solaris. [Bob Farrell] - -*** When dotted signal lookup fails, help the user by showing known scopes. - -*** Reduce depth of priority encoded case statements. [Eugene Weber] - -**** Fixed dotted references inside generated cells. [David Hewson] - -**** Fixed missed split optimization points underneath other re-split blocks. - - -* Verilator 3.623 2006-12-05 - -*** Add --output-split-cfuncs for accelerating GCC compile. [Eugene Weber] - -**** Fixed $signed mis-extending when input has a WIDTH violation. [Eugene Weber] - -**** Add M32 make variable to support -m32 compiles. [Eugene Weber] - - -* Verilator 3.622 2006-10-17 Stable - -**** Fixed --skip-identical without --debug, broken in 3.621. [Andy Meier] - - -* Verilator 3.621 2006-10-11 Beta - -** Add /*verilator no_inline_task*/ to prevent over-expansion. [Eugene Weber] - -*** Public functions now allow > 64 bit arguments. - -**** Remove .vpp intermediate files when not under --debug. - -**** Fixed link error when using --exe with --trace. [Eugene Weber] - -**** Fixed mis-optimization of wide concats with constants. - -**** Fixed core dump on printing error when not under --debug. [Allan Cochrane] - - -* Verilator 3.620 2006-10-04 Stable - -*** Support simple inout task ports. [Eugene Weber] - -*** Allow overriding Perl, Flex and Bison versions. [by Robert Farrell] - -*** Optimize variables set to constants within basic blocks for ~3%. - -**** Default make no longer makes the docs; if you edit the documentation. - sources, run "make info" to get them. - -**** Optimize additional boolean identities (a|a = a, etc.) - -**** Fixed coredump when dotted cross-ref inside task call. [Eugene Weber] - -**** Fixed dotted variables in always sensitivity lists. [Allan Cochrane] - - -* Verilator 3.610 2006-09-20 Stable - -*** Verilator now works under DJGPP (Pentium GCC). [John Stroebel] - -**** Add default define for VL_PRINTF. [John Stroebel] - -**** Removed coverage request variable; see Coverage limitations in docs. - -**** Fixed DOS carriage returns in multiline defines. [Ralf Karge] - -**** Fixed printf format warnings on 64-bit linux. - - -* Verilator 3.602 2006-09-11 Stable - -**** Fixed function references under top inlined module. [David Hewson] - - -* Verilator 3.601 2006-09-06 Beta - -*** Added --inhibit-sim flag for environments using old __Vm_inhibitSim. - -*** Added `systemc_dtor for destructor extensions. [Allan Cochrane] - -*** Added -MP to make phony dependencies, ala GCC's. - -*** Changed how internal functions are invoked to reduce aliasing. - Useful when using GCC's -O2 or -fstrict-aliasing, to gain another ~4%. - -**** Fixed memory leak when destroying modules. [John Stroebel] - -**** Fixed coredump when unused modules have unused cells. [David Hewson] - -**** Fixed 3.600 internal error with arrayed instances. [David Hewson] - -**** Fixed 3.600 internal error with non-unrolled function loops. [David Hewson] - -**** Fixed $display %m name not matching Verilog name inside SystemC modules. - -**** Declare optimized lookup tables as 'static', to reduce D-Cache miss rate. - - -* Verilator 3.600 2006-08-28 Beta - -** Support dotted cross-hierarchy variable and task references. - -**** Lint for x's in generate case statements. - -**** Fixed line numbers being off by one when first file starts with newline. - -**** Fixed naming of generate for blocks to prevent non-inline name conflict. - -**** Fixed redundant statements remaining after table optimization. - - -* Verilator 3.542 2006-08-11 Stable - -**** Fixed extraneous UNSIGNED warning when comparing genvars. [David Hewson] - -**** Fixed extra white space in $display %c. [by David Addison] - -**** vl_finish and vl_fatal now print via VL_PRINTF rather then cerr/cout. - -**** Add VL_CONST_W_24X macro. [Bernard Deadman] - - -* Verilator 3.541 2006-07-05 Beta - -*** Fixed "// verilator lint_on" not re-enabling warnings. [David Hewson] - -*** Fixed 3.540's multiple memory assignments to same block. [David Hewson] - -**** Add warning on changeDetect to arrayed structures. [David Hewson] - -**** Fixed non-zero start number for arrayed instantiations. [Jae Hossell] - -**** Fixed GCC 4.0 header file warnings. - - -* Verilator 3.540 2006-06-27 Beta - -**** Optimize combo assignments that are used only once, ~5-25% faster. - -**** Optimize delayed assignments to memories inside loops, ~0-5% faster. - -**** Fixed mis-width warning on bit selects of memories. [David Hewson] - -**** Fixed mis-width warning on dead generate-if branches. [Jae Hossell] - - -* Verilator 3.533 2006-06-05 Stable - -*** Add PDF user manual, verilator.pdf. - -**** Fixed delayed bit-selected arrayed assignments. [David Hewson] - -**** Fixed execution path to Perl. [Shanshan Xu] - -**** Fixed Bison compile errors in verilog.y. [by Ben Jackson] - - -* Verilator 3.531 2006-05-10 Stable - -*** Support $c routines which return 64 bit values. - -**** Fixed `include `DEFINE. - -**** Fixed Verilator core dump when have empty public function. [David.Hewson] - - -* Verilator 3.530 2006-04-24 Stable - -** $time is now 64 bits. The macro VL_TIME_I is now VL_TIME_Q, but calls - the same sc_time_stamp() function to get the current time. - - -* Verilator 3.523 2006-03-06 Stable - -**** Fixed error line numbers being off due to multi-line defines. [Mat Zeno] - -**** Fixed GCC sign extending (uint64_t)(a>>, $signed, $unsigned. [MANY!] - -** Support multi-dimensional arrays. [Eugen Fekete] - -** Add very limited support for the Property Specification Language - (aka PSL or Sugar). The format and keywords are now very limited, but will - grow with future releases. The --assert switch enables this feature. - -** With --assert, generate assertions for synthesis parallel_case and full_case. - -**** Fixed generate if's with empty if/else blocks. [Mat Zeno] - -**** Fixed generate for cell instantiations with same name. [Mat Zeno] - - -* Verilator 3.481 2005-10-12 Stable - -*** Add /*verilator tracing_on/off*/ for waveform control. - -**** Fixed split optimization reordering $display statements. - - -* Verilator 3.480 2005-09-27 Beta - -** Allow coverage of flattened modules, and multiple points per line. - Coverage analysis requires SystemPerl 1.230 or newer. - -**** Add preprocessor changes to support meta-comments. - -**** Optimize sequential assignments of different bits of same bus; ~5% faster. - -**** Optimize away duplicate lookup tables. - -**** Optimize wide concatenates into individual words. [Ralf Karge] - -**** Optimize local variables from delayed array assignments. - - -* Verilator 3.470 2005-09-06 Stable - -*** Optimize staging flops under reset blocks. - -*** Add '-Werror-...' to upgrade specific warnings to errors. - -**** Add GCC branch prediction hints on generated if statements. - -**** Fixed bad simulation when same function called twice in same expression. - -**** Fixed preprocessor substitution of quoted parameterized defines. - - -* Verilator 3.464 2005-08-24 Stable - -*** Add `systemc_imp_header, for use when using --output-split. - -*** Add --stats option to dump design statistics. - -**** Fixed core dump with clock inversion optimizations. - - -* Verilator 3.463 2005-08-05 Stable - -*** Fixed case defaults when not last statement in case list. [Wim Michiels] - - -* Verilator 3.462 2005-08-03 Stable - -*** Fixed reordering of delayed assignments to same memory index. [Wim Michiels] - -**** Fixed compile error with Flex 2.5.1. [Jens Arm] - -**** Fixed multiply-instantiated public tasks generating non-compilable code. - - -* Verilator 3.461 2005-07-28 Beta - -**** Fixed compile error with older versions of bison. [Jeff Dutton] - - -* Verilator 3.460 2005-07-27 Beta - -** Add -output-split option to enable faster parallel GCC compiles. - To support --output-split, the makefiles now split VM_CLASSES - into VM_CLASSES_FAST and VM_CLASSES_SLOW. This may require a - change to local makefiles. - -** Support -v argument to read library files. - -*** When issuing unoptimizable warning, show an example path. - -**** Fixed false warning when a clock is constant. - -**** Fixed X/Z in decimal numbers. [Wim Michiels] - -**** Fixed genvar statements in non-named generate blocks. - -**** Fixed core dump when missing newline in `define. [David van der bokke] - -**** Internal tree dumps now indicate edit number that changed the node. - - -* Verilator 3.450 2005-07-12 - -** $finish will no longer exit, but set Verilated::gotFinish(). - This enables support for final statements, and for other cleanup code. - If this is undesired, redefine the vl_user_finish routine. Top level - loops should use Verilated::gotFinish() as a exit condition for their - loop, and then call top->final(). To prevent a infinite loop, a - double $finish will still exit; this may be removed in future - releases. - -*** Add support for SystemVerilog keywords $bits, $countones, $isunknown, - $onehot, $onehot0, always_comb, always_ff, always_latch, finish. - -**** Fixed "=== 1'bx" to always be false, instead of random. - - -* Verilator 3.440 2005-06-28 Stable - -** Add Verilog 2001 generate for/if/case statements. - - -* Verilator 3.431 2005-06-24 Stable - -*** Fixed selection bugs introduced in 3.430 beta. - - -* Verilator 3.430 2005-06-22 Beta - -** Add Verilog 2001 variable part selects [n+:m] and [n-:m]. [Wim Michiels] - - -* Verilator 3.422 2005-06-10 Stable - -*** Added Verilog 2001 power (**) operator. [Danny Ding] - -**** Fixed crash and added error message when assigning to inputs. [Ralf Karge] - -**** Fixed tracing of modules with public functions. - - -* Verilator 3.421 2005-06-02 Beta - -**** Fixed error about reserved word on non-public signals. - -**** Fixed missing initialization compile errors in 3.420 beta. [Ralf Karge] - - -* Verilator 3.420 2005-06-02 Beta - -*** Fixed case defaults when not last statement in case list. [Ralf Karge] - -**** Added error message when multiple defaults in case statement. - -**** Fixed crash when wire self-assigns x=x. - -** Performance improvements worth ~20% - -** Added -x-assign options; ~5% faster if use -x-assign=0. - -**** Optimize shifts out of conditionals and if statements. - -**** Optimize local 'short' wires. - -**** Fixed gate optimization with top-flattened modules. [Mahesh Kumashikar] - - -* Verilator 3.411 2005-05-30 Stable - -**** Fixed compile error in GCC 2.96. [Jeff Dutton] - - -* Verilator 3.410 2005-05-25 Beta - -** Allow functions and tasks to be declared public. - They will become public C++ functions, with appropriate C++ types. - This allows users to make public accessor functions/tasks, instead - of having to use public variables and `systemc_header hacks. - -*** Skip producing output files if all inputs are identical - This uses timestamps, similar to make. Disable with --no-skip-identical. - -**** Improved compile performance with large case statements. - -**** Fixed internal error in V3Table. [Jeff Dutton] - -**** Fixed compile error in GCC 2.96, and with SystemC 1.2. [Jeff Dutton] - - -* Verilator 3.400 2005-04-29 Beta - -** Internal changes to support future clocking features. - -** Verilog-Perl and SystemPerl are no longer required for C++ or SystemC - output. If you want tracing or coverage analysis, they are still needed. - -*** Added --sc to create pure SystemC output not requiring SystemPerl. - -*** Added --pins64 to create 64 bit SystemC outputs instead of sc_bv<64>. - -*** The --exe flag is now required to produce executables inside the makefile. - This was previously the case any time .cpp files were passed on the - command line. - -*** Added -O3 and --inline-mult for performance tuning. [Ralf Karge] - One experiment regained 5% performance, at a cost of 300% in compile time. - -*** Improved performance of large case/always statements with low fanin - by converting to internal lookup tables (ROMs). - -*** Initialize SystemC port names. [S Shuba] - -**** Added Doxygen comments to Verilated includes. - -**** Fixed -cc pins 8 bits wide and less to be uint8_t instead of uint16_t. - -**** Fixed crash when Mdir has same name as .v file. [Gernot Koch] - -**** Fixed crash with size mismatches on case items. [Gernot Koch] - - -* Verilator 3.340 2005-02-18 Stable - -*** Report misconnected pins across all modules, instead of just first error. - -**** Fixed over-active inlining, resulting in compile slowness. - -**** Improved large netlist compile times. - -**** Added additional internal assertions. - - -* Verilator 3.332 2005-01-27 - -*** Added -E preprocess only flag, similar to GCC. - -*** Added CMPCONSTLR when comparison is constant due to > or < with all ones. - -**** Fixed loss of first -f file argument, introduced in 3.331. - - -* Verilator 3.331 2005-01-18 - -** The Verilog::Perl preprocessor is now C++ code inside of Verilator. - This improves performance, makes compilation easier, and enables - some future features. - -*** Support arrays of instantiations (non-primitives only). [Wim Michiels] - -**** Fixed unlinked error with defparam. [Shawn Wang] - - -* Verilator 3.320 2004-12-10 - -** NEWS is now renamed Changes, to support CPAN indexing. - -*** If Verilator is passed a C file, create a makefile link rule. - This saves several user steps when compiling small projects. - -*** Added new COMBDLY warning in place of fatal error. [Shawn Wang] - -*** Fixed mis-simulation with wide-arrays under bit selects. [Ralf Karge] - -**** Added NC Verilog as alternative to VCS for reference tests. - -**** Support implicit wire declarations on input-only signals. - (Dangerous, as leads to wires without drivers, but allowed by spec.) - -**** Fixed compile warnings on Suse 9.1 - - -* Verilator 3.311 2004-11-29 - -** Support implicit wire declarations (as a warning). [Shawn Wang] - -**** Fixed over-shift difference in Verilog vs C++. [Ralf Karge] - - -* Verilator 3.310 2004-11-15 - -** Support defparam. - -** Support gate primitives: buf, not, and, nand, or, nor, xor, xnor. - -*** Ignore all specify blocks. - - -* Verilator 3.302 2004-11-12 - -*** Support NAND and NOR operators. - -*** Better warnings when port widths don't match. - -**** Fixed internal error due to some port width mismatches. [Ralf Karge] - -**** Fixed WIDTH warnings on modules that are only used - parameterized, not in 'default' state. - -**** Fixed selection of SystemC library on cygwin systems. [Shawn Wang] - -**** Fixed runtime bit-selection of parameter constants. - - -* Verilator 3.301 2004-11-04 - -**** Fixed 64 bit [31:0] = {#{}} mis-simulation. [Ralf Karge] - -**** Fixed shifts greater then word width mis-simulation. [Ralf Karge] - -**** Work around GCC 2.96 negation bug. - - -* Verilator 3.300 2004-10-21 - -** New backend that eliminates most VL_ macros. - Improves performance 20%-50%, depending on frequency of use of signals - over 64 bits. GCC compile times with -O2 shrink by a factor of 10. - -**** Fixed "setting unsigned int from signed value" warning. - - -* Verilator 3.271 2004-10-21 - -**** Fixed "loops detected" error with some negedge clocks. - -**** Cleaned up some output code spacing issues. - - -* Verilator 3.270 2004-10-15 - -*** Support Verilog 2001 parameters in module headers. [Ralf Karge] - -**** Suppress numeric fault when dividing by zero. - -**** Faster code to support compilers not inlining all Verilated functions. - - -* Verilator 3.260 2004-10-07 - -** Support Verilog 2001 named parameter instantiation. [Ralf Karge] - -**** Return 1's when one bit wide extract indexes outside array bounds. - -**** Fixed compile warnings on 64-bit operating systems. - -**** Fixed incorrect dependency in .d file when setting VERILATOR_BIN. - - -* Verilator 3.251 2004-09-09 - -**** Fixed parenthesis overflow in Microsoft Visual C++ [Renga Sundararajan] - - -* Verilator 3.250 2004-08-30 - -** Support Microsoft Visual C++ [Renga Sundararajan] - -*** SystemPerl 1.161+ is required. - - -* Verilator 3.241 2004-08-17 - -** Support ,'s to separate multiple assignments. [Paul Nitza] - -**** Fixed shift sign extension problem using non-GCC compilers. - - -* Verilator 3.240 2004-08-13 - -** Verilator now uses 64 bit math where appropriate. - Inputs and outputs of 33-64 bits wide to the C++ Verilated model must - now be uint64_t's; SystemC has not changed, they will remain sc_bv's. - This increases performance by ~ 9% on x86 machines, varying with how - frequently 33-64 bit signals occur. Signals 9-16 bits wide are now - stored as 16 bit shorts instead of longs, this aids cache packing. - -**** Fixed SystemC compile error with feedthrus. [Paul Nitza] - -**** Fixed concat value error introduced in 3.230. - - -* Verilator 3.230 2004-08-10 - -*** Added coverage output to test_sp example, SystemPerl 1.160+ is required. - -**** Fixed time 0 value of signals. [Hans Van Antwerpen] - Earlier versions would not evaluate some combinatorial signals - until posedge/negedge blocks had been activated. - -**** Fixed wide constant inputs to public submodules [Hans Van Antwerpen] - -**** Fixed wide signal width extension bug. - Only applies when width mismatch warnings were overridden. - - -* Verilator 3.220 2004-06-22 - -** Many waveform tracing changes: - -*** Tracing is now supported on C++ standalone simulations. [John Brownlee] - -*** When tracing, SystemPerl 1.150 or newer is required. - -*** When tracing, Verilator must be called with the --trace switch. - -**** Added SystemPerl example to documentation. [John Brownlee] - -**** Various Cygwin compilation fixes. [John Brownlee] - - -* Verilator 3.210 2004-04-01 - -** Compiler optimization switches have changed - See the BENCHMARKING section of the documentation. - -*** With Verilog-Perl 2.3 or newer, Verilator supports SystemVerilog - preprocessor extensions. - -*** Added localparam. [Thomas Hawkins] - -*** Added warnings for SystemVerilog reserved words. - - -* Verilator 3.203 2004-03-10 - -*** Notes and repairs for Solaris. [Fred Ma] - - -* Verilator 3.202 2004-01-27 - -** The beta version is now the primary release. See below for many changes. - If you have many problems, you may wish to try release 3.125. - -*** Verilated::traceEverOn(true) must be called at time 0 if you will ever - turn on tracing (waveform dumping) of signals. Future versions will - need this switch to disable trace incompatible optimizations. - -**** Fixed several tracing bugs - -**** Added optimizations for common replication operations. - - -* Verilator 3.201-beta 2003-12-10 - -** BETA VERSION, USE 3.124 for stable release! - -** Version 3.2XX includes a all new back-end. - This includes automatic inlining, flattening of signals between - hierarchy, and complete ordering of statements. This results in - 60-300% execution speedups, though less pretty C++ output. Even - better results are possible using GCC 3.2.2 (part of Redhat 9.1), as - GCC has fixed some optimization problems which Verilator exposes. - - If you are using `systemc_ctor, beware pointers to submodules are now - initialized after the constructor is called for a module, to avoid - segfaults, move statements that reference subcells into initial - statements. - -*** C++ Constructor that creates a verilog module may take a char* name. - This name will be used to prefix any $display %m arguments, so users may - distinguish between multiple Verilated modules in a single executable. - - -* Verilator 3.125 2004-01-27 - -**** Optimization of bit replications - - -* Verilator 3.124 2003-12-05 - -*** A optimized executable will be made by default, in addition to a debug - executable. Invoking Verilator with --debug will pick the debug version. - -**** Many minor invisible changes to support the next version. - - -* Verilator 3.123 2003-11-10 - -**** Wide bus performance enhancements. - -**** Fixed function call bug when width warning suppressed. [Leon Wildman] - -**** Fixed __DOT__ compile problem with funcs in last revision. [Leon Wildman] - - -* Verilator 3.122 2003-10-29 - -*** Modules which are accessed from external code now must be marked with - /*verilator public_module*/ unless they already contain public signals. - To enforce this, private cell names now have a string prepended. - -**** Fixed replicated function calls in one statement. [Robert A. Clark] - -**** Fixed function call bug when width warning suppressed. [Leon Wildman] - - -* Verilator 3.121 2003-09-29 - -*** Support multiplication over 32 bits. [Chris Boumenot] - Also improved speed of addition and subtraction over 32 bits. - -*** Detect bit selection out of range errors. - -*** Detect integer width errors. - -**** Fixed width problems on function arguments. [Robert A. Clark] - - -* Verilator 3.120 2003-09-24 - -*** $finish now exits the model (via vl_finish function). - -*** Support inputs/outputs in tasks. - -*** Support V2K "integer int = {INITIAL_VALUE};" - -*** Ignore floating point delay values. [Robert A. Clark] - -**** Ignore `celldefine, `endcelldefine, etc. [Robert A. Clark] - -**** New optimizations on reduction operators. - -**** Fixed converting "\ooo" into octal values. - -**** Fixed $display("%x"); - - -* Verilator 3.112 2003-09-16 - -**** Fixed functions in continuous assignments. [Robert A. Clark] - -**** Fixed inlining of modules with 2-level deep outputs. - - -* Verilator 3.111 2003-09-15 - -**** Fixed declaration of functions before using that module. [Robert A. Clark] - -**** Fixed module inlining bug with outputs. - - -* Verilator 3.110 2003-09-12 - -** Support Verilog 2001 style input/output declarations. [Robert A. Clark] - -*** Allow local vars in headers of function/tasks. [Leon Wildman] - - -* Verilator 3.109 2003-08-28 - -** Added support for local variables in named begin blocks. [Leon Wildman] - - -* Verilator 3.108 2003-08-11 - -** Added support for functions. - -*** Signals 8 bits and shorter are now stored as chars - instead of uint32_t's. This improves Dcache packing and - improves performance by ~7%. - -**** $display now usually results in a single VL_PRINT rather then many. - -**** Many optimizations involving conditionals (?:) - - -* Verilator 3.107 2003-07-15 - -*** --private and --l2name are now the default, - as this enables additional optimizations. - Use --noprivate or --nol2name to get the older behavior. - -*** Now support $display of binary and wide format data. - -*** Added detection of incomplete case statements, - and added related optimizations worth ~4%. - -**** Work around flex bug in Redhat 8.0. [Eugene Weber] - -**** Added some additional C++ reserved words. - -**** Additional constant optimizations, ~5% speed improvement. - - -* Verilator 3.106 2003-06-17 - -** $c can now take multiple expressions as arguments. - For example $c("foo","bar(",32+1,");") will insert "foobar(33);" - This makes it easier to pass the values of signals. - -** Several changes to support future versions that may have - signal-eliminating optimizations. Users should try to use these switch - on designs, they will become the default in later versions. - -*** Added --private switch and /*verilator public*/ metacomment. - This renames all signals so that compile errors will result if any - signals referenced by C++ code are missing a /*verilator public*/ - metacomment. - -*** With --l2name, the second level cell C++ cell is now named "v". - Previously it was named based on the name of the verilog code. This - means to get to signals, scope to "{topcell} ->v ->{mysignal}" instead - of "{topcell} ->{verilogmod}. {mysignal}". This allows different - modules to be substituted for the cell without requiring source - changes. - -**** Several cleanups for Redhat 8.0. - - -* Verilator 3.105 2003-05-08 - -**** Fixed more GCC 3.2 errors. [David Black] - - -* Verilator 3.104 2003-04-30 - -*** Indicate direction of ports with VL_IN and VL_OUT. - -*** Allow $c32, etc, to specify width of the $c statement for VCS. - -**** Fixed false "indent underflow" error inside `systemc_ctor sections. - -**** Fixed missing ordering optimizations when outputs also used internally. - -*** Numerous performance improvements, worth about 25% - -**** Assign constant cell pins in initial blocks rather then every cycle. - -**** Promote subcell's combo logic to sequential evaluation when possible. - -**** Fixed GCC 3.2 compile errors. [Narayan Bhagavatula] - - -* Verilator 3.103 2003-01-28 - -**** Fixed missing model evaluation when clock generated several levels of - hierarchy across from where it is used as a clock. [Richard Myers] - -**** Fixed sign-extension bug introduced in 3.102. - - -* Verilator 3.102 2003-01-24 - -**** Fixed sign-extension of X/Z's ("32'hx") - - -* Verilator 3.101 2003-01-13 - -**** Fixed 'parameter FOO=#'bXXXX' [Richard Myers] - -**** Allow spaces inside numbers ("32'h 1234") [Sam Gladstone] - - -* Verilator 3.100 2002-12-23 - -** Support for simple tasks w/o vars or I/O. [Richard Myers] - -**** Ignore DOS carriage returns in Linux files. [Richard Myers] - - -* Verilator 3.012 2002-12-18 - -**** Fixed parsing bug with casex statements containing case items - with bit extracts of parameters. [Richard Myers] - -**** Fixed bug which could cause writes of non-power-of-2 sized arrays to - corrupt memory beyond the size of the array. [Dan Lussier] - -**** Fixed bug which did not detect UNOPT problems caused by - submodules. See the description in the verilator man page. [John Deroo] - -**** Fixed compile with threaded Perl. [Ami Keren] - - -* Verilator 3.010 2002-11-03 - -*** Support SystemC 2.0.1. SystemPerl version 1.130 or newer is required. - -**** Fixed bug with inlined modules under other inlined modules. [Scott - Bleiweiss] - - -* Verilator 3.005 2002-10-21 - -**** Fixed X's in case (not casex/z) to constant propagate correctly. - -**** Fixed missing include. [Kurachi] - - -* Verilator 3.004 2002-10-10 - -*** Added /* verilator module_inline */ and associated optimizations. - -*** Allow /* verilator coverage_block_off */ in place of `coverage_block_off. - This prevents problems with Emacs AUTORESET. [Ray Strouble] - -**** Fixed `coverage_block_off also disabling subsequent blocks. - -**** Fixed unrolling of loops with multiple simple statements. - -**** Fixed compile warnings on newer GCC. [Kurachi] - -**** Additional concatenation optimizations. - - -* Verilator 3.003 2002-09-13 - -*** Now compiles on Windows 2000 with Cygwin. - -**** Fixed bug with pin assignments to wide memories. - -**** Optimize wire assignments to constants. - - -* Verilator 3.002 2002-08-19 - -** First public release of version 3. - - -* Verilator 3.000 2002-08-03 - -** All new code base. Many changes too numerous to mention. - -*** Approximately 4 times faster then Verilator 2. -*** Supports initial statements -*** Supports correct blocking/nonblocking assignments -*** Supports `defines across multiple modules -*** Optimizes call ordering, constant propagation, and dead code elimination. - - -* Verilator 2.1.8 2002-04-03 - -** All applications must now link against include/verilated.cpp - -*** Paths specified to verilator_make should be absolute, or be formed - to allow for execution in the object directory (prepend ../ to each path.) - This allows relative filenames for makes which hash and cache dependencies. - -**** Added warning when parameter constants are too large. [John Deroo] - -**** Added warning when x/?'s used in non-casez statements. - -**** Added warning when blocking assignments used in posedge blocks. [Dan Lussier] - -**** Split evaluation function into clocked and non-clocked, 20% perf gain. - - -* Verilator 2.1.5 2001-12-01 - -** Added coverage analysis. In conjunction with SystemC provide line - coverage reports, without SystemC, provide a hook to user written - accumulation function. See --coverage option of verilator_make. - -*** Relaxed multiply range checking - -*** Support for constants up to 128 bits - -*** Randomize values used when assigning to X's. - -**** Added -guard option of internal testing. - -**** Changed indentation in emitted code to be automatically generated. - -**** Fixed corruption of assignments of signal over 32 bits with non-0 lsb. - - -* Verilator 2.1.4 2001-11-16 - -** Added $c("c_commands();"); for embedding arbitrary C code in Verilog. - - -* Verilator 2.1.3 2001-11-03 - -** Support for parameters. - - -* Verilator 2.1.2 2001-10-25 - -** Verilog Errors now reference the .v file rather then the .vpp file. - -*** Support strings in assignments: reg [31:0] foo = "STRG"; - -*** Support %m in format strings. Ripped out old $info support, use - Verilog-Perl's vpm program instead. - -*** Convert $stop to call of v_stop() which user can define. - -**** Fixed bug where a==b==c would have wrong precedence rule. - -**** Fixed bug where XNOR on odd-bit-widths (~^ or ^~) had bad value. - - -* Verilator 2.1.1 2001-05-17 - -** New test_sp directory for System-Perl (SystemC) top level instantiation -of the Verilated code, lower modules are still C++ code. (Experimental). - -** New test_spp directory for Pure System-Perl (SystemC) where every module -is true SystemC code. (Experimental) - -*** Input ports are now loaded by pointer reference into the sub-cell. -This is faster on I-386 machines, as the stack must be used when there are -a large number of parameters. Also, this simplifies debugging as the value -of input ports exists for tracing. - -**** Many code cleanups towards standard C++ style conventions. - - -* Verilator 2.1.0 2001-05-08 - -**** Many code cleanups towards standard C++ style conventions. - - -* {Version history lost} - - -* Verilator 1.8 1996-07-08 - -** [Versions 0 to 1.8 were by Paul Wasson] - -**** Fixed single bit in concat from instance output incorrect offset bug. - - -* Verilator 1.7 1996-05-20 - -**** Mask unused bits of DONTCAREs. - - -* Verilator 1.6 1996-05-13 - -*** Added fasttrace script - - -* Verilator 1.5 1996-01-09 - -*** Pass structure pointer into translated code, - so multiple instances can use same functions. - -**** Fixed static value concat on casex items. - - -* Verilator 1.1 1995-03-30 - -*** Bug fixes, added verimake_partial script, performance improvements. - - -* Verilator 1.0c 1994-09-30 - -*** Initial release of Verilator - - -* Verilator 0.0 1994-07-08 - -**** First code written. - ----------------------------------------------------------------------- - -This uses outline mode in Emacs. See C-h m [M-x describe-mode]. +Copyright +========= Copyright 2001-2021 by Wilson Snyder. This program is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0. -SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -Local variables: -mode: outline -paragraph-separate: "[ \f\n]*$" -end: +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index 9d35df7de..cc4c8292c 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -13,6 +13,7 @@ Dan Petrisko David Horton David Stanford David Turner +Drew Taussig Driss Hafdi Edgar E. Iglesias Eric Rippey @@ -24,11 +25,12 @@ Glen Gibb Harald Heckmann Howard Su Huang Rui +HyungKi Jeong Iztok Jeras James Hanlon James Hutchinson -Jamey Hicks James Pallister +Jamey Hicks Jan Van Winkel Jean Berniolles Jeremy Bennett @@ -81,13 +83,11 @@ Todd Strader Tomasz Gorochowik Tymoteusz Blazejczyk Unai Martinez-Corral -Victor Besyakov Vassilis Papaefstathiou Veripool API Bot +Victor Besyakov Wilson Snyder Yossi Nivin Yuri Victorovich Yutetsu TAKATSUKASA Yves Mathieu -HyungKi Jeong -Drew Taussig From ba1f53a07076a8656dbe6e3886bf34a0be81ab5f Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 14 Mar 2021 20:36:43 -0400 Subject: [PATCH 018/110] Improve DEFPARAM warning text. --- docs/xml.rst | 1 - src/V3LinkDot.cpp | 4 +++- test_regress/t/t_lint_defparam_bad.out | 3 ++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/docs/xml.rst b/docs/xml.rst index 6231c8273..a6aab1e0c 100644 --- a/docs/xml.rst +++ b/docs/xml.rst @@ -69,7 +69,6 @@ The XML document consists of 4 sections within the top level by elements in the ```` elements using the ``dtype_id`` attribute. -.. __distribution: Distribution ============ diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index a9a3210b8..6bc5d26ea 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -1392,7 +1392,9 @@ private: } virtual void visit(AstDefParam* nodep) override { iterateChildren(nodep); - nodep->v3warn(DEFPARAM, "Suggest replace defparam assignment with Verilog 2001 #(." + nodep->v3warn(DEFPARAM, "defparam is deprecated (IEEE 1800-2017 C.4.1)\n" + << nodep->warnMore() + << "... Suggest use instantiation with #(." << nodep->prettyName() << "(...etc...))"); VSymEnt* foundp = m_statep->getNodeSym(nodep)->findIdFallback(nodep->path()); AstCell* cellp = foundp ? VN_CAST(foundp->nodep(), Cell) : nullptr; diff --git a/test_regress/t/t_lint_defparam_bad.out b/test_regress/t/t_lint_defparam_bad.out index f7093b05a..15a90af01 100644 --- a/test_regress/t/t_lint_defparam_bad.out +++ b/test_regress/t/t_lint_defparam_bad.out @@ -1,4 +1,5 @@ -%Warning-DEFPARAM: t/t_lint_defparam.v:10:19: Suggest replace defparam assignment with Verilog 2001 #(.P(...etc...)) +%Warning-DEFPARAM: t/t_lint_defparam.v:10:19: defparam is deprecated (IEEE 1800-2017 C.4.1) + : ... Suggest use instantiation with #(.P(...etc...)) 10 | defparam sub.P = 2; | ^ ... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message. From 8350c381c2717b112d854525e3f0d596e99d5549 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 14 Mar 2021 21:23:48 -0400 Subject: [PATCH 019/110] Add EOFNEWLINE warning when missing a newline at EOF. --- Changes | 1 + bin/verilator | 20 ++++++++++---- src/V3Error.h | 10 ++++--- src/V3FileLine.h | 8 ++++++ src/V3PreProc.cpp | 17 ++++++++++++ test_regress/t/t_lint_eofline.out | 3 +++ test_regress/t/t_lint_eofline.pl | 34 ++++++++++++++++++++++++ test_regress/t/t_lint_eofline_bad.out | 5 ++++ test_regress/t/t_lint_eofline_bad.pl | 38 +++++++++++++++++++++++++++ 9 files changed, 127 insertions(+), 9 deletions(-) create mode 100644 test_regress/t/t_lint_eofline.out create mode 100755 test_regress/t/t_lint_eofline.pl create mode 100644 test_regress/t/t_lint_eofline_bad.out create mode 100755 test_regress/t/t_lint_eofline_bad.pl diff --git a/Changes b/Changes index b19a62339..7bcadc42f 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,7 @@ Verilator 4.201 devel **Minor:** +* Add EOFNEWLINE warning when missing a newline at EOF. * Verilated signals now use VlWide and VlPacked in place of C arrays. * Fix class unpacked-array compile error (#2774). [Iru Cai] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] diff --git a/bin/verilator b/bin/verilator index d18eafd5c..36176b5ed 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1730,8 +1730,9 @@ received from third parties. Disable all code style related warning messages (note by default they are already disabled). This is equivalent to "-Wno-DECLFILENAME -Wno-DEFPARAM --Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY -Wno-PINNOCONNECT --Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED -Wno-VARHIDDEN". +-Wno-EOFNEWLINE -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY +-Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED +-Wno-VARHIDDEN". =item -Wpedantic @@ -1756,9 +1757,9 @@ enabled), but do not affect style messages. This is equivalent to =item -Wwarn-style Enable all code style related warning messages. This is equivalent to -"-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-INCABSPATH --Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN -Wwarn-UNUSED --Wwarn-VARHIDDEN". +"-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-EOFNEWLINE +-Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN +-Wwarn-UNUSED -Wwarn-VARHIDDEN". =item --x-assign 0 @@ -4501,6 +4502,15 @@ the label attached to the block start. Ignoring this warning will only suppress the lint check, it will simulate correctly. +=item EOFNEWLINE + +Warns that a file does not end in a newline. POSIX defines that a line +must end in newline, as otherwise for example 'cat' of the file may produce +undesirable results. + +Disabled by default as this is a code style warning; it will simulate +correctly. + =item GENCLK Deprecated and no longer used as a warning. Used to indicate that the diff --git a/src/V3Error.h b/src/V3Error.h index 1b8ff02ed..307b8a397 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -82,6 +82,7 @@ public: DECLFILENAME, // Declaration doesn't match filename DEPRECATED, // Feature will be deprecated ENDLABEL, // End lable name mismatch + EOFNEWLINE, // End-of-file missing newline GENCLK, // Generated Clock HIERBLOCK, // Ignored hierarchical block setting IFDEPTH, // If statements too deep @@ -160,7 +161,7 @@ public: "CASEINCOMPLETE", "CASEOVERLAP", "CASEWITHX", "CASEX", "CASTCONST", "CDCRSTLOGIC", "CLKDATA", "CMPCONST", "COLONPLUS", "COMBDLY", "CONTASSREG", "DEFPARAM", "DECLFILENAME", "DEPRECATED", - "ENDLABEL", "GENCLK", "HIERBLOCK", + "ENDLABEL", "EOFNEWLINE", "GENCLK", "HIERBLOCK", "IFDEPTH", "IGNOREDRETURN", "IMPERFECTSCH", "IMPLICIT", "IMPORTSTAR", "IMPURE", "INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE", @@ -207,9 +208,10 @@ public: // Warnings that are style only bool styleError() const { return (m_e == ASSIGNDLY // More than style, but for backward compatibility - || m_e == BLKSEQ || m_e == DEFPARAM || m_e == DECLFILENAME || m_e == IMPORTSTAR - || m_e == INCABSPATH || m_e == PINCONNECTEMPTY || m_e == PINNOCONNECT - || m_e == SYNCASYNCNET || m_e == UNDRIVEN || m_e == UNUSED || m_e == VARHIDDEN); + || m_e == BLKSEQ || m_e == DEFPARAM || m_e == DECLFILENAME || m_e == EOFNEWLINE + || m_e == IMPORTSTAR || m_e == INCABSPATH || m_e == PINCONNECTEMPTY + || m_e == PINNOCONNECT || m_e == SYNCASYNCNET || m_e == UNDRIVEN || m_e == UNUSED + || m_e == VARHIDDEN); } }; inline bool operator==(const V3ErrorCode& lhs, const V3ErrorCode& rhs) { diff --git a/src/V3FileLine.h b/src/V3FileLine.h index fa77fdafa..0d8519d83 100644 --- a/src/V3FileLine.h +++ b/src/V3FileLine.h @@ -148,11 +148,19 @@ public: #endif // METHODS void newContent(); + void contentLineno(int num) { + lineno(num); + m_contentLineno = num; + } void lineno(int num) { m_firstLineno = num; m_lastLineno = num; m_firstColumn = m_lastColumn = 1; } + void column(int firstColumn, int lastColumn) { + m_firstColumn = firstColumn; + m_lastColumn = lastColumn; + } void language(V3LangCode lang) { singleton().numberToLang(filenameno(), lang); } void filename(const string& name) { m_filenameno = singleton().nameToNumber(name); } void parent(FileLine* fileline) { m_parent = fileline; } diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index c71070add..2fd43fa54 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -810,6 +810,8 @@ void V3PreProcImp::openFile(FileLine*, VInFilter* filterp, const string& filenam // Filter all DOS CR's en-mass. This avoids bugs with lexing CRs in the wrong places. // This will also strip them from strings, but strings aren't supposed // to be multi-line without a "\" + int eof_newline = 0; // Number of characters following last newline + int eof_lineno = 1; for (StrList::iterator it = wholefile.begin(); it != wholefile.end(); ++it) { // We don't end-loop at \0 as we allow and strip mid-string '\0's (for now). bool strip = false; @@ -821,6 +823,12 @@ void V3PreProcImp::openFile(FileLine*, VInFilter* filterp, const string& filenam strip = true; break; } + if (VL_UNLIKELY(*cp == '\n')) { + eof_newline = 0; + ++eof_lineno; + } else { + ++eof_newline; + } } if (strip) { string out; @@ -836,6 +844,15 @@ void V3PreProcImp::openFile(FileLine*, VInFilter* filterp, const string& filenam // Reclaim memory; the push saved the string contents for us *it = ""; } + + // Warning check + if (eof_newline) { + FileLine* fl = new FileLine{flsp}; + fl->contentLineno(eof_lineno); + fl->column(eof_newline + 1, eof_newline + 1); + fl->v3warn(EOFNEWLINE, "Missing newline at end of file (POSIX 3.206)." + << fl->warnMore() << "... Suggest add newline."); + } } void V3PreProcImp::insertUnreadbackAtBol(const string& text) { diff --git a/test_regress/t/t_lint_eofline.out b/test_regress/t/t_lint_eofline.out new file mode 100644 index 000000000..d4f4a5251 --- /dev/null +++ b/test_regress/t/t_lint_eofline.out @@ -0,0 +1,3 @@ +`line 1 "obj_vlt/t_lint_eofline/t_lint_eofline_bad.v" 1 + +`line 2 "obj_vlt/t_lint_eofline/t_lint_eofline_bad.v" 2 diff --git a/test_regress/t/t_lint_eofline.pl b/test_regress/t/t_lint_eofline.pl new file mode 100755 index 000000000..be8639453 --- /dev/null +++ b/test_regress/t/t_lint_eofline.pl @@ -0,0 +1,34 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +use IO::File; +use strict; +use vars qw($Self); + +scenarios(vlt => 1); + +sub gen { + my $filename = shift; + + my $fh = IO::File->new(">$filename"); + # Empty file should not EOFLINE warn +} + +top_filename("$Self->{obj_dir}/t_lint_eofline_bad.v"); + +gen($Self->{top_filename}); + +lint( + verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME -E"], + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_eofline_bad.out b/test_regress/t/t_lint_eofline_bad.out new file mode 100644 index 000000000..ee6a52af0 --- /dev/null +++ b/test_regress/t/t_lint_eofline_bad.out @@ -0,0 +1,5 @@ +%Warning-EOFNEWLINE: obj_vlt/t_lint_eofline_bad/t_lint_eofline_bad.v:4:10: Missing newline at end of file (POSIX 3.206). : ... Suggest add newline. + 4 | endmodule + | ^ + ... Use "/* verilator lint_off EOFNEWLINE */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_lint_eofline_bad.pl b/test_regress/t/t_lint_eofline_bad.pl new file mode 100755 index 000000000..1528e4cef --- /dev/null +++ b/test_regress/t/t_lint_eofline_bad.pl @@ -0,0 +1,38 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +use IO::File; +use strict; +use vars qw($Self); + +scenarios(vlt => 1); + +sub gen { + my $filename = shift; + + my $fh = IO::File->new(">$filename"); + $fh->print("// Generated by t_lint_eofline_bad.pl\n"); + $fh->print("module t;\n"); + $fh->print("// No newline below:\n"); + $fh->print("endmodule"); # Intentionally no newline +} + +top_filename("$Self->{obj_dir}/t_lint_eofline_bad.v"); + +gen($Self->{top_filename}); + +lint( + verilator_flags2 => ["--lint-only -Wall -Wno-DECLFILENAME"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; From daf51741342b8db2a181e2f4b3b8d87daa785814 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 14 Mar 2021 21:26:56 -0400 Subject: [PATCH 020/110] Commentary --- bin/verilator | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/bin/verilator b/bin/verilator index 36176b5ed..ce28b6d45 100755 --- a/bin/verilator +++ b/bin/verilator @@ -2033,7 +2033,7 @@ This is an example similar to the above, but using SystemC. cat >our.v <<'EOF' module our (clk); input clk; // Clock is required to get initial activation - always @ (posedge clk) + always @(posedge clk) begin $display("Hello World"); $finish; end endmodule EOF @@ -2410,7 +2410,7 @@ example: // allow modulus. This is in units of the timeprecision // used in Verilog (or from --timescale-override) - double sc_time_stamp () { // Called by $time in Verilog + double sc_time_stamp() { // Called by $time in Verilog return main_time; // converts to double, to match // what SystemC does } @@ -2484,7 +2484,7 @@ Verilog, put in our.v: Then after Verilating, Verilator will create a file Vour__Dpi.h with the prototype to call this function: - extern int add (int a, int b); + extern int add(int a, int b); From the sc_main.cpp file (or another .cpp file passed to the Verilator command line, or the link), you'd then: @@ -2563,7 +2563,7 @@ wrapper: // This DPI function will read "din" import "DPI-C" context function void dpi_that_accesses_din(); - always @ (...) + always @(...) dpi_din_args(din); task dpi_din_args(input din); @@ -3488,7 +3488,7 @@ analysis.) For example: reg enable_r /*verilator clock_enable*/; wire gated_clk = clk & enable_r; - always_ff @ (posedge clk) + always_ff @(posedge clk) enable_r <= enable_early; The clock_enable attribute will cause the clock gate to be ignored in the @@ -3562,7 +3562,7 @@ IE, with the following reg splitme /* verilator isolate_assignments*/; // Note the placement of the semicolon above - always @* begin + always_comb begin if (....) begin splitme = ....; other assignments @@ -3575,13 +3575,13 @@ two blocks: It would then internally break it into (sort of): // All assignments excluding those to splitme - always @* begin + always_comb begin if (....) begin other assignments end end // All assignments to splitme - always @* begin + always_comb begin if (....) begin splitme = ....; end @@ -3825,7 +3825,7 @@ Verilator supports the Synthesis subset with other verification constructs being added over time. Verilator also simulates events as Synopsys's Design Compiler would; namely given a block of the form: - always @ (x) y = x & z; + always @(x) y = x & z; This will recompute y when there is even a potential for change in x or a change in z, that is when the flops computing x or z evaluate (which is @@ -4256,15 +4256,15 @@ Generally, this is caused by a register driven by both combo logic and a flop: logic [1:0] foo; - always @ (posedge clk) foo[0] <= ... - always @* foo[1] = ... + always @(posedge clk) foo[0] <= ... + always_comb foo[1] = ... Simply use a different register for the flop: logic [1:0] foo; - always @ (posedge clk) foo_flopped[0] <= ... - always @* foo[0] = foo_flopped[0]; - always @* foo[1] = ... + always @(posedge clk) foo_flopped[0] <= ... + always_comb foo[0] = foo_flopped[0]; + always_comb foo[1] = ... Or, this may also avoid the error: @@ -4279,7 +4279,7 @@ reasonable to do this if the generated signal is used ONLY later in the same block, however this style is generally discouraged as it is error prone. - always @ (posedge clk) foo = ... + always @(posedge clk) foo = ... Disabled by default as this is a code style warning; it will simulate correctly. @@ -4292,7 +4292,7 @@ were used, the simulator would have to copy large arrays every cycle. (In smaller loops, loop unrolling allows the delayed assignment to work, though it's a bit slower than a non-delayed assignment.) Here's an example - always @ (posedge clk) + always @(posedge clk) if (~reset_l) begin for (i=0; i<`ARRAY_SIZE; i++) begin array[i] = 0; // Non-delayed for verilator From f79e59b2268788e46520121b7639e1b99ec69bcf Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 16 Mar 2021 21:17:55 -0400 Subject: [PATCH 021/110] Commentary --- Changes | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Changes b/Changes index 7bcadc42f..b17e71805 100644 --- a/Changes +++ b/Changes @@ -1,6 +1,8 @@ -******************************* +.. for github, vim: syntax=reStructuredText + +=============================== Revision History and Change Log -******************************* +=============================== The changes in each Verilator version are described below. The contributors that suggested a given feature are shown in []. Thanks! From 12eb4e85ac01306ce61850d69f9cbfa3ca73134a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 16 Mar 2021 21:58:15 -0400 Subject: [PATCH 022/110] Changed TIMESCALEMOD from error into a warning. (#2838) --- Changes | 1 + bin/verilator | 12 +++++++----- src/V3Error.h | 3 +-- src/V3LinkLevel.cpp | 2 +- test_regress/t/t_timescale_lint_bad.out | 5 +++-- 5 files changed, 13 insertions(+), 10 deletions(-) diff --git a/Changes b/Changes index b17e71805..f13e2b07d 100644 --- a/Changes +++ b/Changes @@ -14,6 +14,7 @@ Verilator 4.201 devel **Minor:** * Add EOFNEWLINE warning when missing a newline at EOF. +* Changed TIMESCALEMOD from error into a warning. * Verilated signals now use VlWide and VlPacked in place of C arrays. * Fix class unpacked-array compile error (#2774). [Iru Cai] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] diff --git a/bin/verilator b/bin/verilator index ce28b6d45..96a44c640 100755 --- a/bin/verilator +++ b/bin/verilator @@ -4885,16 +4885,18 @@ correctly. =item TIMESCALEMOD -Error that `timescale is used in some but not all modules. -Recommend using --timescale argument, or in front of all modules use: +Warns that `timescale is used in some but not all modules. Recommend using +--timescale argument, or in front of all modules use: `include "timescale.vh" Then in that file set the timescale. -This is an error due to IEEE specifications, but it may be disabled similar -to warnings. Ignoring this error may result in a module having an -unexpected timescale. +It may be disabled similar to other warnings. Ignoring this warning may +result in a module having an unexpected timescale. + +IEEE recommends this be an error, for that behavior use +-Werror-TIMESCALEMOD. =item UNDRIVEN diff --git a/src/V3Error.h b/src/V3Error.h index 307b8a397..eb3ec178d 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -190,8 +190,7 @@ public: // Later -Werror- options may make more of these. bool pretendError() const { return (m_e == ASSIGNIN || m_e == BLKANDNBLK || m_e == BLKLOOPINIT || m_e == CONTASSREG - || m_e == IMPURE || m_e == PKGNODECL || m_e == PROCASSWIRE // - || m_e == TIMESCALEMOD); // Says IEEE + || m_e == IMPURE || m_e == PKGNODECL || m_e == PROCASSWIRE); // Says IEEE } // Warnings to mention manual bool mentionManual() const { diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index fd118f4a9..53ee0f514 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -106,7 +106,7 @@ void V3LinkLevel::timescaling(const ModVec& mods) { && !(VN_IS(nodep, Package) && VN_CAST(nodep, Package)->isDollarUnit())) { nodep->v3warn(TIMESCALEMOD, "Timescale missing on this module as other modules have " - "it (IEEE 1800-2017 3.14.2.2)\n" + "it (IEEE 1800-2017 3.14.2.3)\n" << nodep->warnContextPrimary() << '\n' << modTimedp->warnOther() << "... Location of module with timescale\n" diff --git a/test_regress/t/t_timescale_lint_bad.out b/test_regress/t/t_timescale_lint_bad.out index fece9ec2e..43d692c37 100644 --- a/test_regress/t/t_timescale_lint_bad.out +++ b/test_regress/t/t_timescale_lint_bad.out @@ -1,7 +1,8 @@ -%Error-TIMESCALEMOD: t/t_timescale_lint_bad.v:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2) +%Warning-TIMESCALEMOD: t/t_timescale_lint_bad.v:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.3) 7 | module pre_no_ts; | ^~~~~~~~~ - t/t_timescale_lint_bad.v:12:8: ... Location of module with timescale + t/t_timescale_lint_bad.v:12:8: ... Location of module with timescale 12 | module t; | ^ + ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. %Error: Exiting due to From 26c0fa0a6a868f656f1599d5a40dfd7922e0db5c Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 16 Mar 2021 22:42:28 -0400 Subject: [PATCH 023/110] Fix --timescale-override not suppressing TIMESCALEMOD (#2838). --- Changes | 1 + src/V3LinkLevel.cpp | 8 ++++++-- test_regress/t/t_timescale_lint2.pl | 20 ++++++++++++++++++++ test_regress/t/t_timescale_lint_bad.out | 4 ++-- test_regress/t/t_timescale_lint_bad.pl | 2 ++ test_regress/t/t_timescale_lint_bad.v | 18 ------------------ 6 files changed, 31 insertions(+), 22 deletions(-) create mode 100755 test_regress/t/t_timescale_lint2.pl delete mode 100644 test_regress/t/t_timescale_lint_bad.v diff --git a/Changes b/Changes index f13e2b07d..fd3cb4cf3 100644 --- a/Changes +++ b/Changes @@ -19,6 +19,7 @@ Verilator 4.201 devel * Fix class unpacked-array compile error (#2774). [Iru Cai] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] * Fix false $dumpfile warning on model save (#2834). [Yinan Xu] +* Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett] Verilator 4.200 2021-03-12 diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index 53ee0f514..de3eeff3e 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -102,8 +102,12 @@ void V3LinkLevel::timescaling(const ModVec& mods) { for (AstNodeModule* nodep : mods) { if (nodep->timeunit().isNone()) { - if (modTimedp && !VN_IS(nodep, Iface) && !VN_IS(nodep, Primitive) - && !(VN_IS(nodep, Package) && VN_CAST(nodep, Package)->isDollarUnit())) { + if (modTimedp // Got previous + && ( // unit doesn't already include an override + v3Global.opt.timeOverrideUnit().isNone() + && v3Global.opt.timeDefaultUnit().isNone()) + && (!VN_IS(nodep, Iface) && !VN_IS(nodep, Primitive) + && !(VN_IS(nodep, Package) && VN_CAST(nodep, Package)->isDollarUnit()))) { nodep->v3warn(TIMESCALEMOD, "Timescale missing on this module as other modules have " "it (IEEE 1800-2017 3.14.2.3)\n" diff --git a/test_regress/t/t_timescale_lint2.pl b/test_regress/t/t_timescale_lint2.pl new file mode 100755 index 000000000..6a8798deb --- /dev/null +++ b/test_regress/t/t_timescale_lint2.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +top_filename("t/t_timescale_lint.v"); + +lint( + verilator_flags2 => ["--lint-only --timescale 1ns/1ns"], + ); + +ok(1); +1; diff --git a/test_regress/t/t_timescale_lint_bad.out b/test_regress/t/t_timescale_lint_bad.out index 43d692c37..dea8a0a8c 100644 --- a/test_regress/t/t_timescale_lint_bad.out +++ b/test_regress/t/t_timescale_lint_bad.out @@ -1,7 +1,7 @@ -%Warning-TIMESCALEMOD: t/t_timescale_lint_bad.v:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.3) +%Warning-TIMESCALEMOD: t/t_timescale_lint.v:7:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.3) 7 | module pre_no_ts; | ^~~~~~~~~ - t/t_timescale_lint_bad.v:12:8: ... Location of module with timescale + t/t_timescale_lint.v:12:8: ... Location of module with timescale 12 | module t; | ^ ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_timescale_lint_bad.pl b/test_regress/t/t_timescale_lint_bad.pl index 7ad36d5cd..022ca4683 100755 --- a/test_regress/t/t_timescale_lint_bad.pl +++ b/test_regress/t/t_timescale_lint_bad.pl @@ -10,6 +10,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(linter => 1); +top_filename("t/t_timescale_lint.v"); + lint( verilator_flags2 => ["--lint-only"], fails => 1, diff --git a/test_regress/t/t_timescale_lint_bad.v b/test_regress/t/t_timescale_lint_bad.v deleted file mode 100644 index ae23c49dc..000000000 --- a/test_regress/t/t_timescale_lint_bad.v +++ /dev/null @@ -1,18 +0,0 @@ -// DESCRIPTION: Verilator: Verilog Test module -// -// This file ONLY is placed under The Creative Commons Public Domain, for -// any use, without warranty, 2020 by Wilson Snyder. -// SPDX-License-Identifier: CC0-1.0 - -module pre_no_ts; -endmodule - -`timescale 1ns/1ns - -module t; - pre_no_ts pre_no_ts(); - post_no_ts pst_no_ts(); -endmodule - -module post_no_ts; -endmodule From 38f6a467e9871e0c4a4792535af813240b8ab197 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 16 Mar 2021 22:44:13 -0400 Subject: [PATCH 024/110] Fix --timescale-override not suppressing TIMESCALEMOD (#2838). --- test_regress/t/t_timescale_lint.pl | 18 ++++++++++++++++++ test_regress/t/t_timescale_lint.v | 18 ++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100755 test_regress/t/t_timescale_lint.pl create mode 100644 test_regress/t/t_timescale_lint.v diff --git a/test_regress/t/t_timescale_lint.pl b/test_regress/t/t_timescale_lint.pl new file mode 100755 index 000000000..051f08f78 --- /dev/null +++ b/test_regress/t/t_timescale_lint.pl @@ -0,0 +1,18 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + verilator_flags2 => ["--lint-only --timescale-override 1ns/1ns"], + ); + +ok(1); +1; diff --git a/test_regress/t/t_timescale_lint.v b/test_regress/t/t_timescale_lint.v new file mode 100644 index 000000000..ae23c49dc --- /dev/null +++ b/test_regress/t/t_timescale_lint.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under The Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module pre_no_ts; +endmodule + +`timescale 1ns/1ns + +module t; + pre_no_ts pre_no_ts(); + post_no_ts pst_no_ts(); +endmodule + +module post_no_ts; +endmodule From dfab80fab16e88d8e76cdc31f32ea78d5b827e05 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 16 Mar 2021 22:52:29 -0400 Subject: [PATCH 025/110] Fix false TIMESCALEMOD on generate-ignored instances (#2838). --- Changes | 1 + bin/verilator | 4 ++-- src/V3Ast.h | 1 + src/V3AstNodes.h | 9 +++++++++ src/V3LinkLevel.cpp | 4 ++-- test_regress/t/t_flag_timescale_override.out | 1 + test_regress/t/t_flag_timescale_override.v | 8 ++++++++ test_regress/t/t_flag_timescale_override2.out | 1 + test_regress/t/t_hier_block.pl | 1 + test_regress/t/t_sv_cpu.pl | 3 ++- test_regress/t/t_timescale_udp.v | 8 ++++++++ 11 files changed, 36 insertions(+), 5 deletions(-) diff --git a/Changes b/Changes index fd3cb4cf3..30d299c1f 100644 --- a/Changes +++ b/Changes @@ -20,6 +20,7 @@ Verilator 4.201 devel * Fix exceeding command-line ar limit (#2834). [Yinan Xu] * Fix false $dumpfile warning on model save (#2834). [Yinan Xu] * Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett] +* Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett] Verilator 4.200 2021-03-12 diff --git a/bin/verilator b/bin/verilator index 96a44c640..d17a442a2 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1509,8 +1509,8 @@ good value. =item --timescale I/I Sets default timescale, timeunit and timeprecision for when `timescale does -not occur in sources. Default is "1ps/1ps" (to match SystemC). This is -overridden by C<--timescale-override>. +not occur before a given module. Default is "1ps/1ps" (to match SystemC). +This is overridden by C<--timescale-override>. =item --timescale-override I/I diff --git a/src/V3Ast.h b/src/V3Ast.h index 3c838d9c4..abf9474cc 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -2880,6 +2880,7 @@ public: virtual void dump(std::ostream& str) const override; virtual bool maybePointedTo() const override { return true; } virtual string name() const override { return m_name; } + virtual bool timescaleMatters() const = 0; AstNode* stmtsp() const { return op2p(); } // op2 = List of statements AstActive* activesp() const { return VN_CAST(op3p(), Active); } // op3 = List of i/sblocks // METHODS diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 5da14deca..d0b37b1ea 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -290,6 +290,7 @@ public: ASTNODE_NODE_FUNCS(ClassPackage) virtual string verilogKwd() const override { return "/*class*/package"; } virtual const char* broken() const override; + virtual bool timescaleMatters() const override { return false; } AstClass* classp() const { return m_classp; } void classp(AstClass* classp) { m_classp = classp; } }; @@ -317,6 +318,7 @@ public: BROKEN_RTN(m_classOrPackagep && !m_classOrPackagep->brokeExists()); return nullptr; } + virtual bool timescaleMatters() const override { return false; } // op1/op2/op3 in AstNodeModule AstClassPackage* classOrPackagep() const { return m_classOrPackagep; } void classOrPackagep(AstClassPackage* classpackagep) { m_classOrPackagep = classpackagep; } @@ -2559,6 +2561,7 @@ public: , m_isProgram{program} {} ASTNODE_NODE_FUNCS(Module) virtual string verilogKwd() const override { return m_isProgram ? "program" : "module"; } + virtual bool timescaleMatters() const override { return true; } }; class AstNotFoundModule final : public AstNodeModule { @@ -2568,6 +2571,7 @@ public: : ASTGEN_SUPER(fl, name) {} ASTNODE_NODE_FUNCS(NotFoundModule) virtual string verilogKwd() const override { return "/*not-found-*/ module"; } + virtual bool timescaleMatters() const override { return false; } }; class AstPackage final : public AstNodeModule { @@ -2577,6 +2581,7 @@ public: : ASTGEN_SUPER(fl, name) {} ASTNODE_NODE_FUNCS(Package) virtual string verilogKwd() const override { return "package"; } + virtual bool timescaleMatters() const override { return !isDollarUnit(); } static string dollarUnitName() { return AstNode::encodeName("$unit"); } bool isDollarUnit() const { return name() == dollarUnitName(); } }; @@ -2588,6 +2593,7 @@ public: : ASTGEN_SUPER(fl, name) {} ASTNODE_NODE_FUNCS(Primitive) virtual string verilogKwd() const override { return "primitive"; } + virtual bool timescaleMatters() const override { return false; } }; class AstPackageExportStarStar final : public AstNode { @@ -2653,6 +2659,9 @@ public: AstIface(FileLine* fl, const string& name) : ASTGEN_SUPER(fl, name) {} ASTNODE_NODE_FUNCS(Iface) + // Interfaces have `timescale applicability but lots of code seems to + // get false warnings if we enable this + virtual bool timescaleMatters() const override { return false; } }; class AstMemberSel final : public AstNodeMath { diff --git a/src/V3LinkLevel.cpp b/src/V3LinkLevel.cpp index de3eeff3e..add541016 100644 --- a/src/V3LinkLevel.cpp +++ b/src/V3LinkLevel.cpp @@ -101,13 +101,13 @@ void V3LinkLevel::timescaling(const ModVec& mods) { v3Global.rootp()->timeunit(unit); for (AstNodeModule* nodep : mods) { + if (!v3Global.opt.timeOverrideUnit().isNone()) nodep->timeunit(unit); if (nodep->timeunit().isNone()) { if (modTimedp // Got previous && ( // unit doesn't already include an override v3Global.opt.timeOverrideUnit().isNone() && v3Global.opt.timeDefaultUnit().isNone()) - && (!VN_IS(nodep, Iface) && !VN_IS(nodep, Primitive) - && !(VN_IS(nodep, Package) && VN_CAST(nodep, Package)->isDollarUnit()))) { + && nodep->timescaleMatters()) { nodep->v3warn(TIMESCALEMOD, "Timescale missing on this module as other modules have " "it (IEEE 1800-2017 3.14.2.3)\n" diff --git a/test_regress/t/t_flag_timescale_override.out b/test_regress/t/t_flag_timescale_override.out index b82ab0b9a..7ae0946dc 100644 --- a/test_regress/t/t_flag_timescale_override.out +++ b/test_regress/t/t_flag_timescale_override.out @@ -1,2 +1,3 @@ Time scale of t is 1ms / 1us +Time scale of sub is 1ms / 1us *-* All Finished *-* diff --git a/test_regress/t/t_flag_timescale_override.v b/test_regress/t/t_flag_timescale_override.v index 61ebcfd56..e66060f4c 100644 --- a/test_regress/t/t_flag_timescale_override.v +++ b/test_regress/t/t_flag_timescale_override.v @@ -7,9 +7,17 @@ `timescale 1s/1s module t; + sub sub (); initial begin $printtimescale; + sub.pts(); $write("*-* All Finished *-*\n"); $finish; end endmodule + +module sub; + task pts; + $printtimescale; + endtask +endmodule diff --git a/test_regress/t/t_flag_timescale_override2.out b/test_regress/t/t_flag_timescale_override2.out index 3a0d42216..d75101d0e 100644 --- a/test_regress/t/t_flag_timescale_override2.out +++ b/test_regress/t/t_flag_timescale_override2.out @@ -1,2 +1,3 @@ Time scale of t is 1s / 1us +Time scale of sub is 1s / 1us *-* All Finished *-* diff --git a/test_regress/t/t_hier_block.pl b/test_regress/t/t_hier_block.pl index fe743cb94..cffc7ba04 100755 --- a/test_regress/t/t_hier_block.pl +++ b/test_regress/t/t_hier_block.pl @@ -20,6 +20,7 @@ compile( v_flags2 => ['t/t_hier_block.cpp'], verilator_flags2 => ['--stats', ($Self->{vltmt} ? ' --threads 6' : ''), '--hierarchical', + '--Wno-TIMESCALEMOD', '--CFLAGS', '"-pipe -DCPP_MACRO=cplusplus"' ], ); diff --git a/test_regress/t/t_sv_cpu.pl b/test_regress/t/t_sv_cpu.pl index 6cc81f85a..5bc4f46a7 100755 --- a/test_regress/t/t_sv_cpu.pl +++ b/test_regress/t/t_sv_cpu.pl @@ -34,7 +34,8 @@ compile( "t/t_sv_cpu_code/cpu.sv", "t/t_sv_cpu_code/chip.sv"], vcs_flags2 => ["-R -sverilog +memcbk -y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code"], - verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t"], + verilator_flags2 => ["-y t/t_sv_cpu_code +libext+.sv+ +incdir+t/t_sv_cpu_code --top-module t", + "--timescale-override 1ns/1ps"], iv_flags2 => ["-yt/t_sv_cpu_code -It/t_sv_cpu_code -Y.sv"], ); diff --git a/test_regress/t/t_timescale_udp.v b/test_regress/t/t_timescale_udp.v index 4b30c71ef..2b3bd9da9 100644 --- a/test_regress/t/t_timescale_udp.v +++ b/test_regress/t/t_timescale_udp.v @@ -7,10 +7,18 @@ `timescale 1ns/1ns module t; p p (); + + // Also check not-found modules + localparam NOT = 0; + if (NOT) begin + NotFound not_found(.*); + end + initial begin $write("*-* All Finished *-*\n"); $finish; end + endmodule `timescale 1ns/1ns From c20bced4858753513375ec2515dfd667d314255d Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 17 Mar 2021 18:25:54 -0400 Subject: [PATCH 026/110] Fix --output-split with class extends (#2839). --- Changes | 1 + include/verilated.cpp | 4 ++-- src/V3EmitC.cpp | 12 ++++++------ test_regress/t/t_class_split.pl | 22 +++++++++++++++++++++ test_regress/t/t_class_split.v | 34 +++++++++++++++++++++++++++++++++ 5 files changed, 65 insertions(+), 8 deletions(-) create mode 100755 test_regress/t/t_class_split.pl create mode 100644 test_regress/t/t_class_split.v diff --git a/Changes b/Changes index 30d299c1f..d7923afde 100644 --- a/Changes +++ b/Changes @@ -21,6 +21,7 @@ Verilator 4.201 devel * Fix false $dumpfile warning on model save (#2834). [Yinan Xu] * Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett] * Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett] +* Fix --output-split with class extends (#2839). [Iru Cai] Verilator 4.200 2021-03-12 diff --git a/include/verilated.cpp b/include/verilated.cpp index 0ee5a46e6..06c632e2e 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -2403,6 +2403,8 @@ void VerilatedContextImp::commandArgVl(const std::string& arg) { VL_PRINTF_MT("For help, please see 'verilator --help'\n"); VL_FATAL_MT("COMMAND_LINE", 0, "", "Exiting due to command line argument (not an error)"); + } else if (arg == "+verilator+noassert") { + assertOn(false); } else if (commandArgVlValue(arg, "+verilator+prof+threads+start+", value /*ref*/)) { profThreadsStart(atoll(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+prof+threads+window+", value /*ref*/)) { @@ -2413,8 +2415,6 @@ void VerilatedContextImp::commandArgVl(const std::string& arg) { randReset(atoi(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+seed+", value /*ref*/)) { randSeed(atoi(value.c_str())); - } else if (arg == "+verilator+noassert") { - assertOn(false); } else if (arg == "+verilator+V") { VerilatedImp::versionDump(); // Someday more info too VL_FATAL_MT("COMMAND_LINE", 0, "", diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 0ea41997c..a83efb16b 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -1853,7 +1853,7 @@ class EmitCImp final : EmitCStmts { void emitTextSection(AstType type); // High level void emitImpTop(AstNodeModule* modp); - void emitImp(AstNodeModule* modp); + void emitImp(AstNodeModule* fileModp, AstNodeModule* modp); void emitSettleLoop(const std::string& eval_call, bool initial); void emitWrapEval(AstNodeModule* modp); void emitWrapFast(AstNodeModule* modp); @@ -3351,7 +3351,7 @@ void EmitCImp::emitImpTop(AstNodeModule* fileModp) { emitTextSection(AstType::atScImpHdr); } -void EmitCImp::emitImp(AstNodeModule* modp) { +void EmitCImp::emitImp(AstNodeModule* fileModp, AstNodeModule* modp) { puts("\n//==========\n"); if (m_slow) { string section; @@ -3374,7 +3374,7 @@ void EmitCImp::emitImp(AstNodeModule* modp) { // Blocks for (AstNode* nodep = modp->stmtsp(); nodep; nodep = nodep->nextp()) { if (AstCFunc* funcp = VN_CAST(nodep, CFunc)) { - maybeSplit(modp); + maybeSplit(fileModp); mainDoFunc(funcp); } } @@ -3427,14 +3427,14 @@ void EmitCImp::mainImp(AstNodeModule* modp, bool slow) { m_ofp = newOutCFile(fileModp, !m_fast, true /*source*/); emitImpTop(fileModp); - emitImp(modp); + emitImp(fileModp, modp); if (AstClassPackage* packagep = VN_CAST(modp, ClassPackage)) { // Put the non-static class implementation in same C++ files as // often optimizations are possible when both are seen by the // compiler together m_modp = packagep->classp(); - emitImp(packagep->classp()); + emitImp(fileModp, packagep->classp()); m_modp = modp; } @@ -3447,7 +3447,7 @@ void EmitCImp::mainImp(AstNodeModule* modp, bool slow) { vxp = vxp->verticesNextp()) { const ExecMTask* mtaskp = dynamic_cast(vxp); if (mtaskp->threadRoot()) { - maybeSplit(modp); + maybeSplit(fileModp); // Only define one function for all the mtasks packed on // a given thread. We'll name this function after the // root mtask though it contains multiple mtasks' worth diff --git a/test_regress/t/t_class_split.pl b/test_regress/t/t_class_split.pl new file mode 100755 index 000000000..2dd83547c --- /dev/null +++ b/test_regress/t/t_class_split.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ['--output-split 10'], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_class_split.v b/test_regress/t/t_class_split.v new file mode 100644 index 000000000..7c6a6b8e8 --- /dev/null +++ b/test_regress/t/t_class_split.v @@ -0,0 +1,34 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Iru Cai. +// SPDX-License-Identifier: CC0-1.0 + +class Cls1; + int ctr; + task run(); + $display("%d", ctr); + ctr = ctr + 1; + endtask: run +endclass; + +class Cls2 extends Cls1; + task runtask(); + run(); + run(); + run(); + run(); + run(); + run(); + endtask: runtask +endclass + +module top; + Cls2 o; + initial begin + o = new; + o.runtask(); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule From 5da9368032654c0a5d9bc13a104fb7c7eb7c2f22 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 17 Mar 2021 18:39:32 -0400 Subject: [PATCH 027/110] Update contributors. --- bin/verilator | 145 ++++++++++++++++++++++++++------------------------ 1 file changed, 76 insertions(+), 69 deletions(-) diff --git a/bin/verilator b/bin/verilator index d17a442a2..f63734ec3 100755 --- a/bin/verilator +++ b/bin/verilator @@ -5683,75 +5683,82 @@ Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van Cauwenberghe, Gene Weber, and Clifford Wolf. Some of the people who have provided ideas, and feedback for Verilator -include: David Addison, Tariq B. Ahmad, Nikana Anastasiadis, Hans Van -Antwerpen, Vasu Arasanipalai, Jens Arm, Sharad Bagri, Matthew Ballance, -Andrew Bardsley, Matthew Barr, Geoff Barrett, Julius Baxter, Jeremy -Bennett, Michael Berman, Victor Besyakov, Moinak Bhattacharyya, David -Binderman, Piotr Binkowski, Johan Bjork, David Black, Tymoteusz Blazejczyk, -Daniel Bone, Gregg Bouchard, Christopher Boumenot, Nick Bowler, Byron -Bradley, Bryan Brady, Maarten De Braekeleer, Charlie Brej, J Briquet, Lane -Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, Tony Bybell, Ted -Campbell, Chris Candler, Lauren Carlson, Donal Casey, Sebastien Van -Cauwenberghe, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert -A. Clark, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean Cross, -George Cuan, Joe DErrico, Lukasz Dalek, Laurens van Dam, Gunter -Dannoritzer, Ashutosh Das, Bernard Deadman, John Demme, Mike Denio, John -Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny Ding, Jacko Dirks, -Ivan Djordjevic, Jonathon Donaldson, Leendert van Doorn, Sebastian -Dressler, Alex Duller, Jeff Dutton, Tomas Dzetkulic, Usuario Eda, Charles -Eddleston, Chandan Egbert, Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, -Mats Engstrom, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi -Finkelstein, Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, -Benjamin Gartner, Christian Gelinek, Peter Gerst, Glen Gibb, Michael -Gielda, Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Amir -Gonnen, Chitlesh Goorah, Kai Gossner, Sergi Granell, Al Grant, Alexander -Grobman, Xuan Guo, Driss Hafdi, Neil Hamilton, James Hanlon, Oyvind Harboe, -Jannis Harder, Junji Hashimoto, Thomas Hawkins, Mitch Hayenga, Robert -Henry, Stephen Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew -Holme, Hiroki Honda, Alex Hornung, David Horton, Peter Horvath, Jae -Hossell, Alan Hunter, James Hutchinson, Jamie Iles, Ben Jackson, Shareef -Jalloq, Krzysztof Jankowski, HyungKi Jeong, Iztok Jeras, James Johnson, -Christophe Joly, Franck Jullien, James Jung, Mike Kagen, Arthur Kahlich, -Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, Kanad Kanhere, Patricio -Kaplan, Pieter Kapsenberg, Ralf Karge, Dan Katz, Sol Katzman, Ian Kennedy, -Jonathan Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, -Gernot Koch, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, Will -Korteland, Wojciech Koszek, Varun Koyyalagunta, David Kravitz, Roland -Kruse, Sergey Kvachonok, Charles Eric LaForest, Ed Lander, Steve Lang, -Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor Lesik, -John Li, Eivind Liland, Yu Sheng Lin, Charlie Lind, Andrew Ling, Jiuyang -Liu, Paul Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan -Ludwig, Dan Lussier, Fred Ma, Duraid Madina, Affe Mao, Julien Margetts, -Mark Marshall, Alfonso Martinez, Yves Mathieu, Patrick Maupin, Jason -McMullan, Elliot Mednick, Wim Michiels, Miodrag Milanovic, Wai Sum Mong, -Peter Monsson, Sean Moore, Dennis Muhlestein, John Murphy, Matt Myers, -Nathan Myers, Richard Myers, Dimitris Nalbantis, Peter Nelson, Bob Newgard, -Cong Van Nguyen, Paul Nitza, Yossi Nivin, Pete Nixon, Lisa Noack, Mark -Nodine, Kuba Ober, Andreas Olofsson, Aleksander Osman, James Pallister, -Vassilis Papaefstathiou, Brad Parker, Dan Petrisko, Maciej Piechotka, David -Pierce, Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich -Porter, Niranjan Prabhu, Usha Priyadharshini, Mark Jackson Pulver, Prateek -Puri, Marshal Qiao, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, -Odd Magne Reitan, Frederic Requin, Frederick Requin, Dustin Richmond, -Alberto Del Rio, Eric Rippey, Oleg Rodionov, Ludwig Rogiers, Paul Rolfe, -Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Jan Egil Ruud, Denis -Rystsov, John Sanguinetti, Galen Seitz, Salman Sheikh, Hao Shi, Mike -Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Anderson Ignacio Da Silva, -Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim Snyder, -Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, Wei Song, Art Stamness, -David Stanford, John Stevenson, Pete Stevenson, Patrick Stewart, Rob -Stoddard, Todd Strader, John Stroebel, Sven Stucki, Howard Su, Emerson -Suguimoto, Gene Sullivan, Qingyao Sun, Renga Sundararajan, Rupert -Swarbrick, Yutetsu Takatsukasa, Peter Tengstrand, Wesley Terpstra, Rui -Terra, Stefan Thiede, Gary Thomas, Ian Thompson, Kevin Thompson, Mike -Thyer, Hans Tichelaar, Viktor Tomov, Steve Tong, Michael Tresidder, Neil -Turton, Srini Vemuri, Yuri Victorovich, Bogdan Vukobratovic, Holger -Waechtler, Philipp Wagner, Stefan Wallentowitz, Shawn Wang, Paul Wasson, -Greg Waters, Thomas Watts, Eugene Weber, David Welch, Thomas J Whatson, -Marco Widmer, Leon Wildman, Daniel Wilkerson, Gerald Williams, Trevor -Williams, Jan Van Winkel, Jeff Winston, Joshua Wise, Clifford Wolf, Tobias -Wolfel, Johan Wouters, Junyi Xi, Ding Xiaoliang, Jie Xu, Mandy Xu, -Takatsukasa Y, Luke Yang, and Amir Yazdanbakhsh. +include: David Addison, Nikana Anastasiadis, Vasu Arasanipalai, Jens Arm, +Tariq B. Ahmad, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew +Barr, Geoff Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael +Berman, Jean Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof +Bieganski, David Binderman, Piotr Binkowski, Johan Bjork, David Black, +Tymoteusz Blazejczyk, Daniel Bone, Morten Borup Petersen, Gregg Bouchard, +Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Charlie +Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, +Tony Bybell, Iru Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal +Casey, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark, +Ryan Clarke, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean +Cross, George Cuan, Joe DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh +Das, Maarten De Braekeleer, Bernard Deadman, Alberto Del Rio, John Demme, +Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny +Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Sebastian Dressler, +Alex Duller, Jeff Dutton, Tomas Dzetkulic, Richard E George, Edgar +E. Iglesias, Usuario Eda, Charles Eddleston, Chandan Egbert, Jan Egil Ruud, +Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Charles Eric +LaForest, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein, +Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner, +Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl, +Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Andrew +Goessling, Amir Gonnen, Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner, +Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil +Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto, +Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry, Stephen +Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki +Honda, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath, Jae +Hossell, Kuoping Hsu, Alan Hunter, James Hutchinson, Anderson Ignacio da +Silva, Jamie Iles, Thomas J Whatson, Ben Jackson, Mark Jackson Pulver, +Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong, Iztok +Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike +Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, +Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf +Karge, Dan Katz, Sol Katzman, Ian Kennedy, Michael Killough, Jonathan +Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot +Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, +Will Korteland, Wojciech Koszek, Varun Koyyalagunta, Markus Krause, David +Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok, Ed Lander, Steve +Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor +Lesik, John Li, Eivind Liland, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul +Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan +Lussier, Fred Ma, Duraid Madina, Odd Magne Reitan, Affe Mao, Julien +Margetts, Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Yves +Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot Mednick, +Wim Michiels, Miodrag Milanovic, Peter Monsson, Sean Moore, Dennis +Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris +Nalbantis, Peter Nelson, Bob Newgard, Paul Nitza, Yossi Nivin, Pete Nixon, +Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz, +Aleksander Osman, Don Owen, James Pallister, Vassilis Papaefstathiou, Brad +Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Cody Piersall, +Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter, +Niranjan Prabhu, Usha Priyadharshini, Prateek Puri, Marshal Qiao, Nandu +Raj, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Frederic +Requin, Dustin Richmond, Samuel Riedel, Eric Rippey, Oleg Rodionov, Ludwig +Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Denis +Rystsov, John Sanguinetti, Galen Seitz, Joseph Shaker, Salman Sheikh, Yu +Sheng Lin, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan +Shupei, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim +Snyder, Wilson Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, +Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson, +Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki, +Howard Su, Emerson Suguimoto, Gene Sullivan, Wai Sum Mong, Qingyao Sun, +Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Thierry Tambe, +Drew Taussig, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede, +Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, +Viktor Tomov, Steve Tong, Alex Torregrosa, Michael Tresidder, David Turner, +Neil Turton, Cong Van Nguyen, Hans Van Antwerpen, Jan Van Winkel, Sebastien +Van Cauwenberghe, Laurens van Dam, Leendert van Doorn, Srini Vemuri, Yuri +Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan +Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene +Weber, David Welch, Martin Whitaker, Marco Widmer, Leon Wildman, Daniel +Wilkerson, Gerald Williams, Trevor Williams, Jeff Winston, Joshua Wise, +Clifford Wolf, Tobias Wolfel, Johan Wouters, Paul Wright, Junyi Xi, Ding +Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke Yang, Amir Yazdanbakhsh, and +Keyi Zhang. Thanks to them, and all those we've missed including above, or wished to remain anonymous. From 96f9f8558bd47f8291bdd615abecb957a7004e5b Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 17 Mar 2021 18:59:45 -0400 Subject: [PATCH 028/110] Mark --no-relative-cfuncs as scheduled for deprecation. --- Changes | 1 + bin/verilator | 5 +++++ src/V3Options.cpp | 3 +++ test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl | 2 +- 4 files changed, 10 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index d7923afde..5a4d10fb8 100644 --- a/Changes +++ b/Changes @@ -16,6 +16,7 @@ Verilator 4.201 devel * Add EOFNEWLINE warning when missing a newline at EOF. * Changed TIMESCALEMOD from error into a warning. * Verilated signals now use VlWide and VlPacked in place of C arrays. +* Mark --no-relative-cfuncs as scheduled for deprecation. * Fix class unpacked-array compile error (#2774). [Iru Cai] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] * Fix false $dumpfile warning on model save (#2834). [Yinan Xu] diff --git a/bin/verilator b/bin/verilator index f63734ec3..478c06c0f 100755 --- a/bin/verilator +++ b/bin/verilator @@ -5142,6 +5142,11 @@ Verilator currently requires C++11 or newer compilers. Verilator will require C++14 or newer compilers for both compiling Verilator and compiling Verilated models no sooner than January 2022. +=item --no-relative-cfuncs + +The --no-relative-cfuncs option is not be required by any C++11 compliant +compiler and is planned for removal no sooner than July 2021. + =item --inhibit-sim The --inhibit-sim option is planned for removal no sooner than July 2021. diff --git a/src/V3Options.cpp b/src/V3Options.cpp index eb0ff8828..a13340cf6 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1088,6 +1088,9 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char m_quietExit = flag; } else if (onoff(sw, "-relative-cfuncs", flag /*ref*/)) { m_relativeCFuncs = flag; + if (!m_relativeCFuncs) + fl->v3warn(DEPRECATED, + "Deprecated --no-relative-cfuncs, unnecessary with C++11."); } else if (onoff(sw, "-relative-includes", flag /*ref*/)) { m_relativeIncludes = flag; } else if (onoff(sw, "-report-unoptflat", flag /*ref*/)) { diff --git a/test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl b/test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl index 679b4369f..0ec805e0e 100755 --- a/test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl +++ b/test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl @@ -13,7 +13,7 @@ scenarios(simulator => 1); top_filename("t/t_inst_tree.v"); compile( - verilator_flags2 => ['--stats', '--norelative-cfuncs', + verilator_flags2 => ['--stats', '-Wno-DEPRECATED', '--norelative-cfuncs', "$Self->{t_dir}/t_inst_tree_inl0_pub1.vlt", $Self->wno_unopthreads_for_few_cores()] ); From 334e42b38e0b7997f72ac573ee778cdc3a567efd Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 17 Mar 2021 20:33:31 -0400 Subject: [PATCH 029/110] Cleanup REDEFMACRO to not show two separate warnings --- src/V3PreProc.cpp | 15 +++++++++------ test_regress/t/t_pp_dupdef_bad.out | 8 ++++---- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/V3PreProc.cpp b/src/V3PreProc.cpp index 2fd43fa54..87fbf38ef 100644 --- a/src/V3PreProc.cpp +++ b/src/V3PreProc.cpp @@ -335,12 +335,15 @@ void V3PreProcImp::define(FileLine* fl, const string& name, const string& value, if (!(defValue(name) == value && defParams(name) == params)) { // Duplicate defs are OK fl->v3warn(REDEFMACRO, "Redefining existing define: '" - << name << "', with different value: " << value - << (params == "" ? "" : " ") << params); - defFileline(name)->v3warn(REDEFMACRO, "Previous definition is here, with value: " - << defValue(name) - << (defParams(name).empty() ? "" : " ") - << defParams(name)); + << name << "', with different value: '" << value + << (params == "" ? "" : " ") << params << "'\n" + << fl->warnContextPrimary() << '\n' + << defFileline(name)->warnOther() + << "... Location of previous definition, with value: '" + << defValue(name) + << (defParams(name).empty() ? "" : " ") + << defParams(name) << "'\n" + << defFileline(name)->warnContextSecondary()); } undef(name); } diff --git a/test_regress/t/t_pp_dupdef_bad.out b/test_regress/t/t_pp_dupdef_bad.out index 82ffa436e..cb207f1d3 100644 --- a/test_regress/t/t_pp_dupdef_bad.out +++ b/test_regress/t/t_pp_dupdef_bad.out @@ -1,6 +1,6 @@ -%Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Redefining existing define: 'DUP', with different value: barney +%Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Redefining existing define: 'DUP', with different value: 'barney' + t/t_pp_dupdef.v:11:20: ... Location of previous definition, with value: 'fred' ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message. -%Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Previous definition is here, with value: fred -%Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Redefining existing define: 'DUPP', with different value: paramed(x,z) (x*z) -%Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Previous definition is here, with value: paramed(x) (x) +%Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Redefining existing define: 'DUPP', with different value: 'paramed(x,z) (x*z)' + t/t_pp_dupdef.v:14:33: ... Location of previous definition, with value: 'paramed(x) (x)' %Error: Exiting due to From 07de647cd7e76c169e7e45ee7c1c707bdf99b5de Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 18 Mar 2021 18:45:34 -0400 Subject: [PATCH 030/110] Tests: On first file_identical miscompare look for others --- test_regress/driver.pl | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 2796baabf..846e74930 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -716,6 +716,14 @@ sub error { $self->{errors} ||= $msg; } +sub error_keep_going { + my $self = (ref $_[0] ? shift : $Self); + my $msg = join('',@_); + # Called from tests as: error_keep_going("Reason message"[, ...]); + warn "%Warning: $self->{scenario}/$self->{name}: ".$msg."\n"; + $self->{errors_keep_going} ||= $msg; +} + sub skip { my $self = (ref $_[0] ? shift : $Self); my $msg = join('',@_); @@ -1396,7 +1404,7 @@ sub inline_checks { sub ok { my $self = (ref $_[0]? shift : $Self); $self->{ok} = $_[0] if defined $_[0]; - $self->{ok} = 0 if $self->{errors} || $self->{skips} || $self->unsupporteds; + $self->{ok} = 0 if $self->{errors} || $self->{errors_keep_going} || $self->{skips} || $self->unsupporteds; return $self->{ok}; } @@ -2143,7 +2151,7 @@ sub files_identical { for (my $l=0; $l<=$nl; ++$l) { if (($l1[$l]||"") ne ($l2[$l]||"")) { next try if $moretry; - $self->error("Line ".($l+1)." miscompares; $fn1 != $fn2"); + $self->error_keep_going("Line ".($l+1)." miscompares; $fn1 != $fn2"); warn("F1: ".($l1[$l]||"*EOF*\n") ."F2: ".($l2[$l]||"*EOF*\n")); if ($ENV{HARNESS_UPDATE_GOLDEN}) { # Update golden files with current From a159c41219f96411bb2a32bcbe72b46141db7503 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 18 Mar 2021 18:46:07 -0400 Subject: [PATCH 031/110] Fix USERINFO etc to show message with no arguments --- src/V3Width.cpp | 10 ++++++---- test_regress/t/t_assert_comp_bad.out | 22 +++++++++++----------- test_regress/t/t_assert_comp_bad.v | 8 ++++---- 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/src/V3Width.cpp b/src/V3Width.cpp index d0226f4e5..a8ad15b01 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -3938,11 +3938,13 @@ private: userIterateChildren(nodep, WidthVP(SELF, BOTH).p()); if (!m_paramsOnly) { V3Const::constifyParamsEdit(nodep->fmtp()); // fmtp may change + string text = nodep->fmtp()->text(); + if (text.empty()) text = "Elaboration system task message (IEEE 1800-2017 20.11)"; switch (nodep->displayType()) { - case AstDisplayType::DT_INFO: nodep->v3warn(USERINFO, nodep->fmtp()->text()); break; - case AstDisplayType::DT_ERROR: nodep->v3warn(USERERROR, nodep->fmtp()->text()); break; - case AstDisplayType::DT_WARNING: nodep->v3warn(USERWARN, nodep->fmtp()->text()); break; - case AstDisplayType::DT_FATAL: nodep->v3warn(USERFATAL, nodep->fmtp()->text()); break; + case AstDisplayType::DT_INFO: nodep->v3warn(USERINFO, text); break; + case AstDisplayType::DT_ERROR: nodep->v3warn(USERERROR, text); break; + case AstDisplayType::DT_WARNING: nodep->v3warn(USERWARN, text); break; + case AstDisplayType::DT_FATAL: nodep->v3warn(USERFATAL, text); break; default: UASSERT_OBJ(false, nodep, "Unexpected elaboration display type"); } VL_DO_DANGLING(nodep->unlinkFrBack()->deleteTree(), nodep); diff --git a/test_regress/t/t_assert_comp_bad.out b/test_regress/t/t_assert_comp_bad.out index 13838eddd..5cf3179a8 100644 --- a/test_regress/t/t_assert_comp_bad.out +++ b/test_regress/t/t_assert_comp_bad.out @@ -1,34 +1,34 @@ --Info: t/t_assert_comp_bad.v:10:7: +-Info: t/t_assert_comp_bad.v:10:7: Elaboration system task message (IEEE 1800-2017 20.11) : ... In instance t 10 | $info; | ^~~~~ --Info: t/t_assert_comp_bad.v:11:7: User compile-time info +-Info: t/t_assert_comp_bad.v:11:7: User elaboration-time info : ... In instance t - 11 | $info("User compile-time info"); + 11 | $info("User elaboration-time info"); | ^~~~~ -%Warning-USERWARN: t/t_assert_comp_bad.v:12:7: +%Warning-USERWARN: t/t_assert_comp_bad.v:12:7: Elaboration system task message (IEEE 1800-2017 20.11) : ... In instance t 12 | $warning; | ^~~~~~~~ ... Use "/* verilator lint_off USERWARN */" and lint_on around source to disable this message. -%Warning-USERWARN: t/t_assert_comp_bad.v:13:7: User compile-time warning +%Warning-USERWARN: t/t_assert_comp_bad.v:13:7: User elaboration-time warning : ... In instance t - 13 | $warning("User compile-time warning"); + 13 | $warning("User elaboration-time warning"); | ^~~~~~~~ %Warning-USERWARN: t/t_assert_comp_bad.v:14:7: 1 : ... In instance t 14 | $warning(1); | ^~~~~~~~ -%Warning-USERERROR: t/t_assert_comp_bad.v:15:7: +%Warning-USERERROR: t/t_assert_comp_bad.v:15:7: Elaboration system task message (IEEE 1800-2017 20.11) : ... In instance t 15 | $error; | ^~~~~~ -%Warning-USERERROR: t/t_assert_comp_bad.v:16:7: User compile-time error +%Warning-USERERROR: t/t_assert_comp_bad.v:16:7: User elaboration-time error : ... In instance t - 16 | $error("User compile-time error"); + 16 | $error("User elaboration-time error"); | ^~~~~~ -%Warning-USERFATAL: t/t_assert_comp_bad.v:17:7: +%Warning-USERFATAL: t/t_assert_comp_bad.v:17:7: User elaboration-time fatal : ... In instance t - 17 | $fatal; + 17 | $fatal(0, "User elaboration-time fatal"); | ^~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_assert_comp_bad.v b/test_regress/t/t_assert_comp_bad.v index 22434a8ff..b8bcb1bb3 100644 --- a/test_regress/t/t_assert_comp_bad.v +++ b/test_regress/t/t_assert_comp_bad.v @@ -8,13 +8,13 @@ module t (/*AUTOARG*/); if (1) begin $info; - $info("User compile-time info"); + $info("User elaboration-time info"); $warning; - $warning("User compile-time warning"); + $warning("User elaboration-time warning"); $warning(1); // Check can convert arguments to format $error; - $error("User compile-time error"); - $fatal; + $error("User elaboration-time error"); + $fatal(0, "User elaboration-time fatal"); end endmodule From 29505ef013e732579fc923c8f6cfc224d20cd9ab Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 19 Mar 2021 18:44:26 -0400 Subject: [PATCH 032/110] Support arrayed parameter functions partial (#2846) --- src/V3Const.cpp | 4 +- src/V3Simulate.h | 5 ++- test_regress/t/t_dynarray_param.pl | 21 +++++++++++ test_regress/t/t_dynarray_param.v | 54 +++++++++++++++++++++++++++ test_regress/t/t_enum_recurse_bad.out | 2 +- test_regress/t/t_param_avec.out | 5 --- test_regress/t/t_param_avec.pl | 4 +- 7 files changed, 82 insertions(+), 13 deletions(-) create mode 100755 test_regress/t/t_dynarray_param.pl create mode 100644 test_regress/t/t_dynarray_param.v delete mode 100644 test_regress/t/t_param_avec.out diff --git a/src/V3Const.cpp b/src/V3Const.cpp index a73085e37..ee97ffd50 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -2114,7 +2114,7 @@ private: VL_DO_DANGLING(replaceNum(nodep, num), nodep); did = true; } - } else if (m_params && VN_IS(valuep, InitArray) && VN_IS(nodep->backp(), Pin)) { + } else if (m_params && VN_IS(valuep, InitArray)) { // Allow parameters to pass arrays // Earlier recursion of InitArray made sure each array value is constant // This exception is fairly fragile, i.e. doesn't @@ -2156,7 +2156,7 @@ private: } } if (!did && m_required) { - nodep->v3error("Expecting expression to be constant, but variable isn't const: " + nodep->v3error("Expecting expression to be constant, but enum value isn't const: " << nodep->itemp()->prettyNameQ()); } } diff --git a/src/V3Simulate.h b/src/V3Simulate.h index 3fa35da56..02e6692cc 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -191,8 +191,9 @@ public: AstVar* portp = conIt->first; AstNode* pinp = conIt->second->exprp(); AstNodeDType* dtypep = pinp->dtypep(); - stack << "\n " << portp->prettyName() << " = " - << prettyNumber(&fetchConst(pinp)->num(), dtypep); + if (AstConst* valp = fetchConstNull(pinp)) + stack << "\n " << portp->prettyName() << " = " + << prettyNumber(&valp->num(), dtypep); } } m_whyNotOptimizable += stack.str(); diff --git a/test_regress/t/t_dynarray_param.pl b/test_regress/t/t_dynarray_param.pl new file mode 100755 index 000000000..2cb5eeaff --- /dev/null +++ b/test_regress/t/t_dynarray_param.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_dynarray_param.v b/test_regress/t/t_dynarray_param.v new file mode 100644 index 000000000..72098b871 --- /dev/null +++ b/test_regress/t/t_dynarray_param.v @@ -0,0 +1,54 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Noam Gallmann. +// SPDX-License-Identifier: CC0-1.0 + +`define stop $stop +`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0) + +module t(/*AUTOARG*/); + localparam int SIZES [3:0] = '{1,2,3,4}; + typedef int calc_sums_t [3:0]; + + localparam int SUMS_ARRAY [3:0] = calc_sums_array(SIZES, 4); + function calc_sums_t calc_sums_array(int s[3:0], int n); + int sum = 0; + for (int ii = 0; ii < n; ++ii) begin + sum = sum + s[ii]; + calc_sums_array[ii] = sum; + end + endfunction + +`ifndef VERILATOR + localparam int SUMS_DYN [3:0] = calc_sums_dyn(SIZES, 4); +`endif + function calc_sums_t calc_sums_dyn(int s[], int n); + int sum = 0; + for (int ii = 0; ii < n; ++ii) begin + sum = sum + s[ii]; + calc_sums_dyn[ii] = sum; + end + endfunction + + initial begin + `checkh(SIZES[0], 4); + `checkh(SIZES[1], 3); + `checkh(SIZES[2], 2); + `checkh(SIZES[3], 1); + + `checkh(SUMS_ARRAY[0], 4); + `checkh(SUMS_ARRAY[1], 7); + `checkh(SUMS_ARRAY[2], 9); + `checkh(SUMS_ARRAY[3], 10); + +`ifndef VERILATOR + `checkh(SUMS_DYN[0], 1); + `checkh(SUMS_DYN[1], 3); + `checkh(SUMS_DYN[2], 6); + `checkh(SUMS_DYN[3], 10); +`endif + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_enum_recurse_bad.out b/test_regress/t/t_enum_recurse_bad.out index 3cc8a55d3..edc69c63a 100644 --- a/test_regress/t/t_enum_recurse_bad.out +++ b/test_regress/t/t_enum_recurse_bad.out @@ -1,7 +1,7 @@ %Error: t/t_enum_recurse_bad.v:7:9: Recursive enum value: 'u' 7 | enum {u=u} e_t; | ^ -%Error: t/t_enum_recurse_bad.v:7:9: Expecting expression to be constant, but variable isn't const: 'u' +%Error: t/t_enum_recurse_bad.v:7:9: Expecting expression to be constant, but enum value isn't const: 'u' 7 | enum {u=u} e_t; | ^ %Error: t/t_enum_recurse_bad.v:7:9: Enum value isn't a constant diff --git a/test_regress/t/t_param_avec.out b/test_regress/t/t_param_avec.out deleted file mode 100644 index 842a71140..000000000 --- a/test_regress/t/t_param_avec.out +++ /dev/null @@ -1,5 +0,0 @@ -%Error: t/t_param_avec.v:34:43: Expecting expression to be constant, but variable isn't const: 'array' - : ... In instance t.i0 - 34 | localparam elementf = get_element(IDX, array); - | ^~~~~ -%Error: Exiting due to diff --git a/test_regress/t/t_param_avec.pl b/test_regress/t/t_param_avec.pl index b2836602c..b46d46042 100755 --- a/test_regress/t/t_param_avec.pl +++ b/test_regress/t/t_param_avec.pl @@ -11,13 +11,11 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di scenarios(simulator => 1); compile( - fails => $Self->{vlt_all}, # Verilator unsupported, bug477 - expect_filename => $Self->{golden_filename}, ); execute( check_finished => 1, - ) if !$Self->{vlt_all}; + ); ok(1); 1; From 82710a55a4339470deac9e645f78b67ee7b83c91 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 19 Mar 2021 20:58:42 -0400 Subject: [PATCH 033/110] Quieter archive (broke few commits ago) --- include/verilated.mk.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/verilated.mk.in b/include/verilated.mk.in index 51ac744d8..e1c8f91ca 100644 --- a/include/verilated.mk.in +++ b/include/verilated.mk.in @@ -210,7 +210,7 @@ endif $(info Archive $(AR) -rcs $@ $^) $(file >$@.tmp) $(foreach L, $(filter-out %.a,$^), $(file >>$@.tmp, $L)) - if test $(words $(filter %.a,$^)) -eq 0; then \ + @if test $(words $(filter %.a,$^)) -eq 0; then \ $(AR) -rcs $@ @$@.tmp; \ else \ $(RM) -rf $@.tmpdir; \ From 3fd3526d766bbead4aa024a38a6ec0e2dd9443bb Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 19 Mar 2021 21:53:08 -0400 Subject: [PATCH 034/110] Ignore _build directories. --- .gitignore | 1 + MANIFEST.SKIP | 1 + 2 files changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 8721ca5a8..2ecc92aad 100644 --- a/.gitignore +++ b/.gitignore @@ -36,4 +36,5 @@ verilator_coverage_bin* verilator.pc verilator-config.cmake verilator-config-version.cmake +**/_build/* **/obj_dir/* diff --git a/MANIFEST.SKIP b/MANIFEST.SKIP index 298886f43..f765c3326 100644 --- a/MANIFEST.SKIP +++ b/MANIFEST.SKIP @@ -19,6 +19,7 @@ .*\.1 \.codacy\.yml \.travis\.yml +/_build/ /build/ /obj_dbg/ /obj_dir/ From b6c393e9f025aae8b678610205fbfc56d9688e36 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 19 Mar 2021 22:24:00 -0400 Subject: [PATCH 035/110] Add VerilatedCovContext::forcePerInstance (#2793). --- Changes | 1 + include/verilated_cov.cpp | 10 +++++++++ include/verilated_cov.h | 2 ++ test_regress/t/t_cover_lib.pl | 1 + test_regress/t/t_cover_lib_1.out | 9 +++++--- test_regress/t/t_cover_lib_1_per_instance.out | 8 +++++++ test_regress/t/t_cover_lib_2.out | 4 ++-- test_regress/t/t_cover_lib_3.out | 4 ++-- test_regress/t/t_cover_lib_c.cpp | 22 ++++++++++++++++++- 9 files changed, 53 insertions(+), 8 deletions(-) create mode 100644 test_regress/t/t_cover_lib_1_per_instance.out diff --git a/Changes b/Changes index 5a4d10fb8..6040d6b58 100644 --- a/Changes +++ b/Changes @@ -17,6 +17,7 @@ Verilator 4.201 devel * Changed TIMESCALEMOD from error into a warning. * Verilated signals now use VlWide and VlPacked in place of C arrays. * Mark --no-relative-cfuncs as scheduled for deprecation. +* Add VerilatedCovContext::forcePerInstance (#2793). [Kevin Laeufer] * Fix class unpacked-array compile error (#2774). [Iru Cai] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] * Fix false $dumpfile warning on model save (#2834). [Yinan Xu] diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index e94291dc6..3ba9576a8 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -107,6 +107,7 @@ private: VerilatedCovImpItem* m_insertp VL_GUARDED_BY(m_mutex) = nullptr; ///< Item about to insert const char* m_insertFilenamep VL_GUARDED_BY(m_mutex) = nullptr; ///< Filename about to insert int m_insertLineno VL_GUARDED_BY(m_mutex) = 0; ///< Line number about to insert + bool m_forcePerInstance VL_GUARDED_BY(m_mutex) = false; ///< Force per_instance public: // CONSTRUCTORS @@ -245,6 +246,11 @@ private: public: // PUBLIC METHODS + void forcePerInstance(bool flag) VL_MT_SAFE_EXCLUDES(m_mutex) { + Verilated::quiesce(); + const VerilatedLockGuard lock(m_mutex); + m_forcePerInstance = flag; + } void clear() VL_MT_SAFE_EXCLUDES(m_mutex) { Verilated::quiesce(); const VerilatedLockGuard lock(m_mutex); @@ -362,6 +368,7 @@ public: std::string name; std::string hier; bool per_instance = false; + if (m_forcePerInstance) per_instance = true; for (int i = 0; i < VerilatedCovConst::MAX_KEYS; ++i) { if (itemp->m_keys[i] != VerilatedCovConst::KEY_UNDEF) { @@ -413,6 +420,9 @@ public: //============================================================================= // VerilatedCovContext +void VerilatedCovContext::forcePerInstance(bool flag) VL_MT_SAFE { + impp()->forcePerInstance(flag); +} void VerilatedCovContext::clear() VL_MT_SAFE { impp()->clear(); } void VerilatedCovContext::clearNonMatch(const char* matchp) VL_MT_SAFE { impp()->clearNonMatch(matchp); diff --git a/include/verilated_cov.h b/include/verilated_cov.h index 450b4c071..b00036d5a 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -96,6 +96,8 @@ public: // METHODS /// Return default filename static const char* defaultFilename() VL_PURE { return "coverage.dat"; } + /// Make all data per_instance, overriding point's per_instance + void forcePerInstance(bool flag) VL_MT_SAFE; /// Write all coverage data to a file void write(const char* filenamep = defaultFilename()) VL_MT_SAFE; /// Clear coverage points (and call delete on all items) diff --git a/test_regress/t/t_cover_lib.pl b/test_regress/t/t_cover_lib.pl index 9d7305ac5..f54ac29df 100755 --- a/test_regress/t/t_cover_lib.pl +++ b/test_regress/t/t_cover_lib.pl @@ -26,6 +26,7 @@ files_identical_sorted("$Self->{obj_dir}/coverage1.dat", "t/t_cover_lib_1.out"); files_identical_sorted("$Self->{obj_dir}/coverage2.dat", "t/t_cover_lib_2.out"); files_identical_sorted("$Self->{obj_dir}/coverage3.dat", "t/t_cover_lib_3.out"); files_identical_sorted("$Self->{obj_dir}/coverage4.dat", "t/t_cover_lib_4.out"); +files_identical_sorted("$Self->{obj_dir}/coverage1_per_instance.dat", "t/t_cover_lib_1_per_instance.out"); ok(1); 1; diff --git a/test_regress/t/t_cover_lib_1.out b/test_regress/t/t_cover_lib_1.out index 30cc8a765..919cea884 100644 --- a/test_regress/t/t_cover_lib_1.out +++ b/test_regress/t/t_cover_lib_1.out @@ -1,4 +1,7 @@ # SystemC::Coverage-3 -C 'f../../t/t_cover_lib_c.cppl39pagesp_user/t_cover_lib_cokept_onehmain' 100 -C 'f../../t/t_cover_lib_c.cppl40pagesp_user/t_cover_lib_cokept_twohmain' 210 -C 'f../../t/t_cover_lib_c.cppl41pagesp_user/t_cover_lib_colost_threehmain' 220 +C 'f../../t/t_cover_lib_c.cppl37pagesp_user/t_cover_lib_cP0htop.a*.pi' 500 +C 'f../../t/t_cover_lib_c.cppl37pagesp_user/t_cover_lib_cP1htop.a0.npi' 200 +C 'f../../t/t_cover_lib_c.cppl37pagesp_user/t_cover_lib_cP1htop.a1.npi' 300 +C 'f../../t/t_cover_lib_c.cppl46pagesp_user/t_cover_lib_cokept_onehmain' 100 +C 'f../../t/t_cover_lib_c.cppl47pagesp_user/t_cover_lib_cokept_twohmain' 210 +C 'f../../t/t_cover_lib_c.cppl48pagesp_user/t_cover_lib_colost_threehmain' 220 diff --git a/test_regress/t/t_cover_lib_1_per_instance.out b/test_regress/t/t_cover_lib_1_per_instance.out new file mode 100644 index 000000000..dd3dfec0d --- /dev/null +++ b/test_regress/t/t_cover_lib_1_per_instance.out @@ -0,0 +1,8 @@ +# SystemC::Coverage-3 +C 'f../../t/t_cover_lib_c.cppl37pagesp_user/t_cover_lib_cP0htop.a0.pi' 200 +C 'f../../t/t_cover_lib_c.cppl37pagesp_user/t_cover_lib_cP0htop.a1.pi' 300 +C 'f../../t/t_cover_lib_c.cppl37pagesp_user/t_cover_lib_cP1htop.a0.npi' 200 +C 'f../../t/t_cover_lib_c.cppl37pagesp_user/t_cover_lib_cP1htop.a1.npi' 300 +C 'f../../t/t_cover_lib_c.cppl46pagesp_user/t_cover_lib_cokept_onehmain' 100 +C 'f../../t/t_cover_lib_c.cppl47pagesp_user/t_cover_lib_cokept_twohmain' 210 +C 'f../../t/t_cover_lib_c.cppl48pagesp_user/t_cover_lib_colost_threehmain' 220 diff --git a/test_regress/t/t_cover_lib_2.out b/test_regress/t/t_cover_lib_2.out index a015f43e9..e9fa447e8 100644 --- a/test_regress/t/t_cover_lib_2.out +++ b/test_regress/t/t_cover_lib_2.out @@ -1,3 +1,3 @@ # SystemC::Coverage-3 -C 'f../../t/t_cover_lib_c.cppl39pagesp_user/t_cover_lib_cokept_onehmain' 100 -C 'f../../t/t_cover_lib_c.cppl40pagesp_user/t_cover_lib_cokept_twohmain' 210 +C 'f../../t/t_cover_lib_c.cppl46pagesp_user/t_cover_lib_cokept_onehmain' 100 +C 'f../../t/t_cover_lib_c.cppl47pagesp_user/t_cover_lib_cokept_twohmain' 210 diff --git a/test_regress/t/t_cover_lib_3.out b/test_regress/t/t_cover_lib_3.out index 26778b3b9..7db8b9cb0 100644 --- a/test_regress/t/t_cover_lib_3.out +++ b/test_regress/t/t_cover_lib_3.out @@ -1,3 +1,3 @@ # SystemC::Coverage-3 -C 'f../../t/t_cover_lib_c.cppl39pagesp_user/t_cover_lib_cokept_onehmain' 0 -C 'f../../t/t_cover_lib_c.cppl40pagesp_user/t_cover_lib_cokept_twohmain' 0 +C 'f../../t/t_cover_lib_c.cppl46pagesp_user/t_cover_lib_cokept_onehmain' 0 +C 'f../../t/t_cover_lib_c.cppl47pagesp_user/t_cover_lib_cokept_twohmain' 0 diff --git a/test_regress/t/t_cover_lib_c.cpp b/test_regress/t/t_cover_lib_c.cpp index 863ce000b..fc9f38206 100644 --- a/test_regress/t/t_cover_lib_c.cpp +++ b/test_regress/t/t_cover_lib_c.cpp @@ -30,9 +30,16 @@ int errors = 0; const char* name() { return "main"; } +void hier_insert(VerilatedCovContext* covContextp, vluint64_t* countp, const char* hierp, + const char* peri) { + // This needs to be a function at one line number so all of the + // line numbers for coverage are constant, otherwise instances won't combine. + VL_COVER_INSERT(covContextp, countp, "hier", hierp, "per_instance", peri); +} + int main() { vluint32_t covers[1]; - vluint64_t coverw[2]; + vluint64_t coverw[6]; VerilatedCovContext* covContextp = Verilated::defaultContextp()->coveragep(); @@ -40,13 +47,26 @@ int main() { VL_COVER_INSERT(covContextp, &coverw[0], "comment", "kept_two"); VL_COVER_INSERT(covContextp, &coverw[1], "comment", "lost_three"); + hier_insert(covContextp, &coverw[2], "top.a0.pi", "0"); + hier_insert(covContextp, &coverw[3], "top.a1.pi", "0"); + hier_insert(covContextp, &coverw[4], "top.a0.npi", "1"); + hier_insert(covContextp, &coverw[5], "top.a1.npi", "1"); + covers[0] = 100; coverw[0] = 210; coverw[1] = 220; + coverw[2] = 200; + coverw[3] = 300; + coverw[4] = 200; + coverw[5] = 300; + #ifdef T_COVER_LIB TEST_CHECK_CSTR(covContextp->defaultFilename(), "coverage.dat"); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage1.dat"); + covContextp->forcePerInstance(true); + covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage1_per_instance.dat"); + covContextp->forcePerInstance(false); covContextp->clearNonMatch("kept_"); covContextp->write(VL_STRINGIFY(TEST_OBJ_DIR) "/coverage2.dat"); covContextp->zero(); From 93eabb83b258c0f5cabbd05800acf2f06f632c26 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 20 Mar 2021 17:37:24 -0400 Subject: [PATCH 036/110] Cleanup some python warnings. No functional change. --- .gitignore | 1 + Makefile.in | 4 ++-- docs/install.rst | 2 +- nodist/code_coverage | 2 +- src/astgen | 3 ++- 5 files changed, 7 insertions(+), 5 deletions(-) diff --git a/.gitignore b/.gitignore index 2ecc92aad..7545baa1d 100644 --- a/.gitignore +++ b/.gitignore @@ -36,5 +36,6 @@ verilator_coverage_bin* verilator.pc verilator-config.cmake verilator-config-version.cmake +**/__pycache__/* **/_build/* **/obj_dir/* diff --git a/Makefile.in b/Makefile.in index de87a7a68..c3dbbb6da 100644 --- a/Makefile.in +++ b/Makefile.in @@ -508,8 +508,8 @@ PYLINT = pylint PYLINT_FLAGS = --disable=R0801 lint-py: - $(FLAKE8) $(FLAKE8_FLAGS) $(PY_PROGRAMS) - $(PYLINT) $(PYLINT_FLAGS) $(PY_PROGRAMS) + -$(FLAKE8) $(FLAKE8_FLAGS) $(PY_PROGRAMS) + -$(PYLINT) $(PYLINT_FLAGS) $(PY_PROGRAMS) format-pl-exec: -chmod a+x test_regress/t/*.pl diff --git a/docs/install.rst b/docs/install.rst index 0a47b3822..f6f7a2031 100644 --- a/docs/install.rst +++ b/docs/install.rst @@ -362,7 +362,7 @@ Some relevant files and directories in this package are as follows: :: Changes => Version history - README.rst => This document + README.rst => This document bin/verilator => Compiler wrapper invoked to Verilate code docs/ => Additional documentation examples/make_hello_c => Example GNU-make simple Verilog->C++ conversion diff --git a/nodist/code_coverage b/nodist/code_coverage index 44efa6d0f..3e70bbb36 100755 --- a/nodist/code_coverage +++ b/nodist/code_coverage @@ -47,7 +47,7 @@ def test(): # to uncovered (in G++ 9.3.0) even with all inlining turned off. # Having false negative coverage is more effort then missing negatives. # Also this seems to explode the runtime (since a lot more data). - #+ " -fkeep-inline-functions" + # + " -fkeep-inline-functions" # Otherwise static may not show as uncovered + " -fkeep-static-functions" # Exceptions can pollute the branch coverage data diff --git a/src/astgen b/src/astgen index a78973055..a5057b7a8 100755 --- a/src/astgen +++ b/src/astgen @@ -602,7 +602,8 @@ def write_type_enum(fh, typen, idx, processed, kind, indent): def write_types(filename): with open_file(filename) as fh: fh.write(" enum en : uint16_t {\n") - (final, last) = write_type_enum(fh, "Node", 0, {}, "concrete-enum", 2) + (final, ignored) = write_type_enum( # pylint: disable=W0612 + fh, "Node", 0, {}, "concrete-enum", 2) fh.write(" _ENUM_END = " + str(final) + "\n") fh.write(" };\n") From a1ab295b747a7d0a16f874f2a495c27d0deb471e Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 20 Mar 2021 17:46:00 -0400 Subject: [PATCH 037/110] Commentary: Cleanup all include/* header comments. --- include/verilated.cpp | 14 ++++++++------ include/verilated.h | 20 ++++++++++++-------- include/verilated.v | 2 -- include/verilated_config.h.in | 12 +++++++----- include/verilated_cov.cpp | 9 +++++++-- include/verilated_cov.h | 33 +++++++++++++++++++++------------ include/verilated_cov_key.h | 11 +++++++---- include/verilated_dpi.cpp | 11 +++++++---- include/verilated_dpi.h | 15 +++++++++------ include/verilated_fst_c.cpp | 9 +++++++-- include/verilated_fst_c.h | 6 ++++-- include/verilated_heavy.h | 16 ++++++++-------- include/verilated_imp.h | 9 ++++++--- include/verilated_intrinsics.h | 16 ++++++++++------ include/verilated_save.cpp | 9 +++++++-- include/verilated_save.h | 7 +++++-- include/verilated_sc.h | 25 ++++++++++++++----------- include/verilated_sym_props.h | 19 +++++++++---------- include/verilated_syms.h | 18 +++++++++--------- include/verilated_threads.cpp | 9 ++++++++- include/verilated_threads.h | 8 ++++++-- include/verilated_trace.h | 7 +++++-- include/verilated_trace_imp.cpp | 9 +++++++-- include/verilated_vcd_c.cpp | 9 +++++++-- include/verilated_vcd_c.h | 6 ++++-- include/verilated_vcd_sc.cpp | 9 +++++++-- include/verilated_vcd_sc.h | 5 ++++- include/verilated_vpi.cpp | 12 ++++++------ include/verilated_vpi.h | 12 +++++++----- include/verilatedos.h | 23 +++++++++++++++-------- 30 files changed, 233 insertions(+), 137 deletions(-) diff --git a/include/verilated.cpp b/include/verilated.cpp index 06c632e2e..47747556c 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,15 +12,15 @@ //========================================================================= /// /// \file -/// \brief Verilator: Linked against all applications using Verilated source. +/// \brief Verilated general routine implementation code /// -/// This file must be compiled and linked against all objects -/// created from Verilator. +/// This file must be compiled and linked against all Verilated objects +/// (all code created from Verilator). /// -/// Those macro/function/variable starting or ending in _ are internal, -/// however many of the other function/macros here are also internal. +/// Verilator always adds this file to the Makefile for the linker. /// -/// Code available from: https://verilator.org +/// Those macro/function/variable starting or ending in _ are internal, +/// however many of the other function/macros here are also internal. /// //========================================================================= // Internal note: diff --git a/include/verilated.h b/include/verilated.h index 49997bcbc..1e6bffc65 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,21 +12,23 @@ //************************************************************************* /// /// \file -/// \brief Verilator: Common include for all Verilated C files +/// \brief Verilated common header, include for all Verilated C files /// -/// This file is included automatically by Verilator at the top of -/// all C++ files it generates. It contains standard macros and -/// classes required by the Verilated code. +/// This file is included automatically by Verilator at the top of all C++ +/// files it generates. It contains standard macros and classes required +/// by the Verilated code. /// -/// Those macro/function/variable starting or ending in _ are internal, -/// however many of the other function/macros here are also internal. +/// User wrapper code may need to include this to get appropriate +/// structures, however they would generally just include the +/// Verilated-model's header instead (which then includes this). /// -/// Code available from: https://verilator.org +/// Those macro/function/variable starting or ending in _ are internal, +/// however many of the other function/macros here are also internal. /// //************************************************************************* #ifndef VERILATOR_VERILATED_H_ -#define VERILATOR_VERILATED_H_ ///< Header Guard +#define VERILATOR_VERILATED_H_ // clang-format off #include "verilatedos.h" diff --git a/include/verilated.v b/include/verilated.v index 85bff0940..bfd98d29a 100644 --- a/include/verilated.v +++ b/include/verilated.v @@ -2,8 +2,6 @@ // // Code available from: https://verilator.org // -//************************************************************************* -// // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License diff --git a/include/verilated_config.h.in b/include/verilated_config.h.in index 334781991..953332221 100644 --- a/include/verilated_config.h.in +++ b/include/verilated_config.h.in @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,14 +12,14 @@ //************************************************************************* /// /// \file -/// \brief Verilator: Auto version information include for all Verilated C files -/// -/// Code available from: https://verilator.org +/// \brief Verilator program version information header /// //************************************************************************* -///**** Product and Version name - +/// Verilator product name, e.g. "Verilator" // Autoconf substitutes this with the strings from AC_INIT. #define VERILATOR_PRODUCT "@PACKAGE_NAME@" + +/// Verilator version name, e.g. "1.000 2000-01-01" +// Autoconf substitutes this with the strings from AC_INIT. #define VERILATOR_VERSION "@PACKAGE_VERSION@" diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index 3ba9576a8..e8716a59e 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,12 @@ //============================================================================= /// /// \file -/// \brief Verilator coverage analysis +/// \brief Verilated coverage analysis implementation code +/// +/// This file must be compiled and linked against all Verilated objects +/// that use coverage. +/// +/// Use "verilator --coverage" to add this to the Makefile for the linker. /// //============================================================================= diff --git a/include/verilated_cov.h b/include/verilated_cov.h index b00036d5a..4b859f319 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,13 @@ //============================================================================= /// /// \file -/// \brief Coverage analysis support +/// \brief Verilated coverage analysis support header +/// +/// This must be included in user wrapper code that wants to save coverage +/// data. +/// +/// It declares the VerilatedCovContext::write() which writes the collected +/// coverage information. /// //============================================================================= @@ -29,7 +35,8 @@ class VerilatedCovImp; //============================================================================= -/// Conditionally compile coverage code +/// Conditionally compile statements only when doing coverage (when +/// VM_COVERAGE is defined) // clang-format off #ifdef VM_COVERAGE @@ -50,7 +57,8 @@ class VerilatedCovImp; /// The value may be a string, or another type which will be auto-converted to a string. /// /// Some typical keys: -/// filename File the recording occurs in. Defaults to __FILE__ +/// +/// filename File the recording occurs in. Defaults to __FILE__. /// lineno Line number the recording occurs in. Defaults to __LINE__ /// column Column number (or occurrence# for dup file/lines). Defaults to undef. /// hier Hierarchical name. Defaults to name() @@ -61,13 +69,14 @@ class VerilatedCovImp; /// thresh Threshold to consider fully covered. /// If unspecified, downstream tools will determine it. /// -/// Examples: +/// Example: /// -/// vluint32_t m_cases[10]; -/// constructor { -/// for (int i=0; i<10; ++i) { m_cases[i]=0; } -/// } -/// for (int i=0; i<10; ++i) { +/// vluint32_t m_cases[10]; // Storage for coverage data +/// constructor() { +/// // Initialize +/// for (int i = 0; i < 10; ++i) m_cases[i] = 0; +/// // Insert +/// for (int i = 0; i < 10; ++i) /// VL_COVER_INSERT(&m_cases[i], "comment", "Coverage Case", "i", cvtToNumStr(i)); /// } @@ -76,7 +85,7 @@ class VerilatedCovImp; covcontextp->_insertp("hier", name(), __VA_ARGS__)) //============================================================================= -/// Convert VL_COVER_INSERT value arguments to strings +/// Convert VL_COVER_INSERT value arguments to strings, is \internal template std::string vlCovCvtToStr(const T& t) VL_PURE { std::ostringstream os; @@ -86,7 +95,7 @@ template std::string vlCovCvtToStr(const T& t) VL_PURE { //============================================================================= // VerilatedCov -/// Verilator coverage per-context structure +/// Verilator coverage per-context structure. /// All public methods in this class are thread safe. class VerilatedCovContext VL_NOT_FINAL : public VerilatedVirtualBase { diff --git a/include/verilated_cov_key.h b/include/verilated_cov_key.h index e0dad8c61..7bf8339a9 100644 --- a/include/verilated_cov_key.h +++ b/include/verilated_cov_key.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,10 @@ //============================================================================= /// /// \file -/// \brief Coverage item keys +/// \brief Verilated coverage item keys internal header +/// +/// This file is not part of the Verilated public-facing API. +/// It is only for internal use by the Verilated library coverage routines. /// //============================================================================= @@ -57,11 +60,11 @@ VLCOVGEN_ITEM("'name':'weight', 'short':'w', 'group':0, 'default':None, 'd //============================================================================= // VerilatedCovKey -/// Verilator coverage global class. -/// This class is thread safe. +// Namespace-style static class for \internal use. class VerilatedCovKey final { public: + // Return the short key code for a given a long coverage key static std::string shortKey(const std::string& key) VL_PURE { // VLCOVGEN_SHORT_AUTO_EDIT_BEGIN if (key == "column") return VL_CIK_COLUMN; diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp index 5a9e8aa74..65579865e 100644 --- a/include/verilated_dpi.cpp +++ b/include/verilated_dpi.cpp @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2009-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,12 +12,13 @@ //========================================================================= /// /// \file -/// \brief Verilator: DPI implementation code +/// \brief Verilated DPI implementation code /// -/// This file must be compiled and linked against all objects -/// created from Verilator or called by Verilator that use the DPI. +/// This file must be compiled and linked against all Verilated objects +/// that use the DPI. /// -/// Code available from: https://verilator.org +/// Declare any DPI routine inside Verilog to add this to the Makefile for +/// the linker. /// //========================================================================= diff --git a/include/verilated_dpi.h b/include/verilated_dpi.h index cc2e27ef3..8ad748e6a 100644 --- a/include/verilated_dpi.h +++ b/include/verilated_dpi.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,18 +12,19 @@ //************************************************************************* /// /// \file -/// \brief Verilator: Common include for all Verilated C files that use DPI +/// \brief Verilated DPI header /// -/// This file is included automatically by Verilator at the top of -/// all C++ files it generates where DPI is used. It contains -/// DPI interface functions required by the Verilated code. +/// This file is included automatically by Verilator at the top of all C++ +/// files it generates where DPI is used. It contains DPI interface +/// functions required by the Verilated code. /// -/// Code available from: https://verilator.org +/// This file is not part of the Verilated public-facing API. +/// It is only for internal use. /// //************************************************************************* #ifndef VERILATOR_VERILATED_DPI_H_ -#define VERILATOR_VERILATED_DPI_H_ ///< Header Guard +#define VERILATOR_VERILATED_DPI_H_ #include "verilatedos.h" #include "verilated.h" // Also presumably included by caller diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index cfbec316d..ca7ab3495 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,12 @@ //============================================================================= /// /// \file -/// \brief C++ Tracing in FST Format +/// \brief Verilated C++ tracing in FST format implementation code +/// +/// This file must be compiled and linked against all Verilated objects +/// that use --trace-fst. +/// +/// Use "verilator --trace-fst" to add this to the Makefile for the linker. /// //============================================================================= diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 232905eea..fd43f365b 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,9 @@ //============================================================================= /// /// \file -/// \brief C++ Tracing in FST Format +/// \brief Verilated tracing in FST format header +/// +/// User wrapper code should use this header when creating FST traces. /// //============================================================================= // SPDIFF_OFF diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index 19df8b552..83faf9f36 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2010-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,19 +12,17 @@ //************************************************************************* /// /// \file -/// \brief Verilator: String include for all Verilated C files +/// \brief Verilated string and data-type header /// -/// This file is included automatically by Verilator at the top of -/// all C++ files it generates. It is used when strings or other -/// heavyweight types are required; these contents are not part of -/// verilated.h to save compile time when such types aren't used. -/// -/// Code available from: https://verilator.org +/// This file is included automatically by Verilator at the top of +/// all C++ files it generates. It is used when strings or other +/// heavyweight types are required; these contents are not part of +/// verilated.h to save compile time when such types aren't used. /// //************************************************************************* #ifndef VERILATOR_VERILATED_HEAVY_H_ -#define VERILATOR_VERILATED_HEAVY_H_ ///< Header Guard +#define VERILATOR_VERILATED_HEAVY_H_ #include "verilated.h" diff --git a/include/verilated_imp.h b/include/verilated_imp.h index 62a5671b8..7a37b1017 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2009-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,14 +12,15 @@ //========================================================================= /// /// \file -/// \brief Verilator: Implementation Header, only for verilated.cpp internals. +/// \brief Verilated implementation Header, only for verilated.cpp internals. /// -/// Code available from: https://verilator.org +/// This file is not part of the Verilated public-facing API. +/// It is only for internal use by the Verilated libraries. /// //========================================================================= #ifndef VERILATOR_VERILATED_IMP_H_ -#define VERILATOR_VERILATED_IMP_H_ ///< Header Guard +#define VERILATOR_VERILATED_IMP_H_ // clang-format off #if !defined(VERILATOR_VERILATED_CPP_) && !defined(VERILATOR_VERILATED_DPI_CPP_) \ diff --git a/include/verilated_intrinsics.h b/include/verilated_intrinsics.h index bba2a324c..6c4dd0e70 100644 --- a/include/verilated_intrinsics.h +++ b/include/verilated_intrinsics.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,17 +12,19 @@ //************************************************************************* /// /// \file -/// \brief Verilator: Common include for target specific intrinsics. +/// \brief Verilator common target specific intrinsics header /// -/// Code using machine specific intrinsics for optimization should -/// include this header rather than directly including he target -/// specific headers. We provide macros to check for availability -/// of instruction sets, and a common mechanism to disable them. +/// This file is not part of the Verilated public-facing API. +/// +/// It is only for internal use; code using machine specific intrinsics for +/// optimization should include this header rather than directly including +/// he target specific headers. We provide macros to check for availability +/// of instruction sets, and a common mechanism to disable them. /// //************************************************************************* #ifndef VERILATOR_VERILATED_INTRINSICS_H_ -#define VERILATOR_VERILATED_INTRINSICS_H_ ///< Header Guard +#define VERILATOR_VERILATED_INTRINSICS_H_ // clang-format off diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp index ed71dc4b9..67f8f3a7d 100644 --- a/include/verilated_save.cpp +++ b/include/verilated_save.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,12 @@ //============================================================================= /// /// \file -/// \brief C++ Tracing in VCD Format +/// \brief Verilated save/restore implementation code +/// +/// This file must be compiled and linked against all Verilated objects +/// that use --savable. +/// +/// Use "verilator --savable" to add this to the Makefile for the linker. /// //============================================================================= diff --git a/include/verilated_save.h b/include/verilated_save.h index b710308da..23595f377 100644 --- a/include/verilated_save.h +++ b/include/verilated_save.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2000-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,10 @@ //============================================================================= /// /// \file -/// \brief Save-restore serialization of verilated modules +/// \brief Verilated save-restore serialization header +/// +/// This must be included in user wrapper code that wants to use +/// save/restore. /// //============================================================================= diff --git a/include/verilated_sc.h b/include/verilated_sc.h index ed88081f3..649b388ed 100644 --- a/include/verilated_sc.h +++ b/include/verilated_sc.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2009-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,30 +12,31 @@ //************************************************************************* /// /// \file -/// \brief Verilator: Common include for all Verilated SystemC files +/// \brief Verilated SystemC header for all Verilated SystemC files /// -/// This file is included automatically by Verilator at the top of -/// all SystemC files it generates. +/// This file is included automatically by Verilator at the top of all +/// SystemC files it generates. It contains functions Verilated code uses +/// internally to connect the Verilated model into SystemC. /// -/// Code available from: https://verilator.org +/// User wrapper code is not required to include nor use anything in this +/// header, but may prefer to include it in place of "verilated.h" when +/// using Verilator with SystemC. /// //************************************************************************* #ifndef VERILATOR_VERILATED_SC_H_ -#define VERILATOR_VERILATED_SC_H_ ///< Header Guard +#define VERILATOR_VERILATED_SC_H_ #include "verilatedos.h" #include "systemc.h" //============================================================================= -// VL_SC_BV_DATAP -// We want to get a pointer to m_data in the sc_bv_base class, -// but it is protected. So make an exposing class, then use -// cast magic to get at it. Saves patching get_datap in SystemC. -// This class is thread safe (though most of SystemC is not). - +// For \internal use, get a pointer to m_data in the sc_bv_base class, +// getting around that it is protected. So make an exposing class, then +// use cast magic to get at it. Saves patching get_datap in SystemC. #define VL_SC_BV_DATAP(bv) (VlScBvExposer::sp_datap(bv)) +// This class is thread safe (though most of SystemC is not). class VlScBvExposer final : public sc_bv_base { public: static const vluint32_t* sp_datap(const sc_bv_base& base) VL_MT_SAFE { diff --git a/include/verilated_sym_props.h b/include/verilated_sym_props.h index feb3ea94e..c1d896731 100644 --- a/include/verilated_sym_props.h +++ b/include/verilated_sym_props.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,22 +12,19 @@ //************************************************************************* /// /// \file -/// \brief Verilator: Include to provide information about symbol inspection +/// \brief Verilated symbol inspection header /// -/// This file is for inclusion by internal files that need to inspect -/// specific symbols. +/// This file is for inclusion by internal files that need to inspect +/// specific symbols. /// -/// User routines wanting to inspect the symbol table should use -/// verilated_syms.h instead. -/// -/// These classes are thread safe, and read only. -/// -/// Code available from: https://verilator.org +/// User wrapper code wanting to inspect the symbol table should use +/// verilated_syms.h instead. /// //************************************************************************* +// These classes are thread safe, and read only. #ifndef VERILATOR_VERILATED_SYM_PROPS_H_ -#define VERILATOR_VERILATED_SYM_PROPS_H_ ///< Header Guard +#define VERILATOR_VERILATED_SYM_PROPS_H_ #include "verilatedos.h" diff --git a/include/verilated_syms.h b/include/verilated_syms.h index 72f294c45..71f01ecea 100644 --- a/include/verilated_syms.h +++ b/include/verilated_syms.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,21 +12,19 @@ //************************************************************************* /// /// \file -/// \brief Verilator: Include to allow symbol inspection +/// \brief Verilated symbol inspection header /// -/// This file is for inclusion by files that need to inspect the symbol -/// table. It is not included in verilated.h (instead see -/// verilated_sym_props.h) as it requires some heavyweight C++ classes. +/// This file is for inclusion by user wrapper code that needs to inspect +/// the symbol table. It is not included in verilated.h (instead see +/// verilated_sym_props.h) as it requires some heavyweight C++ classes. /// -/// These classes are thread safe and read only. It is constructed only -/// when a model is built (from the main thread). -/// -/// Code available from: https://verilator.org +/// These classes are thread safe and read only. It is constructed only +/// when a model is built (from the main thread). /// //************************************************************************* #ifndef VERILATOR_VERILATED_SYMS_H_ -#define VERILATOR_VERILATED_SYMS_H_ ///< Header Guard +#define VERILATOR_VERILATED_SYMS_H_ #include "verilatedos.h" #include "verilated_heavy.h" diff --git a/include/verilated_threads.cpp b/include/verilated_threads.cpp index 6eb241fac..aabad76c8 100644 --- a/include/verilated_threads.cpp +++ b/include/verilated_threads.cpp @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // +// Code available from: https://verilator.org +// // Copyright 2012-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,7 +12,12 @@ //============================================================================= /// /// \file -/// \brief Thread pool for verilated modules +/// \brief Verilated thread pool implementation code +/// +/// This file must be compiled and linked against all Verilated objects +/// that use --threads. +/// +/// Use "verilator --threads" to add this to the Makefile for the linker. /// //============================================================================= diff --git a/include/verilated_threads.h b/include/verilated_threads.h index 2231dded9..433d28f58 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2012-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,11 @@ //============================================================================= /// /// \file -/// \brief Thread pool and profiling for Verilated modules +/// \brief Verilated thread pool and profiling header +/// +/// This file is not part of the Verilated public-facing API. +/// It is only for internal use by Verilated library multithreaded +/// routines. /// //============================================================================= diff --git a/include/verilated_trace.h b/include/verilated_trace.h index 56d6373ca..3d0ccce3b 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,10 @@ //============================================================================= /// /// \file -/// \brief Internal tracing functionality common to all formats +/// \brief Verilated internal common-tracing header +/// +/// This file is not part of the Verilated public-facing API. +/// It is only for internal use by Verilated tracing routines. /// //============================================================================= diff --git a/include/verilated_trace_imp.cpp b/include/verilated_trace_imp.cpp index 5ed1f3d88..71d4f5f30 100644 --- a/include/verilated_trace_imp.cpp +++ b/include/verilated_trace_imp.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,12 @@ //============================================================================= /// /// \file -/// \brief Implementation of tracing functionality common to all trace formats +/// \brief Verilated common-format tracing implementation code +/// +/// This file must be compiled and linked against all Verilated objects +/// that use --trace. +/// +/// Use "verilator --trace" to add this to the Makefile for the linker. /// //============================================================================= diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index 7fc6bd4a3..e1e3eb5c7 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,12 @@ //============================================================================= /// /// \file -/// \brief C++ Tracing in VCD Format +/// \brief Verilated C++ tracing in VCD format implementation code +/// +/// This file must be compiled and linked against all Verilated objects +/// that use --trace. +/// +/// Use "verilator --trace" to add this to the Makefile for the linker. /// //============================================================================= diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 02431c9a0..74efa39ca 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,9 @@ //============================================================================= /// /// \file -/// \brief C++ Tracing in VCD Format +/// \brief Verilated tracing in VCD format header +/// +/// User wrapper code should use this header when creating VCD traces. /// //============================================================================= // SPDIFF_OFF diff --git a/include/verilated_vcd_sc.cpp b/include/verilated_vcd_sc.cpp index 215139022..ac0dc52c7 100644 --- a/include/verilated_vcd_sc.cpp +++ b/include/verilated_vcd_sc.cpp @@ -1,7 +1,7 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //============================================================================= // -// THIS MODULE IS PUBLICLY LICENSED +// Code available from: https://verilator.org // // Copyright 2001-2021 by Wilson Snyder. This program is free software; you // can redistribute it and/or modify it under the terms of either the GNU @@ -12,7 +12,12 @@ //============================================================================= /// /// \file -/// \brief Verilator tracing in VCD Format +/// \brief Verilated tracing in VCD Format implementation code +/// +/// This file must be compiled and linked against all Verilated objects +/// that use --trace. +/// +/// Use "verilator --trace" to add this to the Makefile for the linker. /// //============================================================================= diff --git a/include/verilated_vcd_sc.h b/include/verilated_vcd_sc.h index 2c7fe4cc2..bfe1bd1fa 100644 --- a/include/verilated_vcd_sc.h +++ b/include/verilated_vcd_sc.h @@ -10,7 +10,10 @@ //============================================================================= /// /// \file -/// \brief Verilator tracing in VCD format +/// \brief Verilated tracing in VCD format for SystemC header +/// +/// User wrapper code should use this header when creating VCD SystemC +/// traces. /// /// This class is not threadsafe, as the SystemC kernel is not threadsafe. /// diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index f788dabf3..5089ad5e4 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2009-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,14 +12,12 @@ //========================================================================= /// /// \file -/// \brief Verilator: VPI implementation code +/// \brief Verilated VPI implementation code /// -/// This file must be compiled and linked against all objects -/// created from Verilator or called by Verilator that use the VPI. +/// This file must be compiled and linked against all Verilated objects +/// that use the VPI. /// -/// Use "verilator --vpi" to add this to the Makefile for the linker. -/// -/// Code available from: https://verilator.org +/// Use "verilator --vpi" to add this to the Makefile for the linker. /// //========================================================================= diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h index 2e2d125a5..58ca002bb 100644 --- a/include/verilated_vpi.h +++ b/include/verilated_vpi.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2009-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,17 +12,17 @@ //========================================================================= /// /// \file -/// \brief Verilator: VPI implementation code +/// \brief Verilated VPI header /// -/// This file must be compiled and linked against all objects -/// created from Verilator or called by Verilator that use the VPI. +/// This file contains routines related to using VPI with Verilated models. /// -/// Code available from: https://verilator.org +/// User wrapper code may need to include this if controlling Verilated +/// models that use ths VPI. /// //========================================================================= #ifndef VERILATOR_VERILATED_VPI_H_ -#define VERILATOR_VERILATED_VPI_H_ ///< Header Guard +#define VERILATOR_VERILATED_VPI_H_ #include "verilatedos.h" #include "verilated.h" diff --git a/include/verilatedos.h b/include/verilatedos.h index c8d6a9dc3..503fedb45 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -1,6 +1,8 @@ // -*- mode: C++; c-file-style: "cc-mode" -*- //************************************************************************* // +// Code available from: https://verilator.org +// // Copyright 2003-2021 by Wilson Snyder. This program is free software; you can // redistribute it and/or modify it under the terms of either the GNU // Lesser General Public License Version 3 or the Perl Artistic License @@ -10,20 +12,25 @@ //************************************************************************* /// /// \file -/// \brief Verilator: Common include for OS portability (verilated & verilator) +/// \brief Verilated/Verilator common header for OS portability /// -/// This header is used by both the Verilator source code (run on the -/// build and host system), and the Verilated output (run on the target -/// system). Code needed by only the host system goes into -/// config_build.h.in, code needed by Verilated code only goes into -/// verilated.h, and code needed by both goes here (verilatedos.h). +/// This header is included by user wrappers and defines the Verilated +/// public-facing API. /// -/// Code available from: https://verilator.org +/// User wrapper code does not generally need to include this, instead +/// include verilated.h. +/// +/// This header is used by both the Verilator source code (run on the build +/// and host system), and the Verilated output (run on the target system). +/// +/// Configuration code needed by only the host system is in +/// config_build.h.in, code needed by Verilated code only is in +/// verilated.h, and code needed by both is here (verilatedos.h). /// //************************************************************************* #ifndef VERILATOR_VERILATEDOS_H_ -#define VERILATOR_VERILATEDOS_H_ ///< Header Guard +#define VERILATOR_VERILATEDOS_H_ // Current clang-format versions botch #ifdef inclusion, so // clang-format off From 2e158d88c106825d43eb1717799e02385bd5caea Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 20 Mar 2021 21:11:53 -0400 Subject: [PATCH 038/110] Commentary. Remove dox comments from private members, --- include/verilated.cpp | 2 +- include/verilated.h | 92 ++++++++++++++++++++--------------- include/verilated_cov.cpp | 48 +++++++++--------- include/verilated_cov.h | 20 +++++--- include/verilated_dpi.cpp | 21 ++++---- include/verilated_fst_c.h | 6 +-- include/verilated_imp.h | 28 +++++------ include/verilated_save.h | 81 ++++++++++++++++++++++-------- include/verilated_sym_props.h | 22 ++++----- include/verilated_threads.h | 2 +- include/verilated_trace.h | 26 +++++----- include/verilated_vcd_c.cpp | 4 +- include/verilated_vcd_c.h | 34 ++++++------- include/verilated_vpi.cpp | 13 +++-- include/verilated_vpi.h | 14 +++--- include/verilatedos.h | 50 +++++++++++-------- 16 files changed, 268 insertions(+), 195 deletions(-) diff --git a/include/verilated.cpp b/include/verilated.cpp index 47747556c..c7cfceecf 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -67,7 +67,7 @@ #endif // clang-format on -/// Max static char array for VL_VALUE_STRING +// Max characters in static char string for VL_VALUE_STRING constexpr unsigned VL_VALUE_STRING_MAX_WIDTH = 8192; //=========================================================================== diff --git a/include/verilated.h b/include/verilated.h index 1e6bffc65..749d1dcbe 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -134,7 +134,7 @@ enum VerilatedVarFlags { //========================================================================= // Mutex and threading support -/// Return current thread ID (or 0), not super fast, cache if needed +// Return current thread ID (or 0), not super fast, cache if needed extern vluint32_t VL_THREAD_ID() VL_MT_SAFE; #if VL_THREADED @@ -253,7 +253,7 @@ class VerilatedModule VL_NOT_FINAL { VL_UNCOPYABLE(VerilatedModule); private: - const char* m_namep; ///< Module name + const char* m_namep; // Module name public: explicit VerilatedModule(const char* namep); ///< Create module with given hierarchy name ~VerilatedModule(); @@ -580,15 +580,15 @@ public: }; // Type of a scope, currently module is only interesting private: // Fastpath: - VerilatedSyms* m_symsp = nullptr; ///< Symbol table - void** m_callbacksp = nullptr; ///< Callback table pointer (Fastpath) - int m_funcnumMax = 0; ///< Maxium function number stored (Fastpath) + VerilatedSyms* m_symsp = nullptr; // Symbol table + void** m_callbacksp = nullptr; // Callback table pointer (Fastpath) + int m_funcnumMax = 0; // Maxium function number stored (Fastpath) // 4 bytes padding (on -m64), for rent. - VerilatedVarNameMap* m_varsp = nullptr; ///< Variable map - const char* m_namep = nullptr; ///< Scope name (Slowpath) - const char* m_identifierp = nullptr; ///< Identifier of scope (with escapes removed) - vlsint8_t m_timeunit = 0; ///< Timeunit in negative power-of-10 - Type m_type = SCOPE_OTHER; ///< Type of the scope + VerilatedVarNameMap* m_varsp = nullptr; // Variable map + const char* m_namep = nullptr; // Scope name (Slowpath) + const char* m_identifierp = nullptr; // Identifier of scope (with escapes removed) + vlsint8_t m_timeunit = 0; // Timeunit in negative power-of-10 + Type m_type = SCOPE_OTHER; // Type of the scope public: // But internals only - called from VerilatedModule's VerilatedScope() = default; @@ -639,9 +639,9 @@ class Verilated final { // Internal note: Globals may multi-construct, see verilated.cpp top. // Debug is reloaded from on command-line settings, so do not need to persist - static int s_debug; ///< See accessors... only when VL_DEBUG set + static int s_debug; // See accessors... only when VL_DEBUG set - static VerilatedContext* s_lastContextp; ///< Last context constructed/attached + static VerilatedContext* s_lastContextp; // Last context constructed/attached // Not covered by mutex, as per-thread static VL_THREAD_LOCAL struct ThreadLocal { @@ -655,9 +655,9 @@ class Verilated final { // Messages maybe pending on thread, needs end-of-eval calls vluint32_t t_endOfEvalReqd = 0; #endif - const VerilatedScope* t_dpiScopep = nullptr; ///< DPI context scope - const char* t_dpiFilename = nullptr; ///< DPI context filename - int t_dpiLineno = 0; ///< DPI context line number + const VerilatedScope* t_dpiScopep = nullptr; // DPI context scope + const char* t_dpiFilename = nullptr; // DPI context filename + int t_dpiLineno = 0; // DPI context line number ThreadLocal() = default; ~ThreadLocal() = default; @@ -715,11 +715,13 @@ public: #ifndef VL_NO_LEGACY /// Call VerilatedContext::assertOn using current thread's VerilatedContext static void assertOn(bool flag) VL_MT_SAFE { Verilated::threadContextp()->assertOn(flag); } + /// Return VerilatedContext::assertOn() using current thread's VerilatedContext static bool assertOn() VL_MT_SAFE { return Verilated::threadContextp()->assertOn(); } /// Call VerilatedContext::calcUnusedSigs using current thread's VerilatedContext static void calcUnusedSigs(bool flag) VL_MT_SAFE { Verilated::threadContextp()->calcUnusedSigs(flag); } + /// Return VerilatedContext::calcUnusedSigs using current thread's VerilatedContext static bool calcUnusedSigs() VL_MT_SAFE { return Verilated::threadContextp()->calcUnusedSigs(); } @@ -730,43 +732,55 @@ public: static void commandArgs(int argc, char** argv) VL_MT_SAFE { commandArgs(argc, const_cast(argv)); } + /// Call VerilatedContext::commandArgsAdd using current thread's VerilatedContext static void commandArgsAdd(int argc, const char** argv) { Verilated::threadContextp()->commandArgsAdd(argc, argv); } + /// Return VerilatedContext::commandArgsPlusMatch using current thread's VerilatedContext static const char* commandArgsPlusMatch(const char* prefixp) VL_MT_SAFE { return Verilated::threadContextp()->commandArgsPlusMatch(prefixp); } /// Call VerilatedContext::errorLimit using current thread's VerilatedContext static void errorLimit(int val) VL_MT_SAFE { Verilated::threadContextp()->errorLimit(val); } + /// Return VerilatedContext::errorLimit using current thread's VerilatedContext static int errorLimit() VL_MT_SAFE { return Verilated::threadContextp()->errorLimit(); } /// Call VerilatedContext::fatalOnError using current thread's VerilatedContext static void fatalOnError(bool flag) VL_MT_SAFE { Verilated::threadContextp()->fatalOnError(flag); } + /// Return VerilatedContext::fatalOnError using current thread's VerilatedContext static bool fatalOnError() VL_MT_SAFE { return Verilated::threadContextp()->fatalOnError(); } /// Call VerilatedContext::fatalOnVpiError using current thread's VerilatedContext static void fatalOnVpiError(bool flag) VL_MT_SAFE { Verilated::threadContextp()->fatalOnVpiError(flag); } + /// Return VerilatedContext::fatalOnVpiError using current thread's VerilatedContext static bool fatalOnVpiError() VL_MT_SAFE { return Verilated::threadContextp()->fatalOnVpiError(); } /// Call VerilatedContext::gotError using current thread's VerilatedContext static void gotError(bool flag) VL_MT_SAFE { Verilated::threadContextp()->gotError(flag); } + /// Return VerilatedContext::gotError using current thread's VerilatedContext static bool gotError() VL_MT_SAFE { return Verilated::threadContextp()->gotError(); } /// Call VerilatedContext::gotFinish using current thread's VerilatedContext static void gotFinish(bool flag) VL_MT_SAFE { Verilated::threadContextp()->gotFinish(flag); } + /// Return VerilatedContext::gotFinish using current thread's VerilatedContext static bool gotFinish() VL_MT_SAFE { return Verilated::threadContextp()->gotFinish(); } /// Call VerilatedContext::randReset using current thread's VerilatedContext static void randReset(int val) VL_MT_SAFE { Verilated::threadContextp()->randReset(val); } + /// Return VerilatedContext::randReset using current thread's VerilatedContext static int randReset() VL_MT_SAFE { return Verilated::threadContextp()->randReset(); } /// Call VerilatedContext::randSeed using current thread's VerilatedContext static void randSeed(int val) VL_MT_SAFE { Verilated::threadContextp()->randSeed(val); } + /// Return VerilatedContext::randSeed using current thread's VerilatedContext static int randSeed() VL_MT_SAFE { return Verilated::threadContextp()->randSeed(); } /// Call VerilatedContext::time using current thread's VerilatedContext static void time(vluint64_t val) VL_MT_SAFE { Verilated::threadContextp()->time(val); } + /// Return VerilatedContext::time using current thread's VerilatedContext static vluint64_t time() VL_MT_SAFE { return Verilated::threadContextp()->time(); } + /// Call VerilatedContext::timeInc using current thread's VerilatedContext static void timeInc(vluint64_t add) VL_MT_UNSAFE { Verilated::threadContextp()->timeInc(add); } + // Deprecated static int timeunit() VL_MT_SAFE { return Verilated::threadContextp()->timeunit(); } static int timeprecision() VL_MT_SAFE { return Verilated::threadContextp()->timeprecision(); } /// Call VerilatedContext::tracesEverOn using current thread's VerilatedContext @@ -775,7 +789,8 @@ public: } #endif - typedef void (*VoidPCb)(void*); // Callback type for below + /// Callback typedef for addFlushCb, addExitCb + using VoidPCb = void (*)(void*); /// Add callback to run on global flush static void addFlushCb(VoidPCb cb, void* datap) VL_MT_SAFE; /// Remove callback to run on global flush @@ -921,7 +936,7 @@ extern vluint64_t vl_rand64() VL_MT_SAFE; inline IData VL_RANDOM_I(int obits) VL_MT_SAFE { return vl_rand64() & VL_MASK_I(obits); } inline QData VL_RANDOM_Q(int obits) VL_MT_SAFE { return vl_rand64() & VL_MASK_Q(obits); } #ifndef VL_NO_LEGACY -extern WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp); ///< Randomize a signal +extern WDataOutP VL_RANDOM_W(int obits, WDataOutP outwp); #endif extern IData VL_RANDOM_SEEDED_II(int obits, IData seed) VL_MT_SAFE; inline IData VL_URANDOM_RANGE_I(IData hi, IData lo) { @@ -934,10 +949,13 @@ inline IData VL_URANDOM_RANGE_I(IData hi, IData lo) { } } -/// Init time only, so slow is fine -extern IData VL_RAND_RESET_I(int obits); ///< Random reset a signal -extern QData VL_RAND_RESET_Q(int obits); ///< Random reset a signal -extern WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp); ///< Random reset a signal +// These are init time only, so slow is fine +/// Random reset a signal of given width +extern IData VL_RAND_RESET_I(int obits); +/// Random reset a signal of given width +extern QData VL_RAND_RESET_Q(int obits); +/// Random reset a signal of given width +extern WDataOutP VL_RAND_RESET_W(int obits, WDataOutP outwp); /// Zero reset a signal (slow - else use VL_ZERO_W) extern WDataOutP VL_ZERO_RESET_W(int obits, WDataOutP outwp); @@ -953,11 +971,9 @@ inline QData VL_RDTSC_Q() { extern void VL_PRINTTIMESCALE(const char* namep, const char* timeunitp, const VerilatedContext* contextp) VL_MT_SAFE; -/// Math extern WDataOutP _vl_moddiv_w(int lbits, WDataOutP owp, WDataInP lwp, WDataInP rwp, bool is_modulus); -/// File I/O extern IData VL_FGETS_IXI(int obits, void* destp, IData fpi); extern void VL_FFLUSH_I(IData fdi); @@ -1019,31 +1035,31 @@ extern const char* vl_mc_scan_plusargs(const char* prefixp); // PLIish | (static_cast((lwp)[1]) << (static_cast(VL_EDATASIZE)))) #define VL_SET_QII(ld, rd) ((static_cast(ld) << 32ULL) | static_cast(rd)) -/// Return FILE* from IData +// Return FILE* from IData extern FILE* VL_CVT_I_FP(IData lhs) VL_MT_SAFE; // clang-format off // Use a union to avoid cast-to-different-size warnings -/// Return void* from QData +// Return void* from QData static inline void* VL_CVT_Q_VP(QData lhs) VL_PURE { union { void* fp; QData q; } u; u.q = lhs; return u.fp; } -/// Return QData from const void* +// Return QData from const void* static inline QData VL_CVT_VP_Q(const void* fp) VL_PURE { union { const void* fp; QData q; } u; u.q = 0; u.fp = fp; return u.q; } -/// Return double from QData (bits, not numerically) +// Return double from QData (bits, not numerically) static inline double VL_CVT_D_Q(QData lhs) VL_PURE { union { double d; QData q; } u; u.q = lhs; return u.d; } -/// Return QData from double (bits, not numerically) +// Return QData from double (bits, not numerically) static inline QData VL_CVT_Q_D(double lhs) VL_PURE { union { double d; QData q; } u; u.d = lhs; @@ -1051,7 +1067,7 @@ static inline QData VL_CVT_Q_D(double lhs) VL_PURE { } // clang-format on -/// Return double from lhs (numeric) unsigned +// Return double from lhs (numeric) unsigned double VL_ITOR_D_W(int lbits, WDataInP lwp) VL_PURE; static inline double VL_ITOR_D_I(int, IData lhs) VL_PURE { return static_cast(static_cast(lhs)); @@ -1059,7 +1075,7 @@ static inline double VL_ITOR_D_I(int, IData lhs) VL_PURE { static inline double VL_ITOR_D_Q(int, QData lhs) VL_PURE { return static_cast(static_cast(lhs)); } -/// Return double from lhs (numeric) signed +// Return double from lhs (numeric) signed double VL_ISTOR_D_W(int lbits, WDataInP lwp) VL_PURE; static inline double VL_ISTOR_D_I(int lbits, IData lhs) VL_PURE { if (lbits == 32) return static_cast(static_cast(lhs)); @@ -1073,7 +1089,7 @@ static inline double VL_ISTOR_D_Q(int lbits, QData lhs) VL_PURE { VL_SET_WQ(lwp, lhs); return VL_ISTOR_D_W(lbits, lwp); } -/// Return QData from double (numeric) +// Return QData from double (numeric) static inline IData VL_RTOI_I_D(double lhs) VL_PURE { return static_cast(VL_TRUNC(lhs)); } @@ -1162,24 +1178,24 @@ inline vluint64_t VerilatedContext::time() const VL_MT_SAFE { #define VL_TIME_Q() (Verilated::threadContextp()->time()) #define VL_TIME_D() (static_cast(VL_TIME_Q())) -/// Time scaled from 1-per-precision into a module's time units ("Unit"-ed, not "United") +// Time scaled from 1-per-precision into a module's time units ("Unit"-ed, not "United") // Optimized assuming scale is always constant. // Can't use multiply in Q flavor, as might lose precision #define VL_TIME_UNITED_Q(scale) (VL_TIME_Q() / static_cast(scale)) #define VL_TIME_UNITED_D(scale) (VL_TIME_D() / static_cast(scale)) -/// Time imported from units to time precision +// Return time precision as multiplier of time units double vl_time_multiplier(int scale) VL_PURE; -/// Evaluate expression if debug enabled +/// Evaluate statement if debug enabled #ifdef VL_DEBUG -# define VL_DEBUG_IF(text) \ +# define VL_DEBUG_IF(stmt) \ do { \ - if (VL_UNLIKELY(Verilated::debug())) {text} \ + if (VL_UNLIKELY(Verilated::debug())) {stmt} \ } while (false) #else -// We intentionally do not compile the text to improve compile speed -# define VL_DEBUG_IF(text) do {} while (false) +// We intentionally do not compile the stmt to improve compile speed +# define VL_DEBUG_IF(stmt) do {} while (false) #endif // clang-format on diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index e8716a59e..9d52259e1 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -36,19 +36,19 @@ struct VerilatedCovConst VL_NOT_FINAL { // TYPES - enum { MAX_KEYS = 33 }; /// Maximum user arguments + filename+lineno - enum { KEY_UNDEF = 0 }; /// Magic key # for unspecified values + enum { MAX_KEYS = 33 }; // Maximum user arguments + filename+lineno + enum { KEY_UNDEF = 0 }; // Magic key # for unspecified values }; //============================================================================= // VerilatedCovImpItem -/// Implementation class for a VerilatedCov item +// Implementation class for a VerilatedCov item class VerilatedCovImpItem VL_NOT_FINAL { public: // But only local to this file // MEMBERS - int m_keys[VerilatedCovConst::MAX_KEYS]; ///< Key - int m_vals[VerilatedCovConst::MAX_KEYS]; ///< Value for specified key + int m_keys[VerilatedCovConst::MAX_KEYS]; // Key + int m_vals[VerilatedCovConst::MAX_KEYS]; // Value for specified key // CONSTRUCTORS // Derived classes should call zero() in their constructor VerilatedCovImpItem() { @@ -63,15 +63,15 @@ public: // But only local to this file }; //============================================================================= -/// VerilatedCoverItem templated for a specific class -/// Creates a new coverage item for the specified type. -/// This isn't in the header file for auto-magic conversion because it -/// inlines to too much code and makes compilation too slow. +// VerilatedCoverItem templated for a specific class +// Creates a new coverage item for the specified type. +// This isn't in the header file for auto-magic conversion because it +// inlines to too much code and makes compilation too slow. template class VerilatedCoverItemSpec final : public VerilatedCovImpItem { private: // MEMBERS - T* m_countp; ///< Count value + T* m_countp; // Count value public: // METHODS // cppcheck-suppress truncLongCastReturn @@ -88,11 +88,11 @@ public: //============================================================================= // VerilatedCovImp -/// -/// Implementation class for VerilatedCovContext. See that class for -/// public method information. All value and keys are indexed into a -/// unique number. Thus we can greatly reduce the storage requirements for -/// otherwise identical keys. +// +// Implementation class for VerilatedCovContext. See that class for +// public method information. All value and keys are indexed into a +// unique number. Thus we can greatly reduce the storage requirements for +// otherwise identical keys. class VerilatedCovImp final : public VerilatedCovContext { private: @@ -102,17 +102,17 @@ private: using ItemList = std::deque; // MEMBERS - VerilatedMutex m_mutex; ///< Protects all members - ValueIndexMap m_valueIndexes VL_GUARDED_BY(m_mutex); ///< Unique arbitrary value for values - IndexValueMap m_indexValues VL_GUARDED_BY(m_mutex); ///< Unique arbitrary value for keys - ItemList m_items VL_GUARDED_BY(m_mutex); ///< List of all items + VerilatedMutex m_mutex; // Protects all members + ValueIndexMap m_valueIndexes VL_GUARDED_BY(m_mutex); // Unique arbitrary value for values + IndexValueMap m_indexValues VL_GUARDED_BY(m_mutex); // Unique arbitrary value for keys + ItemList m_items VL_GUARDED_BY(m_mutex); // List of all items int m_nextIndex VL_GUARDED_BY(m_mutex) - = (VerilatedCovConst::KEY_UNDEF + 1); ///< Next insert value + = (VerilatedCovConst::KEY_UNDEF + 1); // Next insert value - VerilatedCovImpItem* m_insertp VL_GUARDED_BY(m_mutex) = nullptr; ///< Item about to insert - const char* m_insertFilenamep VL_GUARDED_BY(m_mutex) = nullptr; ///< Filename about to insert - int m_insertLineno VL_GUARDED_BY(m_mutex) = 0; ///< Line number about to insert - bool m_forcePerInstance VL_GUARDED_BY(m_mutex) = false; ///< Force per_instance + VerilatedCovImpItem* m_insertp VL_GUARDED_BY(m_mutex) = nullptr; // Item about to insert + const char* m_insertFilenamep VL_GUARDED_BY(m_mutex) = nullptr; // Filename about to insert + int m_insertLineno VL_GUARDED_BY(m_mutex) = 0; // Line number about to insert + bool m_forcePerInstance VL_GUARDED_BY(m_mutex) = false; // Force per_instance public: // CONSTRUCTORS diff --git a/include/verilated_cov.h b/include/verilated_cov.h index 4b859f319..552c6c1c0 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -68,6 +68,7 @@ class VerilatedCovImp; /// Comments for type==block: 'if', 'else', 'elsif', 'case' /// thresh Threshold to consider fully covered. /// If unspecified, downstream tools will determine it. +/// per_instance If non-zero don't combine all hierarchies into one count /// /// Example: /// @@ -97,6 +98,9 @@ template std::string vlCovCvtToStr(const T& t) VL_PURE { // VerilatedCov /// Verilator coverage per-context structure. /// All public methods in this class are thread safe. +/// +/// This structure is accessed and constructed on first access via +/// VerilatedContext::coveragep() class VerilatedCovContext VL_NOT_FINAL : public VerilatedVirtualBase { VL_UNCOPYABLE(VerilatedCovContext); @@ -117,10 +121,10 @@ public: void zero() VL_MT_SAFE; public: // But Internal use only - /// Insert a coverage item - /// We accept from 1-30 key/value pairs, all as strings. - /// Call _insert1, followed by _insert2 and _insert3 - /// Do not call directly; use VL_COVER_INSERT or higher level macros instead + // Insert a coverage item + // We accept from 1-30 key/value pairs, all as strings. + // Call _insert1, followed by _insert2 and _insert3 + // Do not call directly; use VL_COVER_INSERT or higher level macros instead // _insert1: Remember item pointer with count. (Not const, as may add zeroing function) void _inserti(vluint32_t* itemp) VL_MT_SAFE; void _inserti(vluint64_t* itemp) VL_MT_SAFE; @@ -163,9 +167,9 @@ protected: // VerilatedCov /// Verilator coverage global class /// -/// Global class that accesses via current thread's context. These are -/// provided for backward-compatibility, use VerilatedContext->coveragep() -/// instead. +/// Global class that accesses via current thread's context's +/// VerilatedCovContext. This class is provided only for +/// backward-compatibility, use VerilatedContext::coveragep() instead. #ifndef VL_NO_LEGACY class VerilatedCov final { @@ -189,7 +193,7 @@ public: static void zero() VL_MT_SAFE { threadCovp()->zero(); } private: - /// Current thread's coverage structure + // Current thread's coverage structure static VerilatedCovContext* threadCovp() VL_MT_SAFE; }; #endif diff --git a/include/verilated_dpi.cpp b/include/verilated_dpi.cpp index 65579865e..47139cd1e 100644 --- a/include/verilated_dpi.cpp +++ b/include/verilated_dpi.cpp @@ -20,6 +20,9 @@ /// Declare any DPI routine inside Verilog to add this to the Makefile for /// the linker. /// +/// For documentation on the exported functions (named sv*) that are +/// implemented here, refer to the IEEE DPI chapter. +/// //========================================================================= #define VERILATOR_VERILATED_DPI_CPP_ @@ -200,13 +203,13 @@ int svIncrement(const svOpenArrayHandle h, int d) { return _vl_openhandle_varp(h int svSize(const svOpenArrayHandle h, int d) { return _vl_openhandle_varp(h)->elements(d); } int svDimensions(const svOpenArrayHandle h) { return _vl_openhandle_varp(h)->udims(); } -/// Return pointer to open array data, or nullptr if not in IEEE standard C layout +// Return pointer to open array data, or nullptr if not in IEEE standard C layout void* svGetArrayPtr(const svOpenArrayHandle h) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h); if (VL_UNLIKELY(!varp->isDpiStdLayout())) return nullptr; return varp->datap(); } -/// Return size of open array, or 0 if not in IEEE standard C layout +// Return size of open array, or 0 if not in IEEE standard C layout int svSizeOfArray(const svOpenArrayHandle h) { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h); if (VL_UNLIKELY(!varp->isDpiStdLayout())) return 0; @@ -256,7 +259,7 @@ static void* _vl_sv_adjusted_datap(const VerilatedDpiOpenVar* varp, int nargs, i return datap; } -/// Return pointer to simulator open array element, or nullptr if outside range +// Return pointer to simulator open array element, or nullptr if outside range static void* _vl_svGetArrElemPtr(const svOpenArrayHandle h, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(h); @@ -265,7 +268,7 @@ static void* _vl_svGetArrElemPtr(const svOpenArrayHandle h, int nargs, int indx1 return datap; } -/// Copy to user bit array from simulator open array +// Copy to user bit array from simulator open array static void _vl_svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s); @@ -293,7 +296,7 @@ static void _vl_svGetBitArrElemVecVal(svBitVecVal* d, const svOpenArrayHandle s, return; // LCOV_EXCL_STOP } } -/// Copy to user logic array from simulator open array +// Copy to user logic array from simulator open array static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandle s, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(s); @@ -336,7 +339,7 @@ static void _vl_svGetLogicArrElemVecVal(svLogicVecVal* d, const svOpenArrayHandl } } -/// Copy to simulator open array from from user bit array +// Copy to simulator open array from from user bit array static void _vl_svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecVal* s, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d); @@ -358,7 +361,7 @@ static void _vl_svPutBitArrElemVecVal(const svOpenArrayHandle d, const svBitVecV return; // LCOV_EXCL_STOP } } -/// Copy to simulator open array from from user logic array +// Copy to simulator open array from from user logic array static void _vl_svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogicVecVal* s, int nargs, int indx1, int indx2, int indx3) VL_MT_SAFE { const VerilatedDpiOpenVar* varp = _vl_openhandle_varp(d); @@ -381,7 +384,7 @@ static void _vl_svPutLogicArrElemVecVal(const svOpenArrayHandle d, const svLogic } } -/// Return bit from simulator open array +// Return bit from simulator open array static svBit _vl_svGetBitArrElem(const svOpenArrayHandle s, int nargs, int indx1, int indx2, int indx3, int indx4) VL_MT_SAFE { // One extra index supported, as need bit number @@ -396,7 +399,7 @@ static svBit _vl_svGetBitArrElem(const svOpenArrayHandle s, int nargs, int indx1 return 0; // LCOV_EXCL_STOP } } -/// Update simulator open array from bit +// Update simulator open array from bit static void _vl_svPutBitArrElem(const svOpenArrayHandle d, svBit value, int nargs, int indx1, int indx2, int indx3, int indx4) VL_MT_SAFE { // One extra index supported, as need bit number diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index fd43f365b..786058f10 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -49,8 +49,8 @@ private: std::map m_code2symbol; std::map m_local2fstdtype; std::list m_curScope; - fstHandle* m_symbolp = nullptr; ///< same as m_code2symbol, but as an array - char* m_strbuf = nullptr; ///< String buffer long enough to hold maxBits() chars + fstHandle* m_symbolp = nullptr; // same as m_code2symbol, but as an array + char* m_strbuf = nullptr; // String buffer long enough to hold maxBits() chars // CONSTRUCTORS VL_UNCOPYABLE(VerilatedFst); @@ -128,7 +128,7 @@ template <> void VerilatedTrace::set_time_resolution(const std::st /// Also derived for use in SystemC simulations. class VerilatedFstC final { - VerilatedFst m_sptrace; ///< Trace file being created + VerilatedFst m_sptrace; // Trace file being created // CONSTRUCTORS VL_UNCOPYABLE(VerilatedFstC); diff --git a/include/verilated_imp.h b/include/verilated_imp.h index 7a37b1017..3cf36bf0e 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -61,8 +61,8 @@ public: private: // MEMBERS - vluint32_t m_mtaskId; ///< MTask that did enqueue - std::function m_cb; ///< Lambda to execute when message received + vluint32_t m_mtaskId; // MTask that did enqueue + std::function m_cb; // Lambda to execute when message received public: // CONSTRUCTORS explicit VerilatedMsg(const std::function& cb) @@ -85,10 +85,10 @@ public: class VerilatedEvalMsgQueue final { using VerilatedThreadQueue = std::multiset; - std::atomic m_depth; ///< Current depth of queue (see comments below) + std::atomic m_depth; // Current depth of queue (see comments below) - VerilatedMutex m_mutex; ///< Mutex protecting queue - VerilatedThreadQueue m_queue VL_GUARDED_BY(m_mutex); ///< Message queue + VerilatedMutex m_mutex; // Mutex protecting queue + VerilatedThreadQueue m_queue VL_GUARDED_BY(m_mutex); // Message queue public: // CONSTRUCTORS VerilatedEvalMsgQueue() @@ -197,7 +197,7 @@ public: //====================================================================== // VerilatedContextImpData -/// Class for hidden implementation members inside VerilatedContext +// Class for hidden implementation members inside VerilatedContext // Avoids needing std::unordered_map inside verilated.h class VerilatedContextImpData final { friend class VerilatedContext; @@ -206,7 +206,7 @@ class VerilatedContextImpData final { protected: /// Map of // Used by scopeInsert, scopeFind, scopeErase, scopeNameMap - mutable VerilatedMutex m_nameMutex; ///< Protect m_nameMap + mutable VerilatedMutex m_nameMutex; // Protect m_nameMap VerilatedScopeNameMap m_nameMap VL_GUARDED_BY(m_nameMutex); }; @@ -407,22 +407,22 @@ protected: // MEMBERS // Nothing below here is save-restored; users expected to re-register appropriately - VerilatedMutex m_userMapMutex; ///< Protect m_userMap + VerilatedMutex m_userMapMutex; // Protect m_userMap // For userInsert, userFind. As indexed by pointer is common across contexts. - UserMap m_userMap VL_GUARDED_BY(m_userMapMutex); ///< Map of <(scope,userkey), userData> + UserMap m_userMap VL_GUARDED_BY(m_userMapMutex); // Map of <(scope,userkey), userData> - VerilatedMutex m_hierMapMutex; ///< Protect m_hierMap - /// Map that represents scope hierarchy + VerilatedMutex m_hierMapMutex; // Protect m_hierMap + // Map that represents scope hierarchy // Used by hierarchyAdd, hierarchyRemove, hierarchyMap VerilatedHierarchyMap m_hierMap VL_GUARDED_BY(m_hierMapMutex); // Slow - somewhat static: - VerilatedMutex m_exportMutex; ///< Protect m_nameMap - /// Map of + VerilatedMutex m_exportMutex; // Protect m_nameMap + // Map of // Used by exportInsert, exportFind, exportName. // Export numbers same across all contexts as just a string-to-number conversion ExportNameMap m_exportMap VL_GUARDED_BY(m_exportMutex); - int m_exportNext VL_GUARDED_BY(m_exportMutex) = 0; ///< Next export funcnum + int m_exportNext VL_GUARDED_BY(m_exportMutex) = 0; // Next export funcnum // CONSTRUCTORS VerilatedImpData() = default; diff --git a/include/verilated_save.h b/include/verilated_save.h index 23595f377..c2f5ec8a4 100644 --- a/include/verilated_save.h +++ b/include/verilated_save.h @@ -28,18 +28,23 @@ #include //============================================================================= -// VerilatedSerialize - convert structures to a stream representation -// This class is not thread safe, it must be called by a single thread +// VerilatedSerialize +/// Convert structures to a stream representation. +/// +/// User wrapper code will more typically use VerilatedSave which uses this +/// as a subclass to write a file. +/// +/// This class is not thread safe, it must be called by a single thread class VerilatedSerialize VL_NOT_FINAL { protected: // MEMBERS // For speed, keep m_cp as the first member of this structure - vluint8_t* m_cp; ///< Current pointer into m_bufp buffer - vluint8_t* m_bufp; ///< Output buffer - bool m_isOpen = false; ///< True indicates open file/stream - std::string m_filename; ///< Filename, for error messages - VerilatedAssertOneThread m_assertOne; ///< Assert only called from single thread + vluint8_t* m_cp; // Current pointer into m_bufp buffer + vluint8_t* m_bufp; // Output buffer + bool m_isOpen = false; // True indicates open file/stream + std::string m_filename; // Filename, for error messages + VerilatedAssertOneThread m_assertOne; // Assert only called from single thread static constexpr size_t bufferSize() { return 256 * 1024; } // See below for slack calculation static constexpr size_t bufferInsertSize() { return 16 * 1024; } @@ -51,19 +56,26 @@ protected: VL_UNCOPYABLE(VerilatedSerialize); public: + /// Construct VerilatedSerialize() { m_bufp = new vluint8_t[bufferSize()]; m_cp = m_bufp; } + /// Flish, close, and destruct virtual ~VerilatedSerialize() { close(); if (m_bufp) VL_DO_CLEAR(delete[] m_bufp, m_bufp = nullptr); } // METHODS + /// Return true if file is open bool isOpen() const { return m_isOpen; } + /// Return current filename std::string filename() const { return m_filename; } + /// Close the stream virtual void close() VL_MT_UNSAFE_ONE { flush(); } + /// Flush pending data to stream virtual void flush() VL_MT_UNSAFE_ONE {} + /// Write data to stream VerilatedSerialize& write(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { const vluint8_t* __restrict dp = (const vluint8_t* __restrict)datap; while (size) { @@ -87,19 +99,24 @@ private: }; //============================================================================= -// VerilatedDeserial - load structures from a stream representation -// This class is not thread safe, it must be called by a single thread +// VerilatedDeserialize +/// Load structures from a stream representation +/// +/// User wrapper code will more typically use VerilatedRestore which uses +/// this as a subclass to a read from a file. +/// +/// This class is not thread safe, it must be called by a single thread class VerilatedDeserialize VL_NOT_FINAL { protected: // MEMBERS // For speed, keep m_cp as the first member of this structure - vluint8_t* m_cp; ///< Current pointer into m_bufp buffer - vluint8_t* m_bufp; ///< Output buffer - vluint8_t* m_endp = nullptr; ///< Last valid byte in m_bufp buffer - bool m_isOpen = false; ///< True indicates open file/stream - std::string m_filename; ///< Filename, for error messages - VerilatedAssertOneThread m_assertOne; ///< Assert only called from single thread + vluint8_t* m_cp; // Current pointer into m_bufp buffer + vluint8_t* m_bufp; // Output buffer + vluint8_t* m_endp = nullptr; // Last valid byte in m_bufp buffer + bool m_isOpen = false; // True indicates open file/stream + std::string m_filename; // Filename, for error messages + VerilatedAssertOneThread m_assertOne; // Assert only called from single thread static constexpr size_t bufferSize() { return 256 * 1024; } // See below for slack calculation static constexpr size_t bufferInsertSize() { return 16 * 1024; } @@ -112,19 +129,26 @@ protected: VL_UNCOPYABLE(VerilatedDeserialize); public: + /// Construct VerilatedDeserialize() { m_bufp = new vluint8_t[bufferSize()]; m_cp = m_bufp; } + /// Destruct virtual ~VerilatedDeserialize() { close(); if (m_bufp) VL_DO_CLEAR(delete[] m_bufp, m_bufp = nullptr); } // METHODS + /// Return true if file is open bool isOpen() const { return m_isOpen; } + /// Return current filename std::string filename() const { return m_filename; } + /// Close the stream virtual void close() VL_MT_UNSAFE_ONE { flush(); } + /// Flush pending data to stream virtual void flush() VL_MT_UNSAFE_ONE {} + /// Read data from stream VerilatedDeserialize& read(void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE { vluint8_t* __restrict dp = static_cast(datap); while (size) { @@ -137,6 +161,8 @@ public: } return *this; // For function chaining } + + // Internal use: // Read a datum and compare with expected value VerilatedDeserialize& readAssert(const void* __restrict datap, size_t size) VL_MT_UNSAFE_ONE; VerilatedDeserialize& readAssert(vluint64_t data) VL_MT_UNSAFE_ONE { @@ -154,42 +180,55 @@ private: }; //============================================================================= -// VerilatedSave - serialize to a file -// This class is not thread safe, it must be called by a single thread +// VerilatedSave +/// Stream-like object that serializes Verilated model to a file. +/// +/// This class is not thread safe, it must be called by a single thread class VerilatedSave final : public VerilatedSerialize { private: - int m_fd = -1; ///< File descriptor we're writing to + int m_fd = -1; // File descriptor we're writing to public: // CONSTRUCTORS + /// Construct new object VerilatedSave() = default; + /// Flush, close and destruct virtual ~VerilatedSave() override { close(); } // METHODS /// Open the file; call isOpen() to see if errors void open(const char* filenamep) VL_MT_UNSAFE_ONE; + /// Open the file; call isOpen() to see if errors void open(const std::string& filename) VL_MT_UNSAFE_ONE { open(filename.c_str()); } + /// Flush and close the file virtual void close() override VL_MT_UNSAFE_ONE; + /// Flush data to file virtual void flush() override VL_MT_UNSAFE_ONE; }; //============================================================================= -// VerilatedRestore - deserialize from a file -// This class is not thread safe, it must be called by a single thread +// VerilatedRestore +/// Stream-like object that serializes Verilated model from a file. +/// +/// This class is not thread safe, it must be called by a single thread class VerilatedRestore final : public VerilatedDeserialize { private: - int m_fd = -1; ///< File descriptor we're writing to + int m_fd = -1; // File descriptor we're writing to public: // CONSTRUCTORS + /// Construct new object VerilatedRestore() = default; + /// Flush, close and destruct virtual ~VerilatedRestore() override { close(); } // METHODS /// Open the file; call isOpen() to see if errors void open(const char* filenamep) VL_MT_UNSAFE_ONE; + /// Open the file; call isOpen() to see if errors void open(const std::string& filename) VL_MT_UNSAFE_ONE { open(filename.c_str()); } + /// Close the file virtual void close() override VL_MT_UNSAFE_ONE; virtual void flush() override VL_MT_UNSAFE_ONE {} virtual void fill() override VL_MT_UNSAFE_ONE; diff --git a/include/verilated_sym_props.h b/include/verilated_sym_props.h index c1d896731..4294aa0c6 100644 --- a/include/verilated_sym_props.h +++ b/include/verilated_sym_props.h @@ -15,7 +15,7 @@ /// \brief Verilated symbol inspection header /// /// This file is for inclusion by internal files that need to inspect -/// specific symbols. +/// specific symbols. Applications typically use the VPI instead. /// /// User wrapper code wanting to inspect the symbol table should use /// verilated_syms.h instead. @@ -31,8 +31,8 @@ #include //=========================================================================== -/// Verilator range -/// Thread safety: Assume is constructed only with model, then any number of readers +// Verilator range +// Thread safety: Assume is constructed only with model, then any number of readers // See also V3Ast::VNumRange class VerilatedRange final { @@ -64,8 +64,8 @@ public: }; //=========================================================================== -/// Verilator variable -/// Thread safety: Assume is constructed only with model, then any number of readers +// Verilator variable +// Thread safety: Assume is constructed only with model, then any number of readers class VerilatedVarProps VL_NOT_FINAL { // TYPES @@ -144,7 +144,7 @@ public: } vluint32_t entSize() const; bool isPublicRW() const { return ((m_vlflags & VLVF_PUB_RW) != 0); } - /// DPI compatible C standard layout + // DPI compatible C standard layout bool isDpiCLayout() const { return ((m_vlflags & VLVF_DPI_CLAY) != 0); } int udims() const { return m_udims; } int dims() const { return m_pdims + m_udims; } @@ -177,14 +177,14 @@ public: ? m_packed.elements() : VL_LIKELY(dim >= 1 && dim <= udims()) ? m_unpacked[dim - 1].elements() : 0; } - /// Total size in bytes (note DPI limited to 4GB) + // Total size in bytes (note DPI limited to 4GB) size_t totalSize() const; - /// Adjust a data pointer to access a given array element, NuLL if something goes bad + // Adjust a data pointer to access a given array element, NuLL if something goes bad void* datapAdjustIndex(void* datap, int dim, int indx) const; }; //=========================================================================== -/// Verilator DPI open array variable +// Verilator DPI open array variable class VerilatedDpiOpenVar final { // MEMBERS @@ -221,8 +221,8 @@ public: }; //=========================================================================== -/// Verilator variable -/// Thread safety: Assume is constructed only with model, then any number of readers +// Verilator variable +// Thread safety: Assume is constructed only with model, then any number of readers class VerilatedVar final : public VerilatedVarProps { // MEMBERS diff --git a/include/verilated_threads.h b/include/verilated_threads.h index 433d28f58..3416ae965 100644 --- a/include/verilated_threads.h +++ b/include/verilated_threads.h @@ -55,7 +55,7 @@ using VlThrSymTab = void*; using VlExecFnp = void (*)(bool, VlThrSymTab); -/// Track dependencies for a single MTask. +// Track dependencies for a single MTask. class VlMTaskVertex final { // MEMBERS static std::atomic s_yields; // Statistics diff --git a/include/verilated_trace.h b/include/verilated_trace.h index 3d0ccce3b..b0173f7fd 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -139,20 +139,20 @@ private: , m_userp{userp} {} }; - vluint32_t* m_sigs_oldvalp; ///< Old value store - vluint64_t m_timeLastDump; ///< Last time we did a dump - std::vector m_initCbs; ///< Routines to initialize traciong - std::vector m_fullCbs; ///< Routines to perform full dump - std::vector m_chgCbs; ///< Routines to perform incremental dump - std::vector m_cleanupCbs; ///< Routines to call at the end of dump - bool m_fullDump; ///< Whether a full dump is required on the next call to 'dump' - vluint32_t m_nextCode; ///< Next code number to assign - vluint32_t m_numSignals; ///< Number of distinct signals - vluint32_t m_maxBits; ///< Number of bits in the widest signal - std::string m_moduleName; ///< Name of module being trace initialized now + vluint32_t* m_sigs_oldvalp; // Old value store + vluint64_t m_timeLastDump; // Last time we did a dump + std::vector m_initCbs; // Routines to initialize traciong + std::vector m_fullCbs; // Routines to perform full dump + std::vector m_chgCbs; // Routines to perform incremental dump + std::vector m_cleanupCbs; // Routines to call at the end of dump + bool m_fullDump; // Whether a full dump is required on the next call to 'dump' + vluint32_t m_nextCode; // Next code number to assign + vluint32_t m_numSignals; // Number of distinct signals + vluint32_t m_maxBits; // Number of bits in the widest signal + std::string m_moduleName; // Name of module being trace initialized now char m_scopeEscape; - double m_timeRes; ///< Time resolution (ns/ms etc) - double m_timeUnit; ///< Time units (ns/ms etc) + double m_timeRes; // Time resolution (ns/ms etc) + double m_timeUnit; // Time units (ns/ms etc) void addCallbackRecord(std::vector& cbVec, CallbackRecord& cbRec) VL_MT_SAFE_EXCLUDES(m_mutex); diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index e1e3eb5c7..f7a18d138 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -53,14 +53,14 @@ // This size comes form VCD allowing use of printable ASCII characters between // '!' and '~' inclusive, which are a total of 94 different values. Encoding a // 32 bit code hence needs a maximum of ceil(log94(2**32-1)) == 5 bytes. -constexpr unsigned VL_TRACE_MAX_VCD_CODE_SIZE = 5; ///< Maximum length of a VCD string code +constexpr unsigned VL_TRACE_MAX_VCD_CODE_SIZE = 5; // Maximum length of a VCD string code // We use 8 bytes per code in a suffix buffer array. // 1 byte optional separator + VL_TRACE_MAX_VCD_CODE_SIZE bytes for code // + 1 byte '\n' + 1 byte suffix size. This luckily comes out to a power of 2, // meaning the array can be aligned such that entries never straddle multiple // cache-lines. -constexpr unsigned VL_TRACE_SUFFIX_ENTRY_SIZE = 8; ///< Size of a suffix entry +constexpr unsigned VL_TRACE_SUFFIX_ENTRY_SIZE = 8; // Size of a suffix entry //============================================================================= // Specialization of the generics for this trace format diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 74efa39ca..0e5e2e336 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -38,7 +38,7 @@ class VerilatedVcd; class VerilatedVcdFile VL_NOT_FINAL { private: - int m_fd = 0; ///< File descriptor we're writing to + int m_fd = 0; // File descriptor we're writing to public: // METHODS VerilatedVcdFile() = default; @@ -61,25 +61,25 @@ private: //========================================================================= // VCD specific internals - VerilatedVcdFile* m_filep; ///< File we're writing to - bool m_fileNewed; ///< m_filep needs destruction - bool m_isOpen = false; ///< True indicates open file - bool m_evcd = false; ///< True for evcd format - std::string m_filename; ///< Filename we're writing to (if open) - vluint64_t m_rolloverMB = 0; ///< MB of file size to rollover at - int m_modDepth = 0; ///< Depth of module hierarchy + VerilatedVcdFile* m_filep; // File we're writing to + bool m_fileNewed; // m_filep needs destruction + bool m_isOpen = false; // True indicates open file + bool m_evcd = false; // True for evcd format + std::string m_filename; // Filename we're writing to (if open) + vluint64_t m_rolloverMB = 0; // MB of file size to rollover at + int m_modDepth = 0; // Depth of module hierarchy - char* m_wrBufp; ///< Output buffer - char* m_wrFlushp; ///< Output buffer flush trigger location - char* m_writep; ///< Write pointer into output buffer - vluint64_t m_wrChunkSize; ///< Output buffer size - vluint64_t m_wroteBytes = 0; ///< Number of bytes written to this file + char* m_wrBufp; // Output buffer + char* m_wrFlushp; // Output buffer flush trigger location + char* m_writep; // Write pointer into output buffer + vluint64_t m_wrChunkSize; // Output buffer size + vluint64_t m_wroteBytes = 0; // Number of bytes written to this file - std::vector m_suffixes; ///< VCD line end string codes + metadata - const char* m_suffixesp; ///< Pointer to first element of above + std::vector m_suffixes; // VCD line end string codes + metadata + const char* m_suffixesp; // Pointer to first element of above using NameMap = std::map; - NameMap* m_namemapp = nullptr; ///< List of names for the header + NameMap* m_namemapp = nullptr; // List of names for the header void bufferResize(vluint64_t minsize); void bufferFlush() VL_MT_UNSAFE_ONE; @@ -331,7 +331,7 @@ template <> void VerilatedTrace::set_time_resolution(const std::st /// Also derived for use in SystemC simulations. class VerilatedVcdC VL_NOT_FINAL { - VerilatedVcd m_sptrace; ///< Trace file being created + VerilatedVcd m_sptrace; // Trace file being created // CONSTRUCTORS VL_UNCOPYABLE(VerilatedVcdC); diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 5089ad5e4..69c37a876 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -19,6 +19,9 @@ /// /// Use "verilator --vpi" to add this to the Makefile for the linker. /// +/// For documentation on the exported functions (named vpi_*) that are +/// implemented here, refer to the IEEE DPI chapter. +/// //========================================================================= #define VERILATOR_VERILATED_VPI_CPP_ @@ -57,8 +60,8 @@ constexpr unsigned VL_VPI_LINE_SIZE_ = 8192; // Base VPI handled object class VerilatedVpio VL_NOT_FINAL { // CONSTANTS - /// Magic value stored in front of object to detect double free etc - /// Must be odd, as aligned pointer can never be odd + // Magic value stored in front of object to detect double free etc + // Must be odd, as aligned pointer can never be odd static constexpr vluint32_t activeMagic() { return 0xfeed100f; } // MEM MANGLEMENT @@ -489,7 +492,7 @@ public: }; struct VerilatedVpiTimedCbsCmp { - /// Ordering sets keyed by time, then callback unique id + // Ordering sets keyed by time, then callback unique id bool operator()(const std::pair& a, const std::pair& b) const { if (a.first < b.first) return true; @@ -509,7 +512,7 @@ class VerilatedVpiImp final { VpioCbList m_cbObjLists[CB_ENUM_MAX_VALUE]; // Callbacks for each supported reason VpioTimedCbs m_timedCbs; // Time based callbacks VerilatedVpiError* m_errorInfop = nullptr; // Container for vpi error info - VerilatedAssertOneThread m_assertOne; ///< Assert only called from single thread + VerilatedAssertOneThread m_assertOne; // Assert only called from single thread vluint64_t m_nextCallbackId = 1; // Id to identify callback static VerilatedVpiImp& s() { // Singleton @@ -652,7 +655,7 @@ VL_THREAD_LOCAL vluint8_t* VerilatedVpio::t_freeHead = nullptr; //====================================================================== // VerilatedVpiError -/// Internal container for vpi error info +// Internal container for vpi error info class VerilatedVpiError final { t_vpi_error_info m_errorInfo; diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h index 58ca002bb..d24600498 100644 --- a/include/verilated_vpi.h +++ b/include/verilated_vpi.h @@ -37,17 +37,17 @@ class VerilatedVpi final { public: - /// Call timed callbacks - /// Users should call this from their main loops + /// Call timed callbacks. + /// User wrapper code should call this from their main loops. static void callTimedCbs() VL_MT_UNSAFE_ONE; - /// Call value based callbacks - /// Users should call this from their main loops + /// Call value based callbacks. + /// User wrapper code should call this from their main loops. static bool callValueCbs() VL_MT_UNSAFE_ONE; - /// Call callbacks of arbitrary types - /// Users can call this from their application code + /// Call callbacks of arbitrary types. + /// User wrapper code should call this from their main loops. static bool callCbs(vluint32_t reason) VL_MT_UNSAFE_ONE; /// Returns time of the next registered VPI callback, or - /// ~(0) if none are registered + /// ~(0ULL) if none are registered static QData cbNextDeadline() VL_MT_UNSAFE_ONE; // Self test, for internal use only diff --git a/include/verilatedos.h b/include/verilatedos.h index 503fedb45..bdc71add4 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -120,15 +120,16 @@ # define VL_LIKELY(x) (!!(x)) ///< Boolean expression more often true than false # define VL_UNLIKELY(x) (!!(x)) ///< Boolean expression more often false than true #endif -# define VL_UNCOVERABLE(x) VL_UNLIKELY(x) ///< Boolean expression never hit by users (no coverage) +/// Boolean expression never hit by users (branch coverage disabled) +# define VL_UNCOVERABLE(x) VL_UNLIKELY(x) #ifndef VL_UNREACHABLE # define VL_UNREACHABLE ///< Point that may never be reached #endif #ifndef VL_PREFETCH_RD -# define VL_PREFETCH_RD(p) ///< Prefetch data with read intent +# define VL_PREFETCH_RD(p) ///< Prefetch pointed-to-data with read intent #endif #ifndef VL_PREFETCH_RW -# define VL_PREFETCH_RW(p) ///< Prefetch data with read/write intent +# define VL_PREFETCH_RW(p) ///< Prefetch pointed-to-data with read/write intent #endif #if defined(VL_THREADED) && !defined(VL_CPPCHECK) @@ -141,31 +142,38 @@ # else # error "Unsupported compiler for VL_THREADED: No thread-local declarator" # endif -# define VL_THREAD_LOCAL thread_local ///< Use new C++ static local thread +# define VL_THREAD_LOCAL thread_local ///< "thread_local" when supported #else -# define VL_THREAD_LOCAL ///< Use new C++ static local thread +# define VL_THREAD_LOCAL ///< "thread_local" when supported #endif #ifndef VL_NO_LEGACY -# define VL_THREAD ///< Deprecated -# define VL_STATIC_OR_THREAD static ///< Deprecated +# define VL_THREAD // Deprecated +# define VL_STATIC_OR_THREAD static // Deprecated #endif -#define VL_PURE ///< Comment tag that Function is pure (and thus also VL_MT_SAFE) -#define VL_MT_SAFE ///< Comment tag that function is threadsafe when VL_THREADED -#define VL_MT_SAFE_POSTINIT ///< Comment tag that function is threadsafe when VL_THREADED, only - ///< during normal operation (post-init) -#define VL_MT_SAFE_EXCLUDES(mutex) VL_EXCLUDES(mutex) ///< Threadsafe and uses given mutex -#define VL_MT_UNSAFE ///< Comment tag that function is not threadsafe when VL_THREADED -#define VL_MT_UNSAFE_ONE ///< Comment tag that function is not threadsafe when VL_THREADED, - ///< protected to make sure single-caller +/// Comment tag that Function is pure (and thus also VL_MT_SAFE) +#define VL_PURE +/// Comment tag that function is threadsafe when VL_THREADED +#define VL_MT_SAFE +/// Comment tag that function is threadsafe when VL_THREADED, only +/// during normal operation (post-init) +#define VL_MT_SAFE_POSTINIT +/// Clang threadsafe and uses given mutex +#define VL_MT_SAFE_EXCLUDES(mutex) VL_EXCLUDES(mutex) +/// Comment tag that function is not threadsafe when VL_THREADED +#define VL_MT_UNSAFE +/// Comment tag that function is not threadsafe when VL_THREADED, +/// protected to make sure single-caller +#define VL_MT_UNSAFE_ONE #ifndef VL_NO_LEGACY -# define VL_ULL(c) (c##ULL) ///< Add appropriate suffix to 64-bit constant (deprecated) +# define VL_ULL(c) (c##ULL) // Add appropriate suffix to 64-bit constant (deprecated) #endif -// This is not necessarily the same as #UL, depending on what the IData typedef is. -#define VL_UL(c) (static_cast(c##UL)) ///< Add appropriate suffix to 32-bit constant +/// Convert argument to IData +/// This is not necessarily the same as #UL, depending on what the IData typedef is. +#define VL_UL(c) (static_cast(c##UL)) #if defined(VL_CPPCHECK) || defined(__clang_analyzer__) || __cplusplus < 201103L # define VL_DANGLING(var) @@ -384,7 +392,7 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type #define VL_CACHE_LINE_BYTES 64 ///< Bytes in a cache line (for alignment) #ifndef VL_NO_LEGACY -# define VL_WORDSIZE VL_IDATASIZE ///< Legacy define +# define VL_WORDSIZE VL_IDATASIZE // Legacy define #endif /// Bytes this number of bits needs (1 bit=1 byte) @@ -397,10 +405,10 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type //========================================================================= // Class definition helpers -/// Used to indicate a base class, e.g. cannot label "class final" +/// Comment tag to indicate a base class, e.g. cannot label "class final" #define VL_NOT_FINAL -/// Used to declare a class as uncopyable; put after a private: +/// Declare a class as uncopyable; put after a private: #define VL_UNCOPYABLE(Type) \ Type(const Type& other) = delete; \ Type& operator=(const Type&) = delete From 7ea014dab53e9341ed2bda0a76d948d4029546ce Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 23 Mar 2021 19:49:57 -0400 Subject: [PATCH 039/110] Fix false WIDTHCONCAT on casted constant (#2849). --- Changes | 1 + src/V3Width.cpp | 1 + test_regress/t/t_cast.v | 7 +++++++ 3 files changed, 9 insertions(+) diff --git a/Changes b/Changes index 6040d6b58..a69c14979 100644 --- a/Changes +++ b/Changes @@ -24,6 +24,7 @@ Verilator 4.201 devel * Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett] * Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett] * Fix --output-split with class extends (#2839). [Iru Cai] +* Fix false WIDTHCONCAT on casted constant (#2849). [Rupert Swarbrick] Verilator 4.200 2021-03-12 diff --git a/src/V3Width.cpp b/src/V3Width.cpp index a8ad15b01..62e1a945f 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -1821,6 +1821,7 @@ private: if (m_vup->final()) { // CastSize not needed once sizes determined AstNode* underp = nodep->lhsp()->unlinkFrBack(); + underp->dtypeFrom(nodep); nodep->replaceWith(underp); VL_DO_DANGLING(pushDeletep(nodep), nodep); } diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v index b41caa110..3a6cfe81c 100644 --- a/test_regress/t/t_cast.v +++ b/test_regress/t/t_cast.v @@ -46,6 +46,10 @@ module t; (27'(coeff1 * samp1) >>> 11) + (27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings + logic one = 1'b1; + logic [32:0] b33 = {32'(0), one}; + logic [31:0] b32 = {31'(0), one}; + initial begin if (logic8bit != 8'h12) $stop; if (4'shf > 4'sh0) $stop; @@ -79,6 +83,9 @@ module t; if (27'h7ffecec != mida) $stop; if (27'h7ffecec != midb) $stop; + if (b33 != 33'b1) $stop; + if (b32 != 32'b1) $stop; + $write("*-* All Finished *-*\n"); $finish; end From 4e41c1350167a5b5c35911125f4755acbaf273fe Mon Sep 17 00:00:00 2001 From: Yutetsu TAKATSUKASA Date: Fri, 26 Mar 2021 22:48:24 +0900 Subject: [PATCH 040/110] Structurize option parser (#2809) Add V3OptionsParser that can suggest correct option. Co-authored-by: Wilson Snyder Co-authored-by: github action --- src/V3Options.cpp | 1451 ++++++++++++++++------------- src/V3Options.h | 2 - test_regress/t/t_flag_suggest.out | 11 + test_regress/t/t_flag_suggest.pl | 51 + 4 files changed, 851 insertions(+), 664 deletions(-) create mode 100644 test_regress/t/t_flag_suggest.out create mode 100755 test_regress/t/t_flag_suggest.pl diff --git a/src/V3Options.cpp b/src/V3Options.cpp index a13340cf6..5339d4260 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -25,6 +25,7 @@ #include "V3Error.h" #include "V3File.h" #include "V3PreShell.h" +#include "V3String.h" // clang-format off #include @@ -36,6 +37,7 @@ #include #include #include +#include #include #include #include @@ -104,6 +106,226 @@ public: ~V3OptionsImp() = default; }; +//###################################################################### +// V3 OptionParser + +class V3OptionsParser final { +public: + // TYPES + class ActionIfs VL_NOT_FINAL { + public: + virtual ~ActionIfs() = default; + virtual bool isValueNeeded() const = 0; // Need val of "-opt val" + virtual bool isOnOffAllowed() const = 0; // true if "-no-opt" is allowd + virtual bool isPartialMatchAllowed() const = 0; // true if "-Wno-" matches "-Wno-fatal" + virtual bool isUndocumented() const = 0; // Will not be suggested in typo + // Set a value or run callback + virtual void exec(const char* optp, const char* valp) = 0; + virtual void undocumented() = 0; + }; + enum class en { // Setting for isOnOffAllowed() and isPartialMatchAllowed() + NONE, // "-opt" + ONOFF, // "-opt" and "-no-opt" + VALUE // "-opt val" + }; + // Base class of actual action classes + template + class ActionBase VL_NOT_FINAL : public ActionIfs { + bool m_undocumented = false; // This option is not documented + public: + virtual bool isValueNeeded() const override final { return MODE == en::VALUE; } + virtual bool isOnOffAllowed() const override final { return MODE == en::ONOFF; } + virtual bool isPartialMatchAllowed() const override final { return ALLOW_PARTIAL_MATCH; } + virtual bool isUndocumented() const override { return m_undocumented; } + virtual void undocumented() override { m_undocumented = true; } + }; + // Actual action classes + template class ActionSet; // "-opt" for bool-ish, "-opt val" for int and string + template class ActionOnOff; // "-opt" and "-no-opt" for bool-ish + class ActionCbCall; // Callback without argument for "-opt" + class ActionCbOnOff; // Callback for "-opt" and "-no-opt" + template class ActionCbVal; // Callback for "-opt val" + class ActionCbPartialMatch; // Callback "-O3" for "-O" + class ActionCbPartialMatchVal; // Callback "-debugi-V3Options 3" for "-debugi-" + + // Functor to register options to V3OptionsParser + struct AppendHelper; + +private: + // MEMBERS + std::map> m_options; // All actions for option + bool m_isFinalized{false}; // Becomes after finalize() is called + VSpellCheck m_spellCheck; // Suggests closest option when not found + + // METHODS + ActionIfs* find(const char* optp) { + auto it = m_options.find(optp); + if (it != m_options.end()) return it->second.get(); + for (auto&& act : m_options) { + if (act.second->isOnOffAllowed()) { // Find starts with "-no" + const char* const nop = std::strncmp(optp, "-no", 3) ? nullptr : (optp + 3); + if (nop && (act.first == nop || act.first == (string{"-"} + nop))) { + return act.second.get(); + } + } else if (act.second->isPartialMatchAllowed()) { + if (!std::strncmp(optp, act.first.c_str(), act.first.length())) { + return act.second.get(); + } + } + } + return nullptr; + } + template ActionIfs& add(const std::string& opt, ARG arg) { + UASSERT(!m_isFinalized, "Cannot add after finalize() is called"); + std::unique_ptr act{new ACT{std::move(arg)}}; + UASSERT(opt.size() >= 2, opt << " is too short"); + UASSERT(opt[0] == '-' || opt[0] == '+', opt << " does not start with either '-' or '+'"); + UASSERT(!(opt[0] == '-' && opt[1] == '-'), "Option must have single '-', but " << opt); + const auto insertedResult = m_options.emplace(opt, std::move(act)); + UASSERT(insertedResult.second, opt << " is already registered"); + return *insertedResult.first->second; + } + static bool hasPrefixNo(const char* strp) { // Returns true if strp starts with "-no" + UASSERT(strp[0] == '-', strp << " does not start with '-'"); + if (strp[1] == '-') ++strp; + return std::strncmp(strp, "-no", 3) == 0; + } + +public: + // METHODS + // Returns how many args are consumed. 0 means not match + int parse(int idx, int argc, char* argv[]) { + UASSERT(m_isFinalized, "finalize() must be called before parse()"); + const char* optp = argv[idx]; + if (optp[0] == '-' && optp[1] == '-') ++optp; + ActionIfs* actp = find(optp); + if (!actp) return 0; + if (!actp->isValueNeeded()) { + actp->exec(optp, nullptr); + return 1; + } else if (idx + 1 < argc) { + actp->exec(optp, argv[idx + 1]); + return 2; + } + return 0; + } + // Find the most similar option + string getSuggestion(const char* str) const { return m_spellCheck.bestCandidateMsg(str); } + void addSuggestionCandidate(const string& s) { m_spellCheck.pushCandidate(s); } + void finalize() { + UASSERT(!m_isFinalized, "finalize() must not be called twice"); + for (auto&& opt : m_options) { + if (opt.second->isUndocumented()) continue; + m_spellCheck.pushCandidate(opt.first); + if (opt.second->isOnOffAllowed()) m_spellCheck.pushCandidate("-no" + opt.first); + } + m_isFinalized = true; + } +}; + +#define V3OPTIONS_DEF_ACT_CLASS(className, type, body, enType) \ + template <> class V3OptionsParser::className final : public ActionBase { \ + type* m_valp; /* Pointer to a option variable*/ \ +\ + public: \ + explicit className(type* valp) \ + : m_valp(valp) {} \ + virtual void exec(const char* optp, const char* argp) override { body; } \ + } + +V3OPTIONS_DEF_ACT_CLASS(ActionSet, bool, *m_valp = true, en::NONE); +V3OPTIONS_DEF_ACT_CLASS(ActionSet, VOptionBool, m_valp->setTrueOrFalse(true), en::NONE); +V3OPTIONS_DEF_ACT_CLASS(ActionSet, int, *m_valp = std::atoi(argp), en::VALUE); +V3OPTIONS_DEF_ACT_CLASS(ActionSet, string, *m_valp = argp, en::VALUE); + +V3OPTIONS_DEF_ACT_CLASS(ActionOnOff, bool, *m_valp = !hasPrefixNo(optp), en::ONOFF); +V3OPTIONS_DEF_ACT_CLASS(ActionOnOff, VOptionBool, m_valp->setTrueOrFalse(!hasPrefixNo(optp)), + en::ONOFF); + +#undef V3OPTIONS_DEF_ACT_CLASS + +#define V3OPTIONS_DEF_ACT_CB_CLASS(className, funcType, body, ...) \ + class V3OptionsParser::className final : public ActionBase<__VA_ARGS__> { \ + std::function m_cb; /* Callback function */ \ +\ + public: \ + using CbType = std::function; \ + explicit className(CbType cb) \ + : m_cb(std::move(cb)) {} \ + virtual void exec(const char* optp, const char* argp) override { body; } \ + } + +V3OPTIONS_DEF_ACT_CB_CLASS(ActionCbCall, void(void), m_cb(), en::NONE); +V3OPTIONS_DEF_ACT_CB_CLASS(ActionCbOnOff, void(bool), m_cb(!hasPrefixNo(optp)), en::ONOFF); +template <> +V3OPTIONS_DEF_ACT_CB_CLASS(ActionCbVal, void(int), m_cb(std::atoi(argp)), en::VALUE); +template <> +V3OPTIONS_DEF_ACT_CB_CLASS(ActionCbVal, void(const char*), m_cb(argp), en::VALUE); +V3OPTIONS_DEF_ACT_CB_CLASS(ActionCbPartialMatch, void(const char*), m_cb(optp), en::NONE, true); +V3OPTIONS_DEF_ACT_CB_CLASS(ActionCbPartialMatchVal, void(const char*, const char*), + m_cb(optp, argp), en::VALUE, true); + +#undef V3OPTIONS_DEF_ACT_CB_CLASS + +// A helper class to register options +struct V3OptionsParser::AppendHelper final { + V3OptionsParser& m_parser; // The actual option registory + + // TYPES + // Tag to specify which operator() to call + struct Set {}; // For ActionSet + struct OnOff {}; // For ActionOnOff + struct CbCall {}; // For ActionCbCall + struct CbOnOff {}; // For ActionOnOff + struct CbVal {}; // For ActionCbVal + struct CbPartialMatch {}; // For ActionCbPartialMatch + struct CbPartialMatchVal {}; // For ActionCbPartialMatchVal + + // METHODS + +#define V3OPTIONS_DEF_OP(actKind, argType, actType) \ + ActionIfs& operator()(const char* optp, actKind, argType arg) const { \ + return m_parser.add(optp, arg); \ + } + V3OPTIONS_DEF_OP(Set, bool*, ActionSet) + V3OPTIONS_DEF_OP(Set, VOptionBool*, ActionSet) + V3OPTIONS_DEF_OP(Set, int*, ActionSet) + V3OPTIONS_DEF_OP(Set, string*, ActionSet) + V3OPTIONS_DEF_OP(OnOff, bool*, ActionOnOff) + V3OPTIONS_DEF_OP(OnOff, VOptionBool*, ActionOnOff) + V3OPTIONS_DEF_OP(CbCall, ActionCbCall::CbType, ActionCbCall) + V3OPTIONS_DEF_OP(CbOnOff, ActionCbOnOff::CbType, ActionCbOnOff) + V3OPTIONS_DEF_OP(CbVal, ActionCbVal::CbType, ActionCbVal) + V3OPTIONS_DEF_OP(CbVal, ActionCbVal::CbType, ActionCbVal) +#undef V3OPTIONS_DEF_OP + + // Syntax sugar to register a member function of V3Options directry + ActionIfs& operator()(const char* optp, CbVal, + std::pair arg) const { + auto cb = [arg](int v) { (arg.first->*arg.second)(v); }; + return m_parser.add>(optp, cb); + } + ActionIfs& operator()(const char* optp, CbVal, + std::pair arg) const { + auto cb = [arg](const string& v) { (arg.first->*arg.second)(v); }; + return m_parser.add>(optp, cb); + } + // Callback of partial match expects prefix to be removed, so wrap the given callback + ActionIfs& operator()(const char* optp, CbPartialMatch, + ActionCbPartialMatch::CbType cb) const { + const size_t prefixLen = std::strlen(optp); + auto wrap = [prefixLen, cb](const char* optp) { cb(optp + prefixLen); }; + return m_parser.add(optp, std::move(wrap)); + } + ActionIfs& operator()(const char* optp, CbPartialMatchVal, + ActionCbPartialMatchVal::CbType cb) const { + const size_t prefixLen = std::strlen(optp); + auto wrap + = [prefixLen, cb](const char* optp, const char* argp) { cb(optp + prefixLen, argp); }; + return m_parser.add(optp, std::move(wrap)); + } +}; + //###################################################################### // V3LangCode class functions @@ -877,34 +1099,6 @@ void V3Options::parseOpts(FileLine* fl, int argc, char** argv) { //====================================================================== -bool V3Options::onoff(const char* sw, const char* arg, bool& flag) { - // if sw==arg, then return true (found it), and flag=true - // if sw=="-no-arg", then return true (found it), and flag=false - // if sw=="-noarg", then return true (found it), and flag=false - // else return false - if (arg[0] != '-') v3fatalSrc("OnOff switches must have leading dash"); - if (0 == strcmp(sw, arg)) { - flag = true; - return true; - } else if (0 == strncmp(sw, "-no", 3) && (0 == strcmp(sw + 3, arg + 1))) { - flag = false; - return true; - } else if (0 == strncmp(sw, "-no-", 4) && (0 == strcmp(sw + 4, arg + 1))) { - flag = false; - return true; - } - return false; -} -bool V3Options::onoffb(const char* sw, const char* arg, VOptionBool& flagr) { - bool flag; - if (onoff(sw, arg, flag /*ref*/)) { - flagr.setTrueOrFalse(flag); - return true; - } else { - return false; - } -} - bool V3Options::suffixed(const string& sw, const char* arg) { if (strlen(arg) > sw.length()) return false; return (0 == strcmp(sw.c_str() + sw.length() - strlen(arg), arg)); @@ -917,643 +1111,577 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char for (int i = 0; i < argc; ++i) { addArg(argv[i]); // -f's really should be inserted in the middle, but this is for debug } -#define shift \ - do { ++i; } while (false) + + V3OptionsParser parser; + const auto Set = V3OptionsParser::AppendHelper::Set{}; + const auto OnOff = V3OptionsParser::AppendHelper::OnOff{}; + const auto CbCall = V3OptionsParser::AppendHelper::CbCall{}; + const auto CbOnOff = V3OptionsParser::AppendHelper::CbOnOff{}; + const auto CbVal = V3OptionsParser::AppendHelper::CbVal{}; + const auto CbPartialMatch = V3OptionsParser::AppendHelper::CbPartialMatch{}; + const auto CbPartialMatchVal = V3OptionsParser::AppendHelper::CbPartialMatchVal{}; + V3OptionsParser::AppendHelper DECL_OPTION{parser}; + // Usage + // DECL_OPTION("-option", action, pointer_or_lambda); + // action: one of Set, OnOff, CbCall, CbOnOff, CbVal, CbPartialMatch, and CbPartialMatchVal + // Set : Set value to a variable, pointer_or_lambda must be a pointer to the + // variable. + // true is set to bool-ish variable when '-opt' is passed to verilator. + // val is set to int and string variable when '-opt val' is passed. + // OnOff : Set value to a bool-ish variable, pointer_or_lambda must be a pointer + // to bool or VOptionBool. + // true is set if "-opt" is passed to verilator while false is set if + // "-no-opt" is given. + // CbCall : Call lambda or function that does not take argument. + // CbOnOff : Call lambda or function that takes bool argument. + // Supports "-opt" and "-no-opt" style options. + // CbVal : Call lambda or function that takes int or const char*. + // "-opt val" is passed to verilator, val is passed to the lambda. + // If a function to be called is a member of V3Options that only takes + // bool/const string&, {this, &V3Options::memberFunc} can be passed + // instead of lambda as a syntax sugar. + // CbPartialMatch : Call lambda or function that takes remaining string. + // e.g. DECL_OPTION("-opt-", CbPartialMatch, [](const char*optp) { cout << + // optp << endl; }); and "-opt-ABC" is passed, "ABC" will be emit to + // stdout. + // CbPartialMatchVal: Call lambda or function that takes remaining string and value. + // e.g. DECL_OPTION("-opt-", CbPartialMatchVal, [](const char*optp, const + // char*valp) { + // cout << optp << ":" << valp << endl; }); + // and "-opt-ABC VAL" is passed, "ABC:VAL" will be emit to stdout. + // + // DECL_OPTION is not C-macro to get correct line coverage even when lambda is passed. + // (If DECL_OPTION is a macro, then lambda would be collapsed into a single line). + + // Plus options + DECL_OPTION("+define+", CbPartialMatch, [this](const char* optp) { addDefine(optp, true); }); + DECL_OPTION("+incdir+", CbPartialMatch, + [this, &optdir](const char* optp) { addIncDirUser(parseFileArg(optdir, optp)); }); + DECL_OPTION("+libext+", CbPartialMatch, [this](const char* optp) { + string exts = optp; + string::size_type pos; + while ((pos = exts.find('+')) != string::npos) { + addLibExtV(exts.substr(0, pos)); + exts = exts.substr(pos + 1); + } + addLibExtV(exts); + }); + DECL_OPTION("+librescan", CbCall, []() {}); // NOP + DECL_OPTION("+notimingchecks", CbCall, []() {}); // NOP + DECL_OPTION("+systemverilogext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2017); }); + DECL_OPTION("+verilog1995ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1364_1995); }); + DECL_OPTION("+verilog2001ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1364_2001); }); + DECL_OPTION("+1364-1995ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1364_1995); }); + DECL_OPTION("+1364-2001ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1364_2001); }); + DECL_OPTION("+1364-2005ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1364_2005); }); + DECL_OPTION("+1800-2005ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2005); }); + DECL_OPTION("+1800-2009ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2009); }); + DECL_OPTION("+1800-2012ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2012); }); + DECL_OPTION("+1800-2017ext+", CbPartialMatch, + [this](const char* optp) { addLangExt(optp, V3LangCode::L1800_2017); }); + + // Minus options + DECL_OPTION("-assert", OnOff, &m_assert); + DECL_OPTION("-autoflush", OnOff, &m_autoflush); + + DECL_OPTION("-bbox-sys", OnOff, &m_bboxSys); + DECL_OPTION("-bbox-unsup", CbOnOff, [this](bool flag) { + m_bboxUnsup = flag; + FileLine::globalWarnOff(V3ErrorCode::E_UNSUPPORTED, true); + }); + DECL_OPTION("-bin", Set, &m_bin); + DECL_OPTION("-build", Set, &m_build); + + DECL_OPTION("-CFLAGS", CbVal, {this, &V3Options::addCFlags}); + DECL_OPTION("-cc", CbCall, [this]() { + m_outFormatOk = true; + m_systemC = false; + }); + DECL_OPTION("-cdc", OnOff, &m_cdc); + DECL_OPTION("-clk", CbVal, {this, &V3Options::addClocker}); + DECL_OPTION("-no-clk", CbVal, {this, &V3Options::addNoClocker}); + DECL_OPTION("-comp-limit-blocks", Set, &m_compLimitBlocks).undocumented(); + DECL_OPTION("-comp-limit-members", Set, + &m_compLimitMembers) + .undocumented(); // Ideally power-of-two so structs stay aligned + DECL_OPTION("-comp-limit-parens", Set, &m_compLimitParens).undocumented(); + DECL_OPTION("-comp-limit-syms", CbVal, [](int val) { VName::maxLength(val); }).undocumented(); + DECL_OPTION("-compiler", CbVal, [this, fl](const char* valp) { + if (!strcmp(valp, "clang")) { + m_compLimitBlocks = 80; // limit unknown + m_compLimitMembers = 64; // soft limit, has slowdown bug as of clang++ 3.8 + m_compLimitParens = 80; // limit unknown + } else if (!strcmp(valp, "gcc")) { + m_compLimitBlocks = 0; // Bug free + m_compLimitMembers = 64; // soft limit, has slowdown bug as of g++ 7.1 + m_compLimitParens = 0; // Bug free + } else if (!strcmp(valp, "msvc")) { + m_compLimitBlocks = 80; // 128, but allow some room + m_compLimitMembers = 0; // probably ok, and AFAIK doesn't support anon structs + m_compLimitParens = 80; // 128, but allow some room + } else { + fl->v3fatal("Unknown setting for --compiler: '" + << valp << "'\n" + << fl->warnMore() << "... Suggest 'clang', 'gcc', or 'msvc'"); + } + }); + DECL_OPTION("-coverage", CbOnOff, [this](bool flag) { coverage(flag); }); + DECL_OPTION("-converge-limit", Set, &m_convergeLimit); + DECL_OPTION("-coverage-line", OnOff, &m_coverageLine); + DECL_OPTION("-coverage-toggle", OnOff, &m_coverageToggle); + DECL_OPTION("-coverage-underscore", OnOff, &m_coverageUnderscore); + DECL_OPTION("-coverage-user", OnOff, &m_coverageUser); + + DECL_OPTION("-D", CbPartialMatch, [this](const char* valp) { addDefine(valp, false); }); + DECL_OPTION("-debug", CbCall, [this]() { setDebugMode(3); }); + DECL_OPTION("-debugi", CbVal, {this, &V3Options::setDebugMode}); + DECL_OPTION("-debugi-", CbPartialMatchVal, [this](const char* optp, const char* valp) { + setDebugSrcLevel(optp, std::atoi(valp)); + }); + DECL_OPTION("-debug-abort", CbCall, + V3Error::vlAbort) + .undocumented(); // See also --debug-sigsegv + DECL_OPTION("-debug-check", OnOff, &m_debugCheck); + DECL_OPTION("-debug-collision", OnOff, &m_debugCollision).undocumented(); + DECL_OPTION("-debug-emitv", OnOff, &m_debugEmitV).undocumented(); + DECL_OPTION("-debug-exit-parse", OnOff, &m_debugExitParse).undocumented(); + DECL_OPTION("-debug-exit-uvm", OnOff, &m_debugExitUvm).undocumented(); + DECL_OPTION("-debug-fatalsrc", CbCall, []() { + v3fatalSrc("--debug-fatal-src"); + }).undocumented(); // See also --debug-abort + DECL_OPTION("-debug-leak", OnOff, &m_debugLeak); + DECL_OPTION("-debug-nondeterminism", OnOff, &m_debugNondeterminism); + DECL_OPTION("-debug-partition", OnOff, &m_debugPartition).undocumented(); + DECL_OPTION("-debug-protect", OnOff, &m_debugProtect).undocumented(); + DECL_OPTION("-debug-self-test", OnOff, &m_debugSelfTest).undocumented(); + DECL_OPTION("-debug-sigsegv", CbCall, throwSigsegv).undocumented(); // See also --debug-abort + DECL_OPTION("-decoration", OnOff, &m_decoration); + DECL_OPTION("-dpi-hdr-only", OnOff, &m_dpiHdrOnly); + DECL_OPTION("-dump-defines", OnOff, &m_dumpDefines); + DECL_OPTION("-dump-tree", CbOnOff, + [this](bool flag) { m_dumpTree = flag ? 3 : 0; }); // Also see --dump-treei + DECL_OPTION("-dump-tree-addrids", OnOff, &m_dumpTreeAddrids); + DECL_OPTION("-dump-treei", Set, &m_dumpTree); + DECL_OPTION("-dump-treei-", CbPartialMatchVal, [this](const char* optp, const char* valp) { + setDumpTreeLevel(optp, std::atoi(valp)); + }); + + DECL_OPTION("-E", Set, &m_preprocOnly); + DECL_OPTION("-error-limit", CbVal, static_cast(&V3Error::errorLimit)); + DECL_OPTION("-exe", OnOff, &m_exe); + + DECL_OPTION("-F", CbVal, [this, fl, &optdir](const char* valp) { + parseOptsFile(fl, parseFileArg(optdir, valp), true); + }); + DECL_OPTION("-FI", CbVal, + [this, &optdir](const char* valp) { addForceInc(parseFileArg(optdir, valp)); }); + DECL_OPTION("-f", CbVal, [this, fl, &optdir](const char* valp) { + parseOptsFile(fl, parseFileArg(optdir, valp), false); + }); + DECL_OPTION("-flatten", OnOff, &m_flatten); + + DECL_OPTION("-G", CbPartialMatch, [this](const char* optp) { addParameter(optp, false); }); + DECL_OPTION("-gate-stmts", Set, &m_gateStmts); + DECL_OPTION("-gdb", CbCall, []() {}); // Processed only in bin/verilator shell + DECL_OPTION("-gdbbt", CbCall, []() {}); // Processed only in bin/verilator shell + DECL_OPTION("-generate-key", CbCall, [this]() { + cout << protectKeyDefaulted() << endl; + exit(0); + }); + DECL_OPTION("-getenv", CbVal, [](const char* valp) { + cout << V3Options::getenvBuiltins(valp) << endl; + exit(0); + }); + + DECL_OPTION("-hierarchical", OnOff, &m_hierarchical); + DECL_OPTION("-hierarchical-block", CbVal, [this](const char* valp) { + V3HierarchicalBlockOption opt(valp); + m_hierBlocks.emplace(opt.mangledName(), opt); + }); + DECL_OPTION("-hierarchical-child", OnOff, &m_hierChild); + + DECL_OPTION("-I", CbPartialMatch, + [this, &optdir](const char* optp) { addIncDirUser(parseFileArg(optdir, optp)); }); + DECL_OPTION("-if-depth", Set, &m_ifDepth); + DECL_OPTION("-ignc", OnOff, &m_ignc); + DECL_OPTION("-inhibit-sim", CbOnOff, [this, fl](bool flag) { + fl->v3warn(DEPRECATED, "-inhibit-sim option is deprecated"); + m_inhibitSim = flag; + }); + DECL_OPTION("-inline-mult", Set, &m_inlineMult); + + DECL_OPTION("-LDFLAGS", CbVal, {this, &V3Options::addLdLibs}); + auto setLang = [this, fl](const char* valp) { + V3LangCode optval = V3LangCode(valp); + if (optval.legal()) { + m_defaultLanguage = optval; + } else { + VSpellCheck spell; + for (int i = V3LangCode::L_ERROR + 1; i < V3LangCode::_ENUM_END; ++i) { + spell.pushCandidate(V3LangCode{i}.ascii()); + } + fl->v3fatal("Unknown language specified: " << valp << spell.bestCandidateMsg(valp)); + } + }; + DECL_OPTION("-default-language", CbVal, setLang); + DECL_OPTION("-language", CbVal, setLang); + DECL_OPTION("-lint-only", OnOff, &m_lintOnly); + DECL_OPTION("-l2-name", Set, &m_l2Name); + DECL_OPTION("-no-l2name", CbCall, [this]() { m_l2Name = ""; }).undocumented(); // Historical + DECL_OPTION("-l2name", CbCall, [this]() { m_l2Name = "v"; }).undocumented(); // Historical + + DECL_OPTION("-MAKEFLAGS", CbVal, {this, &V3Options::addMakeFlags}); + DECL_OPTION("-MMD", OnOff, &m_makeDepend); + DECL_OPTION("-MP", OnOff, &m_makePhony); + DECL_OPTION("-Mdir", CbVal, [this](const char* valp) { + m_makeDir = valp; + addIncDirFallback(m_makeDir); // Need to find generated files there too + }); + DECL_OPTION("-main", OnOff, &m_main).undocumented(); // Future + DECL_OPTION("-make", CbVal, [this, fl](const char* valp) { + if (!strcmp(valp, "cmake")) { + m_cmake = true; + } else if (!strcmp(valp, "gmake")) { + m_gmake = true; + } else { + fl->v3fatal("Unknown --make system specified: '" << valp << "'"); + } + }); + DECL_OPTION("-max-num-width", Set, &m_maxNumWidth); + DECL_OPTION("-mod-prefix", Set, &m_modPrefix); + + DECL_OPTION("-O", CbPartialMatch, [this](const char* optp) { + // Optimization + for (const char* cp = optp; *cp; ++cp) { + const bool flag = isupper(*cp); + switch (tolower(*cp)) { + case '0': optimize(0); break; // 0=all off + case '1': optimize(1); break; // 1=all on + case '2': optimize(2); break; // 2=not used + case '3': optimize(3); break; // 3=high + case 'a': m_oTable = flag; break; + case 'b': m_oCombine = flag; break; + case 'c': m_oConst = flag; break; + case 'd': m_oDedupe = flag; break; + case 'e': m_oCase = flag; break; + // f + case 'g': m_oGate = flag; break; + // h + case 'i': m_oInline = flag; break; + // j + case 'k': m_oSubstConst = flag; break; + case 'l': m_oLife = flag; break; + case 'm': m_oAssemble = flag; break; + // n + case 'o': m_oConstBitOpTree = flag; break; // Can remove ~2022-01 when stable + case 'p': + m_public = !flag; + break; // With -Op so flag=0, we want public on so few optimizations done + // q + case 'r': m_oReorder = flag; break; + case 's': m_oSplit = flag; break; + case 't': m_oLifePost = flag; break; + case 'u': m_oSubst = flag; break; + case 'v': m_oReloop = flag; break; + case 'w': m_oMergeCond = flag; break; + case 'x': m_oExpand = flag; break; + case 'y': m_oAcycSimp = flag; break; + case 'z': m_oLocalize = flag; break; + default: break; // No error, just ignore + } + } + }); + DECL_OPTION("-o", Set, &m_exeName); + DECL_OPTION("-order-clock-delay", OnOff, &m_orderClockDly); + DECL_OPTION("-output-split", Set, &m_outputSplit); + DECL_OPTION("-output-split-cfuncs", CbVal, [this, fl](const char* valp) { + m_outputSplitCFuncs = std::atoi(valp); + if (m_outputSplitCFuncs < 0) { + fl->v3error("--output-split-cfuncs must be >= 0: " << valp); + } + }); + DECL_OPTION("-output-split-ctrace", CbVal, [this, fl](const char* valp) { + m_outputSplitCTrace = std::atoi(valp); + if (m_outputSplitCTrace < 0) { + fl->v3error("--output-split-ctrace must be >= 0: " << valp); + } + }); + + DECL_OPTION("-P", Set, &m_preprocNoLine); + DECL_OPTION("-pvalue+", CbPartialMatch, + [this](const char* varp) { addParameter(varp, false); }); + DECL_OPTION("-pins64", CbCall, [this]() { m_pinsBv = 65; }); + DECL_OPTION("-no-pins64", CbCall, [this]() { m_pinsBv = 33; }); + DECL_OPTION("-pins-bv", CbVal, [this, fl](const char* valp) { + m_pinsBv = std::atoi(valp); + if (m_pinsBv > 65) fl->v3fatal("--pins-bv maximum is 65: " << valp); + }); + DECL_OPTION("-pins-sc-uint", CbOnOff, [this](bool flag) { + m_pinsScUint = flag; + if (!m_pinsScBigUint) m_pinsBv = 65; + }); + DECL_OPTION("-pins-sc-biguint", CbOnOff, [this](bool flag) { + m_pinsScBigUint = flag; + m_pinsBv = 513; + }); + DECL_OPTION("-pins-uint8", OnOff, &m_pinsUint8); + DECL_OPTION("-pipe-filter", Set, &m_pipeFilter); + DECL_OPTION("-pp-comments", OnOff, &m_ppComments); + DECL_OPTION("-prefix", CbVal, [this](const char* valp) { + m_prefix = valp; + if (m_modPrefix == "") m_modPrefix = m_prefix; + }); + DECL_OPTION("-private", CbCall, [this]() { m_public = false; }); + DECL_OPTION("-prof-cfuncs", OnOff, &m_profCFuncs); + DECL_OPTION("-profile-cfuncs", OnOff, &m_profCFuncs).undocumented(); // Renamed + DECL_OPTION("-prof-threads", OnOff, &m_profThreads); + DECL_OPTION("-protect-ids", OnOff, &m_protectIds); + DECL_OPTION("-protect-key", Set, &m_protectKey); + DECL_OPTION("-protect-lib", CbVal, [this](const char* valp) { + m_protectLib = valp; + m_protectIds = true; + }); + DECL_OPTION("-public", OnOff, &m_public); + DECL_OPTION("-public-flat-rw", CbOnOff, [this](bool flag) { + m_publicFlatRW = flag; + v3Global.dpi(true); + }); + + DECL_OPTION("-quiet-exit", OnOff, &m_quietExit); + + DECL_OPTION("-relative-cfuncs", CbOnOff, [this, fl](bool flag) { + m_relativeCFuncs = flag; + if (!m_relativeCFuncs) + fl->v3warn(DEPRECATED, "Deprecated --no-relative-cfuncs, unnecessary with C++11."); + }); + DECL_OPTION("-relative-includes", OnOff, &m_relativeIncludes); + DECL_OPTION("-report-unoptflat", OnOff, &m_reportUnoptflat); + DECL_OPTION("-rr", CbCall, []() {}); // Processed only in bin/verilator shell + + DECL_OPTION("-savable", OnOff, &m_savable); + DECL_OPTION("-sc", CbCall, [this]() { + m_outFormatOk = true; + m_systemC = true; + }); + DECL_OPTION("-skip-identical", OnOff, &m_skipIdentical); + DECL_OPTION("-stats", OnOff, &m_stats); + DECL_OPTION("-stats-vars", CbOnOff, [this](bool flag) { + m_statsVars = flag; + m_stats |= flag; + }); + DECL_OPTION("-structs-unpacked", OnOff, &m_structsPacked); + DECL_OPTION("-sv", CbCall, [this]() { m_defaultLanguage = V3LangCode::L1800_2017; }); + + DECL_OPTION("-threads-coarsen", OnOff, &m_threadsCoarsen).undocumented(); // Debug + DECL_OPTION("-no-threads", CbCall, [this]() { m_threads = 0; }); + DECL_OPTION("-threads", CbVal, [this, fl](const char* valp) { + m_threads = std::atoi(valp); + if (m_threads < 0) fl->v3fatal("--threads must be >= 0: " << valp); + }); + DECL_OPTION("-threads-dpi", CbVal, [this, fl](const char* valp) { + if (!strcmp(valp, "all")) { + m_threadsDpiPure = true; + m_threadsDpiUnpure = true; + } else if (!strcmp(valp, "none")) { + m_threadsDpiPure = false; + m_threadsDpiUnpure = false; + } else if (!strcmp(valp, "pure")) { + m_threadsDpiPure = true; + m_threadsDpiUnpure = false; + } else { + fl->v3fatal("Unknown setting for --threads-dpi: " << valp); + } + }); + DECL_OPTION("-threads-max-mtasks", CbVal, [this, fl](const char* valp) { + m_threadsMaxMTasks = std::atoi(valp); + if (m_threadsMaxMTasks < 1) fl->v3fatal("--threads-max-mtasks must be >= 1: " << valp); + }); + DECL_OPTION("-timescale", CbVal, [this, fl](const char* valp) { + VTimescale unit; + VTimescale prec; + VTimescale::parseSlashed(fl, valp, unit /*ref*/, prec /*ref*/); + if (!unit.isNone() && timeOverrideUnit().isNone()) m_timeDefaultUnit = unit; + if (!prec.isNone() && timeOverridePrec().isNone()) m_timeDefaultPrec = prec; + }); + DECL_OPTION("-timescale-override", CbVal, [this, fl](const char* valp) { + VTimescale unit; + VTimescale prec; + VTimescale::parseSlashed(fl, valp, unit /*ref*/, prec /*ref*/, true); + if (!unit.isNone()) { + m_timeDefaultUnit = unit; + m_timeOverrideUnit = unit; + } + if (!prec.isNone()) { + m_timeDefaultPrec = prec; + m_timeOverridePrec = prec; + } + }); + DECL_OPTION("-top-module", Set, &m_topModule); + DECL_OPTION("-top", Set, &m_topModule); + DECL_OPTION("-trace", OnOff, &m_trace); + DECL_OPTION("-trace-coverage", OnOff, &m_traceCoverage); + DECL_OPTION("-trace-depth", Set, &m_traceDepth); + DECL_OPTION("-trace-fst", CbCall, [this]() { + m_trace = true; + m_traceFormat = TraceFormat::FST; + addLdLibs("-lz"); + }); + DECL_OPTION("-trace-fst-thread", CbCall, [this, fl]() { + m_trace = true; + m_traceFormat = TraceFormat::FST; + addLdLibs("-lz"); + fl->v3warn(DEPRECATED, "Option --trace-fst-thread is deprecated. " + "Use --trace-fst with --trace-threads > 0."); + if (m_traceThreads == 0) m_traceThreads = 1; + }); + DECL_OPTION("-trace-max-array", Set, &m_traceMaxArray); + DECL_OPTION("-trace-max-width", Set, &m_traceMaxWidth); + DECL_OPTION("-trace-params", OnOff, &m_traceParams); + DECL_OPTION("-trace-structs", OnOff, &m_traceStructs); + DECL_OPTION("-trace-threads", CbVal, [this, fl](const char* valp) { + m_trace = true; + m_traceThreads = std::atoi(valp); + if (m_traceThreads < 0) fl->v3fatal("--trace-threads must be >= 0: " << valp); + }); + DECL_OPTION("-trace-underscore", OnOff, &m_traceUnderscore); + + DECL_OPTION("-U", CbPartialMatch, &V3PreShell::undef); + DECL_OPTION("-underline-zero", OnOff, &m_underlineZero); // Deprecated + DECL_OPTION("-unroll-count", Set, &m_unrollCount).undocumented(); // Optimization tweak + DECL_OPTION("-unroll-stmts", Set, &m_unrollStmts).undocumented(); // Optimization tweak + DECL_OPTION("-unused-regexp", Set, &m_unusedRegexp); + + DECL_OPTION("-V", CbCall, [this]() { + showVersion(true); + exit(0); + }); + DECL_OPTION("-v", CbVal, [this, &optdir](const char* valp) { + V3Options::addLibraryFile(parseFileArg(optdir, valp)); + }); + DECL_OPTION("-verilate", OnOff, &m_verilate); + DECL_OPTION("-version", CbCall, [this]() { + showVersion(false); + exit(0); + }); + DECL_OPTION("-vpi", OnOff, &m_vpi); + + DECL_OPTION("-Wpedantic", OnOff, &m_pedantic); + DECL_OPTION("-Wall", CbCall, []() { + FileLine::globalWarnLintOff(false); + FileLine::globalWarnStyleOff(false); + }); + DECL_OPTION("-Werror-", CbPartialMatch, [this, fl](const char* optp) { + V3ErrorCode code(optp); + if (code == V3ErrorCode::EC_ERROR) { + if (!isFuture(optp)) fl->v3fatal("Unknown warning specified: -Werror-" << optp); + } else { + V3Error::pretendError(code, true); + } + }); + DECL_OPTION("-Wfuture-", CbPartialMatch, [this](const char* optp) { + // Note it may not be a future option, but one that is currently implemented. + addFuture(optp); + }); + DECL_OPTION("-Wno-", CbPartialMatch, [fl, &parser](const char* optp) { + if (!FileLine::globalWarnOff(optp, true)) { + const string fullopt = string{"-Wno-"} + optp; + fl->v3fatal("Unknown warning specified: " << fullopt + << parser.getSuggestion(fullopt.c_str())); + } + }); + for (int i = V3ErrorCode::EC_FIRST_WARN; i < V3ErrorCode::_ENUM_MAX; ++i) { + for (const string prefix : {"-Wno-", "-Wwarn-"}) + parser.addSuggestionCandidate(prefix + V3ErrorCode{i}.ascii()); + } + DECL_OPTION("-Wno-context", CbCall, [this]() { m_context = false; }); + DECL_OPTION("-Wno-fatal", CbCall, []() { V3Error::warnFatal(false); }); + DECL_OPTION("-Wno-lint", CbCall, []() { + FileLine::globalWarnLintOff(true); + FileLine::globalWarnStyleOff(true); + }); + DECL_OPTION("-Wno-style", CbCall, []() { FileLine::globalWarnStyleOff(true); }); + DECL_OPTION("-Wwarn-", CbPartialMatch, [this, fl, &parser](const char* optp) { + const V3ErrorCode code{optp}; + if (code == V3ErrorCode::EC_ERROR) { + if (!isFuture(optp)) { + const string fullopt = string{"-Wwarn-"} + optp; + fl->v3fatal("Unknown warning specified: " + << fullopt << parser.getSuggestion(fullopt.c_str())); + } + } else { + FileLine::globalWarnOff(code, false); + V3Error::pretendError(code, false); + } + }); + DECL_OPTION("-Wwarn-lint", CbCall, []() { FileLine::globalWarnLintOff(false); }); + DECL_OPTION("-Wwarn-style", CbCall, []() { FileLine::globalWarnStyleOff(false); }); + DECL_OPTION("-waiver-output", Set, &m_waiverOutput); + + DECL_OPTION("-x-assign", CbVal, [this, fl](const char* valp) { + if (!strcmp(valp, "0")) { + m_xAssign = "0"; + } else if (!strcmp(valp, "1")) { + m_xAssign = "1"; + } else if (!strcmp(valp, "fast")) { + m_xAssign = "fast"; + } else if (!strcmp(valp, "unique")) { + m_xAssign = "unique"; + } else { + fl->v3fatal("Unknown setting for --x-assign: " << valp); + } + }); + DECL_OPTION("-x-initial", CbVal, [this, fl](const char* valp) { + if (!strcmp(valp, "0")) { + m_xInitial = "0"; + } else if (!strcmp(valp, "fast")) { + m_xInitial = "fast"; + } else if (!strcmp(valp, "unique")) { + m_xInitial = "unique"; + } else { + fl->v3fatal("Unknown setting for --x-initial: " << valp); + } + }); + DECL_OPTION("-x-initial-edge", OnOff, &m_xInitialEdge); + DECL_OPTION("-xml-only", OnOff, &m_xmlOnly); + DECL_OPTION("-xml-output", CbVal, [this](const char* valp) { + m_xmlOutput = valp; + m_xmlOnly = true; + }); + + DECL_OPTION("-y", CbVal, [this, &optdir](const char* valp) { + addIncDirUser(parseFileArg(optdir, string(valp))); + }); + parser.finalize(); + for (int i = 0; i < argc;) { UINFO(9, " Option: " << argv[i] << endl); - // + options - if (argv[i][0] == '+') { - char* sw = argv[i]; - if (!strncmp(sw, "+define+", 8)) { - addDefine(string(sw + strlen("+define+")), true); - } else if (!strncmp(sw, "+incdir+", 8)) { - addIncDirUser(parseFileArg(optdir, string(sw + strlen("+incdir+")))); - } else if (parseLangExt(sw, "+systemverilogext+", V3LangCode::L1800_2017) - || parseLangExt(sw, "+verilog1995ext+", V3LangCode::L1364_1995) - || parseLangExt(sw, "+verilog2001ext+", V3LangCode::L1364_2001) - || parseLangExt(sw, "+1364-1995ext+", V3LangCode::L1364_1995) - || parseLangExt(sw, "+1364-2001ext+", V3LangCode::L1364_2001) - || parseLangExt(sw, "+1364-2005ext+", V3LangCode::L1364_2005) - || parseLangExt(sw, "+1800-2005ext+", V3LangCode::L1800_2005) - || parseLangExt(sw, "+1800-2009ext+", V3LangCode::L1800_2009) - || parseLangExt(sw, "+1800-2012ext+", V3LangCode::L1800_2012) - || parseLangExt(sw, "+1800-2017ext+", V3LangCode::L1800_2017)) { - // Nothing to do here - all done in the test - - } else if (!strncmp(sw, "+libext+", 8)) { - string exts = string(sw + strlen("+libext+")); - string::size_type pos; - while ((pos = exts.find('+')) != string::npos) { - addLibExtV(exts.substr(0, pos)); - exts = exts.substr(pos + 1); + if (!strcmp(argv[i], "-j") || !strcmp(argv[i], "--j")) { // Allow gnu -- switches + ++i; + m_buildJobs = 0; // Unlimited parallelism + if (i < argc && isdigit(argv[i][0])) { + m_buildJobs = atoi(argv[i]); + if (m_buildJobs <= 0) { + fl->v3error("-j accepts positive integer, but '" << argv[i] << "' is passed"); } - addLibExtV(exts); - } else if (!strcmp(sw, "+librescan")) { // NOP - } else if (!strcmp(sw, "+notimingchecks")) { // NOP + ++i; + } + } else if (argv[i][0] == '-' || argv[i][0] == '+') { + if (const int consumed = parser.parse(i, argc, argv)) { + i += consumed; } else { - fl->v3fatal("Invalid option: " << argv[i]); + fl->v3fatal("Invalid option: " << argv[i] << parser.getSuggestion(argv[i])); + ++i; } - shift; - } - // - options - else if (argv[i][0] == '-') { - const char* sw = argv[i]; - bool flag = true; - VOptionBool bflag; - // Allow gnu -- switches - if (sw[0] == '-' && sw[1] == '-') ++sw; - bool hadSwitchPart1 = true; - // Single switches - if (!strcmp(sw, "-E")) { - m_preprocOnly = true; - } else if (onoffb(sw, "-MMD", bflag /*ref*/)) { - m_makeDepend = bflag; - } else if (onoff(sw, "-MP", flag /*ref*/)) { - m_makePhony = flag; - } else if (!strcmp(sw, "-P")) { - m_preprocNoLine = true; - } else if (onoff(sw, "-assert", flag /*ref*/)) { - m_assert = flag; - } else if (onoff(sw, "-autoflush", flag /*ref*/)) { - m_autoflush = flag; - } else if (onoff(sw, "-bbox-sys", flag /*ref*/)) { - m_bboxSys = flag; - } else if (onoff(sw, "-bbox-unsup", flag /*ref*/)) { - FileLine::globalWarnOff(V3ErrorCode::E_UNSUPPORTED, true); - m_bboxUnsup = flag; - } else if (!strcmp(sw, "-build")) { - m_build = true; - } else if (!strcmp(sw, "-cc")) { - m_outFormatOk = true; - m_systemC = false; - } else if (onoff(sw, "-cdc", flag /*ref*/)) { - m_cdc = flag; - } else if (onoff(sw, "-coverage", flag /*ref*/)) { - coverage(flag); - } else if (onoff(sw, "-coverage-line", flag /*ref*/)) { - m_coverageLine = flag; - } else if (onoff(sw, "-coverage-toggle", flag /*ref*/)) { - m_coverageToggle = flag; - } else if (onoff(sw, "-coverage-underscore", flag /*ref*/)) { - m_coverageUnderscore = flag; - } else if (onoff(sw, "-coverage-user", flag /*ref*/)) { - m_coverageUser = flag; - } else if (!strcmp(sw, "-debug-abort")) { // Undocumented, see also --debug-sigsegv - V3Error::vlAbort(); - } else if (onoff(sw, "-debug-check", flag /*ref*/)) { - m_debugCheck = flag; - } else if (onoff(sw, "-debug-collision", flag /*ref*/)) { // Undocumented - m_debugCollision = flag; - } else if (onoff(sw, "-debug-emitv", flag /*ref*/)) { // Undocumented - m_debugEmitV = flag; - } else if (onoff(sw, "-debug-exit-parse", flag /*ref*/)) { // Undocumented - m_debugExitParse = flag; - } else if (onoff(sw, "-debug-exit-uvm", flag /*ref*/)) { // Undocumented - m_debugExitUvm = flag; - } else if (onoff(sw, "-debug-leak", flag /*ref*/)) { - m_debugLeak = flag; - } else if (onoff(sw, "-debug-nondeterminism", flag /*ref*/)) { - m_debugNondeterminism = flag; - } else if (onoff(sw, "-debug-partition", flag /*ref*/)) { // Undocumented - m_debugPartition = flag; - } else if (onoff(sw, "-debug-protect", flag /*ref*/)) { // Undocumented - m_debugProtect = flag; - } else if (onoff(sw, "-debug-self-test", flag /*ref*/)) { // Undocumented - m_debugSelfTest = flag; - } else if (!strcmp(sw, "-debug-sigsegv")) { // Undocumented, see also --debug-abort - throwSigsegv(); - } else if (!strcmp(sw, "-debug-fatalsrc")) { // Undocumented, see also --debug-abort - v3fatalSrc("--debug-fatal-src"); - } else if (onoff(sw, "-decoration", flag /*ref*/)) { - m_decoration = flag; - } else if (onoff(sw, "-dpi-hdr-only", flag /*ref*/)) { - m_dpiHdrOnly = flag; - } else if (onoff(sw, "-dump-defines", flag /*ref*/)) { - m_dumpDefines = flag; - } else if (onoff(sw, "-dump-tree", flag /*ref*/)) { // Also see --dump-treei - m_dumpTree = flag ? 3 : 0; - } else if (onoff(sw, "-dump-tree-addrids", flag /*ref*/)) { - m_dumpTreeAddrids = flag; - } else if (onoff(sw, "-exe", flag /*ref*/)) { - m_exe = flag; - } else if (onoff(sw, "-flatten", flag /*ref*/)) { - m_flatten = flag; - } else if (onoff(sw, "-hierarchical", flag /*ref*/)) { - m_hierarchical = flag; - } else if (onoff(sw, "-hierarchical-child", flag /*ref*/)) { - m_hierChild = flag; - } else if (onoff(sw, "-ignc", flag /*ref*/)) { - m_ignc = flag; - } else if (onoff(sw, "-inhibit-sim", flag /*ref*/)) { - fl->v3warn(DEPRECATED, "-inhibit-sim option is deprecated"); - m_inhibitSim = flag; - } else if (onoff(sw, "-lint-only", flag /*ref*/)) { - m_lintOnly = flag; - } else if (onoff(sw, "-main", flag /*ref*/)) { // Undocumented future - m_main = flag; - } else if (!strcmp(sw, "-no-pins64")) { - m_pinsBv = 33; - } else if (onoff(sw, "-order-clock-delay", flag /*ref*/)) { - m_orderClockDly = flag; - } else if (!strcmp(sw, "-pins64")) { - m_pinsBv = 65; - } else if (onoff(sw, "-pins-sc-uint", flag /*ref*/)) { - m_pinsScUint = flag; - if (!m_pinsScBigUint) m_pinsBv = 65; - } else if (onoff(sw, "-pins-sc-biguint", flag /*ref*/)) { - m_pinsScBigUint = flag; - m_pinsBv = 513; - } else if (onoff(sw, "-pins-uint8", flag /*ref*/)) { - m_pinsUint8 = flag; - } else if (onoff(sw, "-pp-comments", flag /*ref*/)) { - m_ppComments = flag; - } else if (!strcmp(sw, "-private")) { - m_public = false; - } else if (onoff(sw, "-prof-cfuncs", flag /*ref*/)) { - m_profCFuncs = flag; - } else if (onoff(sw, "-profile-cfuncs", flag /*ref*/)) { // Undocumented, renamed - m_profCFuncs = flag; - } else if (onoff(sw, "-prof-threads", flag /*ref*/)) { - m_profThreads = flag; - } else if (onoff(sw, "-protect-ids", flag /*ref*/)) { - m_protectIds = flag; - } else if (onoff(sw, "-public", flag /*ref*/)) { - m_public = flag; - } else if (onoff(sw, "-public-flat-rw", flag /*ref*/)) { - m_publicFlatRW = flag; - v3Global.dpi(true); - } else if (!strncmp(sw, "-pvalue+", strlen("-pvalue+"))) { - addParameter(string(sw + strlen("-pvalue+")), false); - } else if (onoff(sw, "-quiet-exit", flag /*ref*/)) { - m_quietExit = flag; - } else if (onoff(sw, "-relative-cfuncs", flag /*ref*/)) { - m_relativeCFuncs = flag; - if (!m_relativeCFuncs) - fl->v3warn(DEPRECATED, - "Deprecated --no-relative-cfuncs, unnecessary with C++11."); - } else if (onoff(sw, "-relative-includes", flag /*ref*/)) { - m_relativeIncludes = flag; - } else if (onoff(sw, "-report-unoptflat", flag /*ref*/)) { - m_reportUnoptflat = flag; - } else if (onoff(sw, "-savable", flag /*ref*/)) { - m_savable = flag; - } else if (!strcmp(sw, "-sc")) { - m_outFormatOk = true; - m_systemC = true; - } else if (onoffb(sw, "-skip-identical", bflag /*ref*/)) { - m_skipIdentical = bflag; - } else if (onoff(sw, "-stats", flag /*ref*/)) { - m_stats = flag; - } else if (onoff(sw, "-stats-vars", flag /*ref*/)) { - m_statsVars = flag; - m_stats |= flag; - } else if (onoff(sw, "-structs-unpacked", flag /*ref*/)) { - m_structsPacked = flag; - } else if (!strcmp(sw, "-sv")) { - m_defaultLanguage = V3LangCode::L1800_2017; - } else if (onoff(sw, "-threads-coarsen", flag /*ref*/)) { // Undocumented, debug - m_threadsCoarsen = flag; - } else if (onoff(sw, "-trace", flag /*ref*/)) { - m_trace = flag; - } else if (onoff(sw, "-trace-coverage", flag /*ref*/)) { - m_traceCoverage = flag; - } else if (onoff(sw, "-trace-params", flag /*ref*/)) { - m_traceParams = flag; - } else if (onoff(sw, "-trace-structs", flag /*ref*/)) { - m_traceStructs = flag; - } else if (onoff(sw, "-trace-underscore", flag /*ref*/)) { - m_traceUnderscore = flag; - } else if (onoff(sw, "-underline-zero", flag /*ref*/)) { // Deprecated - m_underlineZero = flag; - } else if (onoff(sw, "-verilate", flag /*ref*/)) { - m_verilate = flag; - } else if (onoff(sw, "-vpi", flag /*ref*/)) { - m_vpi = flag; - } else if (onoff(sw, "-Wpedantic", flag /*ref*/)) { - m_pedantic = flag; - } else if (onoff(sw, "-x-initial-edge", flag /*ref*/)) { - m_xInitialEdge = flag; - } else if (onoff(sw, "-xml-only", flag /*ref*/)) { - m_xmlOnly = flag; - } else { - hadSwitchPart1 = false; - } - - if (hadSwitchPart1) { - } else if (!strncmp(sw, "-O", 2)) { - // Optimization - for (const char* cp = sw + strlen("-O"); *cp; ++cp) { - flag = isupper(*cp); - switch (tolower(*cp)) { - case '0': optimize(0); break; // 0=all off - case '1': optimize(1); break; // 1=all on - case '2': optimize(2); break; // 2=not used - case '3': optimize(3); break; // 3=high - case 'a': m_oTable = flag; break; - case 'b': m_oCombine = flag; break; - case 'c': m_oConst = flag; break; - case 'd': m_oDedupe = flag; break; - case 'e': m_oCase = flag; break; - // f - case 'g': m_oGate = flag; break; - // h - case 'i': m_oInline = flag; break; - // j - case 'k': m_oSubstConst = flag; break; - case 'l': m_oLife = flag; break; - case 'm': m_oAssemble = flag; break; - // n - case 'o': m_oConstBitOpTree = flag; break; // Can remove ~2022-01 when stable - case 'p': - m_public = !flag; - break; // With -Op so flag=0, we want public on so few optimizations done - // q - case 'r': m_oReorder = flag; break; - case 's': m_oSplit = flag; break; - case 't': m_oLifePost = flag; break; - case 'u': m_oSubst = flag; break; - case 'v': m_oReloop = flag; break; - case 'w': m_oMergeCond = flag; break; - case 'x': m_oExpand = flag; break; - case 'y': m_oAcycSimp = flag; break; - case 'z': m_oLocalize = flag; break; - default: break; // No error, just ignore - } - } - } - // Parameterized switches - else if (!strcmp(sw, "-CFLAGS") && (i + 1) < argc) { - shift; - addCFlags(argv[i]); - } else if (!strcmp(sw, "-comp-limit-blocks") && (i + 1) < argc) { // Undocumented - shift; - m_compLimitBlocks = atoi(argv[i]); - } else if (!strcmp(sw, "-comp-limit-members") && (i + 1) < argc) { // Undocumented - shift; - m_compLimitMembers - = atoi(argv[i]); // Ideally power-of-two so structs stay aligned - } else if (!strcmp(sw, "-comp-limit-parens") && (i + 1) < argc) { // Undocumented - shift; - m_compLimitParens = atoi(argv[i]); - } else if (!strcmp(sw, "-comp-limit-syms") && (i + 1) < argc) { // Undocumented - shift; - VName::maxLength(atoi(argv[i])); - } else if (!strcmp(sw, "-converge-limit") && (i + 1) < argc) { - shift; - m_convergeLimit = atoi(argv[i]); - } else if (!strncmp(sw, "-D", 2)) { - addDefine(string(sw + strlen("-D")), false); - } else if (!strcmp(sw, "-debug")) { - setDebugMode(3); - } else if (!strcmp(sw, "-debugi") && (i + 1) < argc) { - shift; - setDebugMode(atoi(argv[i])); - } else if (!strncmp(sw, "-debugi-", strlen("-debugi-"))) { - const char* src = sw + strlen("-debugi-"); - shift; - setDebugSrcLevel(src, atoi(argv[i])); - } else if (!strcmp(sw, "-dump-treei") && (i + 1) < argc) { - shift; - m_dumpTree = atoi(argv[i]); - } else if (!strncmp(sw, "-dump-treei-", strlen("-dump-treei-"))) { - const char* src = sw + strlen("-dump-treei-"); - shift; - setDumpTreeLevel(src, atoi(argv[i])); - } else if (!strcmp(sw, "-error-limit") && (i + 1) < argc) { - shift; - V3Error::errorLimit(atoi(argv[i])); - } else if (!strcmp(sw, "-FI") && (i + 1) < argc) { - shift; - addForceInc(parseFileArg(optdir, string(argv[i]))); - } else if (!strncmp(sw, "-G", strlen("-G"))) { - addParameter(string(sw + strlen("-G")), false); - } else if (!strcmp(sw, "-gate-stmts") && (i + 1) < argc) { - shift; - m_gateStmts = atoi(argv[i]); - } else if (!strcmp(sw, "-generate-key")) { - cout << protectKeyDefaulted() << endl; - exit(0); - } else if (!strcmp(sw, "-getenv") && (i + 1) < argc) { - shift; - cout << V3Options::getenvBuiltins(argv[i]) << endl; - exit(0); - } else if (!strcmp(sw, "-hierarchical-block") && (i + 1) < argc) { - shift; - V3HierarchicalBlockOption opt(argv[i]); - m_hierBlocks.emplace(opt.mangledName(), opt); - } else if (!strncmp(sw, "-I", 2)) { - addIncDirUser(parseFileArg(optdir, string(sw + strlen("-I")))); - } else if (!strcmp(sw, "-if-depth") && (i + 1) < argc) { - shift; - m_ifDepth = atoi(argv[i]); - } else if (!strcmp(sw, "-inline-mult") && (i + 1) < argc) { - shift; - m_inlineMult = atoi(argv[i]); - } else if (!strcmp(sw, "-j")) { - if ((i + 1) >= argc || !isdigit(argv[i + 1][0])) { // No value is given - m_buildJobs = 0; // Unlimited parallelism - } else { - shift; - m_buildJobs = atoi(argv[i]); - if (m_buildJobs <= 0) { - fl->v3error("-j accepts positive integer, but " << argv[i] - << " is passed"); - } - } - } else if (!strcmp(sw, "-LDFLAGS") && (i + 1) < argc) { - shift; - addLdLibs(argv[i]); - } else if (!strcmp(sw, "-l2-name") && (i + 1) < argc) { - shift; - m_l2Name = argv[i]; - } else if (!strcmp(sw, "-l2name")) { // Historical and undocumented - m_l2Name = "v"; - } else if (!strcmp(sw, "-make")) { - shift; - if (!strcmp(argv[i], "cmake")) { - m_cmake = true; - } else if (!strcmp(argv[i], "gmake")) { - m_gmake = true; - } else { - fl->v3fatal("Unknown --make system specified: '" << argv[i] << "'"); - } - } else if (!strcmp(sw, "-MAKEFLAGS") && (i + 1) < argc) { - shift; - addMakeFlags(argv[i]); - } else if (!strcmp(sw, "-max-num-width")) { - shift; - m_maxNumWidth = atoi(argv[i]); - } else if (!strcmp(sw, "-no-l2name")) { // Historical and undocumented - m_l2Name = ""; - } else if ((!strcmp(sw, "-language") && (i + 1) < argc) - || (!strcmp(sw, "-default-language") && (i + 1) < argc)) { - shift; - V3LangCode optval = V3LangCode(argv[i]); - if (optval.legal()) { - m_defaultLanguage = optval; - } else { - fl->v3fatal("Unknown language specified: " << argv[i]); - } - } else if (!strcmp(sw, "-Mdir") && (i + 1) < argc) { - shift; - m_makeDir = argv[i]; - addIncDirFallback(m_makeDir); // Need to find generated files there too - } else if (!strcmp(sw, "-o") && (i + 1) < argc) { - shift; - m_exeName = argv[i]; - } else if (!strcmp(sw, "-output-split") && (i + 1) < argc) { - shift; - m_outputSplit = atoi(argv[i]); - } else if (!strcmp(sw, "-output-split-cfuncs") && (i + 1) < argc) { - shift; - m_outputSplitCFuncs = atoi(argv[i]); - if (m_outputSplitCFuncs < 0) { - fl->v3error("--output-split-cfuncs must be >= 0: " << argv[i]); - } - } else if (!strcmp(sw, "-output-split-ctrace")) { - shift; - m_outputSplitCTrace = atoi(argv[i]); - if (m_outputSplitCTrace < 0) { - fl->v3error("--output-split-ctrace must be >= 0: " << argv[i]); - } - } else if (!strcmp(sw, "-protect-lib") && (i + 1) < argc) { - shift; - m_protectLib = argv[i]; - m_protectIds = true; - } else if (!strcmp(sw, "-trace-fst")) { - m_trace = true; - m_traceFormat = TraceFormat::FST; - addLdLibs("-lz"); - } else if (!strcmp(sw, "-trace-fst-thread")) { - m_trace = true; - m_traceFormat = TraceFormat::FST; - addLdLibs("-lz"); - fl->v3warn(DEPRECATED, "Option --trace-fst-thread is deprecated. " - "Use --trace-fst with --trace-threads > 0."); - if (m_traceThreads == 0) m_traceThreads = 1; - } else if (!strcmp(sw, "-trace-threads")) { - shift; - m_trace = true; - m_traceThreads = atoi(argv[i]); - if (m_traceThreads < 0) fl->v3fatal("--trace-threads must be >= 0: " << argv[i]); - } else if (!strcmp(sw, "-trace-depth") && (i + 1) < argc) { - shift; - m_traceDepth = atoi(argv[i]); - } else if (!strcmp(sw, "-trace-max-array") && (i + 1) < argc) { - shift; - m_traceMaxArray = atoi(argv[i]); - } else if (!strcmp(sw, "-trace-max-width") && (i + 1) < argc) { - shift; - m_traceMaxWidth = atoi(argv[i]); - } else if (!strncmp(sw, "-U", 2)) { - V3PreShell::undef(string(sw + strlen("-U"))); - } else if (!strcmp(sw, "-unroll-count")) { // Undocumented optimization tweak - shift; - m_unrollCount = atoi(argv[i]); - } else if (!strcmp(sw, "-unroll-stmts")) { // Undocumented optimization tweak - shift; - m_unrollStmts = atoi(argv[i]); - } else if (!strcmp(sw, "-v") && (i + 1) < argc) { - shift; - V3Options::addLibraryFile(parseFileArg(optdir, argv[i])); - } else if (!strcmp(sw, "-clk") && (i + 1) < argc) { - shift; - V3Options::addClocker(argv[i]); - } else if (!strcmp(sw, "-no-clk") && (i + 1) < argc) { - shift; - V3Options::addNoClocker(argv[i]); - } else if (!strcmp(sw, "-V")) { - showVersion(true); - exit(0); - } else if (!strcmp(sw, "-version")) { - showVersion(false); - exit(0); - } else if (!strcmp(sw, "-Wall")) { - FileLine::globalWarnLintOff(false); - FileLine::globalWarnStyleOff(false); - } else if (!strncmp(sw, "-Werror-", strlen("-Werror-"))) { - string msg = sw + strlen("-Werror-"); - V3ErrorCode code(msg.c_str()); - if (code == V3ErrorCode::EC_ERROR) { - if (!isFuture(msg)) fl->v3fatal("Unknown warning specified: " << sw); - } else { - V3Error::pretendError(code, true); - } - } else if (!strncmp(sw, "-Wfuture-", strlen("-Wfuture-"))) { - string msg = sw + strlen("-Wfuture-"); - // Note it may not be a future option, but one that is currently implemented. - addFuture(msg); - } else if (!strncmp(sw, "-Wno-", 5)) { - if (!strcmp(sw, "-Wno-context")) { - m_context = false; - } else if (!strcmp(sw, "-Wno-fatal")) { - V3Error::warnFatal(false); - } else if (!strcmp(sw, "-Wno-lint")) { - FileLine::globalWarnLintOff(true); - FileLine::globalWarnStyleOff(true); - } else if (!strcmp(sw, "-Wno-style")) { - FileLine::globalWarnStyleOff(true); - } else { - string msg = sw + strlen("-Wno-"); - if (!(FileLine::globalWarnOff(msg, true))) { - fl->v3fatal("Unknown warning specified: " << sw); - } - } - } else if (!strncmp(sw, "-Wwarn-", 5)) { - if (!strcmp(sw, "-Wwarn-lint")) { - FileLine::globalWarnLintOff(false); - } else if (!strcmp(sw, "-Wwarn-style")) { - FileLine::globalWarnStyleOff(false); - } else { - string msg = sw + strlen("-Wwarn-"); - V3ErrorCode code(msg.c_str()); - if (code == V3ErrorCode::EC_ERROR) { - if (!isFuture(msg)) fl->v3fatal("Unknown warning specified: " << sw); - } else { - FileLine::globalWarnOff(code, false); - V3Error::pretendError(code, false); - } - } - } else if (!strcmp(sw, "-bin") && (i + 1) < argc) { - shift; - m_bin = argv[i]; - } else if (!strcmp(sw, "-compiler") && (i + 1) < argc) { - shift; - if (!strcmp(argv[i], "clang")) { - m_compLimitBlocks = 80; // limit unknown - m_compLimitMembers = 64; // soft limit, has slowdown bug as of clang++ 3.8 - m_compLimitParens = 80; // limit unknown - } else if (!strcmp(argv[i], "gcc")) { - m_compLimitBlocks = 0; // Bug free - m_compLimitMembers = 64; // soft limit, has slowdown bug as of g++ 7.1 - m_compLimitParens = 0; // Bug free - } else if (!strcmp(argv[i], "msvc")) { - m_compLimitBlocks = 80; // 128, but allow some room - m_compLimitMembers = 0; // probably ok, and AFAIK doesn't support anon structs - m_compLimitParens = 80; // 128, but allow some room - } else { - fl->v3fatal("Unknown setting for --compiler: " << argv[i]); - } - } else if (!strcmp(sw, "-F") && (i + 1) < argc) { - shift; - parseOptsFile(fl, parseFileArg(optdir, argv[i]), true); - } else if (!strcmp(sw, "-f") && (i + 1) < argc) { - shift; - parseOptsFile(fl, parseFileArg(optdir, argv[i]), false); - } else if (!strcmp(sw, "-gdb")) { - // Processed only in bin/verilator shell - } else if (!strcmp(sw, "-waiver-output") && (i + 1) < argc) { - shift; - m_waiverOutput = argv[i]; - } else if (!strcmp(sw, "-rr")) { - // Processed only in bin/verilator shell - } else if (!strcmp(sw, "-gdbbt")) { - // Processed only in bin/verilator shell - } else if (!strcmp(sw, "-mod-prefix") && (i + 1) < argc) { - shift; - m_modPrefix = argv[i]; - } else if (!strcmp(sw, "-pins-bv") && (i + 1) < argc) { - shift; - m_pinsBv = atoi(argv[i]); - if (m_pinsBv > 65) fl->v3fatal("--pins-bv maximum is 65: " << argv[i]); - } else if (!strcmp(sw, "-pipe-filter") && (i + 1) < argc) { - shift; - m_pipeFilter = argv[i]; - } else if (!strcmp(sw, "-prefix") && (i + 1) < argc) { - shift; - m_prefix = argv[i]; - if (m_modPrefix == "") m_modPrefix = m_prefix; - } else if (!strcmp(sw, "-protect-key") && (i + 1) < argc) { - shift; - m_protectKey = argv[i]; - } else if (!strcmp(sw, "-no-threads")) { - m_threads = 0; - } else if (!strcmp(sw, "-threads") && (i + 1) < argc) { - shift; - m_threads = atoi(argv[i]); - if (m_threads < 0) fl->v3fatal("--threads must be >= 0: " << argv[i]); - } else if (!strcmp(sw, "-threads-dpi") && (i + 1) < argc) { - shift; - if (!strcmp(argv[i], "all")) { - m_threadsDpiPure = true; - m_threadsDpiUnpure = true; - } else if (!strcmp(argv[i], "none")) { - m_threadsDpiPure = false; - m_threadsDpiUnpure = false; - } else if (!strcmp(argv[i], "pure")) { - m_threadsDpiPure = true; - m_threadsDpiUnpure = false; - } else { - fl->v3fatal("Unknown setting for --threads-dpi: " << argv[i]); - } - } else if (!strcmp(sw, "-threads-max-mtasks")) { - shift; - m_threadsMaxMTasks = atoi(argv[i]); - if (m_threadsMaxMTasks < 1) - fl->v3fatal("--threads-max-mtasks must be >= 1: " << argv[i]); - } else if (!strcmp(sw, "-timescale") && (i + 1) < argc) { - shift; - VTimescale unit; - VTimescale prec; - VTimescale::parseSlashed(fl, argv[i], unit /*ref*/, prec /*ref*/); - if (!unit.isNone() && timeOverrideUnit().isNone()) m_timeDefaultUnit = unit; - if (!prec.isNone() && timeOverridePrec().isNone()) m_timeDefaultPrec = prec; - } else if (!strcmp(sw, "-timescale-override") && (i + 1) < argc) { - shift; - VTimescale unit; - VTimescale prec; - VTimescale::parseSlashed(fl, argv[i], unit /*ref*/, prec /*ref*/, true); - if (!unit.isNone()) { - m_timeDefaultUnit = unit; - m_timeOverrideUnit = unit; - } - if (!prec.isNone()) { - m_timeDefaultPrec = prec; - m_timeOverridePrec = prec; - } - } else if ((!strcmp(sw, "-top-module") || !strcmp(sw, "-top")) && (i + 1) < argc) { - shift; - m_topModule = argv[i]; - } else if (!strcmp(sw, "-unused-regexp") && (i + 1) < argc) { - shift; - m_unusedRegexp = argv[i]; - } else if (!strcmp(sw, "-x-assign") && (i + 1) < argc) { - shift; - if (!strcmp(argv[i], "0")) { - m_xAssign = "0"; - } else if (!strcmp(argv[i], "1")) { - m_xAssign = "1"; - } else if (!strcmp(argv[i], "fast")) { - m_xAssign = "fast"; - } else if (!strcmp(argv[i], "unique")) { - m_xAssign = "unique"; - } else { - fl->v3fatal("Unknown setting for --x-assign: " << argv[i]); - } - } else if (!strcmp(sw, "-x-initial") && (i + 1) < argc) { - shift; - if (!strcmp(argv[i], "0")) { - m_xInitial = "0"; - } else if (!strcmp(argv[i], "fast")) { - m_xInitial = "fast"; - } else if (!strcmp(argv[i], "unique")) { - m_xInitial = "unique"; - } else { - fl->v3fatal("Unknown setting for --x-initial: " << argv[i]); - } - } else if (!strcmp(sw, "-xml-output") && (i + 1) < argc) { - shift; - m_xmlOutput = argv[i]; - m_xmlOnly = true; - } else if (!strcmp(sw, "-y") && (i + 1) < argc) { - shift; - addIncDirUser(parseFileArg(optdir, string(argv[i]))); - } else { - fl->v3fatal("Invalid option: " << argv[i]); - } - shift; - } // - options - else { + } else { // Filename string filename = parseFileArg(optdir, argv[i]); if (suffixed(filename, ".cpp") // @@ -1569,10 +1697,9 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char } else { V3Options::addVFile(filename); } - shift; + ++i; } } -#undef shift } //====================================================================== diff --git a/src/V3Options.h b/src/V3Options.h index 27c9b0126..ad522f373 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -371,8 +371,6 @@ private: void optimize(int level); void showVersion(bool verbose); void coverage(bool flag) { m_coverageLine = m_coverageToggle = m_coverageUser = flag; } - static bool onoff(const char* sw, const char* arg, bool& flag); - static bool onoffb(const char* sw, const char* arg, VOptionBool& flagr); static bool suffixed(const string& sw, const char* arg); static string parseFileArg(const string& optdir, const string& relfilename); bool parseLangExt(const char* swp, const char* langswp, const V3LangCode& lc); diff --git a/test_regress/t/t_flag_suggest.out b/test_regress/t/t_flag_suggest.out new file mode 100644 index 000000000..01ad7c7b0 --- /dev/null +++ b/test_regress/t/t_flag_suggest.out @@ -0,0 +1,11 @@ +%Error: Invalid option: -ccc... Suggested alternative: '-cc' +%Error: Invalid option: --ccc... Suggested alternative: '-cc' +%Error: Invalid option: -no-asserT... Suggested alternative: '-no-assert' +%Error: Invalid option: -noasserT... Suggested alternative: '-no-assert' +%Error: Invalid option: -asserT... Suggested alternative: '-assert' +%Error: Invalid option: +definE+A=B... Suggested alternative: '+define+' +%Error: Invalid option: -CFLAGs... Suggested alternative: '-CFLAGS' +%Error: Invalid option: -debug-aborT +%Error: Invalid option: -Won-SPLITVAR... Suggested alternative: '-Wno-SPLITVAR' +%Error: Unknown warning specified: -Wno-SPLITVER... Suggested alternative: '-Wno-SPLITVAR' +%Error: Unknown language specified: 1364-1997... Suggested alternative: '1364-1995' diff --git a/test_regress/t/t_flag_suggest.pl b/test_regress/t/t_flag_suggest.pl new file mode 100755 index 000000000..1022af5ff --- /dev/null +++ b/test_regress/t/t_flag_suggest.pl @@ -0,0 +1,51 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +my @opts; +# Typo +push @opts, "-ccc"; +# Typo of an option that starts with "--" +push @opts, "--ccc"; +# Typo of an option that starts with "-no-" +push @opts, "-no-asserT"; +# Typo of an option that starts with "-no" +push @opts, "-noasserT"; +# Typo of an option that allows "-no" +push @opts, "-asserT"; +# Typo of an option that starts with '+' +push @opts, "+definE+A=B"; +# Typo that takes arg +push @opts, "-CFLAGs -ggdb"; +# Typo of an undocumented option +push @opts, "-debug-aborT"; +# Typo of "-Wno" for partial match +push @opts, "-Won-SPLITVAR"; +# Typo after -Wno- for partial match +push @opts, "-Wno-SPLITVER"; +# Typo of -language +push @opts, "-language 1364-1997"; + +my $cmd = ""; + +foreach my $var (@opts) { + $cmd = $cmd . $ENV{VERILATOR_ROOT} . "/bin/verilator ${var}; "; +} + +run(cmd => [$cmd], + verilator_run => 1, + logfile => "$Self->{obj_dir}/sim.log", + fails => 1, + expect_filename => $Self->{golden_filename}, +); + +ok(1); +1; From 87728a9ee30540087ff49abf5ffd066d029e4ade Mon Sep 17 00:00:00 2001 From: Todd Strader Date: Fri, 26 Mar 2021 18:24:31 -0400 Subject: [PATCH 041/110] Fix --public-flat-rw / DPI issue (#2858) --- src/V3EmitCSyms.cpp | 3 ++- test_regress/t/t_vpi_get.cpp | 2 ++ test_regress/t/t_vpi_get.v | 3 +++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index fa7df71fc..a389d6a7b 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -330,7 +330,8 @@ class EmitCSyms final : EmitCBaseVisitor { virtual void visit(AstVar* nodep) override { nameCheck(nodep); iterateChildren(nodep); - if (nodep->isSigUserRdPublic()) m_modVars.emplace_back(std::make_pair(m_modp, nodep)); + if (nodep->isSigUserRdPublic() && !m_cfuncp) + m_modVars.emplace_back(std::make_pair(m_modp, nodep)); } virtual void visit(AstCoverDecl* nodep) override { // Assign numbers to all bins, so we know how big of an array to use diff --git a/test_regress/t/t_vpi_get.cpp b/test_regress/t/t_vpi_get.cpp index ba97e83fb..b07104480 100644 --- a/test_regress/t/t_vpi_get.cpp +++ b/test_regress/t/t_vpi_get.cpp @@ -202,6 +202,8 @@ int mon_check() { return 0; // Ok } +void dpi_print(const char* somestring) { printf("SOMESTRING = %s\n", somestring); } + //====================================================================== #ifdef IS_VPI diff --git a/test_regress/t/t_vpi_get.v b/test_regress/t/t_vpi_get.v index 93191301c..0782339c1 100644 --- a/test_regress/t/t_vpi_get.v +++ b/test_regress/t/t_vpi_get.v @@ -12,6 +12,8 @@ import "DPI-C" context function int mon_check(); `endif +import "DPI-C" function void dpi_print(input string somestring); + `ifdef VERILATOR_COMMENTS `define PUBLIC_FLAT_RD /*verilator public_flat_rd*/ `define PUBLIC_FLAT_RW /*verilator public_flat_rw @(posedge clk)*/ @@ -54,6 +56,7 @@ extern "C" int mon_check(); // Test loop initial begin + dpi_print("foo"); `ifdef VERILATOR status = $c32("mon_check()"); `endif From ee25114a0070ff575c49c9f195bdbcb50d276214 Mon Sep 17 00:00:00 2001 From: Todd Strader Date: Fri, 26 Mar 2021 18:27:38 -0400 Subject: [PATCH 042/110] interface localparam access (#2859) --- src/V3SymTable.h | 2 +- test_regress/t/t_interface_parameter_access.v | 29 +++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/V3SymTable.h b/src/V3SymTable.h index 12c1e1ba3..085b25e71 100644 --- a/src/V3SymTable.h +++ b/src/V3SymTable.h @@ -249,7 +249,7 @@ public: const string& name = it->first; VSymEnt* subSrcp = it->second; const AstVar* varp = VN_CAST(subSrcp->nodep(), Var); - if (!onlyUnmodportable || (varp && varp->varType() == AstVarType::GPARAM)) { + if (!onlyUnmodportable || (varp && varp->isParam())) { VSymEnt* subSymp = new VSymEnt(graphp, subSrcp); reinsert(name, subSymp); // And recurse to create children diff --git a/test_regress/t/t_interface_parameter_access.v b/test_regress/t/t_interface_parameter_access.v index 3912fd2ff..4bdd8c6ec 100644 --- a/test_regress/t/t_interface_parameter_access.v +++ b/test_regress/t/t_interface_parameter_access.v @@ -11,6 +11,8 @@ interface test_if #(parameter integer FOO = 1); // Interface variable logic data; + localparam integer BAR = FOO + 1; + // Modport modport mp( import getFoo, @@ -76,6 +78,9 @@ module testmod localparam THE_FOO = intf.FOO; localparam THE_OTHER_FOO = intf_no_mp.FOO; localparam THE_ARRAY_FOO = intf_array[0].FOO; + localparam THE_BAR = intf.BAR; + localparam THE_OTHER_BAR = intf_no_mp.BAR; + localparam THE_ARRAY_BAR = intf_array[0].BAR; always @(posedge clk) begin if (THE_FOO != 5) begin @@ -106,6 +111,30 @@ module testmod // $display("%%Error: i.getFoo() = %0d", i.getFoo()); // $stop; // end + if (THE_BAR != 6) begin + $display("%%Error: THE_BAR = %0d", THE_BAR); + $stop; + end + if (THE_OTHER_BAR != 6) begin + $display("%%Error: THE_OTHER_BAR = %0d", THE_OTHER_BAR); + $stop; + end + if (THE_ARRAY_BAR != 8) begin + $display("%%Error: THE_ARRAY_BAR = %0d", THE_ARRAY_BAR); + $stop; + end + if (intf.BAR != 6) begin + $display("%%Error: intf.BAR = %0d", intf.BAR); + $stop; + end + if (intf_no_mp.BAR != 6) begin + $display("%%Error: intf_no_mp.BAR = %0d", intf_no_mp.BAR); + $stop; + end + if (intf_array[0].BAR != 8) begin + $display("%%Error: intf_array[0].BAR = %0d", intf_array[0].BAR); + $stop; + end $write("*-* All Finished *-*\n"); $finish; end From ca01d6f18ded1848a0bc3cbd99b382c081f860c3 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 26 Mar 2021 21:23:18 -0400 Subject: [PATCH 043/110] Internals: Add some std::'s. No functional change intended. --- include/verilated.cpp | 132 ++++++++++++++++---------------- include/verilated_cov.cpp | 12 +-- include/verilated_imp.h | 14 ++-- include/verilated_save.cpp | 16 ++-- include/verilated_threads.cpp | 4 +- include/verilated_trace.h | 2 +- include/verilated_trace_imp.cpp | 4 +- include/verilated_vcd_c.cpp | 22 +++--- include/verilated_vpi.cpp | 26 ++++--- include/verilatedos.h | 10 +-- src/V3AstNodes.h | 40 +++++----- src/V3Error.cpp | 2 +- src/V3Options.cpp | 8 +- src/V3TSP.cpp | 2 +- src/V3Width.cpp | 2 +- src/Verilator.cpp | 8 +- src/VlcMain.cpp | 4 +- 17 files changed, 156 insertions(+), 152 deletions(-) diff --git a/include/verilated.cpp b/include/verilated.cpp index c7cfceecf..025109183 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -105,7 +105,7 @@ void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE "- %s:%d: Second verilog $finish, exiting\n", filename, linenum); Verilated::runFlushCallbacks(); Verilated::runExitCallbacks(); - exit(0); + std::exit(0); } Verilated::threadContextp()->gotFinish(true); } @@ -150,7 +150,7 @@ void vl_fatal(const char* filename, int linenum, const char* hier, const char* m // Callbacks prior to termination Verilated::runExitCallbacks(); - abort(); + std::abort(); } #endif @@ -279,7 +279,7 @@ static vluint32_t vl_sys_rand32() VL_MT_UNSAFE { const VerilatedLockGuard lock(s_mutex); // Otherwise rand is unsafe #if defined(_WIN32) && !defined(__CYGWIN__) // Windows doesn't have lrand48(), although Cygwin does. - return (rand() << 16) ^ rand(); + return (std::rand() << 16) ^ std::rand(); #else return (lrand48() << 16) ^ lrand48(); #endif @@ -581,10 +581,10 @@ double VL_ITOR_D_W(int lbits, WDataInP lwp) VL_PURE { EData ihi = lwp[ms_word]; EData imid = lwp[ms_word - 1]; EData ilo = lwp[ms_word - 2]; - double hi = static_cast(ihi) * exp2(2 * VL_EDATASIZE); - double mid = static_cast(imid) * exp2(VL_EDATASIZE); + double hi = static_cast(ihi) * std::exp2(2 * VL_EDATASIZE); + double mid = static_cast(imid) * std::exp2(VL_EDATASIZE); double lo = static_cast(ilo); - double d = (hi + mid + lo) * exp2(VL_EDATASIZE * (ms_word - 2)); + double d = (hi + mid + lo) * std::exp2(VL_EDATASIZE * (ms_word - 2)); return d; } double VL_ISTOR_D_W(int lbits, WDataInP lwp) VL_PURE { @@ -915,14 +915,14 @@ void _vl_vsformat(std::string& output, const char* formatp, va_list ap) VL_MT_SA static inline bool _vl_vsss_eof(FILE* fp, int floc) VL_MT_SAFE { if (fp) { - return feof(fp) ? true : false; // true : false to prevent MSVC++ warning + return std::feof(fp) ? true : false; // true : false to prevent MSVC++ warning } else { return floc < 0; } } static inline void _vl_vsss_advance(FILE* fp, int& floc) VL_MT_SAFE { if (fp) { - fgetc(fp); + std::fgetc(fp); } else { floc -= 8; } @@ -931,7 +931,7 @@ static inline int _vl_vsss_peek(FILE* fp, int& floc, WDataInP fromp, const std::string& fstr) VL_MT_SAFE { // Get a character without advancing if (fp) { - int data = fgetc(fp); + int data = std::fgetc(fp); if (data == EOF) return EOF; ungetc(data, fp); return data; @@ -949,7 +949,7 @@ static inline void _vl_vsss_skipspace(FILE* fp, int& floc, WDataInP fromp, const std::string& fstr) VL_MT_SAFE { while (true) { int c = _vl_vsss_peek(fp, floc, fromp, fstr); - if (c == EOF || !isspace(c)) return; + if (c == EOF || !std::isspace(c)) return; _vl_vsss_advance(fp, floc); } } @@ -959,9 +959,9 @@ static inline void _vl_vsss_read_str(FILE* fp, int& floc, WDataInP fromp, const char* cp = tmpp; while (true) { int c = _vl_vsss_peek(fp, floc, fromp, fstr); - if (c == EOF || isspace(c)) break; - if (acceptp && nullptr == strchr(acceptp, c)) break; // String - allow anything - if (acceptp) c = tolower(c); // Non-strings we'll simplify + if (c == EOF || std::isspace(c)) break; + if (acceptp && nullptr == std::strchr(acceptp, c)) break; // String - allow anything + if (acceptp) c = std::tolower(c); // Non-strings we'll simplify *cp++ = c; _vl_vsss_advance(fp, floc); } @@ -1037,8 +1037,8 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf if (!inPct && pos[0] == '%') { inPct = true; inIgnore = false; - } else if (!inPct && isspace(pos[0])) { // Format spaces - while (isspace(pos[1])) pos++; + } else if (!inPct && std::isspace(pos[0])) { // Format spaces + while (std::isspace(pos[1])) pos++; _vl_vsss_skipspace(fp, floc, fromp, fstr); } else if (!inPct) { // Expected Format _vl_vsss_skipspace(fp, floc, fromp, fstr); @@ -1092,7 +1092,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, nullptr); if (!t_tmp[0]) goto done; if (owp) { - int lpos = (static_cast(strlen(t_tmp))) - 1; + int lpos = (static_cast(std::strlen(t_tmp))) - 1; int lsb = 0; for (int i = 0; i < obits && lpos >= 0; --lpos) { _vl_vsss_setbit(owp, obits, lsb, 8, t_tmp[lpos]); @@ -1106,7 +1106,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, "0123456789+-xXzZ?_"); if (!t_tmp[0]) goto done; vlsint64_t ld = 0; - sscanf(t_tmp, "%30" VL_PRI64 "d", &ld); + std::sscanf(t_tmp, "%30" VL_PRI64 "d", &ld); VL_SET_WQ(owp, ld); break; } @@ -1121,7 +1121,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf double r; vlsint64_t ld; } u; - u.r = strtod(t_tmp, nullptr); + u.r = std::strtod(t_tmp, nullptr); VL_SET_WQ(owp, u.ld); break; } @@ -1131,7 +1131,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, "0123456789+-xXzZ?_"); if (!t_tmp[0]) goto done; QData ld = 0; - sscanf(t_tmp, "%30" VL_PRI64 "u", &ld); + std::sscanf(t_tmp, "%30" VL_PRI64 "u", &ld); VL_SET_WQ(owp, ld); break; } @@ -1139,14 +1139,14 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, "01xXzZ?_"); if (!t_tmp[0]) goto done; - _vl_vsss_based(owp, obits, 1, t_tmp, 0, strlen(t_tmp)); + _vl_vsss_based(owp, obits, 1, t_tmp, 0, std::strlen(t_tmp)); break; } case 'o': { _vl_vsss_skipspace(fp, floc, fromp, fstr); _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, "01234567xXzZ?_"); if (!t_tmp[0]) goto done; - _vl_vsss_based(owp, obits, 3, t_tmp, 0, strlen(t_tmp)); + _vl_vsss_based(owp, obits, 3, t_tmp, 0, std::strlen(t_tmp)); break; } case 'x': { @@ -1154,7 +1154,7 @@ IData _vl_vsscanf(FILE* fp, // If a fscanf _vl_vsss_read_str(fp, floc, fromp, fstr, t_tmp, "0123456789abcdefABCDEFxXzZ?_"); if (!t_tmp[0]) goto done; - _vl_vsss_based(owp, obits, 4, t_tmp, 0, strlen(t_tmp)); + _vl_vsss_based(owp, obits, 4, t_tmp, 0, std::strlen(t_tmp)); break; } case 'u': { @@ -1242,7 +1242,7 @@ void _vl_vint_to_string(int obits, char* destoutp, WDataInP sourcep) VL_MT_SAFE } *destp = '\0'; // Terminate if (!start) { // Drop trailing spaces - while (isspace(*(destp - 1)) && destp > destoutp) *--destp = '\0'; + while (std::isspace(*(destp - 1)) && destp > destoutp) *--destp = '\0'; } } @@ -1297,7 +1297,7 @@ IData VL_FGETS_NI(std::string& dest, IData fpi) VL_MT_SAFE { IData VL_FERROR_IN(IData, std::string& outputr) VL_MT_SAFE { // We ignore lhs/fpi - IEEE says "most recent error" so probably good enough IData ret = errno; - outputr = std::string(::strerror(ret)); + outputr = std::string(::std::strerror(ret)); return ret; } @@ -1479,7 +1479,7 @@ IData VL_FREAD_I(int width, int array_lsb, int array_size, void* memp, IData fpi // We process a character at a time, as then we don't need to deal // with changing buffer sizes dynamically, etc. while (true) { - int c = fgetc(fp); + int c = std::fgetc(fp); if (VL_UNLIKELY(c == EOF)) break; // Shift value in IData entry = read_elements + start - array_lsb; @@ -1524,7 +1524,7 @@ IData VL_SYSTEM_IQ(QData lhs) VL_MT_SAFE { IData VL_SYSTEM_IW(int lhswords, WDataInP lhsp) VL_MT_SAFE { char filenamez[VL_TO_STRING_MAX_WORDS * VL_EDATASIZE + 1]; _vl_vint_to_string(lhswords * VL_EDATASIZE, filenamez, lhsp); - int code = system(filenamez); // Yes, system() is threadsafe + int code = std::system(filenamez); // Yes, std::system() is threadsafe return code >> 8; // Want exit status } @@ -1544,7 +1544,7 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M } else if (!inPct) { // Normal text prefix += *posp; } else { // Format character - switch (tolower(*posp)) { + switch (std::tolower(*posp)) { case '%': prefix += *posp; inPct = false; @@ -1562,20 +1562,20 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M if (match.empty()) return 0; VL_ZERO_RESET_W(rbits, rwp); - switch (tolower(fmt)) { + switch (std::tolower(fmt)) { case 'd': { vlsint64_t lld = 0; - sscanf(dp, "%30" VL_PRI64 "d", &lld); + std::sscanf(dp, "%30" VL_PRI64 "d", &lld); VL_SET_WQ(rwp, lld); break; } - case 'b': _vl_vsss_based(rwp, rbits, 1, dp, 0, strlen(dp)); break; - case 'o': _vl_vsss_based(rwp, rbits, 3, dp, 0, strlen(dp)); break; + case 'b': _vl_vsss_based(rwp, rbits, 1, dp, 0, std::strlen(dp)); break; + case 'o': _vl_vsss_based(rwp, rbits, 3, dp, 0, std::strlen(dp)); break; case 'h': // FALLTHRU - case 'x': _vl_vsss_based(rwp, rbits, 4, dp, 0, strlen(dp)); break; + case 'x': _vl_vsss_based(rwp, rbits, 4, dp, 0, std::strlen(dp)); break; case 's': { // string/no conversion - for (int i = 0, lsb = 0, posp = static_cast(strlen(dp)) - 1; i < rbits && posp >= 0; - --posp) { + for (int i = 0, lsb = 0, posp = static_cast(std::strlen(dp)) - 1; + i < rbits && posp >= 0; --posp) { _vl_vsss_setbit(rwp, rbits, lsb, 8, dp[posp]); lsb += 8; } @@ -1583,19 +1583,19 @@ IData VL_VALUEPLUSARGS_INW(int rbits, const std::string& ld, WDataOutP rwp) VL_M } case 'e': { double temp = 0.F; - sscanf(dp, "%le", &temp); + std::sscanf(dp, "%le", &temp); VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); break; } case 'f': { double temp = 0.F; - sscanf(dp, "%lf", &temp); + std::sscanf(dp, "%lf", &temp); VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); break; } case 'g': { double temp = 0.F; - sscanf(dp, "%lg", &temp); + std::sscanf(dp, "%lg", &temp); VL_SET_WQ(rwp, VL_CVT_Q_D(temp)); break; } @@ -1615,7 +1615,7 @@ IData VL_VALUEPLUSARGS_INN(int, const std::string& ld, std::string& rdr) VL_MT_S } else if (!inPct) { // Normal text prefix += *posp; } else { // Format character - switch (tolower(*posp)) { + switch (std::tolower(*posp)) { case '%': prefix += *posp; inPct = false; @@ -1638,7 +1638,7 @@ const char* vl_mc_scan_plusargs(const char* prefixp) VL_MT_SAFE { static VL_THREAD_LOCAL char t_outstr[VL_VALUE_STRING_MAX_WIDTH]; if (match.empty()) return nullptr; char* dp = t_outstr; - for (const char* sp = match.c_str() + strlen(prefixp) + 1; // +1 to skip the "+" + for (const char* sp = match.c_str() + std::strlen(prefixp) + 1; // +1 to skip the "+" *sp && (dp - t_outstr) < (VL_VALUE_STRING_MAX_WIDTH - 2);) *dp++ = *sp++; *dp++ = '\0'; @@ -1658,12 +1658,12 @@ std::string VL_TO_STRING_W(int words, WDataInP obj) { std::string VL_TOLOWER_NN(const std::string& ld) VL_MT_SAFE { std::string out = ld; - for (auto& cr : out) cr = tolower(cr); + for (auto& cr : out) cr = std::tolower(cr); return out; } std::string VL_TOUPPER_NN(const std::string& ld) VL_MT_SAFE { std::string out = ld; - for (auto& cr : out) cr = toupper(cr); + for (auto& cr : out) cr = std::toupper(cr); return out; } @@ -1763,7 +1763,7 @@ VlReadMem::VlReadMem(bool hex, int bits, const std::string& filename, QData star , m_end{end} , m_addr{start} , m_linenum{0} { - m_fp = fopen(filename.c_str(), "r"); + m_fp = std::fopen(filename.c_str(), "r"); if (VL_UNLIKELY(!m_fp)) { // We don't report the Verilog source filename as it slow to have to pass it down VL_FATAL_MT(filename.c_str(), 0, "", "$readmem file not found"); @@ -1773,7 +1773,7 @@ VlReadMem::VlReadMem(bool hex, int bits, const std::string& filename, QData star } VlReadMem::~VlReadMem() { if (m_fp) { - fclose(m_fp); + std::fclose(m_fp); m_fp = nullptr; } } @@ -1790,13 +1790,13 @@ bool VlReadMem::get(QData& addrr, std::string& valuer) { // We process a character at a time, as then we don't need to deal // with changing buffer sizes dynamically, etc. while (true) { - int c = fgetc(m_fp); + int c = std::fgetc(m_fp); if (VL_UNLIKELY(c == EOF)) break; // printf("%d: Got '%c' Addr%lx IN%d IgE%d IgC%d\n", // m_linenum, c, m_addr, indata, ignore_to_eol, ignore_to_cmt); // See if previous data value has completed, and if so return if (c == '_') continue; // Ignore _ e.g. inside a number - if (indata && !isxdigit(c) && c != 'x' && c != 'X') { + if (indata && !std::isxdigit(c) && c != 'x' && c != 'X') { // printf("Got data @%lx = %s\n", m_addr, valuer.c_str()); ungetc(c, m_fp); addrr = m_addr; @@ -1828,8 +1828,8 @@ bool VlReadMem::get(QData& addrr, std::string& valuer) { m_addr = 0; } // Check for hex or binary digits as file format requests - else if (isxdigit(c) || (!reading_addr && (c == 'x' || c == 'X'))) { - c = tolower(c); + else if (std::isxdigit(c) || (!reading_addr && (c == 'x' || c == 'X'))) { + c = std::tolower(c); int value = (c >= 'a' ? (c == 'x' ? VL_RAND_RESET_I(4) : (c - 'a' + 10)) : (c - '0')); if (reading_addr) { @@ -1863,7 +1863,7 @@ void VlReadMem::setData(void* valuep, const std::string& rhs) { bool innum = false; // Shift value in for (const auto& i : rhs) { - char c = tolower(i); + char c = std::tolower(i); int value = (c >= 'a' ? (c == 'x' ? VL_RAND_RESET_I(4) : (c - 'a' + 10)) : (c - '0')); if (m_bits <= 8) { CData* datap = reinterpret_cast(valuep); @@ -1901,7 +1901,7 @@ VlWriteMem::VlWriteMem(bool hex, int bits, const std::string& filename, QData st return; } - m_fp = fopen(filename.c_str(), "w"); + m_fp = std::fopen(filename.c_str(), "w"); if (VL_UNLIKELY(!m_fp)) { VL_FATAL_MT(filename.c_str(), 0, "", "$writemem file not found"); // cppcheck-suppress resourceLeak // m_fp is nullptr - bug in cppcheck @@ -1910,7 +1910,7 @@ VlWriteMem::VlWriteMem(bool hex, int bits, const std::string& filename, QData st } VlWriteMem::~VlWriteMem() { if (m_fp) { - fclose(m_fp); + std::fclose(m_fp); m_fp = nullptr; } } @@ -2355,7 +2355,7 @@ std::string VerilatedContextImp::argPlusMatch(const char* prefixp) VL_MT_SAFE_EXCLUDES(m_argMutex) { const VerilatedLockGuard lock(m_argMutex); // Note prefixp does not include the leading "+" - size_t len = strlen(prefixp); + size_t len = std::strlen(prefixp); if (VL_UNLIKELY(!m_args.m_argVecLoaded)) { m_args.m_argVecLoaded = true; // Complain only once VL_FATAL_MT("unknown", 0, "", @@ -2364,7 +2364,7 @@ std::string VerilatedContextImp::argPlusMatch(const char* prefixp) } for (const auto& i : m_args.m_argVec) { if (i[0] == '+') { - if (0 == strncmp(prefixp, i.c_str() + 1, len)) return i; + if (0 == std::strncmp(prefixp, i.c_str() + 1, len)) return i; } } return ""; @@ -2383,7 +2383,7 @@ std::pair VerilatedContextImp::argc_argv() VL_MT_SAFE_EXCLUDES(m_ar int in = 0; for (const auto& i : m_args.m_argVec) { s_argvp[in] = new char[i.length() + 1]; - strcpy(s_argvp[in], i.c_str()); + std::strcpy(s_argvp[in], i.c_str()); ++in; } s_argvp[s_argc] = nullptr; @@ -2392,14 +2392,14 @@ std::pair VerilatedContextImp::argc_argv() VL_MT_SAFE_EXCLUDES(m_ar } void VerilatedContextImp::commandArgVl(const std::string& arg) { - if (0 == strncmp(arg.c_str(), "+verilator+", strlen("+verilator+"))) { + if (0 == std::strncmp(arg.c_str(), "+verilator+", std::strlen("+verilator+"))) { std::string value; if (arg == "+verilator+debug") { Verilated::debug(4); } else if (commandArgVlValue(arg, "+verilator+debugi+", value /*ref*/)) { - Verilated::debug(atoi(value.c_str())); + Verilated::debug(std::atoi(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+error+limit+", value /*ref*/)) { - errorLimit(atoi(value.c_str())); + errorLimit(std::atoi(value.c_str())); } else if (arg == "+verilator+help") { VerilatedImp::versionDump(); VL_PRINTF_MT("For help, please see 'verilator --help'\n"); @@ -2408,15 +2408,15 @@ void VerilatedContextImp::commandArgVl(const std::string& arg) { } else if (arg == "+verilator+noassert") { assertOn(false); } else if (commandArgVlValue(arg, "+verilator+prof+threads+start+", value /*ref*/)) { - profThreadsStart(atoll(value.c_str())); + profThreadsStart(std::atoll(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+prof+threads+window+", value /*ref*/)) { - profThreadsWindow(atol(value.c_str())); + profThreadsWindow(std::atol(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+prof+threads+file+", value /*ref*/)) { profThreadsFilename(value); } else if (commandArgVlValue(arg, "+verilator+rand+reset+", value /*ref*/)) { - randReset(atoi(value.c_str())); + randReset(std::atoi(value.c_str())); } else if (commandArgVlValue(arg, "+verilator+seed+", value /*ref*/)) { - randSeed(atoi(value.c_str())); + randSeed(std::atoi(value.c_str())); } else if (arg == "+verilator+V") { VerilatedImp::versionDump(); // Someday more info too VL_FATAL_MT("COMMAND_LINE", 0, "", @@ -2433,7 +2433,7 @@ void VerilatedContextImp::commandArgVl(const std::string& arg) { bool VerilatedContextImp::commandArgVlValue(const std::string& arg, const std::string& prefix, std::string& valuer) { size_t len = prefix.length(); - if (0 == strncmp(prefix.c_str(), arg.c_str(), len)) { + if (0 == std::strncmp(prefix.c_str(), arg.c_str(), len)) { valuer = arg.substr(len); return true; } else { @@ -2543,7 +2543,7 @@ const char* Verilated::catName(const char* n1, const char* n2, const char* delim // Used by symbol table creation to make module names static VL_THREAD_LOCAL char* t_strp = nullptr; static VL_THREAD_LOCAL size_t t_len = 0; - size_t newlen = strlen(n1) + strlen(n2) + strlen(delimiter) + 1; + size_t newlen = std::strlen(n1) + std::strlen(n2) + std::strlen(delimiter) + 1; if (VL_UNLIKELY(!t_strp || newlen > t_len)) { if (t_strp) delete[] t_strp; t_strp = new char[newlen]; @@ -2603,8 +2603,8 @@ void Verilated::runFlushCallbacks() VL_MT_SAFE { runCallbacks(VlCbStatic.s_flushCbs); } --s_recursing; - fflush(stderr); - fflush(stdout); + std::fflush(stderr); + std::fflush(stdout); // When running internal code coverage (gcc --coverage, as opposed to // verilator --coverage), dump coverage data to properly cover failing // tests. @@ -2760,7 +2760,7 @@ void VerilatedScope::configure(VerilatedSyms* symsp, const char* prefixp, const m_type = type; m_timeunit = timeunit; { - char* namep = new char[strlen(prefixp) + strlen(suffixp) + 2]; + char* namep = new char[std::strlen(prefixp) + std::strlen(suffixp) + 2]; char* dp = namep; for (const char* sp = prefixp; *sp;) *dp++ = *sp++; if (*prefixp && *suffixp) *dp++ = '.'; @@ -2787,7 +2787,7 @@ void VerilatedScope::exportInsert(int finalize, const char* namep, void* cb) VL_ } if (VL_UNLIKELY(!m_callbacksp)) { // First allocation m_callbacksp = new void*[m_funcnumMax]; - memset(m_callbacksp, 0, m_funcnumMax * sizeof(void*)); + std::memset(m_callbacksp, 0, m_funcnumMax * sizeof(void*)); } m_callbacksp[funcnum] = cb; } diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index 9d52259e1..c69a8c67f 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -142,7 +142,7 @@ private: // Quote any special characters std::string rtn; for (const char* pos = text.c_str(); *pos; ++pos) { - if (!isprint(*pos) || *pos == '%' || *pos == '"') { + if (!std::isprint(*pos) || *pos == '%' || *pos == '"') { char hex[10]; VL_SNPRINTF(hex, 10, "%%%02X", pos[0]); rtn += hex; @@ -158,13 +158,13 @@ private: // a letter differently, nor want them to rely on our compression... // (Considered using numeric keys, but will remain back compatible.) if (key.length() < 2) return false; - if (key.length() == 2 && isdigit(key[1])) return false; + if (key.length() == 2 && std::isdigit(key[1])) return false; return true; } static std::string keyValueFormatter(const std::string& key, const std::string& value) VL_PURE { std::string name; - if (key.length() == 1 && isalpha(key[0])) { + if (key.length() == 1 && std::isalpha(key[0])) { name += std::string("\001") + key; } else { name += std::string("\001") + dequote(key); @@ -196,8 +196,8 @@ private: std::string prefix = std::string(a, apre - a); // Scan backward to last mismatch - const char* apost = a + strlen(a) - 1; - const char* bpost = b + strlen(b) - 1; + const char* apost = a + std::strlen(a) - 1; + const char* bpost = b + std::strlen(b) - 1; while (*apost == *bpost && apost > apre && bpost > bpre) { apost--; bpost--; @@ -305,7 +305,7 @@ public: valps[1] = linestr.c_str(); // Default page if not specified const char* fnstartp = m_insertFilenamep; - while (const char* foundp = strchr(fnstartp, '/')) fnstartp = foundp + 1; + while (const char* foundp = std::strchr(fnstartp, '/')) fnstartp = foundp + 1; const char* fnendp = fnstartp; for (; *fnendp && *fnendp != '.'; fnendp++) {} std::string page_default = "sp_user/" + std::string(fnstartp, fnendp - fnstartp); diff --git a/include/verilated_imp.h b/include/verilated_imp.h index 3cf36bf0e..e49db308f 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -280,12 +280,12 @@ public: // But only for verilated*.cpp if (m_fdFreeMct.empty()) return 0; IData idx = m_fdFreeMct.back(); m_fdFreeMct.pop_back(); - m_fdps[idx] = fopen(filenamep, "w"); + m_fdps[idx] = std::fopen(filenamep, "w"); if (VL_UNLIKELY(!m_fdps[idx])) return 0; return (1 << idx); } IData fdNew(const char* filenamep, const char* modep) VL_MT_SAFE_EXCLUDES(m_fdMutex) { - FILE* fp = fopen(filenamep, modep); + FILE* fp = std::fopen(filenamep, modep); if (VL_UNLIKELY(!fp)) return 0; // Bit 31 indicates it's a descriptor not a MCD const VerilatedLockGuard lock(m_fdMutex); @@ -308,20 +308,20 @@ public: // But only for verilated*.cpp void fdFlush(IData fdi) VL_MT_SAFE_EXCLUDES(m_fdMutex) { const VerilatedLockGuard lock(m_fdMutex); const VerilatedFpList fdlist = fdToFpList(fdi); - for (const auto& i : fdlist) fflush(i); + for (const auto& i : fdlist) std::fflush(i); } IData fdSeek(IData fdi, IData offset, IData origin) VL_MT_SAFE_EXCLUDES(m_fdMutex) { const VerilatedLockGuard lock(m_fdMutex); const VerilatedFpList fdlist = fdToFpList(fdi); if (VL_UNLIKELY(fdlist.size() != 1)) return 0; return static_cast( - fseek(*fdlist.begin(), static_cast(offset), static_cast(origin))); + std::fseek(*fdlist.begin(), static_cast(offset), static_cast(origin))); } IData fdTell(IData fdi) VL_MT_SAFE_EXCLUDES(m_fdMutex) { const VerilatedLockGuard lock(m_fdMutex); const VerilatedFpList fdlist = fdToFpList(fdi); if (VL_UNLIKELY(fdlist.size() != 1)) return 0; - return static_cast(ftell(*fdlist.begin())); + return static_cast(std::ftell(*fdlist.begin())); } void fdWrite(IData fdi, const std::string& output) VL_MT_SAFE_EXCLUDES(m_fdMutex) { const VerilatedLockGuard lock(m_fdMutex); @@ -338,14 +338,14 @@ public: // But only for verilated*.cpp IData idx = VL_MASK_I(31) & fdi; if (VL_UNLIKELY(idx >= m_fdps.size())) return; if (VL_UNLIKELY(!m_fdps[idx])) return; // Already free - fclose(m_fdps[idx]); + std::fclose(m_fdps[idx]); m_fdps[idx] = (FILE*)0; m_fdFree.push_back(idx); } else { // MCD case for (int i = 0; (fdi != 0) && (i < 31); i++, fdi >>= 1) { if (fdi & VL_MASK_I(1)) { - fclose(m_fdps[i]); + std::fclose(m_fdps[i]); m_fdps[i] = nullptr; m_fdFreeMct.push_back(i); } diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp index 67f8f3a7d..257a1f1f0 100644 --- a/include/verilated_save.cpp +++ b/include/verilated_save.cpp @@ -83,13 +83,13 @@ VerilatedDeserialize& VerilatedDeserialize::readAssert(const void* __restrict da void VerilatedSerialize::header() VL_MT_UNSAFE_ONE { VerilatedSerialize& os = *this; // So can cut and paste standard << code below - assert((strlen(VLTSAVE_HEADER_STR) & 7) == 0); // Keep aligned - os.write(VLTSAVE_HEADER_STR, strlen(VLTSAVE_HEADER_STR)); + assert((std::strlen(VLTSAVE_HEADER_STR) & 7) == 0); // Keep aligned + os.write(VLTSAVE_HEADER_STR, std::strlen(VLTSAVE_HEADER_STR)); } void VerilatedDeserialize::header() VL_MT_UNSAFE_ONE { VerilatedDeserialize& os = *this; // So can cut and paste standard >> code below - if (VL_UNLIKELY(os.readDiffers(VLTSAVE_HEADER_STR, strlen(VLTSAVE_HEADER_STR)))) { + if (VL_UNLIKELY(os.readDiffers(VLTSAVE_HEADER_STR, std::strlen(VLTSAVE_HEADER_STR)))) { std::string fn = filename(); std::string msg = std::string( @@ -102,13 +102,13 @@ void VerilatedDeserialize::header() VL_MT_UNSAFE_ONE { void VerilatedSerialize::trailer() VL_MT_UNSAFE_ONE { VerilatedSerialize& os = *this; // So can cut and paste standard << code below - assert((strlen(VLTSAVE_TRAILER_STR) & 7) == 0); // Keep aligned - os.write(VLTSAVE_TRAILER_STR, strlen(VLTSAVE_TRAILER_STR)); + assert((std::strlen(VLTSAVE_TRAILER_STR) & 7) == 0); // Keep aligned + os.write(VLTSAVE_TRAILER_STR, std::strlen(VLTSAVE_TRAILER_STR)); } void VerilatedDeserialize::trailer() VL_MT_UNSAFE_ONE { VerilatedDeserialize& os = *this; // So can cut and paste standard >> code below - if (VL_UNLIKELY(os.readDiffers(VLTSAVE_TRAILER_STR, strlen(VLTSAVE_TRAILER_STR)))) { + if (VL_UNLIKELY(os.readDiffers(VLTSAVE_TRAILER_STR, std::strlen(VLTSAVE_TRAILER_STR)))) { std::string fn = filename(); std::string msg = std::string("Can't deserialize; file has wrong end-of-file signature: ") + filename(); @@ -202,7 +202,7 @@ void VerilatedSave::flush() VL_MT_UNSAFE_ONE { if (VL_UNCOVERABLE(errno != EAGAIN && errno != EINTR)) { // LCOV_EXCL_START // write failed, presume error (perhaps out of disk space) - std::string msg = std::string(__FUNCTION__) + ": " + strerror(errno); + std::string msg = std::string(__FUNCTION__) + ": " + std::strerror(errno); VL_FATAL_MT("", 0, "", msg.c_str()); close(); break; @@ -233,7 +233,7 @@ void VerilatedRestore::fill() VL_MT_UNSAFE_ONE { if (VL_UNCOVERABLE(errno != EAGAIN && errno != EINTR)) { // LCOV_EXCL_START // write failed, presume error (perhaps out of disk space) - std::string msg = std::string(__FUNCTION__) + ": " + strerror(errno); + std::string msg = std::string(__FUNCTION__) + ": " + std::strerror(errno); VL_FATAL_MT("", 0, "", msg.c_str()); close(); break; diff --git a/include/verilated_threads.cpp b/include/verilated_threads.cpp index aabad76c8..49e2f2624 100644 --- a/include/verilated_threads.cpp +++ b/include/verilated_threads.cpp @@ -149,7 +149,7 @@ void VlThreadPool::profileDump(const char* filenamep, vluint64_t ticksElapsed) const VerilatedLockGuard lk(m_mutex); VL_DEBUG_IF(VL_DBG_MSGF("+prof+threads writing to '%s'\n", filenamep);); - FILE* fp = fopen(filenamep, "w"); + FILE* fp = std::fopen(filenamep, "w"); if (VL_UNLIKELY(!fp)) { VL_FATAL_MT(filenamep, 0, "", "+prof+threads+file file not writable"); // cppcheck-suppress resourceLeak // bug, doesn't realize fp is nullptr @@ -191,5 +191,5 @@ void VlThreadPool::profileDump(const char* filenamep, vluint64_t ticksElapsed) } fprintf(fp, "VLPROF stat ticks %" VL_PRI64 "u\n", ticksElapsed); - fclose(fp); + std::fclose(fp); } diff --git a/include/verilated_trace.h b/include/verilated_trace.h index b0173f7fd..bdfed6f85 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -225,7 +225,7 @@ protected: void declCode(vluint32_t code, vluint32_t bits, bool tri); // Is this an escape? - bool isScopeEscape(char c) { return c != '\f' && (isspace(c) || c == m_scopeEscape); } + bool isScopeEscape(char c) { return c != '\f' && (std::isspace(c) || c == m_scopeEscape); } // Character that splits scopes. Note whitespace are ALWAYS escapes. char scopeEscape() { return m_scopeEscape; } diff --git a/include/verilated_trace_imp.cpp b/include/verilated_trace_imp.cpp index 71d4f5f30..6a31b6cd0 100644 --- a/include/verilated_trace_imp.cpp +++ b/include/verilated_trace_imp.cpp @@ -45,11 +45,11 @@ static double timescaleToDouble(const char* unitp) { char* endp = nullptr; - double value = strtod(unitp, &endp); + double value = std::strtod(unitp, &endp); // On error so we allow just "ns" to return 1e-9. if (value == 0.0 && endp == unitp) value = 1; unitp = endp; - for (; *unitp && isspace(*unitp); unitp++) {} + for (; *unitp && std::isspace(*unitp); unitp++) {} switch (*unitp) { case 's': value *= 1e0; break; case 'm': value *= 1e-3; break; diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index f7a18d138..796e742a1 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -52,7 +52,7 @@ // This size comes form VCD allowing use of printable ASCII characters between // '!' and '~' inclusive, which are a total of 94 different values. Encoding a -// 32 bit code hence needs a maximum of ceil(log94(2**32-1)) == 5 bytes. +// 32 bit code hence needs a maximum of std::ceil(log94(2**32-1)) == 5 bytes. constexpr unsigned VL_TRACE_MAX_VCD_CODE_SIZE = 5; // Maximum length of a VCD string code // We use 8 bytes per code in a suffix buffer array. @@ -134,9 +134,9 @@ void VerilatedVcd::openNextImp(bool incFilename) { // Find _0000.{ext} in filename std::string name = m_filename; size_t pos = name.rfind('.'); - if (pos > 8 && 0 == strncmp("_cat", name.c_str() + pos - 8, 4) - && isdigit(name.c_str()[pos - 4]) && isdigit(name.c_str()[pos - 3]) - && isdigit(name.c_str()[pos - 2]) && isdigit(name.c_str()[pos - 1])) { + if (pos > 8 && 0 == std::strncmp("_cat", name.c_str() + pos - 8, 4) + && std::isdigit(name.c_str()[pos - 4]) && std::isdigit(name.c_str()[pos - 3]) + && std::isdigit(name.c_str()[pos - 2]) && std::isdigit(name.c_str()[pos - 1])) { // Increment code. if ((++(name[pos - 1])) > '9') { name[pos - 1] = '0'; @@ -287,7 +287,7 @@ void VerilatedVcd::bufferResize(vluint64_t minsize) { char* oldbufp = m_wrBufp; m_wrChunkSize = minsize * 2; m_wrBufp = new char[m_wrChunkSize * 8]; - memcpy(m_wrBufp, oldbufp, m_writep - oldbufp); + std::memcpy(m_wrBufp, oldbufp, m_writep - oldbufp); m_writep = m_wrBufp + (m_writep - oldbufp); m_wrFlushp = m_wrBufp + m_wrChunkSize * 6; VL_DO_CLEAR(delete[] oldbufp, oldbufp = nullptr); @@ -314,7 +314,8 @@ void VerilatedVcd::bufferFlush() VL_MT_UNSAFE_ONE { if (VL_UNCOVERABLE(errno != EAGAIN && errno != EINTR)) { // LCOV_EXCL_START // write failed, presume error (perhaps out of disk space) - std::string msg = std::string("VerilatedVcd::bufferFlush: ") + strerror(errno); + std::string msg + = std::string("VerilatedVcd::bufferFlush: ") + std::strerror(errno); VL_FATAL_MT("", 0, "", msg.c_str()); closeErr(); break; @@ -360,7 +361,7 @@ void VerilatedVcd::dumpHeader() { VL_LOCALTIME_R(&tick, &ticktm); constexpr int bufsize = 50; char buf[bufsize]; - strftime(buf, bufsize, "%c", &ticktm); + std::strftime(buf, bufsize, "%c", &ticktm); printStr(buf); } printStr(" $end\n"); @@ -520,7 +521,8 @@ void VerilatedVcd::declare(vluint32_t code, const char* name, const char* wirep, const bool isBit = bits == 1; entryp[0] = ' '; // Separator // Use memcpy as we checked size above, and strcpy is flagged unsafe - std::memcpy(entryp + !isBit, buf, strlen(buf)); // Code (overwrite separator if isBit) + std::memcpy(entryp + !isBit, buf, + std::strlen(buf)); // Code (overwrite separator if isBit) entryp[length + !isBit] = '\n'; // Replace '\0' with line termination '\n' // Set length of suffix (used to increment write pointer) entryp[VL_TRACE_SUFFIX_ENTRY_SIZE - 1] = !isBit + length + 1; @@ -673,7 +675,7 @@ void VerilatedVcd::emitDouble(vluint32_t code, double newval) { char* wp = m_writep; // Buffer can't overflow before VL_SNPRINTF; we sized during declaration VL_SNPRINTF(wp, m_wrChunkSize, "r%.16g", newval); - wp += strlen(wp); + wp += std::strlen(wp); finishLine(code, wp); } @@ -787,7 +789,7 @@ void VerilatedVcd::fullDouble(vluint32_t code, const double newval) { (*(reinterpret_cast(oldp(code)))) = newval; // Buffer can't overflow before VL_SNPRINTF; we sized during declaration VL_SNPRINTF(m_writep, m_wrChunkSize, "r%.16g", newval); - m_writep += strlen(m_writep); + m_writep += std::strlen(m_writep); *m_writep++ = ' '; m_writep = writeCode(m_writep, code); *m_writep++ = '\n'; diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 69c37a876..9901ead6d 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -317,7 +317,7 @@ public: void createPrevDatap() { if (VL_UNLIKELY(!m_prevDatap)) { m_prevDatap = new vluint8_t[entSize()]; - memcpy(prevDatap(), varp()->datap(), entSize()); + std::memcpy(prevDatap(), varp()->datap(), entSize()); } } }; @@ -422,7 +422,7 @@ public: explicit VerilatedVpioModule(const VerilatedScope* modulep) : VerilatedVpioScope{modulep} { m_fullname = m_scopep->name(); - if (strncmp(m_fullname, "TOP.", 4) == 0) m_fullname += 4; + if (std::strncmp(m_fullname, "TOP.", 4) == 0) m_fullname += 4; m_name = m_scopep->identifier(); } static VerilatedVpioModule* castp(vpiHandle h) { @@ -628,7 +628,7 @@ public: VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_test %s v[0]=%d/%d %p %p\n", varop->fullname(), *((CData*)newDatap), *((CData*)prevDatap), newDatap, prevDatap);); - if (memcmp(prevDatap, newDatap, varop->entSize()) != 0) { + if (std::memcmp(prevDatap, newDatap, varop->entSize()) != 0) { VL_DEBUG_IF_PLI(VL_DBG_MSGF("- vpi: value_callback %" VL_PRI64 "d %s v[0]=%d\n", ho.id(), varop->fullname(), *((CData*)newDatap));); @@ -640,7 +640,9 @@ public: } if (was_last) break; } - for (const auto& ip : update) { memcpy(ip->prevDatap(), ip->varDatap(), ip->entSize()); } + for (const auto& ip : update) { + std::memcpy(ip->prevDatap(), ip->varDatap(), ip->entSize()); + } return called; } @@ -1099,7 +1101,7 @@ const char* VerilatedVpiError::strFromVpiProp(PLI_INT32 vpiVal) VL_MT_SAFE { } #define SELF_CHECK_RESULT_CSTR(got, exp) \ - if (0 != strcmp((got), (exp))) { \ + if (0 != std::strcmp((got), (exp))) { \ std::string msg \ = std::string("%Error: ") + "GOT = '" + got + "'" + " EXP = '" + exp + "'"; \ VL_FATAL_MT(__FILE__, __LINE__, "", msg.c_str()); \ @@ -1236,7 +1238,7 @@ vpiHandle vpi_handle_by_name(PLI_BYTE8* namep, vpiHandle scope) { } const char* baseNamep = scopeAndName.c_str(); std::string scopename; - const char* dotp = strrchr(namep, '.'); + const char* dotp = std::strrchr(namep, '.'); if (VL_LIKELY(dotp)) { baseNamep = dotp + 1; scopename = std::string(namep, dotp - namep); @@ -1826,7 +1828,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ } } else if (valuep->format == vpiBinStrVal) { int bits = vop->varp()->packed().elements(); - int len = strlen(valuep->value.str); + int len = std::strlen(valuep->value.str); CData* datap = (reinterpret_cast(vop->varDatap())); for (int i = 0; i < bits; ++i) { char set = (i < len) ? (valuep->value.str[len - i - 1] == '1') : 0; @@ -1842,7 +1844,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ } else if (valuep->format == vpiOctStrVal) { int chars = (vop->varp()->packed().elements() + 2) / 3; int bytes = VL_BYTES_I(vop->varp()->packed().elements()); - int len = strlen(valuep->value.str); + int len = std::strlen(valuep->value.str); CData* datap = (reinterpret_cast(vop->varDatap())); div_t idx; datap[0] = 0; // reset zero'th byte @@ -1892,7 +1894,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ } else if (valuep->format == vpiDecStrVal) { char remainder[16]; unsigned long long val; - int success = sscanf(valuep->value.str, "%30llu%15s", &val, remainder); + int success = std::sscanf(valuep->value.str, "%30llu%15s", &val, remainder); if (success < 1) { VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Parsing failed for '%s' as value %s for %s", VL_FUNC, valuep->value.str, @@ -1925,7 +1927,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ char* val = valuep->value.str; // skip hex ident if one is detected at the start of the string if (val[0] == '0' && (val[1] == 'x' || val[1] == 'X')) val += 2; - int len = strlen(val); + int len = std::strlen(val); for (int i = 0; i < chars; ++i) { char hex; // compute hex digit value @@ -1961,7 +1963,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ return object; } else if (valuep->format == vpiStringVal) { int bytes = VL_BYTES_I(vop->varp()->packed().elements()); - int len = strlen(valuep->value.str); + int len = std::strlen(valuep->value.str); CData* datap = (reinterpret_cast(vop->varDatap())); for (int i = 0; i < bytes; ++i) { // prepend with 0 values before placing string the least significant bytes @@ -2104,7 +2106,7 @@ PLI_INT32 vpi_mcd_flush(PLI_UINT32 mcd) { FILE* fp = VL_CVT_I_FP(mcd); VL_VPI_ERROR_RESET_(); if (VL_UNLIKELY(!fp)) return 1; - fflush(fp); + std::fflush(fp); return 0; } diff --git a/include/verilatedos.h b/include/verilatedos.h index bdc71add4..697e82429 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -240,7 +240,7 @@ extern "C" { void __gcov_flush(); // gcc sources gcc/gcov-io.h has the prototype } -/// Flush internal code coverage data before e.g. abort() +/// Flush internal code coverage data before e.g. std::abort() # define VL_GCOV_FLUSH() \ __gcov_flush() #else @@ -446,11 +446,11 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type // #defines, to avoid requiring math.h on all compile runs #ifdef _MSC_VER -# define VL_TRUNC(n) (((n) < 0) ? ceil((n)) : floor((n))) -# define VL_ROUND(n) (((n) < 0) ? ceil((n)-0.5) : floor((n) + 0.5)) +# define VL_TRUNC(n) (((n) < 0) ? std::ceil((n)) : std::floor((n))) +# define VL_ROUND(n) (((n) < 0) ? std::ceil((n)-0.5) : std::floor((n) + 0.5)) #else -# define VL_TRUNC(n) trunc(n) -# define VL_ROUND(n) round(n) +# define VL_TRUNC(n) std::trunc(n) +# define VL_ROUND(n) std::round(n) #endif //========================================================================= diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index d0b37b1ea..0e621df7f 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -6315,7 +6315,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(LogD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(log(lhs.toDouble())); + out.setDouble(std::log(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$ln(%l)"; } virtual string emitC() override { return "log(%li)"; } @@ -6326,7 +6326,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(Log10D) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(log10(lhs.toDouble())); + out.setDouble(std::log10(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$log10(%l)"; } virtual string emitC() override { return "log10(%li)"; } @@ -6338,7 +6338,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(ExpD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(exp(lhs.toDouble())); + out.setDouble(std::exp(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$exp(%l)"; } virtual string emitC() override { return "exp(%li)"; } @@ -6350,7 +6350,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(SqrtD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(sqrt(lhs.toDouble())); + out.setDouble(std::sqrt(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$sqrt(%l)"; } virtual string emitC() override { return "sqrt(%li)"; } @@ -6362,7 +6362,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(FloorD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(floor(lhs.toDouble())); + out.setDouble(std::floor(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$floor(%l)"; } virtual string emitC() override { return "floor(%li)"; } @@ -6374,7 +6374,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(CeilD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(ceil(lhs.toDouble())); + out.setDouble(std::ceil(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$ceil(%l)"; } virtual string emitC() override { return "ceil(%li)"; } @@ -6386,7 +6386,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(SinD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(sin(lhs.toDouble())); + out.setDouble(std::sin(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$sin(%l)"; } virtual string emitC() override { return "sin(%li)"; } @@ -6398,7 +6398,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(CosD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(cos(lhs.toDouble())); + out.setDouble(std::cos(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$cos(%l)"; } virtual string emitC() override { return "cos(%li)"; } @@ -6410,7 +6410,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(TanD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(tan(lhs.toDouble())); + out.setDouble(std::tan(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$tan(%l)"; } virtual string emitC() override { return "tan(%li)"; } @@ -6422,7 +6422,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(AsinD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(asin(lhs.toDouble())); + out.setDouble(std::asin(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$asin(%l)"; } virtual string emitC() override { return "asin(%li)"; } @@ -6434,7 +6434,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(AcosD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(acos(lhs.toDouble())); + out.setDouble(std::acos(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$acos(%l)"; } virtual string emitC() override { return "acos(%li)"; } @@ -6446,7 +6446,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(AtanD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(atan(lhs.toDouble())); + out.setDouble(std::atan(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$atan(%l)"; } virtual string emitC() override { return "atan(%li)"; } @@ -6458,7 +6458,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(SinhD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(sinh(lhs.toDouble())); + out.setDouble(std::sinh(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$sinh(%l)"; } virtual string emitC() override { return "sinh(%li)"; } @@ -6470,7 +6470,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(CoshD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(cosh(lhs.toDouble())); + out.setDouble(std::cosh(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$cosh(%l)"; } virtual string emitC() override { return "cosh(%li)"; } @@ -6482,7 +6482,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(TanhD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(tanh(lhs.toDouble())); + out.setDouble(std::tanh(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$tanh(%l)"; } virtual string emitC() override { return "tanh(%li)"; } @@ -6494,7 +6494,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(AsinhD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(asinh(lhs.toDouble())); + out.setDouble(std::asinh(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$asinh(%l)"; } virtual string emitC() override { return "asinh(%li)"; } @@ -6506,7 +6506,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(AcoshD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(acosh(lhs.toDouble())); + out.setDouble(std::acosh(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$acosh(%l)"; } virtual string emitC() override { return "acosh(%li)"; } @@ -6518,7 +6518,7 @@ public: : ASTGEN_SUPER(fl, lhsp) {} ASTNODE_NODE_FUNCS(AtanhD) virtual void numberOperate(V3Number& out, const V3Number& lhs) override { - out.setDouble(atanh(lhs.toDouble())); + out.setDouble(std::atanh(lhs.toDouble())); } virtual string emitVerilog() override { return "%f$atanh(%l)"; } virtual string emitC() override { return "atanh(%li)"; } @@ -8190,7 +8190,7 @@ public: return new AstAtan2D(this->fileline(), lhsp, rhsp); } virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { - out.setDouble(atan2(lhs.toDouble(), rhs.toDouble())); + out.setDouble(std::atan2(lhs.toDouble(), rhs.toDouble())); } virtual string emitVerilog() override { return "%f$atan2(%l,%r)"; } virtual string emitC() override { return "atan2(%li,%ri)"; } @@ -8205,7 +8205,7 @@ public: return new AstHypotD(this->fileline(), lhsp, rhsp); } virtual void numberOperate(V3Number& out, const V3Number& lhs, const V3Number& rhs) override { - out.setDouble(hypot(lhs.toDouble(), rhs.toDouble())); + out.setDouble(std::hypot(lhs.toDouble(), rhs.toDouble())); } virtual string emitVerilog() override { return "%f$hypot(%l,%r)"; } virtual string emitC() override { return "hypot(%li,%ri)"; } diff --git a/src/V3Error.cpp b/src/V3Error.cpp index b8c0e6484..f9e0701ad 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -161,7 +161,7 @@ void V3Error::vlAbortOrExit() { std::cerr << msgPrefix() << "Aborting since under --debug" << endl; V3Error::vlAbort(); } else { - exit(1); + std::exit(1); } } diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 5339d4260..f2f4ae6f3 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1295,11 +1295,11 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char DECL_OPTION("-gdbbt", CbCall, []() {}); // Processed only in bin/verilator shell DECL_OPTION("-generate-key", CbCall, [this]() { cout << protectKeyDefaulted() << endl; - exit(0); + std::exit(0); }); DECL_OPTION("-getenv", CbVal, [](const char* valp) { cout << V3Options::getenvBuiltins(valp) << endl; - exit(0); + std::exit(0); }); DECL_OPTION("-hierarchical", OnOff, &m_hierarchical); @@ -1562,7 +1562,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char DECL_OPTION("-V", CbCall, [this]() { showVersion(true); - exit(0); + std::exit(0); }); DECL_OPTION("-v", CbVal, [this, &optdir](const char* valp) { V3Options::addLibraryFile(parseFileArg(optdir, valp)); @@ -1570,7 +1570,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char DECL_OPTION("-verilate", OnOff, &m_verilate); DECL_OPTION("-version", CbCall, [this]() { showVersion(false); - exit(0); + std::exit(0); }); DECL_OPTION("-vpi", OnOff, &m_vpi); diff --git a/src/V3TSP.cpp b/src/V3TSP.cpp index afd103a27..770c2895b 100644 --- a/src/V3TSP.cpp +++ b/src/V3TSP.cpp @@ -515,7 +515,7 @@ public: unsigned yabs; xabs = diff(otherp->m_xpos, m_xpos); yabs = diff(otherp->m_ypos, m_ypos); - return lround(sqrt(xabs * xabs + yabs * yabs)); + return std::lround(std::sqrt(xabs * xabs + yabs * yabs)); } unsigned xpos() const { return m_xpos; } unsigned ypos() const { return m_ypos; } diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 62e1a945f..9128ce4c2 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -3880,7 +3880,7 @@ private: newp = new AstMul(argp->fileline(), new AstConst(argp->fileline(), AstConst::Unsized64(), - llround(scale)), + std::llround(scale)), argp); } relinkHandle.relink(newp); diff --git a/src/Verilator.cpp b/src/Verilator.cpp index 342506342..8b8605430 100644 --- a/src/Verilator.cpp +++ b/src/Verilator.cpp @@ -117,7 +117,7 @@ static void process() { V3Error::abortIfErrors(); if (v3Global.opt.debugExitParse()) { cout << "--debug-exit-parse: Exiting after parse\n"; - exit(0); + std::exit(0); } // Convert parseref's to varrefs, and other directly post parsing fixups @@ -125,7 +125,7 @@ static void process() { if (v3Global.opt.debugExitUvm()) { V3Error::abortIfErrors(); cout << "--debug-exit-uvm: Exiting after UVM-supported pass\n"; - exit(0); + std::exit(0); } // Cross-link signal names @@ -664,7 +664,7 @@ static void execBuildJob() { const int exit_code = V3Os::system(cmdStr); if (exit_code != 0) { v3error(cmdStr << " exited with " << exit_code << std::endl); - exit(exit_code); + std::exit(exit_code); } } @@ -676,7 +676,7 @@ static void execHierVerilation() { const int exit_code = V3Os::system(cmdStr); if (exit_code != 0) { v3error(cmdStr << " exited with " << exit_code << std::endl); - exit(exit_code); + std::exit(exit_code); } } diff --git a/src/VlcMain.cpp b/src/VlcMain.cpp index 3df97d3cb..84f6ea5fa 100644 --- a/src/VlcMain.cpp +++ b/src/VlcMain.cpp @@ -101,10 +101,10 @@ void VlcOptions::parseOptsList(int argc, char** argv) { V3Error::debugDefault(atoi(argv[i])); } else if (!strcmp(sw, "-V")) { showVersion(true); - exit(0); + std::exit(0); } else if (!strcmp(sw, "-version")) { showVersion(false); - exit(0); + std::exit(0); } else if (!strcmp(sw, "-write") && (i + 1) < argc) { shift; m_writeFile = argv[i]; From 02d82978e547f66e060f73a1e0641be7e5cbf99f Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 26 Mar 2021 22:13:55 -0400 Subject: [PATCH 044/110] Avoid quoting + to appease cygwin bash/gcc --gdbbt (#2856) --- bin/verilator | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/verilator b/bin/verilator index 478c06c0f..ee0dbeab6 100755 --- a/bin/verilator +++ b/bin/verilator @@ -225,7 +225,7 @@ sub sh_escape { # This is similar to quotemeta() but less aggressive. # There's no need to escape hyphens, periods, or forward slashes # for the shell as these have no special meaning to the shell. - $arg =~ s/([^0-9a-zA-Z_\-\.\/])/\\$1/g; + $arg =~ s/([^0-9a-zA-Z_\-\+\=\.\/])/\\$1/g; return $arg; } From 4155de721b700ea122cfa81058b146a2bd7e5055 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 26 Mar 2021 23:01:58 -0400 Subject: [PATCH 045/110] Fix Cygwin example compile issues (#2856). --- Changes | 1 + examples/make_protect_lib/Makefile | 6 ++++++ examples/make_tracing_c/Makefile | 7 ++++++- examples/make_tracing_c/Makefile_obj | 8 ++++++-- 4 files changed, 19 insertions(+), 3 deletions(-) diff --git a/Changes b/Changes index a69c14979..d3e675d92 100644 --- a/Changes +++ b/Changes @@ -25,6 +25,7 @@ Verilator 4.201 devel * Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett] * Fix --output-split with class extends (#2839). [Iru Cai] * Fix false WIDTHCONCAT on casted constant (#2849). [Rupert Swarbrick] +* Fix Cygwin example compile issues (#2856). [Mark Shaw] Verilator 4.200 2021-03-12 diff --git a/examples/make_protect_lib/Makefile b/examples/make_protect_lib/Makefile index 319ce5c4a..215df0396 100644 --- a/examples/make_protect_lib/Makefile +++ b/examples/make_protect_lib/Makefile @@ -36,6 +36,12 @@ VERILATOR_FLAGS += -cc VERILATOR_FLAGS += -Os -x-assign 0 # Warn abount lint issues; may not want this on less solid designs VERILATOR_FLAGS += -Wall +# This example does not use vl_time_stamp but rather +# VerilatedContext::timeInc(), so to avoid a linker error on cygwin which +# does not support weak symbols, we need to define VL_TIME_CONTEXT *in CPP* +# to not compile in the vl_time_stamp using code. +VERILATOR_FLAGS += -CFLAGS -DVL_TIME_CONTEXT + # Make waveforms TOP_VERILATOR_FLAGS = $(VERILATOR_FLAGS) --trace diff --git a/examples/make_tracing_c/Makefile b/examples/make_tracing_c/Makefile index e16d285fd..01556bc59 100644 --- a/examples/make_tracing_c/Makefile +++ b/examples/make_tracing_c/Makefile @@ -31,7 +31,6 @@ VERILATOR = $(VERILATOR_ROOT)/bin/verilator VERILATOR_COVERAGE = $(VERILATOR_ROOT)/bin/verilator_coverage endif -VERILATOR_FLAGS = # Generate C++ in executable form VERILATOR_FLAGS += -cc --exe # Generate makefile dependencies (not shown as complicates the Makefile) @@ -50,6 +49,12 @@ VERILATOR_FLAGS += --coverage #VERILATOR_FLAGS += --debug # Add this trace to get a backtrace in gdb #VERILATOR_FLAGS += --gdbbt +# This example does not use vl_time_stamp but rather +# VerilatedContext::timeInc(), so to avoid a linker error on cygwin which +# does not support weak symbols, we need to define VL_TIME_CONTEXT *in CPP* +# to not compile in the vl_time_stamp using code. +VERILATOR_FLAGS += -CFLAGS -DVL_TIME_CONTEXT + # Input files for Verilator VERILATOR_INPUT = -f input.vc top.v sim_main.cpp diff --git a/examples/make_tracing_c/Makefile_obj b/examples/make_tracing_c/Makefile_obj index 3177ef188..b757bd8d4 100644 --- a/examples/make_tracing_c/Makefile_obj +++ b/examples/make_tracing_c/Makefile_obj @@ -22,10 +22,13 @@ COMPILE.cc = $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c ####################################################################### # Compile flags -# Override some default compile flags +# Turn on creating .d make dependency files CPPFLAGS += -MMD -MP + +# Compile in Verilator runtime debugging, so +verilator+debug works CPPFLAGS += -DVL_DEBUG=1 -# Turn on some more flags (when configured appropriately) + +# Turn on some more compiler lint flags (when configured appropriately) # For testing inside Verilator, "configure --enable-ccwarn" will do this # automatically; otherwise you may want this unconditionally enabled ifeq ($(CFG_WITH_CCWARN),yes) # Local... Else don't burden users @@ -36,6 +39,7 @@ endif # Support class optimizations. This includes the tracing and symbol table. # SystemC takes minutes to optimize, thus it is off by default. OPT_SLOW = + # Fast path optimizations. Most time is spent in these classes. OPT_FAST = -Os -fstrict-aliasing #OPT_FAST = -O From e0808bcd154cc1ac8ecc0319704aa67c39970812 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 26 Mar 2021 23:05:04 -0400 Subject: [PATCH 046/110] Commentary --- Changes | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Changes b/Changes index d3e675d92..84ca20cbd 100644 --- a/Changes +++ b/Changes @@ -25,6 +25,8 @@ Verilator 4.201 devel * Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett] * Fix --output-split with class extends (#2839). [Iru Cai] * Fix false WIDTHCONCAT on casted constant (#2849). [Rupert Swarbrick] +* Fix --public-flat-rw / DPI issue (#2858). [Todd Strader] +* Fix interface localparam access (#2859). [Todd Strader] * Fix Cygwin example compile issues (#2856). [Mark Shaw] From 5b4448de23eae9c6ef49bbd0f69c9bf206548c55 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Fri, 26 Mar 2021 23:22:52 -0400 Subject: [PATCH 047/110] Internals: Add some std::'s. No functional change intended. --- src/V3Error.cpp | 4 ++-- src/V3Number.h | 3 ++- src/V3Param.cpp | 2 +- src/V3ProtectLib.cpp | 2 +- src/V3Table.cpp | 2 +- src/VlcBucket.h | 2 +- src/VlcPoint.h | 8 ++++---- src/VlcTop.cpp | 15 ++++++++------- 8 files changed, 20 insertions(+), 18 deletions(-) diff --git a/src/V3Error.cpp b/src/V3Error.cpp index f9e0701ad..13e506916 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -77,7 +77,7 @@ void V3Error::init() { string V3Error::lineStr(const char* filename, int lineno) { std::ostringstream out; - const char* fnslashp = strrchr(filename, '/'); + const char* fnslashp = std::strrchr(filename, '/'); if (fnslashp) filename = fnslashp + 1; out << filename << ":" << std::dec << lineno << ":"; const char* const spaces = " "; @@ -167,7 +167,7 @@ void V3Error::vlAbortOrExit() { void V3Error::vlAbort() { VL_GCOV_FLUSH(); - abort(); + std::abort(); } //====================================================================== diff --git a/src/V3Number.h b/src/V3Number.h index 248461947..ab1bc4dd2 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -30,7 +30,8 @@ // Return if two numbers within Epsilon of each other inline bool v3EpsilonEqual(double a, double b) { - return fabs(a - b) <= (std::numeric_limits::epsilon() * std::max(1.0, std::max(a, b))); + return std::fabs(a - b) + <= (std::numeric_limits::epsilon() * std::max(1.0, std::max(a, b))); } //============================================================================ diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 0ff23444c..8b7ba30d6 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -276,7 +276,7 @@ class ParamProcessor final { if (AstVar* varp = VN_CAST(stmtp, Var)) { if (varp->isGParam() || varp->isIfaceRef()) { char ch = varp->name()[0]; - ch = toupper(ch); + ch = std::toupper(ch); if (ch < 'A' || ch > 'Z') ch = 'Z'; varp->user4(usedLetter[static_cast(ch)] * 256 + ch); usedLetter[static_cast(ch)]++; diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp index b7327c2be..ec267187c 100644 --- a/src/V3ProtectLib.cpp +++ b/src/V3ProtectLib.cpp @@ -321,7 +321,7 @@ private: + " library, " "Verliog (%u) and library (%u) hash values do not " "agree\\n\", protectlib_hash__V, expected_hash__V);\n"); - txtp->addText(fl, "exit(EXIT_FAILURE);\n"); + txtp->addText(fl, "std::exit(EXIT_FAILURE);\n"); txtp->addText(fl, "}\n"); txtp->addText(fl, "}\n\n"); diff --git a/src/V3Table.cpp b/src/V3Table.cpp index 6e35b8d10..c31adb692 100644 --- a/src/V3Table.cpp +++ b/src/V3Table.cpp @@ -116,7 +116,7 @@ private: // Calc data storage in bytes size_t chgWidth = m_outVarps.size(); // Width of one change-it-vector if (chgWidth < 8) chgWidth = 8; - double space = (pow(static_cast(2.0), static_cast(m_inWidth)) + double space = (std::pow(static_cast(2.0), static_cast(m_inWidth)) * static_cast(m_outWidth + chgWidth)); // Instruction count bytes (ok, it's space also not time :) double bytesPerInst = 4; diff --git a/src/VlcBucket.h b/src/VlcBucket.h index e68483af2..3add0dd46 100644 --- a/src/VlcBucket.h +++ b/src/VlcBucket.h @@ -39,7 +39,7 @@ private: if (m_dataSize < point) m_dataSize = (point + 64) & ~63ULL; // Keep power of two m_dataSize *= 2; // UINFO(9, "Realloc "<(realloc(m_datap, allocSize())); + vluint64_t* newp = static_cast(std::realloc(m_datap, allocSize())); if (VL_UNCOVERABLE(!newp)) { // cppcheck-suppress doubleFree // cppcheck 1.90 bug - realloc doesn't free on fail free(m_datap); // LCOV_EXCL_LINE diff --git a/src/VlcPoint.h b/src/VlcPoint.h index 8be685d2c..8e20f999d 100644 --- a/src/VlcPoint.h +++ b/src/VlcPoint.h @@ -56,16 +56,16 @@ public: string type() const { return keyExtract(VL_CIK_TYPE); } string thresh() const { return keyExtract(VL_CIK_THRESH); } // string as maybe "" string linescov() const { return keyExtract(VL_CIK_LINESCOV); } - int lineno() const { return atoi(keyExtract(VL_CIK_LINENO).c_str()); } - int column() const { return atoi(keyExtract(VL_CIK_COLUMN).c_str()); } + int lineno() const { return std::atoi(keyExtract(VL_CIK_LINENO).c_str()); } + int column() const { return std::atoi(keyExtract(VL_CIK_COLUMN).c_str()); } // METHODS string keyExtract(const char* shortKey) const { // Hot function - size_t shortLen = strlen(shortKey); + size_t shortLen = std::strlen(shortKey); const string namestr = name(); for (const char* cp = namestr.c_str(); *cp; ++cp) { if (*cp == '\001') { - if (0 == strncmp(cp + 1, shortKey, shortLen) && cp[shortLen + 1] == '\002') { + if (0 == std::strncmp(cp + 1, shortKey, shortLen) && cp[shortLen + 1] == '\002') { cp += shortLen + 2; // Skip \001+short+\002 const char* ep = cp; while (*ep && *ep != '\001') ++ep; diff --git a/src/VlcTop.cpp b/src/VlcTop.cpp index 021e875c4..5999e8ba3 100644 --- a/src/VlcTop.cpp +++ b/src/VlcTop.cpp @@ -45,7 +45,7 @@ void VlcTop::readCoverage(const string& filename, bool nonfatal) { if (line[secspace] == '\'' && line[secspace + 1] == ' ') break; } string point = line.substr(3, secspace - 3); - vluint64_t hits = atoll(line.c_str() + secspace + 1); + vluint64_t hits = std::atoll(line.c_str() + secspace + 1); // UINFO(9," point '"<= thresh); UINFO(9, "AnnoCalc count " << filename << ":" << lineno << ":" << point.column() << " " << point.count() << " " << point.linescov() << '\n'); @@ -225,12 +226,12 @@ void VlcTop::annotateCalc() { range = false; } else if (*covp == '-') { range = true; - } else if (isdigit(*covp)) { + } else if (std::isdigit(*covp)) { const char* digitsp = covp; - while (isdigit(*covp)) ++covp; + while (std::isdigit(*covp)) ++covp; --covp; // Will inc in for loop - if (!range) start = atoi(digitsp); - end = atoi(digitsp); + if (!range) start = std::atoi(digitsp); + end = std::atoi(digitsp); } } } @@ -314,7 +315,7 @@ void VlcTop::annotateOutputFiles(const string& dirname) { // Multiple columns on same line; print line just once string indent; for (string::const_iterator pos = line.begin(); - pos != line.end() && isspace(*pos); ++pos) { + pos != line.end() && std::isspace(*pos); ++pos) { indent += *pos; } line = indent + "verilator_coverage: (next point on previous line)\n"; From d4d87ef3006ef1cd40d3b350310e12f39593768c Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 27 Mar 2021 08:45:13 -0400 Subject: [PATCH 048/110] Examples: Clearer to define sc_time_stamp --- examples/make_tracing_c/Makefile | 6 ------ examples/make_tracing_c/Makefile_obj | 6 ------ examples/make_tracing_c/sim_main.cpp | 3 +++ 3 files changed, 3 insertions(+), 12 deletions(-) diff --git a/examples/make_tracing_c/Makefile b/examples/make_tracing_c/Makefile index 01556bc59..be77c71e4 100644 --- a/examples/make_tracing_c/Makefile +++ b/examples/make_tracing_c/Makefile @@ -49,12 +49,6 @@ VERILATOR_FLAGS += --coverage #VERILATOR_FLAGS += --debug # Add this trace to get a backtrace in gdb #VERILATOR_FLAGS += --gdbbt -# This example does not use vl_time_stamp but rather -# VerilatedContext::timeInc(), so to avoid a linker error on cygwin which -# does not support weak symbols, we need to define VL_TIME_CONTEXT *in CPP* -# to not compile in the vl_time_stamp using code. -VERILATOR_FLAGS += -CFLAGS -DVL_TIME_CONTEXT - # Input files for Verilator VERILATOR_INPUT = -f input.vc top.v sim_main.cpp diff --git a/examples/make_tracing_c/Makefile_obj b/examples/make_tracing_c/Makefile_obj index b757bd8d4..56db2ee15 100644 --- a/examples/make_tracing_c/Makefile_obj +++ b/examples/make_tracing_c/Makefile_obj @@ -45,12 +45,6 @@ OPT_FAST = -Os -fstrict-aliasing #OPT_FAST = -O #OPT_FAST = -####################################################################### -# Linking final exe -- presumes have a sim_main.cpp - -# Special compile rule -sim_main.o: sim_main.cpp $(VM_PREFIX).h - ###################################################################### ###################################################################### # Automatically understand dependencies diff --git a/examples/make_tracing_c/sim_main.cpp b/examples/make_tracing_c/sim_main.cpp index edd786a14..c8ee021a6 100644 --- a/examples/make_tracing_c/sim_main.cpp +++ b/examples/make_tracing_c/sim_main.cpp @@ -14,6 +14,9 @@ // Include model header, generated from Verilating "top.v" #include "Vtop.h" +// Legacy function required only so linking works on Cygwin and MSVC++ +double sc_time_stamp() { return 0; } + int main(int argc, char** argv, char** env) { // This is a more complicated example, please also see the simpler examples/make_hello_c. From 05db4e41cd79baa5f947d63d51f5e86f76d54e47 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 27 Mar 2021 13:14:43 -0400 Subject: [PATCH 049/110] Add better suggestions on some bad options. --- src/V3Options.cpp | 12 +++++++++--- src/VlcMain.cpp | 17 +++++++---------- test_regress/t/t_flag_compiler_bad.out | 2 ++ test_regress/t/t_flag_compiler_bad.pl | 20 ++++++++++++++++++++ test_regress/t/t_flag_threads_dpi_bad.out | 2 ++ test_regress/t/t_flag_threads_dpi_bad.pl | 20 ++++++++++++++++++++ test_regress/t/t_flag_x_assign_bad.out | 2 ++ test_regress/t/t_flag_x_assign_bad.pl | 20 ++++++++++++++++++++ test_regress/t/t_flag_x_initial_bad.out | 2 ++ test_regress/t/t_flag_x_initial_bad.pl | 20 ++++++++++++++++++++ 10 files changed, 104 insertions(+), 13 deletions(-) create mode 100644 test_regress/t/t_flag_compiler_bad.out create mode 100755 test_regress/t/t_flag_compiler_bad.pl create mode 100644 test_regress/t/t_flag_threads_dpi_bad.out create mode 100755 test_regress/t/t_flag_threads_dpi_bad.pl create mode 100644 test_regress/t/t_flag_x_assign_bad.out create mode 100755 test_regress/t/t_flag_x_assign_bad.pl create mode 100644 test_regress/t/t_flag_x_initial_bad.out create mode 100755 test_regress/t/t_flag_x_initial_bad.pl diff --git a/src/V3Options.cpp b/src/V3Options.cpp index f2f4ae6f3..cbbc25cc9 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1498,7 +1498,9 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char m_threadsDpiPure = true; m_threadsDpiUnpure = false; } else { - fl->v3fatal("Unknown setting for --threads-dpi: " << valp); + fl->v3fatal("Unknown setting for --threads-dpi: '" + << valp << "'\n" + << fl->warnMore() << "... Suggest 'all', 'none', or 'pure'"); } }); DECL_OPTION("-threads-max-mtasks", CbVal, [this, fl](const char* valp) { @@ -1636,7 +1638,9 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char } else if (!strcmp(valp, "unique")) { m_xAssign = "unique"; } else { - fl->v3fatal("Unknown setting for --x-assign: " << valp); + fl->v3fatal("Unknown setting for --x-assign: '" + << valp << "'\n" + << fl->warnMore() << "... Suggest '0', '1', 'fast', or 'unique'"); } }); DECL_OPTION("-x-initial", CbVal, [this, fl](const char* valp) { @@ -1647,7 +1651,9 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char } else if (!strcmp(valp, "unique")) { m_xInitial = "unique"; } else { - fl->v3fatal("Unknown setting for --x-initial: " << valp); + fl->v3fatal("Unknown setting for --x-initial: '" + << valp << "'\n" + << fl->warnMore() << "... Suggest '0', 'fast', or 'unique'"); } }); DECL_OPTION("-x-initial-edge", OnOff, &m_xInitialEdge); diff --git a/src/VlcMain.cpp b/src/VlcMain.cpp index 84f6ea5fa..68e22cc70 100644 --- a/src/VlcMain.cpp +++ b/src/VlcMain.cpp @@ -70,8 +70,6 @@ void VlcOptions::parseOptsList(int argc, char** argv) { // Parse parameters // Note argc and argv DO NOT INCLUDE the filename in [0]!!! // May be called recursively when there are -f files. -#define shift \ - do { ++i; } while (false) for (int i = 0; i < argc;) { UINFO(9, " Option: " << argv[i] << endl); if (argv[i][0] == '-') { @@ -89,15 +87,15 @@ void VlcOptions::parseOptsList(int argc, char** argv) { } // Parameterized switches else if (!strcmp(sw, "-annotate-min") && (i + 1) < argc) { - shift; + ++i; m_annotateMin = atoi(argv[i]); } else if (!strcmp(sw, "-annotate") && (i + 1) < argc) { - shift; + ++i; m_annotateOut = argv[i]; } else if (!strcmp(sw, "-debug")) { V3Error::debugDefault(3); } else if (!strcmp(sw, "-debugi") && (i + 1) < argc) { - shift; + ++i; V3Error::debugDefault(atoi(argv[i])); } else if (!strcmp(sw, "-V")) { showVersion(true); @@ -106,22 +104,21 @@ void VlcOptions::parseOptsList(int argc, char** argv) { showVersion(false); std::exit(0); } else if (!strcmp(sw, "-write") && (i + 1) < argc) { - shift; + ++i; m_writeFile = argv[i]; } else if (!strcmp(sw, "-write-info") && (i + 1) < argc) { - shift; + ++i; m_writeInfoFile = argv[i]; } else { v3fatal("Invalid option: " << argv[i]); } - shift; + ++i; } // - options else { addReadFile(argv[i]); - shift; + ++i; } } -#undef shift } void VlcOptions::showVersion(bool verbose) { diff --git a/test_regress/t/t_flag_compiler_bad.out b/test_regress/t/t_flag_compiler_bad.out new file mode 100644 index 000000000..db87cd4d0 --- /dev/null +++ b/test_regress/t/t_flag_compiler_bad.out @@ -0,0 +1,2 @@ +%Error: Unknown setting for --compiler: 'bad_one' + ... Suggest 'clang', 'gcc', or 'msvc' diff --git a/test_regress/t/t_flag_compiler_bad.pl b/test_regress/t/t_flag_compiler_bad.pl new file mode 100755 index 000000000..0bf39f727 --- /dev/null +++ b/test_regress/t/t_flag_compiler_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + verilator_flags2 => ["--compiler bad_one"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_flag_threads_dpi_bad.out b/test_regress/t/t_flag_threads_dpi_bad.out new file mode 100644 index 000000000..ca3423d51 --- /dev/null +++ b/test_regress/t/t_flag_threads_dpi_bad.out @@ -0,0 +1,2 @@ +%Error: Unknown setting for --threads-dpi: 'bad_one' + ... Suggest 'all', 'none', or 'pure' diff --git a/test_regress/t/t_flag_threads_dpi_bad.pl b/test_regress/t/t_flag_threads_dpi_bad.pl new file mode 100755 index 000000000..46cf0221c --- /dev/null +++ b/test_regress/t/t_flag_threads_dpi_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + verilator_flags2 => ["--threads-dpi bad_one"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_flag_x_assign_bad.out b/test_regress/t/t_flag_x_assign_bad.out new file mode 100644 index 000000000..43929ec3c --- /dev/null +++ b/test_regress/t/t_flag_x_assign_bad.out @@ -0,0 +1,2 @@ +%Error: Unknown setting for --x-assign: 'bad_one' + ... Suggest '0', '1', 'fast', or 'unique' diff --git a/test_regress/t/t_flag_x_assign_bad.pl b/test_regress/t/t_flag_x_assign_bad.pl new file mode 100755 index 000000000..af3b0a78c --- /dev/null +++ b/test_regress/t/t_flag_x_assign_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + verilator_flags2 => ["--x-assign bad_one"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_flag_x_initial_bad.out b/test_regress/t/t_flag_x_initial_bad.out new file mode 100644 index 000000000..8f511db51 --- /dev/null +++ b/test_regress/t/t_flag_x_initial_bad.out @@ -0,0 +1,2 @@ +%Error: Unknown setting for --x-initial: 'bad_one' + ... Suggest '0', 'fast', or 'unique' diff --git a/test_regress/t/t_flag_x_initial_bad.pl b/test_regress/t/t_flag_x_initial_bad.pl new file mode 100755 index 000000000..88423465e --- /dev/null +++ b/test_regress/t/t_flag_x_initial_bad.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + verilator_flags2 => ["--x-initial bad_one"], + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; From 9a39c69cb98686ae83f951a9992000d6be5b4f4d Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 09:54:50 -0400 Subject: [PATCH 050/110] CI: Run coverage with SystemC --- .github/workflows/coverage.yml | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index 8fa0e88e8..4c93ff3e5 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -20,16 +20,22 @@ jobs: Build: - runs-on: ubuntu-20.04 + strategy: + fail-fast: false + matrix: + os: ubuntu-20.04 + runs-on: ${{ matrix.os }} env: CI_BUILD_STAGE_NAME: build CI_RUNS_ON: ${{ matrix.os }} CACHE_KEY: ${{ matrix.os }}-${{ matrix.compiler.cc }}-coverage steps: - - uses: actions/checkout@v2 + - name: Checkout + uses: actions/checkout@v2 - - uses: actions/cache@v2 + - name: Cache + uses: actions/cache@v2 env: cache-name: ccache with: @@ -37,15 +43,14 @@ jobs: key: ${{ env.CACHE_KEY }}-${{ env.cache-name }}-${{ github.sha }} restore-keys: coverage-${{ env.cache-name }} - - name: Install dependencies for build + - name: Install packages for build env: CI_BUILD_STAGE_NAME: build run: ./ci/ci-install.bash - - name: Build Verilator + - name: Build run: | ./ci/ci-script.bash - tar cvzf verilator-${CI_COMMIT}-coverage.tgz bin src/obj*/*.o src/obj*/*.gcno - uses: actions/upload-artifact@v2 @@ -58,6 +63,7 @@ jobs: strategy: fail-fast: false matrix: + os: ubuntu-20.04 test: - vlt- - vltmt- @@ -74,17 +80,19 @@ jobs: - 9 include: - { test: dist, num: '' } + runs-on: ${{ matrix.os }} name: test-${{ matrix.test }}${{ matrix.num }} - runs-on: ubuntu-20.04 env: CI_BUILD_STAGE_NAME: test CI_RUNS_ON: ${{ matrix.os }} CACHE_KEY: ${{ matrix.os }}-${{ matrix.compiler.cc }}-coverage steps: - - uses: actions/checkout@v2 + - name: Checkout + uses: actions/checkout@v2 - - uses: actions/cache@v2 + - name: Cache + uses: actions/cache@v2 env: cache-name: ccache with: From 64802f6f3d0b5eb3c67242d81c9fa471995f25a2 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 09:55:56 -0400 Subject: [PATCH 051/110] CI: Run coverage with SystemC --- .github/workflows/coverage.yml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index 4c93ff3e5..3e35f21e2 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -23,7 +23,8 @@ jobs: strategy: fail-fast: false matrix: - os: ubuntu-20.04 + os: + - ubuntu-20.04 runs-on: ${{ matrix.os }} env: CI_BUILD_STAGE_NAME: build @@ -63,7 +64,8 @@ jobs: strategy: fail-fast: false matrix: - os: ubuntu-20.04 + os: + - ubuntu-20.04 test: - vlt- - vltmt- From 0b17d4f059e25eeaac14effecc6bfb2ce7892f15 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 11:14:44 -0400 Subject: [PATCH 052/110] CI: Run coverage with SystemC --- .github/workflows/coverage.yml | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index 3e35f21e2..a62fad944 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -23,8 +23,7 @@ jobs: strategy: fail-fast: false matrix: - os: - - ubuntu-20.04 + os: [ ubuntu-20.04 ] runs-on: ${{ matrix.os }} env: CI_BUILD_STAGE_NAME: build @@ -64,22 +63,11 @@ jobs: strategy: fail-fast: false matrix: - os: - - ubuntu-20.04 + os: [ ubuntu-20.04 ] test: - vlt- - vltmt- - num: - - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 - - 7 - - 8 - - 9 + num: [ 0 1 2 3 4 5 6 7 8 9 ] include: - { test: dist, num: '' } runs-on: ${{ matrix.os }} From e9b5721fb089dc4abdf78f2620d84fb571f7f065 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 11:14:51 -0400 Subject: [PATCH 053/110] Internals: Remove VL_FUNC as __func__ part of C++11 --- include/verilated_vpi.cpp | 60 +++++++++++++++++++-------------------- include/verilatedos.h | 7 +---- 2 files changed, 31 insertions(+), 36 deletions(-) diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 9901ead6d..39fb58b7d 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -52,7 +52,7 @@ constexpr unsigned VL_VPI_LINE_SIZE_ = 8192; // Not supported yet #define VL_VPI_UNIMP_() \ - (VL_VPI_ERROR_(__FILE__, __LINE__, Verilated::catName("Unsupported VPI function: ", VL_FUNC))) + (VL_VPI_ERROR_(__FILE__, __LINE__, Verilated::catName("Unsupported VPI function: ", __func__))) //====================================================================== // Implementation @@ -1158,7 +1158,7 @@ vpiHandle vpi_register_cb(p_cb_data cb_data_p) { VL_VPI_ERROR_RESET_(); // cppcheck-suppress nullPointer if (VL_UNLIKELY(!cb_data_p)) { - VL_VPI_WARNING_(__FILE__, __LINE__, "%s : callback data pointer is null", VL_FUNC); + VL_VPI_WARNING_(__FILE__, __LINE__, "%s : callback data pointer is null", __func__); return nullptr; } switch (cb_data_p->reason) { @@ -1187,7 +1187,7 @@ vpiHandle vpi_register_cb(p_cb_data cb_data_p) { return vop->castVpiHandle(); } default: - VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported callback type %s", VL_FUNC, + VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported callback type %s", __func__, VerilatedVpiError::strFromVpiCallbackReason(cb_data_p->reason)); return nullptr; } @@ -1290,7 +1290,7 @@ vpiHandle vpi_handle_by_index(vpiHandle object, PLI_INT32 indx) { indx - varop->varp()->unpacked().left())) ->castVpiHandle(); } - VL_VPI_INTERNAL_(__FILE__, __LINE__, "%s : can't resolve handle", VL_FUNC); + VL_VPI_INTERNAL_(__FILE__, __LINE__, "%s : can't resolve handle", __func__); return nullptr; } @@ -1311,7 +1311,7 @@ vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { } VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p) for type %s, nothing will be returned", - VL_FUNC, object, VerilatedVpiError::strFromVpiMethod(type)); + __func__, object, VerilatedVpiError::strFromVpiMethod(type)); return nullptr; } case vpiRightRange: { @@ -1324,7 +1324,7 @@ vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { } VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p) for type %s, nothing will be returned", - VL_FUNC, object, VerilatedVpiError::strFromVpiMethod(type)); + __func__, object, VerilatedVpiError::strFromVpiMethod(type)); return nullptr; } case vpiIndex: { @@ -1344,7 +1344,7 @@ vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { } default: VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", - VL_FUNC, VerilatedVpiError::strFromVpiMethod(type)); + __func__, VerilatedVpiError::strFromVpiMethod(type)); return nullptr; } } @@ -1366,7 +1366,7 @@ vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) { if (vop->varp()->dims() < 2) return nullptr; if (vop->varp()->dims() > 2) { VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: %s, object %s has unsupported number of indices (%d)", VL_FUNC, + "%s: %s, object %s has unsupported number of indices (%d)", __func__, VerilatedVpiError::strFromVpiMethod(type), vop->fullname(), vop->varp()->dims()); } @@ -1379,7 +1379,7 @@ vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) { // Unsupported is multidim list if (vop->varp()->dims() > 2) { VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: %s, object %s has unsupported number of indices (%d)", VL_FUNC, + "%s: %s, object %s has unsupported number of indices (%d)", __func__, VerilatedVpiError::strFromVpiMethod(type), vop->fullname(), vop->varp()->dims()); } @@ -1400,7 +1400,7 @@ vpiHandle vpi_iterate(PLI_INT32 type, vpiHandle object) { } default: VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", - VL_FUNC, VerilatedVpiError::strFromVpiObjType(type)); + __func__, VerilatedVpiError::strFromVpiObjType(type)); return nullptr; } } @@ -1454,7 +1454,7 @@ PLI_INT32 vpi_get(PLI_INT32 property, vpiHandle object) { } default: VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", - VL_FUNC, VerilatedVpiError::strFromVpiProp(property)); + __func__, VerilatedVpiError::strFromVpiProp(property)); return 0; } } @@ -1485,7 +1485,7 @@ PLI_BYTE8* vpi_get_str(PLI_INT32 property, vpiHandle object) { } default: VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported type %s, nothing will be returned", - VL_FUNC, VerilatedVpiError::strFromVpiProp(property)); + __func__, VerilatedVpiError::strFromVpiProp(property)); return nullptr; } } @@ -1545,7 +1545,7 @@ bool vl_check_format(const VerilatedVar* varp, const p_vpi_value valuep, const c } else { status = false; } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) for %s", VL_FUNC, + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) for %s", __func__, VerilatedVpiError::strFromVpiVal(valuep->format), fullname); return status; } @@ -1609,7 +1609,7 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep, __FILE__, __LINE__, "%s: Truncating string value of %s for %s" " as buffer size (%d, VL_MULS_MAX_WORDS=%d) is less than required (%d)", - VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, t_outStrSz, + __func__, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, t_outStrSz, VL_MULS_MAX_WORDS, bits); } for (i = 0; i < bits; ++i) { @@ -1630,7 +1630,7 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep, __FILE__, __LINE__, "%s: Truncating string value of %s for %s" " as buffer size (%d, VL_MULS_MAX_WORDS=%d) is less than required (%d)", - VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, t_outStrSz, + __func__, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, t_outStrSz, VL_MULS_MAX_WORDS, chars); chars = t_outStrSz; } @@ -1688,7 +1688,7 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep, __FILE__, __LINE__, "%s: Truncating string value of %s for %s" " as buffer size (%d, VL_MULS_MAX_WORDS=%d) is less than required (%d)", - VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, t_outStrSz, + __func__, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, t_outStrSz, VL_MULS_MAX_WORDS, chars); chars = t_outStrSz; } @@ -1722,7 +1722,7 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep, __FILE__, __LINE__, "%s: Truncating string value of %s for %s" " as buffer size (%d, VL_MULS_MAX_WORDS=%d) is less than required (%d)", - VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, + __func__, VerilatedVpiError::strFromVpiVal(valuep->format), fullname, t_outStrSz, VL_MULS_MAX_WORDS, bytes); bytes = t_outStrSz; } @@ -1748,7 +1748,7 @@ void vl_get_value(const VerilatedVar* varp, void* varDatap, p_vpi_value valuep, } else if (valuep->format == vpiSuppressVal) { return; } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) as requested for %s", VL_FUNC, + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) as requested for %s", __func__, VerilatedVpiError::strFromVpiVal(valuep->format), fullname); } @@ -1769,11 +1769,11 @@ void vpi_get_value(vpiHandle object, p_vpi_value valuep) { valuep->value.integer = vop->num(); return; } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) for %s", VL_FUNC, + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) for %s", __func__, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); return; } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p)", VL_FUNC, object); + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p)", __func__, object); } vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_p*/, @@ -1862,7 +1862,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ } else { VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Non octal character '%c' in '%s' as value %s for %s", - VL_FUNC, digit, valuep->value.str, + __func__, digit, valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); val.half = 0; @@ -1897,13 +1897,13 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ int success = std::sscanf(valuep->value.str, "%30llu%15s", &val, remainder); if (success < 1) { VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Parsing failed for '%s' as value %s for %s", - VL_FUNC, valuep->value.str, + __func__, valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); return nullptr; } if (success > 1) { VL_VPI_WARNING_(__FILE__, __LINE__, - "%s: Trailing garbage '%s' in '%s' as value %s for %s", VL_FUNC, + "%s: Trailing garbage '%s' in '%s' as value %s for %s", __func__, remainder, valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); } @@ -1942,7 +1942,7 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ } else { VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Non hex character '%c' in '%s' as value %s for %s", - VL_FUNC, digit, valuep->value.str, + __func__, digit, valuep->value.str, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); hex = 0; @@ -1983,18 +1983,18 @@ vpiHandle vpi_put_value(vpiHandle object, p_vpi_value valuep, p_vpi_time /*time_ } } VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported format (%s) as requested for %s", - VL_FUNC, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); + __func__, VerilatedVpiError::strFromVpiVal(valuep->format), vop->fullname()); return nullptr; } else if (VerilatedVpioParam* vop = VerilatedVpioParam::castp(object)) { VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Ignoring vpi_put_value to vpiParameter: %s", - VL_FUNC, vop->fullname()); + __func__, vop->fullname()); return nullptr; } else if (VerilatedVpioConst* vop = VerilatedVpioConst::castp(object)) { VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Ignoring vpi_put_value to vpiConstant: %s", - VL_FUNC, vop->fullname()); + __func__, vop->fullname()); return nullptr; } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p)", VL_FUNC, object); + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported vpiHandle (%p)", __func__, object); return nullptr; } @@ -2035,7 +2035,7 @@ void vpi_get_time(vpiHandle object, p_vpi_time time_p) { time_p->real = dtime; return; } - VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported type (%d)", VL_FUNC, time_p->type); + VL_VPI_ERROR_(__FILE__, __LINE__, "%s: Unsupported type (%d)", __func__, time_p->type); } // I/O routines @@ -2187,7 +2187,7 @@ PLI_INT32 vpi_control(PLI_INT32 operation, ...) { return 1; // LCOV_EXCL_LINE } default: { - VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported type %s, ignoring", VL_FUNC, + VL_VPI_WARNING_(__FILE__, __LINE__, "%s: Unsupported type %s, ignoring", __func__, VerilatedVpiError::strFromVpiProp(operation)); return 0; } diff --git a/include/verilatedos.h b/include/verilatedos.h index 697e82429..54a22ef7e 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -49,7 +49,6 @@ # if !defined(_WIN32) && !defined(__MINGW32__) # define VL_ATTR_WEAK __attribute__((weak)) # endif -# define VL_FUNC __func__ # if defined(__clang__) && defined(VL_THREADED) # define VL_ACQUIRE(...) __attribute__((acquire_capability(__VA_ARGS__))) # define VL_ACQUIRE_SHARED(...) __attribute__((acquire_shared_capability(__VA_ARGS__))) @@ -68,8 +67,6 @@ # define VL_UNREACHABLE __builtin_unreachable(); # define VL_PREFETCH_RD(p) __builtin_prefetch((p), 0) # define VL_PREFETCH_RW(p) __builtin_prefetch((p), 1) -#elif defined(_MSC_VER) -# define VL_FUNC __FUNCTION__ #endif // Defaults for unsupported compiler features @@ -100,9 +97,6 @@ #ifndef VL_ATTR_WEAK # define VL_ATTR_WEAK ///< Function external that is optionally defined #endif -#ifndef VL_FUNC -# define VL_FUNC "__func__" ///< Name of current function for error macros -#endif #ifndef VL_CAPABILITY # define VL_ACQUIRE(...) ///< Function requires a capability/lock (-fthread-safety) # define VL_ACQUIRE_SHARED(...) ///< Function aquires a shared capability/lock (-fthread-safety) @@ -148,6 +142,7 @@ #endif #ifndef VL_NO_LEGACY +# define VL_FUNC __func__ // Deprecated # define VL_THREAD // Deprecated # define VL_STATIC_OR_THREAD static // Deprecated #endif From f39318bde517172658854a620b051b3105be4038 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 11:47:45 -0400 Subject: [PATCH 054/110] CI: Run coverage with SystemC --- .github/workflows/coverage.yml | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index a62fad944..bfa7e98ac 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -20,15 +20,11 @@ jobs: Build: - strategy: - fail-fast: false - matrix: - os: [ ubuntu-20.04 ] - runs-on: ${{ matrix.os }} + runs-on: ubuntu-20.04 env: CI_BUILD_STAGE_NAME: build - CI_RUNS_ON: ${{ matrix.os }} - CACHE_KEY: ${{ matrix.os }}-${{ matrix.compiler.cc }}-coverage + CI_RUNS_ON: ubuntu-20.04 + CACHE_KEY: ubuntu-20.04-${{ matrix.compiler.cc }}-coverage steps: - name: Checkout @@ -63,19 +59,18 @@ jobs: strategy: fail-fast: false matrix: - os: [ ubuntu-20.04 ] test: - vlt- - vltmt- num: [ 0 1 2 3 4 5 6 7 8 9 ] include: - { test: dist, num: '' } - runs-on: ${{ matrix.os }} + runs-on: ubuntu-20.04 name: test-${{ matrix.test }}${{ matrix.num }} env: CI_BUILD_STAGE_NAME: test - CI_RUNS_ON: ${{ matrix.os }} - CACHE_KEY: ${{ matrix.os }}-${{ matrix.compiler.cc }}-coverage + CI_RUNS_ON: ubuntu-20.04 + CACHE_KEY: ubuntu-20.04-${{ matrix.compiler.cc }}-coverage steps: - name: Checkout From 8992e2ec02ea520e0b32ffa243e04120b0ac8b89 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 11:50:05 -0400 Subject: [PATCH 055/110] Commentary --- include/verilated.cpp | 12 +++--- include/verilated.h | 77 ++++++++++++++++++------------------ include/verilated_cov.cpp | 3 ++ include/verilated_cov.h | 10 +++-- include/verilated_fst_c.h | 3 +- include/verilated_heavy.h | 24 +++++++----- include/verilated_imp.h | 24 ++++++------ include/verilated_save.cpp | 4 +- include/verilated_save.h | 4 +- include/verilated_syms.h | 17 ++++---- include/verilated_vcd_c.h | 16 +++++--- include/verilated_vcd_sc.h | 5 ++- include/verilated_vpi.h | 2 + include/verilatedos.h | 80 +++++++++++++++++++------------------- 14 files changed, 152 insertions(+), 129 deletions(-) diff --git a/include/verilated.cpp b/include/verilated.cpp index 025109183..ce762726e 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -95,7 +95,7 @@ VL_THREAD_LOCAL Verilated::ThreadLocal Verilated::t_s; // Note a TODO is a future version of the API will pass a structure so that // the calling arguments allow for extension -#ifndef VL_USER_FINISH ///< Define this to override this function +#ifndef VL_USER_FINISH ///< Define this to override the vl_finish function void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { if (false && hier) {} VL_PRINTF( // Not VL_PRINTF_MT, already on main thread @@ -111,7 +111,7 @@ void vl_finish(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE } #endif -#ifndef VL_USER_STOP ///< Define this to override this function +#ifndef VL_USER_STOP ///< Define this to override the vl_stop function void vl_stop(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { const char* const msg = "Verilog $stop"; Verilated::threadContextp()->gotError(true); @@ -130,7 +130,7 @@ void vl_stop(const char* filename, int linenum, const char* hier) VL_MT_UNSAFE { } #endif -#ifndef VL_USER_FATAL ///< Define this to override this function +#ifndef VL_USER_FATAL ///< Define this to override the vl_fatal function void vl_fatal(const char* filename, int linenum, const char* hier, const char* msg) VL_MT_UNSAFE { if (false && hier) {} Verilated::threadContextp()->gotError(true); @@ -154,7 +154,7 @@ void vl_fatal(const char* filename, int linenum, const char* hier, const char* m } #endif -#ifndef VL_USER_STOP_MAYBE ///< Define this to override this function +#ifndef VL_USER_STOP_MAYBE ///< Define this to override the vl_stop_maybe function void vl_stop_maybe(const char* filename, int linenum, const char* hier, bool maybe) VL_MT_UNSAFE { Verilated::threadContextp()->errorCountInc(); if (maybe @@ -204,7 +204,7 @@ void VL_FATAL_MT(const char* filename, int linenum, const char* hier, const char //=========================================================================== // Debug prints -/// sprintf but return as string (this isn't fast, for print messages only) +// sprintf but return as string (this isn't fast, for print messages only) std::string _vl_string_vprintf(const char* formatp, va_list ap) VL_MT_SAFE { va_list aq; va_copy(aq, ap); @@ -598,7 +598,7 @@ double VL_ISTOR_D_W(int lbits, WDataInP lwp) VL_PURE { //=========================================================================== // Formatting -/// Output a string representation of a wide number +// Output a string representation of a wide number std::string VL_DECIMAL_NW(int width, WDataInP lwp) VL_MT_SAFE { int maxdecwidth = (width + 3) * 4 / 3; // Or (maxdecwidth+7)/8], but can't have more than 4 BCD bits per word diff --git a/include/verilated.h b/include/verilated.h index 749d1dcbe..d318fea92 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -75,37 +75,38 @@ #endif // clang-format on -//========================================================================= -// Basic types - -// clang-format off -// P // Packed data of bit type (C/S/I/Q/W) -typedef vluint8_t CData; ///< Verilated pack data, 1-8 bits -typedef vluint16_t SData; ///< Verilated pack data, 9-16 bits -typedef vluint32_t IData; ///< Verilated pack data, 17-32 bits -typedef vluint64_t QData; ///< Verilated pack data, 33-64 bits -typedef vluint32_t EData; ///< Verilated pack element of WData array -typedef EData WData; ///< Verilated pack data, >64 bits, as an array -// float F // No typedef needed; Verilator uses float -// double D // No typedef needed; Verilator uses double -// string N // No typedef needed; Verilator uses string -// clang-format on - -typedef const WData* WDataInP; ///< Array input to a function -typedef WData* WDataOutP; ///< Array output from a function - class VerilatedContextImp; class VerilatedContextImpData; class VerilatedCovContext; class VerilatedEvalMsgQueue; +class VerilatedFst; +class VerilatedFstC; +class VerilatedScope; class VerilatedScopeNameMap; class VerilatedVar; class VerilatedVarNameMap; class VerilatedVcd; class VerilatedVcdC; class VerilatedVcdSc; -class VerilatedFst; -class VerilatedFstC; + +//========================================================================= +// Basic types + +// clang-format off +// P // Packed data of bit type (C/S/I/Q/W) +typedef vluint8_t CData; ///< Data representing 'bit' of 1-8 packed bits +typedef vluint16_t SData; ///< Data representing 'bit' of 9-16 packed bits +typedef vluint32_t IData; ///< Data representing 'bit' of 17-32 packed bits +typedef vluint64_t QData; ///< Data representing 'bit' of 33-64 packed bits +typedef vluint32_t EData; ///< Data representing one element of WData array +typedef EData WData; ///< Data representing >64 packed bits (used as pointer) +// float F // No typedef needed; Verilator uses float +// double D // No typedef needed; Verilator uses double +// string N // No typedef needed; Verilator uses string +// clang-format on + +typedef const WData* WDataInP; ///< 'bit' of >64 packed bits as array input to a function +typedef WData* WDataOutP; ///< 'bit' of >64 packed bits as array output from a function enum VerilatedVarType : vluint8_t { VLVT_UNKNOWN = 0, @@ -218,7 +219,7 @@ public: class VerilatedAssertOneThread final { // MEMBERS #if defined(VL_THREADED) && defined(VL_DEBUG) - vluint32_t m_threadid; /// Thread that is legal + vluint32_t m_threadid; // Thread that is legal public: // CONSTRUCTORS // The constructor establishes the thread id for all later calls. @@ -245,9 +246,7 @@ public: }; //========================================================================= -/// Base class for all Verilated module classes - -class VerilatedScope; +/// Base class for all Verilated module classes. class VerilatedModule VL_NOT_FINAL { VL_UNCOPYABLE(VerilatedModule); @@ -255,7 +254,7 @@ class VerilatedModule VL_NOT_FINAL { private: const char* m_namep; // Module name public: - explicit VerilatedModule(const char* namep); ///< Create module with given hierarchy name + explicit VerilatedModule(const char* namep); // Create module with given hierarchy name ~VerilatedModule(); const char* name() const { return m_namep; } ///< Return name of module }; @@ -286,7 +285,7 @@ public: #define VL_CELL(instname, type) ///< Declare a cell, ala SP_CELL -/// Declare a module, ala SC_MODULE +///< Declare a module, ala SC_MODULE #define VL_MODULE(modname) class modname VL_NOT_FINAL : public VerilatedModule // Not class final in VL_MODULE, as users might be abstracting our models (--hierarchical) @@ -470,6 +469,8 @@ public: int randSeed() const VL_MT_SAFE { return m_s.m_randSeed; } // Time handling + /// Returns current simulation time. + /// /// How Verilator runtime gets the current simulation time: /// /// * If using SystemC, time comes from the SystemC kernel-defined @@ -553,8 +554,8 @@ public: // But for internal use only }; //=========================================================================== -/// Verilator symbol table base class -/// Used for internal VPI implementation, and introspection into scopes +// Verilator symbol table base class +// Used for internal VPI implementation, and introspection into scopes class VerilatedSyms VL_NOT_FINAL { public: // But for internal use only @@ -569,8 +570,8 @@ public: // But for internal use only }; //=========================================================================== -/// Verilator scope information class -/// Used for internal VPI implementation, and introspection into scopes +// Verilator scope information class +// Used for internal VPI implementation, and introspection into scopes class VerilatedScope final { public: @@ -1008,18 +1009,18 @@ extern const char* vl_mc_scan_plusargs(const char* prefixp); // PLIish //========================================================================= // Base macros -/// Return true if data[bit] set; not 0/1 return, but 0/non-zero return. +// Return true if data[bit] set; not 0/1 return, but 0/non-zero return. #define VL_BITISSET_I(data, bit) ((data) & (VL_UL(1) << VL_BITBIT_I(bit))) #define VL_BITISSET_Q(data, bit) ((data) & (1ULL << VL_BITBIT_Q(bit))) #define VL_BITISSET_E(data, bit) ((data) & (VL_EUL(1) << VL_BITBIT_E(bit))) #define VL_BITISSET_W(data, bit) ((data)[VL_BITWORD_E(bit)] & (VL_EUL(1) << VL_BITBIT_E(bit))) #define VL_BITISSETLIMIT_W(data, width, bit) (((bit) < (width)) && VL_BITISSET_W(data, bit)) -/// Shift appropriate word by bit. Does not account for wrapping between two words +// Shift appropriate word by bit. Does not account for wrapping between two words #define VL_BITRSHIFT_W(data, bit) ((data)[VL_BITWORD_E(bit)] >> VL_BITBIT_E(bit)) -/// Create two 32-bit words from quadword -/// WData is always at least 2 words; does not clean upper bits +// Create two 32-bit words from quadword +// WData is always at least 2 words; does not clean upper bits #define VL_SET_WQ(owp, data) \ do { \ (owp)[0] = static_cast(data); \ @@ -1138,8 +1139,8 @@ extern int VL_TIME_STR_CONVERT(const char* strp) VL_PURE; # endif #endif -/// Return current simulation time #if defined(SYSTEMC_VERSION) +/// Return current simulation time // Already defined: extern sc_time sc_time_stamp(); inline vluint64_t vl_time_stamp64() { return sc_time_stamp().value(); } #else // Non-SystemC @@ -1187,8 +1188,8 @@ inline vluint64_t VerilatedContext::time() const VL_MT_SAFE { // Return time precision as multiplier of time units double vl_time_multiplier(int scale) VL_PURE; -/// Evaluate statement if debug enabled #ifdef VL_DEBUG +/// Evaluate statement if Verilated::debug() enabled # define VL_DEBUG_IF(stmt) \ do { \ if (VL_UNLIKELY(Verilated::debug())) {stmt} \ @@ -2768,7 +2769,7 @@ static inline WDataOutP VL_SEL_WWII(int obits, int lbits, int, int, WDataOutP ow //====================================================================== // Math needing insert/select -/// Return QData from double (numeric) +// Return QData from double (numeric) // EMIT_RULE: VL_RTOIROUND_Q_D: oclean=dirty; lclean==clean/real static inline QData VL_RTOIROUND_Q_D(int, double lhs) VL_PURE { // IEEE format: [63]=sign [62:52]=exp+1023 [51:0]=mantissa diff --git a/include/verilated_cov.cpp b/include/verilated_cov.cpp index c69a8c67f..3cc223236 100644 --- a/include/verilated_cov.cpp +++ b/include/verilated_cov.cpp @@ -444,6 +444,7 @@ void VerilatedCovContext::_insertf(const char* filename, int lineno) VL_MT_SAFE impp()->insertf(filename, lineno); } +#ifndef DOXYGEN #define K(n) const char* key##n #define A(n) const char *key##n, const char *valp##n // Argument list #define C(n) key##n, valp##n // Calling argument list @@ -493,6 +494,8 @@ void VerilatedCovContext::_insertp(A(0), A(1), K(2), int val2, K(3), int val3, K #undef N #undef K +#endif // DOXYGEN + //============================================================================= // VerilatedCov diff --git a/include/verilated_cov.h b/include/verilated_cov.h index 552c6c1c0..3217163c1 100644 --- a/include/verilated_cov.h +++ b/include/verilated_cov.h @@ -86,7 +86,7 @@ class VerilatedCovImp; covcontextp->_insertp("hier", name(), __VA_ARGS__)) //============================================================================= -/// Convert VL_COVER_INSERT value arguments to strings, is \internal +// Convert VL_COVER_INSERT value arguments to strings, is \internal template std::string vlCovCvtToStr(const T& t) VL_PURE { std::ostringstream os; @@ -96,7 +96,7 @@ template std::string vlCovCvtToStr(const T& t) VL_PURE { //============================================================================= // VerilatedCov -/// Verilator coverage per-context structure. +/// Per-VerilatedContext coverage data class. /// All public methods in this class are thread safe. /// /// This structure is accessed and constructed on first access via @@ -134,6 +134,7 @@ public: // But Internal use only // We could have just the maximum argument version, but this compiles // much slower (nearly 2x) than having smaller versions also. However // there's not much more gain in having a version for each number of args. +#ifndef DOXYGEN #define K(n) const char* key##n #define A(n) const char *key##n, const char *valp##n // Argument list #define D(n) const char *key##n = nullptr, const char *valp##n = nullptr // Argument list @@ -150,6 +151,7 @@ public: // But Internal use only #undef K #undef A #undef D +#endif // DOXYGEN protected: friend class VerilatedCovImp; @@ -165,7 +167,7 @@ protected: //============================================================================= // VerilatedCov -/// Verilator coverage global class +/// Coverage global class. /// /// Global class that accesses via current thread's context's /// VerilatedCovContext. This class is provided only for @@ -196,6 +198,6 @@ private: // Current thread's coverage structure static VerilatedCovContext* threadCovp() VL_MT_SAFE; }; -#endif +#endif // VL_NO_LEGACY #endif // Guard diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 786058f10..28c51c9cc 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -17,7 +17,6 @@ /// User wrapper code should use this header when creating FST traces. /// //============================================================================= -// SPDIFF_OFF #ifndef VERILATOR_VERILATED_FST_C_H_ #define VERILATOR_VERILATED_FST_C_H_ @@ -115,12 +114,14 @@ public: fstVarType vartype, bool array, int arraynum); }; +#ifndef DOXYGEN // Declare specialization here as it's used in VerilatedFstC just below template <> void VerilatedTrace::dump(vluint64_t timeui); template <> void VerilatedTrace::set_time_unit(const char* unitp); template <> void VerilatedTrace::set_time_unit(const std::string& unit); template <> void VerilatedTrace::set_time_resolution(const char* unitp); template <> void VerilatedTrace::set_time_resolution(const std::string& unit); +#endif //============================================================================= // VerilatedFstC diff --git a/include/verilated_heavy.h b/include/verilated_heavy.h index 83faf9f36..e89335434 100644 --- a/include/verilated_heavy.h +++ b/include/verilated_heavy.h @@ -88,12 +88,14 @@ public: }; //=================================================================== -// Verilog wide-number-in-array container -// Similar to std::array, but lighter weight, only methods needed -// by Verilator, to help compile time. -// -// This is only used when we need an upper-level container and so can't -// simply use a C style array (which is just a pointer). +/// Verilog wide unpacked bit container. +/// Similar to std::array, but lighter weight, only methods needed +/// by Verilator, to help compile time. +/// +/// For example a Verilog "bit [94:0]" will become a VlWide<3> because 3*32 +/// bits are needed to hold the 95 bits. The MSB (bit 96) must always be +/// zero in memory, but during intermediate operations in the Verilated +/// internals is unpredictable. template class VlWide final { EData m_storage[T_Words]; @@ -795,9 +797,12 @@ void VL_WRITEMEM_N(bool hex, int bits, const std::string& filename, } //=================================================================== -// Verilog packed array container -// For when a standard C++[] array is not sufficient, e.g. an -// array under a queue, or methods operating on the array +/// Verilog packed array container +/// For when a standard C++[] array is not sufficient, e.g. an +/// array under a queue, or methods operating on the array. +/// +/// This class may get exposed to a Verilated Model's top I/O, if the top +/// IO has an unpacked array. template class VlUnpacked final { private: @@ -849,7 +854,6 @@ std::string VL_TO_STRING(const VlUnpacked& obj) { // Verilog class reference container // There are no multithreaded locks on this; the base variable must // be protected by other means -// #define VlClassRef std::shared_ptr diff --git a/include/verilated_imp.h b/include/verilated_imp.h index e49db308f..e1b3d30da 100644 --- a/include/verilated_imp.h +++ b/include/verilated_imp.h @@ -49,7 +49,7 @@ class VerilatedScope; // Threaded message passing #ifdef VL_THREADED -/// Message, enqueued on an mtask, and consumed on the main eval thread +// Message, enqueued on an mtask, and consumed on the main eval thread class VerilatedMsg final { public: // TYPES @@ -75,13 +75,13 @@ public: VerilatedMsg& operator=(VerilatedMsg&&) = default; // METHODS vluint32_t mtaskId() const { return m_mtaskId; } - /// Execute the lambda function + // Execute the lambda function void run() const { m_cb(); } }; -/// Each thread has a queue it pushes to -/// This assumes no thread starts pushing the next tick until the previous has drained. -/// If more aggressiveness is needed, a double-buffered scheme might work well. +// Each thread has a queue it pushes to +// This assumes no thread starts pushing the next tick until the previous has drained. +// If more aggressiveness is needed, a double-buffered scheme might work well. class VerilatedEvalMsgQueue final { using VerilatedThreadQueue = std::multiset; @@ -102,13 +102,13 @@ private: public: // METHODS - //// Add message to queue (called by producer) + // Add message to queue (called by producer) void post(const VerilatedMsg& msg) VL_MT_SAFE_EXCLUDES(m_mutex) { const VerilatedLockGuard lock(m_mutex); m_queue.insert(msg); // Pass by value to copy the message into queue ++m_depth; } - /// Service queue until completion (called by consumer) + // Service queue until completion (called by consumer) void process() VL_MT_SAFE_EXCLUDES(m_mutex) { // Tracking m_depth is redundant to e.g. getting the mutex and looking at queue size, // but on the reader side it's 4x faster to test an atomic then getting a mutex @@ -133,7 +133,7 @@ public: } }; -/// Each thread has a local queue to build up messages until the end of the eval() call +// Each thread has a local queue to build up messages until the end of the eval() call class VerilatedThreadMsgQueue final { std::queue m_queue; @@ -154,7 +154,7 @@ private: } public: - /// Add message to queue, called by producer + // Add message to queue, called by producer static void post(const VerilatedMsg& msg) VL_MT_SAFE { // Handle calls to threaded routines outside // of any mtask -- if an initial block calls $finish, say. @@ -166,7 +166,7 @@ public: threadton().m_queue.push(msg); // Pass by value to copy the message into queue } } - /// Push all messages to the eval's queue + // Push all messages to the eval's queue static void flush(VerilatedEvalMsgQueue* evalMsgQp) VL_MT_SAFE { while (!threadton().m_queue.empty()) { evalMsgQp->post(threadton().m_queue.front()); @@ -204,7 +204,7 @@ class VerilatedContextImpData final { friend class VerilatedContextImp; protected: - /// Map of + // Map of // Used by scopeInsert, scopeFind, scopeErase, scopeNameMap mutable VerilatedMutex m_nameMutex; // Protect m_nameMap VerilatedScopeNameMap m_nameMap VL_GUARDED_BY(m_nameMutex); @@ -474,7 +474,7 @@ public: } public: // But only for verilated.cpp - /// Symbol table destruction cleans up the entries for each scope. + // Symbol table destruction cleans up the entries for each scope. static void userEraseScope(const VerilatedScope* scopep) VL_MT_SAFE { // Slow ok - called once/scope on destruction, so we simply iterate. const VerilatedLockGuard lock(s().m_userMapMutex); diff --git a/include/verilated_save.cpp b/include/verilated_save.cpp index 257a1f1f0..df5ada28c 100644 --- a/include/verilated_save.cpp +++ b/include/verilated_save.cpp @@ -50,9 +50,9 @@ // clang-format on // CONSTANTS -/// Value of first bytes of each file (must be multiple of 8 bytes) +// Value of first bytes of each file (must be multiple of 8 bytes) static const char* const VLTSAVE_HEADER_STR = "verilatorsave02\n"; -/// Value of last bytes of each file (must be multiple of 8 bytes) +// Value of last bytes of each file (must be multiple of 8 bytes) static const char* const VLTSAVE_TRAILER_STR = "vltsaved"; //============================================================================= diff --git a/include/verilated_save.h b/include/verilated_save.h index c2f5ec8a4..937e59524 100644 --- a/include/verilated_save.h +++ b/include/verilated_save.h @@ -29,7 +29,7 @@ //============================================================================= // VerilatedSerialize -/// Convert structures to a stream representation. +/// Class for writing serialization of structures to a stream representation. /// /// User wrapper code will more typically use VerilatedSave which uses this /// as a subclass to write a file. @@ -100,7 +100,7 @@ private: //============================================================================= // VerilatedDeserialize -/// Load structures from a stream representation +/// Class for loading structures from a stream representation. /// /// User wrapper code will more typically use VerilatedRestore which uses /// this as a subclass to a read from a file. diff --git a/include/verilated_syms.h b/include/verilated_syms.h index 71f01ecea..1dc633e6e 100644 --- a/include/verilated_syms.h +++ b/include/verilated_syms.h @@ -1,5 +1,5 @@ -// -*- mode: C++; c-file-style: "cc-mode" -*- -//************************************************************************* +// -*- mode: C++; c-file-style: "cc-mode" +//-*- ************************************************************************* // // Code available from: https://verilator.org // @@ -18,6 +18,9 @@ /// the symbol table. It is not included in verilated.h (instead see /// verilated_sym_props.h) as it requires some heavyweight C++ classes. /// +/// These classes are rarely used by user code; typical user code will +/// instead use the VPI to access this information. +/// /// These classes are thread safe and read only. It is constructed only /// when a model is built (from the main thread). /// @@ -35,14 +38,14 @@ #include //====================================================================== -/// Types +// Types -/// Class to sort maps keyed by const char*'s +// Class to sort maps keyed by const char*'s struct VerilatedCStrCmp { bool operator()(const char* a, const char* b) const { return std::strcmp(a, b) < 0; } }; -/// Map of sorted scope names to find associated scope class +// Map of sorted scope names to find associated scope class // This is a class instead of typedef/using to allow forward declaration in verilated.h class VerilatedScopeNameMap final : public std::map { @@ -51,7 +54,7 @@ public: ~VerilatedScopeNameMap() = default; }; -/// Map of sorted variable names to find associated variable class +// Map of sorted variable names to find associated variable class // This is a class instead of typedef/using to allow forward declaration in verilated.h class VerilatedVarNameMap final : public std::map { public: @@ -59,7 +62,7 @@ public: ~VerilatedVarNameMap() = default; }; -/// Map of parent scope to vector of children scopes +// Map of parent scope to vector of children scopes // This is a class instead of typedef/using to allow forward declaration in verilated.h class VerilatedHierarchyMap final : public std::unordered_map> { diff --git a/include/verilated_vcd_c.h b/include/verilated_vcd_c.h index 0e5e2e336..f9d07a731 100644 --- a/include/verilated_vcd_c.h +++ b/include/verilated_vcd_c.h @@ -17,7 +17,6 @@ /// User wrapper code should use this header when creating VCD traces. /// //============================================================================= -// SPDIFF_OFF #ifndef VERILATOR_VERILATED_VCD_C_H_ #define VERILATOR_VERILATED_VCD_C_H_ @@ -31,20 +30,25 @@ class VerilatedVcd; -// SPDIFF_ON //============================================================================= // VerilatedFile -/// File handling routines, which can be overrode for e.g. socket I/O +/// Class representing a file to write to. These virtual methods can be +/// overrode for e.g. socket I/O. class VerilatedVcdFile VL_NOT_FINAL { private: int m_fd = 0; // File descriptor we're writing to public: // METHODS + /// Construct a (as yet) closed file VerilatedVcdFile() = default; + /// Close and destruct virtual ~VerilatedVcdFile() = default; + /// Open a file with given filename virtual bool open(const std::string& name) VL_MT_UNSAFE; + /// Close object's file virtual void close() VL_MT_UNSAFE; + /// Write data to file (if it is open) virtual ssize_t write(const char* bufp, ssize_t len) VL_MT_UNSAFE; }; @@ -318,17 +322,19 @@ public: #endif // VL_TRACE_VCD_OLD_API }; +#ifndef DOXYGEN // Declare specializations here they are used in VerilatedVcdC just below template <> void VerilatedTrace::dump(vluint64_t timeui); template <> void VerilatedTrace::set_time_unit(const char* unitp); template <> void VerilatedTrace::set_time_unit(const std::string& unit); template <> void VerilatedTrace::set_time_resolution(const char* unitp); template <> void VerilatedTrace::set_time_resolution(const std::string& unit); +#endif // DOXYGEN //============================================================================= // VerilatedVcdC -/// Create a VCD dump file in C standalone (no SystemC) simulations. -/// Also derived for use in SystemC simulations. +/// Class representing a VCD dump file in C standalone (no SystemC) +/// simulations. Also derived for use in SystemC simulations. class VerilatedVcdC VL_NOT_FINAL { VerilatedVcd m_sptrace; // Trace file being created diff --git a/include/verilated_vcd_sc.h b/include/verilated_vcd_sc.h index bfe1bd1fa..415f1911c 100644 --- a/include/verilated_vcd_sc.h +++ b/include/verilated_vcd_sc.h @@ -29,8 +29,9 @@ //============================================================================= // VerilatedVcdSc /// -/// This class creates a Verilator-friendly VCD trace format with the -/// SystemC simulation kernel, just like a SystemC-documented trace format. +/// Class representing a Verilator-friendly VCD trace format registered +/// with the SystemC simulation kernel, just like a SystemC-documented +/// trace format. class VerilatedVcdSc final : sc_trace_file, public VerilatedVcdC { // CONSTRUCTORS diff --git a/include/verilated_vpi.h b/include/verilated_vpi.h index d24600498..1d1e9d4ce 100644 --- a/include/verilated_vpi.h +++ b/include/verilated_vpi.h @@ -35,6 +35,8 @@ //====================================================================== +/// Class for namespace-like groupng of Verilator VPI functions. + class VerilatedVpi final { public: /// Call timed callbacks. diff --git a/include/verilatedos.h b/include/verilatedos.h index 54a22ef7e..8a890af8f 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -71,31 +71,31 @@ // Defaults for unsupported compiler features #ifndef VL_ATTR_ALIGNED -# define VL_ATTR_ALIGNED(alignment) ///< Align structure to specified byte alignment +# define VL_ATTR_ALIGNED(alignment) ///< Attribute to align structure to byte alignment #endif #ifndef VL_ATTR_ALWINLINE -# define VL_ATTR_ALWINLINE ///< Inline, even when not optimizing +# define VL_ATTR_ALWINLINE ///< Attribute to inline, even when not optimizing #endif #ifndef VL_ATTR_COLD -# define VL_ATTR_COLD ///< Function is rarely executed +# define VL_ATTR_COLD ///< Attribute that function is rarely executed #endif #ifndef VL_ATTR_HOT -# define VL_ATTR_HOT ///< Function is highly executed +# define VL_ATTR_HOT ///< Attribute that function is highly executed #endif #ifndef VL_ATTR_NORETURN -# define VL_ATTR_NORETURN ///< Function does not ever return +# define VL_ATTR_NORETURN ///< Attribute that function does not ever return #endif #ifndef VL_ATTR_PRINTF -# define VL_ATTR_PRINTF(fmtArgNum) ///< Function with printf format checking +# define VL_ATTR_PRINTF(fmtArgNum) ///< Attribute for function with printf format checking #endif #ifndef VL_ATTR_PURE -# define VL_ATTR_PURE ///< Function is pure (and thus also VL_MT_SAFE) +# define VL_ATTR_PURE ///< Attribute that function is pure (and thus also VL_MT_SAFE) #endif #ifndef VL_ATTR_UNUSED -# define VL_ATTR_UNUSED ///< Function that may be never used +# define VL_ATTR_UNUSED ///< Attribute that function that may be never used #endif #ifndef VL_ATTR_WEAK -# define VL_ATTR_WEAK ///< Function external that is optionally defined +# define VL_ATTR_WEAK ///< Attribute that function external that is optionally defined #endif #ifndef VL_CAPABILITY # define VL_ACQUIRE(...) ///< Function requires a capability/lock (-fthread-safety) @@ -111,19 +111,19 @@ # define VL_SCOPED_CAPABILITY ///< Scoped threaded capability/lock (-fthread-safety) #endif #ifndef VL_LIKELY -# define VL_LIKELY(x) (!!(x)) ///< Boolean expression more often true than false -# define VL_UNLIKELY(x) (!!(x)) ///< Boolean expression more often false than true +# define VL_LIKELY(x) (!!(x)) ///< Return boolean expression that is more often true +# define VL_UNLIKELY(x) (!!(x)) ///< Return boolean expression that is more often false #endif /// Boolean expression never hit by users (branch coverage disabled) # define VL_UNCOVERABLE(x) VL_UNLIKELY(x) #ifndef VL_UNREACHABLE -# define VL_UNREACHABLE ///< Point that may never be reached +# define VL_UNREACHABLE ///< Statement that may never be reached (for coverage etc) #endif #ifndef VL_PREFETCH_RD -# define VL_PREFETCH_RD(p) ///< Prefetch pointed-to-data with read intent +# define VL_PREFETCH_RD(p) ///< Prefetch pointer argument with read intent #endif #ifndef VL_PREFETCH_RW -# define VL_PREFETCH_RW(p) ///< Prefetch pointed-to-data with read/write intent +# define VL_PREFETCH_RW(p) ///< Prefetch pointer argument with read/write intent #endif #if defined(VL_THREADED) && !defined(VL_CPPCHECK) @@ -136,9 +136,9 @@ # else # error "Unsupported compiler for VL_THREADED: No thread-local declarator" # endif -# define VL_THREAD_LOCAL thread_local ///< "thread_local" when supported +# define VL_THREAD_LOCAL thread_local // "thread_local" when supported #else -# define VL_THREAD_LOCAL ///< "thread_local" when supported +# define VL_THREAD_LOCAL // "thread_local" when supported #endif #ifndef VL_NO_LEGACY @@ -147,27 +147,27 @@ # define VL_STATIC_OR_THREAD static // Deprecated #endif -/// Comment tag that Function is pure (and thus also VL_MT_SAFE) +// Comment tag that Function is pure (and thus also VL_MT_SAFE) #define VL_PURE -/// Comment tag that function is threadsafe when VL_THREADED +// Comment tag that function is threadsafe when VL_THREADED #define VL_MT_SAFE -/// Comment tag that function is threadsafe when VL_THREADED, only -/// during normal operation (post-init) +// Comment tag that function is threadsafe when VL_THREADED, only +// during normal operation (post-init) #define VL_MT_SAFE_POSTINIT -/// Clang threadsafe and uses given mutex +// Attribute that function is clang threadsafe and uses given mutex #define VL_MT_SAFE_EXCLUDES(mutex) VL_EXCLUDES(mutex) -/// Comment tag that function is not threadsafe when VL_THREADED +// Comment tag that function is not threadsafe when VL_THREADED #define VL_MT_UNSAFE -/// Comment tag that function is not threadsafe when VL_THREADED, -/// protected to make sure single-caller +// Comment tag that function is not threadsafe when VL_THREADED, +// protected to make sure single-caller #define VL_MT_UNSAFE_ONE #ifndef VL_NO_LEGACY # define VL_ULL(c) (c##ULL) // Add appropriate suffix to 64-bit constant (deprecated) #endif -/// Convert argument to IData -/// This is not necessarily the same as #UL, depending on what the IData typedef is. +// Convert argument to IData +// This is not necessarily the same as "#UL", depending on what the IData typedef is. #define VL_UL(c) (static_cast(c##UL)) #if defined(VL_CPPCHECK) || defined(__clang_analyzer__) || __cplusplus < 201103L @@ -235,7 +235,7 @@ extern "C" { void __gcov_flush(); // gcc sources gcc/gcov-io.h has the prototype } -/// Flush internal code coverage data before e.g. std::abort() +// Flush internal code coverage data before e.g. std::abort() # define VL_GCOV_FLUSH() \ __gcov_flush() #else @@ -390,20 +390,20 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type # define VL_WORDSIZE VL_IDATASIZE // Legacy define #endif -/// Bytes this number of bits needs (1 bit=1 byte) +/// Return number of bytes argument-number of bits needs (1 bit=1 byte) #define VL_BYTES_I(nbits) (((nbits) + (VL_BYTESIZE - 1)) / VL_BYTESIZE) -/// Words/EDatas this number of bits needs (1 bit=1 word) +/// Return Words/EDatas in argument-number of bits needs (1 bit=1 word) #define VL_WORDS_I(nbits) (((nbits) + (VL_EDATASIZE - 1)) / VL_EDATASIZE) -/// Words/EDatas a quad requires +// Number of Words/EDatas a quad requires #define VL_WQ_WORDS_E VL_WORDS_I(VL_QUADSIZE) //========================================================================= // Class definition helpers -/// Comment tag to indicate a base class, e.g. cannot label "class final" +// Comment tag to indicate a base class, e.g. cannot label "class final" #define VL_NOT_FINAL -/// Declare a class as uncopyable; put after a private: +// Declare a class as uncopyable; put after a private: #define VL_UNCOPYABLE(Type) \ Type(const Type& other) = delete; \ Type& operator=(const Type&) = delete @@ -421,14 +421,14 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type #define VL_SIZEBITS_Q (VL_QUADSIZE - 1) ///< Bit mask for bits in a quad #define VL_SIZEBITS_E (VL_EDATASIZE - 1) ///< Bit mask for bits in a quad -/// Mask for words with 1's where relevant bits are (0=all bits) +/// Return mask for words with 1's where relevant bits are (0=all bits) #define VL_MASK_I(nbits) (((nbits) & VL_SIZEBITS_I) ? ((1U << ((nbits) & VL_SIZEBITS_I)) - 1) : ~0) -/// Mask for quads with 1's where relevant bits are (0=all bits) +/// Return mask for quads with 1's where relevant bits are (0=all bits) #define VL_MASK_Q(nbits) \ (((nbits) & VL_SIZEBITS_Q) ? ((1ULL << ((nbits) & VL_SIZEBITS_Q)) - 1ULL) : ~0ULL) -/// Mask for EData with 1's where relevant bits are (0=all bits) +/// Return mask for EData with 1's where relevant bits are (0=all bits) #define VL_MASK_E(nbits) VL_MASK_I(nbits) -#define VL_EUL(n) VL_UL(n) ///< Make constant number EData sized +#define VL_EUL(n) VL_UL(n) // Make constant number EData sized #define VL_BITWORD_I(bit) ((bit) / VL_IDATASIZE) ///< Word number for sv DPI vectors #define VL_BITWORD_E(bit) ((bit) >> VL_EDATASIZE_LOG2) ///< Word number for a wide quantity @@ -451,9 +451,9 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type //========================================================================= // Performance counters -/// The vluint64_t argument is loaded with a high-performance counter for profiling -/// or 0x0 if not implemented on this platform #if defined(__i386__) || defined(__x86_64__) +// The vluint64_t argument is loaded with a high-performance counter for profiling +// or 0x0 if not implemented on this platform #define VL_RDTSC(val) \ { \ vluint32_t hi, lo; \ @@ -477,8 +477,8 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type # include "Windows.h" # define VL_CPU_RELAX() YieldProcessor() # elif defined(__i386__) || defined(__x86_64__) || defined(VL_CPPCHECK) -/// For more efficient busy waiting on SMT CPUs, let the processor know -/// we're just waiting so it can let another thread run +// For more efficient busy waiting on SMT CPUs, let the processor know +// we're just waiting so it can let another thread run # define VL_CPU_RELAX() asm volatile("rep; nop" ::: "memory") # elif defined(__ia64__) # define VL_CPU_RELAX() asm volatile("hint @pause" ::: "memory") From 014bffdf5ec4025ed46d55996f2871db092ecd4f Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 12:47:35 -0400 Subject: [PATCH 056/110] CI: Run coverage with SystemC --- .github/workflows/coverage.yml | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/.github/workflows/coverage.yml b/.github/workflows/coverage.yml index bfa7e98ac..81ce290f8 100644 --- a/.github/workflows/coverage.yml +++ b/.github/workflows/coverage.yml @@ -62,7 +62,17 @@ jobs: test: - vlt- - vltmt- - num: [ 0 1 2 3 4 5 6 7 8 9 ] + num: + - 0 + - 1 + - 2 + - 3 + - 4 + - 5 + - 6 + - 7 + - 8 + - 9 include: - { test: dist, num: '' } runs-on: ubuntu-20.04 From d6c2e2faf622649755fc80cc96c3b4a9c973c9bd Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Mon, 29 Mar 2021 00:57:36 +0100 Subject: [PATCH 057/110] Allow overlaps in priority case statements (#2864) This will still warn if a case item is completely covered by previous items, but will no longer complain about overlaps like this: priority casez (foo_i) 2'b ?1: bar_o = 3'd0; 2'b 1?: bar_o = 3'd1; Before, there was a warning for the second statement because the first two patterns match 2'b11. --- src/V3Case.cpp | 47 +++++++++++++++++++++------- test_regress/t/t_priority_case.out | 8 +++++ test_regress/t/t_priority_case.pl | 19 ++++++++++++ test_regress/t/t_priority_case.v | 50 ++++++++++++++++++++++++++++++ 4 files changed, 113 insertions(+), 11 deletions(-) create mode 100644 test_regress/t/t_priority_case.out create mode 100755 test_regress/t/t_priority_case.pl create mode 100644 test_regress/t/t_priority_case.v diff --git a/src/V3Case.cpp b/src/V3Case.cpp index 1b3122d7d..23653a592 100644 --- a/src/V3Case.cpp +++ b/src/V3Case.cpp @@ -159,11 +159,13 @@ private: return false; // Too wide for analysis } UINFO(8, "Simple case statement: " << nodep << endl); + uint32_t numCases = 1UL << m_caseWidth; // Zero list of items for each value - for (uint32_t i = 0; i < (1UL << m_caseWidth); ++i) m_valueItem[i] = nullptr; + for (uint32_t i = 0; i < numCases; ++i) m_valueItem[i] = nullptr; // Now pick up the values for each assignment // We can cheat and use uint32_t's because we only support narrow case's - bool bitched = false; + bool reportedOverlap = false; + bool reportedSubcase = false; for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp = VN_CAST(itemp->nextp(), CaseItem)) { for (AstNode* icondp = itemp->condsp(); icondp; icondp = icondp->nextp()) { @@ -179,29 +181,52 @@ private: V3Number numval(itemp, iconstp->width()); numval.opBitsOne(iconstp->num()); uint32_t val = numval.toUInt(); - for (uint32_t i = 0; i < (1UL << m_caseWidth); ++i) { + + uint32_t firstOverlap = 0; + bool foundOverlap = false; + bool foundHit = false; + for (uint32_t i = 0; i < numCases; ++i) { if ((i & mask) == val) { if (!m_valueItem[i]) { m_valueItem[i] = itemp; - } else if (!itemp->ignoreOverlap() && !bitched) { - icondp->v3warn(CASEOVERLAP, - "Case values overlap (example pattern 0x" - << std::hex << i << ")"); - bitched = true; + foundHit = true; + } else if (!foundOverlap && !itemp->ignoreOverlap()) { + firstOverlap = i; + foundOverlap = true; m_caseNoOverlapsAllCovered = false; } } } + if (!nodep->priorityPragma()) { + // If this case statement doesn't have the priority + // keyword, we want to warn on any overlap. + if (!reportedOverlap && foundOverlap) { + icondp->v3warn(CASEOVERLAP, "Case values overlap (example pattern 0x" + << std::hex << firstOverlap << ")"); + reportedOverlap = true; + } + } else { + // If this is a priority case, we only want to complain + // if every possible value for this item is already hit + // by some other item. This is true if foundHit is + // false. + if (!reportedSubcase && !foundHit) { + icondp->v3warn(CASEOVERLAP, + "Case item ignored: every matching value is covered " + "by an earlier item"); + reportedSubcase = true; + } + } } } // Defaults were moved to last in the caseitem list by V3LinkDot if (itemp->isDefault()) { // Case statement's default... Fill the table - for (uint32_t i = 0; i < (1UL << m_caseWidth); ++i) { + for (uint32_t i = 0; i < numCases; ++i) { if (!m_valueItem[i]) m_valueItem[i] = itemp; } } } - for (uint32_t i = 0; i < (1UL << m_caseWidth); ++i) { + for (uint32_t i = 0; i < numCases; ++i) { if (!m_valueItem[i]) { nodep->v3warn(CASEINCOMPLETE, "Case values incompletely covered " "(example pattern 0x" @@ -218,7 +243,7 @@ private: // Convert valueItem from AstCaseItem* to the expression // Not done earlier, as we may now have a nullptr because it's just a ";" NOP branch - for (uint32_t i = 0; i < (1UL << m_caseWidth); ++i) { + for (uint32_t i = 0; i < numCases; ++i) { m_valueItem[i] = VN_CAST(m_valueItem[i], CaseItem)->bodysp(); } return true; // All is fine diff --git a/test_regress/t/t_priority_case.out b/test_regress/t/t_priority_case.out new file mode 100644 index 000000000..f3e336f9d --- /dev/null +++ b/test_regress/t/t_priority_case.out @@ -0,0 +1,8 @@ +%Warning-CASEOVERLAP: t/t_priority_case.v:34:7: Case item ignored: every matching value is covered by an earlier item + 34 | 2'b ?1: out1 = 3'd1; + | ^~~~~~ + ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. +%Warning-CASEOVERLAP: t/t_priority_case.v:44:7: Case item ignored: every matching value is covered by an earlier item + 44 | 2'b ?1: out1 = 3'd1; + | ^~~~~~ +%Error: Exiting due to diff --git a/test_regress/t/t_priority_case.pl b/test_regress/t/t_priority_case.pl new file mode 100755 index 000000000..4f29861db --- /dev/null +++ b/test_regress/t/t_priority_case.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_priority_case.v b/test_regress/t/t_priority_case.v new file mode 100644 index 000000000..477752748 --- /dev/null +++ b/test_regress/t/t_priority_case.v @@ -0,0 +1,50 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Rupert Swarbrick. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + value + ); + input [1:0] value; + + sub u_sub(.value(value), .out0(), .out1()); + +endmodule + +module sub (input logic [1:0] value, + output logic [2:0] out0, + output logic [2:0] out1); + + always_comb begin + // This case statement shouldn't cause any warnings. Although the cases overlap (2'b11 matches + // both 2'b?1 and 2'b1?), the second item matches 2'b10 and the first one doesn't. + priority casez (value) + 2'b ?1: out0 = 3'd0; + 2'b 1?: out0 = 3'd1; + default: out0 = 3'd2; + endcase + + // This case statement *should* cause a warning: the second case is completely covered by the + // first. + priority casez (value) + 2'b ?1: out1 = 3'd0; + 2'b ?1: out1 = 3'd1; + default: out1 = 3'd2; + endcase + + // This case statement should cause a warning too: the second case and third cases are + // completely covered by the first. But it should only cause one: like with overlapping cases, + // we assume that the author messed up the first case, so there's no real benefit to reporting + // each thing it subsumes. + priority casez (value) + 2'b ?1: out1 = 3'd0; + 2'b ?1: out1 = 3'd1; + 2'b 11: out1 = 3'd2; + default: out1 = 3'd3; + endcase + end + +endmodule From 2ca21c01d266c2f83b4c0771510ab59a89c665e9 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 14:05:16 -0400 Subject: [PATCH 058/110] Internal coverage improvements --- nodist/code_coverage.dat | 3 ++- src/V3Ast.h | 1 - src/V3AstNodes.cpp | 41 ------------------------------- src/V3Task.cpp | 1 - src/V3Width.cpp | 2 +- test_regress/t/t_debug_emitv.out | 23 +++++++++++++++++ test_regress/t/t_debug_emitv.v | 42 ++++++++++++++++---------------- test_regress/t/t_past_bad.out | 16 +++++++++--- test_regress/t/t_past_bad.v | 9 +++++-- 9 files changed, 66 insertions(+), 72 deletions(-) diff --git a/nodist/code_coverage.dat b/nodist/code_coverage.dat index 14f516a59..d725dad4b 100644 --- a/nodist/code_coverage.dat +++ b/nodist/code_coverage.dat @@ -56,7 +56,8 @@ exclude_line_regexp(r'\bUINFO\b') # Exclude for branch coverage only exclude_branch_regexp(r'\bdebug\(\)') exclude_branch_regexp(r'\bassert\(') -exclude_branch_regexp(r'\bBROKEN_RTK\(') +exclude_branch_regexp(r'\bBROKEN_BASE_RTN\(') +exclude_branch_regexp(r'\bBROKEN_RTN\(') exclude_branch_regexp(r'\bSELF_CHECK') True diff --git a/src/V3Ast.h b/src/V3Ast.h index abf9474cc..d1a4709b5 100644 --- a/src/V3Ast.h +++ b/src/V3Ast.h @@ -2450,7 +2450,6 @@ public: bool widthSized() const { return !m_widthMin || m_widthMin == m_width; } bool generic() const { return m_generic; } void generic(bool flag) { m_generic = flag; } - AstNodeDType* dtypeDimensionp(int dimension); std::pair dimensions(bool includeBasic); uint32_t arrayUnpackedElements(); // 1, or total multiplication of all dimensions static int uniqueNumInc() { return ++s_uniqueNum; } diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp index c317b99ea..a5c17b50a 100644 --- a/src/V3AstNodes.cpp +++ b/src/V3AstNodes.cpp @@ -694,47 +694,6 @@ AstNodeDType::CTypeRecursed AstNodeDType::cTypeRecurse(bool compound) const { return info; } -AstNodeDType* AstNodeDType::dtypeDimensionp(int dimension) { - // dimension passed from AstArraySel::dimension - // Dimension 0 means the VAR itself, 1 is the closest SEL to the AstVar, - // which is the lowest in the dtype list. - // ref order: a[1][2][3][4] - // Created as: reg [4] a [1][2][3]; - // *or* reg a [1][2][3][4]; - // // The bit select is optional; used only if "leftover" []'s - // SEL: SEL4(SEL3(SEL2(SEL1(VARREF0 a)))) - // DECL: VAR a (ARRAYSEL0 (ARRAYSEL1 (ARRAYSEL2 (DT RANGE3)))) - // *or* VAR a (ARRAYSEL0 (ARRAYSEL1 (ARRAYSEL2 (ARRAYSEL3 (DT)))) - // SEL1 needs to select from entire variable which is a pointer to ARRAYSEL0 - // TODO this function should be removed in favor of recursing the dtype(), - // as that allows for more complicated data types. - int dim = 0; - for (AstNodeDType* dtypep = this; dtypep;) { - dtypep = dtypep->skipRefp(); // Skip AstRefDType/AstTypedef, or return same node - if (AstNodeArrayDType* adtypep = VN_CAST(dtypep, NodeArrayDType)) { - if ((dim++) == dimension) return dtypep; - dtypep = adtypep->subDTypep(); - continue; - } else if (AstBasicDType* adtypep = VN_CAST(dtypep, BasicDType)) { - // AstBasicDType - nothing below, return null - if (adtypep->isRanged()) { - // cppcheck-suppress unreadVariable // Cppcheck bug - thinks dim isn't used - if ((dim++) == dimension) return adtypep; - } - return nullptr; - } else if (AstNodeUOrStructDType* adtypep = VN_CAST(dtypep, NodeUOrStructDType)) { - if (adtypep->packed()) { - // cppcheck-suppress unreadVariable // Cppcheck bug - thinks dim isn't used - if ((dim++) == dimension) return adtypep; - } - return nullptr; - } - // Node no ->next in loop; use continue where necessary - break; - } - return nullptr; -} - uint32_t AstNodeDType::arrayUnpackedElements() { uint32_t entries = 1; for (AstNodeDType* dtypep = this; dtypep;) { diff --git a/src/V3Task.cpp b/src/V3Task.cpp index 192e93b40..66cbd18b3 100644 --- a/src/V3Task.cpp +++ b/src/V3Task.cpp @@ -66,7 +66,6 @@ public: AstNodeFTask* nodep() const { return m_nodep; } virtual string name() const override { return nodep()->name(); } virtual string dotColor() const override { return pure() ? "black" : "red"; } - virtual FileLine* fileline() const override { return nodep()->fileline(); } AstCFunc* cFuncp() const { return m_cFuncp; } void cFuncp(AstCFunc* nodep) { m_cFuncp = nodep; } }; diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 9128ce4c2..06381e587 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -1091,7 +1091,7 @@ private: iterateCheckSizedSelf(nodep, "Ticks", nodep->ticksp(), SELF, BOTH); V3Const::constifyParamsEdit(nodep->ticksp()); // ticksp may change const AstConst* constp = VN_CAST(nodep->ticksp(), Const); - if (!constp || constp->toSInt() < 1) { + if (!constp) { nodep->v3error("$past tick value must be constant (IEEE 1800-2017 16.9.3)"); nodep->ticksp()->unlinkFrBack()->deleteTree(); } else if (constp->toSInt() < 1) { diff --git a/test_regress/t/t_debug_emitv.out b/test_regress/t/t_debug_emitv.out index 50ed186bf..e37daa2fd 100644 --- a/test_regress/t/t_debug_emitv.out +++ b/test_regress/t/t_debug_emitv.out @@ -9,6 +9,7 @@ module Vt_debug_emitv; signed int [31:0] t.cyc; signed int [31:0] t.fo; signed int [31:0] t.sum; + signed real t.r; string t.str; signed int [31:0] t._Vpast_0_0; signed int [31:0] t._Vpast_1_0; @@ -57,6 +58,7 @@ module Vt_debug_emitv; end always @(posedge clk)@(negedge clk) begin __Vdly__t.cyc <= (32'sh1 + t.cyc); + __Vdly__t.r <= (0.01 + t.r); t.fo = t.cyc; // Function: inc __Vtask_t.sub.inc__2__i = t.fo; @@ -178,6 +180,24 @@ module Vt_debug_emitv; t.sum = ???? // RAND 32'sha; + $display("%g", $log10(t.r)); + $display("%g", $ln(t.r)); + $display("%g", $exp(t.r)); + $display("%g", $sqrt(t.r)); + $display("%g", $floor(t.r)); + $display("%g", $ceil(t.r)); + $display("%g", $sin(t.r)); + $display("%g", $cos(t.r)); + $display("%g", $tan(t.r)); + $display("%g", $asin(t.r)); + $display("%g", $acos(t.r)); + $display("%g", $atan(t.r)); + $display("%g", $sinh(t.r)); + $display("%g", $cosh(t.r)); + $display("%g", $tanh(t.r)); + $display("%g", $asinh(t.r)); + $display("%g", $acosh(t.r)); + $display("%g", $atanh(t.r)); end /*verilator public_flat_rw @(posedge clk)@(negedge clk) t.pubflat*/ @@ -191,6 +211,8 @@ module Vt_debug_emitv; t._Vpast_1_0 = __Vdly__t._Vpast_1_0; __Vdly__t._Vpast_0_0 = t._Vpast_0_0; t._Vpast_0_0 = __Vdly__t._Vpast_0_0; + __Vdly__t.r = t.r; + t.r = __Vdly__t.r; __Vdly__t.cyc = t.cyc; t.cyc = __Vdly__t.cyc; __Vdly__t.pubflat_r = t.pubflat_r; @@ -204,6 +226,7 @@ module Vt_debug_emitv; signed int [31:0] __Vfunc_t.sub.f__3__v; logic [15:0] __Vdly__t.pubflat_r; signed int [31:0] __Vdly__t.cyc; + signed real __Vdly__t.r; signed int [31:0] __Vdly__t._Vpast_0_0; signed int [31:0] __Vdly__t._Vpast_1_0; endmodule diff --git a/test_regress/t/t_debug_emitv.v b/test_regress/t/t_debug_emitv.v index 9ab85d288..f8ebe44ac 100644 --- a/test_regress/t/t_debug_emitv.v +++ b/test_regress/t/t_debug_emitv.v @@ -107,9 +107,11 @@ module t (/*AUTOARG*/ int cyc; int fo; int sum; + real r; string str; always_ff @ (posedge clk) begin cyc <= cyc + 1; + r <= r + 0.01; fo = cyc; sub.inc(fo, sum); sum = sub.f(sum); @@ -176,6 +178,25 @@ module t (/*AUTOARG*/ if (Pkg::PKG_PARAM != 1) $stop; sub.r = 62.0; + + $display("%g", $log10(r)); + $display("%g", $ln(r)); + $display("%g", $exp(r)); + $display("%g", $sqrt(r)); + $display("%g", $floor(r)); + $display("%g", $ceil(r)); + $display("%g", $sin(r)); + $display("%g", $cos(r)); + $display("%g", $tan(r)); + $display("%g", $asin(r)); + $display("%g", $acos(r)); + $display("%g", $atan(r)); + $display("%g", $sinh(r)); + $display("%g", $cosh(r)); + $display("%g", $tanh(r)); + $display("%g", $asinh(r)); + $display("%g", $acosh(r)); + $display("%g", $atanh(r)); end endmodule @@ -188,27 +209,6 @@ module sub(); return {31'd0, v[2]} + 32'd1; endfunction real r; - initial begin - r = 1.0; - r = $log10(r); - r = $ln(r); - r = $exp(r); - r = $sqrt(r); - r = $floor(r); - r = $ceil(r); - r = $sin(r); - r = $cos(r); - r = $tan(r); - r = $asin(r); - r = $acos(r); - r = $atan(r); - r = $sinh(r); - r = $cosh(r); - r = $tanh(r); - r = $asinh(r); - r = $acosh(r); - r = $atanh(r); - end endmodule package p; diff --git a/test_regress/t/t_past_bad.out b/test_regress/t/t_past_bad.out index 86d72e272..39a14b562 100644 --- a/test_regress/t/t_past_bad.out +++ b/test_regress/t/t_past_bad.out @@ -1,10 +1,18 @@ -%Error: t/t_past_bad.v:12:11: $past tick value must be constant (IEEE 1800-2017 16.9.3) +%Error: t/t_past_bad.v:16:20: Expecting expression to be constant, but variable isn't const: 'num' : ... In instance t - 12 | if ($past(d, 0)) $stop; + 16 | if ($past(d, num)) $stop; + | ^~~ +%Error: t/t_past_bad.v:16:11: $past tick value must be constant (IEEE 1800-2017 16.9.3) + : ... In instance t + 16 | if ($past(d, num)) $stop; | ^~~~~ -%Warning-TICKCOUNT: t/t_past_bad.v:13:20: $past tick value of 10000 may have a large performance cost +%Error: t/t_past_bad.v:17:20: $past tick value must be >= 1 (IEEE 1800-2017 16.9.3) + : ... In instance t + 17 | if ($past(d, 0)) $stop; + | ^ +%Warning-TICKCOUNT: t/t_past_bad.v:18:20: $past tick value of 10000 may have a large performance cost : ... In instance t - 13 | if ($past(d, 10000)) $stop; + 18 | if ($past(d, 10000)) $stop; | ^~~~~ ... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_past_bad.v b/test_regress/t/t_past_bad.v index e8ffae7de..ed4462350 100644 --- a/test_regress/t/t_past_bad.v +++ b/test_regress/t/t_past_bad.v @@ -4,12 +4,17 @@ // any use, without warranty, 2018 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 -module t (d, clk); +module t (/*AUTOARG*/ + // Inputs + d, clk, num + ); input d; input clk; + input int num; always @ (posedge clk) begin - if ($past(d, 0)) $stop; // IEEE 16.9.3 must be >- 0 + if ($past(d, num)) $stop; // IEEE 16.9.3 must be const + if ($past(d, 0)) $stop; // IEEE 16.9.3 must be >= 0 if ($past(d, 10000)) $stop; // TICKCOUNT end endmodule From f26a7c2a5d281fa6bc7cd134c7c48d30e69c66b8 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 20:18:18 -0400 Subject: [PATCH 059/110] Fix --comp-limit-parens with real data types --- src/V3Depth.cpp | 10 ++------- test_regress/t/t_flag_comp_limit_parens.pl | 24 ++++++++++++++++++++++ test_regress/t/t_flag_comp_limit_parens.v | 19 +++++++++++++++++ 3 files changed, 45 insertions(+), 8 deletions(-) create mode 100755 test_regress/t/t_flag_comp_limit_parens.pl create mode 100644 test_regress/t/t_flag_comp_limit_parens.v diff --git a/src/V3Depth.cpp b/src/V3Depth.cpp index 4f8be0f75..5ff517a62 100644 --- a/src/V3Depth.cpp +++ b/src/V3Depth.cpp @@ -53,14 +53,8 @@ private: // if (debug() >= 9) nodep->dumpTree(cout, "deep:"); string newvarname = (string("__Vdeeptemp") + cvtToStr(m_modp->varNumGetInc())); - AstVar* varp = new AstVar(nodep->fileline(), AstVarType::STMTTEMP, newvarname, - // Width, not widthMin, as we may be in - // middle of BITSEL expression which though - // it's one bit wide, needs the mask in the - // upper bits. (Someday we'll have a valid - // bitmask instead of widths....) - // See t_func_crc for an example test that requires this - VFlagLogicPacked(), nodep->width()); + AstVar* varp + = new AstVar(nodep->fileline(), AstVarType::STMTTEMP, newvarname, nodep->dtypep()); UASSERT_OBJ(m_cfuncp, nodep, "Deep expression not under a function"); m_cfuncp->addInitsp(varp); // Replace node tree with reference to var diff --git a/test_regress/t/t_flag_comp_limit_parens.pl b/test_regress/t/t_flag_comp_limit_parens.pl new file mode 100755 index 000000000..e1ffcfc7b --- /dev/null +++ b/test_regress/t/t_flag_comp_limit_parens.pl @@ -0,0 +1,24 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +compile( + verilator_flags2 => ["--comp-limit-parens 2"], + ); + +execute( + check_finished => 1, + ); + +file_grep("$Self->{obj_dir}/Vt_flag_comp_limit_parens__Slow.cpp", qr/Vdeeptemp/x); + +ok(1); +1; diff --git a/test_regress/t/t_flag_comp_limit_parens.v b/test_regress/t/t_flag_comp_limit_parens.v new file mode 100644 index 000000000..bda8c841f --- /dev/null +++ b/test_regress/t/t_flag_comp_limit_parens.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + r + ); + input real r; + + initial begin + $display("%g", $cos($cos($cos($cos($cos($cos($cos($cos(r + 0.1))))))))); + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule From 6d3ec160e138ce36aa35be28ee0e3946ff4dbb56 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 28 Mar 2021 20:30:22 -0400 Subject: [PATCH 060/110] Internal coverage improvements --- test_regress/t/t_lint_rsvd_bad.out | 34 ++++++++++++++++++++++++++++-- test_regress/t/t_lint_rsvd_bad.v | 8 +++++++ test_regress/t/t_sys_sformat.v | 9 ++++++++ 3 files changed, 49 insertions(+), 2 deletions(-) diff --git a/test_regress/t/t_lint_rsvd_bad.out b/test_regress/t/t_lint_rsvd_bad.out index e1200e595..c2fd258da 100644 --- a/test_regress/t/t_lint_rsvd_bad.out +++ b/test_regress/t/t_lint_rsvd_bad.out @@ -4,7 +4,37 @@ %Error: t/t_lint_rsvd_bad.v:7:8: syntax error, unexpected IDENTIFIER 7 | config cfgBad; | ^~~~~~ -%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:8:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig' - 8 | endconfig +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:8:4: Unsupported: Verilog 2001-config reserved word not implemented: 'design' + 8 | design rtlLib.top; + | ^~~~~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:9:12: Unsupported: Verilog 2001-config reserved word not implemented: 'liblist' + 9 | default liblist rtlLib; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:10:4: Unsupported: Verilog 2001-config reserved word not implemented: 'instance' + 10 | instance top.a2 liblist gateLib; + | ^~~~~~~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:10:20: Unsupported: Verilog 2001-config reserved word not implemented: 'liblist' + 10 | instance top.a2 liblist gateLib; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:11:4: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: 'include' + 11 | include none; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:12:4: Unsupported: Verilog 2001-config reserved word not implemented: 'library' + 12 | library rtlLib *.v; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:13:4: Unsupported: Verilog 2001-config reserved word not implemented; suggest you want `include instead: 'include' + 13 | include aa; + | ^~~~~~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:14:4: Unsupported: Verilog 2001-config reserved word not implemented: 'use' + 14 | use gateLib; + | ^~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:15:4: Unsupported: Verilog 2001-config reserved word not implemented: 'cell' + 15 | cell rtlLib.cell; + | ^~~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:15:16: Unsupported: Verilog 2001-config reserved word not implemented: 'cell' + 15 | cell rtlLib.cell; + | ^~~~ +%Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:16:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig' + 16 | endconfig | ^~~~~~~~~ %Error: Exiting due to diff --git a/test_regress/t/t_lint_rsvd_bad.v b/test_regress/t/t_lint_rsvd_bad.v index 7fc2f16c5..aaef81658 100644 --- a/test_regress/t/t_lint_rsvd_bad.v +++ b/test_regress/t/t_lint_rsvd_bad.v @@ -5,6 +5,14 @@ // SPDX-License-Identifier: CC0-1.0 config cfgBad; + design rtlLib.top; + default liblist rtlLib; + instance top.a2 liblist gateLib; + include none; + library rtlLib *.v; + include aa; + use gateLib; + cell rtlLib.cell; endconfig module t; diff --git a/test_regress/t/t_sys_sformat.v b/test_regress/t/t_sys_sformat.v index bce43cb5e..2e3443e5b 100644 --- a/test_regress/t/t_sys_sformat.v +++ b/test_regress/t/t_sys_sformat.v @@ -74,6 +74,15 @@ module t; $sformat(ochar,"%s","c"); if (ochar != "c") $stop; + $swrite(str2, 4'd12); + if (str2 != "12") $stop; + $swriteb(str2, 4'd12); + if (str2 != "1100") $stop; + $swriteh(str2, 4'd12); + if (str2 != "c") $stop; + $swriteo(str2, 4'd12); + if (str2 != "14") $stop; + $write("*-* All Finished *-*\n"); $finish; end From c62546c7618b51001cfd061109d31e70b6292787 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 29 Mar 2021 18:54:51 -0400 Subject: [PATCH 061/110] Add --coverage-max-width (#2853). --- Changes | 1 + bin/verilator | 7 +++++++ src/V3Coverage.cpp | 5 +++-- src/V3Options.cpp | 1 + src/V3Options.h | 2 ++ test_regress/t/t_cover_toggle.pl | 2 ++ test_regress/t/t_cover_toggle.v | 2 +- test_regress/t/t_cover_toggle_width.pl | 26 ++++++++++++++++++++++++++ 8 files changed, 43 insertions(+), 3 deletions(-) create mode 100755 test_regress/t/t_cover_toggle_width.pl diff --git a/Changes b/Changes index 84ca20cbd..f4d7990b4 100644 --- a/Changes +++ b/Changes @@ -17,6 +17,7 @@ Verilator 4.201 devel * Changed TIMESCALEMOD from error into a warning. * Verilated signals now use VlWide and VlPacked in place of C arrays. * Mark --no-relative-cfuncs as scheduled for deprecation. +* Add --coverage-max-width (#2853). [xuejiazidi] * Add VerilatedCovContext::forcePerInstance (#2793). [Kevin Laeufer] * Fix class unpacked-array compile error (#2774). [Iru Cai] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] diff --git a/bin/verilator b/bin/verilator index ee0dbeab6..31879c192 100755 --- a/bin/verilator +++ b/bin/verilator @@ -313,6 +313,7 @@ arguments. --converge-limit Tune convergence settle time --coverage Enable all coverage --coverage-line Enable line coverage + --coverage-max-width Maximum array depth for coverage --coverage-toggle Enable toggle coverage --coverage-user Enable SVL user coverage --coverage-underscore Enable coverage of _signals @@ -697,6 +698,12 @@ Note Verilator may over-count combinatorial (non-clocked) blocks when those blocks receive signals which have had the UNOPTFLAT warning disabled; for most accurate results do not disable this warning when using coverage. +=item --trace-max-width I + +Rarely needed. Specify the maximum bit width of a signal that is subject +to toggle coverage. Defaults to 256, as covering large vectors may greatly +slow coverage simulations. + =item --coverage-toggle Specifies signal toggle coverage analysis code should be inserted. diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp index d7aee3ee0..b2fa737d3 100644 --- a/src/V3Coverage.cpp +++ b/src/V3Coverage.cpp @@ -96,8 +96,9 @@ private: if (prettyName[0] == '_') return "Leading underscore"; if (prettyName.find("._") != string::npos) return "Inlined leading underscore"; } - if ((nodep->width() * nodep->dtypep()->arrayUnpackedElements()) > 256) { - return "Wide bus/array > 256 bits"; + if ((nodep->width() * nodep->dtypep()->arrayUnpackedElements()) + > static_cast(v3Global.opt.coverageMaxWidth())) { + return "Wide bus/array > --coverage-max-width setting's bits"; } // We allow this, though tracing doesn't // if (nodep->arrayp(1)) return "Unsupported: Multi-dimensional array"; diff --git a/src/V3Options.cpp b/src/V3Options.cpp index cbbc25cc9..244d890d0 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -1237,6 +1237,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char DECL_OPTION("-coverage", CbOnOff, [this](bool flag) { coverage(flag); }); DECL_OPTION("-converge-limit", Set, &m_convergeLimit); DECL_OPTION("-coverage-line", OnOff, &m_coverageLine); + DECL_OPTION("-coverage-max-width", Set, &m_coverageMaxWidth); DECL_OPTION("-coverage-toggle", OnOff, &m_coverageToggle); DECL_OPTION("-coverage-underscore", OnOff, &m_coverageUnderscore); DECL_OPTION("-coverage-user", OnOff, &m_coverageUser); diff --git a/src/V3Options.h b/src/V3Options.h index ad522f373..7cb64f2ea 100644 --- a/src/V3Options.h +++ b/src/V3Options.h @@ -283,6 +283,7 @@ private: int m_buildJobs = 1; // main switch: -j int m_convergeLimit = 100; // main switch: --converge-limit + int m_coverageMaxWidth = 256; // main switch: --coverage-max-width int m_dumpTree = 0; // main switch: --dump-tree int m_gateStmts = 100; // main switch: --gate-stmts int m_ifDepth = 0; // main switch: --if-depth @@ -477,6 +478,7 @@ public: int buildJobs() const { return m_buildJobs; } int convergeLimit() const { return m_convergeLimit; } + int coverageMaxWidth() const { return m_coverageMaxWidth; } int dumpTree() const { return m_dumpTree; } bool dumpTreeAddrids() const { return m_dumpTreeAddrids; } int gateStmts() const { return m_gateStmts; } diff --git a/test_regress/t/t_cover_toggle.pl b/test_regress/t/t_cover_toggle.pl index e0feb7514..64324cf9d 100755 --- a/test_regress/t/t_cover_toggle.pl +++ b/test_regress/t/t_cover_toggle.pl @@ -21,6 +21,8 @@ execute( # Read the input .v file and do any CHECK_COVER requests inline_checks(); +file_grep_not("$Self->{obj_dir}/coverage.dat", "largeish"); + file_grep($Self->{stats}, qr/Coverage, Toggle points joined\s+(\d+)/i, 25) if $Self->{vlt_all}; diff --git a/test_regress/t/t_cover_toggle.v b/test_regress/t/t_cover_toggle.v index eb8e24ae2..a2920779f 100644 --- a/test_regress/t/t_cover_toggle.v +++ b/test_regress/t/t_cover_toggle.v @@ -62,7 +62,7 @@ module t (/*AUTOARG*/ reg [1:0] memory[121:110]; - reg [1023:0] largeish; + wire [1023:0] largeish = {992'h0, cyc}; // CHECK_COVER_MISSING(-1) always @ (posedge clk) begin diff --git a/test_regress/t/t_cover_toggle_width.pl b/test_regress/t/t_cover_toggle_width.pl new file mode 100755 index 000000000..f3823a558 --- /dev/null +++ b/test_regress/t/t_cover_toggle_width.pl @@ -0,0 +1,26 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +top_filename("t/t_cover_toggle.v"); + +compile( + verilator_flags2 => ['--cc --coverage-toggle --coverage-max-width 1025'], + ); + +execute( + check_finished => 1, + ); + +file_grep("$Self->{obj_dir}/coverage.dat", "largeish"); + +ok(1); +1; From 8c12dcf751e20b81cf97bf69f7b3788fe5d06fb7 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 29 Mar 2021 19:37:47 -0400 Subject: [PATCH 062/110] Commentary --- .clang-format | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.clang-format b/.clang-format index edb50069b..ad282b495 100644 --- a/.clang-format +++ b/.clang-format @@ -20,7 +20,7 @@ AlwaysBreakBeforeMultilineStrings: false AlwaysBreakTemplateDeclarations: false BinPackArguments: true BinPackParameters: true -BraceWrapping: +BraceWrapping: AfterClass: false AfterControlStatement: false AfterEnum: false @@ -55,12 +55,12 @@ DerivePointerAlignment: false DisableFormat: false ExperimentalAutoDetectBinPacking: false FixNamespaceComments: true -ForEachMacros: +ForEachMacros: - foreach - Q_FOREACH - BOOST_FOREACH IncludeBlocks: Preserve -IncludeCategories: +IncludeCategories: - Regex: '^"(llvm|llvm-c|clang|clang-c)/' Priority: 2 - Regex: '^(<|"(gtest|gmock|isl|json)/)' From e9c7f40bb46063d3926bc67bfc4aa2d5d31b0372 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 29 Mar 2021 21:28:08 -0400 Subject: [PATCH 063/110] Internals: Prefer using over typedef. No functional change. --- include/verilated.h | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/include/verilated.h b/include/verilated.h index d318fea92..07a609e57 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -93,20 +93,20 @@ class VerilatedVcdSc; // Basic types // clang-format off -// P // Packed data of bit type (C/S/I/Q/W) -typedef vluint8_t CData; ///< Data representing 'bit' of 1-8 packed bits -typedef vluint16_t SData; ///< Data representing 'bit' of 9-16 packed bits -typedef vluint32_t IData; ///< Data representing 'bit' of 17-32 packed bits -typedef vluint64_t QData; ///< Data representing 'bit' of 33-64 packed bits -typedef vluint32_t EData; ///< Data representing one element of WData array -typedef EData WData; ///< Data representing >64 packed bits (used as pointer) -// float F // No typedef needed; Verilator uses float -// double D // No typedef needed; Verilator uses double -// string N // No typedef needed; Verilator uses string +// P // Packed data of bit type (C/S/I/Q/W) +using CData = vluint8_t; ///< Data representing 'bit' of 1-8 packed bits +using SData = vluint16_t; ///< Data representing 'bit' of 9-16 packed bits +using IData = vluint32_t; ///< Data representing 'bit' of 17-32 packed bits +using QData = vluint64_t; ///< Data representing 'bit' of 33-64 packed bits +using EData = vluint32_t; ///< Data representing one element of WData array +using WData = EData; ///< Data representing >64 packed bits (used as pointer) +// F = float; // No typedef needed; Verilator uses float +// D = double; // No typedef needed; Verilator uses double +// N = std::string; // No typedef needed; Verilator uses string // clang-format on -typedef const WData* WDataInP; ///< 'bit' of >64 packed bits as array input to a function -typedef WData* WDataOutP; ///< 'bit' of >64 packed bits as array output from a function +using WDataInP = const WData*; ///< 'bit' of >64 packed bits as array input to a function +using WDataOutP = WData*; ///< 'bit' of >64 packed bits as array output from a function enum VerilatedVarType : vluint8_t { VLVT_UNKNOWN = 0, From c8d8e95d52f5bcd45556d4783e3dc53bee2ac972 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 1 Apr 2021 08:52:48 -0400 Subject: [PATCH 064/110] Tests: Honor make_top_shell=>0 (#2847). --- test_regress/driver.pl | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 846e74930..cb68f1885 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -969,9 +969,9 @@ sub compile { compile_vlt_cmd(%param); - if (!$self->{make_top_shell}) { + if (!$param{make_top_shell}) { $param{top_shell_filename} - = $self->{top_shell_filename} = $self->{top_filename}; + = $self->{top_shell_filename} = ""; } else { $param{top_shell_filename} = $self->{top_shell_filename} = "$self->{obj_dir}/$self->{VM_PREFIX}__top.".$self->v_suffix; @@ -979,7 +979,7 @@ sub compile { if ($param{atsim}) { $param{tool_define} ||= $param{atsim_define}; - $self->_make_top(); + $self->_make_top() if $param{make_top_shell}; $self->_run(logfile=>"$self->{obj_dir}/atsim_compile.log", fails=>$param{fails}, cmd=>[($ENV{VERILATOR_ATSIM}||"atsim"), @@ -995,7 +995,7 @@ sub compile { elsif ($param{ghdl}) { $param{tool_define} ||= $param{ghdl_define}; mkdir $self->{ghdl_work_dir}; - $self->_make_top(); + $self->_make_top() if $param{make_top_shell}; $self->_run(logfile=>"$self->{obj_dir}/ghdl_compile.log", fails=>$param{fails}, cmd=>[($ENV{VERILATOR_GHDL}||"ghdl"), @@ -1013,7 +1013,7 @@ sub compile { } elsif ($param{vcs}) { $param{tool_define} ||= $param{vcs_define}; - $self->_make_top(); + $self->_make_top() if $param{make_top_shell}; $self->_run(logfile=>"$self->{obj_dir}/vcs_compile.log", fails=>$param{fails}, cmd=>[($ENV{VERILATOR_VCS}||"vcs"), @@ -1029,7 +1029,7 @@ sub compile { } elsif ($param{nc}) { $param{tool_define} ||= $param{nc_define}; - $self->_make_top(); + $self->_make_top() if $param{make_top_shell}; my @more_args; if ($self->vhdl) { ((my $ts = $param{top_shell_filename}) =~ s!\.v!!); @@ -1051,7 +1051,7 @@ sub compile { } elsif ($param{ms}) { $param{tool_define} ||= $param{ms_define}; - $self->_make_top(); + $self->_make_top() if $param{make_top_shell}; $self->_run(logfile=>"$self->{obj_dir}/ms_compile.log", fails=>$param{fails}, cmd=>[("vlib $self->{obj_dir}/work && "), @@ -1067,7 +1067,7 @@ sub compile { } elsif ($param{iv}) { $param{tool_define} ||= $param{iv_define}; - $self->_make_top(); + $self->_make_top() if $param{make_top_shell}; my @cmd = (($ENV{VERILATOR_IVERILOG}||"iverilog"), @{$param{iv_flags}}, @{$param{iv_flags2}}, @@ -1084,7 +1084,7 @@ sub compile { } elsif ($param{xsim}) { $param{tool_define} ||= $param{xsim_define}; - $self->_make_top(); + $self->_make_top() if $param{make_top_shell}; $self->_run(logfile=>"$self->{obj_dir}/xsim_compile.log", fails=>$param{fails}, cmd=>[($ENV{VERILATOR_XVLOG}||"xvlog"), From a9f4129b6b7548061ae1fe4f48368d7926b672ae Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 1 Apr 2021 09:03:38 -0400 Subject: [PATCH 065/110] Tests: Add test for (#1613) --- test_regress/t/t_select_2d.pl | 21 ++++++++++ test_regress/t/t_select_2d.v | 78 +++++++++++++++++++++++++++++++++++ 2 files changed, 99 insertions(+) create mode 100755 test_regress/t/t_select_2d.pl create mode 100644 test_regress/t/t_select_2d.v diff --git a/test_regress/t/t_select_2d.pl b/test_regress/t/t_select_2d.pl new file mode 100755 index 000000000..2cb5eeaff --- /dev/null +++ b/test_regress/t/t_select_2d.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_select_2d.v b/test_regress/t/t_select_2d.v new file mode 100644 index 000000000..bbe492e52 --- /dev/null +++ b/test_regress/t/t_select_2d.v @@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [4:0] cnt_i = (crc[4:0] <= 5'd17) ? crc[4:0] : 5'd0; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic [63:0] out_o; // From test of Test.v + // End of automatics + + Test test(/*AUTOINST*/ + // Outputs + .out_o (out_o[63:0]), + // Inputs + .cnt_i (cnt_i[4:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = out_o; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 90) begin + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h1f324087bbba0bfa + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test + (input logic [4:0] cnt_i, + output logic [63:0] out_o); + + logic [17:0][63:0] data; + initial begin + for (int a = 0; a < 18; ++a) + data[a] = {8{a[7:0]}}; + end + + // verilator lint_off WIDTH + assign out_o = data[5'd17 - cnt_i]; + +endmodule From 0ea5af40c5c741d70c08ee8e65daba430111320d Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Fri, 2 Apr 2021 01:17:42 +0300 Subject: [PATCH 066/110] Add PINNOTFOUND warning in place of "Pin not found" error (#2868) --- bin/verilator | 28 +++++++++++++++++++++++ docs/CONTRIBUTORS | 1 + src/V3Error.h | 10 ++++---- src/V3LinkDot.cpp | 7 +++--- test_regress/t/t_class_param_bad.out | 6 ++--- test_regress/t/t_lint_pindup_bad.out | 8 +++---- test_regress/t/t_lint_pinnotfound.pl | 13 +++++++++++ test_regress/t/t_lint_pinnotfound.v | 20 ++++++++++++++++ test_regress/t/t_lint_pinnotfound_bad.out | 7 ++++++ test_regress/t/t_lint_pinnotfound_bad.pl | 19 +++++++++++++++ test_regress/t/t_lint_pinnotfound_bad.v | 19 +++++++++++++++ 11 files changed, 124 insertions(+), 14 deletions(-) create mode 100755 test_regress/t/t_lint_pinnotfound.pl create mode 100644 test_regress/t/t_lint_pinnotfound.v create mode 100644 test_regress/t/t_lint_pinnotfound_bad.out create mode 100755 test_regress/t/t_lint_pinnotfound_bad.pl create mode 100644 test_regress/t/t_lint_pinnotfound_bad.v diff --git a/bin/verilator b/bin/verilator index 31879c192..b886d5b40 100755 --- a/bin/verilator +++ b/bin/verilator @@ -4740,6 +4740,34 @@ Warns that an instance has a pin which is not connected to another signal. Disabled by default as this is a code style warning; it will simulate correctly. +=item PINNOTFOUND + +Warns that an instance port or Parameter was not found in the module being +instanciated. Please note that Verilator raises these errors also on instances +that should be disabled by generate/if/endgenerate constructs: + + module a; + localparam A=1; + generate + if (A==0) begin + b b_inst1 (.x(1'b0)); // nonexistent port + b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter + end + endgenerate + endmodule + + module b; + endmodule + +In the example above, b is instantiated with a port named x, but module b has +no such port. In the next line, b is instantiated again with +a nonexistent parameter PX. Technically, this code is incorrect because of +this, but other tools may ignore it because module b is not instantiated +due to the generate/if condition being false. + +It is possible to disable the error above using: +/* verilator lint_off PINNOTFOUND */ + =item PKGNODECL Error that a package/class appears to have been referenced that has not yet diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index cc4c8292c..a85ea0582 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -82,6 +82,7 @@ Tobias Wölfel Todd Strader Tomasz Gorochowik Tymoteusz Blazejczyk +Udi Finkelstein Unai Martinez-Corral Vassilis Papaefstathiou Veripool API Bot diff --git a/src/V3Error.h b/src/V3Error.h index eb3ec178d..100573296 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -101,9 +101,10 @@ public: MULTIDRIVEN, // Driven from multiple blocks MULTITOP, // Multiple top level modules NOLATCH, // No latch detected in always_latch block + PINCONNECTEMPTY,// Cell pin connected by name with empty reference PINMISSING, // Cell pin not specified PINNOCONNECT, // Cell pin not connected - PINCONNECTEMPTY,// Cell pin connected by name with empty reference + PINNOTFOUND, // instance port name not found in it's module PKGNODECL, // Error: Package/class needs to be predeclared PROCASSWIRE, // Procedural assignment on wire RANDC, // Unsupported: 'randc' converted to 'rand' @@ -166,8 +167,8 @@ public: "IMPERFECTSCH", "IMPLICIT", "IMPORTSTAR", "IMPURE", "INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE", "LATCH", "LITENDIAN", "MODDUP", - "MULTIDRIVEN", "MULTITOP","NOLATCH", - "PINMISSING", "PINNOCONNECT", "PINCONNECTEMPTY", "PKGNODECL", "PROCASSWIRE", + "MULTIDRIVEN", "MULTITOP","NOLATCH", "PINCONNECTEMPTY", + "PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", "PROCASSWIRE", "RANDC", "REALCVT", "REDEFMACRO", "SELRANGE", "SHORTREAL", "SPLITVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET", "TICKCOUNT", "TIMESCALEMOD", @@ -190,7 +191,8 @@ public: // Later -Werror- options may make more of these. bool pretendError() const { return (m_e == ASSIGNIN || m_e == BLKANDNBLK || m_e == BLKLOOPINIT || m_e == CONTASSREG - || m_e == IMPURE || m_e == PKGNODECL || m_e == PROCASSWIRE); // Says IEEE + || m_e == IMPURE || m_e == PINNOTFOUND || m_e == PKGNODECL + || m_e == PROCASSWIRE); // Says IEEE } // Warnings to mention manual bool mentionManual() const { diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp index 6bc5d26ea..d5d5d0748 100644 --- a/src/V3LinkDot.cpp +++ b/src/V3LinkDot.cpp @@ -2023,9 +2023,10 @@ private: LinkNodeMatcherVarParam()) : m_statep->suggestSymFlat(m_pinSymp, nodep->name(), LinkNodeMatcherVarIO())); - nodep->v3error(ucfirst(whatp) - << " not found: " << nodep->prettyNameQ() << '\n' - << (suggest.empty() ? "" : nodep->warnMore() + suggest)); + nodep->v3warn(PINNOTFOUND, + ucfirst(whatp) + << " not found: " << nodep->prettyNameQ() << '\n' + << (suggest.empty() ? "" : nodep->warnMore() + suggest)); } else if (AstVar* refp = VN_CAST(foundp->nodep(), Var)) { if (!refp->isIO() && !refp->isParam() && !refp->isIfaceRef()) { nodep->v3error(ucfirst(whatp) << " is not an in/out/inout/param/interface: " diff --git a/test_regress/t/t_class_param_bad.out b/test_regress/t/t_class_param_bad.out index 20b89cfa7..83375ea19 100644 --- a/test_regress/t/t_class_param_bad.out +++ b/test_regress/t/t_class_param_bad.out @@ -1,8 +1,8 @@ -%Error: t/t_class_param_bad.v:12:11: Parameter pin not found: 'PARAMBAD' - : ... Suggested alternative: 'PARAMB' +%Error-PINNOTFOUND: t/t_class_param_bad.v:12:11: Parameter pin not found: 'PARAMBAD' + : ... Suggested alternative: 'PARAMB' 12 | Cls #(.PARAMBAD(1)) c; | ^~~~~~~~ -%Error: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2' +%Error-PINNOTFOUND: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2' 13 | Cls #(13, 1) cd; | ^ %Error: Exiting due to diff --git a/test_regress/t/t_lint_pindup_bad.out b/test_regress/t/t_lint_pindup_bad.out index 0e4832769..a34830565 100644 --- a/test_regress/t/t_lint_pindup_bad.out +++ b/test_regress/t/t_lint_pindup_bad.out @@ -8,12 +8,12 @@ t/t_lint_pindup_bad.v:20:10: ... Location of original pin connection 20 | .i(i), | ^ -%Error: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist' - : ... Suggested alternative: 'exists' +%Error-PINNOTFOUND: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist' + : ... Suggested alternative: 'exists' 22 | .nexist(i2) | ^~~~~~ -%Error: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST' - : ... Suggested alternative: 'EXIST' +%Error-PINNOTFOUND: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST' + : ... Suggested alternative: 'EXIST' 16 | .NEXIST(1), | ^~~~~~ %Error: t/t_lint_pindup_bad.v:17:9: Duplicate parameter pin connection: 'P' diff --git a/test_regress/t/t_lint_pinnotfound.pl b/test_regress/t/t_lint_pinnotfound.pl new file mode 100755 index 000000000..7314796b8 --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound.pl @@ -0,0 +1,13 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +lint( + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_pinnotfound.v b/test_regress/t/t_lint_pinnotfound.v new file mode 100644 index 000000000..63f611b10 --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound.v @@ -0,0 +1,20 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +/* verilator lint_off PINNOTFOUND */ +module a; +localparam A=1; +generate +if (A==0) +begin +b b_inst1 (.x(1'b0)); // nonexistent port +b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter +end +endgenerate +endmodule + +module b; +endmodule diff --git a/test_regress/t/t_lint_pinnotfound_bad.out b/test_regress/t/t_lint_pinnotfound_bad.out new file mode 100644 index 000000000..e10eaa161 --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound_bad.out @@ -0,0 +1,7 @@ +%Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:12:13: Pin not found: 'x' + 12 | b b_inst1 (.x(1'b0)); + | ^ +%Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:13:6: Parameter pin not found: 'PX' + 13 | b #(.PX(1'b0)) b_inst2 (); + | ^~ +%Error: Exiting due to diff --git a/test_regress/t/t_lint_pinnotfound_bad.pl b/test_regress/t/t_lint_pinnotfound_bad.pl new file mode 100755 index 000000000..a60503a1f --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound_bad.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_pinnotfound_bad.v b/test_regress/t/t_lint_pinnotfound_bad.v new file mode 100644 index 000000000..c7128a41a --- /dev/null +++ b/test_regress/t/t_lint_pinnotfound_bad.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module a; +localparam A=1; +generate +if (A==0) +begin +b b_inst1 (.x(1'b0)); // nonexistent port +b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter +end +endgenerate +endmodule + +module b; +endmodule From 273fcce09514b266d9a38758677e6afbc65ece07 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 1 Apr 2021 19:51:22 -0400 Subject: [PATCH 067/110] Fix test error in last commit --- src/V3Error.h | 2 +- test_regress/t/t_udp_bad.out | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/V3Error.h b/src/V3Error.h index 100573296..1eec450e0 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -167,7 +167,7 @@ public: "IMPERFECTSCH", "IMPLICIT", "IMPORTSTAR", "IMPURE", "INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE", "LATCH", "LITENDIAN", "MODDUP", - "MULTIDRIVEN", "MULTITOP","NOLATCH", "PINCONNECTEMPTY", + "MULTIDRIVEN", "MULTITOP","NOLATCH", "PINCONNECTEMPTY", "PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", "PROCASSWIRE", "RANDC", "REALCVT", "REDEFMACRO", "SELRANGE", "SHORTREAL", "SPLITVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET", diff --git a/test_regress/t/t_udp_bad.out b/test_regress/t/t_udp_bad.out index f689ded39..451595dd6 100644 --- a/test_regress/t/t_udp_bad.out +++ b/test_regress/t/t_udp_bad.out @@ -5,7 +5,7 @@ %Error: t/t_udp_bad.v:14:18: Pin is not an in/out/inout/interface: 'a_bad' 14 | primitive udp_x (a_bad, b, c_bad); | ^~~~~ -%Error: t/t_udp_bad.v:10:13: Pin not found: '__pinNumber1' +%Error-PINNOTFOUND: t/t_udp_bad.v:10:13: Pin not found: '__pinNumber1' 10 | udp_x x (a, b); | ^ %Error: t/t_udp_bad.v:15:9: Only inputs and outputs are allowed in udp modules From 4f36e3e6c9c651af801f1ba7147a3cd89fef93b7 Mon Sep 17 00:00:00 2001 From: Geza Lore Date: Sat, 3 Apr 2021 17:57:06 +0100 Subject: [PATCH 068/110] Fix incorrect condition in varNotReferenced (#2873) The intention was to not merge impure assignments, but the actual predicate failed if the assignment was indeed pure. This fix gains 1.5% speed on SweRV EH1. --- src/V3Const.cpp | 2 +- test_regress/t/t_split_var_0.pl | 2 +- test_regress/t/t_split_var_2_trace.pl | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/V3Const.cpp b/src/V3Const.cpp index ee97ffd50..e1b990513 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -1531,7 +1531,7 @@ private: // Return false if referenced, or tree too deep to be worth it, or side effects if (!nodep) return true; if (level > 2) return false; - if (nodep->isPure()) return false; // For example a $fgetc can't be reordered + if (!nodep->isPure()) return false; // For example a $fgetc can't be reordered if (VN_IS(nodep, NodeVarRef) && VN_CAST(nodep, NodeVarRef)->varp() == varp) return false; return (varNotReferenced(nodep->nextp(), varp, level + 1) && varNotReferenced(nodep->op1p(), varp, level + 1) diff --git a/test_regress/t/t_split_var_0.pl b/test_regress/t/t_split_var_0.pl index 5f07afe64..f04359527 100755 --- a/test_regress/t/t_split_var_0.pl +++ b/test_regress/t/t_split_var_0.pl @@ -22,7 +22,7 @@ execute( check_finished => 1, ); -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 13); +file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 11); file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 27); ok(1); 1; diff --git a/test_regress/t/t_split_var_2_trace.pl b/test_regress/t/t_split_var_2_trace.pl index c79ed778a..76513de86 100755 --- a/test_regress/t/t_split_var_2_trace.pl +++ b/test_regress/t/t_split_var_2_trace.pl @@ -24,7 +24,7 @@ execute( ); vcd_identical("$Self->{obj_dir}/simx.vcd", $Self->{golden_filename}); -file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 12); +file_grep($Self->{stats}, qr/SplitVar,\s+Split packed variables\s+(\d+)/i, 10); file_grep($Self->{stats}, qr/SplitVar,\s+Split unpacked arrays\s+(\d+)/i, 27); ok(1); From 5658d7238db2757317abdc5425bebe60e066a710 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 3 Apr 2021 13:11:26 -0400 Subject: [PATCH 069/110] Commentary --- Changes | 18 +++++++++--------- bin/verilator | 46 ++++++++++++++++++++++++++++------------------ 2 files changed, 37 insertions(+), 27 deletions(-) diff --git a/Changes b/Changes index f4d7990b4..8952ba3e8 100644 --- a/Changes +++ b/Changes @@ -557,7 +557,7 @@ Verilator 4.014 2019-05-08 * For FST tracing use LZ4 compression. [Tony Bybell] * Add error when use parameters without value. (#1424) [Peter Gerst] * Auto-extend and WIDTH warn on unsized X/Zs. (#1423) [Udi Finkelstein] -* Fix missing VL_SHIFTL_ errors. (#1412) (#1415) [Larry Lee] +* Fix missing VL_SHIFTL errors. (#1412) (#1415) [Larry Lee] * Fix MinGW GCC 6 printf formats. (#1413) [Sergey Kvachonok] * Fix test problems when missing fst2vcd. (#1417) [Todd Strader] * Fix GTKWave register warning. (#1421) [Pieter Kapsenberg] @@ -626,7 +626,7 @@ Verilator 4.006 2018-10-27 * Add --dump-defines. * For --trace-fst, save enum decoding information. (#1358) [Sergi Granell] (To visualize enumeration data you must use GTKwave 3.3.95 or newer.) -* For --trace-fst, instead of *.fst.hier, put data into *.fst. [Tony Bybell] +* For --trace-fst, combine hier information into FST. [Tony Bybell] * Fix --trace-lxt2 compile error on MinGW, msg2667. [HyungKi Jeong] * Fix Windows .exe not found. (#1361) [Patrick Stewart] @@ -1960,7 +1960,7 @@ Verilator 3.700 2009-01-08 more information on supported constructs. * Add --coverage_toggle for toggle coverage analysis. Running coverage now requires SystemPerl 1.301 or newer. -* Add /*verilator coverage_on/_off */ to bracket coverage regions. +* Add coverage_on/_off metacomments to bracket coverage regions. **Minor:** @@ -2098,7 +2098,7 @@ Verilator 3.662 2008-04-25 * Add Verilog 2005 $clog2() function. This is useful in calculating bus-widths from parameters. -* Support /**/ comments in -f option files. [Stefan Thiede] +* Support C-style comments in -f option files. [Stefan Thiede] * Add error message when modules have duplicate names. [Stefan Thiede] * Support defines terminated in EOF, though against spec. [Stefan Thiede] * Support optional argument to $finish and $stop. [by Stefan Thiede] @@ -2224,7 +2224,7 @@ Verilator 3.652 2007-06-21 * Support V2K portlists with "input a,b,...". [Mark Nodine] * Support V2K function/task argument lists. * Optimize constant $display arguments. -* Fix Preprocessor dropping some `line directives. [Mark Nodine] +* Fix preprocessor dropping some `line directives. [Mark Nodine] Verilator 3.651 2007-05-22 @@ -2944,7 +2944,7 @@ Verilator 3.300 2004-10-21 **Major:** -* New backend that eliminates most VL_ macros. +* New backend that eliminates most VL macros. Improves performance 20%-50%, depending on frequency of use of signals over 64 bits. GCC compile times with -O2 shrink by a factor of 10. @@ -3106,7 +3106,7 @@ Verilator 3.202 2004-01-27 Verilator 3.201-beta 2003-12-10 -========================== +=============================== **Major:** @@ -3402,8 +3402,8 @@ Verilator 3.004 2002-10-10 **Minor:** -* Add /* verilator module_inline */ and associated optimizations. -* Allow /* verilator coverage_block_off */ in place of `coverage_block_off. +* Add module_inline metacomment and associated optimizations. +* Allow coverage_block_off metacomment in place of `coverage_block_off. This prevents problems with Emacs AUTORESET. [Ray Strouble] * Fix `coverage_block_off also disabling subsequent blocks. * Fix unrolling of loops with multiple simple statements. diff --git a/bin/verilator b/bin/verilator index b886d5b40..c503e4036 100755 --- a/bin/verilator +++ b/bin/verilator @@ -287,9 +287,11 @@ This is a short summary of the arguments to the "verilator" executable. See L for the detailed descriptions of these arguments. - {file.v} Verilog package, module and top module filenames - {file.c/cc/cpp} Optional C++ files to compile in - {file.a/o/so} Optional C++ files to link in +=for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst" + + Verilog package, module and top module filenames + Optional C++ files to compile in + Optional C++ files to link in +1364-1995ext+ Use Verilog 1995 with file extension +1364-2001ext+ Use Verilog 2001 with file extension @@ -304,7 +306,7 @@ arguments. --bbox-unsup Blackbox unsupported language features --bin Override Verilator binary --build Build model executable/library after Verilation - -CFLAGS C++ compiler flags for makefile + -CFLAGS C++ compiler arguments for makefile --cc Create C++ output --cdc Clock domain crossing analysis --clk Mark specified signal as clock @@ -334,8 +336,8 @@ arguments. -E Preprocess, but do not compile --error-limit Abort after this number of errors --exe Link to create executable - -F Parse options from a file, relatively - -f Parse options from a file + -F Parse arguments from a file, relatively + -f Parse arguments from a file -FI Force include of a file --flatten Force inlining of all modules, tasks and functions -G= Overwrite top-level parameter @@ -352,12 +354,12 @@ arguments. +incdir+ Directory to search for includes --inhibit-sim Create function to turn off sim --inline-mult Tune module inlining - -LDFLAGS Linker pre-object flags for makefile + -LDFLAGS Linker pre-object arguments for makefile --l2-name Verilog scope name of the top module --language Default language standard to parse +libext++[ext]... Extensions for finding modules --lint-only Lint, but do not make output - -MAKEFLAGS Options to make during --build + -MAKEFLAGS Arguments to pass to make during --build --max-num-width Maximum number width (default: 64K) --MMD Create .d dependency files --MP Create phony dependency targets @@ -453,15 +455,18 @@ This is a short summary of the simulation runtime arguments, i.e. for the final Verilated simulation runtime models. See L for the detailed description of these arguments. +=for VL_SPHINX_EXTRACT "_build/gen/args_verilated.rst" + +verilator+debug Enable debugging +verilator+debugi+ Enable debugging at a level + +verilator+error+limit+ Set error limit +verilator+help Display help + +verilator+noassert Disable assert checking +verilator+prof+threads+file+ Set profile filename +verilator+prof+threads+start+ Set profile starting point +verilator+prof+threads+window+ Set profile duration +verilator+rand+reset+ Set random reset technique +verilator+seed+ Set random seed - +verilator+noassert Disable assert checking +verilator+V Verbose version and config +verilator+version Show version and exit @@ -473,11 +478,11 @@ executable. =over 4 -=item {file.v} +=item Specifies the Verilog file containing the top module to be Verilated. -=item {file.c/.cc/.cpp/.cxx} +=item Used with --exe to specify optional C++ files to be linked in with the Verilog code. The file path should either be absolute, or relative to @@ -487,7 +492,7 @@ appropriate directory to find the file. See also the -CFLAGS and -LDFLAGS options, which are useful when the C++ files need special compiler flags. -=item {file.a/.o/.so} +=item Specifies optional object or library files to be linked in with the Verilog code, as a shorthand for -LDFLAGS "". The file path should either be @@ -698,7 +703,7 @@ Note Verilator may over-count combinatorial (non-clocked) blocks when those blocks receive signals which have had the UNOPTFLAT warning disabled; for most accurate results do not disable this warning when using coverage. -=item --trace-max-width I +=item --coverage-max-width I Rarely needed. Specify the maximum bit width of a signal that is subject to toggle coverage. Defaults to 256, as covering large vectors may greatly @@ -763,8 +768,11 @@ is fairly standard across Verilog tools while -D is similar to GCC. Select the debug executable of Verilator (if available), and enable more internal assertions (equivalent to C<--debug-check>), debugging messages -(equivalent to C<--debugi 3>), and intermediate form dump files (equivalent -to C<--dump-treei 3>). +(equivalent to C<--debugi 3>), intermediate form dump files (equivalent to +C<--dump-treei 3>), and leak to make node numbers unique (--debug-leak). + +Verilator will also abort() instead of exit() if there are any errors +detected. =item --debug-check @@ -790,7 +798,8 @@ option has no effect. Rarely needed - for developer use. Set internal debugging level globally to the specified debug level (1-10) or set the specified Verilator source file to the specified level (e.g. C<--debugi-V3Width 9>). Higher levels -produce more detailed messages. +produce more detailed messages. See --debug for other implications of +having debug on (at levels other than zero). =item --default-language I @@ -3070,8 +3079,9 @@ thread. =head1 CONFIGURATION FILES In addition to the command line, warnings and other features may be -controlled by configuration files, typically named with the .vlt -extension. An example: +controlled by configuration files, typically named with the .vlt extension +(what makes it a configuration file is the `verilator_config directive). An +example: `verilator_config lint_off -rule WIDTH From 961a2fef61e5f55917ecb8868c1e10bcaacaaf2a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 4 Apr 2021 22:05:44 -0400 Subject: [PATCH 070/110] Some minor preliminary docs reorg --- MANIFEST.SKIP | 2 +- Makefile.in | 6 +- configure.ac | 2 +- docs/.gitignore | 2 +- docs/CONTRIBUTING.rst | 2 +- docs/{Makefile.in => Makefile} | 0 docs/{ => _static}/verilator_logo.png | Bin docs/doxygen-mainpage | 6 - docs/doxygen.config | 1765 ------------------------- docs/internals.rst | 2 +- src/pod2latexfix | 2 +- 11 files changed, 8 insertions(+), 1781 deletions(-) rename docs/{Makefile.in => Makefile} (100%) rename docs/{ => _static}/verilator_logo.png (100%) delete mode 100644 docs/doxygen-mainpage delete mode 100644 docs/doxygen.config diff --git a/MANIFEST.SKIP b/MANIFEST.SKIP index f765c3326..b46442e93 100644 --- a/MANIFEST.SKIP +++ b/MANIFEST.SKIP @@ -39,7 +39,7 @@ README.html bin/verilator_bin.* bin/verilator_coverage_bin.* docs/.*\.html$ -docs/Makefile$ +docs/_build/ docs/clang-format.txt$ docs/doxygen-doc/.* examples/xml_py/copied/ diff --git a/Makefile.in b/Makefile.in index c3dbbb6da..d44b92cba 100644 --- a/Makefile.in +++ b/Makefile.in @@ -136,13 +136,11 @@ DISTFILES_INC = $(INFOS) .gitignore \ docs/.gitignore \ docs/CONTRIBUTING.rst \ docs/CONTRIBUTORS \ - docs/Makefile.in \ + docs/Makefile \ docs/TODO \ - docs/doxygen-mainpage \ - docs/doxygen.config \ + docs/_static/verilator_logo.png \ docs/install.rst \ docs/internals.rst \ - docs/verilator_logo.png \ docs/xml.rst \ install-sh configure *.pod \ include/*.[chv]* \ diff --git a/configure.ac b/configure.ac index 702679ddb..810812ab0 100644 --- a/configure.ac +++ b/configure.ac @@ -15,7 +15,7 @@ AC_INIT([Verilator],[4.201 devel], # Then 'make maintainer-dist' AC_CONFIG_HEADER(src/config_build.h) -AC_CONFIG_FILES(Makefile docs/Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake) +AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk include/verilated_config.h verilator.pc verilator-config.cmake verilator-config-version.cmake) # Version AC_MSG_RESULT([configuring for $PACKAGE_STRING]) diff --git a/docs/.gitignore b/docs/.gitignore index e1ce07996..4e1217655 100644 --- a/docs/.gitignore +++ b/docs/.gitignore @@ -1,4 +1,4 @@ *.1 *.html *.pdf -Makefile +_build diff --git a/docs/CONTRIBUTING.rst b/docs/CONTRIBUTING.rst index a9ae58e42..47f1ede39 100644 --- a/docs/CONTRIBUTING.rst +++ b/docs/CONTRIBUTING.rst @@ -88,6 +88,6 @@ Code of Conduct - Our contributors and participants pledge to make participation in our project and our community a positive experience for everyone. We follow the `Contributor Covenant version 1.4 - `__. + `__. Thanks! diff --git a/docs/Makefile.in b/docs/Makefile similarity index 100% rename from docs/Makefile.in rename to docs/Makefile diff --git a/docs/verilator_logo.png b/docs/_static/verilator_logo.png similarity index 100% rename from docs/verilator_logo.png rename to docs/_static/verilator_logo.png diff --git a/docs/doxygen-mainpage b/docs/doxygen-mainpage deleted file mode 100644 index 2d0c282a3..000000000 --- a/docs/doxygen-mainpage +++ /dev/null @@ -1,6 +0,0 @@ -/*! \mainpage Verilator Doxygen Documentation - * - * \section intro_sec Introduction - * - * This is a full doxygen analysis of the Verilator source tree. - */ diff --git a/docs/doxygen.config b/docs/doxygen.config deleted file mode 100644 index 3947cabad..000000000 --- a/docs/doxygen.config +++ /dev/null @@ -1,1765 +0,0 @@ -# Doxyfile 1.7.5 - -# This file describes the settings to be used by the documentation system -# doxygen (www.doxygen.org) for a project. -# -# All text after a hash (#) is considered a comment and will be ignored. -# The format is: -# TAG = value [value, ...] -# For lists items can also be appended using: -# TAG += value [value, ...] -# Values that contain spaces should be placed between quotes (" "). - -#--------------------------------------------------------------------------- -# Project related configuration options -#--------------------------------------------------------------------------- - -# This tag specifies the encoding used for all characters in the config file -# that follow. The default is UTF-8 which is also the encoding used for all -# text before the first occurrence of this tag. Doxygen uses libiconv (or the -# iconv built into libc) for the transcoding. See -# http://www.gnu.org/software/libiconv for the list of possible encodings. - -DOXYFILE_ENCODING = UTF-8 - -# The PROJECT_NAME tag is a single word (or sequence of words) that should -# identify the project. Note that if you do not use Doxywizard you need -# to put quotes around the project name if it contains spaces. - -PROJECT_NAME = Verilator - -# The PROJECT_NUMBER tag can be used to enter a project or revision number. -# This could be handy for archiving the generated documentation or -# if some version control system is used. - -PROJECT_NUMBER = - -# Using the PROJECT_BRIEF tag one can provide an optional one line description -# for a project that appears at the top of each page and should give viewer -# a quick idea about the purpose of the project. Keep the description short. - -PROJECT_BRIEF = "Verilog to C translator" - -# With the PROJECT_LOGO tag one can specify an logo or icon that is -# included in the documentation. The maximum height of the logo should not -# exceed 55 pixels and the maximum width should not exceed 200 pixels. -# Doxygen will copy the logo to the output directory. - -PROJECT_LOGO = verilator_logo.png - -# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) -# base path where the generated documentation will be put. -# If a relative path is entered, it will be relative to the location -# where doxygen was started. If left blank the current directory will be used. - -OUTPUT_DIRECTORY = doxygen-doc - -# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create -# 4096 sub-directories (in 2 levels) under the output directory of each output -# format and will distribute the generated files over these directories. -# Enabling this option can be useful when feeding doxygen a huge amount of -# source files, where putting all generated files in the same directory would -# otherwise cause performance problems for the file system. - -CREATE_SUBDIRS = NO - -# The OUTPUT_LANGUAGE tag is used to specify the language in which all -# documentation generated by doxygen is written. Doxygen will use this -# information to generate all constant output in the proper language. -# The default language is English, other supported languages are: -# Afrikaans, Arabic, Brazilian, Catalan, Chinese, Chinese-Traditional, -# Croatian, Czech, Danish, Dutch, Esperanto, Farsi, Finnish, French, German, -# Greek, Hungarian, Italian, Japanese, Japanese-en (Japanese with English -# messages), Korean, Korean-en, Lithuanian, Norwegian, Macedonian, Persian, -# Polish, Portuguese, Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, -# Slovene, Spanish, Swedish, Ukrainian, and Vietnamese. - -OUTPUT_LANGUAGE = English - -# If the BRIEF_MEMBER_DESC tag is set to YES (the default) Doxygen will -# include brief member descriptions after the members that are listed in -# the file and class documentation (similar to JavaDoc). -# Set to NO to disable this. - -BRIEF_MEMBER_DESC = YES - -# If the REPEAT_BRIEF tag is set to YES (the default) Doxygen will prepend -# the brief description of a member or function before the detailed description. -# Note: if both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the -# brief descriptions will be completely suppressed. - -REPEAT_BRIEF = YES - -# This tag implements a quasi-intelligent brief description abbreviator -# that is used to form the text in various listings. Each string -# in this list, if found as the leading text of the brief description, will be -# stripped from the text and the result after processing the whole list, is -# used as the annotated text. Otherwise, the brief description is used as-is. -# If left blank, the following values are used ("$name" is automatically -# replaced with the name of the entity): "The $name class" "The $name widget" -# "The $name file" "is" "provides" "specifies" "contains" -# "represents" "a" "an" "the" - -ABBREVIATE_BRIEF = - -# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then -# Doxygen will generate a detailed section even if there is only a brief -# description. - -ALWAYS_DETAILED_SEC = NO - -# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all -# inherited members of a class in the documentation of that class as if those -# members were ordinary class members. Constructors, destructors and assignment -# operators of the base classes will not be shown. - -INLINE_INHERITED_MEMB = NO - -# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full -# path before files name in the file list and in the header files. If set -# to NO the shortest path that makes the file name unique will be used. - -FULL_PATH_NAMES = YES - -# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag -# can be used to strip a user-defined part of the path. Stripping is -# only done if one of the specified strings matches the left-hand part of -# the path. The tag can be used to show relative paths in the file list. -# If left blank the directory from which doxygen is run is used as the -# path to strip. - -STRIP_FROM_PATH = - -# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of -# the path mentioned in the documentation of a class, which tells -# the reader which header file to include in order to use a class. -# If left blank only the name of the header file containing the class -# definition is used. Otherwise one should specify the include paths that -# are normally passed to the compiler using the -I flag. - -STRIP_FROM_INC_PATH = - -# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter -# (but less readable) file names. This can be useful if your file system -# doesn't support long names like on DOS, Mac, or CD-ROM. - -SHORT_NAMES = NO - -# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen -# will interpret the first line (until the first dot) of a JavaDoc-style -# comment as the brief description. If set to NO, the JavaDoc -# comments will behave just like regular Qt-style comments -# (thus requiring an explicit @brief command for a brief description.) - -JAVADOC_AUTOBRIEF = NO - -# If the QT_AUTOBRIEF tag is set to YES then Doxygen will -# interpret the first line (until the first dot) of a Qt-style -# comment as the brief description. If set to NO, the comments -# will behave just like regular Qt-style comments (thus requiring -# an explicit \brief command for a brief description.) - -QT_AUTOBRIEF = NO - -# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen -# treat a multi-line C++ special comment block (i.e. a block of //! or /// -# comments) as a brief description. This used to be the default behaviour. -# The new default is to treat a multi-line C++ comment block as a detailed -# description. Set this tag to YES if you prefer the old behaviour instead. - -MULTILINE_CPP_IS_BRIEF = NO - -# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented -# member inherits the documentation from any documented member that it -# re-implements. - -INHERIT_DOCS = YES - -# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce -# a new page for each member. If set to NO, the documentation of a member will -# be part of the file/class/namespace that contains it. - -SEPARATE_MEMBER_PAGES = NO - -# The TAB_SIZE tag can be used to set the number of spaces in a tab. -# Doxygen uses this value to replace tabs by spaces in code fragments. - -TAB_SIZE = 8 - -# This tag can be used to specify a number of aliases that acts -# as commands in the documentation. An alias has the form "name=value". -# For example adding "sideeffect=\par Side Effects:\n" will allow you to -# put the command \sideeffect (or @sideeffect) in the documentation, which -# will result in a user-defined paragraph with heading "Side Effects:". -# You can put \n's in the value part of an alias to insert newlines. - -ALIASES = - -# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C -# sources only. Doxygen will then generate output that is more tailored for C. -# For instance, some of the names that are used will be different. The list -# of all members will be omitted, etc. - -OPTIMIZE_OUTPUT_FOR_C = NO - -# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java -# sources only. Doxygen will then generate output that is more tailored for -# Java. For instance, namespaces will be presented as packages, qualified -# scopes will look different, etc. - -OPTIMIZE_OUTPUT_JAVA = NO - -# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran -# sources only. Doxygen will then generate output that is more tailored for -# Fortran. - -OPTIMIZE_FOR_FORTRAN = NO - -# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL -# sources. Doxygen will then generate output that is tailored for -# VHDL. - -OPTIMIZE_OUTPUT_VHDL = NO - -# Doxygen selects the parser to use depending on the extension of the files it -# parses. With this tag you can assign which parser to use for a given extension. -# Doxygen has a built-in mapping, but you can override or extend it using this -# tag. The format is ext=language, where ext is a file extension, and language -# is one of the parsers supported by doxygen: IDL, Java, Javascript, CSharp, C, -# C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, C++. For instance to make -# doxygen treat .inc files as Fortran files (default is PHP), and .f files as C -# (default is Fortran), use: inc=Fortran f=C. Note that for custom extensions -# you also need to set FILE_PATTERNS otherwise the files are not read by doxygen. - -EXTENSION_MAPPING = - -# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want -# to include (a tag file for) the STL sources as input, then you should -# set this tag to YES in order to let doxygen match functions declarations and -# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. -# func(std::string) {}). This also makes the inheritance and collaboration -# diagrams that involve STL classes more complete and accurate. - -BUILTIN_STL_SUPPORT = YES - -# If you use Microsoft's C++/CLI language, you should set this option to YES to -# enable parsing support. - -CPP_CLI_SUPPORT = NO - -# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. -# Doxygen will parse them like normal C++ but will assume all classes use public -# instead of private inheritance when no explicit protection keyword is present. - -SIP_SUPPORT = NO - -# For Microsoft's IDL there are propget and propput attributes to indicate getter -# and setter methods for a property. Setting this option to YES (the default) -# will make doxygen replace the get and set methods by a property in the -# documentation. This will only work if the methods are indeed getting or -# setting a simple type. If this is not the case, or you want to show the -# methods anyway, you should set this option to NO. - -IDL_PROPERTY_SUPPORT = YES - -# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC -# tag is set to YES, then doxygen will reuse the documentation of the first -# member in the group (if any) for the other members of the group. By default -# all members of a group must be documented explicitly. - -DISTRIBUTE_GROUP_DOC = NO - -# Set the SUBGROUPING tag to YES (the default) to allow class member groups of -# the same type (for instance a group of public functions) to be put as a -# subgroup of that type (e.g. under the Public Functions section). Set it to -# NO to prevent subgrouping. Alternatively, this can be done per class using -# the \nosubgrouping command. - -SUBGROUPING = YES - -# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and -# unions are shown inside the group in which they are included (e.g. using -# @ingroup) instead of on a separate page (for HTML and Man pages) or -# section (for LaTeX and RTF). - -INLINE_GROUPED_CLASSES = NO - -# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and -# unions with only public data fields will be shown inline in the documentation -# of the scope in which they are defined (i.e. file, namespace, or group -# documentation), provided this scope is documented. If set to NO (the default), -# structs, classes, and unions are shown on a separate page (for HTML and Man -# pages) or section (for LaTeX and RTF). - -INLINE_SIMPLE_STRUCTS = NO - -# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum -# is documented as struct, union, or enum with the name of the typedef. So -# typedef struct TypeS {} TypeT, will appear in the documentation as a struct -# with name TypeT. When disabled the typedef will appear as a member of a file, -# namespace, or class. And the struct will be named TypeS. This can typically -# be useful for C code in case the coding convention dictates that all compound -# types are typedef'ed and only the typedef is referenced, never the tag name. - -TYPEDEF_HIDES_STRUCT = NO - -# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to -# determine which symbols to keep in memory and which to flush to disk. -# When the cache is full, less often used symbols will be written to disk. -# For small to medium size projects (<1000 input files) the default value is -# probably good enough. For larger projects a too small cache size can cause -# doxygen to be busy swapping symbols to and from disk most of the time -# causing a significant performance penalty. -# If the system has enough physical memory increasing the cache will improve the -# performance by keeping more symbols in memory. Note that the value works on -# a logarithmic scale so increasing the size by one will roughly double the -# memory usage. The cache size is given by this formula: -# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, -# corresponding to a cache size of 2^16 = 65536 symbols - -SYMBOL_CACHE_SIZE = 0 - -#--------------------------------------------------------------------------- -# Build related configuration options -#--------------------------------------------------------------------------- - -# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in -# documentation are documented, even if no documentation was available. -# Private class members and static file members will be hidden unless -# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES - -EXTRACT_ALL = YES - -# If the EXTRACT_PRIVATE tag is set to YES all private members of a class -# will be included in the documentation. - -EXTRACT_PRIVATE = YES - -# If the EXTRACT_STATIC tag is set to YES all static members of a file -# will be included in the documentation. - -EXTRACT_STATIC = YES - -# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) -# defined locally in source files will be included in the documentation. -# If set to NO only classes defined in header files are included. - -EXTRACT_LOCAL_CLASSES = YES - -# This flag is only useful for Objective-C code. When set to YES local -# methods, which are defined in the implementation section but not in -# the interface are included in the documentation. -# If set to NO (the default) only methods in the interface are included. - -EXTRACT_LOCAL_METHODS = NO - -# If this flag is set to YES, the members of anonymous namespaces will be -# extracted and appear in the documentation as a namespace called -# 'anonymous_namespace{file}', where file will be replaced with the base -# name of the file that contains the anonymous namespace. By default -# anonymous namespaces are hidden. - -EXTRACT_ANON_NSPACES = YES - -# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all -# undocumented members of documented classes, files or namespaces. -# If set to NO (the default) these members will be included in the -# various overviews, but no documentation section is generated. -# This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_MEMBERS = NO - -# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all -# undocumented classes that are normally visible in the class hierarchy. -# If set to NO (the default) these classes will be included in the various -# overviews. This option has no effect if EXTRACT_ALL is enabled. - -HIDE_UNDOC_CLASSES = NO - -# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all -# friend (class|struct|union) declarations. -# If set to NO (the default) these declarations will be included in the -# documentation. - -HIDE_FRIEND_COMPOUNDS = NO - -# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any -# documentation blocks found inside the body of a function. -# If set to NO (the default) these blocks will be appended to the -# function's detailed documentation block. - -HIDE_IN_BODY_DOCS = NO - -# The INTERNAL_DOCS tag determines if documentation -# that is typed after a \internal command is included. If the tag is set -# to NO (the default) then the documentation will be excluded. -# Set it to YES to include the internal documentation. - -INTERNAL_DOCS = NO - -# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate -# file names in lower-case letters. If set to YES upper-case letters are also -# allowed. This is useful if you have classes or files whose names only differ -# in case and if your file system supports case sensitive file names. Windows -# and Mac users are advised to set this option to NO. - -CASE_SENSE_NAMES = YES - -# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen -# will show members with their full class and namespace scopes in the -# documentation. If set to YES the scope will be hidden. - -HIDE_SCOPE_NAMES = NO - -# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen -# will put a list of the files that are included by a file in the documentation -# of that file. - -SHOW_INCLUDE_FILES = YES - -# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen -# will list include files with double quotes in the documentation -# rather than with sharp brackets. - -FORCE_LOCAL_INCLUDES = NO - -# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] -# is inserted in the documentation for inline members. - -INLINE_INFO = YES - -# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen -# will sort the (detailed) documentation of file and class members -# alphabetically by member name. If set to NO the members will appear in -# declaration order. - -SORT_MEMBER_DOCS = YES - -# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the -# brief documentation of file, namespace and class members alphabetically -# by member name. If set to NO (the default) the members will appear in -# declaration order. - -SORT_BRIEF_DOCS = NO - -# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen -# will sort the (brief and detailed) documentation of class members so that -# constructors and destructors are listed first. If set to NO (the default) -# the constructors will appear in the respective orders defined by -# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. -# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO -# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. - -SORT_MEMBERS_CTORS_1ST = NO - -# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the -# hierarchy of group names into alphabetical order. If set to NO (the default) -# the group names will appear in their defined order. - -SORT_GROUP_NAMES = NO - -# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be -# sorted by fully-qualified names, including namespaces. If set to -# NO (the default), the class list will be sorted only by class name, -# not including the namespace part. -# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. -# Note: This option applies only to the class list, not to the -# alphabetical list. - -SORT_BY_SCOPE_NAME = NO - -# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to -# do proper type resolution of all parameters of a function it will reject a -# match between the prototype and the implementation of a member function even -# if there is only one candidate or it is obvious which candidate to choose -# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen -# will still accept a match between prototype and implementation in such cases. - -STRICT_PROTO_MATCHING = NO - -# The GENERATE_TODOLIST tag can be used to enable (YES) or -# disable (NO) the todo list. This list is created by putting \todo -# commands in the documentation. - -GENERATE_TODOLIST = YES - -# The GENERATE_TESTLIST tag can be used to enable (YES) or -# disable (NO) the test list. This list is created by putting \test -# commands in the documentation. - -GENERATE_TESTLIST = YES - -# The GENERATE_BUGLIST tag can be used to enable (YES) or -# disable (NO) the bug list. This list is created by putting \bug -# commands in the documentation. - -GENERATE_BUGLIST = YES - -# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or -# disable (NO) the deprecated list. This list is created by putting -# \deprecated commands in the documentation. - -GENERATE_DEPRECATEDLIST= YES - -# The ENABLED_SECTIONS tag can be used to enable conditional -# documentation sections, marked by \if sectionname ... \endif. - -ENABLED_SECTIONS = - -# The MAX_INITIALIZER_LINES tag determines the maximum number of lines -# the initial value of a variable or macro consists of for it to appear in -# the documentation. If the initializer consists of more lines than specified -# here it will be hidden. Use a value of 0 to hide initializers completely. -# The appearance of the initializer of individual variables and macros in the -# documentation can be controlled using \showinitializer or \hideinitializer -# command in the documentation regardless of this setting. - -MAX_INITIALIZER_LINES = 30 - -# Set the SHOW_USED_FILES tag to NO to disable the list of files generated -# at the bottom of the documentation of classes and structs. If set to YES the -# list will mention the files that were used to generate the documentation. - -SHOW_USED_FILES = YES - -# If the sources in your project are distributed over multiple directories -# then setting the SHOW_DIRECTORIES tag to YES will show the directory hierarchy -# in the documentation. The default is NO. - -SHOW_DIRECTORIES = NO - -# Set the SHOW_FILES tag to NO to disable the generation of the Files page. -# This will remove the Files entry from the Quick Index and from the -# Folder Tree View (if specified). The default is YES. - -SHOW_FILES = YES - -# Set the SHOW_NAMESPACES tag to NO to disable the generation of the -# Namespaces page. -# This will remove the Namespaces entry from the Quick Index -# and from the Folder Tree View (if specified). The default is YES. - -SHOW_NAMESPACES = YES - -# The FILE_VERSION_FILTER tag can be used to specify a program or script that -# doxygen should invoke to get the current version for each file (typically from -# the version control system). Doxygen will invoke the program by executing (via -# popen()) the command , where is the value of -# the FILE_VERSION_FILTER tag, and is the name of an input file -# provided by doxygen. Whatever the program writes to standard output -# is used as the file version. See the manual for examples. - -FILE_VERSION_FILTER = - -# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed -# by doxygen. The layout file controls the global structure of the generated -# output files in an output format independent way. The create the layout file -# that represents doxygen's defaults, run doxygen with the -l option. -# You can optionally specify a file name after the option, if omitted -# DoxygenLayout.xml will be used as the name of the layout file. - -LAYOUT_FILE = - -# The CITE_BIB_FILES tag can be used to specify one or more bib files -# containing the references data. This must be a list of .bib files. The -# .bib extension is automatically appended if omitted. Using this command -# requires the bibtex tool to be installed. See also -# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style -# of the bibliography can be controlled using LATEX_BIB_STYLE. - -CITE_BIB_FILES = - -#--------------------------------------------------------------------------- -# configuration options related to warning and progress messages -#--------------------------------------------------------------------------- - -# The QUIET tag can be used to turn on/off the messages that are generated -# by doxygen. Possible values are YES and NO. If left blank NO is used. - -QUIET = NO - -# The WARNINGS tag can be used to turn on/off the warning messages that are -# generated by doxygen. Possible values are YES and NO. If left blank -# NO is used. - -WARNINGS = YES - -# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings -# for undocumented members. If EXTRACT_ALL is set to YES then this flag will -# automatically be disabled. - -WARN_IF_UNDOCUMENTED = YES - -# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for -# potential errors in the documentation, such as not documenting some -# parameters in a documented function, or documenting parameters that -# don't exist or using markup commands wrongly. - -WARN_IF_DOC_ERROR = YES - -# The WARN_NO_PARAMDOC option can be enabled to get warnings for -# functions that are documented, but have no documentation for their parameters -# or return value. If set to NO (the default) doxygen will only warn about -# wrong or incomplete parameter documentation, but not about the absence of -# documentation. - -WARN_NO_PARAMDOC = NO - -# The WARN_FORMAT tag determines the format of the warning messages that -# doxygen can produce. The string should contain the $file, $line, and $text -# tags, which will be replaced by the file and line number from which the -# warning originated and the warning text. Optionally the format may contain -# $version, which will be replaced by the version of the file (if it could -# be obtained via FILE_VERSION_FILTER) - -WARN_FORMAT = "$file:$line: $text" - -# The WARN_LOGFILE tag can be used to specify a file to which warning -# and error messages should be written. If left blank the output is written -# to stderr. - -WARN_LOGFILE = - -#--------------------------------------------------------------------------- -# configuration options related to the input files -#--------------------------------------------------------------------------- - -# The INPUT tag can be used to specify the files and/or directories that contain -# documented source files. You may enter file names like "myfile.cpp" or -# directories like "/usr/src/myproject". Separate the files or directories -# with spaces. - -INPUT = doxygen-mainpage \ - include \ - src \ - -# This tag can be used to specify the character encoding of the source files -# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is -# also the default input encoding. Doxygen uses libiconv (or the iconv built -# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for -# the list of possible encodings. - -INPUT_ENCODING = UTF-8 - -# If the value of the INPUT tag contains directories, you can use the -# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank the following patterns are tested: -# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh -# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py -# *.f90 *.f *.for *.vhd *.vhdl - -FILE_PATTERNS = - -# The RECURSIVE tag can be used to turn specify whether or not subdirectories -# should be searched for input files as well. Possible values are YES and NO. -# If left blank NO is used. - -RECURSIVE = NO - -# The EXCLUDE tag can be used to specify files and/or directories that should -# excluded from the INPUT source files. This way you can easily exclude a -# subdirectory from a directory tree whose root is specified with the INPUT tag. -# Note that relative paths are relative to directory from which doxygen is run. - -EXCLUDE = - -# The EXCLUDE_SYMLINKS tag can be used select whether or not files or -# directories that are symbolic links (a Unix file system feature) are excluded -# from the input. - -EXCLUDE_SYMLINKS = NO - -# If the value of the INPUT tag contains directories, you can use the -# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude -# certain files from those directories. Note that the wildcards are matched -# against the file with absolute path, so to exclude all test directories -# for example use the pattern */test/* - -EXCLUDE_PATTERNS = - -# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names -# (namespaces, classes, functions, etc.) that should be excluded from the -# output. The symbol name can be a fully qualified name, a word, or if the -# wildcard * is used, a substring. Examples: ANamespace, AClass, -# AClass::ANamespace, ANamespace::*Test - -EXCLUDE_SYMBOLS = - -# The EXAMPLE_PATH tag can be used to specify one or more files or -# directories that contain example code fragments that are included (see -# the \include command). - -EXAMPLE_PATH = - -# If the value of the EXAMPLE_PATH tag contains directories, you can use the -# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp -# and *.h) to filter out the source-files in the directories. If left -# blank all files are included. - -EXAMPLE_PATTERNS = - -# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be -# searched for input files to be used with the \include or \dontinclude -# commands irrespective of the value of the RECURSIVE tag. -# Possible values are YES and NO. If left blank NO is used. - -EXAMPLE_RECURSIVE = NO - -# The IMAGE_PATH tag can be used to specify one or more files or -# directories that contain image that are included in the documentation (see -# the \image command). - -IMAGE_PATH = - -# The INPUT_FILTER tag can be used to specify a program that doxygen should -# invoke to filter for each input file. Doxygen will invoke the filter program -# by executing (via popen()) the command , where -# is the value of the INPUT_FILTER tag, and is the name of an -# input file. Doxygen will then use the output that the filter program writes -# to standard output. -# If FILTER_PATTERNS is specified, this tag will be -# ignored. - -INPUT_FILTER = - -# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern -# basis. -# Doxygen will compare the file name with each pattern and apply the -# filter if there is a match. -# The filters are a list of the form: -# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further -# info on how filters are used. If FILTER_PATTERNS is empty or if -# non of the patterns match the file name, INPUT_FILTER is applied. - -FILTER_PATTERNS = - -# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using -# INPUT_FILTER) will be used to filter the input files when producing source -# files to browse (i.e. when SOURCE_BROWSER is set to YES). - -FILTER_SOURCE_FILES = NO - -# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file -# pattern. A pattern will override the setting for FILTER_PATTERN (if any) -# and it is also possible to disable source filtering for a specific pattern -# using *.ext= (so without naming a filter). This option only has effect when -# FILTER_SOURCE_FILES is enabled. - -FILTER_SOURCE_PATTERNS = - -#--------------------------------------------------------------------------- -# configuration options related to source browsing -#--------------------------------------------------------------------------- - -# If the SOURCE_BROWSER tag is set to YES then a list of source files will -# be generated. Documented entities will be cross-referenced with these sources. -# Note: To get rid of all source code in the generated output, make sure also -# VERBATIM_HEADERS is set to NO. - -SOURCE_BROWSER = YES - -# Setting the INLINE_SOURCES tag to YES will include the body -# of functions and classes directly in the documentation. - -INLINE_SOURCES = NO - -# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct -# doxygen to hide any special comment blocks from generated source code -# fragments. Normal C and C++ comments will always remain visible. - -STRIP_CODE_COMMENTS = YES - -# If the REFERENCED_BY_RELATION tag is set to YES -# then for each documented function all documented -# functions referencing it will be listed. - -REFERENCED_BY_RELATION = YES - -# If the REFERENCES_RELATION tag is set to YES -# then for each documented function all documented entities -# called/used by that function will be listed. - -REFERENCES_RELATION = YES - -# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) -# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from -# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will -# link to the source code. -# Otherwise they will link to the documentation. - -REFERENCES_LINK_SOURCE = YES - -# If the USE_HTAGS tag is set to YES then the references to source code -# will point to the HTML generated by the htags(1) tool instead of doxygen -# built-in source browser. The htags tool is part of GNU's global source -# tagging system (see http://www.gnu.org/software/global/global.html). You -# will need version 4.8.6 or higher. - -USE_HTAGS = NO - -# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen -# will generate a verbatim copy of the header file for each class for -# which an include is specified. Set to NO to disable this. - -VERBATIM_HEADERS = YES - -#--------------------------------------------------------------------------- -# configuration options related to the alphabetical class index -#--------------------------------------------------------------------------- - -# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index -# of all compounds will be generated. Enable this if the project -# contains a lot of classes, structs, unions or interfaces. - -ALPHABETICAL_INDEX = YES - -# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then -# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns -# in which this list will be split (can be a number in the range [1..20]) - -COLS_IN_ALPHA_INDEX = 5 - -# In case all classes in a project start with a common prefix, all -# classes will be put under the same header in the alphabetical index. -# The IGNORE_PREFIX tag can be used to specify one or more prefixes that -# should be ignored while generating the index headers. - -IGNORE_PREFIX = - -#--------------------------------------------------------------------------- -# configuration options related to the HTML output -#--------------------------------------------------------------------------- - -# If the GENERATE_HTML tag is set to YES (the default) Doxygen will -# generate HTML output. - -GENERATE_HTML = YES - -# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `html' will be used as the default path. - -HTML_OUTPUT = html - -# The HTML_FILE_EXTENSION tag can be used to specify the file extension for -# each generated HTML page (for example: .htm,.php,.asp). If it is left blank -# doxygen will generate files with .html extension. - -HTML_FILE_EXTENSION = .html - -# The HTML_HEADER tag can be used to specify a personal HTML header for -# each generated HTML page. If it is left blank doxygen will generate a -# standard header. Note that when using a custom header you are responsible -# for the proper inclusion of any scripts and style sheets that doxygen -# needs, which is dependent on the configuration options used. -# It is adviced to generate a default header using "doxygen -w html -# header.html footer.html stylesheet.css YourConfigFile" and then modify -# that header. Note that the header is subject to change so you typically -# have to redo this when upgrading to a newer version of doxygen or when -# changing the value of configuration settings such as GENERATE_TREEVIEW! - -HTML_HEADER = - -# The HTML_FOOTER tag can be used to specify a personal HTML footer for -# each generated HTML page. If it is left blank doxygen will generate a -# standard footer. - -HTML_FOOTER = - -# If the HTML_TIMESTAMP tag is set to YES then the generated HTML documentation will contain the timesstamp. - -HTML_TIMESTAMP = NO - -# The HTML_STYLESHEET tag can be used to specify a user-defined cascading -# style sheet that is used by each HTML page. It can be used to -# fine-tune the look of the HTML output. If the tag is left blank doxygen -# will generate a default style sheet. Note that doxygen will try to copy -# the style sheet file to the HTML output directory, so don't put your own -# stylesheet in the HTML output directory as well, or it will be erased! - -HTML_STYLESHEET = - -# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or -# other source files which should be copied to the HTML output directory. Note -# that these files will be copied to the base HTML output directory. Use the -# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these -# files. In the HTML_STYLESHEET file, use the file name only. Also note that -# the files will be copied as-is; there are no commands or markers available. - -HTML_EXTRA_FILES = - -# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. -# Doxygen will adjust the colors in the stylesheet and background images -# according to this color. Hue is specified as an angle on a colorwheel, -# see http://en.wikipedia.org/wiki/Hue for more information. -# For instance the value 0 represents red, 60 is yellow, 120 is green, -# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. -# The allowed range is 0 to 359. - -HTML_COLORSTYLE_HUE = 220 - -# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of -# the colors in the HTML output. For a value of 0 the output will use -# grayscales only. A value of 255 will produce the most vivid colors. - -HTML_COLORSTYLE_SAT = 100 - -# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to -# the luminance component of the colors in the HTML output. Values below -# 100 gradually make the output lighter, whereas values above 100 make -# the output darker. The value divided by 100 is the actual gamma applied, -# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, -# and 100 does not change the gamma. - -HTML_COLORSTYLE_GAMMA = 80 - -# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML -# page will contain the date and time when the page was generated. Setting -# this to NO can help when comparing the output of multiple runs. - -HTML_TIMESTAMP = YES - -# If the HTML_ALIGN_MEMBERS tag is set to YES, the members of classes, -# files or namespaces will be aligned in HTML using tables. If set to -# NO a bullet list will be used. - -HTML_ALIGN_MEMBERS = YES - -# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML -# documentation will contain sections that can be hidden and shown after the -# page has loaded. For this to work a browser that supports -# JavaScript and DHTML is required (for instance Mozilla 1.0+, Firefox -# Netscape 6.0+, Internet explorer 5.0+, Konqueror, or Safari). - -HTML_DYNAMIC_SECTIONS = NO - -# If the GENERATE_DOCSET tag is set to YES, additional index files -# will be generated that can be used as input for Apple's Xcode 3 -# integrated development environment, introduced with OSX 10.5 (Leopard). -# To create a documentation set, doxygen will generate a Makefile in the -# HTML output directory. Running make will produce the docset in that -# directory and running "make install" will install the docset in -# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find -# it at startup. -# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html -# for more information. - -GENERATE_DOCSET = NO - -# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the -# feed. A documentation feed provides an umbrella under which multiple -# documentation sets from a single provider (such as a company or product suite) -# can be grouped. - -DOCSET_FEEDNAME = "Doxygen generated docs" - -# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that -# should uniquely identify the documentation set bundle. This should be a -# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen -# will append .docset to the name. - -DOCSET_BUNDLE_ID = org.veripool.verilator - -# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely identify -# the documentation publisher. This should be a reverse domain-name style -# string, e.g. com.mycompany.MyDocSet.documentation. - -DOCSET_PUBLISHER_ID = org.veripool.verilator.documentation - -# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. - -DOCSET_PUBLISHER_NAME = Veripool - -# If the GENERATE_HTMLHELP tag is set to YES, additional index files -# will be generated that can be used as input for tools like the -# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) -# of the generated HTML documentation. - -GENERATE_HTMLHELP = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can -# be used to specify the file name of the resulting .chm file. You -# can add a path in front of the file if the result should not be -# written to the html output directory. - -CHM_FILE = - -# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can -# be used to specify the location (absolute path including file name) of -# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run -# the HTML help compiler on the generated index.hhp. - -HHC_LOCATION = - -# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag -# controls if a separate .chi index file is generated (YES) or that -# it should be included in the master .chm file (NO). - -GENERATE_CHI = NO - -# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING -# is used to encode HtmlHelp index (hhk), content (hhc) and project file -# content. - -CHM_INDEX_ENCODING = - -# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag -# controls whether a binary table of contents is generated (YES) or a -# normal table of contents (NO) in the .chm file. - -BINARY_TOC = NO - -# The TOC_EXPAND flag can be set to YES to add extra items for group members -# to the contents of the HTML help documentation and to the tree view. - -TOC_EXPAND = NO - -# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and -# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated -# that can be used as input for Qt's qhelpgenerator to generate a -# Qt Compressed Help (.qch) of the generated HTML documentation. - -GENERATE_QHP = NO - -# If the QHG_LOCATION tag is specified, the QCH_FILE tag can -# be used to specify the file name of the resulting .qch file. -# The path specified is relative to the HTML output folder. - -QCH_FILE = - -# The QHP_NAMESPACE tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#namespace - -QHP_NAMESPACE = org.doxygen.Project - -# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating -# Qt Help Project output. For more information please see -# http://doc.trolltech.com/qthelpproject.html#virtual-folders - -QHP_VIRTUAL_FOLDER = doc - -# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to -# add. For more information please see -# http://doc.trolltech.com/qthelpproject.html#custom-filters - -QHP_CUST_FILTER_NAME = - -# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the -# custom filter to add. For more information please see -# -# Qt Help Project / Custom Filters. - -QHP_CUST_FILTER_ATTRS = - -# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this -# project's -# filter section matches. -# -# Qt Help Project / Filter Attributes. - -QHP_SECT_FILTER_ATTRS = - -# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can -# be used to specify the location of Qt's qhelpgenerator. -# If non-empty doxygen will try to run qhelpgenerator on the generated -# .qhp file. - -QHG_LOCATION = - -# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files -# will be generated, which together with the HTML files, form an Eclipse help -# plugin. To install this plugin and make it available under the help contents -# menu in Eclipse, the contents of the directory containing the HTML and XML -# files needs to be copied into the plugins directory of eclipse. The name of -# the directory within the plugins directory should be the same as -# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before -# the help appears. - -GENERATE_ECLIPSEHELP = NO - -# A unique identifier for the eclipse help plugin. When installing the plugin -# the directory name containing the HTML and XML files should also have -# this name. - -ECLIPSE_DOC_ID = org.doxygen.Project - -# The DISABLE_INDEX tag can be used to turn on/off the condensed index at -# top of each HTML page. The value NO (the default) enables the index and -# the value YES disables it. - -DISABLE_INDEX = NO - -# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values -# (range [0,1..20]) that doxygen will group on one line in the generated HTML -# documentation. Note that a value of 0 will completely suppress the enum -# values from appearing in the overview section. - -ENUM_VALUES_PER_LINE = 4 - -# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index -# structure should be generated to display hierarchical information. -# If the tag value is set to YES, a side panel will be generated -# containing a tree-like index structure (just like the one that -# is generated for HTML Help). For this to work a browser that supports -# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). -# Windows users are probably better off using the HTML help feature. - -GENERATE_TREEVIEW = YES - -# By enabling USE_INLINE_TREES, doxygen will generate the Groups, Directories, -# and Class Hierarchy pages using a tree view instead of an ordered list. - -USE_INLINE_TREES = NO - -# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be -# used to set the initial width (in pixels) of the frame in which the tree -# is shown. - -TREEVIEW_WIDTH = 250 - -# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open -# links to external symbols imported via tag files in a separate window. - -EXT_LINKS_IN_WINDOW = NO - -# Use this tag to change the font size of Latex formulas included -# as images in the HTML documentation. The default is 10. Note that -# when you change the font size after a successful doxygen run you need -# to manually remove any form_*.png images from the HTML output directory -# to force them to be regenerated. - -FORMULA_FONTSIZE = 10 - -# Use the FORMULA_TRANPARENT tag to determine whether or not the images -# generated for formulas are transparent PNGs. Transparent PNGs are -# not supported properly for IE 6.0, but are supported on all modern browsers. -# Note that when changing this option you need to delete any form_*.png files -# in the HTML output before the changes have effect. - -FORMULA_TRANSPARENT = YES - -# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax -# (see http://www.mathjax.org) which uses client side Javascript for the -# rendering instead of using prerendered bitmaps. Use this if you do not -# have LaTeX installed or if you want to formulas look prettier in the HTML -# output. When enabled you also need to install MathJax separately and -# configure the path to it using the MATHJAX_RELPATH option. - -USE_MATHJAX = NO - -# When MathJax is enabled you need to specify the location relative to the -# HTML output directory using the MATHJAX_RELPATH option. The destination -# directory should contain the MathJax.js script. For instance, if the mathjax -# directory is located at the same level as the HTML output directory, then -# MATHJAX_RELPATH should be ../mathjax. The default value points to the -# mathjax.org site, so you can quickly see the result without installing -# MathJax, but it is strongly recommended to install a local copy of MathJax -# before deployment. - -MATHJAX_RELPATH = http://www.mathjax.org/mathjax - -# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension -# names that should be enabled during MathJax rendering. - -MATHJAX_EXTENSIONS = - -# When the SEARCHENGINE tag is enabled doxygen will generate a search box -# for the HTML output. The underlying search engine uses javascript -# and DHTML and should work on any modern browser. Note that when using -# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets -# (GENERATE_DOCSET) there is already a search function so this one should -# typically be disabled. For large projects the javascript based search engine -# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. - -SEARCHENGINE = YES - -# When the SERVER_BASED_SEARCH tag is enabled the search engine will be -# implemented using a PHP enabled web server instead of at the web client -# using Javascript. Doxygen will generate the search PHP script and index -# file to put on the web server. The advantage of the server -# based approach is that it scales better to large projects and allows -# full text search. The disadvantages are that it is more difficult to setup -# and does not have live searching capabilities. - -SERVER_BASED_SEARCH = NO - -#--------------------------------------------------------------------------- -# configuration options related to the LaTeX output -#--------------------------------------------------------------------------- - -# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will -# generate Latex output. - -GENERATE_LATEX = NO - -# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `latex' will be used as the default path. - -LATEX_OUTPUT = latex - -# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be -# invoked. If left blank `latex' will be used as the default command name. -# Note that when enabling USE_PDFLATEX this option is only used for -# generating bitmaps for formulas in the HTML output, but not in the -# Makefile that is written to the output directory. - -LATEX_CMD_NAME = latex - -# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to -# generate index for LaTeX. If left blank `makeindex' will be used as the -# default command name. - -MAKEINDEX_CMD_NAME = makeindex - -# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact -# LaTeX documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_LATEX = NO - -# The PAPER_TYPE tag can be used to set the paper type that is used -# by the printer. Possible values are: a4, letter, legal and -# executive. If left blank a4wide will be used. - -PAPER_TYPE = a4 - -# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX -# packages that should be included in the LaTeX output. - -EXTRA_PACKAGES = - -# The LATEX_HEADER tag can be used to specify a personal LaTeX header for -# the generated latex document. The header should contain everything until -# the first chapter. If it is left blank doxygen will generate a -# standard header. Notice: only use this tag if you know what you are doing! - -LATEX_HEADER = - -# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for -# the generated latex document. The footer should contain everything after -# the last chapter. If it is left blank doxygen will generate a -# standard footer. Notice: only use this tag if you know what you are doing! - -LATEX_FOOTER = - -# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated -# is prepared for conversion to pdf (using ps2pdf). The pdf file will -# contain links (just like the HTML output) instead of page references -# This makes the output suitable for online browsing using a pdf viewer. - -PDF_HYPERLINKS = YES - -# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of -# plain latex in the generated Makefile. Set this option to YES to get a -# higher quality PDF documentation. - -USE_PDFLATEX = YES - -# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. -# command to the generated LaTeX files. This will instruct LaTeX to keep -# running if errors occur, instead of asking the user for help. -# This option is also used when generating formulas in HTML. - -LATEX_BATCHMODE = NO - -# If LATEX_HIDE_INDICES is set to YES then doxygen will not -# include the index chapters (such as File Index, Compound Index, etc.) -# in the output. - -LATEX_HIDE_INDICES = NO - -# If LATEX_SOURCE_CODE is set to YES then doxygen will include -# source code with syntax highlighting in the LaTeX output. -# Note that which sources are shown also depends on other settings -# such as SOURCE_BROWSER. - -LATEX_SOURCE_CODE = NO - -# The LATEX_BIB_STYLE tag can be used to specify the style to use for the -# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See -# http://en.wikipedia.org/wiki/BibTeX for more info. - -LATEX_BIB_STYLE = plain - -#--------------------------------------------------------------------------- -# configuration options related to the RTF output -#--------------------------------------------------------------------------- - -# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output -# The RTF output is optimized for Word 97 and may not look very pretty with -# other RTF readers or editors. - -GENERATE_RTF = NO - -# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `rtf' will be used as the default path. - -RTF_OUTPUT = rtf - -# If the COMPACT_RTF tag is set to YES Doxygen generates more compact -# RTF documents. This may be useful for small projects and may help to -# save some trees in general. - -COMPACT_RTF = NO - -# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated -# will contain hyperlink fields. The RTF file will -# contain links (just like the HTML output) instead of page references. -# This makes the output suitable for online browsing using WORD or other -# programs which support those fields. -# Note: wordpad (write) and others do not support links. - -RTF_HYPERLINKS = NO - -# Load stylesheet definitions from file. Syntax is similar to doxygen's -# config file, i.e. a series of assignments. You only have to provide -# replacements, missing definitions are set to their default value. - -RTF_STYLESHEET_FILE = - -# Set optional variables used in the generation of an rtf document. -# Syntax is similar to doxygen's config file. - -RTF_EXTENSIONS_FILE = - -#--------------------------------------------------------------------------- -# configuration options related to the man page output -#--------------------------------------------------------------------------- - -# If the GENERATE_MAN tag is set to YES (the default) Doxygen will -# generate man pages - -GENERATE_MAN = NO - -# The MAN_OUTPUT tag is used to specify where the man pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `man' will be used as the default path. - -MAN_OUTPUT = man - -# The MAN_EXTENSION tag determines the extension that is added to -# the generated man pages (default is the subroutine's section .3) - -MAN_EXTENSION = .3 - -# If the MAN_LINKS tag is set to YES and Doxygen generates man output, -# then it will generate one additional man file for each entity -# documented in the real man page(s). These additional files -# only source the real man page, but without them the man command -# would be unable to find the correct page. The default is NO. - -MAN_LINKS = NO - -#--------------------------------------------------------------------------- -# configuration options related to the XML output -#--------------------------------------------------------------------------- - -# If the GENERATE_XML tag is set to YES Doxygen will -# generate an XML file that captures the structure of -# the code including all documentation. - -GENERATE_XML = NO - -# The XML_OUTPUT tag is used to specify where the XML pages will be put. -# If a relative path is entered the value of OUTPUT_DIRECTORY will be -# put in front of it. If left blank `xml' will be used as the default path. - -XML_OUTPUT = xml - -# The XML_SCHEMA tag can be used to specify an XML schema, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_SCHEMA = - -# The XML_DTD tag can be used to specify an XML DTD, -# which can be used by a validating XML parser to check the -# syntax of the XML files. - -XML_DTD = - -# If the XML_PROGRAMLISTING tag is set to YES Doxygen will -# dump the program listings (including syntax highlighting -# and cross-referencing information) to the XML output. Note that -# enabling this will significantly increase the size of the XML output. - -XML_PROGRAMLISTING = YES - -#--------------------------------------------------------------------------- -# configuration options for the AutoGen Definitions output -#--------------------------------------------------------------------------- - -# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will -# generate an AutoGen Definitions (see autogen.sf.net) file -# that captures the structure of the code including all -# documentation. Note that this feature is still experimental -# and incomplete at the moment. - -GENERATE_AUTOGEN_DEF = NO - -#--------------------------------------------------------------------------- -# configuration options related to the Perl module output -#--------------------------------------------------------------------------- - -# If the GENERATE_PERLMOD tag is set to YES Doxygen will -# generate a Perl module file that captures the structure of -# the code including all documentation. Note that this -# feature is still experimental and incomplete at the -# moment. - -GENERATE_PERLMOD = NO - -# If the PERLMOD_LATEX tag is set to YES Doxygen will generate -# the necessary Makefile rules, Perl scripts and LaTeX code to be able -# to generate PDF and DVI output from the Perl module output. - -PERLMOD_LATEX = NO - -# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be -# nicely formatted so it can be parsed by a human reader. -# This is useful -# if you want to understand what is going on. -# On the other hand, if this -# tag is set to NO the size of the Perl module output will be much smaller -# and Perl will parse it just the same. - -PERLMOD_PRETTY = YES - -# The names of the make variables in the generated doxyrules.make file -# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. -# This is useful so different doxyrules.make files included by the same -# Makefile don't overwrite each other's variables. - -PERLMOD_MAKEVAR_PREFIX = - -#--------------------------------------------------------------------------- -# Configuration options related to the preprocessor -#--------------------------------------------------------------------------- - -# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will -# evaluate all C-preprocessor directives found in the sources and include -# files. - -ENABLE_PREPROCESSING = YES - -# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro -# names in the source code. If set to NO (the default) only conditional -# compilation will be performed. Macro expansion can be done in a controlled -# way by setting EXPAND_ONLY_PREDEF to YES. - -MACRO_EXPANSION = NO - -# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES -# then the macro expansion is limited to the macros specified with the -# PREDEFINED and EXPAND_AS_DEFINED tags. - -EXPAND_ONLY_PREDEF = NO - -# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files -# pointed to by INCLUDE_PATH will be searched when a #include is found. - -SEARCH_INCLUDES = YES - -# The INCLUDE_PATH tag can be used to specify one or more directories that -# contain include files that are not input files but should be processed by -# the preprocessor. - -INCLUDE_PATH = - -# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard -# patterns (like *.h and *.hpp) to filter out the header-files in the -# directories. If left blank, the patterns specified with FILE_PATTERNS will -# be used. - -INCLUDE_FILE_PATTERNS = - -# The PREDEFINED tag can be used to specify one or more macro names that -# are defined before the preprocessor is started (similar to the -D option of -# gcc). The argument of the tag is a list of macros of the form: name -# or name=definition (no spaces). If the definition and the = are -# omitted =1 is assumed. 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Note that doxygen if the -# number of direct children of the root node in a graph is already larger than -# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note -# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. - -DOT_GRAPH_MAX_NODES = 50 - -# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the -# graphs generated by dot. A depth value of 3 means that only nodes reachable -# from the root by following a path via at most 3 edges will be shown. Nodes -# that lay further from the root node will be omitted. Note that setting this -# option to 1 or 2 may greatly reduce the computation time needed for large -# code bases. Also note that the size of a graph can be further restricted by -# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. - -MAX_DOT_GRAPH_DEPTH = 0 - -# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent -# background. This is disabled by default, because dot on Windows does not -# seem to support this out of the box. Warning: Depending on the platform used, -# enabling this option may lead to badly anti-aliased labels on the edges of -# a graph (i.e. they become hard to read). - -DOT_TRANSPARENT = NO - -# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output -# files in one run (i.e. multiple -o and -T options on the command line). This -# makes dot run faster, but since only newer versions of dot (>1.8.10) -# support this, this feature is disabled by default. - -DOT_MULTI_TARGETS = NO - -# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will -# generate a legend page explaining the meaning of the various boxes and -# arrows in the dot generated graphs. - -GENERATE_LEGEND = YES - -# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will -# remove the intermediate dot files that are used to generate -# the various graphs. - -DOT_CLEANUP = YES diff --git a/docs/internals.rst b/docs/internals.rst index 496598fb4..af5923188 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -872,7 +872,7 @@ There are scripts included to facilitate fuzzing of Verilator. These have been successfully used to find a number of bugs in the frontend. The scripts are based on using `American fuzzy -lop `__ on a Debian-like system. +lop `__ on a Debian-like system. To get started, cd to "nodist/fuzzer/" and run "./all". A sudo password may be required to setup the system for fuzzing. diff --git a/src/pod2latexfix b/src/pod2latexfix index 42e7a82a1..6cf21004e 100755 --- a/src/pod2latexfix +++ b/src/pod2latexfix @@ -23,7 +23,7 @@ my $header = ."\n" ."\\setlength{\\parindent}{0pt} \\setlength{\\parskip}{\\baselineskip}\n" ."\n" - ."\\title{\\includegraphics[width=6cm]{docs/verilator_logo.png}\\\\ ${Opt_DistTitle}}\n" + ."\\title{\\includegraphics[width=6cm]{docs/_static/verilator_logo.png}\\\\ ${Opt_DistTitle}}\n" ."\\date{${Opt_DistDate}}\n" ."\\author{https:\/\/verilator.org}\n" ."\\lhead[${Opt_DistTitle}]{${Opt_DistTitle}}\n" From a29ac44af9bea558fb5095efd0e9c0896ebf8ae1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=80lex=20Torregrosa?= <78434679+atorregrosasmd@users.noreply.github.com> Date: Tue, 6 Apr 2021 22:18:58 +0200 Subject: [PATCH 071/110] Add FST SystemC tracing (#2806) --- bin/verilator | 15 +- include/verilated_fst_c.h | 2 +- include/verilated_fst_sc.cpp | 84 + include/verilated_fst_sc.h | 123 ++ src/V3EmitMk.cpp | 8 +- test_regress/driver.pl | 5 +- .../t/t_interface_ref_trace_fst_sc.out | 769 +++++++ .../t/t_interface_ref_trace_fst_sc.pl | 29 + test_regress/t/t_trace_abort_fst_sc.out | 113 + test_regress/t/t_trace_abort_fst_sc.pl | 29 + .../t/t_trace_array_fst_portable_sc.pl | 33 + test_regress/t/t_trace_array_fst_sc.out | 104 + test_regress/t/t_trace_array_fst_sc.pl | 31 + .../t/t_trace_array_fst_threads_1_sc.pl | 32 + .../t/t_trace_array_fst_threads_2_sc.pl | 32 + test_regress/t/t_trace_complex_fst_sc.out | 284 +++ test_regress/t/t_trace_complex_fst_sc.pl | 31 + .../t/t_trace_complex_fst_threads_1_sc.pl | 32 + .../t/t_trace_complex_fst_threads_2_sc.pl | 32 + .../t/t_trace_complex_params_fst_sc.out | 284 +++ .../t/t_trace_complex_params_fst_sc.pl | 31 + .../t/t_trace_complex_structs_fst_sc.out | 411 ++++ .../t/t_trace_complex_structs_fst_sc.pl | 31 + test_regress/t/t_trace_fst_sc.out | 1824 +++++++++++++++++ test_regress/t/t_trace_fst_sc.pl | 30 + test_regress/t/t_trace_fst_sc.v | 98 + test_regress/t/t_trace_litendian_fst_sc.out | 168 ++ test_regress/t/t_trace_litendian_fst_sc.pl | 35 + .../t/t_trace_packed_struct_fst_sc.out | 73 + .../t/t_trace_packed_struct_fst_sc.pl | 31 + test_regress/t/t_trace_primitive_fst_sc.pl | 28 + test_regress/t/t_trace_string_fst_sc.pl | 29 + 32 files changed, 4850 insertions(+), 11 deletions(-) create mode 100644 include/verilated_fst_sc.cpp create mode 100644 include/verilated_fst_sc.h create mode 100644 test_regress/t/t_interface_ref_trace_fst_sc.out create mode 100755 test_regress/t/t_interface_ref_trace_fst_sc.pl create mode 100644 test_regress/t/t_trace_abort_fst_sc.out create mode 100755 test_regress/t/t_trace_abort_fst_sc.pl create mode 100755 test_regress/t/t_trace_array_fst_portable_sc.pl create mode 100644 test_regress/t/t_trace_array_fst_sc.out create mode 100755 test_regress/t/t_trace_array_fst_sc.pl create mode 100755 test_regress/t/t_trace_array_fst_threads_1_sc.pl create mode 100755 test_regress/t/t_trace_array_fst_threads_2_sc.pl create mode 100644 test_regress/t/t_trace_complex_fst_sc.out create mode 100755 test_regress/t/t_trace_complex_fst_sc.pl create mode 100755 test_regress/t/t_trace_complex_fst_threads_1_sc.pl create mode 100755 test_regress/t/t_trace_complex_fst_threads_2_sc.pl create mode 100644 test_regress/t/t_trace_complex_params_fst_sc.out create mode 100755 test_regress/t/t_trace_complex_params_fst_sc.pl create mode 100644 test_regress/t/t_trace_complex_structs_fst_sc.out create mode 100755 test_regress/t/t_trace_complex_structs_fst_sc.pl create mode 100644 test_regress/t/t_trace_fst_sc.out create mode 100755 test_regress/t/t_trace_fst_sc.pl create mode 100644 test_regress/t/t_trace_fst_sc.v create mode 100644 test_regress/t/t_trace_litendian_fst_sc.out create mode 100755 test_regress/t/t_trace_litendian_fst_sc.pl create mode 100644 test_regress/t/t_trace_packed_struct_fst_sc.out create mode 100755 test_regress/t/t_trace_packed_struct_fst_sc.pl create mode 100755 test_regress/t/t_trace_primitive_fst_sc.pl create mode 100755 test_regress/t/t_trace_string_fst_sc.pl diff --git a/bin/verilator b/bin/verilator index c503e4036..d606fad82 100755 --- a/bin/verilator +++ b/bin/verilator @@ -5390,8 +5390,19 @@ build time, should you require. =item How do I generate FST waveforms (aka dumps or traces) in SystemC? -The FST library from GTKWave does not currently support SystemC; use VCD -format instead. +FST is a trace file format developed by GTKWave. Verilator provides basic FST +support. To dump traces in FST format, add the --trace-fst switch to Verilator +and either A. use $dumpfile/$dumpvars in Verilog as described in the FST +example above, or B. in C++ change the include described in the FST example +above: + + #include "verilated_fst_sc.h" + VerilatedFstSc* tfp = new VerilatedFstSc; + +Note that currently supporting both FST and VCD in a single simulation is +impossible, but such requirement should be rare. You can however ifdef +around the trace format in your C++ main loop, and select VCD or FST at +build time, should you require. =item How do I view waveforms (aka dumps or traces)? diff --git a/include/verilated_fst_c.h b/include/verilated_fst_c.h index 28c51c9cc..3a8e404c5 100644 --- a/include/verilated_fst_c.h +++ b/include/verilated_fst_c.h @@ -128,7 +128,7 @@ template <> void VerilatedTrace::set_time_resolution(const std::st /// Create a FST dump file in C standalone (no SystemC) simulations. /// Also derived for use in SystemC simulations. -class VerilatedFstC final { +class VerilatedFstC VL_NOT_FINAL { VerilatedFst m_sptrace; // Trace file being created // CONSTRUCTORS diff --git a/include/verilated_fst_sc.cpp b/include/verilated_fst_sc.cpp new file mode 100644 index 000000000..4f14fffdb --- /dev/null +++ b/include/verilated_fst_sc.cpp @@ -0,0 +1,84 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//============================================================================= +// +// THIS MODULE IS PUBLICLY LICENSED +// +// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//============================================================================= +/// +/// \file +/// \brief Verilated tracing in FST for SystemC implementation code +/// +/// This file must be compiled and linked against all Verilated objects +/// that use --sc --trace-fst. +/// +/// Use "verilator --sc --trace-fst" to add this to the Makefile for the linker. +/// +//============================================================================= + +#include "verilatedos.h" +#include "verilated_fst_sc.h" + +//====================================================================== +//====================================================================== + +//-------------------------------------------------- +// SystemC 2.1.v1 +// cppcheck-suppress unusedFunction +void VerilatedFstSc::write_comment(const std::string&) {} +void VerilatedFstSc::trace(const unsigned int&, const std::string&, const char**) {} + +#define DECL_TRACE_METHOD_A(tp) \ + void VerilatedFstSc::trace(const tp& object, const std::string& name) {} +#define DECL_TRACE_METHOD_B(tp) \ + void VerilatedFstSc::trace(const tp& object, const std::string& name, int width) {} + +// clang-format off +#if (SYSTEMC_VERSION >= 20171012) + DECL_TRACE_METHOD_A( sc_event ) + DECL_TRACE_METHOD_A( sc_time ) +#endif + + DECL_TRACE_METHOD_A( bool ) + DECL_TRACE_METHOD_A( sc_dt::sc_bit ) + DECL_TRACE_METHOD_A( sc_dt::sc_logic ) + + DECL_TRACE_METHOD_B( unsigned char ) + DECL_TRACE_METHOD_B( unsigned short ) + DECL_TRACE_METHOD_B( unsigned int ) + DECL_TRACE_METHOD_B( unsigned long ) +#ifdef SYSTEMC_64BIT_PATCHES + DECL_TRACE_METHOD_B( unsigned long long) +#endif + DECL_TRACE_METHOD_B( char ) + DECL_TRACE_METHOD_B( short ) + DECL_TRACE_METHOD_B( int ) + DECL_TRACE_METHOD_B( long ) + DECL_TRACE_METHOD_B( sc_dt::int64 ) + DECL_TRACE_METHOD_B( sc_dt::uint64 ) + + DECL_TRACE_METHOD_A( float ) + DECL_TRACE_METHOD_A( double ) + DECL_TRACE_METHOD_A( sc_dt::sc_int_base ) + DECL_TRACE_METHOD_A( sc_dt::sc_uint_base ) + DECL_TRACE_METHOD_A( sc_dt::sc_signed ) + DECL_TRACE_METHOD_A( sc_dt::sc_unsigned ) + + DECL_TRACE_METHOD_A( sc_dt::sc_fxval ) + DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast ) + DECL_TRACE_METHOD_A( sc_dt::sc_fxnum ) + DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast ) + + DECL_TRACE_METHOD_A( sc_dt::sc_bv_base ) + DECL_TRACE_METHOD_A( sc_dt::sc_lv_base ) +// clang-format on + +#undef DECL_TRACE_METHOD_A +#undef DECL_TRACE_METHOD_B + +//******************************************************************** diff --git a/include/verilated_fst_sc.h b/include/verilated_fst_sc.h new file mode 100644 index 000000000..b58e98fe7 --- /dev/null +++ b/include/verilated_fst_sc.h @@ -0,0 +1,123 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//============================================================================= +// +// Copyright 2001-2021 by Wilson Snyder. This program is free software; you can +// redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//============================================================================= +/// +/// \file +/// \brief Verilator tracing in FST format for SystemC header +/// +/// User wrapper code should use this header when creating FST SystemC +/// traces. +/// +/// This class is not threadsafe, as the SystemC kernel is not threadsafe. +/// +//============================================================================= + +#ifndef _VERILATED_FST_SC_H_ +#define _VERILATED_FST_SC_H_ 1 + +#include "verilatedos.h" +#include "verilated_sc.h" +#include "verilated_fst_c.h" + +//============================================================================= +// VerilatedFstSc +/// +/// This class is passed to the SystemC simulation kernel, just like a +/// documented SystemC trace format. + +class VerilatedFstSc final : sc_trace_file, public VerilatedFstC { + // CONSTRUCTORS + VL_UNCOPYABLE(VerilatedFstSc); + +public: + VerilatedFstSc() { + sc_get_curr_simcontext()->add_trace_file(this); + // We want to avoid a depreciated warning, but still be back compatible. + // Turning off the message just for this still results in an + // annoying "to turn off" message. + sc_time t1sec(1, SC_SEC); + if (t1sec.to_default_time_units() != 0) { + sc_time tunits(1.0 / t1sec.to_default_time_units(), SC_SEC); + spTrace()->set_time_unit(tunits.to_string()); + } + spTrace()->set_time_resolution(sc_get_time_resolution().to_string()); + } + virtual ~VerilatedFstSc() { close(); } + + // METHODS + /// Called by SystemC simulate() + virtual void cycle(bool delta_cycle) { + if (!delta_cycle) { this->dump(sc_time_stamp().to_double()); } + } + +private: + /// Fake outs for linker + +#ifdef NC_SYSTEMC + // Cadence Incisive has these as abstract functions so we must create them + virtual void set_time_unit(int exponent10_seconds) {} // deprecated +#endif + virtual void set_time_unit(double v, sc_time_unit tu) {} // LCOV_EXCL_LINE + +//-------------------------------------------------- +// SystemC 2.1.v1 +#define DECL_TRACE_METHOD_A(tp) virtual void trace(const tp& object, const std::string& name); +#define DECL_TRACE_METHOD_B(tp) \ + virtual void trace(const tp& object, const std::string& name, int width); + + virtual void write_comment(const std::string&); + virtual void trace(const unsigned int&, const std::string&, const char**); + + // clang-format off + // Formatting matches that of sc_trace.h +#if (SYSTEMC_VERSION >= 20171012) + DECL_TRACE_METHOD_A( sc_event ) + DECL_TRACE_METHOD_A( sc_time ) +#endif + + DECL_TRACE_METHOD_A( bool ) + DECL_TRACE_METHOD_A( sc_dt::sc_bit ) + DECL_TRACE_METHOD_A( sc_dt::sc_logic ) + + DECL_TRACE_METHOD_B( unsigned char ) + DECL_TRACE_METHOD_B( unsigned short ) + DECL_TRACE_METHOD_B( unsigned int ) + DECL_TRACE_METHOD_B( unsigned long ) +#ifdef SYSTEMC_64BIT_PATCHES + DECL_TRACE_METHOD_B( unsigned long long) +#endif + DECL_TRACE_METHOD_B( char ) + DECL_TRACE_METHOD_B( short ) + DECL_TRACE_METHOD_B( int ) + DECL_TRACE_METHOD_B( long ) + DECL_TRACE_METHOD_B( sc_dt::int64 ) + DECL_TRACE_METHOD_B( sc_dt::uint64 ) + + DECL_TRACE_METHOD_A( float ) + DECL_TRACE_METHOD_A( double ) + DECL_TRACE_METHOD_A( sc_dt::sc_int_base ) + DECL_TRACE_METHOD_A( sc_dt::sc_uint_base ) + DECL_TRACE_METHOD_A( sc_dt::sc_signed ) + DECL_TRACE_METHOD_A( sc_dt::sc_unsigned ) + + DECL_TRACE_METHOD_A( sc_dt::sc_fxval ) + DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast ) + DECL_TRACE_METHOD_A( sc_dt::sc_fxnum ) + DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast ) + + DECL_TRACE_METHOD_A( sc_dt::sc_bv_base ) + DECL_TRACE_METHOD_A( sc_dt::sc_lv_base ) + // clang-format on + +#undef DECL_TRACE_METHOD_A +#undef DECL_TRACE_METHOD_B +}; + +#endif // Guard diff --git a/src/V3EmitMk.cpp b/src/V3EmitMk.cpp index 6d090de60..dc8b932c7 100644 --- a/src/V3EmitMk.cpp +++ b/src/V3EmitMk.cpp @@ -108,13 +108,7 @@ public: if (v3Global.opt.trace()) { putMakeClassEntry(of, v3Global.opt.traceSourceBase() + "_c.cpp"); if (v3Global.opt.systemC()) { - if (v3Global.opt.traceFormat() != TraceFormat::VCD) { - v3warn(E_UNSUPPORTED, - "Unsupported: This trace format is not supported " - "in SystemC, use VCD format."); - } else { - putMakeClassEntry(of, v3Global.opt.traceSourceLang() + ".cpp"); - } + putMakeClassEntry(of, v3Global.opt.traceSourceLang() + ".cpp"); } } if (v3Global.opt.mtasks()) putMakeClassEntry(of, "verilated_threads.cpp"); diff --git a/test_regress/driver.pl b/test_regress/driver.pl index cb68f1885..aceaed76a 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -888,7 +888,8 @@ sub compile_vlt_flags { $self->{sc} = 1 if ($checkflags =~ /-sc\b/); $self->{trace} = ($opt_trace || $checkflags =~ /-trace\b/ || $checkflags =~ /-trace-fst\b/); - $self->{trace_format} = (($checkflags =~ /-trace-fst/ && 'fst-c') + $self->{trace_format} = (($checkflags =~ /-trace-fst/ && $self->{sc} && 'fst-sc') + || ($checkflags =~ /-trace-fst/ && !$self->{sc} && 'fst-c') || ($self->{sc} && 'vcd-sc') || (!$self->{sc} && 'vcd-c')); $self->{savable} = 1 if ($checkflags =~ /-savable\b/); @@ -1747,6 +1748,7 @@ sub _make_main { print $fh "#include \"verilated.h\"\n"; print $fh "#include \"systemc.h\"\n" if $self->sc; print $fh "#include \"verilated_fst_c.h\"\n" if $self->{trace} && $self->{trace_format} eq 'fst-c'; + print $fh "#include \"verilated_fst_sc.h\"\n" if $self->{trace} && $self->{trace_format} eq 'fst-sc'; print $fh "#include \"verilated_vcd_c.h\"\n" if $self->{trace} && $self->{trace_format} eq 'vcd-c'; print $fh "#include \"verilated_vcd_sc.h\"\n" if $self->{trace} && $self->{trace_format} eq 'vcd-sc'; print $fh "#include \"verilated_save.h\"\n" if $self->{savable}; @@ -1808,6 +1810,7 @@ sub _make_main { $fh->print("#if VM_TRACE\n"); $fh->print(" contextp->traceEverOn(true);\n"); $fh->print(" std::unique_ptr tfp{new VerilatedFstC};\n") if $self->{trace_format} eq 'fst-c'; + $fh->print(" std::unique_ptr tfp{new VerilatedFstSc};\n") if $self->{trace_format} eq 'fst-sc'; $fh->print(" std::unique_ptr tfp{new VerilatedVcdC};\n") if $self->{trace_format} eq 'vcd-c'; $fh->print(" std::unique_ptr tfp{new VerilatedVcdSc};\n") if $self->{trace_format} eq 'vcd-sc'; $fh->print(" topp->trace(tfp.get(), 99);\n"); diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.out b/test_regress/t/t_interface_ref_trace_fst_sc.out new file mode 100644 index 000000000..48b2e47ab --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_fst_sc.out @@ -0,0 +1,769 @@ +$date + Thu Apr 1 14:51:24 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc $end +$scope module intf_1 $end +$var wire 1 ! clk $end +$var wire 32 " cyc $end +$var integer 32 # value $end +$scope module the_struct $end +$var logic 32 $ val100 $end +$var logic 32 % val200 $end +$upscope $end +$upscope $end +$scope module s1 $end +$scope module intf_for_struct $end +$var wire 1 ! clk $end +$var wire 32 " cyc $end +$var integer 32 # value $end +$scope module the_struct $end +$var logic 32 $ val100 $end +$var logic 32 % val200 $end +$upscope $end +$upscope $end +$upscope $end +$scope module c1 $end +$scope module intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc $end +$var integer 32 # value $end +$scope module the_struct $end +$var logic 32 $ val100 $end +$var logic 32 % val200 $end +$upscope $end +$upscope $end +$upscope $end +$scope module a $end +$scope module intf_one $end +$var wire 1 ! clk $end +$var wire 32 " cyc $end +$var integer 32 # value $end +$scope module the_struct $end +$var logic 32 $ val100 $end +$var logic 32 % val200 $end +$upscope $end +$upscope $end +$scope module ac1 $end +$scope module intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc $end +$var integer 32 # value $end +$scope module the_struct $end +$var logic 32 $ val100 $end +$var logic 32 % val200 $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module abcdefghijklmnopqrstuvwxyz $end +$scope module intf_two $end +$var wire 1 ! clk $end +$var wire 32 " cyc $end +$var integer 32 # value $end +$scope module the_struct $end +$var logic 32 $ val100 $end +$var logic 32 % val200 $end +$upscope $end +$upscope $end +$scope module ac2 $end +$scope module intf_for_check $end +$var wire 1 ! clk $end +$var wire 32 " cyc $end +$var integer 32 # value $end +$scope module the_struct $end +$var logic 32 $ val100 $end +$var logic 32 % val200 $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$scope module intf_2 $end +$var wire 1 ! clk $end +$var wire 32 " cyc $end +$var integer 32 & value $end +$scope module the_struct $end +$var logic 32 ' val100 $end +$var logic 32 ( val200 $end +$upscope $end +$upscope $end +$scope module s2 $end +$scope module intf_for_struct $end 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+b00000000000000000000000011011110 % +b00000000000000000000000000010111 & +b00000000000000000000000001111011 ' +b00000000000000000000000011011111 ( +b00000000000000000000001111111110 ) +b00000000000000000000010001100010 * +b00000000000000000000010011000110 + +b00000000000000000000001111111111 , +b00000000000000000000010001100011 - +b00000000000000000000010011000111 . +#211 +#212 +#213 +#214 diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.pl b/test_regress/t/t_interface_ref_trace_fst_sc.pl new file mode 100755 index 000000000..4f2137308 --- /dev/null +++ b/test_regress/t/t_interface_ref_trace_fst_sc.pl @@ -0,0 +1,29 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_interface_ref_trace.v"); + + compile( + verilator_flags2 => ['--trace-structs --trace-fst --sc'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} +ok(1); +1; diff --git a/test_regress/t/t_trace_abort_fst_sc.out b/test_regress/t/t_trace_abort_fst_sc.out new file mode 100644 index 000000000..a2de34150 --- /dev/null +++ b/test_regress/t/t_trace_abort_fst_sc.out @@ -0,0 +1,113 @@ +$date + Thu Apr 1 14:55:09 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var logic 3 " cyc $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b000 " +0! +$end +#10 +1! +b001 " +#11 +#12 +#13 +#14 +#15 +0! +#16 +#17 +#18 +#19 +#20 +1! +b010 " +#21 +#22 +#23 +#24 +#25 +0! +#26 +#27 +#28 +#29 +#30 +1! +b011 " +#31 +#32 +#33 +#34 +#35 +0! +#36 +#37 +#38 +#39 +#40 +1! +b100 " +#41 +#42 +#43 +#44 +#45 +0! +#46 +#47 +#48 +#49 +#50 +1! +b101 " +#51 +#52 +#53 +#54 +#55 +0! +#56 +#57 +#58 +#59 +#60 +1! +b110 " +#61 +#62 +#63 +#64 +#65 +0! +#66 +#67 +#68 +#69 +#70 +1! +b111 " +#71 +#72 +#73 +#74 +#75 +0! +#76 +#77 +#78 +#79 diff --git a/test_regress/t/t_trace_abort_fst_sc.pl b/test_regress/t/t_trace_abort_fst_sc.pl new file mode 100755 index 000000000..cef721403 --- /dev/null +++ b/test_regress/t/t_trace_abort_fst_sc.pl @@ -0,0 +1,29 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Geza Lore. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt_all => 1); +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_abort.v"); + + compile( + verilator_flags2 => ['--sc --trace-fst'], + ); + + execute( + fails => 1, + ); + + fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); +} +ok(1); +1; diff --git a/test_regress/t/t_trace_array_fst_portable_sc.pl b/test_regress/t/t_trace_array_fst_portable_sc.pl new file mode 100755 index 000000000..2476e5765 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_portable_sc.pl @@ -0,0 +1,33 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_array.v"); + golden_filename("t/t_trace_array_fst_sc.out"); + + compile( + verilator_flags2 => ['--sc --trace-fst --trace-structs', + '-CFLAGS -DVL_PORTABLE_ONLY'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_array_fst_sc.out b/test_regress/t/t_trace_array_fst_sc.out new file mode 100644 index 000000000..7a218ecd0 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_sc.out @@ -0,0 +1,104 @@ +$date + Thu Apr 1 15:02:16 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc $end +$scope module biggie $end +$var logic 1048577 # d $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars 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# +b00000000000000000000000000000110 " +#61 +#62 +#63 +#64 diff --git a/test_regress/t/t_trace_array_fst_sc.pl b/test_regress/t/t_trace_array_fst_sc.pl new file mode 100755 index 000000000..dda6a138a --- /dev/null +++ b/test_regress/t/t_trace_array_fst_sc.pl @@ -0,0 +1,31 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_array.v"); + + compile( + verilator_flags2 => ['--sc --trace-fst --trace-structs'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_array_fst_threads_1_sc.pl b/test_regress/t/t_trace_array_fst_threads_1_sc.pl new file mode 100755 index 000000000..5f7e2bb69 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_1_sc.pl @@ -0,0 +1,32 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_array.v"); + golden_filename("t/t_trace_array_fst_sc.out"); + + compile( + verilator_flags2 => ['--sc --trace-fst --trace-threads 1 --trace-structs'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_array_fst_threads_2_sc.pl b/test_regress/t/t_trace_array_fst_threads_2_sc.pl new file mode 100755 index 000000000..1cfe67da8 --- /dev/null +++ b/test_regress/t/t_trace_array_fst_threads_2_sc.pl @@ -0,0 +1,32 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_array.v"); + golden_filename("t/t_trace_array_fst_sc.out"); + + compile( + verilator_flags2 => ['--sc --trace-fst --trace-threads 2 --trace-structs'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_complex_fst_sc.out b/test_regress/t/t_trace_complex_fst_sc.out new file mode 100644 index 000000000..85c002638 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_sc.out @@ -0,0 +1,284 @@ +$date + Thu Apr 1 15:12:03 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc $end +$var logic 2 # v_strp $end +$var logic 4 $ v_strp_strp $end +$var logic 2 % v_unip_strp $end +$var logic 2 & v_arrp $end +$var logic 4 ' v_arrp_arrp $end +$var logic 4 ( v_arrp_strp $end +$var logic 1 ) v_arru(1) $end +$var logic 1 * v_arru(2) $end +$var logic 1 + v_arru_arru(3)(1) $end +$var logic 1 , v_arru_arru(3)(2) $end +$var logic 1 - v_arru_arru(4)(1) $end +$var logic 1 . v_arru_arru(4)(2) $end +$var logic 2 / v_arru_arrp(3) $end +$var logic 2 0 v_arru_arrp(4) $end +$var logic 2 1 v_arru_strp(3) $end +$var logic 2 2 v_arru_strp(4) $end +$var real 64 3 v_real $end +$var real 64 4 v_arr_real(0) $end +$var real 64 5 v_arr_real(1) $end +$var logic 64 6 v_str32x2 $end +$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end +$attrbegin misc 07 "" 1 $end +$var logic 32 7 v_enumed $end +$attrbegin misc 07 "" 1 $end +$var logic 32 8 v_enumed2 $end +$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end +$attrbegin misc 07 "" 2 $end +$var logic 3 9 v_enumb $end +$var logic 6 : v_enumb2_str $end +$var logic 8 ; unpacked_array(-2) $end +$var logic 8 < unpacked_array(-1) $end +$var logic 8 = unpacked_array(0) $end +$var bit 1 > LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end +$scope module unnamedblk1 $end +$var integer 32 ? b $end +$scope module unnamedblk2 $end +$var integer 32 @ a $end +$upscope $end +$upscope $end +$scope module p2 $end +$var parameter 32 A PARAM $end +$upscope $end +$scope module p3 $end +$var parameter 32 B PARAM $end +$upscope $end +$upscope $end +$scope module $unit $end +$var bit 1 C global_bit $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +1C +b00000000000000000000000000000011 B +b00000000000000000000000000000010 A +b00000000000000000000000000000000 @ +b00000000000000000000000000000000 ? +0> +b00000000 = +b00000000 < +b00000000 ; +b000000 : +b000 9 +b00000000000000000000000000000000 8 +b00000000000000000000000000000000 7 +b0000000000000000000000000000000000000000000000000000000011111111 6 +r0 5 +r0 4 +r0 3 +b00 2 +b00 1 +b00 0 +b00 / +0. +0- +0, +0+ +0* +0) +b0000 ( +b0000 ' +b00 & +b00 % +b0000 $ +b00 # +b00000000000000000000000000000000 " +0! +$end +#10 +1! +b00000000000000000000000000000001 " +b11 # +b1111 $ +b11 % +b11 & +b1111 ' +b1111 ( +b11 / +b11 0 +b11 1 +b11 2 +r0.1 3 +r0.2 4 +r0.3 5 +b0000000000000000000000000000000100000000000000000000000011111110 6 +b00000000000000000000000000000001 7 +b00000000000000000000000000000010 8 +b111 9 +b00000000000000000000000000000101 ? +b00000000000000000000000000000101 @ +#11 +#12 +#13 +#14 +#15 +0! +#16 +#17 +#18 +#19 +#20 +1! +b110 9 +b00000000000000000000000000000100 8 +b00000000000000000000000000000010 7 +b0000000000000000000000000000001000000000000000000000000011111101 6 +r0.6 5 +r0.4 4 +r0.2 3 +b00 2 +b00 1 +b00 0 +b00 / +b0000 ( +b0000 ' +b00 & +b00 % +b0000 $ +b00 # +b00000000000000000000000000000010 " +b111111 : +#21 +#22 +#23 +#24 +#25 +0! +#26 +#27 +#28 +#29 +#30 +1! +b110110 : +b00000000000000000000000000000011 " +b11 # +b1111 $ +b11 % +b11 & +b1111 ' +b1111 ( +b11 / +b11 0 +b11 1 +b11 2 +r0.3 3 +r0.6000000000000001 4 +r0.8999999999999999 5 +b0000000000000000000000000000001100000000000000000000000011111100 6 +b00000000000000000000000000000011 7 +b00000000000000000000000000000110 8 +b101 9 +#31 +#32 +#33 +#34 +#35 +0! +#36 +#37 +#38 +#39 +#40 +1! +b100 9 +b00000000000000000000000000001000 8 +b00000000000000000000000000000100 7 +b0000000000000000000000000000010000000000000000000000000011111011 6 +r1.2 5 +r0.8 4 +r0.4 3 +b00 2 +b00 1 +b00 0 +b00 / +b0000 ( +b0000 ' +b00 & +b00 % +b0000 $ +b00 # +b00000000000000000000000000000100 " +b101101 : +#41 +#42 +#43 +#44 +#45 +0! +#46 +#47 +#48 +#49 +#50 +1! +b100100 : +b00000000000000000000000000000101 " +b11 # +b1111 $ +b11 % +b11 & +b1111 ' +b1111 ( +b11 / +b11 0 +b11 1 +b11 2 +r0.5 3 +r1 4 +r1.5 5 +b0000000000000000000000000000010100000000000000000000000011111010 6 +b00000000000000000000000000000101 7 +b00000000000000000000000000001010 8 +b011 9 +#51 +#52 +#53 +#54 +#55 +0! +#56 +#57 +#58 +#59 +#60 +1! +b010 9 +b00000000000000000000000000001100 8 +b00000000000000000000000000000110 7 +b0000000000000000000000000000011000000000000000000000000011111001 6 +r1.8 5 +r1.2 4 +r0.6 3 +b00 2 +b00 1 +b00 0 +b00 / +b0000 ( +b0000 ' +b00 & +b00 % +b0000 $ +b00 # +b00000000000000000000000000000110 " +b011011 : +#61 +#62 +#63 +#64 diff --git a/test_regress/t/t_trace_complex_fst_sc.pl b/test_regress/t/t_trace_complex_fst_sc.pl new file mode 100755 index 000000000..054451209 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_sc.pl @@ -0,0 +1,31 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_complex.v"); + + compile( + verilator_flags2 => ['--sc --trace-fst'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_complex_fst_threads_1_sc.pl b/test_regress/t/t_trace_complex_fst_threads_1_sc.pl new file mode 100755 index 000000000..94b4913bd --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_1_sc.pl @@ -0,0 +1,32 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_complex.v"); + golden_filename("t/t_trace_complex_fst_sc.out"); + + compile( + verilator_flags2 => ['--sc --trace-fst --trace-threads 1'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_complex_fst_threads_2_sc.pl b/test_regress/t/t_trace_complex_fst_threads_2_sc.pl new file mode 100755 index 000000000..cb8a45396 --- /dev/null +++ b/test_regress/t/t_trace_complex_fst_threads_2_sc.pl @@ -0,0 +1,32 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_complex.v"); + golden_filename("t/t_trace_complex_fst_sc.out"); + + compile( + verilator_flags2 => ['--sc --trace-fst --trace-threads 2'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_complex_params_fst_sc.out b/test_regress/t/t_trace_complex_params_fst_sc.out new file mode 100644 index 000000000..dcfa501c1 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_fst_sc.out @@ -0,0 +1,284 @@ +$date + Thu Apr 1 15:17:39 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc $end +$var logic 2 # v_strp $end +$var logic 4 $ v_strp_strp $end +$var logic 2 % v_unip_strp $end +$var logic 2 & v_arrp $end +$var logic 4 ' v_arrp_arrp $end +$var logic 4 ( v_arrp_strp $end +$var logic 1 ) v_arru(1) $end +$var logic 1 * v_arru(2) $end +$var logic 1 + v_arru_arru(3)(1) $end +$var logic 1 , v_arru_arru(3)(2) $end +$var logic 1 - v_arru_arru(4)(1) $end +$var logic 1 . v_arru_arru(4)(2) $end +$var logic 2 / v_arru_arrp(3) $end +$var logic 2 0 v_arru_arrp(4) $end +$var logic 2 1 v_arru_strp(3) $end +$var logic 2 2 v_arru_strp(4) $end +$var real 64 3 v_real $end +$var real 64 4 v_arr_real(0) $end +$var real 64 5 v_arr_real(1) $end +$var logic 64 6 v_str32x2 $end +$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end +$attrbegin misc 07 "" 1 $end +$var logic 32 7 v_enumed $end +$attrbegin misc 07 "" 1 $end +$var logic 32 8 v_enumed2 $end +$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end +$attrbegin misc 07 "" 2 $end +$var logic 3 9 v_enumb $end +$var logic 6 : v_enumb2_str $end +$var logic 8 ; unpacked_array(-2) $end +$var logic 8 < unpacked_array(-1) $end +$var logic 8 = unpacked_array(0) $end +$var bit 1 > LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end +$scope module unnamedblk1 $end +$var integer 32 ? b $end +$scope module unnamedblk2 $end +$var integer 32 @ a $end +$upscope $end +$upscope $end +$scope module p2 $end +$var parameter 32 A PARAM $end +$upscope $end +$scope module p3 $end +$var parameter 32 B PARAM $end +$upscope $end +$upscope $end +$scope module $unit $end +$var bit 1 C global_bit $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +1C +b00000000000000000000000000000011 B +b00000000000000000000000000000010 A +b00000000000000000000000000000000 @ +b00000000000000000000000000000000 ? +0> +b00000000 = +b00000000 < +b00000000 ; +b000000 : +b000 9 +b00000000000000000000000000000000 8 +b00000000000000000000000000000000 7 +b0000000000000000000000000000000000000000000000000000000011111111 6 +r0 5 +r0 4 +r0 3 +b00 2 +b00 1 +b00 0 +b00 / +0. +0- +0, +0+ +0* +0) +b0000 ( +b0000 ' +b00 & +b00 % +b0000 $ +b00 # +b00000000000000000000000000000000 " +0! +$end +#10 +1! +b00000000000000000000000000000001 " +b11 # +b1111 $ +b11 % +b11 & +b1111 ' +b1111 ( +b11 / +b11 0 +b11 1 +b11 2 +r0.1 3 +r0.2 4 +r0.3 5 +b0000000000000000000000000000000100000000000000000000000011111110 6 +b00000000000000000000000000000001 7 +b00000000000000000000000000000010 8 +b111 9 +b00000000000000000000000000000101 ? +b00000000000000000000000000000101 @ +#11 +#12 +#13 +#14 +#15 +0! +#16 +#17 +#18 +#19 +#20 +1! +b110 9 +b00000000000000000000000000000100 8 +b00000000000000000000000000000010 7 +b0000000000000000000000000000001000000000000000000000000011111101 6 +r0.6 5 +r0.4 4 +r0.2 3 +b00 2 +b00 1 +b00 0 +b00 / +b0000 ( +b0000 ' +b00 & +b00 % +b0000 $ +b00 # +b00000000000000000000000000000010 " +b111111 : +#21 +#22 +#23 +#24 +#25 +0! +#26 +#27 +#28 +#29 +#30 +1! +b110110 : +b00000000000000000000000000000011 " +b11 # +b1111 $ +b11 % +b11 & +b1111 ' +b1111 ( +b11 / +b11 0 +b11 1 +b11 2 +r0.3 3 +r0.6000000000000001 4 +r0.8999999999999999 5 +b0000000000000000000000000000001100000000000000000000000011111100 6 +b00000000000000000000000000000011 7 +b00000000000000000000000000000110 8 +b101 9 +#31 +#32 +#33 +#34 +#35 +0! +#36 +#37 +#38 +#39 +#40 +1! +b100 9 +b00000000000000000000000000001000 8 +b00000000000000000000000000000100 7 +b0000000000000000000000000000010000000000000000000000000011111011 6 +r1.2 5 +r0.8 4 +r0.4 3 +b00 2 +b00 1 +b00 0 +b00 / +b0000 ( +b0000 ' +b00 & +b00 % +b0000 $ +b00 # +b00000000000000000000000000000100 " +b101101 : +#41 +#42 +#43 +#44 +#45 +0! +#46 +#47 +#48 +#49 +#50 +1! +b100100 : +b00000000000000000000000000000101 " +b11 # +b1111 $ +b11 % +b11 & +b1111 ' +b1111 ( +b11 / +b11 0 +b11 1 +b11 2 +r0.5 3 +r1 4 +r1.5 5 +b0000000000000000000000000000010100000000000000000000000011111010 6 +b00000000000000000000000000000101 7 +b00000000000000000000000000001010 8 +b011 9 +#51 +#52 +#53 +#54 +#55 +0! +#56 +#57 +#58 +#59 +#60 +1! +b010 9 +b00000000000000000000000000001100 8 +b00000000000000000000000000000110 7 +b0000000000000000000000000000011000000000000000000000000011111001 6 +r1.8 5 +r1.2 4 +r0.6 3 +b00 2 +b00 1 +b00 0 +b00 / +b0000 ( +b0000 ' +b00 & +b00 % +b0000 $ +b00 # +b00000000000000000000000000000110 " +b011011 : +#61 +#62 +#63 +#64 diff --git a/test_regress/t/t_trace_complex_params_fst_sc.pl b/test_regress/t/t_trace_complex_params_fst_sc.pl new file mode 100755 index 000000000..6d12ba052 --- /dev/null +++ b/test_regress/t/t_trace_complex_params_fst_sc.pl @@ -0,0 +1,31 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_complex.v"); + + compile( + verilator_flags2 => ['--sc --trace-fst --no-trace-structs --trace-params'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.out b/test_regress/t/t_trace_complex_structs_fst_sc.out new file mode 100644 index 000000000..ac1a62444 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_fst_sc.out @@ -0,0 +1,411 @@ +$date + Thu Apr 1 15:22:14 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc $end +$scope module v_strp $end +$var logic 1 # b1 $end +$var logic 1 $ b0 $end +$upscope $end +$scope module v_strp_strp $end +$scope module x1 $end +$var logic 1 % b1 $end +$var logic 1 & b0 $end +$upscope $end +$scope module x0 $end +$var logic 1 ' b1 $end +$var logic 1 ( b0 $end +$upscope $end +$upscope $end +$scope module v_unip_strp $end +$scope module x1 $end +$var logic 1 ) b1 $end +$var logic 1 * b0 $end +$upscope $end +$scope module x0 $end +$var logic 1 ) b1 $end +$var logic 1 * b0 $end +$upscope $end +$upscope $end +$var logic 2 + v_arrp $end +$var logic 2 , v_arrp_arrp(3) $end +$var logic 2 - v_arrp_arrp(4) $end +$scope module v_arrp_strp(3) $end +$var logic 1 . b1 $end +$var logic 1 / b0 $end +$upscope $end +$scope module v_arrp_strp(4) $end +$var logic 1 0 b1 $end +$var logic 1 1 b0 $end +$upscope $end +$var logic 1 2 v_arru(1) $end +$var logic 1 3 v_arru(2) $end +$var logic 1 4 v_arru_arru(3)(1) $end +$var logic 1 5 v_arru_arru(3)(2) $end +$var logic 1 6 v_arru_arru(4)(1) $end +$var logic 1 7 v_arru_arru(4)(2) $end +$var logic 2 8 v_arru_arrp(3) $end +$var logic 2 9 v_arru_arrp(4) $end +$scope module v_arru_strp(3) $end +$var logic 1 : b1 $end +$var logic 1 ; b0 $end +$upscope $end +$scope module v_arru_strp(4) $end +$var logic 1 < b1 $end +$var logic 1 = b0 $end +$upscope $end +$var real 64 > v_real $end +$var real 64 ? v_arr_real(0) $end +$var real 64 @ v_arr_real(1) $end +$scope module v_str32x2(0) $end +$var logic 32 A data $end +$upscope $end +$scope module v_str32x2(1) $end +$var logic 32 B data $end +$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end +$upscope $end +$attrbegin misc 07 "" 1 $end +$var logic 32 C v_enumed $end +$attrbegin misc 07 "" 1 $end +$var logic 32 D v_enumed2 $end +$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end +$attrbegin misc 07 "" 2 $end +$var logic 3 E v_enumb $end +$scope module v_enumb2_str $end +$attrbegin misc 07 "" 2 $end +$var logic 3 F a $end +$attrbegin misc 07 "" 2 $end +$var logic 3 G b $end +$upscope $end +$var logic 8 H unpacked_array(-2) $end +$var logic 8 I unpacked_array(-1) $end +$var logic 8 J unpacked_array(0) $end +$var bit 1 K LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end +$scope module unnamedblk1 $end +$var integer 32 L b $end +$scope module unnamedblk2 $end +$var integer 32 M a $end +$upscope $end +$upscope $end +$upscope $end +$scope module $unit $end +$var bit 1 N global_bit $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +1N +b00000000000000000000000000000000 M +b00000000000000000000000000000000 L +0K +b00000000 J +b00000000 I +b00000000 H +b000 G +b000 F +b000 E +b00000000000000000000000000000000 D +b00000000000000000000000000000000 C +b00000000000000000000000000000000 B +b00000000000000000000000011111111 A +r0 @ +r0 ? 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+r0.6 > +0= +0< +0; +0: +b00 9 +b00 8 +01 +00 +0/ +0. +b00 - +b00 , +b00 + +0* +0) +0( +0' +0& +0% +0$ +0# +b00000000000000000000000000000110 " +b011 F +b011 G +#61 +#62 +#63 +#64 diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.pl b/test_regress/t/t_trace_complex_structs_fst_sc.pl new file mode 100755 index 000000000..dda24acc7 --- /dev/null +++ b/test_regress/t/t_trace_complex_structs_fst_sc.pl @@ -0,0 +1,31 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2009 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_complex.v"); + + compile( + verilator_flags2 => ['--sc --trace-fst --trace-structs --no-trace-params'], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_fst_sc.out b/test_regress/t/t_trace_fst_sc.out new file mode 100644 index 000000000..3fe026e70 --- /dev/null +++ b/test_regress/t/t_trace_fst_sc.out @@ -0,0 +1,1824 @@ +$date + Thu Apr 1 14:28:55 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var int 32 " cyc $end +$var logic 1 # rstn $end +$var real_parameter 64 $ fst_gparam_real $end +$var real_parameter 64 % fst_lparam_real $end +$var real 64 $ fst_real $end +$var integer 32 & fst_integer $end +$var bit 1 ' fst_bit $end +$var logic 1 ( fst_logic $end +$var int 32 ) fst_int $end +$var shortint 16 * fst_shortint $end +$var longint 64 + fst_longint $end +$var byte 8 , fst_byte $end +$var parameter 32 - fst_parameter $end +$var parameter 32 . fst_lparam $end +$var supply0 1 / fst_supply0 $end +$var supply1 1 0 fst_supply1 $end +$var tri0 1 1 fst_tri0 $end +$var tri1 1 2 fst_tri1 $end +$var tri 1 3 fst_tri $end +$var wire 1 4 fst_wire $end +$var logic 5 5 state $end +$scope module test $end +$var wire 1 ! clk $end +$var wire 1 # rstn $end +$var wire 5 5 state $end +$var logic 5 6 state_w $end +$var logic 5 7 state_array(0) $end +$var logic 5 8 state_array(1) $end +$var logic 5 9 state_array(2) $end +$scope module unnamedblk2 $end +$var int 32 : i $end +$upscope $end +$scope module unnamedblk1 $end +$var int 32 ; i $end +$upscope $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000000000000000000000000000000 ; +b00000000000000000000000000000000 : +b00000 9 +b00000 8 +b00000 7 +b00000 6 +b00000 5 +04 +03 +12 +01 +10 +0/ +b00000000000000000000000111001000 . +b00000000000000000000000001111011 - +b00000000 , +b0000000000000000000000000000000000000000000000000000000000000000 + +b0000000000000000 * +b00000000000000000000000000000000 ) +0( +0' +b00000000000000000000000000000000 & +r4.56 % +r1.23 $ +0# +b00000000000000000000000000000000 " +0! +$end +#10 +1! +b00000000000000000000000000000001 " +b00001 5 +b10100 6 +b00001 7 +b00001 8 +b00001 9 +b00000000000000000000000000000011 ; +#11 +#12 +#13 +#14 +#15 +0! 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This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } + +scenarios(vlt_all => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + compile( + verilator_flags2 => ["--trace-fst --sc"], + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} +ok(1); +1; diff --git a/test_regress/t/t_trace_fst_sc.v b/test_regress/t/t_trace_fst_sc.v new file mode 100644 index 000000000..52c148bd5 --- /dev/null +++ b/test_regress/t/t_trace_fst_sc.v @@ -0,0 +1,98 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw +// SPDX-License-Identifier: CC0-1.0 + +module t (/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + int cyc; + reg rstn; + + parameter real fst_gparam_real = 1.23; + localparam real fst_lparam_real = 4.56; + real fst_real = 1.23; + integer fst_integer; + bit fst_bit; + logic fst_logic; + int fst_int; + shortint fst_shortint; + longint fst_longint; + byte fst_byte; + + parameter fst_parameter = 123; + localparam fst_lparam = 456; + supply0 fst_supply0; + supply1 fst_supply1; + tri0 fst_tri0; + tri1 fst_tri1; + tri fst_tri; + wire fst_wire; + + logic [4:0] state; + + Test test (/*AUTOINST*/ + // Outputs + .state (state[4:0]), + // Inputs + .clk (clk), + .rstn (rstn)); + + // Test loop + always @ (posedge clk) begin + cyc <= cyc + 1; + if (cyc==0) begin + // Setup + rstn <= ~'1; + end + else if (cyc<10) begin + rstn <= ~'1; + end + else if (cyc<90) begin + rstn <= ~'0; + end + else if (cyc==99) begin + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + + +module Test ( + input clk, + input rstn, + output logic [4:0] state + ); + + logic [4:0] state_w; + logic [4:0] state_array [3]; + assign state = state_array[0]; + + always_comb begin + state_w[4] = state_array[2][0]; + state_w[3] = state_array[2][4]; + state_w[2] = state_array[2][3] ^ state_array[2][0]; + state_w[1] = state_array[2][2]; + state_w[0] = state_array[2][1]; + end + + always_ff @(posedge clk or negedge rstn) begin + if (!rstn) begin + for (int i = 0; i < 3; i++) + state_array[i] <= 'b1; + end + else begin + for (int i = 0; i < 2; i++) + state_array[i] <= state_array[i+1]; + state_array[2] <= state_w; + end + end + +endmodule diff --git a/test_regress/t/t_trace_litendian_fst_sc.out b/test_regress/t/t_trace_litendian_fst_sc.out new file mode 100644 index 000000000..1a837701c --- /dev/null +++ b/test_regress/t/t_trace_litendian_fst_sc.out @@ -0,0 +1,168 @@ +$date + Thu Apr 1 15:29:34 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var parameter 8 ! P $end +$var wire 1 " clk $end +$var int 32 # cyc $end +$var parameter 8 $ Q $end +$var logic 1 % v_a $end +$var logic 2 & v_b $end +$var logic 8 ' v_c $end +$var logic 9 ( v_d $end +$var logic 16 ) v_e $end +$var logic 17 * v_f $end +$var logic 32 + v_g $end +$var logic 33 , v_h $end +$var logic 64 - v_i $end +$var logic 65 . v_j $end +$var logic 128 / v_k $end +$var logic 129 0 v_l $end +$var logic 256 1 v_m $end +$var logic 257 2 v_n $end +$var logic 512 3 v_o $end +$var logic 3 4 v_p $end +$var logic 15 5 v_q $end +$var logic 31 6 v_r $end +$var logic 63 7 v_s $end +$var logic 127 8 v_t $end +$var logic 255 9 v_u $end +$var logic 511 : v_v $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars 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+b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 8 +b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 9 +b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 : +#11 +#12 +#13 +#14 +#15 +0" +#16 +#17 +#18 +#19 +#20 +1" +b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 : +b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 9 +b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 8 +b111111111111111111111111111111111111111111111111111111111111110 7 +b1111111111111111111111111111110 6 +b111111111111110 5 +b110 4 +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 3 +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 2 +b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 1 +b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 0 +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 / +b11111111111111111111111111111111111111111111111111111111111111110 . +b1111111111111111111111111111111111111111111111111111111111111110 - +b111111111111111111111111111111110 , +b11111111111111111111111111111110 + +b11111111111111110 * +b1111111111111110 ) +b111111110 ( +b11111110 ' +b10 & +0% +b00000000000000000000000000000010 # +#21 +#22 +#23 +#24 +#25 +0" +#26 +#27 +#28 +#29 +#30 +1" +b00000000000000000000000000000011 # +b00 & +b11111100 ' +b111111100 ( +b1111111111111100 ) +b11111111111111100 * +b11111111111111111111111111111100 + +b111111111111111111111111111111100 , +b1111111111111111111111111111111111111111111111111111111111111100 - +b11111111111111111111111111111111111111111111111111111111111111100 . +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 / +b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 0 +b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 1 +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 2 +b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 3 +b100 4 +b111111111111100 5 +b1111111111111111111111111111100 6 +b111111111111111111111111111111111111111111111111111111111111100 7 +b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 8 +b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 9 +b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 : +#31 +#32 +#33 +#34 diff --git a/test_regress/t/t_trace_litendian_fst_sc.pl b/test_regress/t/t_trace_litendian_fst_sc.pl new file mode 100755 index 000000000..56754b9df --- /dev/null +++ b/test_regress/t/t_trace_litendian_fst_sc.pl @@ -0,0 +1,35 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2020 by Geza Lore. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_litendian.v"); + + # CI environment offers 2 VCPUs, 2 thread setting causes the following warning. + # %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads. + # Strangely, asking for more threads makes it go away. + compile( + verilator_flags2 => ['--sc --trace-fst --trace-params -Wno-LITENDIAN', + ($Self->{vltmt} ? '--threads 6' : '')], + ); + + execute( + check_finished => 1, + ); + + fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.out b/test_regress/t/t_trace_packed_struct_fst_sc.out new file mode 100644 index 000000000..7c9ef71f8 --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_fst_sc.out @@ -0,0 +1,73 @@ +$date + Thu Apr 1 15:33:45 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$scope module t $end +$var wire 1 ! clk $end +$var int 32 " cnt $end +$var parameter 96 # v(0) $end +$var parameter 96 $ v(1) $end +$var parameter 96 % v(2) $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 % +b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $ +b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 # +b00000000000000000000000000000000 " +0! +$end +#10 +1! +b00000000000000000000000000000001 " +#11 +#12 +#13 +#14 +#15 +0! +#16 +#17 +#18 +#19 +#20 +1! +b00000000000000000000000000000010 " +#21 +#22 +#23 +#24 +#25 +0! +#26 +#27 +#28 +#29 +#30 +1! +b00000000000000000000000000000011 " +#31 +#32 +#33 +#34 +#35 +0! +#36 +#37 +#38 +#39 +#40 +1! +#41 +#42 +#43 +#44 diff --git a/test_regress/t/t_trace_packed_struct_fst_sc.pl b/test_regress/t/t_trace_packed_struct_fst_sc.pl new file mode 100755 index 000000000..f5acc5403 --- /dev/null +++ b/test_regress/t/t_trace_packed_struct_fst_sc.pl @@ -0,0 +1,31 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_packed_struct.v"); + + compile( + v_flags2 => ["--sc --trace-fst"] + ); + + execute( + check_finished => 1, + ); + + fst_identical($Self->trace_filename, $Self->{golden_filename}); +} + +ok(1); +1; diff --git a/test_regress/t/t_trace_primitive_fst_sc.pl b/test_regress/t/t_trace_primitive_fst_sc.pl new file mode 100755 index 000000000..b9a8fe2bb --- /dev/null +++ b/test_regress/t/t_trace_primitive_fst_sc.pl @@ -0,0 +1,28 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_primitive.v"); + + compile( + v_flags2 => ["--sc --trace-fst"], + ); + + execute( + check_finished => 1, + ); +} +ok(1); +1; diff --git a/test_regress/t/t_trace_string_fst_sc.pl b/test_regress/t/t_trace_string_fst_sc.pl new file mode 100755 index 000000000..b1298449b --- /dev/null +++ b/test_regress/t/t_trace_string_fst_sc.pl @@ -0,0 +1,29 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +if (!$Self->have_sc) { + skip("No SystemC installed"); +} +else { + top_filename("t/t_trace_string.v"); + + compile( + verilator_flags2 => ['--sc --trace'], + ); + + execute( + check_finished => 1, + ); +} + +ok(1); +1; From efc116323b054b68892a556528fc2abbd9185c63 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 5 Apr 2021 20:04:41 -0400 Subject: [PATCH 072/110] Commentary --- bin/verilator | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/bin/verilator b/bin/verilator index d606fad82..7b51a3d18 100755 --- a/bin/verilator +++ b/bin/verilator @@ -4507,6 +4507,11 @@ likely all of them are oscillating. It may also be that e.g. "a" may be oscillating, then "a" feeds signal "c" which then is also reported as oscillating. +One way DIDNOTCONVERGE may occur is flops are built out of gate primitives. +error. Verilator does not support building flops or latches out of gate +primitives, and any such code must change to use behavioral constructs +(e.g. always_ff and always_latch). + Finally, rare, more difficult cases can be debugged like a "C" program; either enter GDB and use its tracing facilities, or edit the generated C++ code to add appropriate prints to see what is going on. @@ -5012,6 +5017,13 @@ being generated from an always statement that consumed high bits of the same bus processed by another series of always blocks. The fix is the same; split it into two separate signals generated from each block. +Occasionally UNOPTFLAT may be indicated when there is a true circulation. +e.g. if trying to implement a flop or latch using individual gate +primitives. If UNOPTFLAT is suppressed the code may get a DIDNOTCONVERGE +error. Verilator does not support building flops or latches out of gate +primitives, and any such code must change to use behavioral constructs +(e.g. always_ff and always_latch). + Another way to resolve this warning is to add a C metacomment described above. This will cause the variable to be split internally, potentially resolving the conflict. If you run with --report-unoptflat From cb95a7294f647aa16f4d8fa5989fe4fadf6f0f1d Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Mon, 5 Apr 2021 20:05:04 -0400 Subject: [PATCH 073/110] Fix backtrace on bisonpre error --- src/bisonpre | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/bisonpre b/src/bisonpre index 7407f024f..3038f2a06 100755 --- a/src/bisonpre +++ b/src/bisonpre @@ -172,8 +172,8 @@ def warning_check(filename): if re.search(r'(conflicts|warning:|^useless)', line, flags=re.IGNORECASE): - sys.exit("%Error: " + filename + ":" + linenum + ": " + line + - "\n") + sys.exit("%Error: " + filename + ":" + str(linenum) + ": " + + line + "\n") ###################################################################### From 7242ceb998e20b35feee4396e6df3adfba6cedd5 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 6 Apr 2021 18:07:24 -0400 Subject: [PATCH 074/110] Remove old TODO --- Makefile.in | 1 - docs/TODO | 111 ---------------------------------------------------- 2 files changed, 112 deletions(-) delete mode 100644 docs/TODO diff --git a/Makefile.in b/Makefile.in index d44b92cba..1bc4b05d7 100644 --- a/Makefile.in +++ b/Makefile.in @@ -137,7 +137,6 @@ DISTFILES_INC = $(INFOS) .gitignore \ docs/CONTRIBUTING.rst \ docs/CONTRIBUTORS \ docs/Makefile \ - docs/TODO \ docs/_static/verilator_logo.png \ docs/install.rst \ docs/internals.rst \ diff --git a/docs/TODO b/docs/TODO deleted file mode 100644 index 341d51d42..000000000 --- a/docs/TODO +++ /dev/null @@ -1,111 +0,0 @@ -// DESCRIPTION: Verilator: List of To Do issues. -// -// Copyright 2004-2021 by Wilson Snyder. This program is free software; you can -// redistribute it and/or modify it under the terms of either the GNU -// Lesser General Public License Version 3 or the Perl Artistic License -// Version 2.0. -// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 - -* Language support: -** Fix ordering of each bit separately in a signal (mips) - assign b[3:0] = b[7:4]; assign b[7:4] = in; -** Support UDP gate primitives/ cell libraries - (have code for combos - problem is sequential udps) -** Function to eval combo logic after /*verilator public*/ functions [gwaters] -** Support generated clocks (correctness) -** Recursive functions -** Verilog configuration files -** Expression coverage (see notes) -** Better tristate support -** UVM - -* Long-term Features -** Assertions -** Tristate support - -* Testing: -** Code to make wrapper that sets signals, so can do comparison checks -** New random program generator -** Better graph viewer with search and zoom - -* Usability: -** Detect and pre-remove most UNOPTFLATs -** Better reporting of unopt problems, including what lines of code -** Report more errors (all of them?) before exiting [Eugene Weber] -** Auto-create scons config files -** Print version/etc message at runtime. (4.000?) - Include number of lines of code, percent comments, code complexity measurement - <-80chars-------------------------------------------------------------------> - Verilator 3.600 - The fast free open-sourced simulator. Copyright 2001-2013. - Verilated #### modules, #### instances, ##### sigs, - #### non-comment lines, ##### ops, ### KB model size - -* Lint: -** CDCRSTLOGIC should allow filtering with paths - "waive CDCRSTLOGIC --from a.b.sig --to a.c.sig --via OR" - -* Internal Code: -** A Visitor class that understands how to traverse data types -** V3Graph should be templated container type, taking in Vertex + Edge types -** Instead of string, have an VEncodedString/VIdString which contains __DOT__ish - things, to reduce bugs. Also add _20 trailing space to \ encoded names. - -* Runtime: -** New evalulation loop ~/src/verilator/notes/event_loop.txt (4.000?) -** Remove all private internal functions from top level wrapper header, move - to new level -** Completely standalone simulation - main() records arguments for $test$plusvars - instantiates top, - does tracing (support $dump?) - calls top->simulateForever() - exits - -* Performance: -** Latch optimizations -** Constant propagation - Extra cleaning AND: 1 & ((VARREF >> 1) | ((&VARREF >> 1) & VARREF)) - Extra shift (perhaps due to clean): if (1 & CAST (VARREF >> #)) -** Gated clock and latch conversion to flops. [JeanPaul Vanitegem] - Could propagate the AND into pos/negedges and let domaining optimize. -** Negedge reset - Switch to remove negedges that don't matter - Can't remove async resets from control flops (like in syncronizers) -** If all references to array have a constant index, blow up into separate signals-per-index -** Bit-multiply for faster bit swapping and a=b[1,3,2] random bit reorderings. -** Move _last sets and all other combo logic inside master - if() that triggers on all possible sense items -** Rewrite and combine V3Life, V3Subst - If block temp only ever set in one place to constant, propagate it - Used in t_mem for array delayed assignments - Replace variables if set later in same cfunc branch - See for example duplicate sets of _narrow in cycle 90/91 of t_select_plusloop -** Same assignment on both if branches - "if (a) { ... b=2; } else { ... b=2;}" -> "b=2; if ..." - Careful though, as b could appear in the statement or multiple times in statement - (Could just require exatly two 'b's in statement) -** Simplify XOR/AND/OR bit selection trees - Foo = A[1] ^ A[2] ^ A[3] etc are better as ^ ( A & 32'b...1110 ) -** Combine variables into wider elements - Parallel statements on different bits should become single signal - Variables that are always consumed in "parallel" can be joined -** Duplicate assignments in gate optimization - Common to have many separate posedge blocks, each with identical - reset_r <= rst_in -** If signal is used only once (not counting trace), always gate substitute - Don't merge if any combining would form circ logic (out goes back to in) -** Multiple assignments each bit can become single assign with concat - Make sure a SEL of a CONCAT can get the single bit back. -** Better ordering of a<=b, b<=c, put all refs to 'b' next to each other to optimize caching -** I-cache packing improvements (what/how?) -** Data cache organization (order of vars in class) - First have clocks, - then bools instead of uint32_t's - then based on what sense list they come from, all outputs, then all inputs - finally have any signals part of a "usually" block, or constant. -** Rather then tracking widths, have a MSB...LSB of this expression - (or better, a bitmask of bits relevant in this expression) -** Track recirculation and convert into clock-enables -** Clock enables should become new clocking domains for speed -** If floped(a) & flopped(b) and no other a&b, then instead flop(a&b). -** Sort by output bitselects so can combine more assignments (see DDP example dx_dm signal) From 8d0f7cdac82e2991a8de8a50fa7f3e03fede0739 Mon Sep 17 00:00:00 2001 From: Yutetsu TAKATSUKASA Date: Wed, 7 Apr 2021 22:26:40 +0900 Subject: [PATCH 075/110] Tests: Add a test to check if shortcut operators are properly handled. (#2869) --- test_regress/t/t_const_opt_shortcut.cpp | 23 ++++++ test_regress/t/t_const_opt_shortcut.pl | 26 +++++++ test_regress/t/t_const_opt_shortcut.v | 93 +++++++++++++++++++++++++ 3 files changed, 142 insertions(+) create mode 100644 test_regress/t/t_const_opt_shortcut.cpp create mode 100755 test_regress/t/t_const_opt_shortcut.pl create mode 100644 test_regress/t/t_const_opt_shortcut.v diff --git a/test_regress/t/t_const_opt_shortcut.cpp b/test_regress/t/t_const_opt_shortcut.cpp new file mode 100644 index 000000000..9d2e9bb33 --- /dev/null +++ b/test_regress/t/t_const_opt_shortcut.cpp @@ -0,0 +1,23 @@ +#include +extern "C" int import_func0() { + static int c = 0; + return ++c; +} + +extern "C" int import_func1() { + static int c = 0; + return ++c; +} +extern "C" int import_func2() { + static int c = 0; + return ++c; +} + +extern "C" int import_func3() { + static int c = 0; + return ++c; +} +extern "C" int import_func4() { + static int c = 0; + return ++c; +} diff --git a/test_regress/t/t_const_opt_shortcut.pl b/test_regress/t/t_const_opt_shortcut.pl new file mode 100755 index 000000000..89c1226dd --- /dev/null +++ b/test_regress/t/t_const_opt_shortcut.pl @@ -0,0 +1,26 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + v_flags2 => ["t/$Self->{name}.cpp"], + verilator_flags2=>["-Wno-UNOPTTHREADS", "--stats"], + ); + +execute( + # Shortcut is not properly implemented yet as in https://github.com/verilator/verilator/issues/487 + # When the issue is fixed, change the following two lines. + check_finished => 0, + fails => $Self->{vlt_all}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_const_opt_shortcut.v b/test_regress/t/t_const_opt_shortcut.v new file mode 100644 index 000000000..5690188f7 --- /dev/null +++ b/test_regress/t/t_const_opt_shortcut.v @@ -0,0 +1,93 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 Yutetsu TAKATSUKASA. +// SPDX-License-Identifier: CC0-1.0 + +import "DPI-C" context function int import_func0(); +import "DPI-C" context function int import_func1(); +import "DPI-C" context function int import_func2(); +import "DPI-C" context function int import_func3(); +import "DPI-C" context function int import_func4(); + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + wire [31:0] i = crc[31:0]; + wire out; + + Test test( + // Outputs + .out (out), + // Inputs + .clk (clk), + .i (i[31:0])); + + wire [63:0] result = {63'b0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + if (import_func1() != 1) $stop; // this must be the first call + if (import_func3() != 1) $stop; // this must be the first call + if (import_func4() < 95) $stop; // expected to return around 100 + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h162c58b1635b8d6e + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test(/*AUTOARG*/ + // Outputs + out, + // Inputs + clk, i + ); + + input clk; + input [31:0] i; + + output wire out; + + logic [2:0] tmp; + assign out = ^tmp; + + always_ff @(posedge clk) begin + // Note that import_func?() always returns positive integer, + // so '|(import_func?())' is always 1'b1 + tmp[0] <= |(import_func0()) || |(import_func1()); // import_fnc1 must not be called + tmp[1] <= !(|(import_func2())) && |(import_func3()); // import_fnc3 must not be called + tmp[2] <= ^(0 * import_func4()); // import_func1 has side effect, so must be executed anyway. + end + +endmodule From 6a31b192242c59ec3669767236a18bb50c7c7858 Mon Sep 17 00:00:00 2001 From: Yutetsu TAKATSUKASA Date: Wed, 7 Apr 2021 22:37:31 +0900 Subject: [PATCH 076/110] Tests: Add a test to improve code coverage of V3Const.cpp (#2878) --- test_regress/t/t_const_opt.pl | 22 +++++++ test_regress/t/t_const_opt.v | 105 ++++++++++++++++++++++++++++++++++ 2 files changed, 127 insertions(+) create mode 100755 test_regress/t/t_const_opt.pl create mode 100644 test_regress/t/t_const_opt.v diff --git a/test_regress/t/t_const_opt.pl b/test_regress/t/t_const_opt.pl new file mode 100755 index 000000000..5dbe1ff36 --- /dev/null +++ b/test_regress/t/t_const_opt.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2=>["-Wno-UNOPTTHREADS", "--stats"], + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_const_opt.v b/test_regress/t/t_const_opt.v new file mode 100644 index 000000000..b9881d967 --- /dev/null +++ b/test_regress/t/t_const_opt.v @@ -0,0 +1,105 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 Yutetsu TAKATSUKASA. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [31:0] in = crc[31:0]; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + logic o; // From test of Test.v + // End of automatics + + wire [31:0] i = crc[31:0]; + + Test test(/*AUTOINST*/ + // Outputs + .o (o), + // Inputs + .clk (clk), + .i (i[31:0])); + + // Aggregate outputs into a single result vector + wire [63:0] result = {63'b0, o}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); + $display("o %b", o); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc < 99) begin + end + else begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'hfab547b426149442 + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module Test(/*AUTOARG*/ + // Outputs + o, + // Inputs + clk, i + ); + + input clk; + input [31:0] i; + logic [31:0] d; + logic d0, d1, d2, d3, d4, d5, d6, d7; + + output logic o; + + logic [3:0] tmp; + assign o = ^tmp; + + always_ff @(posedge clk) begin + d <= i; + d0 <= i[0]; + d1 <= i[1]; + d2 <= i[2]; + d3 <= i[3]; + d4 <= i[4]; + d5 <= i[5]; + d6 <= i[6]; + d7 <= i[7]; + end + always_ff @(posedge clk) begin + // Cover more lines in V3Const.cpp + tmp[0] <= (d0 || (!d0 && d1)) ^ ((!d2 && d3) || d2); // maatchOrAndNot() + tmp[1] <= ((32'd2 ** i) & 32'h10) == 32'b0; // replacePowShift + tmp[2] <= ((d0 & d1) | (d0 & d2))^ ((d3 & d4) | (d5 & d4)); // replaceAndOr() + tmp[3] <= d0 <-> d1; // replaceLogEq() + end + +endmodule From 2b2680770bf4223b65c3746177365a2df3631783 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=80lex=20Torregrosa?= <78434679+atorregrosasmd@users.noreply.github.com> Date: Wed, 7 Apr 2021 15:55:11 +0200 Subject: [PATCH 077/110] Improve scope types in FST and VCD traces (#2805). --- include/verilated.cpp | 8 +- include/verilated.h | 2 +- include/verilated_fst_c.cpp | 29 ++++++- include/verilated_trace.h | 3 +- include/verilated_trace_defs.h | 42 ++++++++++ include/verilated_vcd_c.cpp | 19 +++-- src/V3EmitC.cpp | 2 +- src/V3TraceDecl.cpp | 30 ++++--- test_regress/driver.pl | 2 +- test_regress/t/t_interface_ref_trace.out | 40 +++++----- test_regress/t/t_interface_ref_trace_fst.out | 80 +++++++++---------- .../t/t_interface_ref_trace_fst_sc.out | 80 +++++++++---------- test_regress/t/t_trace_array_fst.out | 2 +- test_regress/t/t_trace_array_fst_sc.out | 2 +- .../t/t_trace_complex_structs_fst.out | 28 +++---- .../t/t_trace_complex_structs_fst_sc.out | 28 +++---- 16 files changed, 241 insertions(+), 156 deletions(-) create mode 100644 include/verilated_trace_defs.h diff --git a/include/verilated.cpp b/include/verilated.cpp index ce762726e..14949b740 100644 --- a/include/verilated.cpp +++ b/include/verilated.cpp @@ -2538,12 +2538,14 @@ void Verilated::debug(int level) VL_MT_SAFE { } } -const char* Verilated::catName(const char* n1, const char* n2, const char* delimiter) VL_MT_SAFE { +const char* Verilated::catName(const char* n1, const char* n2, int scopet, + const char* delimiter) VL_MT_SAFE { // Returns new'ed data // Used by symbol table creation to make module names static VL_THREAD_LOCAL char* t_strp = nullptr; static VL_THREAD_LOCAL size_t t_len = 0; - size_t newlen = std::strlen(n1) + std::strlen(n2) + std::strlen(delimiter) + 1; + size_t newlen + = std::strlen(n1) + std::strlen(n2) + std::strlen(delimiter) + (scopet > 0 ? 2 : 1); if (VL_UNLIKELY(!t_strp || newlen > t_len)) { if (t_strp) delete[] t_strp; t_strp = new char[newlen]; @@ -2551,6 +2553,8 @@ const char* Verilated::catName(const char* n1, const char* n2, const char* delim } char* dp = t_strp; for (const char* sp = n1; *sp;) *dp++ = *sp++; + // Add scope type + if (scopet) *dp++ = (char)(0x80 + scopet); for (const char* sp = delimiter; *sp;) *dp++ = *sp++; for (const char* sp = n2; *sp;) *dp++ = *sp++; *dp++ = '\0'; diff --git a/include/verilated.h b/include/verilated.h index 07a609e57..f9a15307c 100644 --- a/include/verilated.h +++ b/include/verilated.h @@ -841,7 +841,7 @@ public: public: // METHODS - INTERNAL USE ONLY (but public due to what uses it) // Internal: Create a new module name by concatenating two strings - static const char* catName(const char* n1, const char* n2, + static const char* catName(const char* n1, const char* n2, int scopet = 0, const char* delimiter = "."); // Returns static data // Internal: Throw signal assertion diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index ca7ab3495..79b209c2e 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -51,6 +51,24 @@ // clang-format on +//============================================================================= +// Check that vltscope_t matches fstScopeType +static_assert((int)FST_ST_VCD_MODULE == (int)VLT_TRACE_SCOPE_MODULE, "VLT_TRACE_SCOPE_MODULE mismatches"); +static_assert((int)FST_ST_VCD_TASK == (int)VLT_TRACE_SCOPE_TASK, "VLT_TRACE_SCOPE_TASK mismatches"); +static_assert((int)FST_ST_VCD_FUNCTION == (int)VLT_TRACE_SCOPE_FUNCTION, + "VLT_TRACE_SCOPE_FUNCTION mismatches"); +static_assert((int)FST_ST_VCD_BEGIN == (int)VLT_TRACE_SCOPE_BEGIN, "VLT_TRACE_SCOPE_BEGIN mismatches"); +static_assert((int)FST_ST_VCD_FORK == (int)VLT_TRACE_SCOPE_FORK, "VLT_TRACE_SCOPE_FORK mismatches"); +static_assert((int)FST_ST_VCD_GENERATE == (int)VLT_TRACE_SCOPE_GENERATE, + "VLT_TRACE_SCOPE_GENERATE mismatches"); +static_assert((int)FST_ST_VCD_STRUCT == (int)VLT_TRACE_SCOPE_STRUCT, "VLT_TRACE_SCOPE_STRUCT mismatches"); +static_assert((int)FST_ST_VCD_UNION == (int)VLT_TRACE_SCOPE_UNION, "VLT_TRACE_SCOPE_UNION mismatches"); +static_assert((int)FST_ST_VCD_CLASS == (int)VLT_TRACE_SCOPE_CLASS, "VLT_TRACE_SCOPE_CLASS mismatches"); +static_assert((int)FST_ST_VCD_INTERFACE == (int)VLT_TRACE_SCOPE_INTERFACE, + "VLT_TRACE_SCOPE_INTERFACE mismatches"); +static_assert((int)FST_ST_VCD_PACKAGE == (int)VLT_TRACE_SCOPE_PACKAGE, "VLT_TRACE_SCOPE_PACKAGE mismatches"); +static_assert((int)FST_ST_VCD_PROGRAM == (int)VLT_TRACE_SCOPE_PROGRAM, "VLT_TRACE_SCOPE_PROGRAM mismatches"); + //============================================================================= // Specialization of the generics for this trace format @@ -140,6 +158,7 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV std::string symbol_name(tokens.back()); tokens.pop_back(); // Remove symbol name from hierarchy tokens.insert(tokens.begin(), moduleName()); // Add current module to the hierarchy + std::string tmpModName; // Find point where current and new scope diverge auto cur_it = m_curScope.begin(); @@ -158,7 +177,15 @@ void VerilatedFst::declare(vluint32_t code, const char* name, int dtypenum, fstV // Follow the hierarchy of the new variable from the common scope point while (new_it != tokens.end()) { - fstWriterSetScope(m_fst, FST_ST_VCD_SCOPE, new_it->c_str(), nullptr); + if ((new_it->back() & 0x80)) { + tmpModName = *new_it; + tmpModName.pop_back(); + // If the scope ends with a non-ascii character, it will be 0x80 + fstScopeType + fstWriterSetScope(m_fst, (fstScopeType)(new_it->back() & 0x7f), tmpModName.c_str(), + nullptr); + } else + fstWriterSetScope(m_fst, FST_ST_VCD_SCOPE, new_it->c_str(), nullptr); + m_curScope.push_back(*new_it); new_it = tokens.erase(new_it); } diff --git a/include/verilated_trace.h b/include/verilated_trace.h index bdfed6f85..db3b71efc 100644 --- a/include/verilated_trace.h +++ b/include/verilated_trace.h @@ -25,6 +25,7 @@ // clang-format off #include "verilated.h" +#include "verilated_trace_defs.h" #include #include @@ -225,7 +226,7 @@ protected: void declCode(vluint32_t code, vluint32_t bits, bool tri); // Is this an escape? - bool isScopeEscape(char c) { return c != '\f' && (std::isspace(c) || c == m_scopeEscape); } + bool isScopeEscape(char c) { return std::isspace(c) || c == m_scopeEscape; } // Character that splits scopes. Note whitespace are ALWAYS escapes. char scopeEscape() { return m_scopeEscape; } diff --git a/include/verilated_trace_defs.h b/include/verilated_trace_defs.h new file mode 100644 index 000000000..69290c148 --- /dev/null +++ b/include/verilated_trace_defs.h @@ -0,0 +1,42 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +//============================================================================= +// +// Code available from: https://verilator.org +// +// Copyright 2001-2021 by Wilson Snyder. This program is free software; you +// can redistribute it and/or modify it under the terms of either the GNU +// Lesser General Public License Version 3 or the Perl Artistic License +// Version 2.0. +// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +// +//============================================================================= +/// +/// \file +/// \brief Verilated tracing types +/// +/// This file is not part of the Verilated public-facing API. +/// It is only for internal use by Verilated tracing routines. +/// +//============================================================================= +#ifndef VERILATOR_VERILATED_TRACE_DEFS_H_ +#define VERILATOR_VERILATED_TRACE_DEFS_H_ + +// Verilator tracing scope types: +// The values should match FST_ST_VCD_* from fstScopeType in gtkwave/fstapi.h +// verilated_fst_c.cpp contains assertions to enforce this +enum VltTraceScope { + VLT_TRACE_SCOPE_MODULE = 0, + VLT_TRACE_SCOPE_TASK = 1, + VLT_TRACE_SCOPE_FUNCTION = 2, + VLT_TRACE_SCOPE_BEGIN = 3, + VLT_TRACE_SCOPE_FORK = 4, + VLT_TRACE_SCOPE_GENERATE = 5, + VLT_TRACE_SCOPE_STRUCT = 6, + VLT_TRACE_SCOPE_UNION = 7, + VLT_TRACE_SCOPE_CLASS = 8, + VLT_TRACE_SCOPE_INTERFACE = 9, + VLT_TRACE_SCOPE_PACKAGE = 10, + VLT_TRACE_SCOPE_PROGRAM = 11 +}; + +#endif // guard diff --git a/include/verilated_vcd_c.cpp b/include/verilated_vcd_c.cpp index 796e742a1..e11ed947d 100644 --- a/include/verilated_vcd_c.cpp +++ b/include/verilated_vcd_c.cpp @@ -419,20 +419,25 @@ void VerilatedVcd::dumpHeader() { printIndent(1); // Find character after name end const char* sp = np; - while (*sp && *sp != ' ' && *sp != '\t' && *sp != '\f') sp++; + while (*sp && *sp != ' ' && *sp != '\t' && !(*sp & '\x80')) sp++; - if (*sp == '\f') { - printStr("$scope struct "); - } else { - printStr("$scope module "); - } + printStr("$scope "); + if (*sp & '\x80') { + switch (*sp & 0x7f) { + case VLT_TRACE_SCOPE_STRUCT: printStr("struct "); break; + case VLT_TRACE_SCOPE_INTERFACE: printStr("interface "); break; + case VLT_TRACE_SCOPE_UNION: printStr("union "); break; + default: printStr("module "); + } + } else + printStr("module "); for (; *np && *np != ' ' && *np != '\t'; np++) { if (*np == '[') { printStr("("); } else if (*np == ']') { printStr(")"); - } else if (*np != '\f') { + } else if (!(*np & '\x80')) { *m_writep++ = *np; } } diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index a83efb16b..48ad6de4a 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -3606,7 +3606,7 @@ class EmitCTrace final : EmitCStmts { puts(","); if (nodep->isScoped()) puts("Verilated::catName(scopep,"); putsQuoted(VIdProtect::protectWordsIf(nodep->showname(), nodep->protect())); - if (nodep->isScoped()) puts(",\" \")"); + if (nodep->isScoped()) puts(",(int)scopet,\" \")"); // Direction if (v3Global.opt.traceFormat().fst()) { puts("," + cvtToStr(enumNum)); diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index 22d0b2cfe..248fffec4 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -22,6 +22,7 @@ #include "config_build.h" #include "verilatedos.h" +#include "verilated_trace_defs.h" // For VLT_TRACE_SCOPE_* #include "V3Global.h" #include "V3TraceDecl.h" @@ -72,7 +73,7 @@ private: FileLine* const flp = m_topScopep->fileline(); AstCFunc* const funcp = new AstCFunc(flp, name, m_topScopep); string argTypes("void* userp, " + v3Global.opt.traceClassBase() + "* tracep"); - if (m_interface) argTypes += ", const char* scopep"; + if (m_interface) argTypes += ", int scopet, const char* scopep"; funcp->argTypes(argTypes); funcp->funcType(type); funcp->symProlog(true); @@ -84,8 +85,12 @@ private: } void callCFuncSub(AstCFunc* basep, AstCFunc* funcp, AstIntfRef* irp) { AstCCall* callp = new AstCCall(funcp->fileline(), funcp); - callp->argTypes("userp, tracep"); - if (irp) callp->addArgsp(irp->unlinkFrBack()); + if (irp) { + callp->argTypes("userp, tracep, VLT_TRACE_SCOPE_INTERFACE"); + callp->addArgsp(irp->unlinkFrBack()); + } else { + callp->argTypes("userp, tracep"); + } basep->addStmtsp(callp); } AstCFunc* newCFuncSub(AstCFunc* basep) { @@ -94,6 +99,9 @@ private: if (!m_interface) callCFuncSub(basep, funcp, nullptr); return funcp; } + + std::string getScopeChar(VltTraceScope sct) { return std::string(1, (char)(0x80 + sct)); } + void addTraceDecl(const VNumRange& arrayRange, int widthOverride) { // If !=0, is packed struct/array where basicp size // misreflects one element @@ -295,16 +303,12 @@ private: VL_RESTORER(m_traShowname); VL_RESTORER(m_traValuep); { - // Add @ to mark as struct - // Since it is not a valid symbol for verilog variable names, no - // collision should happen - if (v3Global.opt.traceFormat().fst()) { - m_traShowname += string(" ") + itemp->prettyName(); - } else { - m_traShowname += string("\f ") + itemp->prettyName(); - } - if (VN_IS(nodep, StructDType)) { + // Mark scope as a struct by setting the last char to 0x80 + the + // fstScopeType + m_traShowname + += getScopeChar(VLT_TRACE_SCOPE_STRUCT) + " " + itemp->prettyName(); + m_traValuep = new AstSel(nodep->fileline(), m_traValuep->cloneTree(true), itemp->lsb(), subtypep->width()); @@ -312,6 +316,8 @@ private: iterate(subtypep); VL_DO_CLEAR(m_traValuep->deleteTree(), m_traValuep = nullptr); } else { // Else union, replicate fields + m_traShowname + += getScopeChar(VLT_TRACE_SCOPE_UNION) + " " + itemp->prettyName(); iterate(subtypep); } } diff --git a/test_regress/driver.pl b/test_regress/driver.pl index aceaed76a..c33ebb2bb 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -2273,7 +2273,7 @@ sub _vcd_read { my @hier = ($data); my $lasthier; while (defined(my $line = $fh->getline)) { - if ($line =~ /\$scope (module|struct)\s+(\S+)/) { + if ($line =~ /\$scope (module|struct|interface)\s+(\S+)/) { $hier[$#hier]->{$1} ||= {}; push @hier, $hier[$#hier]->{$1}; $lasthier = $hier[$#hier]; diff --git a/test_regress/t/t_interface_ref_trace.out b/test_regress/t/t_interface_ref_trace.out index b9de5a2a5..67a6e327b 100644 --- a/test_regress/t/t_interface_ref_trace.out +++ b/test_regress/t/t_interface_ref_trace.out @@ -10,7 +10,7 @@ $timescale 1ps $end $var wire 32 # cyc [31:0] $end $scope module a $end $scope module ac1 $end - $scope module intf_for_check $end + $scope interface intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end @@ -21,7 +21,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module ac2 $end - $scope module intf_for_check $end + $scope interface intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end @@ -32,7 +32,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module ac3 $end - $scope module intf_for_check $end + $scope interface intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end @@ -43,7 +43,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module as3 $end - $scope module intf_for_struct $end + $scope interface intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end @@ -53,7 +53,7 @@ $timescale 1ps $end $upscope $end $upscope $end $upscope $end - $scope module intf_in_sub_all $end + $scope interface intf_in_sub_all $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 * value [31:0] $end @@ -62,7 +62,7 @@ $timescale 1ps $end $var wire 32 , val200 [31:0] $end $upscope $end $upscope $end - $scope module intf_one $end + $scope interface intf_one $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end @@ -71,7 +71,7 @@ $timescale 1ps $end $var wire 32 & val200 [31:0] $end $upscope $end $upscope $end - $scope module intf_two $end + $scope interface intf_two $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end @@ -83,7 +83,7 @@ $timescale 1ps $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end $scope module ac1 $end - $scope module intf_for_check $end + $scope interface intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end @@ -94,7 +94,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module ac2 $end - $scope module intf_for_check $end + $scope interface intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end @@ -105,7 +105,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module ac3 $end - $scope module intf_for_check $end + $scope interface intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end @@ -116,7 +116,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module as3 $end - $scope module intf_for_struct $end + $scope interface intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end @@ -126,7 +126,7 @@ $timescale 1ps $end $upscope $end $upscope $end $upscope $end - $scope module intf_in_sub_all $end + $scope interface intf_in_sub_all $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 - value [31:0] $end @@ -135,7 +135,7 @@ $timescale 1ps $end $var wire 32 / val200 [31:0] $end $upscope $end $upscope $end - $scope module intf_one $end + $scope interface intf_one $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end @@ -144,7 +144,7 @@ $timescale 1ps $end $var wire 32 ) val200 [31:0] $end $upscope $end $upscope $end - $scope module intf_two $end + $scope interface intf_two $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end @@ -155,7 +155,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module c1 $end - $scope module intf_for_check $end + $scope interface intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end @@ -166,7 +166,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module c2 $end - $scope module intf_for_check $end + $scope interface intf_for_check $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end @@ -176,7 +176,7 @@ $timescale 1ps $end $upscope $end $upscope $end $upscope $end - $scope module intf_1 $end + $scope interface intf_1 $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end @@ -185,7 +185,7 @@ $timescale 1ps $end $var wire 32 & val200 [31:0] $end $upscope $end $upscope $end - $scope module intf_2 $end + $scope interface intf_2 $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end @@ -195,7 +195,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module s1 $end - $scope module intf_for_struct $end + $scope interface intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 $ value [31:0] $end @@ -206,7 +206,7 @@ $timescale 1ps $end $upscope $end $upscope $end $scope module s2 $end - $scope module intf_for_struct $end + $scope interface intf_for_struct $end $var wire 1 0 clk $end $var wire 32 # cyc [31:0] $end $var wire 32 ' value [31:0] $end diff --git a/test_regress/t/t_interface_ref_trace_fst.out b/test_regress/t/t_interface_ref_trace_fst.out index 7ccec6303..ffe8c0410 100644 --- a/test_regress/t/t_interface_ref_trace_fst.out +++ b/test_regress/t/t_interface_ref_trace_fst.out @@ -13,53 +13,53 @@ $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end -$scope module intf_1 $end +$scope interface intf_1 $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $scope module s1 $end -$scope module intf_for_struct $end +$scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $scope module c1 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $scope module a $end -$scope module intf_one $end +$scope interface intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $scope module ac1 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end @@ -67,74 +67,74 @@ $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end -$scope module intf_two $end +$scope interface intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $scope module ac2 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $upscope $end -$scope module intf_2 $end +$scope interface intf_2 $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $scope module s2 $end -$scope module intf_for_struct $end +$scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $upscope $end $scope module c2 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $upscope $end $scope module a $end -$scope module intf_two $end +$scope interface intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $scope module ac2 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end @@ -142,21 +142,21 @@ $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end -$scope module intf_one $end +$scope interface intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $scope module ac1 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end @@ -164,32 +164,32 @@ $upscope $end $upscope $end $upscope $end $scope module a $end -$scope module intf_in_sub_all $end +$scope interface intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 ) value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 * val100 $end $var logic 32 + val200 $end $upscope $end $upscope $end $scope module as3 $end -$scope module intf_for_struct $end +$scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 ) value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 * val100 $end $var logic 32 + val200 $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 ) value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 * val100 $end $var logic 32 + val200 $end $upscope $end @@ -197,32 +197,32 @@ $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end -$scope module intf_in_sub_all $end +$scope interface intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 , value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 - val100 $end $var logic 32 . val200 $end $upscope $end $upscope $end $scope module as3 $end -$scope module intf_for_struct $end +$scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 , value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 - val100 $end $var logic 32 . val200 $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 , value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 - val100 $end $var logic 32 . val200 $end $upscope $end diff --git a/test_regress/t/t_interface_ref_trace_fst_sc.out b/test_regress/t/t_interface_ref_trace_fst_sc.out index 48b2e47ab..753dc7847 100644 --- a/test_regress/t/t_interface_ref_trace_fst_sc.out +++ b/test_regress/t/t_interface_ref_trace_fst_sc.out @@ -12,53 +12,53 @@ $scope module top $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end -$scope module intf_1 $end +$scope interface intf_1 $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $scope module s1 $end -$scope module intf_for_struct $end +$scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $scope module c1 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $scope module a $end -$scope module intf_one $end +$scope interface intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $scope module ac1 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end @@ -66,74 +66,74 @@ $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end -$scope module intf_two $end +$scope interface intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $scope module ac2 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 # value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 $ val100 $end $var logic 32 % val200 $end $upscope $end $upscope $end $upscope $end $upscope $end -$scope module intf_2 $end +$scope interface intf_2 $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $scope module s2 $end -$scope module intf_for_struct $end +$scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $upscope $end $scope module c2 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $upscope $end $scope module a $end -$scope module intf_two $end +$scope interface intf_two $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $scope module ac2 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end @@ -141,21 +141,21 @@ $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end -$scope module intf_one $end +$scope interface intf_one $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end $upscope $end $scope module ac1 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 & value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 ' val100 $end $var logic 32 ( val200 $end $upscope $end @@ -163,32 +163,32 @@ $upscope $end $upscope $end $upscope $end $scope module a $end -$scope module intf_in_sub_all $end +$scope interface intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 ) value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 * val100 $end $var logic 32 + val200 $end $upscope $end $upscope $end $scope module as3 $end -$scope module intf_for_struct $end +$scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 ) value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 * val100 $end $var logic 32 + val200 $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 ) value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 * val100 $end $var logic 32 + val200 $end $upscope $end @@ -196,32 +196,32 @@ $upscope $end $upscope $end $upscope $end $scope module abcdefghijklmnopqrstuvwxyz $end -$scope module intf_in_sub_all $end +$scope interface intf_in_sub_all $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 , value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 - val100 $end $var logic 32 . val200 $end $upscope $end $upscope $end $scope module as3 $end -$scope module intf_for_struct $end +$scope interface intf_for_struct $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 , value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 - val100 $end $var logic 32 . val200 $end $upscope $end $upscope $end $upscope $end $scope module ac3 $end -$scope module intf_for_check $end +$scope interface intf_for_check $end $var wire 1 ! clk $end $var wire 32 " cyc $end $var integer 32 , value $end -$scope module the_struct $end +$scope struct the_struct $end $var logic 32 - val100 $end $var logic 32 . val200 $end $upscope $end diff --git a/test_regress/t/t_trace_array_fst.out b/test_regress/t/t_trace_array_fst.out index 52b55a782..9c1c6afd6 100644 --- a/test_regress/t/t_trace_array_fst.out +++ b/test_regress/t/t_trace_array_fst.out @@ -13,7 +13,7 @@ $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end -$scope module biggie $end +$scope struct biggie $end $var logic 1048577 # d $end $upscope $end $upscope $end diff --git a/test_regress/t/t_trace_array_fst_sc.out b/test_regress/t/t_trace_array_fst_sc.out index 7a218ecd0..51dbb33a9 100644 --- a/test_regress/t/t_trace_array_fst_sc.out +++ b/test_regress/t/t_trace_array_fst_sc.out @@ -12,7 +12,7 @@ $scope module top $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end -$scope module biggie $end +$scope struct biggie $end $var logic 1048577 # d $end $upscope $end $upscope $end diff --git a/test_regress/t/t_trace_complex_structs_fst.out b/test_regress/t/t_trace_complex_structs_fst.out index 3e0bcd6f8..48f9b2fed 100644 --- a/test_regress/t/t_trace_complex_structs_fst.out +++ b/test_regress/t/t_trace_complex_structs_fst.out @@ -13,26 +13,26 @@ $var wire 1 ! clk $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end -$scope module v_strp $end +$scope struct v_strp $end $var logic 1 # b1 $end $var logic 1 $ b0 $end $upscope $end -$scope module v_strp_strp $end -$scope module x1 $end +$scope struct v_strp_strp $end +$scope struct x1 $end $var logic 1 % b1 $end $var logic 1 & b0 $end $upscope $end -$scope module x0 $end +$scope struct x0 $end $var logic 1 ' b1 $end $var logic 1 ( b0 $end $upscope $end $upscope $end -$scope module v_unip_strp $end -$scope module x1 $end +$scope union v_unip_strp $end +$scope struct x1 $end $var logic 1 ) b1 $end $var logic 1 * b0 $end $upscope $end -$scope module x0 $end +$scope struct x0 $end $var logic 1 ) b1 $end $var logic 1 * b0 $end $upscope $end @@ -40,11 +40,11 @@ $upscope $end $var logic 2 + v_arrp $end $var logic 2 , v_arrp_arrp(3) $end $var logic 2 - v_arrp_arrp(4) $end -$scope module v_arrp_strp(3) $end +$scope struct v_arrp_strp(3) $end $var logic 1 . b1 $end $var logic 1 / b0 $end $upscope $end -$scope module v_arrp_strp(4) $end +$scope struct v_arrp_strp(4) $end $var logic 1 0 b1 $end $var logic 1 1 b0 $end $upscope $end @@ -56,21 +56,21 @@ $var logic 1 6 v_arru_arru(4)(1) $end $var logic 1 7 v_arru_arru(4)(2) $end $var logic 2 8 v_arru_arrp(3) $end $var logic 2 9 v_arru_arrp(4) $end -$scope module v_arru_strp(3) $end +$scope struct v_arru_strp(3) $end $var logic 1 : b1 $end $var logic 1 ; b0 $end $upscope $end -$scope module v_arru_strp(4) $end +$scope struct v_arru_strp(4) $end $var logic 1 < b1 $end $var logic 1 = b0 $end $upscope $end $var real 64 > v_real $end $var real 64 ? v_arr_real(0) $end $var real 64 @ v_arr_real(1) $end -$scope module v_str32x2(0) $end +$scope struct v_str32x2(0) $end $var logic 32 A data $end $upscope $end -$scope module v_str32x2(1) $end +$scope struct v_str32x2(1) $end $var logic 32 B data $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $upscope $end @@ -81,7 +81,7 @@ $var logic 32 D v_enumed2 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 E v_enumb $end -$scope module v_enumb2_str $end +$scope struct v_enumb2_str $end $attrbegin misc 07 "" 2 $end $var logic 3 F a $end $attrbegin misc 07 "" 2 $end diff --git a/test_regress/t/t_trace_complex_structs_fst_sc.out b/test_regress/t/t_trace_complex_structs_fst_sc.out index ac1a62444..d666dae4d 100644 --- a/test_regress/t/t_trace_complex_structs_fst_sc.out +++ b/test_regress/t/t_trace_complex_structs_fst_sc.out @@ -12,26 +12,26 @@ $scope module top $end $scope module t $end $var wire 1 ! clk $end $var integer 32 " cyc $end -$scope module v_strp $end +$scope struct v_strp $end $var logic 1 # b1 $end $var logic 1 $ b0 $end $upscope $end -$scope module v_strp_strp $end -$scope module x1 $end +$scope struct v_strp_strp $end +$scope struct x1 $end $var logic 1 % b1 $end $var logic 1 & b0 $end $upscope $end -$scope module x0 $end +$scope struct x0 $end $var logic 1 ' b1 $end $var logic 1 ( b0 $end $upscope $end $upscope $end -$scope module v_unip_strp $end -$scope module x1 $end +$scope union v_unip_strp $end +$scope struct x1 $end $var logic 1 ) b1 $end $var logic 1 * b0 $end $upscope $end -$scope module x0 $end +$scope struct x0 $end $var logic 1 ) b1 $end $var logic 1 * b0 $end $upscope $end @@ -39,11 +39,11 @@ $upscope $end $var logic 2 + v_arrp $end $var logic 2 , v_arrp_arrp(3) $end $var logic 2 - v_arrp_arrp(4) $end -$scope module v_arrp_strp(3) $end +$scope struct v_arrp_strp(3) $end $var logic 1 . b1 $end $var logic 1 / b0 $end $upscope $end -$scope module v_arrp_strp(4) $end +$scope struct v_arrp_strp(4) $end $var logic 1 0 b1 $end $var logic 1 1 b0 $end $upscope $end @@ -55,21 +55,21 @@ $var logic 1 6 v_arru_arru(4)(1) $end $var logic 1 7 v_arru_arru(4)(2) $end $var logic 2 8 v_arru_arrp(3) $end $var logic 2 9 v_arru_arrp(4) $end -$scope module v_arru_strp(3) $end +$scope struct v_arru_strp(3) $end $var logic 1 : b1 $end $var logic 1 ; b0 $end $upscope $end -$scope module v_arru_strp(4) $end +$scope struct v_arru_strp(4) $end $var logic 1 < b1 $end $var logic 1 = b0 $end $upscope $end $var real 64 > v_real $end $var real 64 ? v_arr_real(0) $end $var real 64 @ v_arr_real(1) $end -$scope module v_str32x2(0) $end +$scope struct v_str32x2(0) $end $var logic 32 A data $end $upscope $end -$scope module v_str32x2(1) $end +$scope struct v_str32x2(1) $end $var logic 32 B data $end $attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end $upscope $end @@ -80,7 +80,7 @@ $var logic 32 D v_enumed2 $end $attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end $attrbegin misc 07 "" 2 $end $var logic 3 E v_enumb $end -$scope module v_enumb2_str $end +$scope struct v_enumb2_str $end $attrbegin misc 07 "" 2 $end $var logic 3 F a $end $attrbegin misc 07 "" 2 $end From 52fc1342724adcdba398bd428075a1e1cd528b9a Mon Sep 17 00:00:00 2001 From: github action Date: Wed, 7 Apr 2021 13:56:12 +0000 Subject: [PATCH 078/110] Apply clang-format --- include/verilated_fst_c.cpp | 27 ++++++++++++++++++--------- src/V3TraceDecl.cpp | 4 ++-- 2 files changed, 20 insertions(+), 11 deletions(-) diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index 79b209c2e..1120e0529 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -53,21 +53,30 @@ //============================================================================= // Check that vltscope_t matches fstScopeType -static_assert((int)FST_ST_VCD_MODULE == (int)VLT_TRACE_SCOPE_MODULE, "VLT_TRACE_SCOPE_MODULE mismatches"); -static_assert((int)FST_ST_VCD_TASK == (int)VLT_TRACE_SCOPE_TASK, "VLT_TRACE_SCOPE_TASK mismatches"); +static_assert((int)FST_ST_VCD_MODULE == (int)VLT_TRACE_SCOPE_MODULE, + "VLT_TRACE_SCOPE_MODULE mismatches"); +static_assert((int)FST_ST_VCD_TASK == (int)VLT_TRACE_SCOPE_TASK, + "VLT_TRACE_SCOPE_TASK mismatches"); static_assert((int)FST_ST_VCD_FUNCTION == (int)VLT_TRACE_SCOPE_FUNCTION, "VLT_TRACE_SCOPE_FUNCTION mismatches"); -static_assert((int)FST_ST_VCD_BEGIN == (int)VLT_TRACE_SCOPE_BEGIN, "VLT_TRACE_SCOPE_BEGIN mismatches"); -static_assert((int)FST_ST_VCD_FORK == (int)VLT_TRACE_SCOPE_FORK, "VLT_TRACE_SCOPE_FORK mismatches"); +static_assert((int)FST_ST_VCD_BEGIN == (int)VLT_TRACE_SCOPE_BEGIN, + "VLT_TRACE_SCOPE_BEGIN mismatches"); +static_assert((int)FST_ST_VCD_FORK == (int)VLT_TRACE_SCOPE_FORK, + "VLT_TRACE_SCOPE_FORK mismatches"); static_assert((int)FST_ST_VCD_GENERATE == (int)VLT_TRACE_SCOPE_GENERATE, "VLT_TRACE_SCOPE_GENERATE mismatches"); -static_assert((int)FST_ST_VCD_STRUCT == (int)VLT_TRACE_SCOPE_STRUCT, "VLT_TRACE_SCOPE_STRUCT mismatches"); -static_assert((int)FST_ST_VCD_UNION == (int)VLT_TRACE_SCOPE_UNION, "VLT_TRACE_SCOPE_UNION mismatches"); -static_assert((int)FST_ST_VCD_CLASS == (int)VLT_TRACE_SCOPE_CLASS, "VLT_TRACE_SCOPE_CLASS mismatches"); +static_assert((int)FST_ST_VCD_STRUCT == (int)VLT_TRACE_SCOPE_STRUCT, + "VLT_TRACE_SCOPE_STRUCT mismatches"); +static_assert((int)FST_ST_VCD_UNION == (int)VLT_TRACE_SCOPE_UNION, + "VLT_TRACE_SCOPE_UNION mismatches"); +static_assert((int)FST_ST_VCD_CLASS == (int)VLT_TRACE_SCOPE_CLASS, + "VLT_TRACE_SCOPE_CLASS mismatches"); static_assert((int)FST_ST_VCD_INTERFACE == (int)VLT_TRACE_SCOPE_INTERFACE, "VLT_TRACE_SCOPE_INTERFACE mismatches"); -static_assert((int)FST_ST_VCD_PACKAGE == (int)VLT_TRACE_SCOPE_PACKAGE, "VLT_TRACE_SCOPE_PACKAGE mismatches"); -static_assert((int)FST_ST_VCD_PROGRAM == (int)VLT_TRACE_SCOPE_PROGRAM, "VLT_TRACE_SCOPE_PROGRAM mismatches"); +static_assert((int)FST_ST_VCD_PACKAGE == (int)VLT_TRACE_SCOPE_PACKAGE, + "VLT_TRACE_SCOPE_PACKAGE mismatches"); +static_assert((int)FST_ST_VCD_PROGRAM == (int)VLT_TRACE_SCOPE_PROGRAM, + "VLT_TRACE_SCOPE_PROGRAM mismatches"); //============================================================================= // Specialization of the generics for this trace format diff --git a/src/V3TraceDecl.cpp b/src/V3TraceDecl.cpp index 248fffec4..ac7f9a7f0 100644 --- a/src/V3TraceDecl.cpp +++ b/src/V3TraceDecl.cpp @@ -306,8 +306,8 @@ private: if (VN_IS(nodep, StructDType)) { // Mark scope as a struct by setting the last char to 0x80 + the // fstScopeType - m_traShowname - += getScopeChar(VLT_TRACE_SCOPE_STRUCT) + " " + itemp->prettyName(); + m_traShowname += getScopeChar(VLT_TRACE_SCOPE_STRUCT) + " " + + itemp->prettyName(); m_traValuep = new AstSel(nodep->fileline(), m_traValuep->cloneTree(true), From e2c11cceb891edd6a7f25cdf973810122019e8ae Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Thu, 8 Apr 2021 19:35:03 -0400 Subject: [PATCH 079/110] Fix select of with index variable (#2880). --- Changes | 1 + src/V3LinkResolve.cpp | 3 +++ test_regress/t/t_queue_method.v | 2 ++ 3 files changed, 6 insertions(+) diff --git a/Changes b/Changes index 8952ba3e8..04cfda00b 100644 --- a/Changes +++ b/Changes @@ -29,6 +29,7 @@ Verilator 4.201 devel * Fix --public-flat-rw / DPI issue (#2858). [Todd Strader] * Fix interface localparam access (#2859). [Todd Strader] * Fix Cygwin example compile issues (#2856). [Mark Shaw] +* Fix select of with index variable (#2880). [Alexander Grobman] Verilator 4.200 2021-03-12 diff --git a/src/V3LinkResolve.cpp b/src/V3LinkResolve.cpp index 76339ebc2..09f71d11a 100644 --- a/src/V3LinkResolve.cpp +++ b/src/V3LinkResolve.cpp @@ -227,6 +227,9 @@ private: = VN_CAST(basefromp, UnlinkedRef)) { // Maybe unlinked - so need to clone nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::VAR_BASE, uvxrp->cloneTree(false))); + } else if (auto* fromp = VN_CAST(basefromp, LambdaArgRef)) { + nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::VAR_BASE, + fromp->cloneTree(false))); } else if (AstMemberSel* fromp = VN_CAST(basefromp, MemberSel)) { nodep->attrp(new AstAttrOf(nodep->fileline(), AstAttrType::MEMBER_BASE, fromp->cloneTree(false))); diff --git a/test_regress/t/t_queue_method.v b/test_regress/t/t_queue_method.v index 3e8dfbf1a..0446f406e 100644 --- a/test_regress/t/t_queue_method.v +++ b/test_regress/t/t_queue_method.v @@ -62,6 +62,8 @@ module t (/*AUTOARG*/); // TODO add a lint check that with clause is provided qv = q.find with (item == 2); v = $sformatf("%p", qv); `checks(v, "'{'h2, 'h2} "); + qv = q.find with (item[0] == 1); + v = $sformatf("%p", qv); `checks(v, "'{'h1, 'h3} "); qv = q.find_first with (item == 2); v = $sformatf("%p", qv); `checks(v, "'{'h2} "); qv = q.find_last with (item == 2); From 23c243bb8293daa8e84ea6667fa9145d62f01827 Mon Sep 17 00:00:00 2001 From: Udi Finkelstein Date: Fri, 9 Apr 2021 17:39:46 +0300 Subject: [PATCH 080/110] Add support for null ports (#2875) --- bin/verilator | 11 +++ src/V3Error.h | 3 +- src/verilog.y | 26 ++++++- test_regress/t/t_lint_nullport.out | 107 +++++++++++++++++++++++++++++ test_regress/t/t_lint_nullport.pl | 19 +++++ test_regress/t/t_lint_nullport.v | 80 +++++++++++++++++++++ 6 files changed, 243 insertions(+), 3 deletions(-) create mode 100644 test_regress/t/t_lint_nullport.out create mode 100755 test_regress/t/t_lint_nullport.pl create mode 100644 test_regress/t/t_lint_nullport.v diff --git a/bin/verilator b/bin/verilator index 7b51a3d18..75d4bc395 100755 --- a/bin/verilator +++ b/bin/verilator @@ -4729,6 +4729,17 @@ using a regular always may be more appropriate. Ignoring this warning will only suppress the lint check, it will simulate correctly. +=item NULLPORT + +Warns that a null port was detected in the module definition port list. Null +ports are empty placeholders, i.e. either one ore more commas at the beginning +or the end of a module port list, or two or more consecutive commas in the +middle of a module port list. A null port cannot be accessed within the module, +but when instantiating the module by port order, it is treated like a regular +port and any wire connected to it is left unconnected. +This is considered a warning because this feature is rarely used, and is mostly +the result of a typing error such as a dangling comma at the end of a port list. + =item PINCONNECTEMPTY Warns that an instance has a pin which is connected to .pin_name(), diff --git a/src/V3Error.h b/src/V3Error.h index 1eec450e0..a312fe6e9 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -101,6 +101,7 @@ public: MULTIDRIVEN, // Driven from multiple blocks MULTITOP, // Multiple top level modules NOLATCH, // No latch detected in always_latch block + NULLPORT, // Null port detected in module definition PINCONNECTEMPTY,// Cell pin connected by name with empty reference PINMISSING, // Cell pin not specified PINNOCONNECT, // Cell pin not connected @@ -167,7 +168,7 @@ public: "IMPERFECTSCH", "IMPLICIT", "IMPORTSTAR", "IMPURE", "INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE", "LATCH", "LITENDIAN", "MODDUP", - "MULTIDRIVEN", "MULTITOP","NOLATCH", "PINCONNECTEMPTY", + "MULTIDRIVEN", "MULTITOP","NOLATCH", "NULLPORT", "PINCONNECTEMPTY", "PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", "PROCASSWIRE", "RANDC", "REALCVT", "REDEFMACRO", "SELRANGE", "SHORTREAL", "SPLITVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET", diff --git a/src/verilog.y b/src/verilog.y index e887c3a3d..d5bb07096 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -1284,9 +1284,31 @@ portsStarE: // IEEE: .* + list_of_ports + list_of_port_declarations + em | '(' {VARRESET_LIST(PORT);} list_of_ports ')' { $$ = $3; VARRESET_NONLIST(UNKNOWN); } ; +list_of_portsE: // IEEE: list_of_ports + list_of_port_declarations + portAndTagE { $$ = $1; } + | list_of_portsE ',' portAndTagE { $$ = $1->addNextNull($3); } + ; + list_of_ports: // IEEE: list_of_ports + list_of_port_declarations - portAndTag { $$ = $1; } - | list_of_ports ',' portAndTag { $$ = $1->addNextNull($3); } + portAndTag { $$ = $1; } + | list_of_portsE ',' portAndTagE { $$ = $1->addNextNull($3); } + ; + +portAndTagE: + /* empty */ + { int p = PINNUMINC(); + const string name = "__pinNumber" + cvtToStr(p); + $$ = new AstPort{CRELINE(), p, name}; + AstVar* varp = new AstVar{CRELINE(), AstVarType::PORT, name, VFlagChildDType{}, + new AstBasicDType{CRELINE(), LOGIC_IMPLICIT}}; + varp->declDirection(VDirection::INPUT); + varp->direction(VDirection::INPUT); + varp->ansi(false); + varp->declTyped(true); + varp->trace(false); + $$ = $$->addNext(varp); + $$->v3warn(NULLPORT, "Null port on module (perhaps extraneous comma)"); } + | portAndTag { $$ = $1; } ; portAndTag: diff --git a/test_regress/t/t_lint_nullport.out b/test_regress/t/t_lint_nullport.out new file mode 100644 index 000000000..f35a775cd --- /dev/null +++ b/test_regress/t/t_lint_nullport.out @@ -0,0 +1,107 @@ +%Warning-NULLPORT: t/t_lint_nullport.v:23:13: Null port on module (perhaps extraneous comma) + 23 | module t5(a,); + | ^ + ... Use "/* verilator lint_off NULLPORT */" and lint_on around source to disable this message. +%Warning-NULLPORT: t/t_lint_nullport.v:27:13: Null port on module (perhaps extraneous comma) + 27 | module t6(a,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:27:14: Null port on module (perhaps extraneous comma) + 27 | module t6(a,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:31:15: Null port on module (perhaps extraneous comma) + 31 | module t7(a,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:35:15: Null port on module (perhaps extraneous comma) + 35 | module t8(a,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:35:16: Null port on module (perhaps extraneous comma) + 35 | module t8(a,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:39:13: Null port on module (perhaps extraneous comma) + 39 | module t9(a,,b); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:43:14: Null port on module (perhaps extraneous comma) + 43 | module t10(a,,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:43:17: Null port on module (perhaps extraneous comma) + 43 | module t10(a,,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:47:14: Null port on module (perhaps extraneous comma) + 47 | module t11(a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:47:17: Null port on module (perhaps extraneous comma) + 47 | module t11(a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:47:18: Null port on module (perhaps extraneous comma) + 47 | module t11(a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:51:12: Null port on module (perhaps extraneous comma) + 51 | module t12(,a,,b); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:51:15: Null port on module (perhaps extraneous comma) + 51 | module t12(,a,,b); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:55:12: Null port on module (perhaps extraneous comma) + 55 | module t13(,a,,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:55:15: Null port on module (perhaps extraneous comma) + 55 | module t13(,a,,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:55:18: Null port on module (perhaps extraneous comma) + 55 | module t13(,a,,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:59:12: Null port on module (perhaps extraneous comma) + 59 | module t14(,a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:59:15: Null port on module (perhaps extraneous comma) + 59 | module t14(,a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:59:18: Null port on module (perhaps extraneous comma) + 59 | module t14(,a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:59:19: Null port on module (perhaps extraneous comma) + 59 | module t14(,a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:63:12: Null port on module (perhaps extraneous comma) + 63 | module t15(,,a,,b); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:63:13: Null port on module (perhaps extraneous comma) + 63 | module t15(,,a,,b); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:63:16: Null port on module (perhaps extraneous comma) + 63 | module t15(,,a,,b); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:67:12: Null port on module (perhaps extraneous comma) + 67 | module t16(,,a,,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:67:13: Null port on module (perhaps extraneous comma) + 67 | module t16(,,a,,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:67:16: Null port on module (perhaps extraneous comma) + 67 | module t16(,,a,,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:67:19: Null port on module (perhaps extraneous comma) + 67 | module t16(,,a,,b,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:71:12: Null port on module (perhaps extraneous comma) + 71 | module t17(,,a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:71:13: Null port on module (perhaps extraneous comma) + 71 | module t17(,,a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:71:16: Null port on module (perhaps extraneous comma) + 71 | module t17(,,a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:71:19: Null port on module (perhaps extraneous comma) + 71 | module t17(,,a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:71:20: Null port on module (perhaps extraneous comma) + 71 | module t17(,,a,,b,,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:75:12: Null port on module (perhaps extraneous comma) + 75 | module t18(,); + | ^ +%Warning-NULLPORT: t/t_lint_nullport.v:75:13: Null port on module (perhaps extraneous comma) + 75 | module t18(,); + | ^ +%Error: Exiting due to diff --git a/test_regress/t/t_lint_nullport.pl b/test_regress/t/t_lint_nullport.pl new file mode 100755 index 000000000..4f29861db --- /dev/null +++ b/test_regress/t/t_lint_nullport.pl @@ -0,0 +1,19 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_lint_nullport.v b/test_regress/t/t_lint_nullport.v new file mode 100644 index 000000000..5b42dc176 --- /dev/null +++ b/test_regress/t/t_lint_nullport.v @@ -0,0 +1,80 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Udi Finkelstein. +// SPDX-License-Identifier: CC0-1.0 + +/* verilator lint_off MULTITOP */ +// First, test we haven't broken normal ports +module t1(); +endmodule + +module t2; +endmodule + +module t3(a); +input a; +endmodule + +module t4(a, b); +input a, b; +endmodule + +module t5(a,); +input a; +endmodule + +module t6(a,,); +input a; +endmodule + +module t7(a,b,); +input a, b; +endmodule + +module t8(a,b,,); +input a, b; +endmodule + +module t9(a,,b); +input a, b; +endmodule + +module t10(a,,b,); +input a, b; +endmodule + +module t11(a,,b,,); +input a, b; +endmodule + +module t12(,a,,b); +input a, b; +endmodule + +module t13(,a,,b,); +input a, b; +endmodule + +module t14(,a,,b,,); +input a, b; +endmodule + +module t15(,,a,,b); +input a, b; +endmodule + +module t16(,,a,,b,); +input a, b; +endmodule + +module t17(,,a,,b,,); +input a, b; +endmodule + +module t18(,); +endmodule + +/* verilator lint_off NULLPORT */ +module t19(,,); +endmodule From 0d6099b2b76253a1352083d1a8e72fa6faf440a1 Mon Sep 17 00:00:00 2001 From: HyungKi Jeong <68764729+testdrive-profiling-master@users.noreply.github.com> Date: Fri, 9 Apr 2021 23:40:41 +0900 Subject: [PATCH 081/110] Fix MinGW not supportting 'localtime_r'. (#2882) --- include/verilatedos.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/verilatedos.h b/include/verilatedos.h index 8a890af8f..21cc1447f 100644 --- a/include/verilatedos.h +++ b/include/verilatedos.h @@ -500,7 +500,9 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type # define VL_STRCASECMP strcasecmp #endif -#ifdef _MSC_VER +#ifdef __MINGW32__ +# define VL_LOCALTIME_R(timep, tmp) localtime_s((tmp), (timep)) +#elif defined(_MSC_VER) # define VL_LOCALTIME_R(timep, tmp) localtime_c((tmp), (timep)) #else # define VL_LOCALTIME_R(timep, tmp) localtime_r((timep), (tmp)) From adce7ecf4ba48f57b320f442dc7de34fa79bb6b4 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 11 Apr 2021 18:55:06 -0400 Subject: [PATCH 082/110] Documentation has been rewritten into a book format. --- Changes | 22 +- MANIFEST.SKIP | 1 + Makefile.in | 49 +- bin/verilator | 5411 +--------------------- bin/verilator_coverage | 137 +- bin/verilator_difftree | 2 + bin/verilator_gantt | 90 +- bin/verilator_profcfunc | 17 +- ci/docker/buildenv/README.rst | 3 +- ci/docker/run/README.rst | 3 +- docs/CONTRIBUTING.rst | 9 +- docs/Makefile | 61 +- docs/_static/fig_gantt_min.png | Bin 0 -> 44469 bytes docs/_static/verilator_192_150_min.png | Bin 0 -> 4729 bytes docs/_static/verilator_32x32_min.png | Bin 0 -> 1619 bytes docs/bin/vl_sphinx_extract | 63 + docs/bin/vl_sphinx_fix | 79 + docs/gen/ex_USERERROR_faulty.rst | 4 + docs/gen/ex_USERERROR_msg.rst | 4 + docs/gen/ex_USERFATAL_faulty.rst | 4 + docs/gen/ex_USERFATAL_msg.rst | 4 + docs/gen/ex_USERINFO_faulty.rst | 4 + docs/gen/ex_USERINFO_msg.rst | 4 + docs/gen/ex_USERWARN_faulty.rst | 4 + docs/gen/ex_USERWARN_msg.rst | 4 + docs/gen/ex_VARHIDDEN_faulty.rst | 8 + docs/gen/ex_VARHIDDEN_msg.rst | 5 + docs/gen/ex_WIDTH_1_faulty.rst | 8 + docs/gen/ex_WIDTH_1_fixed.rst | 5 + docs/gen/ex_WIDTH_1_msg.rst | 4 + docs/guide/changes.rst | 16 + docs/guide/conf.py | 221 + docs/guide/connecting.rst | 451 ++ docs/guide/contributing.rst | 68 + docs/guide/contributors.rst | 155 + docs/guide/copyright.rst | 19 + docs/guide/deprecations.rst | 28 + docs/guide/environment.rst | 93 + docs/guide/example_cc.rst | 92 + docs/guide/example_common_install.rst | 18 + docs/guide/example_dist.rst | 40 + docs/guide/example_sc.rst | 73 + docs/guide/examples.rst | 22 + docs/guide/exe_sim.rst | 89 + docs/guide/exe_verilator.rst | 1623 +++++++ docs/guide/exe_verilator_coverage.rst | 114 + docs/guide/exe_verilator_gantt.rst | 76 + docs/guide/exe_verilator_profcfuncs.rst | 25 + docs/guide/executables.rst | 19 + docs/guide/extensions.rst | 492 ++ docs/guide/faq.rst | 495 ++ docs/guide/files.rst | 141 + docs/guide/index.rst | 37 + docs/guide/install.rst | 321 ++ docs/guide/languages.rst | 477 ++ docs/guide/overview.rst | 55 + docs/guide/simulating.rst | 352 ++ docs/guide/verilating.rst | 482 ++ docs/guide/warnings.rst | 1585 +++++++ docs/install.rst | 397 -- docs/internals.rst | 59 +- docs/spelling.txt | 850 ++++ docs/verilated.dox | 42 + docs/xml.rst | 4 +- src/pod2latexfix | 36 - test_regress/driver.pl | 68 + test_regress/t/t_assert_comp_bad.pl | 40 + test_regress/t/t_lint_width_docs_bad.out | 6 + test_regress/t/t_lint_width_docs_bad.pl | 36 + test_regress/t/t_lint_width_docs_bad.v | 19 + test_regress/t/t_var_bad_hide_docs.out | 8 + test_regress/t/t_var_bad_hide_docs.pl | 31 + test_regress/t/t_var_bad_hide_docs.v | 9 + test_regress/t/t_width_docs_bad.v | 19 + 74 files changed, 9186 insertions(+), 6126 deletions(-) create mode 100644 docs/_static/fig_gantt_min.png create mode 100644 docs/_static/verilator_192_150_min.png create mode 100644 docs/_static/verilator_32x32_min.png create mode 100755 docs/bin/vl_sphinx_extract create mode 100755 docs/bin/vl_sphinx_fix create mode 100644 docs/gen/ex_USERERROR_faulty.rst create mode 100644 docs/gen/ex_USERERROR_msg.rst create mode 100644 docs/gen/ex_USERFATAL_faulty.rst create mode 100644 docs/gen/ex_USERFATAL_msg.rst create mode 100644 docs/gen/ex_USERINFO_faulty.rst create mode 100644 docs/gen/ex_USERINFO_msg.rst create mode 100644 docs/gen/ex_USERWARN_faulty.rst create mode 100644 docs/gen/ex_USERWARN_msg.rst create mode 100644 docs/gen/ex_VARHIDDEN_faulty.rst create mode 100644 docs/gen/ex_VARHIDDEN_msg.rst create mode 100644 docs/gen/ex_WIDTH_1_faulty.rst create mode 100644 docs/gen/ex_WIDTH_1_fixed.rst create mode 100644 docs/gen/ex_WIDTH_1_msg.rst create mode 100644 docs/guide/changes.rst create mode 100644 docs/guide/conf.py create mode 100644 docs/guide/connecting.rst create mode 100644 docs/guide/contributing.rst create mode 100644 docs/guide/contributors.rst create mode 100644 docs/guide/copyright.rst create mode 100644 docs/guide/deprecations.rst create mode 100644 docs/guide/environment.rst create mode 100644 docs/guide/example_cc.rst create mode 100644 docs/guide/example_common_install.rst create mode 100644 docs/guide/example_dist.rst create mode 100644 docs/guide/example_sc.rst create mode 100644 docs/guide/examples.rst create mode 100644 docs/guide/exe_sim.rst create mode 100644 docs/guide/exe_verilator.rst create mode 100644 docs/guide/exe_verilator_coverage.rst create mode 100644 docs/guide/exe_verilator_gantt.rst create mode 100644 docs/guide/exe_verilator_profcfuncs.rst create mode 100644 docs/guide/executables.rst create mode 100644 docs/guide/extensions.rst create mode 100644 docs/guide/faq.rst create mode 100644 docs/guide/files.rst create mode 100644 docs/guide/index.rst create mode 100644 docs/guide/install.rst create mode 100644 docs/guide/languages.rst create mode 100644 docs/guide/overview.rst create mode 100644 docs/guide/simulating.rst create mode 100644 docs/guide/verilating.rst create mode 100644 docs/guide/warnings.rst delete mode 100644 docs/install.rst create mode 100644 docs/spelling.txt create mode 100644 docs/verilated.dox delete mode 100755 src/pod2latexfix create mode 100644 test_regress/t/t_lint_width_docs_bad.out create mode 100755 test_regress/t/t_lint_width_docs_bad.pl create mode 100644 test_regress/t/t_lint_width_docs_bad.v create mode 100644 test_regress/t/t_var_bad_hide_docs.out create mode 100755 test_regress/t/t_var_bad_hide_docs.pl create mode 100644 test_regress/t/t_var_bad_hide_docs.v create mode 100644 test_regress/t/t_width_docs_bad.v diff --git a/Changes b/Changes index 04cfda00b..8a9220922 100644 --- a/Changes +++ b/Changes @@ -11,6 +11,10 @@ contributors that suggested a given feature are shown in []. Thanks! Verilator 4.201 devel ========================== +**Major:** + +* Documentation has been rewritten into a book format. + **Minor:** * Add EOFNEWLINE warning when missing a newline at EOF. @@ -169,7 +173,7 @@ Verilator 4.102 2020-10-15 * Support # as a comment in -f files (#2497). [phantom-killua] * Support 'this' (#2585). [Rafal Kapuscik] * Support defines for FST tracing (#2592). [Markus Krause] -* Support |=> inside properties (#1292). [Peter Monsson] +* Support non-overapping implication inside properties (#1292). [Peter Monsson] * Fix timescale with --hierarchical (#2554). [Yutetsu TAKATSUKASA] * Fix cmake build with --hierarchical (#2560). [Yutetsu TAKATSUKASA] * Fix -G dropping public indication (#2561). [Andrew Goessling] @@ -195,7 +199,7 @@ Verilator 4.100 2020-09-07 * Support (with limitations) class extern, class extends, virtual class. * Support $urandom, $urandom_range without stability. * Support assume property. [Peter Monsson] -* Support |=> inside properties (#1292). [Peter Monsson] +* Support non-overapping implication inside properties (#1292). [Peter Monsson] * Fix false DECLFILENAME on black-boxed modules (#2430). [Philipp Wagner] * Fix naming of "id : begin" blocks. * Fix class constructor error on assignments to const. @@ -401,7 +405,7 @@ Verilator 4.026 2020-01-11 **Minor:** * Support bounded queues. -* Support implication operator "|->" in assertions. (#2069) [Peter Monsson] +* Support non-overlapping implication operator in assertions. (#2069) [Peter Monsson] * Support string compare, ato*, etc methods. (#1606) [Yutetsu TAKATSUKASA] * Support immediate cover statements. * Ignore `uselib to end-of-line. (#1634) [Frederic Antonin] @@ -1172,7 +1176,7 @@ Verilator 3.866 2014-11-15 * Add public enums. (#833) [Jonathon Donaldson] * Trace_off now operates on cells. (#826) [Lane Brooks] * Fix public parameters in unused packages. (#804) [Jonathon Donaldson] -* Fix select when partially out-of-bound. (#823) [Cliffort Wolf] +* Fix select when partially out-of-bound. (#823) [Clifford Wolf] * Fix generate unrolling with function call. (#830) [Steven Slatter] * Fix cast-to-size context-determined sizing. (#828) [Geoff Barrett] * Fix not tracing modules following primitives. (#837) [Jie Xu] @@ -1513,7 +1517,7 @@ Verilator 3.833 2012-04-15 **Minor:** * Support += and -= in standard for loops. (#463) [Alex Solomatnikov] -* Fix processing unused parametrized modules. (#469) (#470) [Alex Solomatnikov] +* Fix processing unused parameterized modules. (#469) (#470) [Alex Solomatnikov] * Add SELRANGE as warning instead of error. (#477) [Alex Solomatnikov] * Add readme.pdf and internal.pdf and doxygen. (#483) [by Jeremy Bennett] * Fix change detections on arrays. (#364) [John Stevenson, Alex Solomatnikov] @@ -1585,7 +1589,7 @@ Verilator 3.824 2011-10-25 **Minor:** * Fix "always @ (* )". (#403) (#404) [Walter Lavino] -* Add ASSIGNIN as suppressable error. [Jeremy Bennett] +* Add ASSIGNIN as suppressible error. [Jeremy Bennett] * Fix 3.823 constructor core dump on Debian. (#401) [Ahmed El-Mahmoudy] @@ -1667,7 +1671,7 @@ Verilator 3.811 2011-02-14 * Report error on duplicated or empty pins. (#321) [Christian Leber] * Report error on function call output tied to constant. [Bernard Deadman] -* Throw UNUSED/UNDRIVEN only once per net in a parametrized module. +* Throw UNUSED/UNDRIVEN only once per net in a parameterized module. * Fix internal error on functions called as SV tasks. [Bernard Deadman] * Fix internal error on non-inlined inout pins. [Jeff Winston] * Fix false BLKSEQ on non-unrolled for loop indexes. [Jeff Winston] @@ -1970,7 +1974,7 @@ Verilator 3.700 2009-01-08 * Line coverage now aggregates by hierarchy automatically. Previously this would be done inside SystemPerl, which was slower. * Minor performance improvements of Verilator compiler runtime. -* Coverage of each parametarized module is counted separately. [Bob Fredieu] +* Coverage of each parameterized module is counted separately. [Bob Fredieu] * Fix creating parameterized modules when no parameter values are changed. * Fix certain generate-if cells causing "clone" error. [Stephane Laurent] * Fix line coverage of public functions. [Soon Koh] @@ -2381,7 +2385,7 @@ Verilator 3.620 2006-10-04 Stable * Optimize variables set to constants within basic blocks for ~3%. * Default make no longer makes the docs; if you edit the documentation. sources, run "make info" to get them. -* Optimize additional boolean identities (a|a = a, etc.) +* Optimize additional Boolean identities (a|a = a, etc.) * Fix coredump when dotted cross-ref inside task call. [Eugene Weber] * Fix dotted variables in always sensitivity lists. [Allan Cochrane] diff --git a/MANIFEST.SKIP b/MANIFEST.SKIP index b46442e93..4a964bc40 100644 --- a/MANIFEST.SKIP +++ b/MANIFEST.SKIP @@ -42,6 +42,7 @@ docs/.*\.html$ docs/_build/ docs/clang-format.txt$ docs/doxygen-doc/.* +docs/spelling.txt examples/xml_py/copied/ examples/xml_py/graph.* sonar-project.properties diff --git a/Makefile.in b/Makefile.in index 1bc4b05d7..a2efb887d 100644 --- a/Makefile.in +++ b/Makefile.in @@ -51,7 +51,6 @@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_DATA = @INSTALL_DATA@ MAKEINFO = makeinfo POD2TEXT = pod2text -POD2LATEXFIX = $(srcdir)/src/pod2latexfix MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs PERL = @PERL@ @@ -111,14 +110,14 @@ SUBDIRS = docs src test_regress \ examples/make_protect_lib \ examples/xml_py \ -INFOS = verilator.txt verilator.html verilator.pdf +INFOS = verilator.html verilator.pdf INFOS_OLD = README README.html README.pdf # Files that can be generated, but should be up to date for a distribution. DISTDEP = info Makefile -DISTFILES_INC = $(INFOS) .gitignore \ +DISTFILES1 = $(INFOS) .gitignore \ *.in *.ac \ Artistic \ Changes \ @@ -137,9 +136,14 @@ DISTFILES_INC = $(INFOS) .gitignore \ docs/CONTRIBUTING.rst \ docs/CONTRIBUTORS \ docs/Makefile \ - docs/_static/verilator_logo.png \ + docs/_static/* \ + docs/bin/* \ + docs/gen/* \ + docs/guide/* \ docs/install.rst \ docs/internals.rst \ + docs/internals.rst \ + docs/verilated.dox \ docs/xml.rst \ install-sh configure *.pod \ include/*.[chv]* \ @@ -157,6 +161,8 @@ DISTFILES_INC = $(INFOS) .gitignore \ examples/*/.*ignore examples/*/Makefile* \ examples/*/*.[chv]* examples/*/vl_* \ examples/*/CMakeLists.txt \ + +DISTFILES2 = \ test_*/.*ignore test_*/Makefile* test_*/*.cpp \ test_*/*.pl test_*/*.v test_*/*.vc test_*/*.vh \ test_regress/*.pl \ @@ -195,8 +201,6 @@ INST_PROJ_BIN_FILES = \ bin/verilator_bin_dbg \ bin/verilator_coverage_bin_dbg \ -DISTFILES := $(DISTFILES_INC) - EXAMPLES_FIRST = \ examples/make_hello_c \ examples/make_hello_sc \ @@ -260,20 +264,14 @@ info: $(INFOS) %.1: ${srcdir}/bin/% pod2man $< $@ -verilator.txt: ${srcdir}/bin/verilator - $(POD2TEXT) $< $@ - -verilator.html: ${srcdir}/bin/verilator - pod2html $< >$@ +.PHONY: verilator.html +verilator.html: + $(MAKE) -C docs html # PDF needs DIST variables; but having configure.ac as dependency isn't detected -verilator.pdf: ${srcdir}/bin/verilator Makefile $(POD2LATEXFIX) - pod2latex --full --out verilator.tex $< - $(PERL) $(POD2LATEXFIX) "$(DISTTITLE)" "${DISTDATE}" < verilator.tex > verilator2.tex - mv verilator2.tex verilator.tex - pdflatex verilator.tex - pdflatex verilator.tex - -rm -f verilator.toc verilator.aux verilator.idx verilator.out +.PHONY: verilator.pdf +verilator.pdf: Makefile + $(MAKE) -C docs verilator.pdf # See uninstall also - don't put wildcards in this variable, it might uninstall other stuff VL_INST_BIN_FILES = verilator verilator_bin verilator_bin_dbg verilator_coverage_bin_dbg \ @@ -474,6 +472,10 @@ clang-format: PY_PROGRAMS = \ examples/xml_py/vl_file_copy \ examples/xml_py/vl_hier_graph \ + docs/guide/conf.py \ + docs/guide/vl_sphinx_extract \ + docs/guide/vl_sphinx_extract \ + docs/guide/vl_doxygen_filter \ src/astgen \ src/bisonpre \ src/config_rev \ @@ -564,6 +566,7 @@ clean mostlyclean distclean maintainer-clean:: rm -rf test_*/obj_dir rm -rf nodist/fuzzer/dictionary rm -rf nodist/obj_dir + rm -rf verilator.txt distclean maintainer-clean:: rm -f *.info* *.1 $(INFOS) $(INFOS_OLD) $(VL_INST_MAN_FILES) @@ -588,7 +591,8 @@ doxygen: dist-file-list: @echo "begin-dist-file-list:"; # Scripts look for this - @echo $(wildcard $(DISTFILES)) + @echo $(wildcard $(DISTFILES1)) + @echo $(wildcard $(DISTFILES2)) @echo "end-dist-file-list:"; # Scripts look for this ###################################################################### @@ -607,7 +611,12 @@ tag: # Don't depend on DISTFILES because there's no rule for "standards.info*". dist: $(DISTDEP) maintainer-copy -rm -fr $(DISTNAME) - for file in $(DISTFILES); do \ + for file in $(DISTFILES1); do \ + mkdir -p `dirname $(DISTNAME)/$$file` >/dev/null ; \ + ln $$file $(DISTNAME)/$$file \ + || { echo copying $$file instead; cp -p $$file $(DISTNAME)/$$file;}; \ + done; true; + for file in $(DISTFILES2); do \ mkdir -p `dirname $(DISTNAME)/$$file` >/dev/null ; \ ln $$file $(DISTNAME)/$$file \ || { echo copying $$file instead; cp -p $$file $(DISTNAME)/$$file;}; \ diff --git a/bin/verilator b/bin/verilator index 75d4bc395..59fb5e608 100755 --- a/bin/verilator +++ b/bin/verilator @@ -257,35 +257,14 @@ Verilog and SystemVerilog designs into a C++ or SystemC model that after compiling can be executed. Verilator is not a traditional simulator, but a compiler. -Verilator is typically used as follows: - -1. The C executable is invoked with parameters similar to GCC, -Cadence Verilog-XL/NC-Verilog, or Synopsys VCS. C reads the -specified user's SystemVerilog code, lints it, optionally adds coverage and -waveform tracing support, and compiles the design into a source level C++ -or SystemC "model". The resulting model's C++ or SystemC code is output as -.cpp and .h files. This is referred to as "verilating" and the process is -"to verilate"; the output is a "verilated" model. - -2. For simulation, a small user written C++ wrapper file is required, the -"wrapper". This wrapper defines the C++ function `main()` which -instantiates the Verilated model as a C++/SystemC object. - -3. The user main wrapper, the files created by Verilator, a "runtime -library" provided by Verilator, and if applicable the SystemC libraries are -then compiled using a C++ compiler to create a simulation executable. - -4. The resulting executable will perform the actual simulation, during -"simulation runtime". - -To get started, jump down to the L section. +For documentation see L. =head1 ARGUMENT SUMMARY This is a short summary of the arguments to the "verilator" executable. -See L for the detailed descriptions of these -arguments. +See L for the detailed +descriptions of these arguments. =for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst" @@ -452,8 +431,9 @@ arguments. -y Directory to search for modules This is a short summary of the simulation runtime arguments, i.e. for the -final Verilated simulation runtime models. See L for the detailed description of these arguments. +final Verilated simulation runtime models. See +L for the detailed description of +these arguments. =for VL_SPHINX_EXTRACT "_build/gen/args_verilated.rst" @@ -471,5383 +451,6 @@ ARGUMENTS"> for the detailed description of these arguments. +verilator+version Show version and exit -=head1 VERILATION ARGUMENTS - -The following are the arguments that may be passed to the "verilator" -executable. - -=over 4 - -=item - -Specifies the Verilog file containing the top module to be Verilated. - -=item - -Used with --exe to specify optional C++ files to be linked in with the -Verilog code. The file path should either be absolute, or relative to -where the make will be executed from, or add to your makefile's VPATH the -appropriate directory to find the file. - -See also the -CFLAGS and -LDFLAGS options, which are useful when the C++ -files need special compiler flags. - -=item - -Specifies optional object or library files to be linked in with the Verilog -code, as a shorthand for -LDFLAGS "". The file path should either be -absolute, or relative to where the make will be executed from, or add to -your makefile's VPATH the appropriate directory to find the file. - -If any files are specified in this way, Verilator will include a make rule -that uses these files when linking the I executable. This -generally is only useful when used with the --exe option. - -=item +1364-1995ext+I - -=item +1364-2001ext+I - -=item +1364-2005ext+I - -=item +1800-2005ext+I - -=item +1800-2009ext+I - -=item +1800-2012ext+I - -=item +1800-2017ext+I - -Specifies the language standard to be used with a specific filename -extension, I. - -For compatibility with other simulators, see also the synonyms -C<+verilog1995ext+>I, C<+verilog2001ext+>I, and -C<+systemverilogext+>I. - -For any source file, the language specified by these options takes -precedence over any language specified by the C<--default-language> or -C<--language> options. - -These options take effect in the order they are encountered. Thus the -following would use Verilog 1995 for C and Verilog 2001 for C. - - verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v - -These flags are only recommended for legacy mixed language designs, as the -preferable option is to edit the code to repair new keywords, or add -appropriate C<`begin_keywords>. - -B C<`begin_keywords> is a SystemVerilog construct, which specifies -I the set of keywords to be recognized. This also controls some error -messages that vary between language standards. Note at present Verilator -tends to be overly permissive, e.g. it will accept many grammar and other -semantic extensions which might not be legal when set to an older standard. - -=item --assert - -Enable all assertions. - -=item --autoflush - -After every $display or $fdisplay, flush the output stream. This ensures -that messages will appear immediately but may reduce performance. For best -performance call "fflush(stdout)" occasionally in the C++ main loop. -Defaults to off, which will buffer output as provided by the normal C/C++ -standard library IO. - -=item --bbox-sys - -Black box any unknown $system task or function calls. System tasks will -simply become no-operations, and system functions will be replaced with -unsized zero. Arguments to such functions will be parsed, but not -otherwise checked. This prevents errors when linting in the presence of -company specific PLI calls. - -Using this argument will likely cause incorrect simulation. - -=item --bbox-unsup - -Black box some unsupported language features, currently UDP tables, the -cmos and tran gate primitives, deassign statements, and mixed edge errors. -This may enable linting the rest of the design even when unsupported -constructs are present. - -Using this argument will likely cause incorrect simulation. - -=item --bin I - -Rarely needed. Override the default filename for Verilator itself. When a -dependency (.d) file is created, this filename will become a source -dependency, such that a change in this binary will have make rebuild the -output files. - -=item --build - -After generating the SystemC/C++ code, Verilator will invoke the toolchain to -build the model library (and executable when C<--exe> is also used). Verilator -manages the build itself, and for this --build requires GNU Make to be -available on the platform. - -=item -CFLAGS I - -Add specified C compiler flag to the generated makefiles. For multiple -flags either pass them as a single argument with space separators quoted in -the shell (C<-CFLAGS "-a -b">), or use multiple -CFLAGS arguments -(C<-CFLAGS -a -CFLAGS -b>). - -When make is run on the generated makefile these will be passed to the C++ -compiler (g++/clang++/msvc++). - -=item --cc - -Specifies C++ without SystemC output mode; see also --sc. - -=item --cdc - -Permanently experimental. Perform some clock domain crossing checks and -issue related warnings (CDCRSTLOGIC) and then exit; if warnings other than -CDC warnings are needed make a second run with --lint-only. Additional -warning information is also written to the file {prefix}__cdc.txt. - -Currently only checks some items that other CDC tools missed; if you have -interest in adding more traditional CDC checks, please contact the authors. - -=item --clk I - -Sometimes it is quite difficult for Verilator to distinguish clock signals from -other data signals. Occasionally the clock signals can end up in the checking -list of signals which determines if further evaluation is needed. This will -heavily degrade the performance of a Verilated model. - -With --clk , user can specified root clock into the model, then -Verilator will mark the signal as clocker and propagate the clocker attribute -automatically to other signals derived from that. In this way, Verilator will -try to avoid taking the clocker signal into checking list. - -Note signal-name is specified by the RTL hierarchy path. For example, v.foo.bar. -If the signal is the input to top-module, the directly the signal name. If you -find it difficult to find the exact name, try to use C in -RTL file to mark the signal directly. - -If clock signals are assigned to vectors and then later used individually, -Verilator will attempt to decompose the vector and connect the single-bit -clock signals directly. This should be transparent to the user. - -=item --make I - -Generates a script for the specified build tool. - -Supported values are C for GNU Make and C for CMake. Both can be -specified together. If no build tool is specified, gmake is assumed. The -executable of gmake can be configured via environment variable "MAKE". - -When using --build Verilator takes over the responsibility of building the -model library/executable. For this reason --make cannot be specified when -using --build. - -=item --compiler I - -Enables workarounds for the specified C++ compiler, either C, -C, or C. Currently this does not change any performance tuning -flags, but it may in the future. - -=over 4 - -=item clang - -Tune for clang. This may reduce execution speed as it enables several -workarounds to avoid silly hard-coded limits in clang. This includes -breaking deep structures as for msvc as described below. - -=item gcc - -Tune for GNU C++, although generated code should work on almost any -compliant C++ compiler. Currently the default. - -=item msvc - -Tune for Microsoft Visual C++. This may reduce execution speed as it -enables several workarounds to avoid silly hard-coded limits in MSVC++. -This includes breaking deeply nested parenthesized expressions into -sub-expressions to avoid error C1009, and breaking deep blocks into -functions to avoid error C1061. - -=back - -=item --converge-limit I - -Rarely needed. Specifies the maximum number of runtime iterations before -creating a model failed to converge error. Defaults to 100. - -=item --coverage - -Enables all forms of coverage, alias for "--coverage-line --coverage-toggle ---coverage-user". - -=item --coverage-line - -Specifies basic block line coverage analysis code should be inserted. - -Coverage analysis adds statements at each code flow change point (e.g. at -branches). At each such branch a unique counter is incremented. At the -end of a test, the counters along with the filename and line number -corresponding to each counter are written into logs/coverage.dat. - -Verilator automatically disables coverage of branches that have a $stop in -them, as it is assumed $stop branches contain an error check that should -not occur. A /*verilator coverage_block_off*/ comment will perform a -similar function on any code in that block or below, or /*verilator -coverage_on/coverage_off*/ will disable coverage around lines of code. - -Note Verilator may over-count combinatorial (non-clocked) blocks when those -blocks receive signals which have had the UNOPTFLAT warning disabled; for -most accurate results do not disable this warning when using coverage. - -=item --coverage-max-width I - -Rarely needed. Specify the maximum bit width of a signal that is subject -to toggle coverage. Defaults to 256, as covering large vectors may greatly -slow coverage simulations. - -=item --coverage-toggle - -Specifies signal toggle coverage analysis code should be inserted. - -Every bit of every signal in a module has a counter inserted. The counter -will increment on every edge change of the corresponding bit. - -Signals that are part of tasks or begin/end blocks are considered local -variables and are not covered. Signals that begin with underscores, are -integers, or are very wide (>256 bits total storage across all dimensions) -are also not covered. - -Hierarchy is compressed, such that if a module is instantiated multiple -times, coverage will be summed for that bit across ALL instantiations of -that module with the same parameter set. A module instantiated with -different parameter values is considered a different module, and will get -counted separately. - -Verilator makes a minimally-intelligent decision about what clock domain -the signal goes to, and only looks for edges in that clock domain. This -means that edges may be ignored if it is known that the edge could never be -seen by the receiving logic. This algorithm may improve in the future. -The net result is coverage may be lower than what would be seen by looking -at traces, but the coverage is a more accurate representation of the -quality of stimulus into the design. - -There may be edges counted near time zero while the model stabilizes. It's -a good practice to zero all coverage just before releasing reset to prevent -counting such behavior. - -A /*verilator coverage_off/on */ comment pair can be used around signals -that do not need toggle analysis, such as RAMs and register files. - -=item --coverage-underscore - -Enable coverage of signals that start with an underscore. Normally, these -signals are not covered. See also --trace-underscore. - -=item --coverage-user - -Enables user inserted functional coverage. Currently, all functional -coverage points are specified using SVA which must be separately enabled -with --assert. - -For example, the following statement will add a coverage point, with -the comment "DefaultClock": - - DefaultClock: cover property (@(posedge clk) cyc==3); - -=item -DI=I - -Defines the given preprocessor symbol. Similar to +define, but does not -allow multiple definitions with a single option using plus signs. +define -is fairly standard across Verilog tools while -D is similar to GCC. - -=item --debug - -Select the debug executable of Verilator (if available), and enable more -internal assertions (equivalent to C<--debug-check>), debugging messages -(equivalent to C<--debugi 3>), intermediate form dump files (equivalent to -C<--dump-treei 3>), and leak to make node numbers unique (--debug-leak). - -Verilator will also abort() instead of exit() if there are any errors -detected. - -=item --debug-check - -Rarely needed. Enable internal debugging assertion checks, without -changing debug verbosity. Enabled automatically when --debug specified. - -=item --no-debug-leak - -In --debug mode, by default Verilator intentionally leaks AstNode instances -instead of freeing them, so that each node pointer is unique in the -resulting tree files and dot files. - -This option disables the leak. This may avoid out-of-memory errors -when Verilating large models in --debug mode. - -Outside of --debug mode, AstNode instances should never be leaked and this -option has no effect. - -=item --debugi I - -=item --debugi-I I - -Rarely needed - for developer use. Set internal debugging level globally -to the specified debug level (1-10) or set the specified Verilator source -file to the specified level (e.g. C<--debugi-V3Width 9>). Higher levels -produce more detailed messages. See --debug for other implications of -having debug on (at levels other than zero). - -=item --default-language I - -Select the language to be used by default when first processing each -Verilog file. The language value must be "1364-1995", "1364-2001", -"1364-2005", "1800-2005", "1800-2009", "1800-2012" or "1800-2017". - -Any language associated with a particular file extension (see the various -+Iext+ options) will be used in preference to the language specified -by --default-language. - -The --default-language flag is only recommended for legacy code using the -same language in all source files, as the preferable option is to edit the -code to repair new keywords, or add appropriate C<`begin_keywords>. For -legacy mixed language designs, the various +Iext+ options should be -used. - -If no language is specified, either by this flag or +Iext+ options, -then the latest SystemVerilog language (IEEE 1800-2017) is used. - -=item +define+I=I - -=item +define+I=I+I=I... - -Defines the given preprocessor symbol, or multiple symbols if separated by -plus signs. Similar to -D; +define is fairly standard across Verilog tools -while -D is similar to GCC. - -=item --dpi-hdr-only - -Only generate the DPI header file. This option has no effect on the name -or location of the emitted DPI header file, it is output in C<--Mdir> as it -would be without this option. - -=item --dump-defines - -With -E, suppress normal output, and instead print a list of all defines -existing at the end of pre-processing the input files. Similar to GCC "-dM" -option. This also gives you a way of finding out what is predefined in -Verilator using the command: - - touch foo.v ; verilator -E --dump-defines foo.v - -=item --dump-tree - -Rarely needed. Enable writing .tree debug files with dumping level 3, -which dumps the standard critical stages. For details on the format see -the Verilator Internals manual. --dump-tree is enabled automatically with ---debug, so "--debug --no-dump-tree" may be useful if the dump files are -large and not desired. - -=item --dump-treei I - -=item --dump-treei-I I - -Rarely needed - for developer use. Set internal tree dumping level -globally to a specific dumping level or set the specified Verilator source -file to the specified tree dumping level (e.g. C<--dump-treei-V3Order 9>). -Level 0 disables dumps and is equivalent to "--no-dump-tree". Level 9 -enables dumping of every stage. - -=item --dump-tree-addrids - -Rarely needed - for developer use. Replace AST node addresses with short -identifiers in tree dumps to enhance readability. Each unique pointer value -is mapped to a unique identifier, but note that this is not necessarily -unique per node instance as an address might get reused by a newly allocated -node after a node with the same address has been dumped then freed. - -=item -E - -Preprocess the source code, but do not compile, as with 'gcc -E'. Output -is written to standard out. Beware of enabling debugging messages, as they -will also go to standard out. - -=item --error-limit I - -After this number of errors are encountered during Verilator run, exit. -Warnings are not counted in this limit. Defaults to 50. - -Does not affect simulation runtime errors, for those see -+verilator+error+limit. - -=item --exe - -Generate an executable. You will also need to pass additional .cpp files on -the command line that implement the main loop for your simulation. - -=item -F I - -Read the specified file, and act as if all text inside it was specified as -command line parameters. Any relative paths are relative to the directory -containing the specified file. See also -f. Note -F is fairly standard -across Verilog tools. - -=item -f I - -Read the specified file, and act as if all text inside it was specified as -command line parameters. Any relative paths are relative to the current -directory. See also -F. Note -f is fairly standard across Verilog tools. - -The file may contain // comments which are ignored to the end of the line. -Any $VAR, $(VAR), or ${VAR} will be replaced with the specified environment -variable. - -=item -FI I - -Force include of the specified C++ header file. All generated C++ files -will insert a #include of the specified file before any other includes. The -specified file might be used to contain define prototypes of custom -VL_VPRINTF functions, and may need to include verilatedos.h as this file is -included before any other standard includes. - -=item --flatten - -Force flattening of the design's hierarchy, with all modules, tasks and -functions inlined. Typically used with C<--xml-only>. Note flattening -large designs may require significant CPU time, memory and storage. - -=item -GI=I - -Overwrites the given parameter of the toplevel module. The value is limited -to basic data literals: - -=over 4 - -=item Verilog integer literals - -The standard Verilog integer literals are supported, so values like 32'h8, -2'b00, 4 etc. are allowed. Care must be taken that the single quote (I') is -properly escaped in an interactive shell, e.g., as -GWIDTH=8\'hx. - -=item C integer literals - -It is also possible to use C integer notation, including hexadecimal (0x..), -octal (0..) or binary (0b..) notation. - -=item Double literals - -Double literals must be one of the following styles: - - contains a dot (.) (e.g. 1.23) - - contains an exponent (e/E) (e.g. 12e3) - - contains p/P for hexadecimal floating point in C99 (e.g. 0x123.ABCp1) - -=item Strings - -Strings must be in double quotes (""). They must be escaped properly on the -command line, e.g. as -GSTR="\"My String\"" or -GSTR='"My String"'. - -=back - -=item --gate-stmts I - -Rarely needed. Set the maximum number of statements that may be present in -an equation for the gate substitution optimization to inline that equation. - -=item --gdb - -Run Verilator underneath an interactive GDB (or VERILATOR_GDB environment -variable value) session. See also --gdbbt. - -=item --gdbbt - -If --debug is specified, run Verilator underneath a GDB process and print a -backtrace on exit, then exit GDB immediately. Without --debug or if GDB -doesn't seem to work, this flag is ignored. Intended for easy creation of -backtraces by users; otherwise see the --gdb flag. - -=item --generate-key - -Generate a true-random key suitable for use with --protect-key, print it, -and exit immediately. - -=item --getenv I - -If the variable is declared in the environment, print it and exit -immediately. Otherwise, if it's built into Verilator (e.g. VERILATOR_ROOT), -print that and exit immediately. Otherwise, print a newline and exit -immediately. This can be useful in makefiles. See also -V, and the various -*.mk files. - -=item --help - -Displays this message and program version and exits. - -=item --hierarchical - -Enable hierarchical Verilation otherwise /*verilator hier_block*/ metacomment -is ignored. -See L. - -=item -II - -See -y. - -=item --if-depth I - -Rarely needed. Set the depth at which the IFDEPTH warning will fire, -defaults to 0 which disables this warning. - -=item +incdir+I - -See -y. - -=item --inhibit-sim - -Rarely needed. Create a "inhibitSim(bool)" function to enable and disable -evaluation. This allows an upper level testbench to disable modules that -are not important in a given simulation, without needing to recompile or -change the SystemC modules instantiated. - -=item --inline-mult I - -Tune the inlining of modules. The default value of 2000 specifies that up -to 2000 new operations may be added to the model by inlining, if more than -this number of operations would result, the module is not inlined. Larger -values, or a value < 1 will inline everything, will lead to longer compile -times, but potentially faster simulation speed. This setting is ignored -for very small modules; they will always be inlined, if allowed. - -=item -j - -Specify the level of parallelism for --build. must be a positive -integer specifying the maximum number of parallel build jobs, or can be -omitted. When is omitted, the build will not try to limit the number of -parallel build jobs but attempt to execute all independent build steps in -parallel. - -=item -LDFLAGS I - -Add specified C linker flags to the generated makefiles. For multiple -flags either pass them as a single argument with space separators quoted in -the shell (C<-LDFLAGS "-a -b">), or use multiple -LDFLAGS arguments -(C<-LDFLAGS -a -LDFLAGS -b>). - -When make is run on the generated makefile these will be passed to the C++ -linker (ld) *after* the primary file being linked. This flag is called --LDFLAGS as that's the traditional name in simulators; it's would have been -better called LDLIBS as that's the Makefile variable it controls. (In -Make, LDFLAGS is before the first object, LDLIBS after. -L libraries need -to be in the Make variable LDLIBS, not LDFLAGS.) - -=item --l2-name I - -Instead of using the module name when showing Verilog scope, use the name -provided. This allows simplifying some Verilator-embedded modeling -methodologies. Default is an l2-name matching the top module. The default -before 3.884 was "--l2-name v" - -For example, the program "module t; initial $display("%m"); endmodule" will -show by default "t". With "--l2-name v" it will print "v". - -=item --language I - -A synonym for C<--default-language>, for compatibility with other tools and -earlier versions of Verilator. - -=item +libext+I+I... - -Specify the extensions that should be used for finding modules. If for -example module I is referenced, look in I.I. Note +libext+ is -fairly standard across Verilog tools. Defaults to .v and .sv. - -=item --lint-only - -Check the files for lint violations only, do not create any other output. - -You may also want the -Wall option to enable messages that are considered -stylistic and not enabled by default. - -If the design is not to be completely Verilated see also the --bbox-sys and ---bbox-unsup options. - -=item -MAKEFLAGS - -When using --build, add the specified flag to the invoked make command line. -For multiple flags either pass them as a single argument with space separators -quoted in the shell (e.g. C<-MAKEFLAGS "-a -b">), or use multiple -MAKEFLAGS -arguments (e.g. C<-MAKEFLAGS -l -MAKEFLAGS -k>). Use of this option should not -be required for simple builds using the host toolchain. - -=item --max-num-width I - -Set the maximum number literal width (e.g. in 1024'd22 this it the 1024). -Defaults to 64K. - -=item --MMD -=item --no-MMD - -Enable/disable creation of .d dependency files, used for make dependency -detection, similar to gcc -MMD option. By default this option is enabled -for --cc or --sc modes. - -=item --MP - -When creating .d dependency files with --MMD, make phony targets. Similar -to gcc -MP option. - -=item --Mdir I - -Specifies the name of the Make object directory. All generated files will -be placed in this directory. If not specified, "obj_dir" is used. The -directory is created if it does not exist and the parent directories exist; -otherwise manually create the Mdir before calling Verilator. - -=item --mod-prefix I - -Specifies the name to prepend to all lower level classes. Defaults to -the same as --prefix. - -=item --no-clk I - -Prevent the specified signal from being marked as clock. See C<--clk>. - -=item --no-decoration - -When creating output Verilated code, minimize comments, white space, symbol -names and other decorative items, at the cost of greatly reduced -readability. This may assist C++ compile times. This will not typically -change the ultimate model's performance, but may in some cases. - -=item --no-pins64 - -Backward compatible alias for "--pins-bv 33". - -=item --no-relative-cfuncs - -Disable 'this->' references in generated functions, and instead Verilator -will generate absolute references starting from 'vlTOPp->'. This prevents -V3Combine from merging functions from multiple instances of the same -module, so it can grow the instruction stream. - -This is a work around for old compilers. Don't set this if your C++ -compiler supports __restrict__ properly, as GCC 4.5.x and newer do. For -older compilers, test if this switch gives you better performance or not. - -Compilers which don't honor __restrict__ will suspect that 'this->' -references and 'vlTOPp->' references may alias, and may write slow code -with extra loads and stores to handle the (imaginary) aliasing. Using only -'vlTOPp->' references allows these old compilers to produce tight code. - -=item --no-skip-identical -=item --skip-identical - -Rarely needed. Disables or enables skipping execution of Verilator if all -source files are identical, and all output files exist with newer dates. -By default this option is enabled for --cc or --sc modes only. - -=item +notimingchecks - -Ignored for compatibility with other simulators. - -=item -O0 - -Disables optimization of the model. - -=item -O3 - -Enables slow optimizations for the code Verilator itself generates (as -opposed to "-CFLAGS -O3" which effects the C compiler's optimization. -O3 -may improve simulation performance at the cost of compile time. This currently -sets --inline-mult -1. - -=item -OI - -Rarely needed. Enables or disables a specific optimizations, with the -optimization selected based on the letter passed. A lowercase letter -disables an optimization, an upper case letter enables it. This is -intended for debugging use only; see the source code for version-dependent -mappings of optimizations to -O letters. - -=item -o I - -Specify the name for the final executable built if using --exe. Defaults -to the --prefix if not specified. - -=item --no-order-clock-delay - -Rarely needed. Disables a bug fix for ordering of clock enables with -delayed assignments. This flag should only be used when suggested by the -developers. - -=item --output-split I - -Enables splitting the output .cpp files into multiple outputs. When a C++ -file exceeds the specified number of operations, a new file will be created -at the next function boundary. In addition, if the total output code size -exceeds the specified value, VM_PARALLEL_BUILDS will be set to 1 by default -in the generated make files, making parallel compilation possible. Using ---output-split should have only a trivial impact on model performance. But -can greatly improve C++ compilation speed. The use of I (set for you -if present at configure time) is also more effective with this option. - -This option is on by default with a value of 20000. To disable, pass with a -value of 0. - -=item --output-split-cfuncs I - -Enables splitting functions in the output .cpp files into multiple functions. -When a generated function exceeds the specified number of operations, a new -function will be created. With --output-split, this will enable the C++ -compiler to compile faster, at a small loss in performance that gets worse with -decreasing split values. Note that this option is stronger than --output-split -in the sense that --output-split will not split inside a function. - -Defaults to the value of --output-split, unless explicitly specified. - -=item --output-split-ctrace I - -Similar to --output-split-cfuncs, enables splitting trace functions in the -output .cpp files into multiple functions. - -Defaults to the value of --output-split, unless explicitly specified. - -=item -P - -With -E, disable generation of `line markers and blank lines, similar to -GCC -P flag. - -=item --pins64 - -Backward compatible alias for "--pins-bv 65". Note that's a 65, not a 64. - -=item --pins-bv I - -Specifies SystemC inputs/outputs of greater than or equal to I bits -wide should use sc_bv's instead of uint32/vluint64_t's. The default is -"--pins-bv 65", and the value must be less than or equal to 65. Versions -before Verilator 3.671 defaulted to "--pins-bv 33". The more sc_bv is -used, the worse for performance. Use the "/*verilator sc_bv*/" attribute -to select specific ports to be sc_bv. - -=item --pins-sc-uint - -Specifies SystemC inputs/outputs of greater than 2 bits wide should use -sc_uint between 2 and 64. When combined with the "--pins-sc-biguint" -combination, it results in sc_uint being used between 2 and 64 and -sc_biguint being used between 65 and 512. - -=item --pins-sc-biguint - -Specifies SystemC inputs/outputs of greater than 65 bits wide should use -sc_biguint between 65 and 512, and sc_bv from 513 upwards. When combined -with the "--pins-sc-uint" combination, it results in sc_uint being used -between 2 and 64 and sc_biguint being used between 65 and 512. - -=item --pins-uint8 - -Specifies SystemC inputs/outputs that are smaller than the --pins-bv -setting and 8 bits or less should use uint8_t instead of uint32_t. -Likewise pins of width 9-16 will use uint16_t instead of uint32_t. - -=item --pipe-filter I - -Rarely needed. Verilator will spawn the specified command as a subprocess -pipe, to allow the command to perform custom edits on the Verilog code -before it reaches Verilator. - -Before reading each Verilog file, Verilator will pass the file name to the -subprocess' stdin with 'read ""'. The filter may then read the file -and perform any filtering it desires, and feeds the new file contents back to -Verilator on stdout by first emitting a line defining the length in bytes of -the filtered output 'Content-Length: ', followed by the new filtered -contents. Output to stderr from the filter feeds through to Verilator's stdout -and if the filter exits with non-zero status Verilator terminates. See the -t/t_pipe_filter test for an example. - -To debug the output of the filter, try using the -E option to see -preprocessed output. - -=item --pp-comments - -With -E, show comments in preprocessor output. - -=item --prefix I - -Specifies the name of the top level class and makefile. Defaults to V -prepended to the name of the --top switch, or V prepended to the first -Verilog filename passed on the command line. - -=item --prof-cfuncs - -Modify the created C++ functions to support profiling. The functions will -be minimized to contain one "basic" statement, generally a single always -block or wire statement. (Note this will slow down the executable by ~5%.) -Furthermore, the function name will be suffixed with the basename of the -Verilog module and line number the statement came from. This allows gprof -or oprofile reports to be correlated with the original Verilog source -statements. See also L. - -=item --prof-threads - -Enable gantt chart data collection for threaded builds. - -Verilator will record the start and end time of each macro-task across a -number of calls to eval. (What is a macro-task? See the Verilator internals -document.) - -When profiling is enabled, the simulation runtime will emit a blurb of -profiling data in non-human-friendly form. The C script -will transform this into a nicer visual format and produce some related -statistics. - -=item --protect-key I - -Specifies the private key for --protect-ids. For best security this key -should be 16 or more random bytes, a reasonable secure choice is the output -of C. Typically, a key would be created by the -user once for a given protected design library, then every Verilator run -for subsequent versions of that library would be passed the same ---protect-key. Thus, if the input Verilog is similar between library -versions (Verilator runs), the Verilated code will likewise be mostly -similar. - -If --protect-key is not specified and a key is needed, Verilator will -generate a new key for every Verilator run. As the key is not saved, this -is best for security, but means every Verilator run will give vastly -different output even for identical input, perhaps harming compile times -(and certainly thrashing any I). - -=item --protect-ids - -Hash any private identifiers (variable, module, and assertion block names -that are not on the top level) into hashed random-looking identifiers, -resulting after compilation in protected library binaries that expose less -design information. This hashing uses the provided or default ---protect-key, see important details there. - -Verilator will also create a {prefix}__idmap.xml file which contains the -mapping from the hashed identifiers back to the original identifiers. This -idmap file is to be kept private, and is to assist mapping any simulation -runtime design assertions, coverage, or trace information, which will -report the hashed identifiers, back to the original design's identifier -names. - -Using DPI imports/exports is allowed and generally relatively safe in terms -of information disclosed, which is limited to the DPI function prototyptes. -Use of the VPI is not recommended as many design details may be exposed, -and an INSECURE warning will be issued. - -=item --protect-lib I - -Produces C++, Verilog wrappers and a Makefile which can in turn produce a -DPI library which can be used by Verilator or other simulators along with -the corresponding Verilog wrapper. The Makefile will build both a static -and dynamic version of the library named libI.a and libI.so -respectively. This is done because some simulators require a dynamic -library, but the static library is arguably easier to use if possible. ---protect-lib implies --protect-ids. - -This allows for the secure delivery of sensitive IP without the need for -encrypted RTL (i.e. IEEE P1735). See examples/make_protect_lib in the -distribution for a demonstration of how to build and use the DPI library. - -When using --protect-lib it is advised to also use C<--timescale-override -/1fs> to ensure the model has a time resolution that is always compatible -with the time precision of the upper instantiating module. - -=item --private - -Opposite of --public. Is the default; this option exists for backwards -compatibility. - -=item --public - -This is only for historical debug use. Using it may result in -mis-simulation of generated clocks. - -Declares all signals and modules public. This will turn off signal -optimizations as if all signals had a /*verilator public*/ comments and -inlining. This will also turn off inlining as if all modules had a -/*verilator public_module*/, unless the module specifically enabled it with -/*verilator inline_module*/. - -=item --public-flat-rw - -Declares all variables, ports and wires public as if they had /*verilator -public_flat_rw @ ()*/ comments. This will -make them VPI accessible by their flat name, but not turn off module -inlining. This is particularly useful in combination with --vpi. This may -also in some rare cases result in mis-simulation of generated clocks. -Instead of this global switch, marking only those signals that need -public_flat_rw is typically significantly better performing. - -=item -pvalue+I=I - -Overwrites the given parameter(s) of the toplevel module. See -G for a -detailed description. - -=item --quiet-exit - -When exiting due to an error, do not display the "Exiting due to Errors" -nor "Command Failed" messages. - -=item --relative-includes - -When a file references an include file, resolve the filename relative to -the path of the referencing file, instead of relative to the current -directory. - -=item --report-unoptflat - -Extra diagnostics for UNOPTFLAT warnings. This includes for each loop, the -10 widest variables in the loop, and the 10 most fanned out variables in -the loop. These are candidates for splitting into multiple variables to -break the loop. - -In addition produces a GraphViz DOT file of the entire strongly connected -components within the source associated with each loop. This is produced -irrespective of whether --dump-tree is set. Such graphs may help in -analyzing the problem, but can be very large indeed. - -Various commands exist for viewing and manipulating DOT files. For example -the I command can be used to convert a DOT file to a PDF for -printing. For example: - - dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot - -will generate a PDF Vt_unoptflat_simple_2_35_unoptflat.dot.pdf from the DOT -file. - -As an alternative, the I command can be used to view DOT files -interactively: - - xdot Vt_unoptflat_simple_2_35_unoptflat.dot - -=item --rr - -Run Verilator and record with rr. See: rr-project.org. - -=item --savable - -Enable including save and restore functions in the generated model. - -The user code must create a VerilatedSerialize or VerilatedDeserialze -object then calling the << or >> operators on the generated model and any -other data the process needs saved/restored. These functions are not -thread safe, and are typically called only by a main thread. - -For example: - - void save_model(const char* filenamep) { - VerilatedSave os; - os.open(filenamep); - os << main_time; // user code must save the timestamp, etc - os << *topp; - } - void restore_model(const char* filenamep) { - VerilatedRestore os; - os.open(filenamep); - os >> main_time; - os >> *topp; - } - -=item --sc - -Specifies SystemC output mode; see also --cc. - -=item --stats - -Creates a dump file with statistics on the design in {prefix}__stats.txt. - -=item --stats-vars - -Creates more detailed statistics, including a list of all the variables by -size (plain --stats just gives a count). See --stats, which is implied by -this. - -=item --structs-packed - -Converts all unpacked structures to packed structures and issues a UNPACKED -warning. Currently this is the default and --no-structs-packed will not -work. Specifying this option allows for forward compatibility when a -future version of Verilator no longer always packs unpacked structures. - -=item -sv - -Specifies SystemVerilog language features should be enabled; equivalent to -"--language 1800-2017". This option is selected by default, it exists for -compatibility with other simulators. - -=item +systemverilogext+I - -A synonym for C<+1800-2017ext+>I. - -=item --threads I - -=item --no-threads - -With --threads 0 or --no-threads, the default, the generated model is not -thread safe. With --threads 1, the generated model is single threaded but -may run in a multithreaded environment. With --threads N, where N >= 2, the -model is generated to run multithreaded on up to N threads. See -L. - -=item --threads-dpi all - -=item --threads-dpi none - -=item --threads-dpi pure - -When using --threads, controls which DPI imported tasks and functions are -considered thread safe. - -With --threads-dpi all, enable Verilator to assume all DPI imports are -threadsafe, and to use thread-local storage for communication with DPI, -potentially improving performance. Any DPI libraries need appropriate -mutexes to avoid undefined behavior. - -With --threads-dpi none, Verilator assume DPI imports are not thread safe, -and Verilator will serialize calls to DPI imports by default, potentially -harming performance. - -With --threads-dpi pure, the default, Verilator assumes DPI pure imports -are threadsafe, but non-pure DPI imports are not. - -=item --threads-max-mtasks I - -Rarely needed. When using --threads, specify the number of mtasks the -model is to be partitioned into. If unspecified, Verilator approximates a -good value. - -=item --timescale I/I - -Sets default timescale, timeunit and timeprecision for when `timescale does -not occur before a given module. Default is "1ps/1ps" (to match SystemC). -This is overridden by C<--timescale-override>. - -=item --timescale-override I/I - -=item --timescale-override /I - -Overrides all `timescales in sources. The timeunit may be left empty to -specify only to override the timeprecision, e.g. "/1fs". - -The time precision must be consistent with SystemC's -sc_set_time_resolution, or the C++ code instantiating the Verilated module. -As 1fs is the finest time precision it may be desirable to always use a -precision of 1fs. - -=item --top I - -=item --top-module I - -When the input Verilog contains more than one top level module, specifies -the name of the Verilog module to become the top level module, and sets the -default for --prefix if not explicitly specified. This is not needed with -standard designs with only one top. See also the MULTITOP warning section. - -=item --trace - -Adds waveform tracing code to the model using VCD format. This overrides -C<--trace-fst>. - -Verilator will generate additional {prefix}__Trace*.cpp files that will -need to be compiled. In addition verilated_vcd_sc.cpp (for SystemC traces) -or verilated_vcd_c.cpp (for both) must be compiled and linked in. If using -the Verilator generated Makefiles, these files will be added to the source -file lists for you. If you are not using the Verilator Makefiles, you will -need to add these to your Makefile manually. - -Having tracing compiled in may result in some small performance losses, -even when tracing is not turned on during model execution. - -See also C<--trace-threads>. - -=item --trace-coverage - -With --trace and --coverage-*, enable tracing to include a traced signal -for every --coverage-line or --coverage-user inserted coverage point, to -assist in debugging coverage items. Note --coverage-toggle does not get -additional signals added, as the original signals being toggle-analyzed are -already visible. - -The added signal will be a 32-bit value which will increment on each -coverage occurrence. Due to this, this option may greatly increase trace -file sizes and reduce simulation speed. - -=item --trace-depth I - -Specify the number of levels deep to enable tracing, for example ---trace-level 1 to only see the top level's signals. Defaults to the -entire model. Using a small number will decrease visibility, but greatly -improve simulation performance and trace file size. - -=item --trace-fst - -Enable FST waveform tracing in the model. This overrides C<--trace>. -See also C<--trace-threads>. - -=item --trace-max-array I - -Rarely needed. Specify the maximum array depth of a signal that may be -traced. Defaults to 32, as tracing large arrays may greatly slow traced -simulations. - -=item --trace-max-width I - -Rarely needed. Specify the maximum bit width of a signal that may be -traced. Defaults to 256, as tracing large vectors may greatly slow traced -simulations. - -=item --no-trace-params - -Disable tracing of parameters. - -=item --trace-structs - -Enable tracing to show the name of packed structure, union, and packed -array fields, rather than a single combined packed bus. Due to VCD file -format constraints this may result in significantly slower trace times and -larger trace files. - -=item --trace-threads I - -Enable waveform tracing using separate threads. This is typically faster in -simulation runtime but uses more total compute. This option is independent of, -and works with, both C<--trace> and C<--trace-fst>. Different trace formats can -take advantage of more trace threads to varying degrees. Currently VCD tracing -can utilize at most --trace-threads 1, and FST tracing can utilize at most ---trace-threads 2. This overrides C<--no-threads>. - -=item --trace-underscore - -Enable tracing of signals that start with an underscore. Normally, these -signals are not output during tracing. See also --coverage-underscore. - -=item -UI - -Undefines the given preprocessor symbol. - -=item --unroll-count I - -Rarely needed. Specifies the maximum number of loop iterations that may be -unrolled. See also BLKLOOPINIT warning. - -=item --unroll-stmts I - -Rarely needed. Specifies the maximum number of statements in a loop for -that loop to be unrolled. See also BLKLOOPINIT warning. - -=item --unused-regexp I - -Rarely needed. Specifies a simple regexp with * and ? that if a signal -name matches will suppress the UNUSED warning. Defaults to "*unused*". -Setting it to "" disables matching. - -=item -V - -Shows the verbose version, including configuration information compiled -into Verilator. (Similar to perl -V.) See also --getenv. - -=item -v I - -Read the filename as a Verilog library. Any modules in the file may be -used to resolve instances in the top level module, else ignored. Note -v -is fairly standard across Verilog tools. - -=item --no-verilate - -When using --build, disable generation of C++/SystemC code, and execute only -the build. This can be useful for rebuilding Verilated code produced by a -previous invocation of Verilator. - -=item +verilog1995ext+I - -=item +verilog2001ext+I - -Synonyms for C<+1364-1995ext+>I and C<+1364-2001ext+>I respectively - -=item --version - -Displays program version and exits. - -=item --vpi - -Enable use of VPI and linking against the verilated_vpi.cpp files. - -=item --waiver-output - -Generate a waiver file which contains all waiver statements to suppress the -warnings emitted during this Verilator run. This in particular is useful as -a starting point for solving linter warnings or suppressing them -systematically. - -The generated file is in the Verilator Configuration format, see -L, and can directly be consumed by Verilator. The -standard file extension is .vlt. - -=item -Wall - -Enable all code style warnings, including code style warnings that are -normally disabled by default. Equivalent to "-Wwarn-lint -Wwarn-style". -Excludes some specialty warnings, i.e. IMPERFECTSCH. - -=item -Werror-I - -Promote the specified warning message into an error message. This is -generally to discourage users from violating important site-wide rules, for -example C<-Werror-NOUNOPTFLAT>. - -=item -Wfuture-I - -Rarely needed. Suppress unknown Verilator comments or warning messages -with the given message code. This is used to allow code written with -pragmas for a later version of Verilator to run under a older version; add --Wfuture- arguments for each message code or comment that the new version -supports which the older version does not support. - -=item -Wno-I - -Disable the specified warning/error message. This will override any lint_on -directives in the source, i.e. the warning will still not be printed. - -=item -Wno-context - -Disable showing the suspected context of the warning message by quoting the -source text at the suspected location. This can be used to appease tools which -process the warning messages but may get confused by lines from the original -source. - -=item -Wno-fatal - -When warnings are detected, print them, but do not terminate Verilator. - -Having warning messages in builds is sloppy. It is strongly recommended -you cleanup your code, use inline lint_off, or use -Wno-... flags rather -than using this option. - -=item -Wno-lint - -Disable all lint related warning messages, and all style warnings. This is -equivalent to "-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE --Wno-CASEOVERLAP -Wno-CASEX -Wno-CASTCONST -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS --Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY --Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED --Wno-WIDTH" plus the list shown for Wno-style. - -It is strongly recommended you cleanup your code rather than using this -option, it is only intended to be use when running test-cases of code -received from third parties. - -=item -Wno-style - -Disable all code style related warning messages (note by default they are -already disabled). This is equivalent to "-Wno-DECLFILENAME -Wno-DEFPARAM --Wno-EOFNEWLINE -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY --Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED --Wno-VARHIDDEN". - -=item -Wpedantic - -Warn on any construct demanded by IEEE, and disable all Verilator -extensions that may interfere with IEEE compliance to the standard defined -with --default-language (etc). Similar to GCC's -Wpedantic. Rarely used, -and intended only for strict compliance tests. - -=item -Wwarn-I - -Enables the specified warning message. - -=item -Wwarn-lint - -Enable all lint related warning messages (note by default they are already -enabled), but do not affect style messages. This is equivalent to -"-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE --Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASTCONST -Wwarn-CASEWITHX -Wwarn-CMPCONST --Wwarn-COLONPLUS -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN --Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH". - -=item -Wwarn-style - -Enable all code style related warning messages. This is equivalent to -"-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-EOFNEWLINE --Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN --Wwarn-UNUSED -Wwarn-VARHIDDEN". - -=item --x-assign 0 - -=item --x-assign 1 - -=item --x-assign fast (default) - -=item --x-assign unique - -Controls the two-state value that is substituted when an explicit X value is -encountered in the source. C<--x-assign fast>, the default, converts all Xs to -whatever is best for performance. C<--x-assign 0> converts all Xs to 0s, and -is also fast. C<--x-assign 1> converts all Xs to 1s, this is nearly as fast as -0, but more likely to find reset bugs as active high logic will fire. Using -C<--x-assign unique> will result in all explicit Xs being replaced by a -constant value determined at runtime. The value is determined by calling a -function at initialization time. This enables randomization of Xs with -different seeds on different executions. This method is the slowest, but safest -for finding reset bugs. - -If using --x-assign unique, you may want to seed your random number generator -such that each regression run gets a different randomization sequence. The -simplest is to use the +verilator+seed runtime option. Alternatively use the -system's srand48() or for Windows srand() function to do this. You'll probably -also want to print any seeds selected, and code to enable rerunning with that -same seed so you can reproduce bugs. - -B This option applies only to values which are explicitly written as -X in the Verilog source code. Initial values of clocks are set to 0 unless ---x-initial-edge is specified. Initial values of all other state holding -variables are controlled with --x-initial. - -=item --x-initial 0 - -=item --x-initial fast - -=item --x-initial unique (default) - -Controls the two-state value that is used to initialize variables that are -not otherwise initialized. - -C<--x-initial 0>, initializes all otherwise uninitialized variables to zero. - -C<--x-initial unique>, the default, initializes variables using a function, -which determines the value to use each initialization. This gives greatest -flexibility and allows finding reset bugs. See L. - -C<--x-initial fast>, is best for performance, and initializes all variables to -a state Verilator determines is optimal. This may allow further code -optimizations, but will likely hide any code bugs relating to missing -resets. - -B This option applies only to initial values of variables. Initial -values of clocks are set to 0 unless --x-initial-edge is specified. - -=item --x-initial-edge - -Enables emulation of event driven simulators which generally trigger an -edge on a transition from X to 1 (C) or X to 0 (C). Thus -the following code, where C is uninitialized would set C to -C<1'b1> when C is first set to zero: - - reg res_n = 1'b0; - - always @(negedge rst_n) begin - if (rst_n == 1'b0) begin - res_n <= 1'b1; - end - end - - -In Verilator, by default, uninitialized clocks are given a value of zero, -so the above C block would not trigger. - -While it is not good practice, there are some designs that rely on X -E 0 triggering a C, particularly in reset sequences. Using ---x-initial-edge with Verilator will replicate this behavior. It will also -ensure that X E 1 triggers a C. - -B Some users have reported that using this option can affect -convergence, and that it may be necessary to use --converge-limit to -increase the number of convergence iterations. This may be another -indication of problems with the modeled design that should be addressed. - -=item --xml-only - -Create XML output only, do not create any other output. - -The XML format is intended to be used to leverage Verilator's parser and -elaboration to feed to other downstream tools. Be aware that the XML format -is still evolving; there will be some changes in future versions. - -=item --xml-output I - -Filename for XML output file. Using this option automatically sets ---xml-only. - -=item -y I - -Add the directory to the list of directories that should be searched for -include files or libraries. The three flags -y, +incdir and -I have -similar effect; +incdir and +y are fairly standard across Verilog tools while --I is used by many C++ compilers. - -Verilator defaults to the current directory ("-y .") and any specified ---Mdir, though these default paths are used after any user specified -directories. This allows '-y "$(pwd)"' to be used if absolute filenames -are desired for error messages instead of relative filenames. - -=back - - -=head1 SIMULATION RUNTIME ARGUMENTS - -The following are the arguments that may be passed to a Verilated -executable, provided that executable calls Verilated::commandArgs(). - -All simulation runtime arguments begin with +verilator, so that the user's -executable may skip over all +verilator arguments when parsing its command -line. - -=over 4 - -=item +verilator+debug - -Enable simulation runtime debugging. Equivalent to +verilator+debugi+4. - -=item +verilator+debugi+I - -Enable simulation runtime debugging at the provided level. - -=item +verilator+error+limit+I - -Set number of non-fatal errors (e.g. assertion failures) before exiting -simulation runtime. Also affects number of $stop calls needed before -exit. Defaults to 1. - -=item +verilator+help - -Display help and exit. - -=item +verilator+prof+threads+file+I - -When a model was Verilated using --prof-threads, sets the simulation runtime -filename to dump to. Defaults to "profile_threads.dat". - -=item +verilator+prof+threads+start+I - -When a model was Verilated using --prof-threads, the simulation runtime will -wait until $time is at this value (expressed in units of the time -precision), then start the profiling warmup, then capturing. Generally this -should be set to some time that is well within the normal operation of the -simulation, i.e. outside of reset. If 0, the dump is disabled. Defaults to -1. - -=item +verilator+prof+threads+window+I - -When a model was Verilated using --prof-threads, after $time reaches -+verilator+prof+threads+start, Verilator will warm up the profiling for -this number of eval() calls, then will capture the profiling of this number -of eval() calls. Defaults to 2, which makes sense for a -single-clock-domain module where it's typical to want to capture one -posedge eval() and one negedge eval(). - -=item +verilator+rand+reset+I - -When a model was Verilated using "-x-initial unique", sets the simulation -runtime initialization technique. 0 = Reset to zeros. 1 = Reset to -all-ones. 2 = Randomize. See L. - -=item +verilator+seed+I - -For $random and "-x-initial unique", set the simulation runtime random seed -value. If zero or not specified picks a value from the system random -number generator. - -=item +verilator+noassert - -Disable assert checking per runtime argument. This is the same as calling -"Verilated::assertOn(false)" in the model. - -=item +verilator+V - -Shows the verbose version, including configuration information. - -=item +verilator+version - -Displays program version and exits. - -=back - - -=head1 EXAMPLE C++ EXECUTION - -We'll compile this example into C++. For an extended and commented version -of what this C++ code is doing, see examples/make_tracing_c/sim_main.cpp. - - mkdir test_our - cd test_our - - cat >our.v <<'EOF' - module our; - initial begin $display("Hello World"); $finish; end - endmodule - EOF - - cat >sim_main.cpp <<'EOF' - #include "Vour.h" - #include "verilated.h" - int main(int argc, char** argv, char** env) { - VerilatedContext* contextp = new VerilatedContext; - contextp->commandArgs(argc, argv); - Vour* top = new Vour{contextp}; - while (!contextp->gotFinish()) { top->eval(); } - delete top; - delete contextp; - return 0; - } - EOF - -Next we need Verilator installed. See the README in the source kit for -various ways to install or point to Verilator binaries. In brief, if you -installed Verilator using the package manager of your operating system, or -did a "make install" to place Verilator into your default path, you do not -need anything special in your environment, and should not have -VERILATOR_ROOT set. However, if you installed Verilator from sources and -want to run Verilator out of where you compiled Verilator, you need to -point to the kit: - - # See above; don't do this if using an OS-distributed Verilator - export VERILATOR_ROOT=/path/to/where/verilator/was/installed - export PATH=$VERILATOR_ROOT/bin:$PATH - -Now we run Verilator on our little example. - - verilator -Wall --cc our.v --exe --build sim_main.cpp - -We can see the source code under the "obj_dir" directory. See the FILES -section below for descriptions of some of the files that were created. - - ls -l obj_dir - -(Verilator included a default compile rule and link rule, since we used ---exe and passed a .cpp file on the Verilator command line. Verilator also -then used C to build a final executable, since we used --build. You -can also write your own compile rules, and run make yourself as we'll show -in the SYSTEMC section. - -And now we run it: - - obj_dir/Vour - -And we get as output: - - Hello World - - our.v:2: Verilog $finish - -Really, you're better off writing a Makefile to do all this for you. Then, -when your source changes it will automatically run all of these steps; to -aid this Verilator can create a makefile dependency file. See the examples -directory in the distribution. - - -=head1 EXAMPLE SYSTEMC EXECUTION - -This is an example similar to the above, but using SystemC. - - mkdir test_our_sc - cd test_our_sc - - cat >our.v <<'EOF' - module our (clk); - input clk; // Clock is required to get initial activation - always @(posedge clk) - begin $display("Hello World"); $finish; end - endmodule - EOF - - cat >sc_main.cpp <<'EOF' - #include "Vour.h" - int sc_main(int argc, char** argv) { - Verilated::commandArgs(argc, argv); - sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true}; - Vour* top = new Vour{"top"}; - top->clk(clk); - while (!Verilated::gotFinish()) { sc_start(1, SC_NS); } - delete top; - return 0; - } - EOF - -See the README in the source kit for various ways to install or point to -Verilator binaries. In brief, if you installed Verilator using the package -manager of your operating system, or did a "make install" to place -Verilator into your default path, you do not need anything special in your -environment, and should not have VERILATOR_ROOT set. However, if you -installed Verilator from sources and want to run Verilator out of where you -compiled Verilator, you need to point to the kit: - - # See above; don't do this if using an OS-distributed Verilator - export VERILATOR_ROOT=/path/to/where/verilator/was/installed - export PATH=$VERILATOR_ROOT/bin:$PATH - -Now we run Verilator on our little example. - - verilator -Wall --sc our.v - -We then can compile it - - make -j -C obj_dir -f Vour.mk Vour__ALL.a - make -j -C obj_dir -f Vour.mk ../sc_main.o verilated.o - -And link with SystemC. Note your path to the libraries may vary, -depending on the operating system. - - cd obj_dir - export SYSTEMC_LIBDIR=/path/to/where/libsystemc.a/exists - export LD_LIBRARY_PATH=$SYSTEMC_LIBDIR:$LD_LIBRARY_PATH - # Might be needed if SystemC 2.3.0 - export SYSTEMC_CXX_FLAGS=-pthread - - g++ -L$SYSTEMC_LIBDIR ../sc_main.o Vour__ALL.a verilated.o \ - -o Vour -lsystemc - -And now we run it - - cd .. - obj_dir/Vour - -And we get the same output as the C++ example: - - Hello World - - our.v:2: Verilog $finish - -Really, you're better off using a Makefile to do all this for you. Then, -when your source changes it will automatically run all of these steps. See -the examples directory in the distribution. - - -=head1 EVALUATION LOOP - -When using SystemC, evaluation of the Verilated model is managed by the SystemC -kernel, and for the most part can be ignored. When using C++, the user -must call eval(), or eval_step() and eval_end_step(). - -1. When there is a single design instantiated at the C++ level that needs -to evaluate within a given context, just call designp->eval(). - -2. When there are multiple designs instantiated at the C++ level that need -to evaluate within a context, call first_designp->eval_step() then -->eval_step() on all other designs. Then call ->eval_end_step() on the -first design then all other designs. If there is only a single design, you -would call eval_step() then eval_end_step(); in fact eval() described above -is just a wrapper which calls these two functions. - -When eval() is called Verilator looks for changes in clock signals and -evaluates related sequential always blocks, such as computing always_ff @ -(posedge...) outputs. Then Verilator evaluates combinatorial logic. - -Note combinatorial logic is not computed before sequential always blocks -are computed (for speed reasons). Therefore it is best to set any non-clock -inputs up with a separate eval() call before changing clocks. - -Alternatively, if all always_ff statements use only the posedge of clocks, -or all inputs go directly to always_ff statements, as is typical, then you -can change non-clock inputs on the negative edge of the input clock, which -will be faster as there will be fewer eval() calls. - -For more information on evaluation, see docs/internals.rst in the -distribution. - - -=head1 BENCHMARKING & OPTIMIZATION - -For best performance, run Verilator with the "-O3 --x-assign fast --x-initial -fast --noassert" flags. The -O3 flag will require longer time to run -Verilator, and "--x-assign fast --x-initial fast" may increase the risk of -reset bugs in trade for performance; see the above documentation for these -flags. - -If using Verilated multithreaded, use C to ensure you are using -non-conflicting hardware resources. See L. - -Minor Verilog code changes can also give big wins. You should not have any -UNOPTFLAT warnings from Verilator. Fixing these warnings can result in -huge improvements; one user fixed their one UNOPTFLAT warning by making a -simple change to a clock latch used to gate clocks and gained a 60% -performance improvement. - -Beyond that, the performance of a Verilated model depends mostly on your -C++ compiler and size of your CPU's caches. Experience shows that large models -are often limited by the size of the instruction cache, and as such reducing -code size if possible can be beneficial. - -The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT, OPT_FAST, -OPT_SLOW and OPT_GLOBAL variables to control optimization. You can set these -when compiling the output of Verilator with Make, for example: - - make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a - -OPT_FAST specifies optimization flags for those parts of the model that are on -the fast path. This is mostly code that is executed every cycle. OPT_SLOW -applies to slow-path code, which executes rarely, often only once at the -beginning or end of simulation. Note that OPT_SLOW is ignored if -VM_PARALLEL_BUILDS is not 1, in which case all generated code will be compiled -in a single compilation unit using OPT_FAST. See also the C<--output-split> -option. The OPT_GLOBAL variable applies to common code in the runtime library -used by Verilated models (shipped in $VERILATOR_ROOT/include). Additional C++ -files passed on the verilator command line use OPT_FAST. The OPT variable -applies to all compilation units in addition to the specific OPT_* variables -described above. - -You can also use the -CFLAGS and/or -LDFLAGS options on the verilator command -line to pass flags directly to the compiler or linker. - -The default values of the OPT_* variables are chosen to yield good simulation -speed with reasonable C++ compilation times. To this end, OPT_FAST is set to -"-Os" by default. Higher optimization such as "-O2" or "-O3" may help (though -often they provide only a very small performance benefit), but compile times -may be excessively large even with medium sized designs. Compilation times can -be improved at the expense of simulation speed by reducing optimization, for -example with OPT_FAST="-O0". Often good simulation speed can be achieved with -OPT_FAST="-O1 -fstrict-aliasing" but with improved compilation times. Files -controlled by OPT_SLOW have little effect on performance and therefore OPT_SLOW -is empty by default (equivalent to "-O0") for improved compilation speed. In -common use-cases there should be little benefit in changing OPT_SLOW. -OPT_GLOBAL is set to "-Os" by default and there should rarely be a need to -change it. As the runtime library is small in comparison to a lot of Verilated -models, disabling optimization on the runtime library should not have a -serious effect on overall compilation time, but may have detrimental effect on -simulation speed, especially with tracing. In addition to the above, for best -results use OPT="-march=native", the latest Clang compiler (about 10% faster -than GCC), and link statically. - -Generally the answer to which optimization level gives the best user experience -depends on the use case and some experimentation can pay dividends. For a -speedy debug cycle during development, especially on large designs where C++ -compilation speed can dominate, consider using lower optimization to get to an -executable faster. For throughput oriented use cases, for example regressions, -it is usually worth spending extra compilation time to reduce total CPU time. - -If you will be running many simulations on a single model, you can investigate -profile guided optimization. With GCC, using -fprofile-arcs, then --fbranch-probabilities will yield another 15% or so. - -Modern compilers also support link-time optimization (LTO), which can help -especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in both -compilation and link. Note LTO may cause excessive compile times on large -designs. - -Unfortunately, using the optimizer with SystemC files can result in compilation -taking several minutes. (The SystemC libraries have many little inlined -functions that drive the compiler nuts.) - -If you are using your own makefiles, you may want to compile the Verilated -code with -DVL_INLINE_OPT=inline. This will inline functions, however this -requires that all cpp files be compiled in a single compiler run. - -You may uncover further tuning possibilities by profiling the Verilog code. -Use Verilator's --prof-cfuncs, then GCC's -g -pg. You can then run -either oprofile or gprof to see where in the C++ code the time is spent. -Run the gprof output through verilator_profcfunc and it will tell you what -Verilog line numbers on which most of the time is being spent. - -When done, please let the author know the results. We like to keep tabs on -how Verilator compares, and may be able to suggest additional improvements. - - -=head1 FILES - -All output files are placed in the output directory specified with the -C<--Mdir> option, or "obj_dir" if not specified. - -Verilator creates the following files in the output directory: - -For --make gmake, it creates: - - {prefix}.mk // Make include file for compiling - {prefix}_classes.mk // Make include file with class names - {prefix}_hier.mk // Make file for hierarchy blocks - {prefix}_hierMkArgs.f // Arguments for hierarchical Verilation. - -For --make cmake, it creates: - - {prefix}.cmake // CMake include script for compiling - {prefix}_hierCMakeArgs.f // Arguments for hierarchical Verilation. - -For -cc and -sc mode, it also creates: - - {prefix}.cpp // Top level C++ file - {prefix}.h // Top level header - {prefix}__Slow{__n}.cpp // Constructors and infrequent cold routines - {prefix}{__n}.cpp // Additional top C++ files (--output-split) - {prefix}{each_verilog_module}.cpp // Lower level internal C++ files - {prefix}{each_verilog_module}.h // Lower level internal header files - {prefix}{each_verilog_module}{__n}.cpp // Additional lower C++ files (--output-split) - -For --hierarchy mode, it creates: - {prefix}__hierVer.d // Make dependencies of the top module in the - hierarchical Verilation - {prefix}__hier.dir/ // Directory to store .dot, .vpp, .tree of the - top module in the hierarchical Verilation - V{hier_block}/ // Directory to Verilate each hierarchy block - -In certain debug and other modes, it also creates: - - {prefix}.xml // XML tree information (--xml) - {prefix}__Dpi.cpp // DPI import and export wrappers - {prefix}__Dpi.h // DPI import and export declarations - {prefix}__Inlines.h // Inline support functions - {prefix}__Syms.cpp // Global symbol table C++ - {prefix}__Syms.h // Global symbol table header - {prefix}__Trace__Slow{__n}.cpp // Wave file generation code (--trace) - {prefix}__Trace{__n}.cpp // Wave file generation code (--trace) - {prefix}__cdc.txt // Clock Domain Crossing checks (--cdc) - {prefix}__stats.txt // Statistics (--stats) - {prefix}__idmap.txt // Symbol demangling (--protect-ids) - -It also creates internal files that can be mostly ignored: - - {mod_prefix}_{each_verilog_module}{__n}.vpp // Pre-processed verilog - {prefix}__ver.d // Make dependencies (-MMD) - {prefix}__verFiles.dat // Timestamps for skip-identical - {prefix}{misc}.dot // Debugging graph files (--debug) - {prefix}{misc}.tree // Debugging files (--debug) - -After running Make, the C++ compiler may produce the following: - - verilated{misc}.d // Intermediate dependencies - verilated{misc}.o // Intermediate objects - {mod_prefix}{misc}.d // Intermediate dependencies - {mod_prefix}{misc}.o // Intermediate objects - {prefix} // Final executable (w/--exe argument) - {prefix}__ALL.a // Library of all Verilated objects - {prefix}__ALL.cpp // Include of all code for single compile - {prefix}{misc}.d // Intermediate dependencies - {prefix}{misc}.o // Intermediate objects - - -=head1 ENVIRONMENT - -=over 4 - -=item LD_LIBRARY_PATH - -A generic Linux/OS variable specifying what directories have shared object -(.so) files. This path should include SystemC and any other shared objects -needed at simulation runtime. - -=item MAKE - -Names the executable of the make command invoked when using the --build option. -Some operating systems may require "gmake" to this variable to launch GNU make. -If this variable is not specified, "make" is used. - -=item OBJCACHE - -Optionally specifies a caching or distribution program to place in front of -all runs of the C++ compiler. For example, "ccache". If using distcc or -icecc/icecream, they would generally be run under cache; see the -documentation for those programs. If OBJCACHE is not set, and at configure -time ccache was present, ccache will be used as a default. - -=item SYSTEMC - -Deprecated. Used only if SYSTEMC_INCLUDE or SYSTEMC_LIBDIR is not set. If -set, specifies the directory containing the SystemC distribution. If not -specified, it will come from a default optionally specified at configure -time (before Verilator was compiled). - -=item SYSTEMC_ARCH - -Deprecated. Used only if SYSTEMC_LIBDIR is not set. Specifies the -architecture name used by the SystemC kit. This is the part after the dash -in the lib-{...} directory name created by a 'make' in the SystemC -distribution. If not set, Verilator will try to intuit the proper setting, -or use the default optionally specified at configure time (before Verilator -was compiled). - -=item SYSTEMC_CXX_FLAGS - -Specifies additional flags that are required to be passed to GCC when -building the SystemC model. System 2.3.0 may need this set to "-pthread". - -=item SYSTEMC_INCLUDE - -If set, specifies the directory containing the systemc.h header file. If -not specified, it will come from a default optionally specified at -configure time (before Verilator was compiled), or computed from -SYSTEMC/include. - -=item SYSTEMC_LIBDIR - -If set, specifies the directory containing the libsystemc.a library. If not -specified, it will come from a default optionally specified at configure -time (before Verilator was compiled), or computed from -SYSTEMC/lib-SYSTEMC_ARCH. - -=item VERILATOR_BIN - -If set, specifies an alternative name of the C binary. May be -used for debugging and selecting between multiple operating system builds. - -=item VERILATOR_COVERAGE_BIN - -If set, specifies an alternative name of the C. -May be used for debugging and selecting between multiple operating system -builds. - -=item VERILATOR_GDB - -If set, the command to run when using the --gdb option, such as "ddd". If -not specified, it will use "gdb". - -=item VERILATOR_ROOT - -Specifies the directory containing the distribution kit. This is used to -find the executable, Perl library, and include files. If not specified, it -will come from a default optionally specified at configure time (before -Verilator was compiled). It should not be specified if using a pre-compiled -Verilator package as the hard-coded value should be correct. - -=back - - -=head1 CONNECTING TO C++ - -Verilator creates a I.h and I.cpp file for the top level -module, together with additional .h and .cpp files for internals. See the -examples directory in the kit for examples. - -After the model is created, there will be a I.mk file that may -be used with Make to produce a I__ALL.a file with all required -objects in it. This is then linked with the user's C++ main loop to -create the simulation executable. - -The user must write the C++ main loop of the simulation. Here is a simple -example: - - #include // Defines common routines - #include // Need std::cout - #include "Vtop.h" // From Verilating "top.v" - - Vtop *top; // Instantiation of module - - vluint64_t main_time = 0; // Current simulation time - // This is a 64-bit integer to reduce wrap over issues and - // allow modulus. This is in units of the timeprecision - // used in Verilog (or from --timescale-override) - - double sc_time_stamp() { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does - } - - int main(int argc, char** argv) { - Verilated::commandArgs(argc, argv); // Remember args - - top = new Vtop; // Create instance - - top->reset_l = 0; // Set some inputs - - while (!Verilated::gotFinish()) { - if (main_time > 10) { - top->reset_l = 1; // Deassert reset - } - if ((main_time % 10) == 1) { - top->clk = 1; // Toggle clock - } - if ((main_time % 10) == 6) { - top->clk = 0; - } - top->eval(); // Evaluate model - cout << top->out << endl; // Read a output - main_time++; // Time passes... - } - - top->final(); // Done simulating - // // (Though this example doesn't get here) - delete top; - } - -Note signals are read and written as member variables of the model. -You call the eval() method to evaluate the model. When the simulation is -complete call the final() method to execute any SystemVerilog final blocks, -and complete any assertions. See L. - - -=head1 CONNECTING TO SYSTEMC - -Verilator will convert the top level module to a SC_MODULE. This module -will plug directly into a SystemC netlist. - -The SC_MODULE gets the same pinout as the Verilog module, with the -following type conversions: Pins of a single bit become bool. Pins 2-32 -bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or -vluint64_t's depending on the --no-pins64 switch. Wider pins become sc_bv's. -(Uints simulate the fastest so are used where possible.) - -Lower modules are not pure SystemC code. This is a feature, as using the -SystemC pin interconnect scheme everywhere would reduce performance by an -order of magnitude. - - -=head1 DIRECT PROGRAMMING INTERFACE (DPI) - -Verilator supports SystemVerilog Direct Programming Interface import and -export statements. Only the SystemVerilog form ("DPI-C") is supported, not -the original Synopsys-only DPI. - -=head2 DPI Example - -In the SYSTEMC example above, if you wanted to import C++ functions into -Verilog, put in our.v: - - import "DPI-C" function int add (input int a, input int b); - - initial begin - $display("%x + %x = %x", 1, 2, add(1,2)); - endtask - -Then after Verilating, Verilator will create a file Vour__Dpi.h with the -prototype to call this function: - - extern int add(int a, int b); - -From the sc_main.cpp file (or another .cpp file passed to the Verilator -command line, or the link), you'd then: - - #include "svdpi.h" - #include "Vour__Dpi.h" - int add(int a, int b) { return a+b; } - -=head2 DPI System Task/Functions - -Verilator extends the DPI format to allow using the same scheme to -efficiently add system functions. Simply use a dollar-sign prefixed system -function name for the import, but note it must be escaped. - - export "DPI-C" function integer \$myRand; - - initial $display("myRand=%d", $myRand()); - -Going the other direction, you can export Verilog tasks so they can be -called from C++: - - export "DPI-C" task publicSetBool; - - task publicSetBool; - input bit in_bool; - var_bool = in_bool; - endtask - -Then after Verilating, Verilator will create a file Vour__Dpi.h with the -prototype to call this function: - - extern void publicSetBool(svBit in_bool); - -From the sc_main.cpp file, you'd then: - - #include "Vour__Dpi.h" - publicSetBool(value); - -Or, alternatively, call the function under the design class. This isn't -DPI compatible but is easier to read and better supports multiple designs. - - #include "Vour__Dpi.h" - Vour::publicSetBool(value); - // or top->publicSetBool(value); - -Note that if the DPI task or function accesses any register or net within the -RTL, it will require a scope to be set. This can be done using the standard -functions within svdpi.h, after the module is instantiated, but before the -task(s) and/or function(s) are called. - -For example, if the top level module is instantiated with the name "dut" and -the name references within tasks are all hierarchical (dotted) names with -respect to that top level module, then the scope could be set with - - #include "svdpi.h" - ... - svSetScope(svGetScopeFromName("TOP.dut")); - -(Remember that Verilator adds a "TOP" to the top of the module hierarchy.) - -Scope can also be set from within a DPI imported C function that has been -called from Verilog by querying the scope of that function. See the -sections on DPI Context Functions and DPI Header Isolation below and the -comments within the svdpi.h header for more information. - -=head2 DPI Imports that access signals - -If a DPI import accesses a signal through the VPI Verilator will not be -able to know what variables are accessed and may schedule the code -inappropriately. Ideally pass the values as inputs/outputs so the VPI is -not required. Alternatively a workaround is to use a non-inlined task as a -wrapper: - - logic din; - - // This DPI function will read "din" - import "DPI-C" context function void dpi_that_accesses_din(); - - always @(...) - dpi_din_args(din); - - task dpi_din_args(input din); - /* verilator no_inline_task */ - dpi_that_accesses_din(); - endtask - -=head2 DPI Display Functions - -Verilator allows writing $display like functions using this syntax: - - import "DPI-C" function void - \$my_display(input string formatted /*verilator sformat*/ ); - -The /*verilator sformat*/ indicates that this function accepts a $display -like format specifier followed by any number of arguments to satisfy the -format. - -=head2 DPI Context Functions - -Verilator supports IEEE DPI Context Functions. Context imports pass the -simulator context, including calling scope name, and filename and line -number to the C code. For example, in Verilog: - - import "DPI-C" context function int dpic_line(); - initial $display("This is line %d, again, line %d\n", `line, dpic_line()); - -This will call C++ code which may then use the svGet* functions to read -information, in this case the line number of the Verilog statement that -invoked the dpic_line function: - - int dpic_line() { - // Get a scope: svScope scope = svGetScope(); - - const char* scopenamep = svGetNameFromScope(scope); - assert(scopenamep); - - const char* filenamep = ""; - int lineno = 0; - if (svGetCallerInfo(&filenamep, &lineno)) { - printf("dpic_line called from scope %s on line %d\n", - scopenamep, lineno); - return lineno; - } else { - return 0; - } - } - -See the IEEE Standard for more information. - -=head2 DPI Header Isolation - -Verilator places the IEEE standard header files such as svdpi.h into a -separate include directory, vltstd (VeriLaTor STandarD). When compiling -most applications $VERILATOR_ROOT/include/vltstd would be in the include -path along with the normal $VERILATOR_ROOT/include. However, when -compiling Verilated models into other simulators which have their own -svdpi.h and similar standard files with different contents, the vltstd -directory should not be included to prevent picking up incompatible -definitions. - -=head2 Public Functions - -Instead of DPI exporting, there's also Verilator public functions, which -are slightly faster, but less compatible. - - -=head1 VERIFICATION PROCEDURAL INTERFACE (VPI) - -Verilator supports a very limited subset of the VPI. This subset allows -inspection, examination, value change callbacks, and depositing of values -to public signals only. - -VPI is enabled with the verilator --vpi switch. - -To access signals via the VPI, Verilator must be told exactly which signals -are to be accessed. This is done using the Verilator public pragmas -documented below. - -Verilator has an important difference from an event based simulator; signal -values that are changed by the VPI will not immediately propagate their -values, instead the top level header file's eval() method must be called. -Normally this would be part of the normal evaluation (i.e. the next clock -edge), not as part of the value change. This makes the performance of VPI -routines extremely fast compared to event based simulators, but can confuse -some test-benches that expect immediate propagation. - -Note the VPI by its specified implementation will always be much slower -than accessing the Verilator values by direct reference -(structure->module->signame), as the VPI accessors perform lookup in -functions at simulation runtime requiring at best hundreds of instructions, -while the direct references are evaluated by the compiler and result in -only a couple of instructions. - -For signal callbacks to work the main loop of the program must call -VerilatedVpi::callValueCbs(). - -=head2 VPI Example - -In the below example, we have readme marked read-only, and writeme which if -written from outside the model will have the same semantics as if it -changed on the specified clock edge. - - cat >our.v <<'EOF' - module our (input clk); - reg readme /*verilator public_flat_rd*/; - reg writeme /*verilator public_flat_rw @(posedge clk) */; - initial $finish; - endmodule - EOF - -There are many online tutorials and books on the VPI, but an example that -accesses the above signal "readme" would be: - - cat >sim_main.cpp <<'<eval(); - VerilatedVpi::callValueCbs(); // For signal callbacks - read_and_check(); - } - delete top; - return 0; - } - EOF - - -=head1 CROSS COMPILATION - -Verilator supports cross-compiling Verilated code. This is generally used -to run Verilator on a Linux system and produce C++ code that is then compiled -on Windows. - -Cross compilation involves up to three different OSes. The build system is -where you configured and compiled Verilator, the host system where you run -Verilator, and the target system where you compile the Verilated code and -run the simulation. - -Currently, Verilator requires the build and host system type to be the -same, though the target system type may be different. To support this, -./configure and make Verilator on the build system. Then, run Verilator on -the host system. Finally, the output of Verilator may be compiled on the -different target system. - -To support this, none of the files that Verilator produces will reference -any configure generated build-system specific files, such as config.h -(which is renamed in Verilator to config_build.h to reduce confusion.) The -disadvantage of this approach is that include/verilatedos.h must -self-detect the requirements of the target system, rather than using -configure. - -The target system may also require edits to the Makefiles, the simple -Makefiles produced by Verilator presume the target system is the same type -as the build system. - -=head2 CMake - -Verilator can be run using CMake, which takes care of both running -Verilator and compiling the output. There is a CMake example in the -examples/ directory. The following is a minimal CMakeLists.txt that -would build the code listed in "EXAMPLE C++ EXECUTION": - - project(cmake_example) - find_package(verilator HINTS $ENV{VERILATOR_ROOT}) - add_executable(Vour sim_main.cpp) - verilate(Vour SOURCES our.v) - -find_package will automatically find an installed copy of Verilator, or use -a local build if VERILATOR_ROOT is set. - -It is recommended to use CMake >= 3.12 and the Ninja generator, though -other combinations should work. To build with CMake, change to the folder -containing CMakeLists.txt and run: - - mkdir build - cd build - cmake -GNinja .. - ninja - -Or to build with your system default generator: - - mkdir build - cd build - cmake .. - cmake --build . - -If you're building the example you should have an executable to run: - - ./Vour - -The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and -VERILATOR_BIN to the appropriate values, and also creates a verilate() -function. verilate() will automatically create custom commands to run -Verilator and add the generated C++ sources to the target specified. - - verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name] - [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE] - [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...] - [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...]) - -Lowercase and ... should be replaced with arguments, the uppercase parts -delimit the arguments and can be passed in any order, or left out entirely -if optional. - -verilate(target ...) can be called multiple times to add other verilog -modules to an executable or library target. - -When generating Verilated SystemC sources, you should also include the -SystemC include directories and link to the SystemC libraries. - -Verilator's CMake support provides a convenience function to automatically -find and link to the SystemC library. It can be used as: - - verilator_link_systemc(target) - -where target is the name of your target. - -The search paths can be configured by setting some variables: - -- The variables SYSTEMC_INCLUDE and SYSTEMC_LIBDIR to give a direct path to -the SystemC include an library path. - -- SYSTEMC_ROOT to set the installation prefix of an installed SystemC - library. - -- SYSTEMC to set the installation prefix of an installed SystemC library - (same as above). - -- When using Accellera's SystemC with CMake support, a CMake target is -available that simplifies the above steps. This will only work if the -SystemC installation can be found by CMake. This can be configured by -setting the CMAKE_PREFIX_PATH variable during CMake configuration. - -Don't forget to set the same C++ standard for the Verilated sources as the -SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS environment -variable. - -=over 4 - -=item target - -Name of a target created by add_executable or add_library. - -=item SOURCES - -List of Verilog files to Verilate. Must have at least one file. - -=item PREFIX - -Optional. Sets the Verilator output prefix. Defaults to the name of the -first source file with a "V" prepended. Must be unique in each call to -verilate(), so this is necessary if you build a module multiple times with -different parameters. Must be a valid C++ identifier, i.e. contains no -white space and only characters A-Z, a-z, 0-9 or _. - -=item TOP_MODULE - -Optional. Sets the name of the top module. Defaults to the name of the -first file in the SOURCES array. - -=item TRACE - -Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS --trace". - -=item TRACE_FST - -Optional. Enables FST tracing if present, equivalent to "VERILATOR_ARGS --trace-fst". - -=item SYSTEMC - -Optional. Enables SystemC mode, defaults to C++ if not specified. - -=item COVERAGE - -Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS --coverage" - -=item INCLUDE_DIRS - -Optional. Sets directories that Verilator searches (same as -y). - -=item OPT_SLOW - -Optional. Set compiler flags for the slow path. You may want to reduce the -optimization level to improve compile times with large designs. - -=item OPT_FAST - -Optional. Set compiler flags for the fast path. - -=item OPT_GLOBAL - -Optional. Set compiler flags for the common runtime library used by Verilated -models. - -=item DIRECTORY - -Optional. Set the verilator output directory. It is preferable to use the -default, which will avoid collisions with other files. - -=item VERILATOR_ARGS - -Optional. Extra arguments to Verilator. Do not specify --Mdir or --prefix -here, use DIRECTORY or PREFIX. - -=back - -=head1 HIERARCHICAL VERILATION - -Large designs may take long (e.g. 10+ minutes) and huge memory (e.g. 100+GB) -to Verilate. One workaround is hierarchical Verilation, it is to Verilate -each moderate size of building blocks and finally combine the building blocks. -The building block will be called "hierarchy block" later. - -The current hierarchical Verilation is based on protect-lib. Each hierarchy -block is Verilated to protect-lib. User modules of the hierarchy blocks will see -a tiny wrapper generated by protect-lib instead of the actual design. - -=head2 Usage - -All user need to do is mark moderate size of module as hierarchy block and pass ---hierarchical option to verilator command. -There are two ways to mark a module: - - a) Write /* verilator hier_block */ metacomment in HDL code - See L for more detail. - b) add hier_block line in the configuration file. - See C in L for example. - -You don't have to take care of hierarchical blocks when compiling -Verilated C++ code. You can compile as usual. - make -C obj_dir -f Vtop_module_name.mk - -See also "Overlapping Verilation and compilation" to get executable quickly. - -=head2 Limitations - -Because hierarchy blocks are Verilated to protect-lib, they have some - limitations such as: - - The block cannot be accessed using dot (.) from upper module. - Signals in the block cannot be traced. - Modport cannot be used at the hirarchical block boundary. - -On the other hand, the following usage is supported. - - - Nested hierarchy block. A hierarchy block may instantiate other - hierarchy blocks. - - Parameterized hierarchy block. Parameters of a hierarchy block can be - overridden using #(.param_name(value)) construct. - -The simulation speed may not be as fast as flat Verilation, in which -all modules are globally scheduled. - -=head2 Overlapping Verilation and compilation - -Verilator needs to run N + 2 times in hierarchical Verilation, where N is -the number of hierarchy blocks. -1 of 2 is for the top module which refers wrappers of all other hierarchy -blocks. -The other 1 of 2 is the initial run that searches modules marked with -/*verilator hier_block*/ metacomment and creates a plan and write in -(prefix)_hier.mk. -This initial run internally invokes other N + 1 runs, so you don't have -to care about these N + 1 times of run. - -If -j option is specified, Verilation for hierarchy blocks -runs in parallel. - -If --build option is also specified, C++ compilation also runs as soon as -a hierarchy block is Verilated. C++ compilation and Verilation for -other hierarchy blocks run simultaneously. - -=head1 MULTITHREADING - -Verilator supports multithreaded simulation models. - -With --no-threads, the default, the model is not thread safe, and any use -of more than one thread calling into one or even different Verilated models -may result in unpredictable behavior. This gives the highest single thread -performance. - -With --threads 1, the generated model is single threaded, however the -support libraries are multithread safe. This allows different -instantiations of model(s) to potentially each be run under a different -thread. All threading is the responsibility of the user's C++ testbench. - -With --threads N, where N is at least 2, the generated model will be -designed to run in parallel on N threads. The thread calling eval() -provides one of those threads, and the generated model will create and -manage the other N-1 threads. It's the client's responsibility not to -oversubscribe the available CPU cores. Under CPU oversubscription, the -Verilated model should not livelock nor deadlock, however, you can expect -performance to be far worse than it would be with proper ratio of -threads and CPU cores. - -The remainder of this section describe behavior with --threads 1 or ---threads N (not --no-threads). - -VL_THREADED is defined when compiling a threaded Verilated module, causing -the Verilated support classes become threadsafe. - -The thread used for constructing a model must be the same thread that -calls eval() into the model, this is called the "eval thread". The thread -used to perform certain global operations such as saving and tracing must -be done by a "main thread". In most cases the eval thread and main thread -are the same thread (i.e. the user's top C++ testbench runs on a single -thread), but this is not required. - -The --trace-threads options can be used to produce trace dumps using multiple -threads. If --trace-threads is set without --threads, then --trace-threads will -imply --threads 1, i.e.: the support libraries will be thread safe. - -With --trace-threads 0, trace dumps are produced on the main thread. This again -gives the highest single thread performance. - -With --trace-threads N, where N is at least 1, N additional threads will be -created and managed by the trace files (e.g.: VerilatedVcdC or VerilatedFstC), -to generate the trace dump. The main thread will be released to proceed with -execution as soon as possible, though some blocking of the main thread is still -necessary while capturing the trace. Different trace formats can utilize a -various number of threads. See the --trace-threads option. - -When running a multithreaded model, the default Linux task scheduler often -works against the model, by assuming threads are short lived, and thus -often schedules threads using multiple hyperthreads within the same -physical core. For best performance use the C program to (when the -threading count fits) select unique physical cores on the same socket. The -same applies for --trace-threads as well. - -As an example, if a model was Verilated with "--threads 4", we consult - - egrep 'processor|physical id|core id' /proc/cpuinfo - -To select cores 0, 1, 2, and 3 that are all located on the same socket (0) -but different physical cores. (Also useful is "numactl --hardware", or -C but those doesn't show Hyperthreading cores.) Then we execute - - numactl -m 0 -C 0,1,2,3 -- verilated_executable_name - -This will limit memory to socket 0, and threads to cores 0, 1, 2, 3, -(presumably on socket 0) optimizing performance. Of course this must be -adjusted if you want another simulator using e.g. socket 1, or if you -Verilated with a different number of threads. To see what CPUs are -actually used, use --prof-threads. - -=head2 Multithreaded Verilog and Library Support - -$display/$stop/$finish are delayed until the end of an eval() call in order -to maintain ordering between threads. This may result in additional tasks -completing after the $stop or $finish. - -=over 4 - -If using --coverage, the coverage routines are fully thread safe. - -If using --dpi, Verilator assumes pure DPI imports are thread safe, -balancing performance versus safety. See --threads-dpi. - -If using --savable, the save/restore classes are not multithreaded and -must be called only by the eval thread. - -If using --sc, the SystemC kernel is not thread safe, therefore the eval -thread and main thread must be the same. - -If using --trace, the tracing classes must be constructed and called from -the main thread. - -If using --vpi, since SystemVerilog VPI was not architected by IEEE to be -multithreaded, Verilator requires all VPI calls are only made from the main -thread. - -=back - - -=head1 CONFIGURATION FILES - -In addition to the command line, warnings and other features may be -controlled by configuration files, typically named with the .vlt extension -(what makes it a configuration file is the `verilator_config directive). An -example: - - `verilator_config - lint_off -rule WIDTH - lint_off -rule CASEX -file "silly_vendor_code.v" - -This disables WIDTH warnings globally, and CASEX for a specific file. - -Configuration files are fed through the normal Verilog preprocessor prior to -parsing, so `ifdefs, `defines, and comments may be used as if it were normal -Verilog code. - -Note that file or line-specific configuration only applies to files read -after the configuration file. It is therefore recommended to pass the -configuration file to Verilator as the first file. - -The grammar of configuration commands is as follows: - -=over 4 - -=item `verilator_config - -Take remaining text and treat it as Verilator configuration commands. - -=item coverage_on [-file "" [-lines [ - ]]] - -=item coverage_off [-file "" [-lines [ - ]]] - -Enable/disable coverage for the specified filename (or wildcard with '*' or -'?', or all files if omitted) and range of line numbers (or all lines if -omitted). Often used to ignore an entire module for coverage analysis -purposes. - -=item lint_on [-rule ] [-file "" [-lines [ - ]]] - -=item lint_off [-rule ] [-file "" [-lines [ - ]]] - -=item lint_off [-rule ] [-file ""] [-match ""] - -Enable/disables the specified lint warning, in the specified filename (or -wildcard with '*' or '?', or all files if omitted) and range of line -numbers (or all lines if omitted). - -With lint_off using '*' will override any lint_on directives in the source, -i.e. the warning will still not be printed. - -If the -rule is omitted, all lint warnings (see list in -Wno-lint) are -enabled/disabled. This will override all later lint warning enables for -the specified region. - -If -match is set the linter warnings are matched against this (wildcard) -string and are waived in case they match and iff rule and file (with wildcard) -also match. - -In previous versions -rule was named -msg. The latter is deprecated, but -still works with a deprecation info, it may be removed in future versions. - -=item tracing_on [-file "" [-lines [ - ]]] - -=item tracing_off [-file "" [-lines [ - ]]] - -Enable/disable waveform tracing for all future signals declared in the -specified filename (or wildcard with '*' or '?', or all files if omitted) -and range of line numbers (or all lines if omitted). - -For tracing_off, instances below any module in the files/ranges specified -will also not be traced. - -=item clock_enable -module "" -var "" - -Indicate the signal is used to gate a clock, and the user takes responsibility -for insuring there are no races related to it. - -Same as /*verilator clock_enable*/, see L for -more information and an example. - -=item clocker -module "" [-task ""] -var "" - -=item clocker -module "" [-function ""] -var "" - -=item no_clocker -module "" [-task ""] -var "" - -=item no_clocker -module "" [-function ""] -var "" - -Indicate the signal is used as clock or not. This information is used by -Verilator to mark the signal as clocker and propagate the clocker attribute -automatically to derived signals. See C<--clk> for more information. - -Same as /*verilator clocker*/, see L for more -information. - -=item coverage_block_off -module "" -block "" - -=item coverage_block_off -file "" -line - -Specifies the entire begin/end block should be ignored for coverage -analysis purposes. Can either be specified as a named block or as a -filename and line number. - -Same as /*verilator coverage_block_off*/, see L for more information. - -=item full_case -file "" -lines - -=item parallel_case -file "" -lines - -Same as "//synopsys full_case" and "//synopsys parallel_case". When -these synthesis directives are discovered, Verilator will either -formally prove the directive to be true, or failing that, will insert -the appropriate code to detect failing cases at simulation runtime and -print an "Assertion failed" error message. - -=item hier_block -module "" - -Specifies that the module is a unit of hierarchical Verilation. -Note that the setting is ignored unless --hierachical option is specified. -See L for more information. - -=item inline -module "" - -Specifies the module may be inlined into any modules that use this module. -Same as /*verilator inline_module*/, and see that under L for more information. - -=item isolate_assignments -module "" [-task ""] -var "" - -=item isolate_assignments -module "" [-function ""] -var "" - -=item isolate_assignments -module "" -function "" - -Used to indicate the assignments to this signal in any blocks should be -isolated into new blocks. When there is a large combinatorial block that -is resulting in a UNOPTFLAT warning, attaching this to the signal causing -a false loop may clear up the problem. - -Same as /* verilator isolate_assignments */, see L for more information. - -=item no_inline -module "" - -Specifies the module should not be inlined into any modules that use this -module. Same as /*verilator no_inline_module*/, and see that under -L for more information. - -=item no_inline [-module ""] -task "" - -=item no_inline [-module ""] -function "" - -Specify the function or task should not be inlined into where it is -used. This may reduce the size of the final executable when a task is -used a very large number of times. For this flag to work, the task -and tasks below it must be pure; they cannot reference any variables -outside the task itself. - -Same as /*verilator no_inline_task*/, see L -for more information. - -=item public [-module ""] [-task/-function ""] - -var "" - -=item public_flat [-module ""] [-task/-function ""] - -var "" - -=item public_flat_rd [-module ""] [-task/-function ""] - -var "" - -=item public_flat_rw [-module ""] [-task/-function ""] - -var "" "@(edge)" - -Sets the variable to be public. Same as /*verilator public*/ or -/*verilator public_flat*/ etc, see those under L -for more information. - -=item sc_bv -module "" [-task ""] -var "" - -=item sc_bv -module "" [-function ""] -var "" - -Sets the port to be of sc_bv> type, instead of bool, vluint32_t or -vluint64_t. Same as /*verilator sc_bv*/, see that under L for more information. - -=item sformat [-module ""] [-task ""] -var "" - -=item sformat [-module ""] [-function ""] -var "" - -Must be applied to the final argument of type "input string" of a function or -task to indicate the function or task should pass all remaining arguments -through $sformatf. This allows creation of DPI functions with $display like -behavior. See the test_regress/t/t_dpi_display.v file for an example. - -Same as /*verilator sformat*/, see L for more -information. - -=item split_var [-module ""] [-task ""] -var "" - -=item split_var [-module ""] [-function ""] -var "" - -Break the variable into multiple pieces typically to resolve UNOPTFLAT -performance issues. Typically the variables to attach this to are -recommended by Verilator itself, see UNOPTFLAT. - -Same as /*verilator split_var*/, see L for more -information. - -=back - - -=head1 LANGUAGE STANDARD SUPPORT - -=head2 Verilog 2001 (IEEE 1364-2001) Support - -Verilator supports most Verilog 2001 language features. This includes -signed numbers, "always @*", generate statements, multidimensional arrays, -localparam, and C-style declarations inside port lists. - -=head2 Verilog 2005 (IEEE 1364-2005) Support - -Verilator supports most Verilog 2005 language features. This includes the -`begin_keywords and `end_keywords compiler directives, $clog2, and the -uwire keyword. - -=head2 SystemVerilog 2005 (IEEE 1800-2005) Support - -Verilator supports ==? and !=? operators, ++ and -- in some contexts, -$bits, $countbits, $countones, $error, $fatal, $info, $isunknown, $onehot, -$onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit, byte, -chandle, const, do-while, enum, export, final, import, int, interface, -logic, longint, modport, package, program, shortint, struct, time, typedef, -union, var, void, priority case/if, and unique case/if. - -It also supports .name and .* interconnection. - -Verilator partially supports concurrent assert and cover statements; see -the enclosed coverage tests for the syntax which is allowed. - -=head2 SystemVerilog 2012 (IEEE 1800-2012) Support - -Verilator implements a full SystemVerilog 2012 preprocessor, including -function call-like preprocessor defines, default define arguments, -`__FILE__, `__LINE__ and `undefineall. - -Verilator currently has some support for SystemVerilog synthesis -constructs. As SystemVerilog features enter common usage they are added; -please file a bug if a feature you need is missing. - -=head2 SystemVerilog 2017 (IEEE 1800-2017) Support - -Verilator supports the 2017 "for" loop constructs, and several minor -cleanups made in 1800-2017. - -=head2 Verilog AMS Support - -Verilator implements a very small subset of Verilog AMS (Verilog Analog and -Mixed-Signal Extensions) with the subset corresponding to those VMS -keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009 -languages. - -AMS parsing is enabled with "--language VAMS" or "--language 1800+VAMS". - -At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt, -string, and wreal. - -=head2 Synthesis Directive Assertion Support - -With the --assert switch, Verilator reads any "//synopsys full_case" or -"//synopsys parallel_case" directives. The same applies to any -"//ambit synthesis", "//cadence" or "//pragma" directives of the same form. - -When these synthesis directives are discovered, Verilator will either -formally prove the directive to be true, or failing that, will insert the -appropriate code to detect failing cases at simulation runtime and print an -"Assertion failed" error message. - -Verilator likewise also asserts any "unique" or "priority" SystemVerilog -keywords on case statement, as well as "unique" on if statements. -However, "priority if" is currently simply ignored. - - -=head1 LANGUAGE EXTENSIONS - -The following additional constructs are the extensions Verilator supports -on top of standard Verilog code. Using these features outside of comments -or `ifdef's may break other tools. - -=over 4 - -=item `__FILE__ - -The __FILE__ define expands to the current filename as a string, like C++'s -__FILE__. This was incorporated into to the 1800-2009 standard (but -supported by Verilator since 2006!) - -=item `__LINE__ - -The __LINE__ define expands to the current filename as a string, like C++'s -__LINE__. This was incorporated into to the 1800-2009 standard (but -supported by Verilator since 2006!) - -=item `error I - -This will report an error when encountered, like C++'s #error. - -=item $c(I, ...); - -The string will be embedded directly in the output C++ code at the point -where the surrounding Verilog code is compiled. It may either be a -standalone statement (with a trailing ; in the string), or a function that -returns up to a 32-bit number (without a trailing ;). This can be used to -call C++ functions from your Verilog code. - -String arguments will be put directly into the output C++ code. Expression -arguments will have the code to evaluate the expression inserted. Thus to -call a C++ function, $c("func(",a,")") will result in 'func(a)' in the -output C++ code. For input arguments, rather than hard-coding variable -names in the string $c("func(a)"), instead pass the variable as an -expression $c("func(",a,")"). This will allow the call to work inside -Verilog functions where the variable is flattened out, and also enable -other optimizations. - -If you will be reading or writing any Verilog variables inside the C++ -functions, the Verilog signals must be declared with /*verilator public*/. - -You may also append an arbitrary number to $c, generally the width of the -output. [signal_32_bits = $c32("...");] This allows for compatibility with -other simulators which require a differently named PLI function name for -each different output width. - -=item $display, $write, $fdisplay, $fwrite, $sformat, $swrite - -Format arguments may use C fprintf sizes after the % escape. Per the -Verilog standard, %x prints a number with the natural width, and %0x prints -a number with minimum width. Verilator extends this so %5x prints 5 digits -per the C standard (this is unspecified in Verilog, but was incorporated -into the 1800-2009). - -=item `coverage_block_off - -Specifies the entire begin/end block should be ignored for coverage -analysis. Must be inside a code block, e.g. within a begin/end pair. -Same as /* verilator coverage_block_off */ and C in -L. - -=item `systemc_header - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the output .h file's header. Must be placed as a -module item, e.g. directly inside a module/endmodule pair. Despite the name -of this macro, this also works in pure C++ code. - -=item `systemc_ctor - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the C++ class constructor. Must be placed as a -module item, e.g. directly inside a module/endmodule pair. Despite the name -of this macro, this also works in pure C++ code. - -=item `systemc_dtor - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the C++ class destructor. Must be placed as a -module item, e.g. directly inside a module/endmodule pair. Despite the name -of this macro, this also works in pure C++ code. - -=item `systemc_interface - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the C++ class interface. Must be placed as a module -item, e.g. directly inside a module/endmodule pair. Despite the name of -this macro, this also works in pure C++ code. - -=item `systemc_imp_header - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into the header of all files for this C++ class -implementation. Must be placed as a module item, e.g. directly inside a -module/endmodule pair. Despite the name of this macro, this also works in -pure C++ code. - -=item `systemc_implementation - -Take remaining text up to the next `verilog or `systemc_... mode switch and -place it verbatim into a single file of the C++ class implementation. Must -be placed as a module item, e.g. directly inside a module/endmodule -pair. Despite the name of this macro, this also works in pure C++ code. - -If you will be reading or writing any Verilog variables in the C++ -functions, the Verilog signals must be declared with /*verilator public*/. -See also the public task feature; writing an accessor may result in cleaner -code. - -=item `SYSTEMVERILOG - -The SYSTEMVERILOG, SV_COV_START and related standard defines are set by -default when --language is 1800-*. - -=item `VERILATOR - -=item `verilator - -=item `verilator3 - -The VERILATOR, verilator and verilator3 defines are set by default so you -may `ifdef around tool specific constructs. - -=item `verilator_config - -Take remaining text up to the next `verilog mode switch and treat it as -Verilator configuration commands. - -=item `verilog - -Switch back to processing Verilog code after a `systemc_... mode switch. -The Verilog code returns to the last language mode specified with -`begin_keywords, or SystemVerilog if none was specified. - -=item /*verilator clock_enable*/ - -Used after a signal declaration to indicate the signal is used to gate a -clock, and the user takes responsibility for insuring there are no races -related to it. (Typically by adding a latch, and running static timing -analysis.) For example: - - reg enable_r /*verilator clock_enable*/; - wire gated_clk = clk & enable_r; - always_ff @(posedge clk) - enable_r <= enable_early; - -The clock_enable attribute will cause the clock gate to be ignored in the -scheduling algorithm, sometimes required for correct clock behavior, and -always improving performance. It's also a good idea to enable the -IMPERFECTSCH warning, to ensure all clock enables are properly recognized. - -Same as C in configuration files, see L for more information. - -=item /*verilator clocker*/ - -=item /*verilator no_clocker*/ - -Used after a signal declaration to indicate the signal is used as clock or -not. This information is used by Verilator to mark the signal as clocker -and propagate the clocker attribute automatically to derived signals. See -C<--clk> for more information. - -Same as C and C in configuration files, see -L for more information. - -=item /*verilator coverage_block_off*/ - -Specifies the entire begin/end block should be ignored for coverage -analysis purposes. - -Same as C in configuration files, see -L for more information. - -=item /*verilator coverage_off*/ - -Specifies that following lines of code should have coverage disabled. -Often used to ignore an entire module for coverage analysis purposes. - -=item /*verilator coverage_on*/ - -Specifies that following lines of code should have coverage re-enabled (if -appropriate --coverage flags are passed) after being disabled earlier with -/*verilator coverage_off*/. - -=item /*verilator hier_block*/ - -Specifies that the module is a unit of hierarchical Verilation. -This metacomment must be between - "module module_name(...);" and "endmodule". -The module will not be inlined nor uniquified for each instance in -hierarchical Verilation. -Note that the metacomment is ignored unless --hierachical option is specified. - -See L for more information. - -=item /*verilator inline_module*/ - -Specifies the module the comment appears in may be inlined into any modules -that use this module. This is useful to speed up simulation runtime. Note -if using "--public" that signals under inlined submodules will be named -I__DOT__I as C++ does not allow "." in signal names. - -Same as C in configuration files, see L -for more information. - -=item /*verilator isolate_assignments*/ - -Used after a signal declaration to indicate the assignments to this signal -in any blocks should be isolated into new blocks. When there is a large -combinatorial block that is resulting in a UNOPTFLAT warning, attaching -this to the signal causing a false loop may clear up the problem. - -IE, with the following - - reg splitme /* verilator isolate_assignments*/; - // Note the placement of the semicolon above - always_comb begin - if (....) begin - splitme = ....; - other assignments - end - end - -Verilator will internally split the block that assigns to "splitme" into -two blocks: - -It would then internally break it into (sort of): - - // All assignments excluding those to splitme - always_comb begin - if (....) begin - other assignments - end - end - // All assignments to splitme - always_comb begin - if (....) begin - splitme = ....; - end - end - -Same as C in configuration files, see -L for more information. - -=item /*verilator lint_off I*/ - -Disable the specified warning message for any warnings following the comment. - -=item /*verilator lint_on I*/ - -Re-enable the specified warning message for any warnings following the comment. - -=item /*verilator lint_restore*/ - -After a /*verilator lint_save*/, pop the stack containing lint message -state. Often this is useful at the bottom of include files. - -=item /*verilator lint_save*/ - -Push the current state of what lint messages are turned on or turned off to -a stack. Later meta-comments may then lint_on or lint_off specific -messages, then return to the earlier message state by using /*verilator -lint_restore*/. For example: - - // verilator lint_save - // verilator lint_off SOME_WARNING - ... // code needing SOME_WARNING turned off - // verilator lint_restore - -If SOME_WARNING was on before the lint_off, it will now be restored to on, -and if it was off before the lint_off it will remain off. - -=item /*verilator no_inline_module*/ - -Specifies the module the comment appears in should not be inlined into any -modules that use this module. - -Same as C in configuration files, see L for more information. - -=item /*verilator no_inline_task*/ - -Used in a function or task variable definition section to specify the -function or task should not be inlined into where it is used. This may -reduce the size of the final executable when a task is used a very large -number of times. For this flag to work, the task and tasks below it must -be pure; they cannot reference any variables outside the task itself. - -Same as C in configuration files, see L for more information. - -=item /*verilator public*/ (parameter) - -Used after a parameter declaration to indicate the emitted C code should -have the parameter values visible. Due to C++ language restrictions, this -may only be used on 64-bit or narrower integral enumerations. - - parameter [2:0] PARAM /*verilator public*/ = 2'b0; - -=item /*verilator public*/ (typedef enum) - -Used after an enum typedef declaration to indicate the emitted C code -should have the enum values visible. Due to C++ language restrictions, this -may only be used on 64-bit or narrower integral enumerations. - - typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/; - -=item /*verilator public*/ (variable) - -Used after an input, output, register, or wire declaration to indicate the -signal should be declared so that C code may read or write the value of the -signal. This will also declare this module public, otherwise use -/*verilator public_flat*/. - -Instead of using public variables, consider instead making a DPI or public -function that accesses the variable. This is nicer as it provides an -obvious entry point that is also compatible across simulators. - -Same as C in configuration files, see L -for more information. - -=item /*verilator public*/ (task/function) - -Used inside the declaration section of a function or task declaration to -indicate the function or task should be made into a C++ function, public to -outside callers. Public tasks will be declared as a void C++ function, -public functions will get the appropriate non-void (bool, uint32_t, etc) -return type. Any input arguments will become C++ arguments to the -function. Any output arguments will become C++ reference arguments. Any -local registers/integers will become function automatic variables on the -stack. - -Wide variables over 64 bits cannot be function returns, to avoid exposing -complexities. However, wide variables can be input/outputs; they will be -passed as references to an array of 32-bit numbers. - -Generally, only the values of stored state (flops) should be written, as -the model will NOT notice changes made to variables in these functions. -(Same as when a signal is declared public.) - -You may want to use DPI exports instead, as it's compatible with other -simulators. - -Same as C in configuration files, see L -for more information. - -=item /*verilator public_flat*/ (variable) - -Used after an input, output, register, or wire declaration to indicate the -signal should be declared so that C code may read or write the value of the -signal. This will not declare this module public, which means the name of -the signal or path to it may change based upon the module inlining which -takes place. - -Same as C in configuration files, see L for more information. - -=item /*verilator public_flat_rd*/ (variable) - -Used after an input, output, register, or wire declaration to indicate the -signal should be declared public_flat (see above), but read-only. - -Same as C in configuration files, see L for more information. - -=item /*verilator public_flat_rw @() */ (variable) - -Used after an input, output, register, or wire declaration to indicate the -signal should be declared public_flat_rd (see above), and also writable, -where writes should be considered to have the timing specified by the given -sensitivity edge list. Set for all variables, ports and wires using the ---public-flat-rw switch. - -Same as C in configuration files, see L for more information. - -=item /*verilator public_module*/ - -Used after a module statement to indicate the module should not be inlined -(unless specifically requested) so that C code may access the module. -Verilator automatically sets this attribute when the module contains any -public signals or `systemc_ directives. Also set for all modules when -using the --public switch. - -Same as C in configuration files, see L -for more information. - -=item /*verilator sc_clock*/ - -Deprecated and ignored. Previously used after an input declaration to -indicate the signal should be declared in SystemC as a sc_clock instead of -a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 and -later do not require clock pins to be sc_clocks and this is no longer -needed and is ignored. - -=item /*verilator sc_bv*/ - -Used after a port declaration. It sets the port to be of sc_bv> -type, instead of bool, vluint32_t or vluint64_t. This may be useful if the -port width is parameterized and the instantiating C++ code wants to always -have a sc_bv so it can accept any width. In general you should avoid using -this attribute when not necessary as with increasing usage of sc_bv the -performance decreases significantly. - -Same as C in configuration files, see L -for more information. - -=item /*verilator sformat*/ - -Attached to the final argument of type "input string" of a function or task to -indicate the function or task should pass all remaining arguments through -$sformatf. This allows creation of DPI functions with $display like behavior. -See the test_regress/t/t_dpi_display.v file for an example. - -Same as C in configuration files, see L -for more information. - -=item /*verilator split_var*/ - -Attached to a variable or a net declaration to break the variable into -multiple pieces typically to resolve UNOPTFLAT performance issues. -Typically the variables to attach this to are recommended by Verilator -itself, see UNOPTFLAT below. - -For example, Verilator will internally convert a variable with the -metacomment such as: - - logic [7:0] x [0:1] /*verilator split_var*/; - -To: - - logic [7:0] x__BRA__0__KET__ /*verilator split_var*/; - logic [7:0] x__BRA__1__KET__ /*verilator split_var*/; - -Note that the generated packed variables retain the split_var metacomment -because they may be split into further smaller pieces according to the -access patterns. - -This only supports unpacked arrays, packed arrays, and packed structs of -integer types (reg, logic, bit, byte, int...); otherwise if a split was -requested but cannot occur a SPLITVAR warning is issued. Splitting large -arrays may slow down the Verilation speed, so use this only on variables -that require it. - -Same as C in configuration files, see L -for more information. - -=item /*verilator tag */ - -Attached after a variable or structure member to indicate opaque (to -Verilator) text that should be passed through to the XML output as a tag, -for use by downstream applications. - -=item /*verilator tracing_off*/ - -Disable waveform tracing for all future signals that are declared in this -module, or instances below this module. Often this is placed just after a -primitive's module statement, so that the entire module and instances below -it are not traced. - -=item /*verilator tracing_on*/ - -Re-enable waveform tracing for all future signals or instances that are -declared. - -=back - - -=head1 LANGUAGE LIMITATIONS - -There are some limitations and lack of features relative to the major -closed-source simulators, by intent. - -=head2 Synthesis Subset - -Verilator supports the Synthesis subset with other verification constructs -being added over time. Verilator also simulates events as Synopsys's Design -Compiler would; namely given a block of the form: - - always @(x) y = x & z; - -This will recompute y when there is even a potential for change in x or a -change in z, that is when the flops computing x or z evaluate (which is -what Design Compiler will synthesize.) A compliant simulator would only -calculate y if x changes. We recommend using always_comb to make the code -run the same everywhere. Also avoid putting $displays in combo blocks, as -they may print multiple times when not desired, even on compliant -simulators as event ordering is not specified. - -=head2 Signal Naming - -To avoid conflicts with C symbol naming, any character in a signal name -that is not alphanumeric nor a single underscore will be replaced by __0hh -where hh is the hex code of the character. To avoid conflicts with -Verilator's internal symbols, any double underscore are replaced with -___05F (5F is the hex code of an underscore.) - -=head2 Bind - -Verilator only supports "bind" to a target module name, not an instance -path. - -=head2 Class - -Verilator class support is limited but in active development. Verilator -supports members, and methods. Verilator does not support class static -members, class extend, or class parameters. - -=head2 Dotted cross-hierarchy references - -Verilator supports dotted references to variables, functions and tasks in -different modules. The portion before the dot must have a constant value; -for example a[2].b is acceptable, while a[x].b is generally not. - -References into generated and arrayed instances use the instance names -specified in the Verilog standard; arrayed instances are named -{instanceName}[{instanceNumber}] in Verilog, which becomes -{instanceName}__BRA__{instanceNumber}__KET__ inside the generated C++ code. - -=head2 Latches - -Verilator is optimized for edge sensitive (flop based) designs. It will -attempt to do the correct thing for latches, but most performance -optimizations will be disabled around the latch. - -=head2 Structures and Unions - -Presently Verilator only supports packed structs and packed unions. Rand -and randc tags on members are simply ignored. All structures and unions -are represented as a single vector, which means that generating one member -of a structure from blocking, and another from non-blocking assignments is -unsupported. - -=head2 Time - -All delays (#) are ignored, as they are in synthesis. - -=head2 Unknown states - -Verilator is mostly a two state simulator, not a four state simulator. -However, it has two features which uncover most initialization bugs -(including many that a four state simulator will miss.) - -Identity comparisons (=== or !==) are converted to standard ==/!= when neither -side is a constant. This may make the expression yield a different result -compared to a four state simulator. An === comparison to X will always be -false, so that Verilog code which checks for uninitialized logic will not fire. - -Assigning X to a variable will actually assign a constant value as -determined by the --x-assign switch. This allows runtime randomization, -thus if the value is actually used, the random value should cause -downstream errors. Integers also get randomized, even though the Verilog -2001 specification says they initialize to zero. Note however that -randomization happens at initialization time and hence during a single -simulation run, the same constant (but random) value will be used every -time the assignment is executed. - -All variables, depending on --x-initial setting, are typically randomly -initialized using a function. By running several random simulation runs -you can determine that reset is working correctly. On the first run, have the -function initialize variables to zero. On the second, have it initialize -variables to one. On the third and following runs have it initialize them -randomly. If the results match, reset works. (Note this is what the -hardware will really do.) In practice, just setting all variables to one -at startup finds most problems (since typically control signals are -active-high). - ---x-assign applies to variables explicitly initialized or assigned an -X. Uninitialized clocks are initialized to zero, while all other state -holding variables are initialized to a random value. Event driven -simulators will generally trigger an edge on a transition from X to 1 -(C) or X to 0 (C). However, by default, since clocks are -initialized to zero, Verilator will not trigger an initial negedge. Some -code (particularly for reset) may rely on X->0 triggering an edge. The ---x-initial-edge switch enables this behavior. Comparing runs with and -without this switch will find such problems. - - -=head2 Tri/Inout - -Verilator converts some simple tristate structures into two state. Pullup, -pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are -also supported. Simple comparisons with === 1'bz are also supported. - -An assignment of the form: - - inout driver; - wire driver = (enable) ? output_value : 1'bz; - -Will be converted to - - input driver; // Value being driven in from "external" drivers - output driver__en; // True if driven from this module - output driver__out; // Value being driven from this module - -External logic will be needed to combine these signals with any external -drivers. - -Tristate drivers are not supported inside functions and tasks; an inout -there will be considered a two state variable that is read and written -instead of a four state variable. - -=head2 Functions & Tasks - -All functions and tasks will be inlined (will not become functions in C.) -The only support provided is for simple statements in tasks (which may -affect global variables). - -Recursive functions and tasks are not supported. All inputs and outputs -are automatic, as if they had the Verilog 2001 "automatic" keyword -prepended. (If you don't know what this means, Verilator will do what you -probably expect -- what C does. The default behavior of Verilog is -different.) - -=head2 Generated Clocks - -Verilator attempts to deal with generated and gated clocks correctly, -however some cases cause problems in the scheduling algorithm which is -optimized for performance. The safest option is to have all clocks as -primary inputs to the model, or wires directly attached to primary inputs. -For proper behavior clock enables may also need the /*verilator -clock_enable*/ attribute. - -=head2 Gate Primitives - -The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are -directly converted to behavioral equivalents. The 3-state and MOS gate -primitives are not supported. Tables are not supported. - -=head2 Specify blocks - -All specify blocks and timing checks are ignored. All min:typ:max delays -use the typical value. - -=head2 Array Initialization - -When initializing a large array, you need to use non-delayed assignments. -Verilator will tell you when this needs to be fixed; see the BLKLOOPINIT -error for more information. - -=head2 Array Out of Bounds - -Writing a memory element that is outside the bounds specified for the array -may cause a different memory element inside the array to be written -instead. For power-of-2 sized arrays, Verilator will give a width warning -and the address. For non-power-of-2-sizes arrays, index 0 will be written. - -Reading a memory element that is outside the bounds specified for the array -will give a width warning and wrap around the power-of-2 size. For -non-power-of-2 sizes, it will return a unspecified constant of the -appropriate width. - -=head2 Assertions - -Verilator is beginning to add support for assertions. Verilator currently -only converts assertions to simple "if (...) error" statements, and -coverage statements to increment the line counters described in the -coverage section. - -Verilator does not support SEREs yet. All assertion and coverage -statements must be simple expressions that complete in one cycle. - -=head2 Encrypted Verilog - -Open source simulators like Verilator are unable to use encrypted RTL -(i.e. IEEE P1735). Talk to your IP vendor about delivering IP blocks -via Verilator's --protect-lib feature. - -=head2 Language Keyword Limitations - -This section describes specific limitations for each language keyword. - -=over 4 - -=item `__FILE__, `__LINE__, `begin_keywords, `begin_keywords, `begin_keywords, -`begin_keywords, `begin_keywords, `define, `else, `elsif, `end_keywords, -`endif, `error, `ifdef, `ifndef, `include, `line, `systemc_ctor, -`systemc_dtor, `systemc_header, `systemc_imp_header, -`systemc_implementation, `systemc_interface, `undef, `verilog - -Fully supported. - -=item always, always_comb, always_ff, always_latch, and, assign, begin, -buf, byte, case, casex, casez, default, defparam, do-while, else, end, -endcase, endfunction, endgenerate, endmodule, endspecify, endtask, final, -for, function, generate, genvar, if, initial, inout, input, int, integer, -localparam, logic, longint, macromodule, module, nand, negedge, nor, not, -or, output, parameter, posedge, reg, scalared, shortint, signed, supply0, -supply1, task, time, tri, typedef, var, vectored, while, wire, xnor, xor - -Generally supported. - -=item ++, -- operators - -Increment/decrement can only be used as standalone statements or in certain -limited cases. - -=item '{} operator - -Assignment patterns with order based, default, constant integer (array) or -member identifier (struct/union) keys are supported. Data type keys and -keys which are computed from a constant expression are not supported. - -=item `uselib - -Uselib, a vendor specific library specification method, is ignored along -with anything following it until the end of that line. - -=item cast operator - -Casting is supported only between simple scalar types, signed and unsigned, -not arrays nor structs. - -=item chandle - -Treated as a "longint"; does not yet warn about operations that are -specified as illegal on chandles. - -=item disable - -Disable statements may be used only if the block being disabled is a block -the disable statement itself is inside. This was commonly used to provide -loop break and continue functionality before SystemVerilog added the break -and continue keywords. - -=item inside - -Inside expressions may not include unpacked array traversal or $ as an -upper bound. Case inside and case matches are also unsupported. - -=item interface - -Interfaces and modports, including with generated data types are supported. -Generate blocks around modports are not supported, nor are virtual -interfaces nor unnamed interfaces. - -=item shortreal - -Short floating point (shortreal) numbers are converted to real. Most other -simulators either do not support float, or convert likewise. - -=item specify specparam - -All specify blocks and timing checks are ignored. - -=item uwire - -Verilator does not perform warning checking on uwires, it treats the uwire -keyword as if it were the normal wire keyword. - -=item $bits, $countbits, $countones, $error, $fatal, $finish, $info, -$isunknown, $onehot, $onehot0, $readmemb, $readmemh, $signed, $stime, $stop, -$time, $unsigned, $warning. - -Generally supported. - -=item $dump/$dumpports and related - -$dumpfile or $dumpports will create a VCD or FST file (which is based on -the --trace argument given when the model was Verilated). This will take -effect starting at the next eval() call. If you have multiple Verilated -designs under the same C model, then this will dump signals only from the -design containing the $dumpvars. - -$dumpvars and $dumpports module identifier is ignored; the traced instances -will always start at the top of the design. The levels argument is also -ignored, use tracing_on/tracing_off pragmas instead. - -$dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename argument -is ignored, only a single trace file may be active at once. - -$dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and -$dumplimit/$dumpportlimit are currently ignored. - -=item $exit, $finish, $stop - -The rarely used optional parameter to $finish and $stop is ignored. $exit -is aliased to $finish. - -=item $fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, -$fscanf, $fwrite, $fscanf, $sscanf - -Generally supported. - -=item $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, -$setup, $setuphold, $skew, $timeskew, $width - -All specify blocks and timing checks are ignored. - -=item $random, $urandom, $urandom_range - -Use +verilator+seed argument to set the seed if there is no $random or -$urandom optional argument to set the seed. There is one random seed per C -thread, not per module for $random, nor per object for random stability of -$urandom/$urandom_range. - -=item $readmemb, $readmemh - -Read memory commands should work properly. Note Verilator and the Verilog -specification does not include support for readmem to multi-dimensional -arrays. - -=item $test$plusargs, $value$plusargs - -Supported, but the instantiating C++/SystemC testbench must call - - Verilated::commandArgs(argc, argv); - -to register the command line before calling $test$plusargs or -$value$plusargs. - -=back - - -=head1 ERRORS AND WARNINGS - -Warnings may be disabled in three ways. First, when the warning is -printed it will include a warning code. Simply surround the offending -line with a lint_off/lint_on pair: - - // verilator lint_off UNSIGNED - if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop; - // verilator lint_on UNSIGNED - -Second, warnings may be disabled using a configuration file with a lint_off -command. This is useful when a script is suppressing warnings and the -Verilog source should not be changed. - -Warnings may also be globally disabled by invoking Verilator with the -C<-Wno-I> switch. This should be avoided, as it removes all -checking across the designs, and prevents other users from compiling your -code without knowing the magic set of disables needed to successfully -compile your design. - -=head2 Error and Warning Format - -Warnings and errors printed by Verilator always match this regular -expression: - - %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.* - -Errors and warning start with a percent sign (historical heritage from -Digital Equipment Corporation). Some errors or warning have a code -attached, with meanings described below. Some errors also have a filename, -line number and optional column number (starting at column 1 to match GCC). - -Following the error message, Verilator will typically show the user's -source code corresponding to the error, prefixed by the line number and a " -| ". Following this is typically an arrow and ~ pointing at the error on -the source line directly above. - -=head2 List of all warnings - -=over 4 - -=item ALWCOMBORDER - -Warns that an always_comb block has a variable which is set after it is -used. This may cause simulation-synthesis mismatches, as not all -simulators allow this ordering. - - always_comb begin - a = b; - b = 1; - end - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item ASSIGNIN - -Error that an assignment is being made to an input signal. This is almost -certainly a mistake, though technically legal. - - input a; - assign a = 1'b1; - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item ASSIGNDLY - -Warns that you have an assignment statement with a delayed time in front of -it, for example: - - a <= #100 b; - assign #100 a = b; - -Ignoring this warning may make Verilator simulations differ from other -simulators, however at one point this was a common style so disabled by -default as a code style warning. - -=item BLKANDNBLK - -BLKANDNBLK is an error that a variable comes from a mix of blocking and -non-blocking assignments. - -This is not illegal in SystemVerilog, but a violation of good coding -practice. Verilator reports this as an error, because ignoring this warning -may make Verilator simulations differ from other simulators. - -It is generally safe to disable this error (with a "// verilator lint_off -BLKANDNBLK" metacomment or the -Wno-BLKANDNBLK option) when one of the -assignments is inside a public task, or when the blocking and non-blocking -assignments have non-overlapping bits and structure members. - -Generally, this is caused by a register driven by both combo logic and a -flop: - - logic [1:0] foo; - always @(posedge clk) foo[0] <= ... - always_comb foo[1] = ... - -Simply use a different register for the flop: - - logic [1:0] foo; - always @(posedge clk) foo_flopped[0] <= ... - always_comb foo[0] = foo_flopped[0]; - always_comb foo[1] = ... - -Or, this may also avoid the error: - - logic [1:0] foo /*verilator split_var*/; - -=item BLKSEQ - -This indicates that a blocking assignment (=) is used in a sequential -block. Generally non-blocking/delayed assignments (<=) are used in -sequential blocks, to avoid the possibility of simulator races. It can be -reasonable to do this if the generated signal is used ONLY later in the -same block, however this style is generally discouraged as it is error -prone. - - always @(posedge clk) foo = ... - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item BLKLOOPINIT - -This indicates that the initialization of an array needs to use non-delayed -assignments. This is done in the interest of speed; if delayed assignments -were used, the simulator would have to copy large arrays every cycle. (In -smaller loops, loop unrolling allows the delayed assignment to work, though -it's a bit slower than a non-delayed assignment.) Here's an example - - always @(posedge clk) - if (~reset_l) begin - for (i=0; i<`ARRAY_SIZE; i++) begin - array[i] = 0; // Non-delayed for verilator - end - -This message is only seen on large or complicated loops because Verilator -generally unrolls small loops. You may want to try increasing ---unroll-count (and occasionally --unroll-stmts) which will raise the small -loop bar to avoid this error. - -=item BOUNDED - -This indicates that bounded queues (e.g. "var name[$ : 3]") are -unsupported. - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item BSSPACE - -Warns that a backslash is followed by a space then a newline. Likely the -intent was to have a backslash directly followed by a newline (e.g. when -making a `define) and there's accidentally white space at the end of the -line. If the space is not accidental, suggest removing the backslash in -the code as it serves no function. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASEINCOMPLETE - -Warns that inside a case statement there is a stimulus pattern for which -there is no case item specified. This is bad style, if a case is -impossible, it's better to have a "default: $stop;" or just "default: ;" so -that any design assumption violations will be discovered in simulation. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASEOVERLAP - -Warns that inside a case statement you have case values which are detected -to be overlapping. This is bad style, as moving the order of case values -will cause different behavior. Generally the values can be respecified to -not overlap. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASEWITHX - -Warns that a case statement contains a constant with a C. Verilator is -two-state so interpret such items as always false. Note a common error is -to use a C in a case or casez statement item; often what the user -instead intended is to use a casez with C. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASEX - -Warns that it is simply better style to use casez, and C in place of -C's. See -L - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item CASTCONST - -Warns that a dynamic cast ($cast) is unnecessary as the $cast will always -succeed or fail. If it will always fail, the $cast is useless. If it will -always succeed a static cast may be preferred. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. On other simulators, not fixing CASTCONST may result in -decreased performance. - -=item CDCRSTLOGIC - -With --cdc only, warns that asynchronous flop reset terms come from other -than primary inputs or flopped outputs, creating the potential for reset -glitches. - -=item CLKDATA - -Warns that clock signal is mixed used with/as data signal. The checking for -this warning is enabled only if user has explicitly marked some signal as -clocker using command line option or in-source meta comment (see C<--clk>). - -The warning can be disabled without affecting the simulation result. But it -is recommended to check the warning as this may degrade the performance of -the Verilated model. - -=item CMPCONST - -Warns that you are comparing a value in a way that will always be constant. -For example "X > 1" will always be true when X is a single bit wide. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item COLONPLUS - -Warns that a :+ is seen. Likely the intent was to use +: to select a range -of bits. If the intent was a range that is explicitly positive, suggest -adding a space, e.g. use ": +". - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item COMBDLY - -Warns that you have a delayed assignment inside of a combinatorial block. -Using delayed assignments in this way is considered bad form, and may lead -to the simulator not matching synthesis. If this message is suppressed, -Verilator, like synthesis, will convert this to a non-delayed assignment, -which may result in logic races or other nasties. See -L - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item CONTASSREG - -Error that a continuous assignment is setting a reg. According to IEEE -Verilog, but not SystemVerilog, a wire must be used as the target of -continuous assignments. - -This error is only reported when "--language 1364-1995", "--language -1364-2001", or "--language 1364-2005" is used. - -Ignoring this error will only suppress the lint check, it will simulate -correctly. - -=item DECLFILENAME - -Warns that a module or other declaration's name doesn't match the filename -with path and extension stripped that it is declared in. The filename a -modules/interfaces/programs is declared in should match the name of the -module etc. so that -y directory searching will work. This warning is -printed for only the first mismatching module in any given file, and -v -library files are ignored. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item DEFPARAM - -Warns that the "defparam" statement was deprecated in Verilog 2001 and all -designs should now be using the #(...) format to specify parameters. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item DETECTARRAY - -Error when Verilator tries to deal with a combinatorial loop that could not be -flattened, and which involves a datatype which Verilator cannot handle, such -as an unpacked struct or a large unpacked array. This typically occurs when --Wno-UNOPTFLAT has been used to override an UNOPTFLAT warning (see below). - -The solution is to break the loop, as described for UNOPTFLAT. - -=item DIDNOTCONVERGE - -Error at simulation runtime when model did not properly settle. - -Verilator sometimes has to evaluate combinatorial logic multiple times, -usually around code where a UNOPTFLAT warning was issued, but disabled. -For example: - - always_comb b = ~a; - always_comb a = b - -This code will toggle forever, and thus to prevent an infinite loop, the -executable will give the didn't converge error. - -To debug this, first review any UNOPTFLAT warnings that were ignored. -Though typically it is safe to ignore UNOPTFLAT (at a performance cost), at -the time of issuing a UNOPTFLAT Verilator did not know if the logic would -eventually converge and assumed it would. - -Next, run Verilator with --prof-cfuncs. Run make on the generated files -with "CPP_FLAGS=-DVL_DEBUG", to allow enabling simulation runtime debug -messages. Rerun the test. Now just before the convergence error you -should see additional output similar to this: - - CHANGE: filename.v:1: b - CHANGE: filename.v:2: a - -This means that signal b and signal a keep changing, inspect the code that -modifies these signals. Note if many signals are getting printed then most -likely all of them are oscillating. It may also be that e.g. "a" may be -oscillating, then "a" feeds signal "c" which then is also reported as -oscillating. - -One way DIDNOTCONVERGE may occur is flops are built out of gate primitives. -error. Verilator does not support building flops or latches out of gate -primitives, and any such code must change to use behavioral constructs -(e.g. always_ff and always_latch). - -Finally, rare, more difficult cases can be debugged like a "C" program; -either enter GDB and use its tracing facilities, or edit the generated C++ -code to add appropriate prints to see what is going on. - -=item ENDLABEL - -Warns that a label attached to a "end"-something statement does not match -the label attached to the block start. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item EOFNEWLINE - -Warns that a file does not end in a newline. POSIX defines that a line -must end in newline, as otherwise for example 'cat' of the file may produce -undesirable results. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item GENCLK - -Deprecated and no longer used as a warning. Used to indicate that the -specified signal was is generated inside the model, and also being used as -a clock. - -=item HIERBLOCK - -Warns that the top module is marked as a hierarchy block -by hier_block metacomment, which is not legal. This setting on the top module will be ignored. -=item IFDEPTH - -Warns that if/if else statements have exceeded the depth specified with ---if-depth, as they are likely to result in slow priority encoders. Statements -below unique and priority if statements are ignored. Solutions include -changing the code to a case statement, or a SystemVerilog 'unique if' or -'priority if'. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item IGNOREDRETURN - -Warns that a non-void function is being called as a task, and hence the -return value is being ignored. - -This warning is required by IEEE. The portable way to suppress this warning -(in SystemVerilog) is to use a void cast, e.g. - - void'(function_being_called_as_task()); - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item IMPERFECTSCH - -Warns that the scheduling of the model is not absolutely perfect, and some -manual code edits may result in faster performance. This warning defaults -to off, is not part of -Wall, and must be turned on explicitly before the -top module statement is processed. - -=item IMPLICIT - -Warns that a wire is being implicitly declared (it is a single bit wide -output from a sub-module.) While legal in Verilog, implicit declarations -only work for single bit wide signals (not buses), do not allow using a -signal before it is implicitly declared by an instance, and can lead to -dangling nets. A better option is the /*AUTOWIRE*/ feature of Verilog-Mode -for Emacs, available from L - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item IMPORTSTAR - -Warns that an "import I::*" statement is in $unit scope. This -causes the imported symbols to pollute the global namespace, defeating much -of the purpose of having a package. Generally "import ::*" should only be -used inside a lower scope such as a package or module. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item IMPURE - -Warns that a task or function that has been marked with /*verilator -no_inline_task*/ references variables that are not local to the task. -Verilator cannot schedule these variables correctly. - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item INCABSPATH - -Warns that an `include filename specifies an absolute path. This means the -code will not work on any other system with a different file system layout. -Instead of using absolute paths, relative paths (preferably without any -directory specified whatsoever) should be used, and +incdir used on the -command line to specify the top include source directories. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item INFINITELOOP - -Warns that a while or for statement has a condition that is always true. -and thus results in an infinite loop if the statement ever executes. - -This might be unintended behavior if the loop body contains statements that -in other simulators would make time pass, which Verilator is ignoring -due to e.g. STMTDLY warnings being disabled. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly (i.e. hang due to the infinite loop). - -=item INITIALDLY - -Warns that you have a delayed assignment inside of an initial or final -block. If this message is suppressed, Verilator will convert this to a -non-delayed assignment. See also the COMBDLY warning. - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item INSECURE - -Warns that the combination of options selected may be defeating the attempt -to protect/obscure identifiers or hide information in the model. Correct -the options provided, or inspect the output code to see if the information -exposed is acceptable. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item LATCH - -Warns that a signal is not assigned in all control paths of a combinational -always block, resulting in the inference of a latch. For intentional -latches, consider using the always_latch (SystemVerilog) keyword instead. -The warning may be disabled with a lint_off pragma around the always block. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item LITENDIAN - -Warns that a packed vector is declared with little endian bit numbering -(i.e. [0:7]). Big endian bit numbering is now the overwhelming standard, -and little numbering is now thus often due to simple oversight instead of -intent. - -Also warns that an instance is declared with little endian range -(i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE the -bits will likely be backwards from what you expect (i.e. instance [0] will -connect to signal bit [N-1] not bit [0]). - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item MODDUP - -Warns that a module has multiple definitions. Generally this indicates a -coding error, or a mistake in a library file and it's good practice to have -one module per file (and only put each file once on the command line) to -avoid these issues. For some gate level netlists duplicates are sometimes -unavoidable, and MODDUP should be disabled. - -Ignoring this warning will cause the more recent module definition to be -discarded. - -=item MULTIDRIVEN - -Warns that the specified signal comes from multiple always blocks. This is -often unsupported by synthesis tools, and is considered bad style. It will -also cause longer simulation runtimes due to reduced optimizations. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item MULTITOP - -Warns that there are multiple top level modules, that is modules not -instantiated by any other module, and both modules were put on the command -line (not in a library). Three likely cases: - -1. A single module is intended to be the top. This warning then occurs -because some low level instance is being read in, but is not really needed -as part of the design. The best solution for this situation is to ensure -that only the top module is put on the command line without any flags, and -all remaining library files are read in as libraries with -v, or are -automatically resolved by having filenames that match the module names. - -2. A single module is intended to be the top, the name of it is known, and -all other modules should be ignored if not part of the design. The best -solution is to use the --top option to specify the top module's name. All -other modules that are not part of the design will be for the most part -ignored (they must be clean in syntax and their contents will be removed as -part of the Verilog module elaboration process.) - -3. Multiple modules are intended to be design tops, e.g. when linting a -library file. As multiple modules are desired, disable the MULTITOP -warning. All input/outputs will go uniquely to each module, with any -conflicting and identical signal names being made unique by adding a prefix -based on the top module name followed by __02E (a Verilator-encoded ASCII -".'). This renaming is done even if the two modules' signals seem -identical, e.g. multiple modules with a "clk" input. - -=item NOLATCH - -Warns that no latch was detected in an always_latch block. The warning may -be disabled with a lint_off pragma around the always block, but recoding -using a regular always may be more appropriate. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item NULLPORT - -Warns that a null port was detected in the module definition port list. Null -ports are empty placeholders, i.e. either one ore more commas at the beginning -or the end of a module port list, or two or more consecutive commas in the -middle of a module port list. A null port cannot be accessed within the module, -but when instantiating the module by port order, it is treated like a regular -port and any wire connected to it is left unconnected. -This is considered a warning because this feature is rarely used, and is mostly -the result of a typing error such as a dangling comma at the end of a port list. - -=item PINCONNECTEMPTY - -Warns that an instance has a pin which is connected to .pin_name(), -e.g. not another signal, but with an explicit mention of the pin. It may -be desirable to disable PINCONNECTEMPTY, as this indicates intention to -have a no-connect. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item PINMISSING - -Warns that a module has a pin which is not mentioned in an instance. If a -pin is not missing it should still be specified on the instance declaration -with a empty connection, using "(.pin_name())". - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item PINNOCONNECT - -Warns that an instance has a pin which is not connected to another signal. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item PINNOTFOUND - -Warns that an instance port or Parameter was not found in the module being -instanciated. Please note that Verilator raises these errors also on instances -that should be disabled by generate/if/endgenerate constructs: - - module a; - localparam A=1; - generate - if (A==0) begin - b b_inst1 (.x(1'b0)); // nonexistent port - b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter - end - endgenerate - endmodule - - module b; - endmodule - -In the example above, b is instantiated with a port named x, but module b has -no such port. In the next line, b is instantiated again with -a nonexistent parameter PX. Technically, this code is incorrect because of -this, but other tools may ignore it because module b is not instantiated -due to the generate/if condition being false. - -It is possible to disable the error above using: -/* verilator lint_off PINNOTFOUND */ - -=item PKGNODECL - -Error that a package/class appears to have been referenced that has not yet -been declared. According to IEEE 1800-2017 26.3 all packages must be -declared before being used. - -=item PROCASSWIRE - -Error that a procedural assignment is setting a wire. According to IEEE, a -var/reg must be used as the target of procedural assignments. - -=item RANDC - -Warns that the 'randc' keyword is currently unsupported, and that it is -being converted to 'rand'. - -=item REALCVT - -Warns that a real number is being implicitly rounded to an integer, with -possible loss of precision. - -=item REDEFMACRO - -Warns that you have redefined the same macro with a different value, for -example: - - `define MACRO def1 - //... - `define MACRO otherdef - -The best solution is to use a different name for the second macro. If this -is not possible, add a undef to indicate the code is overriding the value: - - `define MACRO def1 - //... - `undef MACRO - `define MACRO otherdef - -=item SELRANGE - -Warns that a selection index will go out of bounds: - - wire vec[6:0]; - initial out = vec[7]; // There is no 7 - -Verilator will assume zero for this value, instead of X. Note that in some -cases this warning may be false, when a condition upstream or downstream of -the access means the access out of bounds will never execute or be used. - - wire vec[6:0]; - initial begin - seven = 7; - ... - if (seven != 7) out = vec[seven]; // Never will use vec[7] - -=item SHORTREAL - -Warns that Verilator does not support "shortreal" and they will be -automatically promoted to "real". The recommendation is to replace any -"shortreal" in the code with "real", as "shortreal" is not widely supported -across industry tools. - -Ignoring this warning may make Verilator simulations differ from other -simulators, if the increased precision of real affects your model or DPI -calls. - -=item SPLITVAR - -Warns that a variable with a C metacomment was not split. -Some possible reasons for this are: - -* The datatype of the variable is not supported for splitting. (e.g. is a -real). - -* The access pattern of the variable can not be determined -statically. (e.g. is accessed as a memory). - -* The index of the array exceeds the array size. - -* The variable is accessed from outside using dotted reference. -(e.g. top.instance0.variable0 = 1). - -* The variable is not declared in a module, but in a package or an -interface. - -* The variable is a parameter, localparam, genvar, or queue. - -* The variable is tristate or bidirectional. (e.g. inout or ref). - -=item STMTDLY - -Warns that you have a statement with a delayed time in front of it, for -example: - - #100 $finish; - -Ignoring this warning may make Verilator simulations differ from other -simulators. - -=item SYMRSVDWORD - -Warning that a symbol matches a C++ reserved word and using this as a symbol -name would result in odd C++ compiler errors. You may disable this warning, -but the symbol will be renamed by Verilator to avoid the conflict. - -=item SYNCASYNCNET - -Warns that the specified net is used in at least two different always -statements with posedge/negedges (i.e. a flop). One usage has the signal -in the sensitivity list and body, probably as an async reset, and the other -usage has the signal only in the body, probably as a sync reset. Mixing -sync and async resets is usually a mistake. The warning may be disabled -with a lint_off pragma around the net, or either flopped block. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item TASKNSVAR - -Error when a call to a task or function has an inout from that task tied to -a non-simple signal. Instead connect the task output to a temporary signal -of the appropriate width, and use that signal to set the appropriate -expression as the next statement. For example: - - task foo(inout sig); ... endtask - always @* begin - foo(bus_we_select_from[2]); // Will get TASKNSVAR error - end - -Change this to: - - reg foo_temp_out; - always @* begin - foo(foo_temp_out); - bus_we_select_from[2] = foo_temp_out; - end - -Verilator doesn't do this conversion for you, as some more complicated -cases would result in simulator mismatches. - -=item TICKCOUNT - -Warns that the number of ticks to delay a $past variable is greater than -10. At present Verilator effectively creates a flop for each delayed -signals, and as such any large counts may lead to large design size -increases. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item TIMESCALEMOD - -Warns that `timescale is used in some but not all modules. Recommend using ---timescale argument, or in front of all modules use: - - `include "timescale.vh" - -Then in that file set the timescale. - -It may be disabled similar to other warnings. Ignoring this warning may -result in a module having an unexpected timescale. - -IEEE recommends this be an error, for that behavior use --Werror-TIMESCALEMOD. - -=item UNDRIVEN - -Warns that the specified signal has no source. Verilator is fairly -liberal in the usage calculations; making a signal public, or setting only -a single array element marks the entire signal as driven. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item UNOPT - -Warns that due to some construct, optimization of the specified signal or -block is disabled. The construct should be cleaned up to improve -simulation performance. - -A less obvious case of this is when a module instantiates two submodules. -Inside submodule A, signal I is input and signal O is output. Likewise in -submodule B, signal O is an input and I is an output. A loop exists and a -UNOPT warning will result if AI & AO both come from and go to combinatorial -blocks in both submodules, even if they are unrelated always blocks. This -affects performance because Verilator would have to evaluate each submodule -multiple times to stabilize the signals crossing between the modules. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item UNOPTFLAT - -Warns that due to some construct, optimization of the specified signal is -disabled. The signal reported includes a complete scope to the signal; it -may be only one particular usage of a multiply instantiated block. The -construct should be cleaned up to improve simulation performance; two times -better performance may be possible by fixing these warnings. - -Unlike the UNOPT warning, this occurs after flattening the netlist, and -indicates a more basic problem, as the less obvious case described under -UNOPT does not apply. - -Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by -synthesis which analyzes interconnection per-bit, but is circular to -simulation which analyzes per-bus: - - wire [2:0] x = {x[1:0], shift_in}; - -This statement needs to be evaluated multiple times, as a change in -"shift_in" requires "x" to be computed 3 times before it becomes stable. -This is because a change in "x" requires "x" itself to change value, which -causes the warning. - -For significantly better performance, split this into 2 separate signals: - - wire [2:0] xout = {x[1:0], shift_in}; - -and change all receiving logic to instead receive "xout". Alternatively, -change it to - - wire [2:0] x = {xin[1:0], shift_in}; - -and change all driving logic to instead drive "xin". - -With this change this assignment needs to be evaluated only once. These -sort of changes may also speed up your traditional event driven simulator, -as it will result in fewer events per cycle. - -The most complicated UNOPTFLAT path we've seen was due to low bits of a bus -being generated from an always statement that consumed high bits of the -same bus processed by another series of always blocks. The fix is the -same; split it into two separate signals generated from each block. - -Occasionally UNOPTFLAT may be indicated when there is a true circulation. -e.g. if trying to implement a flop or latch using individual gate -primitives. If UNOPTFLAT is suppressed the code may get a DIDNOTCONVERGE -error. Verilator does not support building flops or latches out of gate -primitives, and any such code must change to use behavioral constructs -(e.g. always_ff and always_latch). - -Another way to resolve this warning is to add a C metacomment -described above. This will cause the variable to be split internally, -potentially resolving the conflict. If you run with --report-unoptflat -Verilator will suggest possible candidates for C. - -The UNOPTFLAT warning may also be due to clock enables, identified from the -reported path going through a clock gating instance. To fix these, use the -clock_enable meta comment described above. - -The UNOPTFLAT warning may also occur where outputs from a block of logic -are independent, but occur in the same always block. To fix this, use the -isolate_assignments meta comment described above. - -To assist in resolving UNOPTFLAT, the option C<--report-unoptflat> can be -used, which will provide suggestions for variables that can be split up, -and a graph of all the nodes connected in the loop. See the L -section for more details. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item UNOPTTHREADS - -Warns that the thread scheduler was unable to partition the design to fill -the requested number of threads. - -One workaround is to request fewer threads with C<--threads>. - -Another possible workaround is to allow more MTasks in the simulation -runtime, by increasing the value of --threads-max-mtasks. More MTasks will -result in more communication and synchronization overhead at simulation -runtime; the scheduler attempts to minimize the number of MTasks for this -reason. - -Ignoring this warning will only slow simulations, it will simulate -correctly. - -=item UNPACKED - -Warns that unpacked structs and unions are not supported. - -Ignoring this warning will make Verilator treat the structure as packed, -which may make Verilator simulations differ from other simulators. This -downgrading may also result what would normally be a legal unpacked -struct/array inside an unpacked struct/array becoming an illegal unpacked -struct/array inside a packed struct/array. - -=item UNSIGNED - -Warns that you are comparing a unsigned value in a way that implies it is -signed, for example "X < 0" will always be false when X is unsigned. - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item UNSUPPORTED - -UNSUPPORTED is an error that the construct might be legal according to IEEE -but is not currently supported. - -This error may be ignored with --bbox-unsup, however this will make the -design simulate incorrectly; see the details under --bbox-unsup. - -=item UNUSED - -Warns that the specified signal or parameter is never used/consumed. -Verilator is fairly liberal in the usage calculations; making a signal -public, a signal matching --unused-regexp ("*unused*") or accessing only a -single array element marks the entire signal as used. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -A recommended style for unused nets is to put at the bottom of a file code -similar to the following: - - wire _unused_ok = &{1'b0, - sig_not_used_a, - sig_not_used_yet_b, // To be fixed - 1'b0}; - -The reduction AND and constant zeros mean the net will always be zero, so -won't use simulation runtime. The redundant leading and trailing zeros avoid -syntax errors if there are no signals between them. The magic name -"unused" (-unused-regexp) is recognized by Verilator and suppresses -warnings; if using other lint tools, either teach it to the tool to ignore -signals with "unused" in the name, or put the appropriate lint_off around the -wire. Having unused signals in one place makes it easy to find what is unused, -and reduces the number of lint_off pragmas, reducing bugs. - -=item USERINFO, USERWARN, USERERROR, USERFATAL - -A SystemVerilog elaboration-time assertion print was executed. - -=item VARHIDDEN - -Warns that a task, function, or begin/end block is declaring a variable by -the same name as a variable in the upper level module or begin/end block -(thus hiding the upper variable from being able to be used.) Rename the -variable to avoid confusion when reading the code. - -Disabled by default as this is a code style warning; it will simulate -correctly. - -=item WIDTH - -Warns that based on width rules of Verilog, two operands have different -widths. Verilator generally can intuit the common usages of widths, and -you shouldn't need to disable this message like you do with most lint -programs. Generally other than simple mistakes, you have two solutions: - -If it's a constant 0 that's 32 bits or less, simply leave it -unwidthed. Verilator considers zero to be any width needed. - -Concatenate leading zeros when doing arithmetic. In the statement - - wire [5:0] plus_one = from[5:0] + 6'd1 + carry[0]; - -The best fix, which clarifies intent and will also make all tools happy is: - - wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0, carry[0]}; - -Ignoring this warning will only suppress the lint check, it will simulate -correctly. - -=item WIDTHCONCAT - -Warns that based on width rules of Verilog, a concatenate or replication -has an indeterminate width. In most cases this violates the Verilog rule -that widths inside concatenates and replicates must be sized, and should be -fixed in the code. - - wire [63:0] concat = {1, 2}; - -An example where this is technically legal (though still bad form) is: - - parameter PAR = 1; - wire [63:0] concat = {PAR, PAR}; - -The correct fix is to either size the 1 ("32'h1"), or add the width to the -parameter definition ("parameter [31:0]"), or add the width to the -parameter usage ("{PAR[31:0],PAR[31:0]}". - -=back - -The following describes the less obvious errors: - -=over 4 - -=item Internal Error - -This error should never occur first, though may occur if earlier warnings -or error messages have corrupted the program. If there are no other -warnings or errors, submit a bug report. - -=item Unsupported: .... - -This error indicates that you are using a Verilog language construct -that is not yet supported in Verilator. See the Limitations chapter. - -=back - - -=head1 DEPRECATIONS - -The following deprecated items are scheduled for future removal: - -=over 4 - -=item C++11 compiler support - -Verilator currently requires C++11 or newer compilers. Verilator will -require C++14 or newer compilers for both compiling Verilator and compiling -Verilated models no sooner than January 2022. - -=item --no-relative-cfuncs - -The --no-relative-cfuncs option is not be required by any C++11 compliant -compiler and is planned for removal no sooner than July 2021. - -=item --inhibit-sim - -The --inhibit-sim option is planned for removal no sooner than July 2021. - -=item Configuration File -msg - -The -msg argument to lint_off has been replaced with -rule. -msg is -planned for removal no sooner than January 2021. - -=item XML locations - -The XML C attribute has been replaced with C. C is planned -for removal no sooner than January 2021. - -=back - - -=head1 FAQ/FREQUENTLY ASKED QUESTIONS - -=over 4 - -=item Can I contribute? - -Please contribute! Just submit a pull request, or raise an issue to discuss -if looking for something to help on. For more information see our -contributor agreement. - -=item How widely is Verilator used? - -Verilator is used by many of the largest silicon design companies, and all the -way down to college projects. Verilator is one of the "big 4" simulators, -meaning one of the 4 main SystemVerilog simulators available, namely the -commercial products Synopsys VCS (tm), Mentor Questa/ModelSim (tm), Cadence -Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. The -three commercial offerings are often collectively called the "big 3" -simulators. - -=item Does Verilator run under Windows? - -Yes, using Cygwin. Verilated output also compiles under Microsoft Visual -C++, but this is not tested every release. - -=item Can you provide binaries? - -You can install Verilator via the system package manager (apt, yum, etc.) on -many Linux distributions, including Debian, Ubuntu, SuSE, Fedora, and others. -These packages are provided by the Linux distributions and generally will lag -the version of the mainline Verilator repository. If no binary package is -available for your distribution, how about you set one up? Please contact the -authors for assistance. - -=item How can it be faster than (name-a-big-3-closed-source-simulator)? - -Generally, the implied part of the question is "... with all of the -manpower they can put into developing it." - -Most simulators have to be compliant with the complete IEEE 1364 (Verilog) and -IEEE 1800 (SystemVerilog) standards, meaning they have to be event driven. -This prevents them from being able to reorder blocks and make netlist-style -optimizations, which are where most of the gains come from. - -You should not be scared by non-compliance. Your synthesis tool isn't -compliant with the whole standard to start with, so your simulator need not be -either. Verilator is closer to the synthesis interpretation, so this is a good -thing for getting working silicon. - -=item Will Verilator output remain under my own license? - -Yes, it's just like using GCC on your programs; this is why Verilator uses -the "GNU *Lesser* Public License Version 3" instead of the more typical -"GNU Public License". See the licenses for details, but in brief, if you -change Verilator itself or the header files Verilator includes, you must -make the source code available under the GNU Lesser Public License. -However, Verilator output (the Verilated code) only "include"s the licensed -files, and so you are NOT required to release any output from Verilator. - -You also have the option of using the Perl Artistic License, which again -does not require you to release your Verilog or generated code, and also -allows you to modify Verilator for internal use without distributing the -modified version. But please contribute back to the community! - -One limit is that you cannot under either license release a commercial -Verilog simulation product incorporating Verilator without making the -source code available. - -As is standard with Open Source, contributions back to Verilator will be -placed under the Verilator copyright and LGPL/Artistic license. Small test -cases will be released into the public domain so they can be used anywhere, -and large tests under the LGPL/Artistic, unless requested otherwise. - -=item Why is running Verilator (to create a model) so slow? - -Verilator needs more memory than the resulting simulator will require, as -Verilator internally creates all of the state of the resulting generated -simulator in order to optimize it. If it takes more than a few minutes or -so (and you're not using --debug since debug mode is disk bound), see if your -machine is paging; most likely you need to run it on a machine with more -memory. Very large designs are known to have topped 16GB resident set size. - -=item How do I generate waveforms (traces) in C++? - -See the next question for tracing in SystemC mode. - -A. Add the --trace switch to Verilator, and in your top level C code, call -Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to -enable traces, same as with any Verilog simulator. See -C. - -B. Or, for finer-grained control, or C++ files with multiple Verilated -modules you may also create the trace purely from C++. Create a -VerilatedVcdC object, and in your main loop call "trace_object->dump(time)" -every time step, and finally call "trace_object->close()". You also need -to compile verilated_vcd_c.cpp and add it to your link, preferably by -adding the dependencies in $(VK_GLOBAL_OBJS) to your Makefile's link rule. -This is done for you if using the Verilator --exe flag. Note you can also -call ->trace on multiple Verilated objects with the same trace file if you -want all data to land in the same output file. - - #include "verilated_vcd_c.h" - ... - int main(int argc, char** argv, char** env) { - ... - Verilated::traceEverOn(true); - VerilatedVcdC* tfp = new VerilatedVcdC; - topp->trace(tfp, 99); // Trace 99 levels of hierarchy - tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); - ... - while (vl_time_stamp64() < sim_time && !Verilated::gotFinish()) { - main_time += #; - tfp->dump(main_time); - } - tfp->close(); - } - -=item How do I generate waveforms (traces) in SystemC? - -A. Add the --trace switch to Verilator, and in your top level sc_main, call -Verilated::traceEverOn(true). Then you may use $dumpfile and $dumpvars to -enable traces, same as with any Verilog simulator, see the non-SystemC -example in C. This will trace only the module -containing the $dumpvar. - -B. Or, you may create a trace purely from SystemC, which may trace all -Verilated designs in the SystemC model. Create a VerilatedVcdSc object as -you would create a normal SystemC trace file. For an example, see the call -to VerilatedVcdSc in the examples/make_tracing_sc/sc_main.cpp file of the -distribution, and below. - -Alternatively you may use the C++ trace mechanism described in the previous -question, note the timescale and timeprecision will be inherited from your -SystemC settings. - -You also need to compile verilated_vcd_sc.cpp and verilated_vcd_c.cpp and -add them to your link, preferably by adding the dependencies in -$(VK_GLOBAL_OBJS) to your Makefile's link rule. This is done for you if -using the Verilator --exe flag. - -Note you can also call ->trace on multiple Verilated objects with the same -trace file if you want all data to land in the same output file. - -When using SystemC 2.3, the SystemC library must have been built with the -experimental simulation phase callback based tracing disabled. This is -disabled by default when building SystemC with its configure based build -system, but when building SystemC with CMake, you must pass --DENABLE_PHASE_CALLBACKS_TRACING=OFF to disable this feature. - - #include "verilated_vcd_sc.h" - ... - int main(int argc, char** argv, char** env) { - ... - Verilated::traceEverOn(true); - VerilatedVcdSc* tfp = new VerilatedVcdSc; - topp->trace(tfp, 99); // Trace 99 levels of hierarchy - tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); - ... - sc_start(1); - ... - tfp->close(); - } - -=item How do I generate FST waveforms (traces) in C++? - -FST is a trace file format developed by GTKWave. Verilator provides basic FST -support. To dump traces in FST format, add the --trace-fst switch to Verilator -and either A. use $dumpfile/$dumpvars in Verilog as described in the VCD -example above, or B. in C++ change the include described in the VCD example -above: - - #include "verilated_fst_c.h" - VerilatedFstC* tfp = new VerilatedFstC; - -Note that currently supporting both FST and VCD in a single simulation is -impossible, but such requirement should be rare. You can however ifdef -around the trace format in your C++ main loop, and select VCD or FST at -build time, should you require. - -=item How do I generate FST waveforms (aka dumps or traces) in SystemC? - -FST is a trace file format developed by GTKWave. Verilator provides basic FST -support. To dump traces in FST format, add the --trace-fst switch to Verilator -and either A. use $dumpfile/$dumpvars in Verilog as described in the FST -example above, or B. in C++ change the include described in the FST example -above: - - #include "verilated_fst_sc.h" - VerilatedFstSc* tfp = new VerilatedFstSc; - -Note that currently supporting both FST and VCD in a single simulation is -impossible, but such requirement should be rare. You can however ifdef -around the trace format in your C++ main loop, and select VCD or FST at -build time, should you require. - -=item How do I view waveforms (aka dumps or traces)? - -Verilator creates standard VCD (Value Change Dump) and FST files. VCD files -are viewable with the open source GTKWave (recommended) or Dinotrace (legacy) -programs, or any of the many closed-source offerings; FST is supported only by -GTKWave. - -=item How do I reduce the size of large waveform (trace) files? - -First, instead of calling VerilatedVcdC->open at the beginning of time, -delay calling it until the time stamp where you want tracing to begin. -Likewise you can also call VerilatedVcdC->open before the end of time -(perhaps a short period after you detect a verification error). - -Next, add /*verilator tracing_off*/ to any very low level modules you never -want to trace (such as perhaps library cells). Finally, use the ---trace-depth option to limit the depth of tracing, for example ---trace-depth 1 to see only the top level signals. - -Also be sure you write your trace files to a local solid-state drive, -instead of to a network drive. Network drives are generally far slower. - -You can also consider using FST tracing instead of VCD. FST dumps are a -fraction of the size of the equivalent VCD. FST tracing can be slower than -VCD tracing, but it might be the only option if the VCD file size is -prohibitively large. - -=item How do I do coverage analysis? - -Verilator supports both block (line) coverage and user inserted functional -coverage. - -First, run verilator with the --coverage option. If you are using your own -makefile, compile the model with the GCC flag -DVM_COVERAGE (if using -the makefile provided by Verilator, it will do this for you). - -At the end of your test, call VerilatedCov::write passing the name of the -coverage data file (typically "logs/coverage.dat"). - -Run each of your tests in different directories. Each test will create a -logs/coverage.dat file. - -After running all of your tests, execute the verilator_coverage tool. The -verilator_coverage tool reads the logs/coverage.dat file(s), and creates an -annotated source code listing showing code coverage details. - -For an example, after running 'make test' in the Verilator distribution, -see the examples/make_tracing_c/logs directory. Grep for lines starting -with '%' to see what lines Verilator believes need more coverage. - -Info files can be written by verilator_coverage for import to C. -This enables use of C for HTML reports and importing reports to -sites such as L. - -=item Where is the translate_off command? (How do I ignore a construct?) - -Translate on/off pragmas are generally a bad idea, as it's easy to have -mismatched pairs, and you can't see what another tool sees by just -preprocessing the code. Instead, use the preprocessor; Verilator defines -the "VERILATOR" define for you, so just wrap the code in an ifndef region: - - `ifndef VERILATOR - Something_Verilator_Dislikes; - `endif - -Most synthesis tools similarly define SYNTHESIS for you. - -=item Why do I get "unexpected C" or "unexpected C" errors? - -The words C, C, C, C, and others are reserved keywords -in SystemVerilog. Older Verilog code might use these as identifiers. You -should change your code to not use them to ensure it works with newer -tools. Alternatively, surround them by the Verilog 2005/SystemVerilog -begin_keywords pragma to indicate Verilog 2001 code. - - `begin_keywords "1364-2001" - integer bit; initial bit = 1; - `end_keywords - -If you want the whole design to be parsed as Verilog 2001, please see the -C<--default-language> option. - -=item How do I prevent my assertions from firing during reset? - -Call Verilated::assertOn(false) before you first call the model, then turn -it back on after reset. It defaults to true. When false, all assertions -controlled by --assert are disabled. - -=item Why do I get "undefined reference to `sc_time_stamp()'"? - -In 4.200 and later, using the timeInc function is recommended instead. See -the "CONNECTING TO C++" examples. Some linkers (MSVC++) still require -sc_time_stamp() to be defined, either define this with ("double -sc_time_stamp() { return 0; }") or compile the Verilated code with --DVL_TIME_CONTEXT. - -Prior to Verilator 4.200, the sc_time_stamp function needs to be defined in -C++ (non SystemC) to return the current simulation time. - -=item Why do I get "undefined reference to `VL_RAND_RESET_I' or `Verilated::...'"? - -You need to link your compiled Verilated code against the verilated.cpp -file found in the include directory of the Verilator kit. This is one -target in the $(VK_GLOBAL_OBJS) make variable, which should be part of your -Makefile's link rule. If you use --exe, this is done for you. - -=item Is the PLI supported? - -Only somewhat. More specifically, the common PLI-ish calls $display, -$finish, $stop, $time, $write are converted to C++ equivalents. You can -also use the "import DPI" SystemVerilog feature to call C code (see the -chapter above). There is also limited VPI access to public signals. - -If you want something more complex, since Verilator emits standard C++ -code, you can simply write your own C++ routines that can access and modify -signal values without needing any PLI interface code, and call it with -$c("{any_c++_statement}"). - -=item How do I make a Verilog module that contain a C++ object? - -You need to add the object to the structure that Verilator creates, then -use $c to call a method inside your object. The -test_regress/t/t_extend_class files show an example of how to do this. - -=item How do I get faster build times? - -When running make pass the make variable VM_PARALLEL_BUILDS=1 so that -builds occur in parallel. Note this is now set by default if an output -file was large enough to be split due to the --output-split option. - -Verilator emits any infrequently executed "cold" routines into separate -__Slow.cpp files. This can accelerate compilation as optimization can be -disabled on these routines. See the OPT_FAST and OPT_SLOW make variables -and the BENCHMARKING & OPTIMIZATION section of the manual. - -Use a recent compiler. Newer compilers tend to be faster. - -Compile in parallel on many machines and use caching; see the web for the -ccache, distcc and icecream packages. ccache will skip GCC runs between -identical source builds, even across different users. If ccache was -installed when Verilator was built it is used, or see OBJCACHE environment -variable to override this. Also see the --output-split option. - -To reduce the compile time of classes that use a Verilated module (e.g. a -top CPP file) you may wish to add /*verilator no_inline_module*/ to your -top level module. This will decrease the amount of code in the model's -Verilated class, improving compile times of any instantiating top level C++ -code, at a relatively small cost of execution performance. - -=item Why do so many files need to recompile when I add a signal? - -Adding a new signal requires the symbol table to be recompiled. Verilator -uses one large symbol table, as that results in 2-3 less assembly -instructions for each signal access. This makes the execution time 10-15% -faster, but can result in more compilations when something changes. - -=item How do I access Verilog functions/tasks in C? - -Use the SystemVerilog Direct Programming Interface. You write a Verilog -function or task with input/outputs that match what you want to call in -with C. Then mark that function as a DPI export function. See the DPI -chapter in the IEEE Standard. - -=item How do I access C++ functions/tasks in Verilog? - -Use the SystemVerilog Direct Programming Interface. You write a Verilog -function or task with input/outputs that match what you want to call in -with C. Then mark that function as a DPI import function. See the DPI -chapter in the IEEE Standard. - -=item How do I access signals in C? - -The best thing to do is to make a SystemVerilog "export DPI" task or function -that accesses that signal, as described in the DPI chapter in the manual -and DPI tutorials on the web. This will allow Verilator to better optimize -the model and should be portable across simulators. - -If you really want raw access to the signals, declare the signals you will -be accessing with a /*verilator public*/ comment before the closing -semicolon. Then scope into the C++ class to read the value of the signal, -as you would any other member variable. - -Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t), -16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or -64-bit unsigned long longs (uint64_t) that fits the width of the signal. -Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for -1 to 64 bits, and the compiler will properly up-convert smaller entities. -Note even signed ports are declared as unsigned; you must sign extend -yourself to the appropriate signal width. - -Signals wider than 64 bits are stored as an array of 32-bit uint32_t's. -Thus to read bits 31:0, access signal[0], and for bits 63:32, access -signal[1]. Unused bits (for example bit numbers 65-96 of a 65-bit vector) -will always be zero. If you change the value you must make sure to pack -zeros in the unused bits or core-dumps may result, because Verilator strips -array bound checks where it believes them to be unnecessary to improve -performance. - -In the SYSTEMC example above, if you had in our.v: - - input clk /*verilator public*/; - // Note the placement of the semicolon above - -From the sc_main.cpp file, you'd then: - - #include "Vour.h" - #include "Vour_our.h" - cout << "clock is " << top->our->clk << endl; - -In this example, clk is a bool you can read or set as any other variable. -The value of normal signals may be set, though clocks shouldn't be changed -by your code or you'll get strange results. - -=item Should a module be in Verilog or SystemC? - -Sometimes there is a block that just interconnects instances, and have a -choice as to if you write it in Verilog or SystemC. Everything else being -equal, best performance is when Verilator sees all of the design. So, look -at the hierarchy of your design, labeling instances as to if they are -SystemC or Verilog. Then: - -A module with only SystemC instances below must be SystemC. - -A module with a mix of Verilog and SystemC instances below must be -SystemC. (As Verilator cannot connect to lower-level SystemC instances.) - -A module with only Verilog instances below can be either, but for best -performance should be Verilog. (The exception is if you have a design that -is instantiated many times; in this case Verilating one of the lower -modules and instantiating that Verilated instances multiple times into a -SystemC module *may* be faster.) - -=back - - -=head1 BUGS - -First, check the L section. - -Next, try the --debug switch. This will enable additional internal -assertions, and may help identify the problem. - -Finally, reduce your code to the smallest possible routine that exhibits -the bug. Even better, create a test in the test_regress/t directory, as -follows: - - cd test_regress - cp -p t/t_EXAMPLE.pl t/t_BUG.pl - cp -p t/t_EXAMPLE.v t/t_BUG.v - -There are many hints on how to write a good test in the driver.pl -documentation which can be seen by running: - - cd $VERILATOR_ROOT # Need the original distribution kit - test_regress/driver.pl --help - -Edit t/t_BUG.pl to suit your example; you can do anything you want in the -Verilog code there; just make sure it retains the single clk input and no -outputs. Now, the following should fail: - - cd $VERILATOR_ROOT # Need the original distribution kit - cd test_regress - t/t_BUG.pl # Run on Verilator - t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator - t/t_BUG.pl --vcs # Run on VCS simulator - t/t_BUG.pl --nc|--iv|--ghdl # Likewise on other simulators - -The test driver accepts a number of options, many of which mirror the main -Verilator option. For example the previous test could have been run with -debugging enabled. The full set of test options can be seen by running -driver.pl --help as shown above. - -Finally, report the bug using the bug tracker at -L. The bug will become publicly visible; if -this is unacceptable, mail the bug report to C. - - -=head1 HISTORY - -Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group -at Digital Equipment Corporation. The Verilog code that was converted -to C was then merged with a C based CPU model of the Alpha processor -and simulated in a C based environment called CCLI. - -In 1995 Verilator started being used also for Multimedia and Network -Processor development inside Digital. Duane Galbi took over active -development of Verilator, and added several performance enhancements. -CCLI was still being used as the shell. - -In 1998, through the efforts of existing DECies, mainly Duane Galbi, -Digital graciously agreed to release the source code. (Subject to the -code not being resold, which is compatible with the GNU Public -License.) - -In 2001, Wilson Snyder took the kit, and added a SystemC mode, and -called it Verilator2. This was the first packaged public release. - -In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from -scratch in C++. This added many optimizations, yielding about a 2-5x -performance gain. - -In 2009, major SystemVerilog and DPI language support was added. - -In 2018, Verilator 4.000 was released with multithreaded support. - -Currently, various language features and performance enhancements are added -as the need arises. Verilator is now about 3x faster than in 2002, and is -faster than most (if not every) other simulator. - - -=head1 AUTHORS - -When possible, please instead report bugs to L. - -Wilson Snyder - -Major concepts by Paul Wasson, Duane Galbi, John Coiner and Jie Xu. - - -=head1 CONTRIBUTORS - -Many people have provided ideas and other assistance with Verilator. - -Verilator is receiving major development support from the CHIPS Alliance. - -Previous major corporate sponsors of Verilator, by providing significant -contributions of time or funds included include Atmel Corporation, Cavium -Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., -Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune -Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc., -and SiCortex Inc. - -The people who have contributed major functionality are Byron Bradley, -Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd -Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, and Wilson Snyder. -Major testers included Jeff Dutton, Jonathon Donaldson, Ralf Karge, David -Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van -Cauwenberghe, Gene Weber, and Clifford Wolf. - -Some of the people who have provided ideas, and feedback for Verilator -include: David Addison, Nikana Anastasiadis, Vasu Arasanipalai, Jens Arm, -Tariq B. Ahmad, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew -Barr, Geoff Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael -Berman, Jean Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof -Bieganski, David Binderman, Piotr Binkowski, Johan Bjork, David Black, -Tymoteusz Blazejczyk, Daniel Bone, Morten Borup Petersen, Gregg Bouchard, -Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Charlie -Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, -Tony Bybell, Iru Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal -Casey, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark, -Ryan Clarke, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean -Cross, George Cuan, Joe DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh -Das, Maarten De Braekeleer, Bernard Deadman, Alberto Del Rio, John Demme, -Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny -Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Sebastian Dressler, -Alex Duller, Jeff Dutton, Tomas Dzetkulic, Richard E George, Edgar -E. Iglesias, Usuario Eda, Charles Eddleston, Chandan Egbert, Jan Egil Ruud, -Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Charles Eric -LaForest, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein, -Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner, -Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl, -Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Andrew -Goessling, Amir Gonnen, Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner, -Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil -Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto, -Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry, Stephen -Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki -Honda, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath, Jae -Hossell, Kuoping Hsu, Alan Hunter, James Hutchinson, Anderson Ignacio da -Silva, Jamie Iles, Thomas J Whatson, Ben Jackson, Mark Jackson Pulver, -Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong, Iztok -Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike -Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, -Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf -Karge, Dan Katz, Sol Katzman, Ian Kennedy, Michael Killough, Jonathan -Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot -Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, -Will Korteland, Wojciech Koszek, Varun Koyyalagunta, Markus Krause, David -Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok, Ed Lander, Steve -Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor -Lesik, John Li, Eivind Liland, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul -Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan -Lussier, Fred Ma, Duraid Madina, Odd Magne Reitan, Affe Mao, Julien -Margetts, Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Yves -Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot Mednick, -Wim Michiels, Miodrag Milanovic, Peter Monsson, Sean Moore, Dennis -Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris -Nalbantis, Peter Nelson, Bob Newgard, Paul Nitza, Yossi Nivin, Pete Nixon, -Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz, -Aleksander Osman, Don Owen, James Pallister, Vassilis Papaefstathiou, Brad -Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Cody Piersall, -Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter, -Niranjan Prabhu, Usha Priyadharshini, Prateek Puri, Marshal Qiao, Nandu -Raj, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Frederic -Requin, Dustin Richmond, Samuel Riedel, Eric Rippey, Oleg Rodionov, Ludwig -Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Denis -Rystsov, John Sanguinetti, Galen Seitz, Joseph Shaker, Salman Sheikh, Yu -Sheng Lin, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan -Shupei, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim -Snyder, Wilson Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, -Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson, -Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki, -Howard Su, Emerson Suguimoto, Gene Sullivan, Wai Sum Mong, Qingyao Sun, -Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Thierry Tambe, -Drew Taussig, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede, -Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, -Viktor Tomov, Steve Tong, Alex Torregrosa, Michael Tresidder, David Turner, -Neil Turton, Cong Van Nguyen, Hans Van Antwerpen, Jan Van Winkel, Sebastien -Van Cauwenberghe, Laurens van Dam, Leendert van Doorn, Srini Vemuri, Yuri -Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan -Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene -Weber, David Welch, Martin Whitaker, Marco Widmer, Leon Wildman, Daniel -Wilkerson, Gerald Williams, Trevor Williams, Jeff Winston, Joshua Wise, -Clifford Wolf, Tobias Wolfel, Johan Wouters, Paul Wright, Junyi Xi, Ding -Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke Yang, Amir Yazdanbakhsh, and -Keyi Zhang. - -Thanks to them, and all those we've missed including above, or wished to -remain anonymous. - - =head1 DISTRIBUTION The latest version is available from L. @@ -5869,7 +472,7 @@ L, L, L, L, L which is the source for this document, -and docs/internals.rst in the distribution. +and L for detailed documentation. =cut diff --git a/bin/verilator_coverage b/bin/verilator_coverage index 8093ad94a..e6ecbb77a 100755 --- a/bin/verilator_coverage +++ b/bin/verilator_coverage @@ -160,122 +160,27 @@ verilator_coverage - Verilator coverage analyzer Verilator_coverage processes Verilated model-generated coverage reports. -With --annotate, it reads the specified coverage data file and generates -annotated source code with coverage metrics annotated. If multiple -coverage points exist on the same source code line, additional lines will -be inserted to report the additional points. +For documentation see L. -Additional Verilog-XL-style standard arguments specify the search paths -necessary to find the source code that the coverage analysis was performed -on. +=head1 ARGUMENT SUMMARY -To filter those items to be included in coverage, you may read -logs/coverage.dat into an editor and do a M-x keep-lines to include only -those statistics of interest and save to a new .dat file. + Specify input data filename, default "coverage.dat" + --annotate Directory name for source annotation. + --annotate-all All files should be shown. + --annotate-min Minimum occurrence count for uncovered. + --help Displays this message and version and exits. + --rank Compute relative importance of tests. + --unlink With --write, unlink all inputs + --version Displays program version and exits. + --write Write aggregate coverage results. + --write-info Write lcov .info. -For Verilog conditions that should never occur, either add a $stop -statement to the appropriate statement block, or see the Verilator -documentation on "// verilator coverage_off" and "coverage_off". This will -remove the coverage points after the model is re-Verilated. - -=head1 ARGUMENTS - -=over 4 - -=item I - -Specify input data file. May be repeated to read multiple inputs. If no -data file is specified, by default coverage.dat is read. - -=item --annotate I - -Specifies the directory name that source files with annotated coverage data -should be written to. - -=item --annotate-all - -Specifies all files should be shown. By default, only those source files -which have low coverage are written to the output directory. - -=item --annotate-min I - -Specifies the minimum occurrence count that should be flagged if the -coverage point does not include a specified threshold. Defaults to 10. - -=item --help - -Displays this message and program version and exits. - -=item --rank - -Print an experimental report listing the relative importance of each test -in covering all of the coverage points. The report shows "Covered" which -indicates the number of points that test covers; a test is considered to -cover a point if it has a bucket count of at least 1. The "rank" column has -a higher number t indicate the test is more important, and rank 0 means the -test does not need to be run to cover the points. "RankPts" indicates the -number of coverage points this test will contribute to overall coverage if -all tests are run in the order of highest to lowest rank. - -=item --unlink - -When using --write to combine coverage data, unlink all input files after -the output has been created. - -=item --version - -Displays program version and exits. - -=item --write I - -Specifies the aggregate coverage results, summed across all the files, -should be written to the given filename in verilator_coverage data format. -This is useful in scripts to combine many sequential runs into one master -coverage file. - -=item --write-info I - -Specifies the aggregate coverage results, summed across all the files, -should be written to the given filename in C .info format. -This may be used to use C to aggregate or generate reports. - -The info format loses data compared to the Verilator coverage data format; -the info will all forms of coverage converted to line style coverage, and -if there are multiple coverage points on a single line, the minimum -coverage across those points will be used to report coverage of the line. - -=back - -=head1 VERILOG ARGUMENTS - -The following arguments are compatible with GCC, VCS and most Verilog -programs. - -=over 4 - -=item +libext+I+I... - -Defines the extensions for Verilog files. - -=item +define+I+I -=item -DI=I - -Defines the given variable. - -=item +incdir+I -=item -II - -Specifies a directory for finding include files. - -=item -f I - -Specifies a file containing additional command line arguments. - -=item -y I - -Specifies a module search directory. - -=back + +libext+I+I... Extensions for Verilog files. + +define+I+I Defines the given variable. + -DI=I Defines the given variable. + +incdir+I Add directory for finding include files. + -II Add directory for finding include files. + -y I Specifies module search directory. =head1 DISTRIBUTION @@ -288,16 +193,14 @@ Artistic License Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -=head1 AUTHORS - -Wilson Snyder - =head1 SEE ALSO C, C L which is the source for this document. +and L for detailed documentation. + =cut ###################################################################### diff --git a/bin/verilator_difftree b/bin/verilator_difftree index 4b181318f..52b03d6bb 100755 --- a/bin/verilator_difftree +++ b/bin/verilator_difftree @@ -223,6 +223,8 @@ Wilson Snyder C +and L for detailed documentation. + =cut ###################################################################### diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 701a08788..2251d9f6a 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -535,83 +535,19 @@ verilator_gantt - Create Gantt chart of multi-threaded execution =head1 SYNOPSIS -Creates a visual representation to help analyze Verilator multithreaded -simulation performance, by showing when each macro-task starts and ends, -and showing when each thread is busy or idle. +Verilator_gantt creates a visual representation to help analyze Verilator +multithreaded simulation performance, by showing when each macro-task +starts and ends, and showing when each thread is busy or idle. -The generated Gantt chart has time on the X-axis. Times shown are to the -scale printed, i.e. a certain about of time for each character width. The -Y-axis shows threads, each thread's execution is shown on one line. That -line shows "[" at the position in time when it executes. +For documentation see L. -Following the "[" is the CPU number the task executed on, followed by zero -or more "-" to make the width of the characters match the scaled execution -time, followed by a "]". If the scale is too small, the CPU number and -mtask number will not be printed. If the scale is very small, a "&" -indicates multiple mtasks started at that time position. +=head1 ARGUMENT SUMMARY -Also creates a value change dump (VCD) format dump file which may be viewed -in a waveform viewer (e.g. C). See below. - -=head1 USAGE - - Build with --prof-threads. - - Run a sim with +verilator+prof+threads+window 2. - - This will create profile_threads.dat. - - Then run: - - verilator_gantt profile_threads.dat - - The report will be printed on standard output, this also generates - profile_threads.vcd - - View profile_threads.vcd in a waveform viewer. - -=head1 VCD SIGNALS - -In waveforms there are the following signals. Most signals the "decimal" -format will remove the leading zeros and make the traces easier to read. - -parallelism: The number of mtasks active at this time, for best performance -this will match the thread count. You may want to use an "analog step" -format to view this signal. - -cpu#_thread: For the given CPU number, the thread number executing. - -mtask#_cpu; For the given mtask id, the CPU it is executing on. - -thread#_mtask: For the given thread number, the mtask id executing. - -=head1 ARGUMENTS - -=over 4 - -=item I - -The filename to read data from, defaults to "profile_threads.dat". - -=item --help - -Displays this message and program version and exits. - -=item --scale I - -On the X-axis of the generated Gantt chart, each character represents this -many time units. (On x86, time units are rdtsc ticks.) Defaults to 0, -which will automatically compute a reasonable scale where no two mtasks -need to fit into same character width's worth of scaled time. - -=item --no-vcd - -=item --vcd I - -Set output filename for vcd dump, or disable. Default is -verilator_gantt.vcd. - -=back + Filename to read data from, default "profile_threads.dat". + --help Displays this message and program version and exits. + --scale I Number of characters per time step. + --no-vcd Do not create a VCD file. + --vcd Set output filename for vcd dump, default "verilator_gantt.vcd." =head1 DISTRIBUTION @@ -624,14 +560,12 @@ Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -=head1 AUTHORS - -Wilson Snyder - =head1 SEE ALSO C +and L for detailed documentation. + =cut ###################################################################### diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index c8a29be83..8dade5ef3 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -214,15 +214,12 @@ the functions are then transformed, assuming the user used Verilator's --prof-cfuncs, and a report printed showing the percentage of time, etc, in each Verilog block. -=head1 ARGUMENTS +For documentation see L. -=over 4 +=head1 ARGUMENT SUMMARY -=item --help - -Displays this message and program version and exits. - -=back + Input file (gprof.out) + --help Display this help =head1 DISTRIBUTION @@ -235,14 +232,12 @@ Version 2.0. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -=head1 AUTHORS - -Wilson Snyder - =head1 SEE ALSO C +and L for detailed documentation. + =cut ###################################################################### diff --git a/ci/docker/buildenv/README.rst b/ci/docker/buildenv/README.rst index 2dd2c7215..5e7110c84 100644 --- a/ci/docker/buildenv/README.rst +++ b/ci/docker/buildenv/README.rst @@ -1,4 +1,3 @@ -================================ Verilator Build Docker Container ================================ @@ -52,7 +51,7 @@ top of a repository: Rebuilding -========== +---------- To rebuild the Verilator-buildenv docker image, run: diff --git a/ci/docker/run/README.rst b/ci/docker/run/README.rst index c635a9546..ccd5709a7 100644 --- a/ci/docker/run/README.rst +++ b/ci/docker/run/README.rst @@ -1,4 +1,3 @@ -===================================== Verilator Executable Docker Container ===================================== @@ -60,7 +59,7 @@ You can also use the container to build Verilator at a specific commit: Internals -========= +--------- The Dockerfile builds Verilator and removes the tree when completed to reduce the image size. The entrypoint is set as a wrapper script diff --git a/docs/CONTRIBUTING.rst b/docs/CONTRIBUTING.rst index 47f1ede39..d6cfd2fc3 100644 --- a/docs/CONTRIBUTING.rst +++ b/docs/CONTRIBUTING.rst @@ -1,4 +1,3 @@ -========================= Contributing to Verilator ========================= @@ -9,7 +8,7 @@ contributions flow more efficiently. Did you find a bug? -=================== +------------------- - Please **Ensure the bug was not already reported** by searching `Verilator Issues `__. @@ -26,7 +25,7 @@ Did you find a bug? Did you write a patch that fixes a bug? -======================================= +--------------------------------------- - Please `Open a new issue `__. @@ -72,7 +71,7 @@ Did you write a patch that fixes a bug? Do you have questions? -====================== +---------------------- - Please see FAQ section and rest of the `Verilator manual `__, or `Verilator @@ -83,7 +82,7 @@ Do you have questions? Code of Conduct -=============== +--------------- - Our contributors and participants pledge to make participation in our project and our community a positive experience for everyone. We follow diff --git a/docs/Makefile b/docs/Makefile index 609b67b19..e9488273f 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -5,24 +5,25 @@ # # Code available from: https://verilator.org # -#***************************************************************************** -# # Copyright 2003-2021 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 # -#****************************************************************************/ +###################################################################### # # This file is intended only to be called from the top-level Verilator Makefile. -#### Start of system configuration section. #### - -DOXYGEN = doxygen RST2HTML = rst2html +PYTHON3 = python3 +DOXYGEN = doxygen +SPHINXOPTS ?= -c guide +SPHINXBUILD ?= sphinx-build + +SOURCEDIR = . +BUILDDIR = _build -#### End of system configuration section. #### ###################################################################### .SUFFIXES: @@ -30,9 +31,49 @@ RST2HTML = rst2html default: @echo "error: make not supported here, run 'make docs' from Verilator top-level" +###################################################################### +# Intermediate rules + +vl-extract: ../bin/verilator ../Changes + mkdir -p _build/gen + $(PYTHON3) bin/vl_sphinx_extract ../bin/verilator + sed 's/`/\&96;/g' < ../Changes > _build/gen/Changes + +###################################################################### +# HTML + +htmled: + $(MAKE) vl-extract + $(MAKE) html + $(PYTHON3) bin/vl_sphinx_fix _build + +server: htmled + cd _build/html && $(PYTHON3) -m http.server + %.html: %.rst $(RST2HTML) $< $@ +###################################################################### +# PDF + +.PHONY: verilator.pdf + +verilator.pdf: pdf +pdf: + $(MAKE) vl-extract + $(MAKE) latex + $(PYTHON3) bin/vl_sphinx_fix _build + $(MAKE) -C _build/latex + cp _build/latex/verilator.pdf .. + +###################################################################### + +html latex clean linkcheck spelling:: + $(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) + +help: + 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"w") + fhw.write( + ".. comment: generated by vl_sphinx_extract from " + + filename + "\n") + fhw.write(".. code-block::\n") + elif re.match(r'^[=a-zA-Z0-9_]', line): + fhw = None + elif fhw: + fhw.write(line) + + +####################################################################### + +parser = argparse.ArgumentParser( + allow_abbrev=False, + formatter_class=argparse.RawDescriptionHelpFormatter, + description="""Read a file and extract documentation data.""", + epilog= + """ Copyright 2021-2021 by Wilson Snyder. This package is free software; +you can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") + +parser.add_argument('--debug', + action='store_const', + const=9, + help='enable debug') +parser.add_argument('path', help='path to extract from') +Args = parser.parse_args() + +o = VlSphinxExtract() +o.debug = Args.debug +o.process(Args.path) + +###################################################################### +# Local Variables: +# compile-command: "./vl_sphinx_extract --debug ../../bin/verilator" +# End: diff --git a/docs/bin/vl_sphinx_fix b/docs/bin/vl_sphinx_fix new file mode 100755 index 000000000..cedbc0d63 --- /dev/null +++ b/docs/bin/vl_sphinx_fix @@ -0,0 +1,79 @@ +#!/usr/bin/env python3 +# pylint: disable=C0112,C0114,C0116,C0301,R0903 +# -*- Python -*- See copyright, etc below +###################################################################### + +import argparse +import os +import re + +####################################################################### + + +class VlSphinxFix: + debug = 0 + SkipBasenames = {} + + def process(self, path): + if os.path.isdir(path): + for basefile in os.listdir(path): + file = os.path.join(path, basefile) + if ((basefile != ".") and (basefile != "..") + and basefile not in self.SkipBasenames + and not os.path.islink(file)): + self.process(file) + elif re.search(r'\.(html|tex)$', path): + self._edit(path) + + def _edit(self, filename): + is_html = re.search(r'\.(html)$', filename) + with open(filename) as fhr: + origfile = fhr.read() + wholefile = origfile + # Option doesn't like spaces, so we use + # :option:`/*verilator&32;metacomment*/` + wholefile = re.sub(r'verilator-32-', r'verilator-', wholefile) + if is_html: + wholefile = re.sub(r'&32;', r' ', wholefile) + wholefile = re.sub(r'&96;', r'`', wholefile) + else: + wholefile = re.sub(r'&32;', r' ', wholefile) + wholefile = re.sub(r'&96;', r'`', wholefile) + if wholefile != origfile: + if self.debug: + print("Edit %s" % filename) + tempname = filename + ".tmp" + with open(tempname, "w") as fhw: + fhw.write(wholefile) + os.rename(tempname, filename) + + +####################################################################### + +parser = argparse.ArgumentParser( + allow_abbrev=False, + formatter_class=argparse.RawDescriptionHelpFormatter, + description="""Post-process Sphinx HTML.""", + epilog= + """ Copyright 2021-2021 by Wilson Snyder. This package is free software; +you can redistribute it and/or modify it under the terms of either the GNU +Lesser General Public License Version 3 or the Perl Artistic License +Version 2.0. + +SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0""") + +parser.add_argument('--debug', + action='store_const', + const=9, + help='enable debug') +parser.add_argument('path', help='path to edit') +Args = parser.parse_args() + +o = VlSphinxFix() +o.debug = Args.debug +o.process(Args.path) + +###################################################################### +# Local Variables: +# compile-command: "./vl_sphinx_fix --debug _build" +# End: diff --git a/docs/gen/ex_USERERROR_faulty.rst b/docs/gen/ex_USERERROR_faulty.rst new file mode 100644 index 000000000..fdd1a5978 --- /dev/null +++ b/docs/gen/ex_USERERROR_faulty.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: sv + + $error("User elaboration-time error"); diff --git a/docs/gen/ex_USERERROR_msg.rst b/docs/gen/ex_USERERROR_msg.rst new file mode 100644 index 000000000..386c97e57 --- /dev/null +++ b/docs/gen/ex_USERERROR_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: + + %Warning-USERERROR: example.v:1:7 User elaboration-time error diff --git a/docs/gen/ex_USERFATAL_faulty.rst b/docs/gen/ex_USERFATAL_faulty.rst new file mode 100644 index 000000000..2900b81b7 --- /dev/null +++ b/docs/gen/ex_USERFATAL_faulty.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: sv + + $fatal(0, "User elaboration-time fatal"); diff --git a/docs/gen/ex_USERFATAL_msg.rst b/docs/gen/ex_USERFATAL_msg.rst new file mode 100644 index 000000000..29fc57c93 --- /dev/null +++ b/docs/gen/ex_USERFATAL_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: + + %Warning-USERFATAL: example.v:1:7 User elaboration-time fatal diff --git a/docs/gen/ex_USERINFO_faulty.rst b/docs/gen/ex_USERINFO_faulty.rst new file mode 100644 index 000000000..ab9701e08 --- /dev/null +++ b/docs/gen/ex_USERINFO_faulty.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: sv + + $info("User elaboration-time info"); diff --git a/docs/gen/ex_USERINFO_msg.rst b/docs/gen/ex_USERINFO_msg.rst new file mode 100644 index 000000000..c30d89ec3 --- /dev/null +++ b/docs/gen/ex_USERINFO_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: + + -Info: example.v:1:7 User elaboration-time info diff --git a/docs/gen/ex_USERWARN_faulty.rst b/docs/gen/ex_USERWARN_faulty.rst new file mode 100644 index 000000000..fc2fb53fa --- /dev/null +++ b/docs/gen/ex_USERWARN_faulty.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: sv + + $warning("User elaboration-time warning"); diff --git a/docs/gen/ex_USERWARN_msg.rst b/docs/gen/ex_USERWARN_msg.rst new file mode 100644 index 000000000..e54250fdd --- /dev/null +++ b/docs/gen/ex_USERWARN_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_assert_comp_bad +.. code-block:: + + %Warning-USERWARN: example.v:1:7 User elaboration-time warning diff --git a/docs/gen/ex_VARHIDDEN_faulty.rst b/docs/gen/ex_VARHIDDEN_faulty.rst new file mode 100644 index 000000000..b982e6c90 --- /dev/null +++ b/docs/gen/ex_VARHIDDEN_faulty.rst @@ -0,0 +1,8 @@ +.. comment: generated by t_var_bad_hide_docs +.. code-block:: sv + :linenos: + :emphasize-lines: 2 + + module t; + integer t; //<--- Warning ('t' hidden by module 't') + endmodule diff --git a/docs/gen/ex_VARHIDDEN_msg.rst b/docs/gen/ex_VARHIDDEN_msg.rst new file mode 100644 index 000000000..08d7a5b9a --- /dev/null +++ b/docs/gen/ex_VARHIDDEN_msg.rst @@ -0,0 +1,5 @@ +.. comment: generated by t_var_bad_hide_docs +.. code-block:: + + %Warning-VARHIDDEN: example.v:2:12 Declaration of signal hides declaration in upper scope: 't' + example.v:1:8 ... Location of original declaration diff --git a/docs/gen/ex_WIDTH_1_faulty.rst b/docs/gen/ex_WIDTH_1_faulty.rst new file mode 100644 index 000000000..0121e66ac --- /dev/null +++ b/docs/gen/ex_WIDTH_1_faulty.rst @@ -0,0 +1,8 @@ +.. comment: generated by t_lint_width_docs_bad +.. code-block:: sv + :linenos: + :emphasize-lines: 3 + + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = array[rd_addr]; //<--- Warning diff --git a/docs/gen/ex_WIDTH_1_fixed.rst b/docs/gen/ex_WIDTH_1_fixed.rst new file mode 100644 index 000000000..11a33b7d0 --- /dev/null +++ b/docs/gen/ex_WIDTH_1_fixed.rst @@ -0,0 +1,5 @@ +.. comment: generated by t_lint_width_docs_bad +.. code-block:: sv + :emphasize-lines: 1 + + wire int rd_value = array[{1'b0, rd_addr}]; //<--- Fixed diff --git a/docs/gen/ex_WIDTH_1_msg.rst b/docs/gen/ex_WIDTH_1_msg.rst new file mode 100644 index 000000000..276a8ffc6 --- /dev/null +++ b/docs/gen/ex_WIDTH_1_msg.rst @@ -0,0 +1,4 @@ +.. comment: generated by t_lint_width_docs_bad +.. code-block:: + + %Warning-WIDTH: example.v:3:29 Bit extraction of array[4:0] requires 3 bit index, not 2 bits. diff --git a/docs/guide/changes.rst b/docs/guide/changes.rst new file mode 100644 index 000000000..439aaae79 --- /dev/null +++ b/docs/guide/changes.rst @@ -0,0 +1,16 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +**************** +Revision History +**************** + +.. COMMENT above header must use ### so there is an extra level of headers + here so the index won't show the huge list of revisions when clicking on + "Revision History" in the sidebar. + +Changes are contained in the :file:`Changes` file of the distribution, and +also summarized below. To subscribe to new versions see `Verilator +Announcements `_. + +.. include:: ../_build/gen/Changes diff --git a/docs/guide/conf.py b/docs/guide/conf.py new file mode 100644 index 000000000..1a94aa6b1 --- /dev/null +++ b/docs/guide/conf.py @@ -0,0 +1,221 @@ +# pylint: disable=E402 +# +# Configuration file for Verilator's Sphinx documentation builder. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +# +# This file only contains overridden options. For a full list: +# https://www.sphinx-doc.org/en/master/usage/configuration.html +# +# ---------------------------------------------------------------------- +# -- Path setup + +from datetime import datetime +import os +import re +import shutil +import sys +sys.path.insert(0, os.path.abspath('./_ext')) + +import sphinx_rtd_theme + + +def get_vlt_version(): + filename = "../../src/config_rev.h" + with open(filename) as fh: + for line in fh: + match = re.search(r'= "([a-z0-9.]+)', line) + if match: + return match.group(1) + return "unknown" + + +# ---------------------------------------------------------------------- +# -- Project information + +project = 'Verilator' +copyright = '2021 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0' +author = 'Wilson Snyder' + +# The master toctree document. +master_doc = "guide/index" + +version = get_vlt_version() +release = get_vlt_version() + +rst_prolog = """ +.. role:: vlopt(option) +""" + +# ---------------------------------------------------------------------- +# -- General configuration + +# Add any Sphinx extension module names here, as strings. They can be +# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom +# ones. +# To install: +# sudo install enchant +# sudo pip3 install sphinx sphinx_rtd_theme breathe sphinxcontrib-spelling +# We keep this list empty for now to avoid needing dependencies +extensions = [] +# extensions = ['breathe', 'sphinxcontrib.spelling'] + +# List of patterns, relative to source directory, that match files and +# directories to ignore when looking for source files. +# This pattern also affects html_static_path and html_extra_path. +exclude_patterns = [ + '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst' +] + +# Warn about refs +nitpicky = True +nitpicky_ignore = [] + +# Number figures for referencing +numfig = True + +# The name of the Pygments (syntax highlighting) style to use. +pygments_style = "sphinx" + +# The suffix(es) of source filenames. +# You can specify multiple suffix as a list of string: +source_suffix = [".rst"] + +# Add any paths that contain templates here, relative to this directory. +templates_path = ['_templates'] + +# Date format to ISO +today_fmt = datetime.now().strftime("%F") + +# If true, `todo` and `todoList` produce output, else they produce nothing. +todo_include_todos = True + +# TODO could use this for internals<->guide references +# intersphinx_mapping = { 'sphinx': ('https://sphinx-doc.org/', None), } + +# ---------------------------------------------------------------------- +# -- Options for HTML output + +# html_baseurl = + +html_domain_indices = False + +html_logo = "../_static/verilator_192_150_min.png" + +html_theme = 'sphinx_rtd_theme' +html_theme_path = [sphinx_rtd_theme.get_html_theme_path()] + +html_theme_options = { + 'analytics_id': 'G-D27B0C9QEB', + 'logo_only': True, + 'style_nav_header_background': "#45acf8", # Default is #2980B9 + # 'canonical_url': +} + +html_context = { + 'display_github': True, + 'github_user': 'verilator', + 'github_repo': 'verilator', + 'github_version': 'master/docs/user/', +} + +# Add any paths that contain custom static files (such as style sheets) here, +# relative to this directory. They are copied after the builtin static files, +# so a file named "default.css" will overwrite the builtin "default.css". +html_static_path = ['../_static'] + +# If true, "Created using Sphinx" is shown in the HTML footer. Default is True. +html_show_sphinx = False + +html_use_index = False + +html_favicon = "../_static/verilator_32x32_min.png" + +# Custom sidebar templates, maps document names to template names. +# html_sidebars + +# Add any extra paths that contain custom files (such as robots.txt or +# .htaccess) here, relative to this directory. These files are copied +# directly to the root of the documentation. +# html_extra_path = [] + +# Additional templates that should be rendered to pages, maps page names to +# template names. +# html_additional_pages = {} + +# ---------------------------------------------------------------------- +# -- Options for Latex output + +latex_logo = "../_static/verilator_logo.png" + +latex_elements = { + 'extraclassoptions': 'openany,oneside', + 'papersize': 'letterpaper', + 'makeindex': '', + 'printindex': '', + # 'pointsize': '10pt', + # 'preamble': '', +} + +# Grouping the document tree into LaTeX files. List of tuples +# (source start file, target name, title, +# author, documentclass [howto, manual, or own class]). +# latex_documents = [ +# ( +# master_doc, +# "Verilog-to-Routing.tex", +# "Verilog-to-Routing Documentation", +# "VTR Developers", +# "manual", +# ), +# ] + +# For "manual" documents, if this is true, then toplevel headings are parts, +# not chapters. +# latex_use_parts = False + +# If true, show page references after internal links. +# latex_show_pagerefs = False + +# If true, show URL addresses after external links. +# latex_show_urls = False + +latex_domain_indices = False + +# ---------------------------------------------------------------------- +# -- Options for manual page output + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +# man_pages = [(master_doc, "verilog-to-routing", "Verilog-to-Routing Documentation", [author], 1)] + +# If true, show URL addresses after external links. +# man_show_urls = False + +# ---------------------------------------------------------------------- +# -- Options for spelling + +spelling_word_list_filename = ['spelling.txt'] +spelling_ignore_contributor_names = True + +# ---------------------------------------------------------------------- +# -- Options for doxygen + +#if shutil.which("doxygen"): +# breathe_projects = { +# "verilated": "../_build/doxygen/verilated/xml", +# } +# breathe_default_project = "verilated" +# +# if not os.environ.get("SKIP_DOXYGEN", None) == "True": +# for prjname, prjdir in breathe_projects.items(): +# print("Generating doxygen files for {}...".format(prjname)) +# os.makedirs(prjdir, exist_ok=True) +# cmd = "cd ../_doxygen && doxygen {}.dox".format(prjname) +# subprocess.call(cmd, shell=True) +# else: +# for prjname, prjdir in breathe_projects.items(): +# assert os.path.exists(prjdir) == True, "Regenerate doxygen XML for {}".format(prjname) + +breathe_projects = {"verilated": "_build/doxygen/verilated/xml/"} +breathe_default_project = "verilated" +breathe_default_members = ('members') diff --git a/docs/guide/connecting.rst b/docs/guide/connecting.rst new file mode 100644 index 000000000..720ecb8c1 --- /dev/null +++ b/docs/guide/connecting.rst @@ -0,0 +1,451 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Connecting: + +****************************** +Connecting to Verilated Models +****************************** + +.. _Connecting to C++: + +Connecting to C++ +================= + +Verilator creates a :file:`{prefix}.h` and :file:`{prefix}.cpp` file for +the top level module, together with additional .h and .cpp files for +internals. See the :file:`examples` directory in the kit for examples. See +:ref:`Files Read/Written` for information on all the files it writes. + +After the model is created, there will be a :file:`{prefix}.mk` file that +may be used with Make to produce a :file:`{prefix}__ALL.a` file with all +required objects in it. + +The user must write a C++ wrapper and main loop for the simulation, to link +with the Verilated model. Here is a simple example: + +.. code-block:: C++ + + #include // Defines common routines + #include // Need std::cout + #include "Vtop.h" // From Verilating "top.v" + + Vtop *top; // Instantiation of module + + vluint64_t main_time = 0; // Current simulation time + // This is a 64-bit integer to reduce wrap over issues and + // allow modulus. This is in units of the timeprecision + // used in Verilog (or from --timescale-override) + + double sc_time_stamp() { // Called by $time in Verilog + return main_time; // converts to double, to match + // what SystemC does + } + + int main(int argc, char** argv) { + Verilated::commandArgs(argc, argv); // Remember args + + top = new Vtop; // Create instance + + top->reset_l = 0; // Set some inputs + + while (!Verilated::gotFinish()) { + if (main_time > 10) { + top->reset_l = 1; // Deassert reset + } + if ((main_time % 10) == 1) { + top->clk = 1; // Toggle clock + } + if ((main_time % 10) == 6) { + top->clk = 0; + } + top->eval(); // Evaluate model + cout << top->out << endl; // Read a output + main_time++; // Time passes... + } + + top->final(); // Done simulating + // // (Though this example doesn't get here) + delete top; + } + + +Note signals are read and written as member variables of the model. You +call the :code:`eval()` method to evaluate the model. When the simulation +is complete call the :code:`final()` method to execute any SystemVerilog +final blocks, and complete any assertions. See :ref:`Evaluation Loop`. + + +Connecting to SystemC +===================== + +Verilator will convert the top level module to a SC_MODULE. This module +will attach directly into a SystemC netlist as an instantiation. + +The SC_MODULE gets the same pinout as the Verilog module, with the +following type conversions: Pins of a single bit become bool. Pins 2-32 +bits wide become uint32_t's. Pins 33-64 bits wide become sc_bv's or +vluint64_t's depending on the :vlopt:`--no-pins64` option. Wider pins +become sc_bv's. (Uints simulate the fastest so are used where possible.) + +Lower modules are not pure SystemC code. This is a feature, as using the +SystemC pin interconnect scheme everywhere would reduce performance by an +order of magnitude. + + +Direct Programming Interface (DPI) +================================== + +Verilator supports SystemVerilog Direct Programming Interface import and +export statements. Only the SystemVerilog form ("DPI-C") is supported, not +the original Synopsys-only DPI. + +DPI Example +----------- + +In the SYSTEMC example above, if you wanted to import C++ functions into +Verilog, put in our.v: + +.. code-block:: + + import "DPI-C" function int add (input int a, input int b); + + initial begin + $display("%x + %x = %x", 1, 2, add(1,2)); + endtask + +Then after Verilating, Verilator will create a file Vour__Dpi.h with the +prototype to call this function: + +.. code-block:: C++ + + extern int add(int a, int b); + +From the sc_main.cpp file (or another .cpp file passed to the Verilator +command line, or the link), you'd then: + +.. code-block:: C++ + + #include "svdpi.h" + #include "Vour__Dpi.h" + int add(int a, int b) { return a+b; } + + +DPI System Task/Functions +------------------------- + +Verilator extends the DPI format to allow using the same scheme to +efficiently add system functions. Simply use a dollar-sign prefixed system +function name for the import, but note it must be escaped. + +.. code-block:: sv + + export "DPI-C" function integer \$myRand; + + initial $display("myRand=%d", $myRand()); + +Going the other direction, you can export Verilog tasks so they can be +called from C++: + +.. code-block:: sv + + export "DPI-C" task publicSetBool; + + task publicSetBool; + input bit in_bool; + var_bool = in_bool; + endtask + +Then after Verilating, Verilator will create a file Vour__Dpi.h with the +prototype to call this function: + +.. code-block:: C++ + + extern void publicSetBool(svBit in_bool); + +From the sc_main.cpp file, you'd then: + +.. code-block:: C++ + + #include "Vour__Dpi.h" + publicSetBool(value); + +Or, alternatively, call the function under the design class. This isn't +DPI compatible but is easier to read and better supports multiple designs. + +.. code-block:: C++ + + #include "Vour__Dpi.h" + Vour::publicSetBool(value); + // or top->publicSetBool(value); + +Note that if the DPI task or function accesses any register or net within +the RTL, it will require a scope to be set. This can be done using the +standard functions within svdpi.h, after the module is instantiated, but +before the task(s) and/or function(s) are called. + +For example, if the top level module is instantiated with the name "dut" +and the name references within tasks are all hierarchical (dotted) names +with respect to that top level module, then the scope could be set with + +.. code-block:: C++ + + #include "svdpi.h" + ... + svSetScope(svGetScopeFromName("TOP.dut")); + +(Remember that Verilator adds a "TOP" to the top of the module hierarchy.) + +Scope can also be set from within a DPI imported C function that has been +called from Verilog by querying the scope of that function. See the +sections on DPI Context Functions and DPI Header Isolation below and the +comments within the svdpi.h header for more information. + + +DPI Imports that access signals +------------------------------- + +If a DPI import accesses a signal through the VPI Verilator will not be +able to know what variables are accessed and may schedule the code +inappropriately. Ideally pass the values as inputs/outputs so the VPI is +not required. Alternatively a workaround is to use a non-inlined task as a +wrapper: + +.. code-block:: + + logic din; + + // This DPI function will read "din" + import "DPI-C" context function void dpi_that_accesses_din(); + + always @(...) + dpi_din_args(din); + + task dpi_din_args(input din); + /* verilator no_inline_task */ + dpi_that_accesses_din(); + endtask + + +DPI Display Functions +--------------------- + +Verilator allows writing $display like functions using this syntax: + +.. code-block:: + + import "DPI-C" function void + \$my_display(input string formatted /*verilator sformat*/ ); + +The :option:`/*verilator&32;sformat*/` metacomment indicates that this +function accepts a $display like format specifier followed by any number of +arguments to satisfy the format. + + +DPI Context Functions +--------------------- + +Verilator supports IEEE DPI Context Functions. Context imports pass the +simulator context, including calling scope name, and filename and line +number to the C code. For example, in Verilog: + +.. code-block:: + + import "DPI-C" context function int dpic_line(); + initial $display("This is line %d, again, line %d\n", `line, dpic_line()); + +This will call C++ code which may then use the svGet\* functions to read +information, in this case the line number of the Verilog statement that +invoked the dpic_line function: + +.. code-block:: C++ + + int dpic_line() { + // Get a scope: svScope scope = svGetScope(); + + const char* scopenamep = svGetNameFromScope(scope); + assert(scopenamep); + + const char* filenamep = ""; + int lineno = 0; + if (svGetCallerInfo(&filenamep, &lineno)) { + printf("dpic_line called from scope %s on line %d\n", + scopenamep, lineno); + return lineno; + } else { + return 0; + } + } + +See the IEEE Standard for more information. + + +DPI Header Isolation +-------------------- + +Verilator places the IEEE standard header files such as svdpi.h into a +separate include directory, vltstd (VeriLaTor STandarD). When compiling +most applications $VERILATOR_ROOT/include/vltstd would be in the include +path along with the normal $VERILATOR_ROOT/include. However, when +compiling Verilated models into other simulators which have their own +svdpi.h and similar standard files with different contents, the vltstd +directory should not be included to prevent picking up incompatible +definitions. + + +Public Functions +---------------- + +Instead of DPI exporting, there's also Verilator public functions, which +are slightly faster, but less compatible. + + +Verification Procedural Interface (VPI) +======================================= + +Verilator supports a limited subset of the VPI. This subset allows +inspection, examination, value change callbacks, and depositing of values +to public signals only. + +VPI is enabled with the Verilator :vlopt:`--vpi` option. + +To access signals via the VPI, Verilator must be told exactly which signals +are to be accessed. This is done using the Verilator public pragmas +documented below. + +Verilator has an important difference from an event based simulator; signal +values that are changed by the VPI will not immediately propagate their +values, instead the top level header file's :code:`eval()` method must be +called. Normally this would be part of the normal evaluation (i.e. the +next clock edge), not as part of the value change. This makes the +performance of VPI routines extremely fast compared to event based +simulators, but can confuse some test-benches that expect immediate +propagation. + +Note the VPI by its specified implementation will always be much slower +than accessing the Verilator values by direct reference +(structure->module->signame), as the VPI accessors perform lookup in +functions at simulation runtime requiring at best hundreds of instructions, +while the direct references are evaluated by the compiler and result in +only a couple of instructions. + +For signal callbacks to work the main loop of the program must call +:code:`VerilatedVpi::callValueCbs()`. + + +.. _VPI Example: + +VPI Example +----------- + +In the below example, we have readme marked read-only, and writeme which if +written from outside the model will have the same semantics as if it +changed on the specified clock edge. + +.. code-block:: bash + + cat >our.v <<'EOF' + module our (input clk); + reg readme /*verilator public_flat_rd*/; + reg writeme /*verilator public_flat_rw @(posedge clk) */; + initial $finish; + endmodule + EOF + +There are many online tutorials and books on the VPI, but an example that +accesses the above signal "readme" would be: + +.. code-block:: bash + + cat >sim_main.cpp <<'<eval(); + VerilatedVpi::callValueCbs(); // For signal callbacks + read_and_check(); + } + delete top; + return 0; + } + EOF + + +.. _Evaluation Loop: + +Wrappers and Model Evaluation Loop +================================== + +When using SystemC, evaluation of the Verilated model is managed by the +SystemC kernel, and for the most part can be ignored. When using C++, the +user must call :code:`eval()`, or :code:`eval_step()` and +:code:`eval_end_step()`. + +1. When there is a single design instantiated at the C++ level that needs +to evaluate within a given context, call :code:`designp->eval()`. + +2. When there are multiple designs instantiated at the C++ level that need +to evaluate within a context, call :code:`first_designp->eval_step()` then +:code:`->eval_step()` on all other designs. Then call +:code:`->eval_end_step()` on the first design then all other designs. If +there is only a single design, you would call :code:`eval_step()` then +:code:`eval_end_step()`; in fact :code:`eval()` described above is just a +wrapper which calls these two functions. + +When :code:`eval()` (or :code:`eval_step()`) is called Verilator looks for +changes in clock signals and evaluates related sequential always blocks, +such as computing always_ff @ (posedge...) outputs. Then Verilator +evaluates combinatorial logic. + +Note combinatorial logic is not computed before sequential always blocks +are computed (for speed reasons). Therefore it is best to set any non-clock +inputs up with a separate :code:`eval()` call before changing clocks. + +Alternatively, if all always_ff statements use only the posedge of clocks, +or all inputs go directly to always_ff statements, as is typical, then you +can change non-clock inputs on the negative edge of the input clock, which +will be faster as there will be fewer :code:`eval()` calls. + +For more information on evaluation, see :file:`docs/internals.rst` in the +distribution. + + +Verilated and VerilatedContext +============================== + +Multiple Verilated models may be part of the same simulation context, that +is share a VPI interface, sense of time, and common settings. This common +simulation context information is stored in a ``VerilatedContext`` +structure. If a ``VerilatedContext`` is not created prior to creating a +model, a default global one is created automatically. + +The ``Verilated::`` methods, including the ``Verilated::commandArgs`` call +shown above, simply call VerilatedContext methods using the default global +VerilatedContext. (Technically they operate on the last one used by a +given thread.) If you are using multiple simulation contexts you should +not use the Verilated:: methods, and instead always use VerilatedContext +methods called on the appropriate VerilatedContext object. + +For methods available under Verilated and VerilatedContext see +:file:`include/verilated.h` in the distribution. diff --git a/docs/guide/contributing.rst b/docs/guide/contributing.rst new file mode 100644 index 000000000..d3d091bae --- /dev/null +++ b/docs/guide/contributing.rst @@ -0,0 +1,68 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +******************************* +Contributing and Reporting Bugs +******************************* + +Announcements +============= + +To get notified of new releases and other important announcements, go to +`Verilator announcement repository +`__ and follow the +instructions there. + + +Reporting Bugs +============== + +First, check the :ref:`Language Limitations` section. + +Next, try the :vlopt:`--debug` option. This will enable additional +internal assertions, and may help identify the problem. + +Finally, reduce your code to the smallest possible routine that exhibits +the bug. Even better, create a test in the :file:`test_regress/t` +directory, as follows: + +.. code-block:: bash + + cd test_regress + cp -p t/t_EXAMPLE.pl t/t_BUG.pl + cp -p t/t_EXAMPLE.v t/t_BUG.v + +There are many hints on how to write a good test in the +:file:`test_regress/driver.pl` documentation which can be seen by running: + +.. code-block:: bash + + cd $VERILATOR_ROOT # Need the original distribution kit + test_regress/driver.pl --help + +Edit :file:`t/t_BUG.pl` to suit your example; you can do anything you want +in the Verilog code there; just make sure it retains the single clk input +and no outputs. Now, the following should fail: + +.. code-block:: bash + + cd $VERILATOR_ROOT # Need the original distribution kit + cd test_regress + t/t_BUG.pl # Run on Verilator + t/t_BUG.pl --debug # Run on Verilator, passing --debug to Verilator + t/t_BUG.pl --vcs # Run on VCS simulator + t/t_BUG.pl --nc|--iv|--ghdl # Likewise on other simulators + +The test driver accepts a number of options, many of which mirror the main +Verilator options. For example the previous test could have been run with +debugging enabled. The full set of test options can be seen by running +:command:`driver.pl --help` as shown above. + +Finally, report the bug at `Verilator Issues +`_. The bug will become publicly visible; if +this is unacceptable, mail the bug report to ``wsnyder@wsnyder.org``. + + +.. Contributing +.. ============ +.. include:: ../CONTRIBUTING.rst diff --git a/docs/guide/contributors.rst b/docs/guide/contributors.rst new file mode 100644 index 000000000..c38cb8515 --- /dev/null +++ b/docs/guide/contributors.rst @@ -0,0 +1,155 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +************************ +Contributors and Origins +************************ + +Authors +======= + +When possible, please instead report bugs at `Verilator Issues +`_. + +Primary author is Wilson Snyder . + +Major concepts by Paul Wasson, Duane Galbi, John Coiner and Jie Xu. + + +Contributors +============ + +Many people have provided ideas and other assistance with Verilator. + +Verilator is receiving major development support from the `CHIPS Alliance +`_. + +Previous major corporate sponsors of Verilator, by providing significant +contributions of time or funds included include: Atmel Corporation, Cavium +Inc., Compaq Corporation, Digital Equipment Corporation, Embecosm Ltd., +Hicamp Systems, Intel Corporation, Mindspeed Technologies Inc., MicroTune +Inc., picoChip Designs Ltd., Sun Microsystems Inc., Nauticus Networks Inc., +and SiCortex Inc. + +The people who have contributed major functionality are: Byron Bradley, +Jeremy Bennett, Lane Brooks, John Coiner, Duane Galbi, Geza Lore, Todd +Strader, Stefan Wallentowitz, Paul Wasson, Jie Xu, and Wilson Snyder. +Major testers included Jeff Dutton, Jonathon Donaldson, Ralf Karge, David +Hewson, Iztok Jeras, Wim Michiels, Alex Solomatnikov, Sebastien Van +Cauwenberghe, Gene Weber, and Clifford Wolf. + +Some of the people who have provided ideas, and feedback for Verilator +include: David Addison, Nikana Anastasiadis, Vasu Arasanipalai, Jens Arm, +Tariq B. Ahmad, Sharad Bagri, Matthew Ballance, Andrew Bardsley, Matthew +Barr, Geoff Barrett, Kaleb Barrett, Julius Baxter, Jeremy Bennett, Michael +Berman, Jean Berniolles, Victor Besyakov, Moinak Bhattacharyya, Krzysztof +Bieganski, David Binderman, Piotr Binkowski, Johan Bjork, David Black, +Tymoteusz Blazejczyk, Daniel Bone, Morten Borup Petersen, Gregg Bouchard, +Christopher Boumenot, Nick Bowler, Byron Bradley, Bryan Brady, Charlie +Brej, J Briquet, Lane Brooks, John Brownlee, Jeff Bush, Lawrence Butcher, +Tony Bybell, Iru Cai, Ted Campbell, Chris Candler, Lauren Carlson, Donal +Casey, Alex Chadwick, Terry Chen, Yi-Chung Chen, Enzo Chi, Robert A. Clark, +Ryan Clarke, Allan Cochrane, John Coiner, Gianfranco Costamagna, Sean +Cross, George Cuan, Joe DErrico, Lukasz Dalek, Gunter Dannoritzer, Ashutosh +Das, Maarten De Braekeleer, Bernard Deadman, Alberto Del Rio, John Demme, +Mike Denio, John Deroo, Philip Derrick, John Dickol, Ruben Diez, Danny +Ding, Jacko Dirks, Ivan Djordjevic, Jonathon Donaldson, Sebastian Dressler, +Alex Duller, Jeff Dutton, Tomas Dzetkulic, Richard E George, Edgar +E. Iglesias, Usuario Eda, Charles Eddleston, Chandan Egbert, Jan Egil Ruud, +Joe Eiler, Ahmed El-Mahmoudy, Trevor Elbourne, Mats Engstrom, Charles Eric +LaForest, Robert Farrell, Eugen Fekete, Fabrizio Ferrandi, Udi Finkelstein, +Brian Flachs, Andrea Foletto, Bob Fredieu, Duane Galbi, Benjamin Gartner, +Christian Gelinek, Peter Gerst, Glen Gibb, Michael Gielda, Barbara Gigerl, +Shankar Giri, Dan Gisselquist, Petr Gladkikh, Sam Gladstone, Andrew +Goessling, Amir Gonnen, Chitlesh Goorah, Tomasz Gorochowik, Kai Gossner, +Sergi Granell, Al Grant, Alexander Grobman, Xuan Guo, Driss Hafdi, Neil +Hamilton, James Hanlon, Oyvind Harboe, Jannis Harder, Junji Hashimoto, +Thomas Hawkins, Mitch Hayenga, Harald Heckmann, Robert Henry, Stephen +Henry, David Hewson, Jamey Hicks, Joel Holdsworth, Andrew Holme, Hiroki +Honda, Alex Hornung, Pierre-Henri Horrein, David Horton, Peter Horvath, Jae +Hossell, Kuoping Hsu, Alan Hunter, James Hutchinson, Anderson Ignacio da +Silva, Jamie Iles, Thomas J Whatson, Ben Jackson, Mark Jackson Pulver, +Shareef Jalloq, Marlon James, Krzysztof Jankowski, HyungKi Jeong, Iztok +Jeras, James Johnson, Christophe Joly, Franck Jullien, James Jung, Mike +Kagen, Arthur Kahlich, Kaalia Kahn, Guy-Armand Kamendje, Vasu Kandadi, +Kanad Kanhere, Patricio Kaplan, Pieter Kapsenberg, Rafal Kapuscik, Ralf +Karge, Dan Katz, Sol Katzman, Ian Kennedy, Michael Killough, Jonathan +Kimmitt, Olof Kindgren, Kevin Kiningham, Dan Kirkham, Sobhan Klnv, Gernot +Koch, Jack Koenig, Soon Koh, Nathan Kohagen, Steve Kolecki, Brett Koonce, +Will Korteland, Wojciech Koszek, Varun Koyyalagunta, Markus Krause, David +Kravitz, Roland Kruse, Andreas Kuster, Sergey Kvachonok, Ed Lander, Steve +Lang, Stephane Laurent, Walter Lavino, Christian Leber, Larry Lee, Igor +Lesik, John Li, Eivind Liland, Charlie Lind, Andrew Ling, Jiuyang Liu, Paul +Liu, Derek Lockhart, Jake Longo, Geza Lore, Arthur Low, Stefan Ludwig, Dan +Lussier, Fred Ma, Duraid Madina, Odd Magne Reitan, Affe Mao, Julien +Margetts, Mark Marshall, Alfonso Martinez, Unai Martinez-Corral, Yves +Mathieu, Patrick Maupin, Conor McCullough, Jason McMullan, Elliot Mednick, +Wim Michiels, Miodrag Milanovic, Peter Monsson, Sean Moore, Dennis +Muhlestein, John Murphy, Matt Myers, Nathan Myers, Richard Myers, Dimitris +Nalbantis, Peter Nelson, Bob Newgard, Paul Nitza, Yossi Nivin, Pete Nixon, +Lisa Noack, Mark Nodine, Kuba Ober, Andreas Olofsson, Baltazar Ortiz, +Aleksander Osman, Don Owen, James Pallister, Vassilis Papaefstathiou, Brad +Parker, Dan Petrisko, Maciej Piechotka, David Pierce, Cody Piersall, +Dominic Plunkett, David Poole, Mike Popoloski, Roman Popov, Rich Porter, +Niranjan Prabhu, Usha Priyadharshini, Prateek Puri, Marshal Qiao, Nandu +Raj, Danilo Ramos, Chris Randall, Anton Rapp, Josh Redford, Frederic +Requin, Dustin Richmond, Samuel Riedel, Eric Rippey, Oleg Rodionov, Ludwig +Rogiers, Paul Rolfe, Arjen Roodselaar, Tobias Rosenkranz, Huang Rui, Denis +Rystsov, John Sanguinetti, Galen Seitz, Joseph Shaker, Salman Sheikh, Yu +Sheng Lin, Hao Shi, Mike Shinkarovsky, Rafael Shirakawa, Jeffrey Short, Fan +Shupei, Rodney Sinclair, Steven Slatter, Brian Small, Garrett Smith, Tim +Snyder, Wilson Snyder, Maciej Sobkowski, Stan Sokorac, Alex Solomatnikov, +Wei Song, Art Stamness, David Stanford, John Stevenson, Pete Stevenson, +Patrick Stewart, Rob Stoddard, Todd Strader, John Stroebel, Sven Stucki, +Howard Su, Emerson Suguimoto, Gene Sullivan, Wai Sum Mong, Qingyao Sun, +Renga Sundararajan, Rupert Swarbrick, Yutetsu Takatsukasa, Thierry Tambe, +Drew Taussig, Peter Tengstrand, Wesley Terpstra, Rui Terra, Stefan Thiede, +Gary Thomas, Ian Thompson, Kevin Thompson, Mike Thyer, Hans Tichelaar, +Viktor Tomov, Steve Tong, Alex Torregrosa, Michael Tresidder, David Turner, +Neil Turton, Cong Van Nguyen, Hans Van Antwerpen, Jan Van Winkel, Sebastien +Van Cauwenberghe, Laurens van Dam, Leendert van Doorn, Srini Vemuri, Yuri +Victorovich, Bogdan Vukobratovic, Holger Waechtler, Philipp Wagner, Stefan +Wallentowitz, Shawn Wang, Paul Wasson, Greg Waters, Thomas Watts, Eugene +Weber, David Welch, Martin Whitaker, Marco Widmer, Leon Wildman, Daniel +Wilkerson, Gerald Williams, Trevor Williams, Jeff Winston, Joshua Wise, +Clifford Wolf, Tobias Wolfel, Johan Wouters, Paul Wright, Junyi Xi, Ding +Xiaoliang, Jie Xu, Mandy Xu, Yinan Xu, Luke Yang, Amir Yazdanbakhsh, and +Keyi Zhang. + +Thanks to them, and all those we've missed including above, or wished to +remain anonymous. + +Historical Origins +================== + +Verilator was conceived in 1994 by Paul Wasson at the Core Logic Group at +Digital Equipment Corporation. The Verilog code that was converted to C +was then merged with a C based CPU model of the Alpha processor and +simulated in a C based environment called CCLI. + +In 1995 Verilator started being used also for Multimedia and Network +Processor development inside Digital. Duane Galbi took over active +development of Verilator, and added several performance enhancements. CCLI +was still being used as the shell. + +In 1998, through the efforts of existing DECies, mainly Duane Galbi, +Digital graciously agreed to release the source code. (Subject to the code +not being resold, which is compatible with the GNU Public License.) + +In 2001, Wilson Snyder took the kit, and added a SystemC mode, and called +it Verilator2. This was the first packaged public release. + +In 2002, Wilson Snyder created Verilator 3.000 by rewriting Verilator from +scratch in C++. This added many optimizations, yielding about a 2-5x +performance gain. + +In 2009, major SystemVerilog and DPI language support was added. + +In 2018, Verilator 4.000 was released with multithreaded support. + +In 2019, Verilator joined the `CHIPS Alliance +`_. + +Currently, various language features and performance enhancements are added +as the need arises. Verilator is now about 3x faster than in 2002, and is +faster than most (if not every) other simulator. diff --git a/docs/guide/copyright.rst b/docs/guide/copyright.rst new file mode 100644 index 000000000..e00dc420a --- /dev/null +++ b/docs/guide/copyright.rst @@ -0,0 +1,19 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +********* +Copyright +********* + +The latest version of Verilator is available from `https://verilator.org +`_. + +Copyright 2003-2021 by Wilson Snyder. This program is free software; you +can redistribute it and/or modify the Verilator internals under the terms +of either the GNU Lesser General Public License Version 3 or the Perl +Artistic License Version 2.0. + +All Verilog and C++/SystemC code quoted within this documentation file are +released as Creative Commons Public Domain (CC0). Many example files and +test files are likewise released under CC0 into effectively the Public +Domain as described in the files themselves. diff --git a/docs/guide/deprecations.rst b/docs/guide/deprecations.rst new file mode 100644 index 000000000..ddb7546db --- /dev/null +++ b/docs/guide/deprecations.rst @@ -0,0 +1,28 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +Deprecations +============ + +The following deprecated items are scheduled for future removal: + +C++11 compiler support + Verilator currently requires C++11 or newer compilers. Verilator will + require C++14 or newer compilers for both compiling Verilator and + compiling Verilated models no sooner than January 2022. + +No-Relative-Cfuncs Option + The :vlopt:`--no-relative-cfuncs` option is not be required by any C++11 + compliant compiler and is planned for removal no sooner than July 2021. + +Inhibit-Sim Option + The :vlopt:`--inhibit-sim` option is planned for removal no sooner than + July 2021. + +Configuration File -msg + The :vlopt:`lint_off` "-msg" option has been replaced with the "-rule" + option. "-msg" is planned for removal no sooner than January 2021. + +XML locations + The XML "fl" attribute has been replaced with the "loc" attribute. "fl" + is planned for removal no sooner than January 2021. diff --git a/docs/guide/environment.rst b/docs/guide/environment.rst new file mode 100644 index 000000000..f52fe0a41 --- /dev/null +++ b/docs/guide/environment.rst @@ -0,0 +1,93 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +Environment +=========== + +This section describes the environment variables used by Verilator and +associated programs. + +.. option:: LD_LIBRARY_PATH + + A generic Linux/OS variable specifying what directories have shared + object (.so) files. This path should include SystemC and any other + shared objects needed at simulation runtime. + +.. option:: MAKE + + Names the executable of the make command invoked when using the + :vlopt:`--build` option. Some operating systems may require "gmake" to + this variable to launch GNU make. If this variable is not specified, + "make" is used. + +.. option:: OBJCACHE + + Optionally specifies a caching or distribution program to place in front + of all runs of the C++ compiler. For example, "ccache". If using + :command:`distcc` or :command:`icecc`/:command:`icecream`, they would + generally be run under :command:`ccache`; see the documentation for + those programs. If OBJCACHE is not set, and at configure time ccache + was present, ccache will be used as a default. + +.. option:: SYSTEMC + + Deprecated. Used only if :option:`SYSTEMC_INCLUDE` or + :option:`SYSTEMC_LIBDIR` is not set. If set, specifies the directory + containing the SystemC distribution. If not specified, it will come + from a default optionally specified at configure time (before Verilator + was compiled). + +.. option:: SYSTEMC_ARCH + + Deprecated. Used only if :option:`SYSTEMC_LIBDIR` is not set. + Specifies the architecture name used by the SystemC kit. This is the + part after the dash in the "lib-{...}" directory name created by a + :command:`make` in the SystemC distribution. If not set, Verilator will + try to intuit the proper setting, or use the default optionally + specified at configure time (before Verilator was compiled). + +.. option:: SYSTEMC_CXX_FLAGS + + Specifies additional flags that are required to be passed to GCC when + building the SystemC model. System 2.3.0 may need this set to + "-pthread". + +.. option:: SYSTEMC_INCLUDE + + If set, specifies the directory containing the systemc.h header file. If + not specified, it will come from a default optionally specified at + configure time (before Verilator was compiled), or computed from + SYSTEMC/include. + +.. option:: SYSTEMC_LIBDIR + + If set, specifies the directory containing the libsystemc.a library. If + not specified, it will come from a default optionally specified at + configure time (before Verilator was compiled), or computed from + SYSTEMC/lib-SYSTEMC_ARCH. + +.. option:: VERILATOR_BIN + + If set, specifies an alternative name of the ``verilator`` binary. May + be used for debugging and selecting between multiple operating system + builds. + +.. option:: VERILATOR_COVERAGE_BIN + + If set, specifies an alternative name of the ``verilator_coverage`` + binary. May be used for debugging and selecting between multiple + operating system builds. + +.. option:: VERILATOR_GDB + + If set, the command to run when using the :vlopt:`--gdb` option, such as + "ddd". If not specified, it will use "gdb". + +.. option:: VERILATOR_ROOT + + Specifies the directory containing the distribution kit. This is used + to find the executable, Perl library, and include files. If not + specified, it will come from a default optionally specified at configure + time (before Verilator was compiled). It should not be specified if + using a pre-compiled Verilator package as the hard-coded value should be + correct. See :ref:`Installation`. diff --git a/docs/guide/example_cc.rst b/docs/guide/example_cc.rst new file mode 100644 index 000000000..1894c2074 --- /dev/null +++ b/docs/guide/example_cc.rst @@ -0,0 +1,92 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Example C++ Execution: + +Example C++ Execution +===================== + +We'll compile this example into C++. For an extended and commented version +of what this C++ code is doing, see +:file:`examples/make_tracing_c/sim_main.cpp` in the distribution. + +.. include:: example_common_install.rst + +Now, let's create an example Verilog, and C++ wrapper file: + +.. code-block:: bash + + mkdir test_our + cd test_our + + cat >our.v <<'EOF' + module our; + initial begin $display("Hello World"); $finish; end + endmodule + EOF + + cat >sim_main.cpp <<'EOF' + #include "Vour.h" + #include "verilated.h" + int main(int argc, char** argv, char** env) { + VerilatedContext* contextp = new VerilatedContext; + contextp->commandArgs(argc, argv); + Vour* top = new Vour{contextp}; + while (!contextp->gotFinish()) { top->eval(); } + delete top; + delete contextp; + return 0; + } + EOF + +Now we run Verilator on our little example. + +.. code-block:: bash + + verilator -Wall --cc --exe --build sim_main.cpp our.v + +Breaking this command down: + +#. :vlopt:`-Wall` so Verilator has stronger lint warnings + enabled. + +#. :vlopt:`--cc` to get C++ output (versus e.g. SystemC + or only linting). + +#. :vlopt:`--exe`, along with our :command:`sim_main.cpp` wrapper file, so + the build will create an executable instead of only a library. + +#. :vlopt:`--build` so Verilator will call make itself. This is we don't + need to manually call make as a separate step. You can also write your + own compile rules, and run make yourself as we show in :ref:`Example + SystemC Execution`.) + +#. An finally, :command:`our.v` which is our SystemVerilog design file. + +Once Verilator completes we can see the generated C++ code under the +:file:`obj_dir` directory. + +.. code-block:: bash + + ls -l obj_dir + +(See :ref:`Files Read/Written` for descriptions of some of the files that +were created.) + +And now we run it: + +.. code-block:: bash + + obj_dir/Vour + +And we get as output: + +.. code-block:: bash + + Hello World + - our.v:2: Verilog $finish + +Really, you're better off using a Makefile to run the steps for you so when +your source changes it will automatically run all of the appropriate steps. +To aid this Verilator can create a makefile dependency file. For examples +that do this see the :file:`examples` directory in the distribution. diff --git a/docs/guide/example_common_install.rst b/docs/guide/example_common_install.rst new file mode 100644 index 000000000..4a7795344 --- /dev/null +++ b/docs/guide/example_common_install.rst @@ -0,0 +1,18 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +First you need Verilator installed, see :ref:`Installation`. In brief, if +you installed Verilator using the package manager of your operating system, +or did a :command:`make install` to place Verilator into your default path, +you do not need anything special in your environment, and should not have +VERILATOR_ROOT set. However, if you installed Verilator from sources and +want to run Verilator out of where you compiled Verilator, you need to +point to the kit: + +.. code-block:: bash + + # See above; don't do this if using an OS-distributed Verilator + export VERILATOR_ROOT=/path/to/where/verilator/was/installed + export PATH=$VERILATOR_ROOT/bin:$PATH + + diff --git a/docs/guide/example_dist.rst b/docs/guide/example_dist.rst new file mode 100644 index 000000000..493e3d204 --- /dev/null +++ b/docs/guide/example_dist.rst @@ -0,0 +1,40 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Examples in the Distribution: + +Examples in the Distribution +============================ + +See the ``examples/`` directory that is part of the distribution, and +is installed (in a OS-specific place, often in e.g. +``/usr/local/share/verilator/examples``). These examples include: + +examples/make_hello_c + Example GNU-make simple Verilog->C++ conversion +examples/make_hello_sc + Example GNU-make simple Verilog->SystemC conversion +examples/make_tracing_c + Example GNU-make Verilog->C++ with tracing +examples/make_tracing_sc + Example GNU-make Verilog->SystemC with tracing +examples/make_protect_lib + Example using --protect-lib +examples/cmake_hello_c + Example building make_hello_c with CMake +examples/cmake_hello_sc + Example building make_hello_sc with CMake +examples/cmake_tracing_c + Example building make_tracing_c with CMake +examples/cmake_tracing_sc + Example building make_tracing_sc with CMake +examples/cmake_protect_lib + Example building make_protect_lib with CMake + +To run an example copy the example to a new directory and run it. + +:: + + cp -rp {path_to}/examples/make_hello_c make_hello_c + cd make_hello_c + make diff --git a/docs/guide/example_sc.rst b/docs/guide/example_sc.rst new file mode 100644 index 000000000..4e982f3b3 --- /dev/null +++ b/docs/guide/example_sc.rst @@ -0,0 +1,73 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Example SystemC Execution: + +Example SystemC Execution +========================= + +This is an example similar to the :ref:`Example C++ Execution`, but using +SystemC. We'll also explicitly run make. + +.. include:: example_common_install.rst + +Now, let's create an example Verilog, and SystemC wrapper file: + +.. code-block:: bash + + mkdir test_our_sc + cd test_our_sc + + cat >our.v <<'EOF' + module our (clk); + input clk; // Clock is required to get initial activation + always @(posedge clk) + begin $display("Hello World"); $finish; end + endmodule + EOF + + cat >sc_main.cpp <<'EOF' + #include "Vour.h" + int sc_main(int argc, char** argv) { + Verilated::commandArgs(argc, argv); + sc_clock clk{"clk", 10, SC_NS, 0.5, 3, SC_NS, true}; + Vour* top = new Vour{"top"}; + top->clk(clk); + while (!Verilated::gotFinish()) { sc_start(1, SC_NS); } + delete top; + return 0; + } + EOF + +Now we run Verilator on our little example: + +.. code-block:: bash + + verilator -Wall --sc --exe sc_main.cpp our.v + +This example does not use --build, therefore we need to explicitly compile +it: + +.. code-block:: bash + + make -j -C obj_dir -f Vour.mk Vour + +And now we run it: + +.. code-block:: bash + + obj_dir/Vour + +And we get, after the SystemC banner, the same output as the C++ example: + +.. code-block:: bash + + SystemC 2.3.3-Accellera + + Hello World + - our.v:4: Verilog $finish + +Really, you're better off using a Makefile to run the steps for you so when +your source changes it will automatically run all of the appropriate steps. +For examples that do this see the :file:`examples` directory in the +distribution. diff --git a/docs/guide/examples.rst b/docs/guide/examples.rst new file mode 100644 index 000000000..83b94f770 --- /dev/null +++ b/docs/guide/examples.rst @@ -0,0 +1,22 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Examples: + +======== +Examples +======== + +This section covers the following examples: + +* :ref:`Example C++ Execution` +* :ref:`Example SystemC Execution` +* :ref:`Examples in the Distribution` + +.. toctree:: + :maxdepth: 1 + :hidden: + + example_cc.rst + example_sc.rst + example_dist.rst diff --git a/docs/guide/exe_sim.rst b/docs/guide/exe_sim.rst new file mode 100644 index 000000000..bd805aab8 --- /dev/null +++ b/docs/guide/exe_sim.rst @@ -0,0 +1,89 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Simulation Runtime Arguments: + +Simulation Runtime Arguments +============================ + +The following are the arguments that may be passed to a Verilated +executable, provided that executable calls +:code:`Verilated::commandArgs()`. + +All simulation runtime arguments begin with "+verilator", so that the +user's executable may skip over all "+verilator" arguments when parsing its +command line. + +Summary: + + .. include:: ../_build/gen/args_verilated.rst + + +.. option:: +verilator+debug + + Enable simulation runtime debugging. Equivalent to + :vlopt:`+verilator+debugi+4 <+verilator+debugi+\>`. + +.. option:: +verilator+debugi+ + + Enable simulation runtime debugging at the provided level. + +.. option:: +verilator+error+limit+ + + Set number of non-fatal errors (e.g. assertion failures) before exiting + simulation runtime. Also affects number of $stop calls needed before + exit. Defaults to 1. + +.. option:: +verilator+help + + Display help and exit. + +.. option:: +verilator+prof+threads+file+ + + When a model was Verilated using :vlopt:`--prof-threads`, sets the + simulation runtime filename to dump to. Defaults to + :file:`profile_threads.dat`. + +.. option:: +verilator+prof+threads+start+ + + When a model was Verilated using :vlopt:`--prof-threads`, the simulation + runtime will wait until $time is at this value (expressed in units of + the time precision), then start the profiling warmup, then + capturing. Generally this should be set to some time that is well within + the normal operation of the simulation, i.e. outside of reset. If 0, the + dump is disabled. Defaults to 1. + +.. option:: +verilator+prof+threads+window+ + + When a model was Verilated using :vlopt:`--prof-threads`, after $time + reaches :vlopt:`+verilator+prof+threads+start+\`, Verilator will + warm up the profiling for this number of eval() calls, then will capture + the profiling of this number of eval() calls. Defaults to 2, which + makes sense for a single-clock-domain module where it's typical to want + to capture one posedge eval() and one negedge eval(). + +.. option:: +verilator+rand+reset+ + + When a model was Verilated using :vlopt:`--x-initial unique + <--x-initial>`, sets the simulation runtime initialization technique. 0 + = Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See + :ref:`Unknown States`. + +.. option:: +verilator+seed+ + + For $random and :vlopt:`--x-initial unique <--x-initial>`, set the + simulation runtime random seed value. If zero or not specified picks a + value from the system random number generator. + +.. option:: +verilator+noassert + + Disable assert checking per runtime argument. This is the same as + calling :code:`Verilated::assertOn(false)` in the model. + +.. option:: +verilator+V + + Shows the verbose version, including configuration information. + +.. option:: +verilator+version + + Displays program version and exits. diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst new file mode 100644 index 000000000..060d80d2d --- /dev/null +++ b/docs/guide/exe_verilator.rst @@ -0,0 +1,1623 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +verilator Arguments +=================== + +The following are the arguments that may be passed to the "verilator" +executable. + +Summary: + + .. include:: ../_build/gen/args_verilator.rst + + +.. option:: + + Specifies the Verilog file containing the top module to be Verilated. + +.. option:: + + Used with :vlopt:`--exe` to specify optional C++ files to be linked in + with the Verilog code. The file path should either be absolute, or + relative to where the make will be executed from, or add to your + makefile's VPATH the appropriate directory to find the file. + + See also :vlopt:`-CFLAGS` and :vlopt:`-LDFLAGS` options, which are + useful when the C++ files need special compiler flags. + +.. option:: + + Specifies optional object or library files to be linked in with the + Verilog code, as a shorthand for :vlopt:`-LDFLAGS \ + <-LDFLAGS>`. The file path should either be absolute, or relative to + where the make will be executed from, or add to your makefile's VPATH + the appropriate directory to find the file. + + If any files are specified in this way, Verilator will include a make + rule that uses these files when linking the module's executable. This + generally is only useful when used with the :vlopt:`--exe` option. + +.. option:: +1364-1995ext+ + +.. option:: +1364-2001ext+ + +.. option:: +1364-2005ext+ + +.. option:: +1800-2005ext+ + +.. option:: +1800-2009ext+ + +.. option:: +1800-2012ext+ + +.. option:: +1800-2017ext+ + + Specifies the language standard to be used with a specific filename + extension, . + + For compatibility with other simulators, see also the synonyms + :vlopt:`+verilog1995ext+\`, :vlopt:`+verilog2001ext+\`, and + :vlopt:`+systemverilogext+\`. + + For any source file, the language specified by these options takes + precedence over any language specified by the + :vlopt:`--default-language` or :vlopt:`--language` options. + + These options take effect in the order they are encountered. Thus the + following would use Verilog 1995 for ``a.v`` and Verilog 2001 for + ``b.v``: + + .. code-block:: bash + + verilator ... +1364-1995ext+v a.v +1364-2001ext+v b.v + + These options are only recommended for legacy mixed language designs, as + the preferable option is to edit the code to repair new keywords, or add + appropriate ```begin_keywords``. + + .. note:: + + ```begin_keywords`` is a SystemVerilog construct, which specifies + *only* the set of keywords to be recognized. This also controls some + error messages that vary between language standards. Note at present + Verilator tends to be overly permissive, e.g. it will accept many + grammar and other semantic extensions which might not be legal when + set to an older standard. + +.. option:: --assert + + Enable all assertions. + +.. option:: --autoflush + + After every $display or $fdisplay, flush the output stream. This + ensures that messages will appear immediately but may reduce + performance. For best performance call :code:`fflush(stdout)` + occasionally in the C++ main loop. Defaults to off, which will buffer + output as provided by the normal C/C++ standard library IO. + +.. option:: --bbox-sys + + Black box any unknown $system task or function calls. System tasks will + simply become no-operations, and system functions will be replaced with + unsized zero. Arguments to such functions will be parsed, but not + otherwise checked. This prevents errors when linting in the presence of + company specific PLI calls. + + Using this argument will likely cause incorrect simulation. + +.. option:: --bbox-unsup + + Black box some unsupported language features, currently UDP tables, the + cmos and tran gate primitives, deassign statements, and mixed edge + errors. This may enable linting the rest of the design even when + unsupported constructs are present. + + Using this argument will likely cause incorrect simulation. + +.. option:: --bin + + Rarely needed. Override the default filename for Verilator itself. + When a dependency (.d) file is created, this filename will become a + source dependency, such that a change in this binary will have make + rebuild the output files. + +.. option:: --build + + After generating the SystemC/C++ code, Verilator will invoke the + toolchain to build the model library (and executable when :vlopt:`--exe` + is also used). Verilator manages the build itself, and for this --build + requires GNU Make to be available on the platform. + +.. option:: -CFLAGS + + Add specified C compiler argument to the generated makefiles. For + multiple flags either pass them as a single argument with space + separators quoted in the shell (:command:`-CFLAGS "-a -b"`), or use + multiple -CFLAGS options (:command:`-CFLAGS -a -CFLAGS -b`). + + When make is run on the generated makefile these will be passed to the + C++ compiler (g++/clang++/msvc++). + +.. option:: --cc + + Specifies C++ without SystemC output mode; see also :vlopt:`--sc` + option. + +.. option:: --cdc + + Permanently experimental. Perform some clock domain crossing checks and + issue related warnings (CDCRSTLOGIC) and then exit; if warnings other + than CDC warnings are needed make a second run with + :vlopt:`--lint-only`. Additional warning information is also written to + the file :file:`__cdc.txt`. + + Currently only checks some items that other CDC tools missed; if you + have interest in adding more traditional CDC checks, please contact the + authors. + +.. option:: --clk + + Sometimes it is quite difficult for Verilator to distinguish clock + signals from other data signals. Occasionally the clock signals can end + up in the checking list of signals which determines if further + evaluation is needed. This will heavily degrade the performance of a + Verilated model. + + With :vlopt:`--clk`, the specified signal-name is taken as a root clock + into the model, then Verilator will mark the signal as clocker and + propagate the clocker attribute automatically to other signals derived + from that. In this way, Verilator will try to avoid taking the clocker + signal into checking list. + + Note signal-name is specified by the RTL hierarchy path. For example, + v.foo.bar. If the signal is the input to top-module, the directly the + signal name. If you find it difficult to find the exact name, try to use + a :option:`/*verilator&32;clocker*/` metacomment in RTL file to mark the + signal directly. + + If clock signals are assigned to vectors and then later used + individually, Verilator will attempt to decompose the vector and connect + the single-bit clock signals directly. This should be transparent to + the user. + +.. option:: --make + + Generates a script for the specified build tool. + + Supported values are ``gmake`` for GNU Make and ``cmake`` for CMake. + Both can be specified together. If no build tool is specified, gmake is + assumed. The executable of gmake can be configured via environment + variable "MAKE". + + When using :vlopt:`--build` Verilator takes over the responsibility of + building the model library/executable. For this reason :option:`--make` + cannot be specified when using :vlopt:`--build`. + +.. option:: --compiler + + Enables workarounds for the specified C++ compiler (list below). + Currently this does not change any performance tuning options, but it may + in the future. + + clang + Tune for clang. This may reduce execution speed as it enables several + workarounds to avoid silly hard-coded limits in clang. This includes + breaking deep structures as for msvc as described below. + + gcc + Tune for GNU C++, although generated code should work on almost any + compliant C++ compiler. Currently the default. + + msvc + Tune for Microsoft Visual C++. This may reduce execution speed as it + enables several workarounds to avoid silly hard-coded limits in + MSVC++. This includes breaking deeply nested parenthesized + expressions into sub-expressions to avoid error C1009, and breaking + deep blocks into functions to avoid error C1061. + +.. option:: --converge-limit + + Rarely needed. Specifies the maximum number of runtime iterations + before creating a model failed to converge error. Defaults to 100. + +.. option:: --coverage + + Enables all forms of coverage, alias for :vlopt:`--coverage-line` + :vlopt:`--coverage-toggle` :vlopt:`--coverage-user`. + +.. option:: --coverage-line + + Enables basic block line coverage analysis. See :ref:`Line Coverage`. + +.. option:: --coverage-max-width + + Rarely needed. Specify the maximum bit width of a signal that is + subject to toggle coverage. Defaults to 256, as covering large vectors + may greatly slow coverage simulations. + +.. option:: --coverage-toggle + + Enables adding signal toggle coverage. See :ref:`Toggle Coverage`. + +.. option:: --coverage-underscore + + Enable coverage of signals that start with an underscore. Normally, + these signals are not covered. See also :vlopt:`--trace-underscore` + option. + +.. option:: --coverage-user + + Enables adding user inserted functional coverage. See :ref:`User Coverage`. + +.. option:: -D= + + Defines the given preprocessor symbol. Similar to :vlopt:`+define + <+define+>`, but does not allow multiple definitions with a single + option using plus signs. "+define" is fairly standard across Verilog + tools while "-D" is similar to :command:`gcc -D`. + +.. option:: --debug + + Run under debug. + + * Select the debug executable of Verilator (if available), this + generally is a less-optimized binary with symbols present (so GDB can be used on it). + * Enable debugging messages (equivalent to :vlopt:`--debugi 3 <--debugi>`). + * Enable internal assertions (equivalent to :vlopt:`--debug-check`). + * Enable intermediate form dump files (equivalent to :vlopt:`--dump-treei 3 + <--dump-treei>`). + * Leak to make node numbers unique (equivalent to :vlopt:`--debug-leak + <--no-debug-leak>`. + * Call abort() instead of exit() if there are any errors (so GDB can see + the program state). + +.. option:: --debug-check + + Rarely needed. Enable internal debugging assertion checks, without + changing debug verbosity. Enabled automatically with :vlopt:`--debug` + option. + +.. option:: --no-debug-leak + + In :vlopt:`--debug` mode, by default Verilator intentionally leaks + AstNode instances instead of freeing them, so that each node pointer is + unique in the resulting tree files and dot files. + + This option disables the leak. This may avoid out-of-memory errors when + Verilating large models in :vlopt:`--debug` mode. + + Outside of :vlopt:`--debug` mode, AstNode instances should never be + leaked and this option has no effect. + +.. option:: --debugi + + Rarely needed - for developer use. Set internal debugging level + globally to the specified debug level (1-10). Higher levels produce more + detailed messages. + +.. option:: --debugi- + + Rarely needed - for developer use. Set the specified Verilator source + file to the specified level (e.g. :vlopt:`--debugi-V3Width 9 + <--debugi>`). Higher levels produce more detailed messages. See + :vlopt:`--debug` for other implications of enabling debug. + +.. option:: --default-language + + Select the language to be used by default when first processing each + Verilog file. The language value must be "VAMS", "1364-1995", + "1364-2001", "1364-2001-noconfig", "1364-2005", "1800-2005", + "1800-2009", "1800-2012", "1800-2017", or "1800+VAMS". + + Any language associated with a particular file extension (see the + various +*\ ext+ options) will be used in preference to the + language specified by :vlopt:`--default-language`. + + The :vlopt:`--default-language` is only recommended for legacy code + using the same language in all source files, as the preferable option is + to edit the code to repair new keywords, or add appropriate + :code:`\`begin_keywords`. For legacy mixed language designs, the various + ``+ext+`` options should be used. + + If no language is specified, either by this option or ``+ext+`` + options, then the latest SystemVerilog language (IEEE 1800-2017) is + used. + +.. option:: +define+= + +.. option:: +define+=[+=][...] + + Defines the given preprocessor symbol, or multiple symbols if separated + by plus signs. Similar to :vlopt:`-D <-D>`; +define is fairly + standard across Verilog tools while :vlopt:`-D <-D>` is similar to + :command:`gcc -D`. + +.. option:: --dpi-hdr-only + + Only generate the DPI header file. This option has no effect on the + name or location of the emitted DPI header file, it is output in + :vlopt:`--Mdir` as it would be without this option. + +.. option:: --dump-defines + + With :vlopt:`-E`, suppress normal output, and instead print a list of + all defines existing at the end of pre-processing the input + files. Similar to GCC "-dM" option. This also gives you a way of finding + out what is predefined in Verilator using the command: + + .. code-block:: bash + + touch foo.v ; verilator -E --dump-defines foo.v + +.. option:: --dump-tree + + Rarely needed. Enable writing .tree debug files with dumping level 3, + which dumps the standard critical stages. For details on the format see + the Verilator Internals manual. :vlopt:`--dump-tree` is enabled + automatically with :vlopt:`--debug`, so :vlopt:`--debug --no-dump-tree + <--dump-tree>` may be useful if the dump files are large and not + desired. + +.. option:: --dump-treei + +.. option:: --dump-treei- + + Rarely needed - for developer use. Set internal tree dumping level + globally to a specific dumping level or set the specified Verilator + source file to the specified tree dumping level (e.g. + :vlopt:`--dump-treei-V3Order 9 <--dump-treei>`). Level 0 disables dumps + and is equivalent to :vlopt:`--no-dump-tree <--dump-tree>`. Level 9 + enables dumping of every stage. + +.. option:: --dump-tree-addrids + + Rarely needed - for developer use. Replace AST node addresses with + short identifiers in tree dumps to enhance readability. Each unique + pointer value is mapped to a unique identifier, but note that this is + not necessarily unique per node instance as an address might get reused + by a newly allocated node after a node with the same address has been + dumped then freed. + +.. option:: -E + + Preprocess the source code, but do not compile, similar to C++ + preprocessing using :command:`gcc -E`. Output is written to standard + out. Beware of enabling debugging messages, as they will also go to + standard out. + + See also :vlopt:`--dump-defines`, :vlopt:`-P`, and + :vlopt:`--pp-comments` options. + +.. option:: --error-limit + + After this number of errors are encountered during Verilator run, exit. + Warnings are not counted in this limit. Defaults to 50. + + Does not affect simulation runtime errors, for those see + :vlopt:`+verilator+error+limit+\`. + +.. option:: --exe + + Generate an executable. You will also need to pass additional .cpp + files on the command line that implement the main loop for your + simulation. + +.. option:: -F + + Read the specified file, and act as if all text inside it was specified + as command line arguments. Any relative paths are relative to the + directory containing the specified file. See also :vlopt:`-f` + option. Note :option:`-F` is fairly standard across Verilog tools. + +.. option:: -f + + Read the specified file, and act as if all text inside it was specified + as command line arguments. Any relative paths are relative to the + current directory. See also :vlopt:`-F` option. Note :option:`-f` is + fairly standard across Verilog tools. + + The file may contain :code:`//` comments which are ignored to the end of + the line. Any :code:`$VAR`, :code:`$(VAR)`, or :code:`${VAR}` will be + replaced with the specified environment variable. + +.. option:: -FI + + Force include of the specified C++ header file. All generated C++ files + will insert a #include of the specified file before any other + includes. The specified file might be used to contain define prototypes + of custom :code:`VL_VPRINTF` functions, and may need to include + :file:`verilatedos.h` as this file is included before any other standard + includes. + +.. option:: --flatten + + Force flattening of the design's hierarchy, with all modules, tasks and + functions inlined. Typically used with :vlopt:`--xml-only`. Note + flattening large designs may require significant CPU time, memory and + storage. + +.. option:: -G= + + Overwrites the given parameter of the toplevel module. The value is + limited to basic data literals: + + Verilog integer literals + The standard Verilog integer literals are supported, so values like + 32'h8, 2'b00, 4 etc. are allowed. Care must be taken that the single + quote (I') is properly escaped in an interactive shell, e.g., + as :code:`-GWIDTH=8'hx`. + + C integer literals + It is also possible to use C integer notation, including hexadecimal + (0x..), octal (0..) or binary (0b..) notation. + + Double literals + Double literals must be one of the following styles: + - contains a dot (.) (e.g. 1.23) + - contains an exponent (e/E) (e.g. 12e3) + - contains p/P for hexadecimal floating point in C99 (e.g. 0x123.ABCp1) + + Strings + Strings must be in double quotes (""). They must be escaped properly + on the command line, e.g. as :code:`-GSTR="\"My String\""` or + :code:`-GSTR='"My String"'`. + +.. option:: --gate-stmts + + Rarely needed. Set the maximum number of statements that may be present + in an equation for the gate substitution optimization to inline that + equation. + +.. option:: --gdb + + Run Verilator underneath an interactive GDB (or VERILATOR_GDB + environment variable value) session. See also :vlopt:`--gdbbt` option. + +.. option:: --gdbbt + + If :vlopt:`--debug` is specified, run Verilator underneath a GDB process + and print a backtrace on exit, then exit GDB immediately. Without + :vlopt:`--debug` or if GDB doesn't seem to work, this flag is ignored. + Intended for easy creation of backtraces by users; otherwise see the + :vlopt:`--gdb` option. + +.. option:: --generate-key + + Generate a true-random key suitable for use with :vlopt:`--protect-key`, + print it, and exit immediately. + +.. option:: --getenv + + If the variable is declared in the environment, print it and exit + immediately. Otherwise, if it's built into Verilator + (e.g. VERILATOR_ROOT), print that and exit immediately. Otherwise, print + a newline and exit immediately. This can be useful in makefiles. See + also :vlopt:`-V`, and the various :file:`*.mk` files. + +.. option:: --help + + Displays this message and program version and exits. + +.. option:: --hierarchical + + Enable hierarchical Verilation otherwise + :option:`/*verilator&32;hier_block*/` metacomment is ignored. See + :ref:`Hierarchical Verilation`. + +.. option:: -I

+ + See :vlopt:`-y`. + +.. option:: --if-depth + + Rarely needed. Set the depth at which the IFDEPTH warning will fire, + defaults to 0 which disables this warning. + +.. option:: +incdir+ + + See :vlopt:`-y`. + +.. option:: --inhibit-sim + + Rarely needed and deprecated. Create a :code:`inhibitSim(bool)` + function to enable and disable evaluation. This allows an upper level + testbench to disable modules that are not important in a given + simulation, without needing to recompile or change the SystemC modules + instantiated. + +.. option:: --inline-mult + + Tune the inlining of modules. The default value of 2000 specifies that up + to 2000 new operations may be added to the model by inlining, if more than + this number of operations would result, the module is not inlined. Larger + values, or a value < 1 will inline everything, will lead to longer compile + times, but potentially faster simulation speed. This setting is ignored + for very small modules; they will always be inlined, if allowed. + +.. option:: -j [] + + Specify the level of parallelism for :vlopt:`--build`. The must + be a positive integer specifying the maximum number of parallel build + jobs, or can be omitted. When is omitted, the build will not try + to limit the number of parallel build jobs but attempt to execute all + independent build steps in parallel. + +.. option:: -LDFLAGS + + Add specified C linker arguments to the generated makefiles. For multiple + flags either pass them as a single argument with space separators quoted + in the shell (``-LDFLAGS "-a -b"``), or use multiple -LDFLAGS arguments + (``-LDFLAGS -a -LDFLAGS -b``). + + When make is run on the generated makefile these will be passed to the + C++ linker (ld) **after** the primary file being linked. This flag is + called :vlopt:`-LDFLAGS` as that's the traditional name in simulators; + it's would have been better called LDLIBS as that's the Makefile + variable it controls. (In Make, LDFLAGS is before the first object, + LDLIBS after. -L libraries need to be in the Make variable LDLIBS, not + LDFLAGS.) + +.. option:: --l2-name + + Instead of using the module name when showing Verilog scope, use the + name provided. This allows simplifying some Verilator-embedded modeling + methodologies. Default is an l2-name matching the top module. The + default before Verilator 3.884 was ``--l2-name v``. + + For example, the program :code:`module t; initial $display("%m"); + endmodule` will show by default "t". With ``--l2-name v`` it will print + "v". + +.. option:: --language + + A synonym for :vlopt:`--default-language`, for compatibility with other + tools and earlier versions of Verilator. + +.. option:: +libext+[+][...] + + Specify the extensions that should be used for finding modules. If for + example module "my" is referenced, look in :file:`my.`. Note + "+libext+" is fairly standard across Verilog tools. Defaults to + ".v+.sv". + +.. option:: --lint-only + + Check the files for lint violations only, do not create any other + output. + + You may also want the :vlopt:`-Wall` option to enable messages that are + considered stylistic and not enabled by default. + + If the design is not to be completely Verilated see also the + :vlopt:`--bbox-sys` and :vlopt:`--bbox-unsup` options. + +.. option:: -MAKEFLAGS + + When using :vlopt:`--build`, add the specified argument to the invoked + make command line. For multiple flags either pass them as a single + argument with space separators quoted in the shell (e.g. ``-MAKEFLAGS + "-a -b"``), or use multiple -MAKEFLAGS arguments + (e.g. ``-MAKEFLAGS -l -MAKEFLAGS -k``). Use of this option should not be + required for simple builds using the host toolchain. + +.. option:: --max-num-width + + Set the maximum number literal width (e.g. in 1024'd22 this it the + 1024). Defaults to 64K. + +.. option:: --MMD =item --no-MMD + + Enable/disable creation of .d dependency files, used for make dependency + detection, similar to gcc -MMD option. By default this option is + enabled for :vlopt:`--cc` or :vlopt:`--sc` modes. + +.. option:: --MP + + When creating .d dependency files with :vlopt:`--MMD` option, make phony + targets. Similar to :command:`gcc -MP` option. + +.. option:: --Mdir + + Specifies the name of the Make object directory. All generated files + will be placed in this directory. If not specified, "obj_dir" is used. + The directory is created if it does not exist and the parent directories + exist; otherwise manually create the Mdir before calling Verilator. + +.. option:: --mod-prefix + + Specifies the name to prepend to all lower level classes. Defaults to + the same as :vlopt:`--prefix`. + +.. option:: --no-clk + + Prevent the specified signal from being marked as clock. See + :vlopt:`--clk`. + +.. option:: --no-decoration + + When creating output Verilated code, minimize comments, white space, + symbol names and other decorative items, at the cost of greatly reduced + readability. This may assist C++ compile times. This will not typically + change the ultimate model's performance, but may in some cases. + +.. option:: --no-pins64 + + Backward compatible alias for :vlopt:`--pins-bv 33 <--pins-bv>`. + +.. option:: --no-relative-cfuncs + + Deprecated. + +.. option:: --no-skip-identical =item --skip-identical + + Rarely needed. Disables or enables skipping execution of Verilator if + all source files are identical, and all output files exist with newer + dates. By default this option is enabled for :vlopt:`--cc` or + :vlopt:`--sc` modes only. + +.. option:: +notimingchecks + + Ignored for compatibility with other simulators. + +.. option:: -O0 + + Disables optimization of the model. + +.. option:: -O3 + + Enables slow optimizations for the code Verilator itself generates (as + opposed to :vlopt:`-CFLAGS -O3 <-CFLAGS>` which effects the C compiler's + optimization. :vlopt:`-O3` may improve simulation performance at the + cost of compile time. This currently sets :vlopt:`--inline-mult -1 + <--inline-mult>`. + +.. option:: -O + + Rarely needed. Enables or disables a specific optimizations, with the + optimization selected based on the letter passed. A lowercase letter + disables an optimization, an upper case letter enables it. This is + intended for debugging use only; see the source code for + version-dependent mappings of optimizations to -O letters. + +.. option:: -o + + Specify the name for the final executable built if using :vlopt:`--exe`. + Defaults to the :vlopt:`--prefix` if not specified. + +.. option:: --no-order-clock-delay + + Rarely needed. Disables a bug fix for ordering of clock enables with + delayed assignments. This option should only be used when suggested by + the developers. + +.. option:: --output-split + + Enables splitting the output .cpp files into multiple outputs. When a + C++ file exceeds the specified number of operations, a new file will be + created at the next function boundary. In addition, if the total output + code size exceeds the specified value, VM_PARALLEL_BUILDS will be set to + 1 by default in the generated make files, making parallel compilation + possible. Using :vlopt:`--output-split` should have only a trivial + impact on model performance. But can greatly improve C++ compilation + speed. The use of "ccache" (set for you if present at configure time) is + also more effective with this option. + + This option is on by default with a value of 20000. To disable, pass with a + value of 0. + +.. option:: --output-split-cfuncs + + Enables splitting functions in the output .cpp files into multiple + functions. When a generated function exceeds the specified number of + operations, a new function will be created. With + :vlopt:`--output-split`, this will enable the C++ compiler to compile + faster, at a small loss in performance that gets worse with decreasing + split values. Note that this option is stronger than + :vlopt:`--output-split` in the sense that :vlopt:`--output-split` will + not split inside a function. + + Defaults to the value of :vlopt:`--output-split`, unless explicitly + specified. + +.. option:: --output-split-ctrace + + Similar to :vlopt:`--output-split-cfuncs`, enables splitting trace + functions in the output .cpp files into multiple functions. + + Defaults to the value of :vlopt:`--output-split`, unless explicitly + specified. + +.. option:: -P + + With :vlopt:`-E`, disable generation of :code:`&96;line` markers and + blank lines, similar to :command:`gcc -P`. + +.. option:: --pins64 + + Backward compatible alias for :vlopt:`--pins-bv 65 <--pins-bv>`. Note + that's a 65, not a 64. + +.. option:: --pins-bv + + Specifies SystemC inputs/outputs of greater than or equal to + bits wide should use sc_bv's instead of uint32/vluint64_t's. The + default is "--pins-bv 65", and the value must be less than or equal + to 65. Versions before Verilator 3.671 defaulted to "--pins-bv 33". + The more sc_bv is used, the worse for performance. Use the + :option:`/*verilator&32;sc_bv*/` metacomment to select specific ports to + be sc_bv. + +.. option:: --pins-sc-uint + + Specifies SystemC inputs/outputs of greater than 2 bits wide should use + sc_uint between 2 and 64. When combined with the + :vlopt:`--pins-sc-biguint` combination, it results in sc_uint being used + between 2 and 64 and sc_biguint being used between 65 and 512. + +.. option:: --pins-sc-biguint + + Specifies SystemC inputs/outputs of greater than 65 bits wide should use + sc_biguint between 65 and 512, and sc_bv from 513 upwards. When + combined with the :vlopt:`--pins-sc-uint` combination, it results in + sc_uint being used between 2 and 64 and sc_biguint being used between 65 + and 512. + +.. option:: --pins-uint8 + + Specifies SystemC inputs/outputs that are smaller than the + :vlopt:`--pins-bv` setting and 8 bits or less should use uint8_t instead + of uint32_t. Likewise pins of width 9-16 will use uint16_t instead of + uint32_t. + +.. option:: --pipe-filter + + Rarely needed. Verilator will spawn the specified command as a + subprocess pipe, to allow the command to perform custom edits on the + Verilog code before it reaches Verilator. + + Before reading each Verilog file, Verilator will pass the file name to + the subprocess' stdin with :code:`read ""`. The filter may + then read the file and perform any filtering it desires, and feeds the + new file contents back to Verilator on stdout by first emitting a line + defining the length in bytes of the filtered output + :code:`Content-Length: `, followed by the new filtered + contents. Output to stderr from the filter feeds through to Verilator's + stdout and if the filter exits with non-zero status Verilator + terminates. See the file:`t/t_pipe_filter` test for an example. + + To debug the output of the filter, try using the :vlopt:`-E` option to + see preprocessed output. + +.. option:: --pp-comments + + With :vlopt:`-E`, show comments in preprocessor output. + +.. option:: --prefix + + Specifies the name of the top level class and makefile. Defaults to V + prepended to the name of the :vlopt:`--top` option, or V prepended to + the first Verilog filename passed on the command line. + +.. option:: --prof-cfuncs + + Modify the created C++ functions to support profiling. The functions + will be minimized to contain one "basic" statement, generally a single + always block or wire statement. (Note this will slow down the + executable by ~5%.) Furthermore, the function name will be suffixed + with the basename of the Verilog module and line number the statement + came from. This allows gprof or oprofile reports to be correlated with + the original Verilog source statements. See :ref:`Profiling`. + +.. option:: --prof-threads + + Enable gantt chart data collection for threaded builds. See :ref:`Thread + Profiling`. + +.. option:: --protect-key + + Specifies the private key for :vlopt:`--protect-ids`. For best security + this key should be 16 or more random bytes, a reasonable secure choice + is the output of :command:`verilator --generate-key` . Typically, a key + would be created by the user once for a given protected design library, + then every Verilator run for subsequent versions of that library would + be passed the same :vlopt:`--protect-key`. Thus, if the input Verilog is + similar between library versions (Verilator runs), the Verilated code + will likewise be mostly similar. + + If :vlopt:`--protect-key` is not specified and a key is needed, + Verilator will generate a new key for every Verilator run. As the key is + not saved, this is best for security, but means every Verilator run will + give vastly different output even for identical input, perhaps harming + compile times (and certainly thrashing any "ccache"). + +.. option:: --protect-ids + + Hash any private identifiers (variable, module, and assertion block + names that are not on the top level) into hashed random-looking + identifiers, resulting after compilation in protected library binaries + that expose less design information. This hashing uses the provided or + default :vlopt:`--protect-key`, see important details there. + + Verilator will also create a :file:`__idmap.xml` file which + contains the mapping from the hashed identifiers back to the original + identifiers. This idmap file is to be kept private, and is to assist + mapping any simulation runtime design assertions, coverage, or trace + information, which will report the hashed identifiers, back to the + original design's identifier names. + + Using DPI imports/exports is allowed and generally relatively safe in + terms of information disclosed, which is limited to the DPI function + prototyptes. Use of the VPI is not recommended as many design details + may be exposed, and an INSECURE warning will be issued. + +.. option:: --protect-lib + + Produces C++, Verilog wrappers and a Makefile which can in turn produce + a DPI library which can be used by Verilator or other simulators along + with the corresponding Verilog wrapper. The Makefile will build both a + static and dynamic version of the library named :file:`lib.a` and + :file:`lib.so` respectively. This is done because some simulators + require a dynamic library, but the static library is arguably easier to + use if possible. :vlopt:`--protect-lib` implies :vlopt:`--protect-ids`. + + This allows for the secure delivery of sensitive IP without the need for + encrypted RTL (i.e. IEEE P1735). See :file:`examples/make_protect_lib` + in the distribution for a demonstration of how to build and use the DPI + library. + + When using :vlopt:`--protect-lib` it is advised to also use + :vlopt:`--timescale-override /1fs <--timescale-override>` to ensure the + model has a time resolution that is always compatible with the time + precision of the upper instantiating module. + +.. option:: --private + + Opposite of :vlopt:`--public`. Is the default; this option exists for + backwards compatibility. + +.. option:: --public + + This is only for historical debug use. Using it may result in + mis-simulation of generated clocks. + + Declares all signals and modules public. This will turn off signal + optimizations as if all signals had a :option:`/*verilator&32;public*/` + metacomments and inlining. This will also turn off inlining as if all + modules had a :option:`/*verilator&32;public_module*/`, unless the + module specifically enabled it with + :option:`/*verilator&32;inline_module*/`. + +.. option:: --public-flat-rw + + Declares all variables, ports and wires public as if they had + :code:`/*verilator public_flat_rw @ + ()*/` metacomments. This will make them + VPI accessible by their flat name, but not turn off module inlining. + This is particularly useful in combination with :vlopt:`--vpi`. This may + also in some rare cases result in mis-simulation of generated clocks. + Instead of this global option, marking only those signals that need + public_flat_rw is typically significantly better performing. + +.. option:: -pvalue+= + + Overwrites the given parameter(s) of the toplevel module. See :vlopt:`-G + <-G>` for a detailed description. + +.. option:: --quiet-exit + + When exiting due to an error, do not display the "Exiting due to Errors" + nor "Command Failed" messages. + +.. option:: --relative-includes + + When a file references an include file, resolve the filename relative to + the path of the referencing file, instead of relative to the current + directory. + +.. option:: --report-unoptflat + + Extra diagnostics for UNOPTFLAT warnings. This includes for each loop, + the 10 widest variables in the loop, and the 10 most fanned out + variables in the loop. These are candidates for splitting into multiple + variables to break the loop. + + In addition produces a GraphViz DOT file of the entire strongly + connected components within the source associated with each loop. This + is produced irrespective of whether :vlopt:`--dump-tree` is set. Such + graphs may help in analyzing the problem, but can be very large indeed. + + Various commands exist for viewing and manipulating DOT files. For + example the "dot" command can be used to convert a DOT file to a PDF for + printing. For example: + + .. code-block:: bash + + dot -Tpdf -O Vt_unoptflat_simple_2_35_unoptflat.dot + + will generate a PDF :file:`Vt_unoptflat_simple_2_35_unoptflat.dot.pdf` + from the DOT file. + + As an alternative, the :command:`xdot` command can be used to view DOT + files interactively: + + .. code-block:: bash + + xdot Vt_unoptflat_simple_2_35_unoptflat.dot + +.. option:: --rr + + Run Verilator and record with the :command:`rr` command. See: + rr-project.org. + +.. option:: --savable + + Enable including save and restore functions in the generated model. See + :ref:`Save/Restore`. + +.. option:: --sc + + Specifies SystemC output mode; see also :vlopt:`--cc` option. + +.. option:: --stats + + Creates a dump file with statistics on the design in + :file:`__stats.txt`. + +.. option:: --stats-vars + + Creates more detailed statistics, including a list of all the variables + by size (plain :vlopt:`--stats` just gives a count). See + :vlopt:`--stats`, which is implied by this. + +.. option:: --structs-packed + + Converts all unpacked structures to packed structures and issues a + UNPACKED warning. Currently this is the default and + :vlopt:`--no-structs-packed <--structs-packed>` will not work. + Specifying this option allows for forward compatibility when a future + version of Verilator no longer always packs unpacked structures. + +.. option:: -sv + + Specifies SystemVerilog language features should be enabled; equivalent + to :vlopt:`--language 1800-2017 <--language>`. This option is selected + by default, it exists for compatibility with other simulators. + +.. option:: +systemverilogext+ + + A synonym for :vlopt:`+1800-2017ext+\`. + +.. option:: --threads + +.. option:: --no-threads + + With "--threads 0" or "--no-threads", the default, the generated model + is not thread safe. With "--threads 1", the generated model is single + threaded but may run in a multithreaded environment. With "--threads N", + where N >= 2, the model is generated to run multithreaded on up to N + threads. See :ref:`Multithreading`. + +.. option:: --threads-dpi all + +.. option:: --threads-dpi none + +.. option:: --threads-dpi pure + + When using :vlopt:`--threads`, controls which DPI imported tasks and + functions are considered thread safe. + + With "--threads-dpi all", + Enable Verilator to assume all DPI imports are threadsafe, and to use + thread-local storage for communication with DPI, potentially improving + performance. Any DPI libraries need appropriate mutexes to avoid + undefined behavior. + + With "--threads-dpi none", + Verilator assume DPI imports are not thread safe, and Verilator will + serialize calls to DPI imports by default, potentially harming + performance. + + With "--threads-dpi pure", the default, + Verilator assumes DPI pure imports are threadsafe, but non-pure DPI + imports are not. + +.. option:: --threads-max-mtasks + + Rarely needed. When using :vlopt:`--threads`, specify the number of + mtasks the model is to be partitioned into. If unspecified, Verilator + approximates a good value. + +.. option:: --timescale / + + Sets default timescale, timeunit and timeprecision for when "`timescale" + does not occur before a given module. Default is "1ps/1ps" (to match + SystemC). This is overridden by :vlopt:`--timescale-override`. + +.. option:: --timescale-override / + +.. option:: --timescale-override / + + Overrides all "\`timescale"s in sources. The timeunit may be left empty + to specify only to override the timeprecision, e.g. "/1fs". + + The time precision must be consistent with SystemC's + "sc_set_time_resolution()", or the C++ code instantiating the Verilated + module. As "1fs" is the finest time precision it may be desirable to + always use a precision of "1fs". + +.. option:: --top + +.. option:: --top-module + + When the input Verilog contains more than one top level module, + specifies the name of the Verilog module to become the top level module, + and sets the default for :vlopt:`--prefix` if not explicitly specified. + This is not needed with standard designs with only one top. See also + :option:`MULTITOP` warning. + +.. option:: --trace + + Adds waveform tracing code to the model using VCD format. This overrides + :vlopt:`--trace-fst`. + + Verilator will generate additional :file:`__Trace*.cpp` files + that will need to be compiled. In addition :file:`verilated_vcd_sc.cpp` + (for SystemC traces) or :file:`verilated_vcd_c.cpp` (for both) must be + compiled and linked in. If using the Verilator generated Makefiles, + these files will be added to the source file lists for you. If you are + not using the Verilator Makefiles, you will need to add these to your + Makefile manually. + + Having tracing compiled in may result in some small performance losses, + even when tracing is not turned on during model execution. + + See also :vlopt:`--trace-threads` option. + +.. option:: --trace-coverage + + With :vlopt:`--trace` and ``--coverage-*``, enable tracing to include a + traced signal for every :vlopt:`--coverage-line` or + :vlopt:`--coverage-user`\ -inserted coverage point, to assist in + debugging coverage items. Note :vlopt:`--coverage-toggle` does not get + additional signals added, as the original signals being toggle-analyzed + are already visible. + + The added signal will be a 32-bit value which will increment on each + coverage occurrence. Due to this, this option may greatly increase trace + file sizes and reduce simulation speed. + +.. option:: --trace-depth + + Specify the number of levels deep to enable tracing, for example + :vlopt:`--trace-depth 1 <--trace-depth>` to only see the top level's + signals. Defaults to the entire model. Using a small number will + decrease visibility, but greatly improve simulation performance and + trace file size. + +.. option:: --trace-fst + + Enable FST waveform tracing in the model. This overrides + :vlopt:`--trace`. See also :vlopt:`--trace-threads` option. + +.. option:: --trace-max-array *depth* + + Rarely needed. Specify the maximum array depth of a signal that may be + traced. Defaults to 32, as tracing large arrays may greatly slow traced + simulations. + +.. option:: --trace-max-width *width* + + Rarely needed. Specify the maximum bit width of a signal that may be + traced. Defaults to 256, as tracing large vectors may greatly slow + traced simulations. + +.. option:: --no-trace-params + + Disable tracing of parameters. + +.. option:: --trace-structs + + Enable tracing to show the name of packed structure, union, and packed + array fields, rather than a single combined packed bus. Due to VCD file + format constraints this may result in significantly slower trace times + and larger trace files. + +.. option:: --trace-threads *threads* + + Enable waveform tracing using separate threads. This is typically faster + in simulation runtime but uses more total compute. This option is + independent of, and works with, both :vlopt:`--trace` and + :vlopt:`--trace-fst`. Different trace formats can take advantage of + more trace threads to varying degrees. Currently VCD tracing can utilize + at most "--trace-threads 1", and FST tracing can utilize at most + "--trace-threads 2". This overrides :vlopt:`--no-threads` . + +.. option:: --trace-underscore + + Enable tracing of signals that start with an underscore. Normally, these + signals are not output during tracing. See also + :vlopt:`--coverage-underscore` option. + +.. option:: -U + + Undefines the given preprocessor symbol. + +.. option:: --unroll-count + + Rarely needed. Specifies the maximum number of loop iterations that may be + unrolled. See also :option:`BLKLOOPINIT` warning. + +.. option:: --unroll-stmts *statements* + + Rarely needed. Specifies the maximum number of statements in a loop for + that loop to be unrolled. See also :option:`BLKLOOPINIT` warning. + +.. option:: --unused-regexp *regexp* + + Rarely needed. Specifies a simple regexp with \* and ? that if a signal + name matches will suppress the UNUSED warning. Defaults to + "\*unused\*". Setting it to "" disables matching. + +.. option:: -V + + Shows the verbose version, including configuration information compiled + into Verilator. (Similar to :command:`perl -V`.) See also + :vlopt:`--getenv` option. + +.. option:: -v *filename* + + Read the filename as a Verilog library. Any modules in the file may be + used to resolve instances in the top level module, else ignored. Note + "-v" is fairly standard across Verilog tools. + +.. option:: --no-verilate + + When using :vlopt:`--build`, disable generation of C++/SystemC code, and + execute only the build. This can be useful for rebuilding Verilated code + produced by a previous invocation of Verilator. + +.. option:: +verilog1995ext+ + + Synonym for :vlopt:`+1364-1995ext+\`. + +.. option:: +verilog2001ext+ + + Synonym for :vlopt:`+1364-2001ext+\`. + +.. option:: --version + + Displays program version and exits. + +.. option:: --vpi + + Enable use of VPI and linking against the :file:`verilated_vpi.cpp` files. + +.. option:: --waiver-output *filename* + + Generate a waiver file which contains all waiver statements to suppress + the warnings emitted during this Verilator run. This in particular is + useful as a starting point for solving linter warnings or suppressing + them systematically. + + The generated file is in the Verilator Configuration format, see + :ref:`Configuration Files`, and can directly be consumed by + Verilator. The standard file extension is ".vlt". + +.. option:: -Wall + + Enable all code style warnings, including code style warnings that are + normally disabled by default. Equivalent to :vlopt:`-Wwarn-lint` + :vlopt:`-Wwarn-style`. Excludes some specialty warnings, + i.e. IMPERFECTSCH. + +.. option:: -Werror- + + Promote the specified warning message into an error message. This is + generally to discourage users from violating important site-wide rules, + for example "-Werror-NOUNOPTFLAT". + +.. option:: -Wfuture- + + Rarely needed. Suppress unknown Verilator comments or warning messages + with the given message code. This is used to allow code written with + pragmas for a later version of Verilator to run under a older version; + add "-Wfuture-" arguments for each message code or comment that the new + version supports which the older version does not support. + +.. option:: -Wno- + + Disable the specified warning/error message. This will override any + lint_on directives in the source, i.e. the warning will still not be + printed. + +.. option:: -Wno-context + + Disable showing the suspected context of the warning message by quoting + the source text at the suspected location. This can be used to appease + tools which process the warning messages but may get confused by lines + from the original source. + +.. option:: -Wno-fatal + + When warnings are detected, print them, but do not terminate Verilator. + + Having warning messages in builds can be sloppy. It is recommended you + cleanup your code, use inline lint_off, or use ``-Wno-...`` options + rather than using this option. + +.. option:: -Wno-lint + + Disable all lint related warning messages, and all style warnings. This is + equivalent to ``-Wno-ALWCOMBORDER -Wno-BSSPACE -Wno-CASEINCOMPLETE + -Wno-CASEOVERLAP -Wno-CASEX -Wno-CASTCONST -Wno-CASEWITHX -Wno-CMPCONST -Wno-COLONPLUS + -Wno-ENDLABEL -Wno-IMPLICIT -Wno-LITENDIAN -Wno-PINCONNECTEMPTY + -Wno-PINMISSING -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNSIGNED -Wno-UNUSED + -Wno-WIDTH`` plus the list shown for Wno-style. + + It is strongly recommended you cleanup your code rather than using this + option, it is only intended to be use when running test-cases of code + received from third parties. + +.. option:: -Wno-style + + Disable all code style related warning messages (note by default they are + already disabled). This is equivalent to ``-Wno-DECLFILENAME -Wno-DEFPARAM + -Wno-EOFNEWLINE -Wno-IMPORTSTAR -Wno-INCABSPATH -Wno-PINCONNECTEMPTY + -Wno-PINNOCONNECT -Wno-SYNCASYNCNET -Wno-UNDRIVEN -Wno-UNUSED + -Wno-VARHIDDEN``. + +.. option:: -Wpedantic + + Warn on any construct demanded by IEEE, and disable all Verilator + extensions that may interfere with IEEE compliance to the standard + defined with :vlopt:`--default-language` (etc). Similar to + :command:`gcc -Wpedantic`. Rarely used, and intended only for strict + compliance tests. + +.. option:: -Wwarn- + + Enables the specified warning message. + +.. option:: -Wwarn-lint + + Enable all lint related warning messages (note by default they are already + enabled), but do not affect style messages. This is equivalent to + ``-Wwarn-ALWCOMBORDER -Wwarn-BSSPACE -Wwarn-CASEINCOMPLETE + -Wwarn-CASEOVERLAP -Wwarn-CASEX -Wwarn-CASTCONST -Wwarn-CASEWITHX -Wwarn-CMPCONST + -Wwarn-COLONPLUS -Wwarn-ENDLABEL -Wwarn-IMPLICIT -Wwarn-LITENDIAN + -Wwarn-PINMISSING -Wwarn-REALCVT -Wwarn-UNSIGNED -Wwarn-WIDTH``. + +.. option:: -Wwarn-style + + Enable all code style related warning messages. This is equivalent to + ``-Wwarn ASSIGNDLY -Wwarn-DECLFILENAME -Wwarn-DEFPARAM -Wwarn-EOFNEWLINE + -Wwarn-INCABSPATH -Wwarn-PINNOCONNECT -Wwarn-SYNCASYNCNET -Wwarn-UNDRIVEN + -Wwarn-UNUSED -Wwarn-VARHIDDEN``. + +.. option:: --x-assign 0 + +.. option:: --x-assign 1 + +.. option:: --x-assign fast (default) + +.. option:: --x-assign unique + + Controls the two-state value that is substituted when an explicit X + value is encountered in the source. "--x-assign fast", the default, + converts all Xs to whatever is best for performance. "--x-assign 0" + converts all Xs to 0s, and is also fast. "--x-assign 1" converts all Xs + to 1s, this is nearly as fast as 0, but more likely to find reset bugs + as active high logic will fire. Using "--x-assign unique" will result in + all explicit Xs being replaced by a constant value determined at + runtime. The value is determined by calling a function at initialization + time. This enables randomization of Xs with different seeds on different + executions. This method is the slowest, but safest for finding reset + bugs. + + If using "--x-assign unique", you may want to seed your random number + generator such that each regression run gets a different randomization + sequence. The simplest is to use the :vlopt:`+verilator+seed+\` + runtime option. Alternatively use the system's :code:`srand48()` or for + Windows :code:`srand()` function to do this. You'll probably also want + to print any seeds selected, and code to enable rerunning with that same + seed so you can reproduce bugs. + + .. note:: + + This option applies only to values which are explicitly written as X + in the Verilog source code. Initial values of clocks are set to 0 + unless `--x-initial-edge` is specified. Initial values of all other + state holding variables are controlled with `--x-initial`. + +.. option:: --x-initial 0 + +.. option:: --x-initial fast + +.. option:: --x-initial unique (default) + + Controls the two-state value that is used to initialize variables that + are not otherwise initialized. + + "--x-initial 0", + initializes all otherwise uninitialized variables to zero. + + "--x-initial unique", the default, + initializes variables using a function, which determines the value to + use each initialization. This gives greatest flexibility and allows + finding reset bugs. See :ref:`Unknown states`. + + "--x-initial fast", + is best for performance, and initializes all variables to a state + Verilator determines is optimal. This may allow further code + optimizations, but will likely hide any code bugs relating to missing + resets. + + .. note:: + + This option applies only to initial values of variables. Initial + values of clocks are set to 0 unless :vlopt:`--x-initial-edge` is + specified. + +.. option:: --x-initial-edge + + Enables emulation of event driven simulators which generally trigger an + edge on a transition from X to 1 (posedge) or X to 0 (negedge). Thus the + following code, where :code:`rst_n` is uninitialized would set + :code:`res_n` to :code:`1'b1` when :code:`rst_n` is first set to zero: + + .. code-block:: sv + + reg res_n = 1'b0; + + always @(negedge rst_n) begin + if (rst_n == 1'b0) begin + res_n <= 1'b1; + end + end + + In Verilator, by default, uninitialized clocks are given a value of + zero, so the above :code:`always` block would not trigger. + + While it is not good practice, there are some designs that rely on X + rarr 0 triggering a negedge, particularly in reset sequences. Using + :vlopt:`--x-initial-edge` with Verilator will replicate this + behavior. It will also ensure that X rarr 1 triggers a posedge. + + .. note:: + + Using this option can affect convergence, andit may be necessary to + use :vlopt:`--converge-limit` to increase the number of convergence + iterations. This may be another indication of problems with the + modeled design that should be addressed. + +.. option:: --xml-only + + Create XML output only, do not create any other output. + + The XML format is intended to be used to leverage Verilator's parser and + elaboration to feed to other downstream tools. Be aware that the XML + format is still evolving; there will be some changes in future versions. + +.. option:: --xml-output + + Filename for XML output file. Using this option automatically sets + :vlopt:`--xml-only`. + +.. option:: -y + + Add the directory to the list of directories that should be searched for + include files or libraries. The three flags :vlopt:`-y`, + :vlopt:`+incdir+\` and :vlopt:`-I\` have similar effect; + :vlopt:`+incdir+\` and :vlopt:`-y` are fairly standard across + Verilog tools while :vlopt:`-I\` is used by many C++ compilers. + + Verilator defaults to the current directory "-y ." and any specified + :vlopt:`--Mdir`, though these default paths are used after any user + specified directories. This allows '-y "$(pwd)"' to be used if absolute + filenames are desired for error messages instead of relative filenames. + + +.. _Configuration Files: + +Configuration Files +=================== + +In addition to the command line, warnings and other features for the +:command:`verilator` command may be controlled with configuration files, +typically named with the .vlt extension (what makes it a configuration file +is the :option:`\`verilator_config` directive). An example: + +.. code-block:: sv + + `verilator_config + lint_off -rule WIDTH + lint_off -rule CASEX -file "silly_vendor_code.v" + +This disables WIDTH warnings globally, and CASEX for a specific file. + +Configuration files are fed through the normal Verilog preprocessor prior +to parsing, so "\`ifdef", "\`define", and comments may be used as if the +configuration file was normal Verilog code. + +Note that file or line-specific configuration only applies to files read +after the configuration file. It is therefore recommended to pass the +configuration file to Verilator as the first file. + +The grammar of configuration commands is as follows: + +.. option:: `verilator_config + + Take remaining text and treat it as Verilator configuration commands. + +.. option:: coverage_on [-file "" [-lines [ - ]]] + +.. option:: coverage_off [-file "" [-lines [ - ]]] + + Enable/disable coverage for the specified filename (or wildcard with + '\*' or '?', or all files if omitted) and range of line numbers (or all + lines if omitted). Often used to ignore an entire module for coverage + analysis purposes. + +.. option:: clock_enable -module "" -var "" + + Indicate the signal is used to gate a clock, and the user takes + responsibility for insuring there are no races related to it. + + Same as :option:`/*verilator&32;clock_enable*/` metacomment. + +.. option:: clocker -module "" [-task ""] -var "" + +.. option:: clocker -module "" [-function ""] -var "" + +.. option:: no_clocker -module "" [-task ""] -var "" + +.. option:: no_clocker -module "" [-function ""] -var "" + + Indicate the signal is used as clock or not. This information is used by + Verilator to mark the signal as clocker and propagate the clocker + attribute automatically to derived signals. See :vlopt:`--clk`. + + Same as :option:`/*verilator&32;clocker*/` metacomment. + +.. option:: coverage_block_off -module "" -block "" + +.. option:: coverage_block_off -file "" -line + + Specifies the entire begin/end block should be ignored for coverage + analysis purposes. Can either be specified as a named block or as a + filename and line number. + + Same as :option:`/*verilator&32;coverage_block_off*/` metacomment. + +.. option:: full_case -file "" -lines + +.. option:: parallel_case -file "" -lines + + Same as :code:`//synopsys full_case` and :code:`//synopsys + parallel_case`. When these synthesis directives are discovered, + Verilator will either formally prove the directive to be true, or + failing that, will insert the appropriate code to detect failing cases + at simulation runtime and print an "Assertion failed" error message. + +.. option:: hier_block -module "" + + Specifies that the module is a unit of hierarchical Verilation. Note + that the setting is ignored unless the :vlopt:`--hierarchical` option is + specified. See :ref:`Hierarchical Verilation`. + +.. option:: inline -module "" + + Specifies the module may be inlined into any modules that use this + module. Same as :option:`/*verilator&32;inline_module*/` metacomment. + +.. option:: isolate_assignments -module "" [-task ""] -var "" + +.. option:: isolate_assignments -module "" [-function ""] -var "" + +.. option:: isolate_assignments -module "" -function "" + + Used to indicate the assignments to this signal in any blocks should be + isolated into new blocks. When there is a large combinatorial block + that is resulting in an UNOPTFLAT warning, attaching this to the signal + causing a false loop may clear up the problem. + + Same as :option:`/*verilator&32;isolate_assignments*/` metacomment. + +.. option:: no_inline -module "" + + Specifies the module should not be inlined into any modules that use + this module. Same as :option:`/*verilator&32;no_inline_module*/` + metacomment. + +.. option:: no_inline [-module ""] -task "" + +.. option:: no_inline [-module ""] -function "" + + Specify the function or task should not be inlined into where it is + used. This may reduce the size of the final executable when a task is + used a very large number of times. For this flag to work, the task and + tasks below it must be pure; they cannot reference any variables outside + the task itself. + + Same as :option:`/*verilator&32;no_inline_task*/` metacomment. + +.. option:: lint_on [-rule ] [-file "" [-lines [ - ]]] + +.. option:: lint_off [-rule ] [-file "" [-lines [ - ]]] + +.. option:: lint_off [-rule ] [-file ""] [-match ""] + + Enable/disables the specified lint warning, in the specified filename + (or wildcard with '\*' or '?', or all files if omitted) and range of + line numbers (or all lines if omitted). + + With lint_off using "\*" will override any lint_on directives in the + source, i.e. the warning will still not be printed. + + If the -rule is omitted, all lint warnings (see list in + :vlopt:`-Wno-lint`) are enabled/disabled. This will override all later + lint warning enables for the specified region. + + If -match is set the linter warnings are matched against this (wildcard) + string and are waived in case they match and iff rule and file (with + wildcard) also match. + + In previous versions -rule was named -msg. The latter is deprecated, but + still works with a deprecation info, it may be removed in future + versions. + +.. option:: public [-module ""] [-task/-function ""] -var "" + +.. option:: public_flat [-module ""] [-task/-function ""] -var "" + +.. option:: public_flat_rd [-module ""] [-task/-function ""] -var "" + +.. option:: public_flat_rw [-module ""] [-task/-function ""] -var "" "@(edge)" + + Sets the variable to be public. Same as + :option:`/*verilator&32;public*/` or + :option:`/*verilator&32;public_flat*/`, etc, metacomments. See + e.g. :ref:`VPI Example`. + +.. option:: sc_bv -module "" [-task ""] -var "" + +.. option:: sc_bv -module "" [-function ""] -var "" + + Sets the port to be of :code:`sc_bv<{width}>` type, instead of bool, + vluint32_t or vluint64_t. Same as :option:`/*verilator&32;sc_bv*/` + metacomment. + +.. option:: sformat [-module ""] [-task ""] -var "" + +.. option:: sformat [-module ""] [-function ""] -var "" + + Must be applied to the final argument of type :code:`input string` of a + function or task to indicate the function or task should pass all + remaining arguments through $sformatf. This allows creation of DPI + functions with $display like behavior. See the + :file:`test_regress/t/t_dpi_display.v` file for an example. + + Same as :option:`/*verilator&32;sformat*/` metacomment. + +.. option:: split_var [-module ""] [-task ""] -var "" + +.. option:: split_var [-module ""] [-function ""] -var "" + + Break the variable into multiple pieces typically to resolve UNOPTFLAT + performance issues. Typically the variables to attach this to are + recommended by Verilator itself, see :option:`UNOPTFLAT`. + + Same as :option:`/*verilator&32;split_var*/` metacomment. + +.. option:: tracing_on [-file "" [-lines [ - ]]] + +.. option:: tracing_off [-file "" [-lines [ - ]]] + + Enable/disable waveform tracing for all future signals declared in the + specified filename (or wildcard with '\*' or '?', or all files if + omitted) and range of line numbers (or all lines if omitted). + + For tracing_off, instances below any module in the files/ranges + specified will also not be traced. + diff --git a/docs/guide/exe_verilator_coverage.rst b/docs/guide/exe_verilator_coverage.rst new file mode 100644 index 000000000..41eba66cf --- /dev/null +++ b/docs/guide/exe_verilator_coverage.rst @@ -0,0 +1,114 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +verilator_coverage +================== + +Verilator_coverage processes Verilated model-generated coverage reports. + +With --annotate, it reads the specified coverage data file and generates +annotated source code with coverage metrics annotated. If multiple +coverage points exist on the same source code line, additional lines will +be inserted to report the additional points. + +Additional Verilog-XL-style standard arguments specify the search paths +necessary to find the source code that the coverage analysis was performed +on. + +To filter those items to be included in coverage, you may read +logs/coverage.dat into an editor and do a M-x keep-lines to include only +those statistics of interest and save to a new .dat file. + +For Verilog conditions that should never occur, either add a $stop +statement to the appropriate statement block, or see +:option:`/*verilator&32;coverage_off*/`. This will remove the coverage +points after the model is re-Verilated. + +For an overview of use of verilator_coverage, see :ref:`Coverage Analysis`. + + +verilator_coverage Example Usage +-------------------------------- + +.. + + verilator_coverage --help + verilator_coverage --version + + verilator_coverage --annotate + + verilator_coverage -write merged.dat -read ... + + verilator_coverage -write-info merged.info -read ... + + +verilator_coverage Arguments +---------------------------- + +.. program:: verilator_coverage + +.. option:: + +Specifies the input coverage data file. Multiple filenames may be provided +to read multiple inputs. If no data file is specified, by default +"coverage.dat" will be read. + +.. option:: --annotate + +Specifies the directory name that source files with annotated coverage data +should be written to. + +.. option:: --annotate-all + +Specifies all files should be shown. By default, only those source files +which have low coverage are written to the output directory. + +.. option:: --annotate-min + +Specifies if the coverage point does not include the count number of +coverage hits, then the coverage point will be considered above the +threashold, and the coverage report will put a "%" to indicate the coverage +is not sufficient. Defaults to 10. + +.. option:: --help + +Displays a help summary, the program version, and exits. + +.. option:: --rank + +Prints an experimental report listing the relative importance of each test +in covering all of the coverage points. The report shows "Covered" which +indicates the number of points that test covers; a test is considered to +cover a point if it has a bucket count of at least 1. The "rank" column has +a higher number t indicate the test is more important, and rank 0 means the +test does not need to be run to cover the points. "RankPts" indicates the +number of coverage points this test will contribute to overall coverage if +all tests are run in the order of highest to lowest rank. + +.. option:: --unlink + +With :option:`--write`, unlink all input files after the output +has been successfully created. + +.. option:: --version + +Displays program version and exits. + +.. option:: --write + +Specifies the aggregate coverage results, summed across all the files, +should be written to the given filename in verilator_coverage data format. +This is useful for use in scripts to combine many coverage data files +(likely generated from random test runs) into one master coverage file. + +.. option:: --write-info + +Specifies the aggregate coverage results, summed across all the files, +should be written to the given filename in :command:`lcov` .info format. +This may be used to feed into :command:`lcov` to aggregate or generate +reports. + +The info format loses data compared to the Verilator coverage data format; +the info will all forms of coverage converted to line style coverage, and +if there are multiple coverage points on a single line, the minimum +coverage across those points will be used to report coverage of the line. diff --git a/docs/guide/exe_verilator_gantt.rst b/docs/guide/exe_verilator_gantt.rst new file mode 100644 index 000000000..ea660c09a --- /dev/null +++ b/docs/guide/exe_verilator_gantt.rst @@ -0,0 +1,76 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +verilator_gantt +=============== + +Verilator_gantt creates a visual representation to help analyze Verilator +multithreaded simulation performance, by showing when each macro-task +starts and ends, and showing when each thread is busy or idle. + +For an overview of use of verilator_gantt, see :ref:`Profiling`. + +Gantt Chart Contents +-------------------- + +The generated Gantt chart has time on the X-axis. Times shown are to the +scale printed, i.e. a certain about of time for each character width. The +Y-axis shows threads, each thread's execution is shown on one line. That +line shows "[" at the position in time when it executes. + +Following the "[" is the CPU number the task executed on, followed by zero +or more "-" to make the width of the characters match the scaled execution +time, followed by a "]". If the scale is too small, the CPU number and +mtask number will not be printed. If the scale is very small, a "&" +indicates multiple mtasks started at that time position. + +Also creates a value change dump (VCD) format dump file which may be viewed +in a waveform viewer (e.g. C). See below. + +Gantt Chart VCD Signals +----------------------- + +In waveforms there are the following signals. Most signals the "decimal" +format will remove the leading zeros and make the traces easier to read. + +parallelism + The number of mtasks active at this time, for best performance this will + match the thread count. You may want to use an "analog step" format to + view this signal. + +cpu#_thread + For the given CPU number, the thread number executing. + +mtask#_cpu + For the given mtask id, the CPU it is executing on. + +thread#_mtask + For the given thread number, the mtask id executing. + +verilator_gantt Arguments +------------------------- + +.. program:: verilator_gantt + +.. option:: + +The filename to read data from, defaults to "profile_threads.dat". + +.. option:: --help + +Displays a help summary, the program version, and exits. + +.. option:: --scale + +Sets the number of time units per character on the X-axis of the generated +Gantt chart. (On x86, time units are rdtsc ticks.) Defaults to 0, which +will automatically compute a reasonable scale where no two mtasks need to +fit into same character width's worth of scaled time. + +.. option:: --no-vcd + +Disables creating a .vcd file. + +.. option:: --vcd + +Sets the output filename for vcd dump. Default is "verilator_gantt.vcd". diff --git a/docs/guide/exe_verilator_profcfuncs.rst b/docs/guide/exe_verilator_profcfuncs.rst new file mode 100644 index 000000000..f3ac26b81 --- /dev/null +++ b/docs/guide/exe_verilator_profcfuncs.rst @@ -0,0 +1,25 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +verilator_profcfuncs +==================== + +Verilator_profcfunc reads a profile report created by gprof. The names of +the functions are then transformed, assuming the user used Verilator's +--prof-cfuncs, and a report printed showing the percentage of time, etc, in +each Verilog block. + +For an overview of use of verilator_profcfuncs, see :ref:`Profiling`. + +verilator_profcfuncs Arguments +------------------------------ + +.. program:: verilator_profcfuncs + +.. option:: + +The :command:`gprof`-generated filename to read data from. Typically "gprof.out". + +.. option:: --help + +Displays a help summary, the program version, and exits. diff --git a/docs/guide/executables.rst b/docs/guide/executables.rst new file mode 100644 index 000000000..e9c3fc700 --- /dev/null +++ b/docs/guide/executables.rst @@ -0,0 +1,19 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +********************************* +Executable and Argument Reference +********************************* + +This section describes the executables that are part of Verilator, and the +options to each executable. + +.. toctree:: + :maxdepth: 1 + :hidden: + + exe_verilator.rst + exe_verilator_coverage.rst + exe_verilator_gantt.rst + exe_verilator_profcfuncs.rst + exe_sim.rst diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst new file mode 100644 index 000000000..d88490afe --- /dev/null +++ b/docs/guide/extensions.rst @@ -0,0 +1,492 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +******************* +Language Extensions +******************* + +The following additional constructs are the extensions Verilator supports +on top of standard Verilog code. Using these features outside of comments +or "`ifdef`"'s may break other tools. + +.. option:: `__FILE__ + + The :option:`\`__FILE__` define expands to the current filename as a + string, like C++'s __FILE__. This Verilator feature added in 2006 was + incorporated into the IEEE 1800-2009 standard. + +.. option:: `__LINE__ + + The :option:`\`__LINE__` define expands to the current filename as a + string, like C++'s __LINE__. This Verilator feature added in 2006 was + incorporated into the IEEE 1800-2009 standard. + +.. option:: `error [string] + + This will report an error when encountered, like C++'s #error. + +.. option:: $c([string], ...); + + The string will be embedded directly in the output C++ code at the point + where the surrounding Verilog code is compiled. It may either be a + standalone statement (with a trailing ; in the string), or a function + that returns up to a 32-bit number (without a trailing ;). This can be + used to call C++ functions from your Verilog code. + + String arguments will be put directly into the output C++ code. + Expression arguments will have the code to evaluate the expression + inserted. Thus to call a C++ function, :code:`$c("func(",a,")")` will + result in :code:`func(a)` in the output C++ code. For input arguments, + rather than hard-coding variable names in the string + :code:`$c("func(a)")`, instead pass the variable as an expression + ::code:`$c("func(",a,")")`. This will allow the call to work inside + Verilog functions where the variable is flattened out, and also enable + other optimizations. + + If you will be reading or writing any Verilog variables inside the C++ + functions, the Verilog signals must be declared with + :option:`/*verilator&32;public*/` metacomments. + + You may also append an arbitrary number to $c, generally the width of + the output; :code:`signal_32_bits = $c32("...");`. This allows for + compatibility with other simulators which require a differently named + PLI function name for each different output width. + +.. option:: $display, $write, $fdisplay, $fwrite, $sformat, $swrite + + Format arguments may use C fprintf sizes after the % escape. Per the + Verilog standard, %x prints a number with the natural width, and %0x + prints a number with minimum width. Verilator extends this so %5x + prints 5 digits per the C standard (this is unspecified in Verilog, but + was incorporated into the 1800-2009). + +.. option:: `coverage_block_off + + Specifies the entire begin/end block should be ignored for coverage + analysis. Must be inside a code block, e.g. within a begin/end pair. + Same as :option:`coverage_block_off` in :ref:`Configuration Files`. + +.. option:: `systemc_header + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the output .h file's header. Must be placed as a module + item, e.g. directly inside a module/endmodule pair. Despite the name of + this macro, this also works in pure C++ code. + +.. option:: `systemc_ctor + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the C++ class constructor. Must be placed as a module + item, e.g. directly inside a module/endmodule pair. Despite the name of + this macro, this also works in pure C++ code. + +.. option:: `systemc_dtor + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the C++ class destructor. Must be placed as a module + item, e.g. directly inside a module/endmodule pair. Despite the name of + this macro, this also works in pure C++ code. + +.. option:: `systemc_interface + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the C++ class interface. Must be placed as a module item, + e.g. directly inside a module/endmodule pair. Despite the name of this + macro, this also works in pure C++ code. + +.. option:: `systemc_imp_header + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into the header of all files for this C++ class implementation. + Must be placed as a module item, e.g. directly inside a module/endmodule + pair. Despite the name of this macro, this also works in pure C++ code. + +.. option:: `systemc_implementation + + Take remaining text up to the next :option:`\`verilog` or + :option:`\`systemc_... <\`systemc_header>` mode switch and place it + verbatim into a single file of the C++ class implementation. Must be + placed as a module item, e.g. directly inside a module/endmodule + pair. Despite the name of this macro, this also works in pure C++ code. + + If you will be reading or writing any Verilog variables in the C++ + functions, the Verilog signals must be declared with a + :option:`/*verilator&32;public*/` metacomment. See also the public task + feature; writing an accessor may result in cleaner code. + +.. option:: `SYSTEMVERILOG + + The SYSTEMVERILOG, SV_COV_START and related standard defines are set by + default when :vlopt:`--language <--language>` is "1800-\*". + +.. option:: `VERILATOR + +.. option:: `verilator + +.. option:: `verilator3 + + The VERILATOR, verilator and verilator3 defines are set by default so + you may "\`ifdef" around tool specific constructs. + +.. option:: `verilator_config + + Take remaining text up to the next :option:`\`verilog` mode switch and + treat it as Verilator configuration commands. See :ref:`Configuration Files`. + +.. option:: `verilog + + Switch back to processing Verilog code after a + :option:`\`systemc_... <\`systemc_header>` mode switch. The Verilog + code returns to the last language mode specified with + "\`begin_keywords", or SystemVerilog if none was specified. + +.. option:: /*verilator&32;clock_enable*/ + + Used after a signal declaration to indicate the signal is used to gate a + clock, and the user takes responsibility for insuring there are no races + related to it. (Typically by adding a latch, and running static timing + analysis.) For example: + + .. code-block:: sv + + reg enable_r /*verilator clock_enable*/; + wire gated_clk = clk & enable_r; + always_ff @(posedge clk) + enable_r <= enable_early; + + The clock_enable attribute will cause the clock gate to be ignored in + the scheduling algorithm, sometimes required for correct clock behavior, + and always improving performance. It's also a good idea to enable the + :option:`IMPERFECTSCH` warning, to ensure all clock enables are properly + recognized. + + Same as :option:`clock_enable` configuration file option. + +.. option:: /*verilator&32;clocker*/ + +.. option:: /*verilator&32;no_clocker*/ + + Used after a signal declaration to indicate the signal is used as clock + or not. This information is used by Verilator to mark the signal as + clocker and propagate the clocker attribute automatically to derived + signals. See :vlopt:`--clk`. + + Same as :option:`clocker` and :option:`no_clocker` in configuration + files. + +.. option:: /*verilator&32;coverage_block_off*/ + + Specifies the entire begin/end block should be ignored for coverage + analysis purposes. + + Same as :option:`coverage_block_off` configuration file option. + +.. option:: /*verilator&32;coverage_off*/ + + Specifies that following lines of code should have coverage disabled. + Often used to ignore an entire module for coverage analysis purposes. + +.. option:: /*verilator&32;coverage_on*/ + + Specifies that following lines of code should have coverage re-enabled + (if appropriate :vlopt:`--coverage` flags are passed) after being + disabled earlier with :option:`/*verilator&32;coverage_off*/`. + + +.. _verilator_hier_block: + +.. option:: /*verilator&32;hier_block*/ + + Specifies that the module is a unit of hierarchical Verilation. This + metacomment must be between :code:`module module_name(...);` and + :code:`endmodule`. The module will not be inlined nor uniquified for + each instance in hierarchical Verilation. Note that the metacomment is + ignored unless the :vlopt:`--hierarchical` option is specified. + + See :ref:`Hierarchical Verilation`. + +.. option:: /*verilator&32;inline_module*/ + + Specifies the module the comment appears in may be inlined into any + modules that use this module. This is useful to speed up simulation + runtime. Note if using :vlopt:`--public` that signals under inlined + submodules will be named :code:`{submodule}__DOT__{subsignal}` as C++ + does not allow "." in signal names. + + Same as :option:`inline` configuration file option. + +.. option:: /*verilator&32;isolate_assignments*/ + + Used after a signal declaration to indicate the assignments to this + signal in any blocks should be isolated into new blocks. When there is + a large combinatorial block that is resulting in an ``UNOPTFLAT`` + warning, attaching this to the signal causing a false loop may clear up + the problem. + + IE, with the following: + + .. code-block:: sv + + reg splitme /* verilator isolate_assignments*/; + // Note the placement of the semicolon above + always_comb begin + if (....) begin + splitme = ....; + other assignments + end + end + + Verilator will internally split the block that assigns to "splitme" into + two blocks: + + It would then internally break it into (sort of): + + .. code-block:: sv + + // All assignments excluding those to splitme + always_comb begin + if (....) begin + other assignments + end + end + // All assignments to splitme + always_comb begin + if (....) begin + splitme = ....; + end + end + + Same as :option:`isolate_assignments` configuration file option. + +.. option:: /*verilator&32;lint_off */ + + Disable the specified warning message for any warnings following the + comment. + +.. option:: /*verilator&32;lint_on */ + + Re-enable the specified warning message for any warnings following the + comment. + +.. option:: /*verilator&32;lint_restore*/ + + After a :code:`/*verilator&32;lint_save*/`, pop the stack containing lint + message state. Often this is useful at the bottom of include files. + +.. option:: /*verilator&32;lint_save*/ + + Push the current state of what lint messages are turned on or turned off + to a stack. Later meta-comments may then lint_on or lint_off specific + messages, then return to the earlier message state by using + :code:`/*verilator&32;lint_restore*/`. For example: + + .. code-block:: sv + + // verilator lint_save + // verilator lint_off WIDTH + ... // code needing WIDTH turned off + // verilator lint_restore + + If WIDTH was on before the lint_off, it will now be restored to on, and + if it was off before the lint_off it will remain off. + +.. option:: /*verilator&32;no_inline_module*/ + + Specifies the module the comment appears in should not be inlined into + any modules that use this module. + + Same as :option:`no_inline` configuration file option. + +.. option:: /*verilator&32;no_inline_task*/ + + Used in a function or task variable definition section to specify the + function or task should not be inlined into where it is used. This may + reduce the size of the final executable when a task is used a very large + number of times. For this flag to work, the task and tasks below it + must be pure; they cannot reference any variables outside the task + itself. + + Same as :option:`no_inline` configuration file option. + +.. option:: /*verilator&32;public*/ (on parameter) + + Used after a parameter declaration to indicate the emitted C code should + have the parameter values visible. Due to C++ language restrictions, + this may only be used on 64-bit or narrower integral enumerations. + + .. code-block:: sv + + parameter [2:0] PARAM /*verilator public*/ = 2'b0; + +.. option:: /*verilator&32;public*/ (on typedef enum) + + Used after an enum typedef declaration to indicate the emitted C code + should have the enum values visible. Due to C++ language restrictions, + this may only be used on 64-bit or narrower integral enumerations. + + .. code-block:: sv + + typedef enum logic [2:0] { ZERO = 3'b0 } pub_t /*verilator public*/; + +.. option:: /*verilator&32;public*/ (on variable) + + Used after an input, output, register, or wire declaration to indicate + the signal should be declared so that C code may read or write the value + of the signal. This will also declare this module public, otherwise use + :code:`/*verilator&32;public_flat*/`. + + Instead of using public variables, consider instead making a DPI or + public function that accesses the variable. This is nicer as it + provides an obvious entry point that is also compatible across + simulators. + + Same as :option:`public` configuration file option. + +.. option:: /*verilator&32;public*/ (on task/function) + + Used inside the declaration section of a function or task declaration to + indicate the function or task should be made into a C++ function, public + to outside callers. Public tasks will be declared as a void C++ + function, public functions will get the appropriate non-void (bool, + uint32_t, etc) return type. Any input arguments will become C++ + arguments to the function. Any output arguments will become C++ + reference arguments. Any local registers/integers will become function + automatic variables on the stack. + + Wide variables over 64 bits cannot be function returns, to avoid + exposing complexities. However, wide variables can be input/outputs; + they will be passed as references to an array of 32-bit numbers. + + Generally, only the values of stored state (flops) should be written, as + the model will NOT notice changes made to variables in these functions. + (Same as when a signal is declared public.) + + You may want to use DPI exports instead, as it's compatible with other + simulators. + + Same as :option:`public` configuration file option. + +.. option:: /*verilator&32;public_flat*/ (on variable) + + Used after an input, output, register, or wire declaration to indicate + the signal should be declared so that C code may read or write the value + of the signal. This will not declare this module public, which means + the name of the signal or path to it may change based upon the module + inlining which takes place. + + Same as :option:`public_flat` configuration file option. + +.. option:: /*verilator&32;public_flat_rd*/ (on variable) + + Used after an input, output, register, or wire declaration to indicate + the signal should be declared public_flat (see above), but read-only. + + Same as :option:`public_flat_rd` configuration file option. + +.. option:: /*verilator&32;public_flat_rw @()*/ (on variable) + + Used after an input, output, register, or wire declaration to indicate + the signal should be declared public_flat_rd (see above), and also + writable, where writes should be considered to have the timing specified + by the given sensitivity edge list. Set for all variables, ports and + wires using the :vlopt:`--public-flat-rw` option. + + Same as :option:`public_flat_rw` configuration file option. + +.. option:: /*verilator&32;public_module*/ + + Used after a module statement to indicate the module should not be + inlined (unless specifically requested) so that C code may access the + module. Verilator automatically sets this attribute when the module + contains any public signals or \`systemc_ directives. Also set for all + modules when using the :vlopt:`--public` option. + + Same as :option:`public` configuration file option. + +.. option:: /*verilator&32;sc_clock*/ + + Deprecated and ignored. Previously used after an input declaration to + indicate the signal should be declared in SystemC as a sc_clock instead + of a bool. This was needed in SystemC 1.1 and 1.2 only; versions 2.0 + and later do not require clock pins to be sc_clocks and this is no + longer needed and is ignored. + +.. option:: /*verilator&32;sc_bv*/ + + Used after a port declaration. It sets the port to be of + :code:`sc_bv<{width}>` type, instead of bool, vluint32_t or vluint64_t. + This may be useful if the port width is parameterized and the + instantiating C++ code wants to always have a sc_bv so it can accept any + width. In general you should avoid using this attribute when not + necessary as with increasing usage of sc_bv the performance decreases + significantly. + + Same as :option:`sc_bv` configuration file option. + +.. option:: /*verilator&32;sformat*/ + + Attached to the final argument of type "input string" of a function or + task to indicate the function or task should pass all remaining + arguments through $sformatf. This allows creation of DPI functions with + $display like behavior. See the :file:`test_regress/t/t_dpi_display.v` + file for an example. + + Same as :option:`sformat` configuration file option. + +.. option:: /*verilator&32;split_var*/ + + Attached to a variable or a net declaration to break the variable into + multiple pieces typically to resolve ``UNOPTFLAT`` performance issues. + Typically the variables to attach this to are recommended by Verilator + itself, see :option:`UNOPTFLAT`. + + For example, Verilator will internally convert a variable with the + metacomment such as: + + .. code-block:: sv + + logic [7:0] x [0:1] /*verilator split_var*/; + + To: + + .. code-block:: sv + + logic [7:0] x__BRA__0__KET__ /*verilator split_var*/; + logic [7:0] x__BRA__1__KET__ /*verilator split_var*/; + + Note that the generated packed variables retain the split_var + metacomment because they may be split into further smaller pieces + according to the access patterns. + + This only supports unpacked arrays, packed arrays, and packed structs of + integer types (reg, logic, bit, byte, int...); otherwise if a split was + requested but cannot occur a SPLITVAR warning is issued. Splitting + large arrays may slow down the Verilation speed, so use this only on + variables that require it. + + Same as :option:`split_var` configuration file option. + +.. option:: /*verilator&32;tag */ + + Attached after a variable or structure member to indicate opaque (to + Verilator) text that should be passed through to the XML output as a tag, + for use by downstream applications. + +.. option:: /*verilator&32;tracing_off*/ + + Disable waveform tracing for all future signals that are declared in + this module, or instances below this module. Often this is placed just + after a primitive's module statement, so that the entire module and + instances below it are not traced. + +.. option:: /*verilator&32;tracing_on*/ + + Re-enable waveform tracing for all future signals or instances that are + declared. + + diff --git a/docs/guide/faq.rst b/docs/guide/faq.rst new file mode 100644 index 000000000..ca99d5e7e --- /dev/null +++ b/docs/guide/faq.rst @@ -0,0 +1,495 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +****************************** +FAQ/Frequently Asked Questions +****************************** + +.. Extra heading level here so sidebar index looks nice + +Questions +========= + +Can I contribute? +""""""""""""""""" + +Please contribute! Just submit a pull request, or raise an issue to +discuss if looking for something to help on. For more information see our +contributor agreement. + + +How widely is Verilator used? +""""""""""""""""""""""""""""" + +Verilator is used by many of the largest silicon design companies, large +organizations such as CERN, and even by college student projects. + +Verilator is one of the "big 4" simulators, meaning one of the 4 main +SystemVerilog simulators available, namely the closed-source products Synopsys +VCS (tm), Mentor Questa/ModelSim (tm), Cadence +Xcelium/Incisive/NC-Verilog/NC-Sim (tm), and the open-source Verilator. +The three closed-source offerings are often collectively called the "big 3" +simulators. + + +Does Verilator run under Windows? +""""""""""""""""""""""""""""""""" + +Yes, using Cygwin. Verilated output also compiles under Microsoft Visual +C++, but this is not tested every release. + + +Can you provide binaries? +""""""""""""""""""""""""" + +You can install Verilator via the system package manager (apt, yum, etc.) +on many Linux distributions, including Debian, Ubuntu, SuSE, RedHat, and +others. These packages are provided by the Linux distributions and +generally will lag the version of the mainline Verilator repository. If no +binary package is available for your distribution, how about you set one +up? + + +How can it be faster than (name-a-big-3-closed-source-simulator)? +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Generally, the implied part of the question is "... with all of the +manpower they can put into developing it." + +Most simulators have to be compliant with the complete IEEE 1364 (Verilog) +and IEEE 1800 (SystemVerilog) standards, meaning they have to be event +driven. This prevents them from being able to reorder blocks and make +netlist-style optimizations, which are where most of the gains come from. + +You should not be scared by non-compliance. Your synthesis tool isn't +compliant with the whole standard to start with, so your simulator need not +be either. Verilator is closer to the synthesis interpretation, so this is +a good thing for getting working silicon. + + +Will Verilator output remain under my own license/copyright? +"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Yes, it's just like using GCC on your programs; this is why Verilator uses +the "GNU **Lesser** Public License Version 3" instead of the more typical +"GNU Public License". See the licenses for details, but in brief, if you +change Verilator itself or the header files Verilator includes, you must +make the source code available under the GNU Lesser Public License. +However, Verilator output (the Verilated code) only "include"s the licensed +files, and so you are **not** required to open-source release any output +from Verilator. + +You also have the option of using the Perl Artistic License, which again +does not require you to release your Verilog or generated code, and also +allows you to modify Verilator for internal use without distributing the +modified version. But please contribute back to the community! + +One limit is that you cannot under either license release a closed-source +Verilog simulation product incorporating Verilator. That is you can have a +commercial product, but must make the source code available. + +As is standard with Open Source, contributions back to Verilator will be +placed under the Verilator copyright and LGPL/Artistic license. Small test +cases will be released into the public domain so they can be used anywhere, +and large tests under the LGPL/Artistic, unless requested otherwise. + + +Why is running Verilator (to create a model) so slow? +""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Verilator may require more memory than the resulting simulator will +require, as Verilator internally creates all of the state of the resulting +generated simulator in order to optimize it. If it takes more than a few +minutes or so (and you're not using :vlopt:`--debug` since debug mode is +disk bound), see if your machine is paging; most likely you need to run it +on a machine with more memory. Very large designs are known to have topped +64 GB resident set size. Alternatively, see :ref:`Hierarchical Verilation`. + + +How do I generate waveforms (traces) in C++? +"""""""""""""""""""""""""""""""""""""""""""" + +See also the next question for tracing in SystemC mode. + +A. Pass the :vlopt:`--trace` option to Verilator, and in your top level C + code, call ``Verilated::traceEverOn(true)``. Then you may use + ``$dumpfile`` and ``$dumpvars`` to enable traces, same as with any + Verilog simulator. See ``examples/make_tracing_c`` in the distribution. + +B. Or, for finer-grained control, or C++ files with multiple Verilated + modules you may also create the trace purely from C++. Create a + VerilatedVcdC object, and in your main loop call + ``trace_object->dump(time)`` every time step, and finally call + ``trace_object->close()``. + + .. code-block:: C++ + :emphasize-lines: 1,5-8,12 + + #include "verilated_vcd_c.h" + ... + int main(int argc, char** argv, char** env) { + ... + Verilated::traceEverOn(true); + VerilatedVcdC* tfp = new VerilatedVcdC; + topp->trace(tfp, 99); // Trace 99 levels of hierarchy + tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); + ... + while (Verilated::time() < sim_time && !Verilated::gotFinish()) { + Verilated::timeInc(1); + tfp->dump(main_time); + } + tfp->close(); + } + +You also need to compile :file:`verilated_vcd_c.cpp` and add it to your +link, preferably by adding the dependencies in your Makefile's +:code:`$(VK_GLOBAL_OBJS)` link rule. This is done for you if using the +Verilator :vlopt:`--exe` option. + +you can call :code:`trace_object->trace()` on multiple Verilated objects +with the same trace file if you want all data to land in the same output +file. + + +How do I generate waveforms (traces) in SystemC? +"""""""""""""""""""""""""""""""""""""""""""""""" + +A. Pass the :vlopt:`--trace` option to Verilator, and in your top level + :code:`sc_main()`, call :code:`Verilated::traceEverOn(true)`. Then you + may use :code:`$dumpfile` and code:`$dumpvars` to enable traces, same as + with any Verilog simulator, see the non-SystemC example in + :file:`examples/make_tracing_c`. This will trace only the module + containing the :code:`$dumpvar`. + +B. Or, you may create a trace purely from SystemC, which may trace all + Verilated designs in the SystemC model. Create a VerilatedVcdSc object + as you would create a normal SystemC trace file. For an example, see + the call to ``VerilatedVcdSc`` in the + :file:`examples/make_tracing_sc/sc_main.cpp` file of the distribution, + and below. + +C. Alternatively you may use the C++ trace mechanism described in the + previous question, note the timescale and timeprecision will be + inherited from your SystemC settings. + + .. code-block:: C++ + :emphasize-lines: 1,5-8 + + #include "verilated_vcd_sc.h" + ... + int main(int argc, char** argv, char** env) { + ... + Verilated::traceEverOn(true); + VerilatedVcdSc* tfp = new VerilatedVcdSc; + topp->trace(tfp, 99); // Trace 99 levels of hierarchy + tfp->open("obj_dir/t_trace_ena_cc/simx.vcd"); + ... + sc_start(1); + ... + tfp->close(); + } + + + +You also need to compile :file:`verilated_vcd_sc.cpp` and +:file:`verilated_vcd_c.cpp` and add them to your link, preferably by adding +the dependencies in your Makefile's :code:`$(VK_GLOBAL_OBJS)` link rule. +This is done for you if using the Verilator :vlopt:`--exe` option. + +You can call :code:`->trace()` on multiple Verilated objects with the same +trace file if you want all data to land in the same output file. + +When using SystemC 2.3, the SystemC library must have been built with the +experimental simulation phase callback based tracing disabled. This is +disabled by default when building SystemC with its configure based build +system, but when building SystemC with CMake, you must pass +``-DENABLE_PHASE_CALLBACKS_TRACING=OFF`` to disable this feature. + + +How do I generate FST waveforms (traces) in C++ or SystemC? +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +FST is a trace file format developed by GTKWave. Verilator provides basic +FST support. To dump traces in FST format, add the :vlopt:`--trace-fst` +option to Verilator and either A. use :code:`$dumpfile & $dumpvars` in +Verilog as described in the VCD example above, + +Or, in C++ change the include described in the VCD example above: + +.. code-block:: C++ + + #include "verilated_fst_c.h" + VerilatedFstC* tfp = new VerilatedFstC; + + +Or, in SystemC change the include described in the VCD example above: + +.. code-block:: C++ + + #include "verilated_fst_sc.h" + VerilatedFstC* tfp = new VerilatedFstSc; + + +Note that currently supporting both FST and VCD in a single simulation is +impossible, but such requirement should be rare. You can however ifdef +around the trace format in your C++ main loop, and select VCD or FST at +build time, should you require. + + +How do I view waveforms (aka dumps or traces)? +"""""""""""""""""""""""""""""""""""""""""""""" + +Verilator creates standard VCD (Value Change Dump) and FST files. VCD +files are viewable with the open source GTKWave (recommended) or Dinotrace +(legacy) programs, or any of the many closed-source offerings; FST is +supported only by GTKWave. + + +How do I speed up writing large waveform (trace) files? +""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +A. Instead of calling ``VerilatedVcdC->open`` or ``$dumpvars`` at the + beginning of time, delay calling it until the time stamp where you want + tracing to begin. + +B. Add the :option:`/*verilator&32;tracing_off*/` metacomment to any very + low level modules you never want to trace (such as perhaps library + cells). + +C. Use the :vlopt:`--trace-depth` option to limit the depth of tracing, for + example :vlopt:`--trace-depth 1 <--trace-depth>` to see only the top + level signals. + +D. You can also consider using FST tracing instead of VCD. FST dumps are a + fraction of the size of the equivalent VCD. FST tracing can be slower + than VCD tracing, but it might be the only option if the VCD file size + is prohibitively large. + +E. Be sure you write your trace files to a local solid-state drive, instead + of to a network drive. Network drives are generally far slower. + + +Where is the translate_off command? (How do I ignore a construct?) +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Translate on/off pragmas are generally a bad idea, as it's easy to have +mismatched pairs, and you can't see what another tool sees by just +preprocessing the code. Instead, use the preprocessor; Verilator defines +the ``\`VERILATOR`` define for you, so just wrap the code in an ifndef +region: + + .. code-block:: sv + :emphasize-lines: 1 + + `ifndef VERILATOR + Something_Verilator_Dislikes; + `endif + +Most synthesis tools similarly define SYNTHESIS for you. + + +Why do I get "unexpected 'do'" or "unexpected 'bit'" errors? +"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +The words \ ``do``\ , \ ``bit``\ , \ ``ref``\ , \ ``return``\ , and others +are reserved keywords in SystemVerilog. Older Verilog code might use these +as identifiers. You should change your code to not use them to ensure it +works with newer tools. Alternatively, surround them by the Verilog +2005/SystemVerilog begin_keywords pragma to indicate Verilog 2001 code. + +.. code-block:: sv + :emphasize-lines: 1 + + `begin_keywords "1364-2001" + integer bit; initial bit = 1; + `end_keywords + + +If you want the whole design to be parsed as Verilog 2001, see the +:vlopt:`--default-language` option. + + +How do I prevent my assertions from firing during reset? +"""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Call :code:`Verilated::assertOn(false)` before you first call the model, +then turn it back on after reset. It defaults to true. When false, all +assertions controlled by :vlopt:`--assert` are disabled. + + +Why do I get "undefined reference to sc_time_stamp()? +""""""""""""""""""""""""""""""""""""""""""""""""""""" + +In Verilator 4.200 and later, using the timeInc function is recommended +instead. See the :ref:`Connecting to C++` examples. Some linkers (MSVC++) +still require :code:`sc_time_stamp()` to be defined, either define this +with :code:`double sc_time_stamp() { return 0; }` or compile the Verilated +code with :code:`-CFLAGS -DVL_TIME_CONTEXT`. + +Prior to Verilator 4.200, the :code:`sc_time_stamp()` function needs to be +defined in C++ (non SystemC) to return the current simulation time. + + +Why do I get "undefined reference to \`VL_RAND_RESET_I' or \`Verilated::...'"? +"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +You need to link your compiled Verilated code against the +:code:`verilated.cpp` file found in the include directory of the Verilator +kit. This is one target in the ``$(VK_GLOBAL_OBJS)`` make variable, which +should be part of your Makefile's link rule. If you use :vlopt:`--exe`, +this is done for you. + + +Is the PLI supported? +""""""""""""""""""""" + +Only somewhat. More specifically, the common PLI-ish calls $display, +$finish, $stop, $time, $write are converted to C++ equivalents. You can +also use the "import DPI" SystemVerilog feature to call C code (see the +chapter above). There is also limited VPI access to public signals. + +If you want something more complex, since Verilator emits standard C++ +code, you can simply write your own C++ routines that can access and modify +signal values without needing any PLI interface code, and call it with +$c("{any_c++_statement}"). + +See the :ref:`Connecting` section. + + +How do I make a Verilog module that contain a C++ object? +""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +You need to add the object to the structure that Verilator creates, then +use $c to call a method inside your object. The +:file:`test_regress/t/t_extend_class` files in the distribution show an +example of how to do this. + + +How do I get faster build times? +"""""""""""""""""""""""""""""""" + +* When running make, pass the make variable VM_PARALLEL_BUILDS=1 so that + builds occur in parallel. Note this is now set by default if an output + file was large enough to be split due to the :vlopt:`--output-split` + option. + +* Verilator emits any infrequently executed "cold" routines into separate + __Slow.cpp files. This can accelerate compilation as optimization can be + disabled on these routines. See the OPT_FAST and OPT_SLOW make variables + and :ref:`Benchmarking & Optimization`. + +* Use a recent compiler. Newer compilers tend to be faster. + +* Compile in parallel on many machines and use caching; see the web for the + ccache, distcc and icecream packages. ccache will skip GCC runs between + identical source builds, even across different users. If ccache was + installed when Verilator was built it is used, or see OBJCACHE + environment variable to override this. Also see the + :vlopt:`--output-split` option. + +* To reduce the compile time of classes that use a Verilated module (e.g. a + top CPP file) you may wish to add a + :option:`/*verilator&32;no_inline_module*/` metacomment to your top level + module. This will decrease the amount of code in the model's Verilated + class, improving compile times of any instantiating top level C++ code, + at a relatively small cost of execution performance. + +* Use :ref:`hierarchical verilation`. + + +Why do so many files need to recompile when I add a signal? +""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" + +Adding a new signal requires the symbol table to be recompiled. Verilator +uses one large symbol table, as that results in 2-3 less assembly +instructions for each signal access. This makes the execution time 10-15% +faster, but can result in more compilations when something changes. + + +How do I access Verilog functions/tasks in C? +""""""""""""""""""""""""""""""""""""""""""""" + +Use the SystemVerilog Direct Programming Interface. You write a Verilog +function or task with input/outputs that match what you want to call in +with C. Then mark that function as a DPI export function. See the DPI +chapter in the IEEE Standard. + + +How do I access C++ functions/tasks in Verilog? +""""""""""""""""""""""""""""""""""""""""""""""" + +Use the SystemVerilog Direct Programming Interface. You write a Verilog +function or task with input/outputs that match what you want to call in +with C. Then mark that function as a DPI import function. See the DPI +chapter in the IEEE Standard. + + +How do I access signals in C? +""""""""""""""""""""""""""""" + +The best thing to do is to make a SystemVerilog "export DPI" task or +function that accesses that signal, as described in the DPI chapter in the +manual and DPI tutorials on the web. This will allow Verilator to better +optimize the model and should be portable across simulators. + +If you really want raw access to the signals, declare the signals you will +be accessing with a :option:`/*verilator&32;public*/` metacomment before +the closing semicolon. Then scope into the C++ class to read the value of +the signal, as you would any other member variable. + +Signals are the smallest of 8-bit unsigned chars (equivalent to uint8_t), +16-bit unsigned shorts (uint16_t), 32-bit unsigned longs (uint32_t), or +64-bit unsigned long longs (uint64_t) that fits the width of the signal. +Generally, you can use just uint32_t's for 1 to 32 bits, or vluint64_t for +1 to 64 bits, and the compiler will properly up-convert smaller entities. +Note even signed ports are declared as unsigned; you must sign extend +yourself to the appropriate signal width. + +Signals wider than 64 bits are stored as an array of 32-bit uint32_t's. +Thus to read bits 31:0, access signal[0], and for bits 63:32, access +signal[1]. Unused bits (for example bit numbers 65-96 of a 65-bit vector) +will always be zero. If you change the value you must make sure to pack +zeros in the unused bits or core-dumps may result, because Verilator strips +array bound checks where it believes them to be unnecessary to improve +performance. + +In the SYSTEMC example above, if you had in our.v: + + .. code-block:: sv + + input clk /*verilator public*/; + // Note the placement of the semicolon above + +From the sc_main.cpp file, you'd then: + + .. code-block:: C++ + + #include "Vour.h" + #include "Vour_our.h" + cout << "clock is " << top->our->clk << endl; + + +In this example, clk is a bool you can read or set as any other variable. +The value of normal signals may be set, though clocks shouldn't be changed +by your code or you'll get strange results. + + +Should a module be in Verilog or SystemC? +""""""""""""""""""""""""""""""""""""""""" + +Sometimes there is a block that just interconnects instances, and have a +choice as to if you write it in Verilog or SystemC. Everything else being +equal, best performance is when Verilator sees all of the design. So, look +at the hierarchy of your design, labeling instances as to if they are +SystemC or Verilog. Then: + +* A module with only SystemC instances below must be SystemC. + +* A module with a mix of Verilog and SystemC instances below must be + SystemC. (As Verilator cannot connect to lower-level SystemC instances.) + +* A module with only Verilog instances below can be either, but for best + performance should be Verilog. (The exception is if you have a design + that is instantiated many times; in this case Verilating one of the lower + modules and instantiating that Verilated instances multiple times into a + SystemC module *may* be faster.) diff --git a/docs/guide/files.rst b/docs/guide/files.rst new file mode 100644 index 000000000..cc2dca400 --- /dev/null +++ b/docs/guide/files.rst @@ -0,0 +1,141 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +***** +Files +***** + +.. _Files in the Distribution: + +Files in the Git Tree +===================== + +The following is a summary of the files in the Git Tree (distribution) of +Verilator: + +:: + + Changes => Version history + README.rst => This document + bin/verilator => Compiler wrapper invoked to Verilate code + docs/ => Additional documentation + examples/ => Examples (see manual for descriptions) + include/ => Files that should be in your -I compiler path + include/verilated*.cpp => Global routines to link into your simulator + include/verilated*.h => Global headers + include/verilated.mk => Common Makefile + src/ => Translator source code + test_regress => Internal tests + + +.. _Files Read/Written: + +Files Read/Written +================== + +All output files are placed in the output directory specified with the +:vlopt:`--Mdir` option, or "obj_dir" if not specified. + +Verilator creates the following files in the output directory: + +For --cc/--sc, it creates: + +.. list-table:: + + * - *{prefix}*\ .cmake + - CMake include script for compiling (from --make cmake) + * - *{prefix}*\ .mk + - Make include file for compiling (from --make gmake) + * - *{prefix}*\ _classes.mk + - Make include file with class names (from --make gmake) + * - *{prefix}*\ _hier.mk + - Make file for hierarchy blocks (from --make gmake) + * - *{prefix|*\ _hierMkArgs.f + - Arguments for hierarchical Verilation (from --make gmake) + * - *{prefix}*\ _hierCMakeArgs.f + - Arguments for hierarchical Verilation (from --make cmake) + * - *{prefix}*\ .cpp + - Top level C++ file + * - *{prefix}{__n}*\ .cpp + - Additional top C++ files (from --output-split) + * - *{prefix}*\ .h + - Top level header + * - *{prefix}*\ __Slow\ *{__n}*\ .cpp + - Infrequent cold routines + * - *{prefix}*\ __Dpi.cpp + - DPI import and export wrappers (from --dpi) + * - *{prefix}*\ __Dpi.h + - DPI import and export declarations (from --dpi) + * - *{prefix}*\ __Inlines.h + - Inline support functions + * - *{prefix}*\ __Syms.cpp + - Global symbol table C++ + * - *{prefix}*\ __Syms.h + - Global symbol table header + * - *{prefix}*\ __Trace{__n}*\ .cpp + - Wave file generation code (from --trace) + * - *{prefix}*\ __Trace__Slow{__n}*\ .cpp + - Wave file generation code (from --trace) + * - *{prefix}{each_verilog_module}*\ .cpp + - Lower level internal C++ files + * - *{prefix}{each_verilog_module}*\ .h + - Lower level internal header files + * - *{prefix}{each_verilog_module}{__n}*\ .cpp + - Additional lower C++ files (from --output-split) + +For --hierarchy mode, it creates: + +.. list-table:: + + * - V\ *{hier_block}*\ / + - Directory to Verilate each hierarchy block (from --hierarchy) + * - *{prefix}*\ __hierVer.d + - Make dependencies of the top module (from --hierarchy) + * - *{prefix}*\ __hier.dir + - Directory to store .dot, .vpp, .tree of top module (from --hierarchy) + +In certain debug and other modes, it also creates: + +.. list-table:: + + * - *{prefix}*\ .xml + - XML tree information (from --xml) + * - *{prefix}*\ __cdc.txt + - Clock Domain Crossing checks (from --cdc) + * - *{prefix}*\ __stats.txt + - Statistics (from --stats) + * - *{prefix}*\ __idmap.txt + - Symbol demangling (from --protect-ids) + * - *{prefix}*\ __ver.d + - Make dependencies (from -MMD) + * - *{prefix}*\ __verFiles.dat + - Timestamps (from --skip-identical) + * - *{prefix}{misc}*\ .dot + - Debugging graph files (from --debug) + * - *{prefix}{misc}*\ .tree + - Debugging files (from --debug) + * - {mod_prefix}_{each_verilog_module}*{__n}*\ .vpp + - Pre-processed verilog (from --debug) + +After running Make, the C++ compiler may produce the following: + +.. list-table:: + + * - verilated{misc}*\ .d + - Intermediate dependencies + * - verilated{misc}*\ .o + - Intermediate objects + * - {mod_prefix}{misc}*\ .d + - Intermediate dependencies + * - {mod_prefix}{misc}*\ .o + - Intermediate objects + * - *{prefix}*\ + - Final executable (from --exe) + * - *{prefix}*\ __ALL.a + - Library of all Verilated objects + * - *{prefix}*\ __ALL.cpp + - Include of all code for single compile + * - *{prefix}{misc}*\ .d + - Intermediate dependencies + * - *{prefix}{misc}*\ .o + - Intermediate objects diff --git a/docs/guide/index.rst b/docs/guide/index.rst new file mode 100644 index 000000000..42c18b4c1 --- /dev/null +++ b/docs/guide/index.rst @@ -0,0 +1,37 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. toctree:: + :maxdepth: 2 + :caption: Getting Started + + overview.rst + examples.rst + install.rst + + +.. toctree:: + :maxdepth: 2 + :caption: User's Guide + + verilating.rst + connecting.rst + simulating.rst + contributing.rst + faq.rst + + +.. toctree:: + :maxdepth: 1 + :caption: Reference Guide + + languages.rst + extensions.rst + executables.rst + warnings.rst + files.rst + environment.rst + deprecations.rst + contributors.rst + changes.rst + copyright.rst diff --git a/docs/guide/install.rst b/docs/guide/install.rst new file mode 100644 index 000000000..7154315ce --- /dev/null +++ b/docs/guide/install.rst @@ -0,0 +1,321 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Installation: + +************ +Installation +************ + +This section discusses how to install Verilator. + +.. _Package Manager Quick Install: + +Package Manager Quick Install +============================= + +Using a distribution's package manager is the easiest way to get +started. (Note packages are unlikely to have the most recent version, so +:ref:`Git Install`, might be a better alternative.) To install as a +package: + +:: + + apt-get install verilator # On Ubuntu + + +.. _Git Install: + +Git Quick Install +================= + +Installing Verilator from Git provides the most flexibility. For additional +options and details see :ref:`Detailed Build Instructions` below. + +In brief, to install from git: + +:: + + # Prerequisites: + #sudo apt-get install git perl python3 make autoconf g++ flex bison ccache + #sudo apt-get install libgoogle-perftools-dev numactl perl-doc + #sudo apt-get install libfl2 # Ubuntu only (ignore if gives error) + #sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error) + #sudo apt-get install zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error) + + git clone https://github.com/verilator/verilator # Only first time + ## Note the URL above is not a page you can see with a browser, it's for git only + + # Every time you need to build: + unsetenv VERILATOR_ROOT # For csh; ignore error if on bash + unset VERILATOR_ROOT # For bash + cd verilator + git pull # Make sure git repository is up-to-date + git tag # See what versions exist + #git checkout master # Use development branch (e.g. recent bug fixes) + #git checkout stable # Use most recent stable release + #git checkout v{version} # Switch to specified release version + + autoconf # Create ./configure script + ./configure # Configure and create Makefile + make -j # Build Verilator itself + sudo make install + + +.. _Detailed Build Instructions: + +Detailed Build Instructions +=========================== + +This section describes details of the build process, and assumes you are +building from Git. For using a pre-built binary for your Linux +distribution, see instead :ref:`Package Manager Quick Install`. + + +OS Requirements +--------------- + +Verilator is developed and has primary testing on Ubuntu, with additional +testing on FreeBSD and Apple OS-X. Versions have also built on Redhat +Linux, HPUX and Solaris. It should run with minor porting on any +GNU/Linux-ish platform. Verilator also works on Windows under Cygwin, and +Windows under MinGW (gcc -mno-cygwin). Verilated output (not Verilator +itself) compiles under all the options above, plus using MSVC++. + + +Install Prerequisites +--------------------- + +To build or run Verilator you need these standard packages: + +:: + + sudo apt-get install git perl python3 make + sudo apt-get install g++ # Alternatively, clang + sudo apt-get install libgz # Non-Ubuntu (ignore if gives error) + sudo apt-get install libfl2 # Ubuntu only (ignore if gives error) + sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error) + sudo apt-get install zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error) + +To build or run the following are optional but should be installed for good +performance: + +:: + + sudo apt-get install ccache # If present at build, needed for run + sudo apt-get install libgoogle-perftools-dev numactl perl-doc + +To build Verilator you will need to install these packages; these do not +need to be present to run Verilator: + +:: + + sudo apt-get install git autoconf flex bison + +Those developing Verilator itself may also want these (see internals.rst): + +:: + + sudo apt-get install gdb graphviz cmake clang clang-format gprof lcov + sudo pip3 install sphinx sphinx_rtd_theme breathe + cpan install Pod::Perldoc + cpan install Parallel::Forker + + +Install SystemC +^^^^^^^^^^^^^^^ + +If you will be using SystemC (vs straight C++ output), download `SystemC +`__. Follow their +installation instructions. You will need to set the +:option:`SYSTEMC_INCLUDE` environment variable to point to the include +directory with ``systemc.h`` in it, and set the :option:`SYSTEMC_LIBDIR` +environment variable to point to the directory with ``libsystemc.a`` in it. + + +Install GTKWave +^^^^^^^^^^^^^^^ + +To make use of Verilator FST tracing you will want `GTKwave +`__ installed, however this is not +required at Verilator build time. + + +Obtain Sources +-------------- + +Get the sources from the git repository: (You need do this only once, +ever.) + +:: + + git clone https://github.com/verilator/verilator # Only first time + ## Note the URL above is not a page you can see with a browser, it's for git only + +Enter the checkout and determine what version/branch to use: + +:: + + cd verilator + git pull # Make sure we're up-to-date + git tag # See what versions exist + #git checkout master # Use development branch (e.g. recent bug fix) + #git checkout stable # Use most recent release + #git checkout v{version} # Switch to specified release version + + +Auto Configure +-------------- + +Create the configuration script: + +:: + + autoconf # Create ./configure script + + +Eventual Installation Options +----------------------------- + +Before configuring the build, you have to decide how you're going to +eventually install Verilator onto your system. Verilator will be compiling +the current value of the environment variables :option:`VERILATOR_ROOT`, +:option:`SYSTEMC_INCLUDE`, and :option:`SYSTEMC_LIBDIR` as defaults into +the executable, so they must be correct before configuring. + +These are the installation options: + + +1. Run-in-Place from VERILATOR_ROOT +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Our personal favorite is to always run Verilator in-place from its Git +directory. This allows the easiest experimentation and upgrading, and +allows many versions of Verilator to co-exist on a system. + +:: + + export VERILATOR_ROOT=`pwd` # if your shell is bash + setenv VERILATOR_ROOT `pwd` # if your shell is csh + ./configure + # Running will use files from $VERILATOR_ROOT, so no install needed + +Note after installing (below steps), a calling program or shell must set +the environment variable :option:`VERILATOR_ROOT` to point to this Git +directory, then execute ``$VERILATOR_ROOT/bin/verilator``, which will find +the path to all needed files. + + +2. Install into a specific location +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +You may eventually be installing onto a project/company-wide "CAD" tools +disk that may support multiple versions of every tool. Tell configure the +eventual destination directory name. We recommend the destination location +include the Verilator version name: + +:: + + unset VERILATOR_ROOT # if your shell is bash + unsetenv VERILATOR_ROOT # if your shell is csh + # For the tarball, use the version number instead of git describe + ./configure --prefix /CAD_DISK/verilator/`git describe | sed "s/verilator_//"` + +Note after installing (below steps), if you use `modulecmd +`__, you'll want a module file like the +following: + +:: + + set install_root /CAD_DISK/verilator/{version-number-used-above} + unsetenv VERILATOR_ROOT + prepend-path PATH $install_root/bin + prepend-path MANPATH $install_root/man + prepend-path PKG_CONFIG_PATH $install_root/share/pkgconfig + + +3. Install into a Specific Path +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +You may eventually install Verilator into a specific installation prefix, +as most GNU tools support: + +:: + + unset VERILATOR_ROOT # if your shell is bash + unsetenv VERILATOR_ROOT # if your shell is csh + ./configure --prefix /opt/verilator-VERSION + +Then after installing (below steps) you will need to add +``/opt/verilator-VERSION/bin`` to your ``$PATH`` environment variable. + + +4. Install System Globally +^^^^^^^^^^^^^^^^^^^^^^^^^^ + +The final option is to eventually install Verilator globally, using +configure's default system paths: + +:: + + unset VERILATOR_ROOT # if your shell is bash + unsetenv VERILATOR_ROOT # if your shell is csh + ./configure + +Then after installing (below) the binaries should be in a location that is +already in your ``$PATH`` environment variable. + + +Configure +--------- + +The command to configure the package was described in the previous step. +Developers should configure to have more complete developer tests. +Additional packages may be required for these tests. + +:: + + export VERILATOR_AUTHOR_SITE=1 # Put in your .bashrc + ./configure --enable-longtests ...above options... + + +Compile +------- + +Compile Verilator: + +:: + + make -j + + +Test +---- + +Check the compilation by running self-tests: + +:: + + make test + + +Install +------- + +If you used any install option other than the `1. Run-in-Place from +VERILATOR_ROOT <#_1_run_in_place_from_verilator_root>`__ scheme, install +the files: + +:: + + make install + + +.. Docker Build Environment + +.. include:: ../../ci/docker/buildenv/README.rst + + +.. Docker Run Environment + +.. include:: ../../ci/docker/run/README.rst diff --git a/docs/guide/languages.rst b/docs/guide/languages.rst new file mode 100644 index 000000000..f09abbd26 --- /dev/null +++ b/docs/guide/languages.rst @@ -0,0 +1,477 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +*************** +Input Languages +*************** + +This section describes the languages Verilator takes as input. See also +:ref:`Configuration Files`. + + +Language Standard Support +========================= + +Verilog 2001 (IEEE 1364-2001) Support +------------------------------------- + +Verilator supports most Verilog 2001 language features. This includes +signed numbers, "always @\*", generate statements, multidimensional arrays, +localparam, and C-style declarations inside port lists. + + +Verilog 2005 (IEEE 1364-2005) Support +------------------------------------- + +Verilator supports most Verilog 2005 language features. This includes the +\`begin_keywords and \`end_keywords compiler directives, $clog2, and the +uwire keyword. + + +SystemVerilog 2005 (IEEE 1800-2005) Support +------------------------------------------- + +Verilator supports ==? and !=? operators, ++ and -- in some contexts, +$bits, $countbits, $countones, $error, $fatal, $info, $isunknown, $onehot, +$onehot0, $unit, $warning, always_comb, always_ff, always_latch, bit, byte, +chandle, const, do-while, enum, export, final, import, int, interface, +logic, longint, modport, package, program, shortint, struct, time, typedef, +union, var, void, priority case/if, and unique case/if. + +It also supports .name and .\* interconnection. + +Verilator partially supports concurrent assert and cover statements; see +the enclosed coverage tests for the syntax which is allowed. + +Verilator has limited support for class and related object-oriented +constructs. + + +SystemVerilog 2012 (IEEE 1800-2012) Support +------------------------------------------- + +Verilator implements a full SystemVerilog-compliant preprocessor, including +function call-like preprocessor defines, default define arguments, +\`__FILE__, \`__LINE__ and \`undefineall. + + +SystemVerilog 2017 (IEEE 1800-2017) Support +------------------------------------------- + +Verilator supports the 2017 "for" loop constructs, and several minor +cleanups IEEE made in 1800-2017. + + +Verilog AMS Support +------------------- + +Verilator implements a very small subset of Verilog AMS (Verilog Analog and +Mixed-Signal Extensions) with the subset corresponding to those VMS +keywords with near equivalents in the Verilog 2005 or SystemVerilog 2009 +languages. + +AMS parsing is enabled with :vlopt:`--language VAMS <--language>` or +:vlopt:`--language 1800+VAMS <--language>`. + +At present Verilator implements ceil, exp, floor, ln, log, pow, sqrt, +string, and wreal. + + +Synthesis Directive Assertion Support +------------------------------------- + +With the :vlopt:`--assert` option, Verilator reads any :code:`//synopsys +full_case` or :code:`//synopsys parallel_case` directives. The same +applies to any :code:`//ambit synthesis`, :code:`//cadence` or +:code:`//pragma` directives of the same form. + +When these synthesis directives are discovered, Verilator will either +formally prove the directive to be true, or failing that, will insert the +appropriate code to detect failing cases at simulation runtime and print an +"Assertion failed" error message. + +Verilator likewise also asserts any "unique" or "priority" SystemVerilog +keywords on case statement, as well as "unique" on if statements. However, +"priority if" is currently simply ignored. + + +.. _Language Limitations: + +Language Limitations +==================== + +This section describes the language limitations of Verilator. Many of these +restrictions are by intent. + +Synthesis Subset +---------------- + +Verilator supports the Synthesis subset with other verification constructs +being added over time. Verilator also simulates events as Synopsys's Design +Compiler would; namely given a block of the form: + +.. code-block:: sv + + always @(x) y = x & z; + +This will recompute y when there is even a potential for change in x or a +change in z, that is when the flops computing x or z evaluate (which is +what Design Compiler will synthesize.) A compliant simulator would only +calculate y if x changes. We recommend using always_comb to make the code +run the same everywhere. Also avoid putting $displays in combo blocks, as +they may print multiple times when not desired, even on compliant +simulators as event ordering is not specified. + + +Signal Naming +------------- + +To avoid conflicts with C symbol naming, any character in a signal name +that is not alphanumeric nor a single underscore will be replaced by __0hh +where hh is the hex code of the character. To avoid conflicts with +Verilator's internal symbols, any double underscore are replaced with +___05F (5F is the hex code of an underscore.) + + +Bind +---- + +sVerilator only supports bind to a target module name, not to an +instance path. + + +Class +----- + +Verilator class support is limited but in active development. Verilator +supports members, and methods. Verilator does not support class static +members, class extend, or class parameters. + + +Dotted cross-hierarchy references +--------------------------------- + +Verilator supports dotted references to variables, functions and tasks in +different modules. The portion before the dot must have a constant value; +for example a[2].b is acceptable, while a[x].b is generally not. + +References into generated and arrayed instances use the instance names +specified in the Verilog standard; arrayed instances are named +``{instanceName}[{instanceNumber}]`` in Verilog, which becomes +``{instanceName}__BRA__{instanceNumber}__KET__`` inside the generated C++ +code. + + +Latches +------- + +Verilator is optimized for edge sensitive (flop based) designs. It will +attempt to do the correct thing for latches, but most performance +optimizations will be disabled around the latch. + + +Structures and Unions +--------------------- + +Presently Verilator only supports packed structs and packed unions. Rand +and randc tags on members are simply ignored. All structures and unions +are represented as a single vector, which means that generating one member +of a structure from blocking, and another from non-blocking assignments is +unsupported. + + +Time +---- + +All delays (#) are ignored, as they are in synthesis. + + +.. _Unknown States: + +Unknown States +-------------- + +Verilator is mostly a two state simulator, not a four state simulator. +However, it has two features which uncover most initialization bugs +(including many that a four state simulator will miss.) + +Identity comparisons (=== or !==) are converted to standard ==/!= when +neither side is a constant. This may make the expression yield a different +result compared to a four state simulator. An === comparison to X will +always be false, so that Verilog code which checks for uninitialized logic +will not fire. + +Assigning X to a variable will actually assign a constant value as +determined by the :vlopt:`--x-assign` option. This allows runtime +randomization, thus if the value is actually used, the random value should +cause downstream errors. Integers also get randomized, even though the +Verilog 2001 specification says they initialize to zero. Note however that +randomization happens at initialization time and hence during a single +simulation run, the same constant (but random) value will be used every +time the assignment is executed. + +All variables, depending on :vlopt:`--x-initial` setting, are typically +randomly initialized using a function. By running several random +simulation runs you can determine that reset is working correctly. On the +first run, have the function initialize variables to zero. On the second, +have it initialize variables to one. On the third and following runs have +it initialize them randomly. If the results match, reset works. (Note +this is what the hardware will really do.) In practice, just setting all +variables to one at startup finds most problems (since typically control +signals are active-high). + +:vlopt:`--x-assign` applies to variables explicitly initialized or assigned +an X. Uninitialized clocks are initialized to zero, while all other state +holding variables are initialized to a random value. Event driven +simulators will generally trigger an edge on a transition from X to 1 +(posedge) or X to 0 (negedge). However, by default, since clocks are +initialized to zero, Verilator will not trigger an initial negedge. Some +code (particularly for reset) may rely on X->0 triggering an edge. The +:vlopt:`--x-initial-edge` option enables this behavior. Comparing runs with +and without this option will find such problems. + + +Tri/Inout +--------- + +Verilator converts some simple tristate structures into two state. Pullup, +pulldown, bufif0, bufif1, notif0, notif1, pmos, nmos, tri0 and tri1 are +also supported. Simple comparisons with :code:`=== 1'bz` are also +supported. + +An assignment of the form: + +.. code-block:: sv + + inout driver; + wire driver = (enable) ? output_value : 1'bz; + +Will be converted to: + +.. code-block:: sv + + input driver; // Value being driven in from "external" drivers + output driver__en; // True if driven from this module + output driver__out; // Value being driven from this module + +External logic will be needed to combine these signals with any external +drivers. + +Tristate drivers are not supported inside functions and tasks; an inout +there will be considered a two state variable that is read and written +instead of a four state variable. + + +Functions & Tasks +----------------- + +All functions and tasks will be inlined (will not become functions in C.) +The only support provided is for simple statements in tasks (which may +affect global variables). + +Recursive functions and tasks are not supported. All inputs and outputs +are automatic, as if they had the Verilog 2001 "automatic" keyword +prepended. (If you don't know what this means, Verilator will do what you +probably expect, what C does. The default behavior of Verilog is +different.) + + +Generated Clocks +---------------- + +Verilator attempts to deal with generated and gated clocks correctly, +however some cases cause problems in the scheduling algorithm which is +optimized for performance. The safest option is to have all clocks as +primary inputs to the model, or wires directly attached to primary inputs. +For proper behavior clock enables may also need the +:option:`/*verilator&32;clock_enable*/` metacomment. + + +Gate Primitives +--------------- + +The 2-state gate primitives (and, buf, nand, nor, not, or, xnor, xor) are +directly converted to behavioral equivalents. The 3-state and MOS gate +primitives are not supported. Tables are not supported. + + +Specify blocks +-------------- + +All specify blocks and timing checks are ignored. All min:typ:max delays +use the typical value. + + +Array Initialization +-------------------- + +When initializing a large array, you need to use non-delayed assignments. +Verilator will tell you when this needs to be fixed; see the BLKLOOPINIT +error for more information. + + +Array Out of Bounds +------------------- + +Writing a memory element that is outside the bounds specified for the array +may cause a different memory element inside the array to be written +instead. For power-of-2 sized arrays, Verilator will give a width warning +and the address. For non-power-of-2-sizes arrays, index 0 will be written. + +Reading a memory element that is outside the bounds specified for the array +will give a width warning and wrap around the power-of-2 size. For +non-power-of-2 sizes, it will return a unspecified constant of the +appropriate width. + + +Assertions +---------- + +Verilator is beginning to add support for assertions. Verilator currently +only converts assertions to simple :code:`if (...) error` statements, and +coverage statements to increment the line counters described in the +coverage section. + +Verilator does not support SEREs yet. All assertion and coverage +statements must be simple expressions that complete in one cycle. + + +Encrypted Verilog +----------------- + +Open source simulators like Verilator are unable to use encrypted RTL +(i.e. IEEE P1735). Talk to your IP vendor about delivering IP blocks via +Verilator's :vlopt:`--protect-lib` feature. + + +Language Keyword Limitations +============================ + +This section describes specific limitations for each language keyword. + +.. Hack to get long definition list: +.. |cmdslong1| replace:: \`__FILE__, \`__LINE__, \`begin_keywords, + \`begin_keywords, \`begin_keywords, \`begin_keywords, \`begin_keywords, + \`define, \`else, \`elsif, \`end_keywords, \`endif, \`error, \`ifdef, + \`ifndef, \`include, \`line, \`systemc_ctor, \`systemc_dtor, + \`systemc_header, \`systemc_imp_header, \`systemc_implementation, + \`systemc_interface, \`undef, \`verilog + +|cmdslong1| + Fully supported. + + +.. Hack to get long definition list: + +.. |cmdslong2| replace:: always, always_comb, always_ff, always_latch, and, + assign, begin, buf, byte, case, casex, casez, default, defparam, + do-while, else, end, endcase, endfunction, endgenerate, endmodule, + endspecify, endtask, final, for, function, generate, genvar, if, + initial, inout, input, int, integer, localparam, logic, longint, + macromodule, module, nand, negedge, nor, not, or, output, parameter, + posedge, reg, scalared, shortint, signed, supply0, supply1, task, time, + tri, typedef, var, vectored, while, wire, xnor, xor + +|cmdslong2| + Generally supported. + +++, -- operators + Increment/decrement can only be used as standalone statements or in + certain limited cases. + +'{} operator + Assignment patterns with order based, default, constant integer (array) + or member identifier (struct/union) keys are supported. Data type keys + and keys which are computed from a constant expression are not supported. + +\`uselib + Uselib, a vendor specific library specification method, is ignored along + with anything following it until the end of that line. + +cast operator + Casting is supported only between simple scalar types, signed and + unsigned, not arrays nor structs. + +chandle + Treated as a "longint"; does not yet warn about operations that are + specified as illegal on chandles. + +disable + Disable statements may be used only if the block being disabled is a + block the disable statement itself is inside. This was commonly used to + provide loop break and continue functionality before SystemVerilog added + the break and continue keywords. + +inside + Inside expressions may not include unpacked array traversal or $ as an + upper bound. Case inside and case matches are also unsupported. + +interface + Interfaces and modports, including with generated data types are + supported. Generate blocks around modports are not supported, nor are + virtual interfaces nor unnamed interfaces. + +shortreal + Short floating point (shortreal) numbers are converted to real. Most + other simulators either do not support float, or convert likewise. + +specify specparam + All specify blocks and timing checks are ignored. + +uwire + Verilator does not perform warning checking on uwires, it treats the + uwire keyword as if it were the normal wire keyword. + +$bits, $countbits, $countones, $finish, $isunknown, $onehot, $onehot0, $signed, $stime, $stop, $time, $unsigned, + Generally supported. + +$dump/$dumpports and related + $dumpfile or $dumpports will create a VCD or FST file (which is based on + the :vlopt:`--trace` option given when the model was Verilated). This + will take effect starting at the next eval() call. If you have multiple + Verilated designs under the same C model, then this will dump signals + only from the design containing the $dumpvars. + + $dumpvars and $dumpports module identifier is ignored; the traced + instances will always start at the top of the design. The levels argument + is also ignored, use tracing_on/tracing_off pragmas instead. + + $dumpportson/$dumpportsoff/$dumpportsall/$dumpportslimit filename + argument is ignored, only a single trace file may be active at once. + + $dumpall/$dumpportsall, $dumpon/$dumpportson, $dumpoff/$dumpportsoff, and + $dumplimit/$dumpportlimit are currently ignored. + +$error, $fatal, $info, $warning. + Generally supported. + +$exit, $finish, $stop + The rarely used optional parameter to $finish and $stop is ignored. $exit + is aliased to $finish. + +$fopen, $fclose, $fdisplay, $ferror, $feof, $fflush, $fgetc, $fgets, $fscanf, $fwrite, $fscanf, $sscanf + Generally supported. + +$fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal, $setup, $setuphold, $skew, $timeskew, $width + All specify blocks and timing checks are ignored. + +$random, $urandom, $urandom_range + Use :vlopt:`+verilator+seed+\` runtime option to set the seed if + there is no $random nor $urandom optional argument to set the seed. + There is one random seed per C thread, not per module for $random, nor + per object for random stability of $urandom/$urandom_range. + +$readmemb, $readmemh + Read memory commands are supported. Note Verilator and the Verilog + specification does not include support for readmem to multi-dimensional + arrays. + +$test$plusargs, $value$plusargs + Supported, but the instantiating C++/SystemC wrapper must call + + .. code-block:: C++ + + Verilated::commandArgs(argc, argv); + + to register the command line before calling $test$plusargs or + $value$plusargs. diff --git a/docs/guide/overview.rst b/docs/guide/overview.rst new file mode 100644 index 000000000..2c60dd2b8 --- /dev/null +++ b/docs/guide/overview.rst @@ -0,0 +1,55 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +******** +Overview +******** + +Welcome to Verilator! + +The Verilator package converts Verilog [#]_ and SystemVerilog [#]_ hardware +description language (HDL) designs into a C++ or SystemC model that after +compiling can be executed. Verilator is not a traditional simulator, but a +compiler. + +Verilator is typically used as follows: + +1. The :command:`verilator` executable is invoked with parameters similar +to GCC, or other simulators such as Cadence Verilog-XL/NC-Verilog, or +Synopsys VCS. Verilator reads the specified SystemVerilog code, lints it, +optionally adds coverage and waveform tracing support, and compiles the +design into a source level multithreaded C++ or SystemC "model". The +resulting model's C++ or SystemC code is output as .cpp and .h files. This +is referred to as "Verilating" and the process is "to Verilate"; the output +is a "Verilated" model. + +2. For simulation, a small user written C++ wrapper file is required, the +"wrapper". This wrapper defines the C++ standard function "main()" which +instantiates the Verilated model as a C++/SystemC object. + +3. The user C++ wrapper, the files created by Verilator, a "runtime +library" provided by Verilator, and if applicable SystemC libraries are +then compiled using a C++ compiler to create a simulation executable. + +4. The resulting executable will perform the actual simulation, during +"simulation runtime". + +5. If appropriately enabled, the executable may also generate waveform +traces of the design that may be viewed. It may also create coverage +analysis data for post-analysis. + +The best place to get started is to try the :ref:`Examples`. + + +.. [#] Verilog is defined by the `Institute of Electrical and Electronics + Engineers (IEEE) Standard for Verilog Hardware Description + Language`, Std. 1364, released in 1995, 2001, and 2005. The + Verilator documentation uses the shorthand e.g. "IEEE 1394-2005" to + refer to the e.g. 2005 version of this standard. + +.. [#] SystemVerilog is defined by the `Institute of Electrical and + Electronics Engineers (IEEE) Standard for SystemVerilog - Unified + Hardware Design, Specification, and Verification Language`, Standard + 1800, released in 2005, 2009, 2012, and 2017. The Verilator + documentation uses the shorthand e.g. "IEEE 1800-2017" to refer to + the e.g. 2017 version of this standard. diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst new file mode 100644 index 000000000..e817dae4c --- /dev/null +++ b/docs/guide/simulating.rst @@ -0,0 +1,352 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +.. _Simulating: + +************************************ +Simulating (Verilated-Model Runtime) +************************************ + +This section describes items related to simulating, that using a Verilated +model's executable. For the runtime arguments to a simulated model, see +:ref:`Simulation Runtime Arguments`. + + +.. _Benchmarking & Optimization: + +Benchmarking & Optimization +=========================== + +For best performance, run Verilator with the :vlopt:`-O3` +:vlopt:`--x-assign fast <--x-assign>` :vlopt:`--x-initial fast +<--x-initial>` :vlopt:`--noassert <--assert>` options. The :vlopt:`-O3` +option will require longer time to run Verilator, and :vlopt:`--x-assign +fast <--x-assign>` :vlopt:`--x-initial fast <--x-assign>` may increase the +risk of reset bugs in trade for performance; see the above documentation +for these options. + +If using Verilated multithreaded, use ``numactl`` to ensure you are using +non-conflicting hardware resources. See :ref:`Multithreading`. + +Minor Verilog code changes can also give big wins. You should not have any +UNOPTFLAT warnings from Verilator. Fixing these warnings can result in +huge improvements; one user fixed their one UNOPTFLAT warning by making a +simple change to a clock latch used to gate clocks and gained a 60% +performance improvement. + +Beyond that, the performance of a Verilated model depends mostly on your +C++ compiler and size of your CPU's caches. Experience shows that large +models are often limited by the size of the instruction cache, and as such +reducing code size if possible can be beneficial. + +The supplied $VERILATOR_ROOT/include/verilated.mk file uses the OPT, +OPT_FAST, OPT_SLOW and OPT_GLOBAL variables to control optimization. You +can set these when compiling the output of Verilator with Make, for +example: + +.. code-block:: bash + + make OPT_FAST="-Os -march=native" -f Vour.mk Vour__ALL.a + +OPT_FAST specifies optimization options for those parts of the model that +are on the fast path. This is mostly code that is executed every +cycle. OPT_SLOW applies to slow-path code, which executes rarely, often +only once at the beginning or end of simulation. Note that OPT_SLOW is +ignored if VM_PARALLEL_BUILDS is not 1, in which case all generated code +will be compiled in a single compilation unit using OPT_FAST. See also the +Verilator :vlopt:`--output-split` option. The OPT_GLOBAL variable applies +to common code in the runtime library used by Verilated models (shipped in +$VERILATOR_ROOT/include). Additional C++ files passed on the verilator +command line use OPT_FAST. The OPT variable applies to all compilation +units in addition to the specific "OPT" variables described above. + +You can also use the :vlopt:`-CFLAGS` and/or :vlopt:`-LDFLAGS` options on +the verilator command line to pass arguments directly to the compiler or +linker. + +The default values of the "OPT" variables are chosen to yield good +simulation speed with reasonable C++ compilation times. To this end, +OPT_FAST is set to "-Os" by default. Higher optimization such as "-O2" or +"-O3" may help (though often they provide only a very small performance +benefit), but compile times may be excessively large even with medium sized +designs. Compilation times can be improved at the expense of simulation +speed by reducing optimization, for example with OPT_FAST="-O0". Often good +simulation speed can be achieved with OPT_FAST="-O1 -fstrict-aliasing" but +with improved compilation times. Files controlled by OPT_SLOW have little +effect on performance and therefore OPT_SLOW is empty by default +(equivalent to "-O0") for improved compilation speed. In common use-cases +there should be little benefit in changing OPT_SLOW. OPT_GLOBAL is set to +"-Os" by default and there should rarely be a need to change it. As the +runtime library is small in comparison to a lot of Verilated models, +disabling optimization on the runtime library should not have a serious +effect on overall compilation time, but may have detrimental effect on +simulation speed, especially with tracing. In addition to the above, for +best results use OPT="-march=native", the latest Clang compiler (about 10% +faster than GCC), and link statically. + +Generally the answer to which optimization level gives the best user +experience depends on the use case and some experimentation can pay +dividends. For a speedy debug cycle during development, especially on large +designs where C++ compilation speed can dominate, consider using lower +optimization to get to an executable faster. For throughput oriented use +cases, for example regressions, it is usually worth spending extra +compilation time to reduce total CPU time. + +If you will be running many simulations on a single model, you can +investigate profile guided optimization. With GCC, using GCC's +"-fprofile-arcs", then GCC's "-fbranch-probabilities" will yield another +15% or so. + +Modern compilers also support link-time optimization (LTO), which can help +especially if you link in DPI code. To enable LTO on GCC, pass "-flto" in +both compilation and link. Note LTO may cause excessive compile times on +large designs. + +Unfortunately, using the optimizer with SystemC files can result in +compilation taking several minutes. (The SystemC libraries have many little +inlined functions that drive the compiler nuts.) + +If you are using your own makefiles, you may want to compile the Verilated +code with ``--MAKEFLAGS -DVL_INLINE_OPT=inline``. This will inline +functions, however this requires that all cpp files be compiled in a single +compiler run. + +You may uncover further tuning possibilities by profiling the Verilog code. +See :ref:`profiling`. + +When done optimizing, please let the author know the results. We like to +keep tabs on how Verilator compares, and may be able to suggest additional +improvements. + + +.. _Coverage Analysis: + +Coverage Analysis +================= + +Verilator supports adding code to the Verilated model to support +SystemVerilog code coverage. With :vlopt:`--coverage`, Verilator enables +all forms of coverage: + +* :ref:`User Coverage` +* :ref:`Line Coverage` +* :ref:`Toggle Coverage` + +When a model with coverage is executed, it will create a coverage file for +collection and later analysis, see :ref:`Coverage Collection`. + + +.. _User Coverage: + +Functional Coverage +------------------- + +With :vlopt:`--coverage` or :vlopt:`--coverage-user`, Verilator will +translate functional coverage points which the user has inserted manually +into the SystemVerilog design, into the Verilated model. + +Currently, all functional coverage points are specified using SystemVerilog +assertion syntax which must be separately enabled with :vlopt:`--assert`. + +For example, the following SystemVerilog statement will add a coverage +point, under the coverage name "DefaultClock": + +.. code-block:: sv + + DefaultClock: cover property (@(posedge clk) cyc==3); + + +.. _Line Coverage: + +Line Coverage +------------- + +With :vlopt:`--coverage` or :vlopt:`--coverage-line`, Verilator will +automatically add coverage analysis at each code flow change point (e.g. at +branches). At each such branch a unique counter is incremented. At the +end of a test, the counters along with the filename and line number +corresponding to each counter are written into the coverage file. + +Verilator automatically disables coverage of branches that have a $stop in +them, as it is assumed $stop branches contain an error check that should +not occur. A :option:`/*verilator&32;coverage_block_off*/` metacomment +will perform a similar function on any code in that block or below, or +:option:`/*verilator&32;coverage_off*/` and +:option:`/*verilator&32;coverage_on*/` will disable and enable coverage +respectively around a block of code. + +Verilator may over-count combinatorial (non-clocked) blocks when those +blocks receive signals which have had the UNOPTFLAT warning disabled; for +most accurate results do not disable this warning when using coverage. + + +.. _Toggle Coverage: + +Toggle Coverage +--------------- + +With :vlopt:`--coverage` or :vlopt:`--coverage-toggle`, Verilator will +automatically add toggle coverage analysis into the Verilated model. + +Every bit of every signal in a module has a counter inserted. The counter +will increment on every edge change of the corresponding bit. + +Signals that are part of tasks or begin/end blocks are considered local +variables and are not covered. Signals that begin with underscores (see +:vlopt:`--coverage-underscore`), are integers, or are very wide (>256 bits +total storage across all dimensions, see :vlopt:`--coverage-max-width`) are +also not covered. + +Hierarchy is compressed, such that if a module is instantiated multiple +times, coverage will be summed for that bit across **all** instantiations +of that module with the same parameter set. A module instantiated with +different parameter values is considered a different module, and will get +counted separately. + +Verilator makes a minimally-intelligent decision about what clock domain +the signal goes to, and only looks for edges in that clock domain. This +means that edges may be ignored if it is known that the edge could never be +seen by the receiving logic. This algorithm may improve in the future. +The net result is coverage may be lower than what would be seen by looking +at traces, but the coverage is a more accurate representation of the +quality of stimulus into the design. + +There may be edges counted near time zero while the model stabilizes. It's +a good practice to zero all coverage just before releasing reset to prevent +counting such behavior. + +A :option:`/*verilator&32;coverage_off*/` +:option:`/*verilator&32;coverage_on*/` metacomment pair can be used around +signals that do not need toggle analysis, such as RAMs and register files. + + +.. _Coverage Collection: + +Coverage Collection +------------------- + +When any coverage flag was used to Verilate, Verilator will add appropriate +coverage point insertions into the model and collect the coverage data. + +To get the coverage data from the model, in the user wrapper code, +typically at the end once a test passes, call +:code:`Verilated::coveragep()->write` with an argument of the filename for +the coverage data file to write coverage data to (typically +"logs/coverage.dat"). + +Run each of your tests in different directories, potentially in parallel. +Each test will create a :file:`logs/coverage.dat` file. + +After running all of the tests, execute the :command:`verilator_coverage` +command, passing arguments pointing to the filenames of all of the +individual coverage files. :command:`verilator_coverage` will reads the +:file:`logs/coverage.dat` file(s), and create an annotated source code +listing showing code coverage details. + +:command:`verilator_coverage` may also be used for test grading, that is +computing which tests are important to fully cover the design. + +For an example, see the :file:`examples/make_tracing_c/logs` directory. +Grep for lines starting with '%' to see what lines Verilator believes need +more coverage. + +Additional options of :command:`verilator_coverage` allow for merging of +coverage data files or other transformations. + +Info files can be written by verilator_coverage for import to +:command:`lcov`. This enables use of :command:`genhtml` for HTML reports +and importing reports to sites such as `https://codecov.io +`_. + + +.. _Profiling: + +Code Profiling +============== + +The Verilated model may be code-profiled using GCC or Clang's C++ profiling +mechanism. Verilator provides additional flags to help map the resulting +C++ profiling results back to the original Verilog code responsible for the +profiled C++ code functions. + +To use profiling: + +#. Use Verilator's :vlopt:`--prof-cfuncs`. +#. Use Verilator's :vlopt:`-CFLAGS "-g -pg" <-CFLAGS>` to pass the + profiling flags through to GCC/Clang. +#. Build and run the simulation model. +#. The model will create gmon.out. +#. Run :command:`gprof` to see where in the C++ code the time is spent. +#. Run the gprof output through the :command:`verilator_profcfunc` program + and it will tell you what Verilog line numbers on which most of the time + is being spent. + + +.. _Thread Profiling: + +Thread Profiling +================ + +When using multithreaded mode (:vlopt:`--threads`), it is useful to see +statistics and visualize how well the multiple CPUs are being utilized. + +With the :vlopt:`--prof-threads` option, Verilator will: + +* Add code to the Verilated model to record the start and end time of each + macro-task across a number of calls to eval. (What is a macro-task? See + the Verilator internals document (:file:`docs/internals.rst` in the + distribution.) + +* Add code to save profiling data in non-human-friendly form to the file + specified with :vlopt:`+verilator+prof+threads+file+\`. + +The :command:`verilator_gantt` program may then be run to transform the +saved profiling file into a nicer visual format and produce some related +statistics. + +.. figure:: ../_static/fig_gantt_min.png + + Example verilator_gantt output, as viewed with GTKWave. + + The parallelism shows the number of CPUs being used at a given moment. + + The cpu_thread section shows which thread is executing on each of the physical CPUs. + + The thread_mtask section shows which macro-task is running on a given thread. + +For more information see :command:`verilator_gantt`. + +.. _Save/Restore: + +Save/Restore +============ + +The intermediate state of a Verilated model may be saved, so that it may +later be restored. + +To enable this feature, use :vlopt:`--savable`. There are limitations in +what language features are supported along with :vlopt:`--savable`; if you +attempt to use an unsupported feature Verilator will throw an error. + +To use save/restore, the user wrapper code must create a VerilatedSerialize +or VerilatedDeserialze object then calling the :code:`<<` or :code:`>>` +operators on the generated model and any other data the process needs +saved/restored. These functions are not thread safe, and are typically +called only by a main thread. + +For example: + +.. code-block:: C++ + + void save_model(const char* filenamep) { + VerilatedSave os; + os.open(filenamep); + os << main_time; // user code must save the timestamp, etc + os << *topp; + } + void restore_model(const char* filenamep) { + VerilatedRestore os; + os.open(filenamep); + os >> main_time; + os >> *topp; + } diff --git a/docs/guide/verilating.rst b/docs/guide/verilating.rst new file mode 100644 index 000000000..53810b67e --- /dev/null +++ b/docs/guide/verilating.rst @@ -0,0 +1,482 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +********** +Verilating +********** + +Verilator may be used in five major ways: + +* With the :vlopt:`--cc` or :vlopt:`--sc` options, Verilator will translate + the design into C++ or SystemC code respectively. See :ref:`C++ and + SystemC Generation`. + +* With the :vlopt:`--lint-only` option, Verilator will lint the design to + check for warnings but will not typically create any output files. + +* With the :vlopt:`--xml-only` option, Verilator will create XML output + that may be used to feed into other user-designed tools. See + :file:`docs/xml.rst` in the distribution. + +* With the :vlopt:`-E` option, Verilator will preprocess the code according + to IEEE preprocessing rules, and write the output to standard out. This + is useful to feed other tools, and to debug how "\`define" statements are + expanded. + + +.. _C++ and SystemC Generation: + +C++ and SystemC Generation +========================== + +Verilator will translate a SystemVerilog design into C++ with the +:vlopt:`--cc` option, or into SystemC with the :vlopt:`--sc` option. + +When using these options: + +#. Verilator reads the input Verilog code, determines all "top modules" that + is modules or programs that are not used as instances under other cells. + If :vlopt:`--top-module` is used, then that determines the top module and + all other top modules are removed, otherwise a :vlopt:`MULTITOP` warning + is given. + +#. Verilator writes the C++/SystemC code to output files into the + :vlopt:`--Mdir` option-specified directory, or defaults to "obj_dir". + The prefix is set with :vlopt:`--prefix`, or defaults to the name of the + top module. + +#. If :vlopt:`--exe` is used, Verilator creates makefiles to generate a + simulation executable, otherwise it creates makefiles to generate an + archive (.a) containing the objects. + +#. If :vlopt:`--build` option was used, it calls :ref:`GNU Make` or + :ref:`CMake` to build the model. + +Once a model is built it is then typically run, see :ref:`Simulating`. + + +.. _Hierarchical Verilation: + +Hierarchical Verilation +======================= + +Large designs may take long (e.g. 10+ minutes) and huge memory (e.g. 100+ +GB) to Verilate. In hierarchical mode, the user manually selects some +large lower-level hierarchy blocks to separate from the larger design. For +example a core may be the hierarchy block, and separated out of a +multi-core SoC. + +Verilator is run in hierarchical mode on the whole SoC. Verilator will +make two models, one for the CPU hierarchy block, and one for the SoC. The +Verialted code for the SoC will automatically call the CPU Verilated model. + +The current hierarchical Verilation is based on protect-lib. Each hierarchy +block is Verilated to a protect-lib. User modules of the hierarchy blocks +will see a tiny wrapper generated by protect-lib instead of the actual +design. + + +Usage +----- + +Users need to mark one or more moderate size module as hierarchy block(s). +There are two ways to mark a module: + +* Write :option:`/*verilator&32;hier_block*/` metacomment in HDL code. + +* Add a :option:`hier_block` line in a the :ref:`Configuration Files`. + +Then pass the :vlopt:`--hierarchical` option to Verilator + +Compilation is the same as when not using hierarchical mode. + +.. code-block:: bash + + make -C obj_dir -f Vtop_module_name.mk + + +Limitations +----------- + +Hierarchy blocks have some limitations including: + +* The hierarchy block cannot be accessed using dot (.) from upper module(s) + or other hierarchy blocks. + +* Signals in the block cannot be traced. + +* Modport cannot be used at the hierarchical block boundary. + +* The simulation speed is likely to not be as fast as flat Verilation, in + which all modules are globally scheduled. + +* Generated clocks may not work correctly if they are generated in the + hierarchical model and pass up into another hierarchical model or the top + module. + +But, the following usage is supported: + +* Nested hierarchy blocks. A hierarchy block may instantiate other + hierarchy blocks. + +* Parameterized hierarchy block. Parameters of a hierarchy block can be + overridden using :code:`#(.param_name(value))` construct. + + +.. _Overlapping Verilation and Compilation: + +Overlapping Verilation and Compilation +-------------------------------------- + +Verilator needs to run 2 + *N* times in hierarchical Verilation, where *N* +is the number of hierarchy blocks. One of the two is for the top module +which refers wrappers of all other hierarchy blocks. The second one of the +two is the initial run that searches modules marked with +:option:`/*verilator&32;hier_block*/` metacomment and creates a plan and +write in :file:`{prefix}_hier.mk`. This initial run internally invokes +other *N* + 1 runs, so you don't have to care about these *N* + 1 times of +run. The additional *N* is the Verilator run for each hierarchical block. + +If ::vlopt:`-j {jobs} <-j>` option is specified, Verilation for hierarchy +blocks runs in parallel. + +If :vlopt:`--build` option is specified, C++ compilation also runs as soon +as a hierarchy block is Verilated. C++ compilation and Verilation for other +hierarchy blocks run simultaneously. + + +Cross Compilation +================= + +Verilator supports cross-compiling Verilated code. This is generally used +to run Verilator on a Linux system and produce C++ code that is then compiled +on Windows. + +Cross compilation involves up to three different OSes. The build system is +where you configured and compiled Verilator, the host system where you run +Verilator, and the target system where you compile the Verilated code and +run the simulation. + +Currently, Verilator requires the build and host system type to be the +same, though the target system type may be different. To support this, +:command:`./configure` and make Verilator on the build system. Then, run +Verilator on the host system. Finally, the output of Verilator may be +compiled on the different target system. + +To support this, none of the files that Verilator produces will reference +any configure generated build-system specific files, such as +:file:`config.h` (which is renamed in Verilator to :file:`config_build.h` +to reduce confusion.) The disadvantage of this approach is that +:file:`include/verilatedos.h` must self-detect the requirements of the +target system, rather than using configure. + +The target system may also require edits to the Makefiles, the simple +Makefiles produced by Verilator presume the target system is the same type +as the build system. + + +.. _Multithreading: + +Multithreading +============== + +Verilator supports multithreaded simulation models. + +With :vlopt:`--no-threads`, the default, the model is not thread safe, and +any use of more than one thread calling into one or even different +Verilated models may result in unpredictable behavior. This gives the +highest single thread performance. + +With :vlopt:`--threads 1 <--threads>`, the generated model is single +threaded, however the support libraries are multithread safe. This allows +different instantiations of model(s) to potentially each be run under a +different thread. All threading is the responsibility of the user's C++ +testbench. + +With :vlopt:`--threads {N} <--threads>`, where N is at least 2, the +generated model will be designed to run in parallel on N threads. The +thread calling eval() provides one of those threads, and the generated +model will create and manage the other N-1 threads. It's the client's +responsibility not to oversubscribe the available CPU cores. Under CPU +oversubscription, the Verilated model should not livelock nor deadlock, +however, you can expect performance to be far worse than it would be with +proper ratio of threads and CPU cores. + +The remainder of this section describe behavior with :vlopt:`--threads 1 +<--threads>` or :vlopt:`--threads {N} <--threads>` (not +:vlopt:`--no-threads`). + +:code:`VL_THREADED` is defined in the C++ code when compiling a threaded +Verilated module, causing the Verilated support classes become threadsafe. + +The thread used for constructing a model must be the same thread that calls +:code:`eval()` into the model, this is called the "eval thread". The thread +used to perform certain global operations such as saving and tracing must +be done by a "main thread". In most cases the eval thread and main thread +are the same thread (i.e. the user's top C++ testbench runs on a single +thread), but this is not required. + +The :vlopt:`--trace-threads` options can be used to produce trace dumps +using multiple threads. If :vlopt:`--trace-threads` is set without +:vlopt:`--threads`, then :vlopt:`--trace-threads` will imply +:vlopt:`--threads 1 <--threads>`, i.e.: the support libraries will be +thread safe. + +With :vlopt:`--trace-threads 0 <--trace-threads>`, trace dumps are produced +on the main thread. This again gives the highest single thread performance. + +With :vlopt:`--trace-threads {N} <--trace-threads>`, where N is at least 1, +N additional threads will be created and managed by the trace files (e.g.: +VerilatedVcdC or VerilatedFstC), to generate the trace dump. The main +thread will be released to proceed with execution as soon as possible, +though some blocking of the main thread is still necessary while capturing +the trace. Different trace formats can utilize a various number of +threads. See the :vlopt:`--trace-threads` option. + +When running a multithreaded model, the default Linux task scheduler often +works against the model, by assuming threads are short lived, and thus +often schedules threads using multiple hyperthreads within the same +physical core. For best performance use the :command:`numactl` program to +(when the threading count fits) select unique physical cores on the same +socket. The same applies for :vlopt:`--trace-threads` as well. + +As an example, if a model was Verilated with :vlopt:`--threads 4 +<--threads>`, we consult: + +.. code-block:: bash + + egrep 'processor|physical id|core id' /proc/cpuinfo + +To select cores 0, 1, 2, and 3 that are all located on the same socket (0) +but different physical cores. (Also useful is :command:`numactl +--hardware`, or :command:`lscpu` but those doesn't show Hyperthreading +cores.) Then we execute: + +.. code-block:: bash + + numactl -m 0 -C 0,1,2,3 -- verilated_executable_name + +This will limit memory to socket 0, and threads to cores 0, 1, 2, 3, +(presumably on socket 0) optimizing performance. Of course this must be +adjusted if you want another simulator using e.g. socket 1, or if you +Verilated with a different number of threads. To see what CPUs are +actually used, use :vlopt:`--prof-threads`. + + +Multithreaded Verilog and Library Support +----------------------------------------- + +$display/$stop/$finish are delayed until the end of an eval() call in order +to maintain ordering between threads. This may result in additional tasks +completing after the $stop or $finish. + +If using :vlopt:`--coverage`, the coverage routines are fully thread safe. + +If using the DPI, Verilator assumes pure DPI imports are thread safe, +balancing performance versus safety. See :vlopt:`--threads-dpi`. + +If using :vlopt:`--savable`, the save/restore classes are not multithreaded +and must be called only by the eval thread. + +If using :vlopt:`--sc`, the SystemC kernel is not thread safe, therefore +the eval thread and main thread must be the same. + +If using :vlopt:`--trace`, the tracing classes must be constructed and +called from the main thread. + +If using :vlopt:`--vpi`, since SystemVerilog VPI was not architected by +IEEE to be multithreaded, Verilator requires all VPI calls are only made +from the main thread. + + +.. _GNU Make: + +GNU Make +======== + +Verilator defaults to creating GNU Make makefiles for the model. Verilator +will call make automatically when the :vlopt:'--build' option is used. + +If calling Verilator from a makefile, the :vlopt:'-MMD' option will create +a dependency file which will allow Make to only run Verilator if input +Verilog files change. + +.. _CMake: + +CMake +===== + +Verilator can be run using CMake, which takes care of both running +Verilator and compiling the output. There is a CMake example in the +examples/ directory. The following is a minimal CMakeLists.txt that would +build the code listed in :ref:`Example C++ Execution` + +.. code-block:: CMake + + project(cmake_example) + find_package(verilator HINTS $ENV{VERILATOR_ROOT}) + add_executable(Vour sim_main.cpp) + verilate(Vour SOURCES our.v) + +:code:`find_package` will automatically find an installed copy of +Verilator, or use a local build if VERILATOR_ROOT is set. + +It is recommended to use CMake >= 3.12 and the Ninja generator, though +other combinations should work. To build with CMake, change to the folder +containing CMakeLists.txt and run: + +.. code-block:: bash + + mkdir build + cd build + cmake -GNinja .. + ninja + +Or to build with your system default generator: + +.. code-block:: bash + + mkdir build + cd build + cmake .. + cmake --build . + +If you're building the example you should have an executable to run: + +.. code-block:: bash + + ./Vour + +The package sets the CMake variables verilator_FOUND, VERILATOR_ROOT and +VERILATOR_BIN to the appropriate values, and also creates a verilate() +function. verilate() will automatically create custom commands to run +Verilator and add the generated C++ sources to the target specified. + +Verilate in CMake +----------------- + +.. code-block:: CMake + + verilate(target SOURCES source ... [TOP_MODULE top] [PREFIX name] + [TRACE] [TRACE_FST] [SYSTEMC] [COVERAGE] + [INCLUDE_DIRS dir ...] [OPT_SLOW ...] [OPT_FAST ...] + [OPT_GLOBAL ..] [DIRECTORY dir] [VERILATOR_ARGS ...]) + +Lowercase and ... should be replaced with arguments, the uppercase parts +delimit the arguments and can be passed in any order, or left out entirely +if optional. + +verilate(target ...) can be called multiple times to add other Verilog +modules to an executable or library target. + +When generating Verilated SystemC sources, you should also include the +SystemC include directories and link to the SystemC libraries. + +.. describe:: target + + Name of a target created by add_executable or add_library. + +.. describe:: COVERAGE + + Optional. Enables coverage if present, equivalent to "VERILATOR_ARGS + --coverage" + +.. describe:: DIRECTORY + + Optional. Set the verilator output directory. It is preferable to use + the default, which will avoid collisions with other files. + +.. describe:: INCLUDE_DIRS + + Optional. Sets directories that Verilator searches (same as -y). + +.. describe:: OPT_SLOW + + Optional. Set compiler options for the slow path. You may want to reduce + the optimization level to improve compile times with large designs. + +.. describe:: OPT_FAST + + Optional. Set compiler options for the fast path. + +.. describe:: OPT_GLOBAL + + Optional. Set compiler options for the common runtime library used by + Verilated models. + +.. describe:: PREFIX + + Optional. Sets the Verilator output prefix. Defaults to the name of the + first source file with a "V" prepended. Must be unique in each call to + verilate(), so this is necessary if you build a module multiple times + with different parameters. Must be a valid C++ identifier, i.e. contains + no white space and only characters A-Z, a-z, 0-9 or _. + +.. describe:: SOURCES + + List of Verilog files to Verilate. Must have at least one file. + +.. describe:: SYSTEMC + + Optional. Enables SystemC mode, defaults to C++ if not specified. + + When using Accellera's SystemC with CMake support, a CMake target is + available that simplifies the SystemC steps. This will only work if the + SystemC installation can be found by CMake. This can be configured by + setting the CMAKE_PREFIX_PATH variable during CMake configuration. + + Don't forget to set the same C++ standard for the Verilated sources as + the SystemC library. This can be specified using the SYSTEMC_CXX_FLAGS + environment variable. + +.. describe:: TOP_MODULE + + Optional. Sets the name of the top module. Defaults to the name of the + first file in the SOURCES array. + +.. describe:: TRACE + + Optional. Enables VCD tracing if present, equivalent to "VERILATOR_ARGS + --trace". + +.. describe:: TRACE_FST + + Optional. Enables FST tracing if present, equivalent to "VERILATOR_ARGS + --trace-fst". + +.. describe:: VERILATOR_ARGS + + Optional. Extra arguments to Verilator. Do not specify :vlopt:`--Mdir` + or :vlopt:`--prefix` here, use DIRECTORY or PREFIX. + + +SystemC Link in CMake +--------------------- + +Verilator's CMake support provides a convenience function to automatically +find and link to the SystemC library. It can be used as: + +.. code-block:: CMake + + verilator_link_systemc(target) + +where target is the name of your target. + +The search paths can be configured by setting some variables: + +.. describe:: SYSTEMC_INCLUDE + + Sets the direct path to the SystemC includes. + +.. describe:: SYSTEMC_LIBDIR + + Sets the direct path to the SystemC libraries. + +.. describe:: SYSTEMC_ROOT + + Sets the installation prefix of an installed SystemC library. + +.. describe:: SYSTEMC + + Sets the installation prefix of an installed SystemC library. (Same as + SYSTEMC_ROOT). diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst new file mode 100644 index 000000000..2e79f4e62 --- /dev/null +++ b/docs/guide/warnings.rst @@ -0,0 +1,1585 @@ +.. Copyright 2003-2021 by Wilson Snyder. +.. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +******************* +Errors and Warnings +******************* + + +Disabling Warnings +================== + +Warnings may be disabled in multiple ways: + +#. Disable the warning in the source code. When the warning is printed it + will include a warning code. Simply surround the offending line with a + :code:`/*verilator&32;lint_off*/` and :code:`/*verilator&32;lint_on*/` + metacomment pair: + + .. code-block:: sv + + // verilator lint_off UNSIGNED + if (`DEF_THAT_IS_EQ_ZERO <= 3) $stop; + // verilator lint_on UNSIGNED + +#. Disable the warning using :ref:`Configuration Files` with a + :option:`lint_off` command. This is useful when a script is suppressing + warnings and the Verilog source should not be changed. This method also + allows matching on the warning text. + + .. code-block:: sv + + lint_off -rule UNSIGNED -file "*/example.v" -line 1 + +#. Disable the warning globally invoking Verilator with the + :code:`-Wno-{warning-code}` option. This should be avoided, as it + removes all checking across the designs, and prevents other users from + compiling your code without knowing the magic set of disables needed to + successfully compile your design. + + +Error And Warning Format +======================== + +Warnings and errors printed by Verilator always match this regular +expression: + +.. code-block:: + + %(Error|Warning)(-[A-Z0-9_]+)?: ((\S+):(\d+):((\d+):)? )?.* + + +Errors and warning start with a percent sign (historical heritage from +Digital Equipment Corporation). Some errors or warning have a code +attached, with meanings described below. Some errors also have a filename, +line number and optional column number (starting at column 1 to match GCC). + +Following the error message, Verilator will typically show the user's +source code corresponding to the error, prefixed by the line number and a " +| ". Following this is typically an arrow and ~ pointing at the error on +the source line directly above. + + +List Of Warnings +================ + +.. option:: Internal Error + + This error should never occur first, though may occur if earlier + warnings or error messages have corrupted the program. If there are no + other warnings or errors, submit a bug report. + + +.. option:: Unsupported: .... + + This error indicates that the code is using a Verilog language construct + that is not yet supported in Verilator. See the Limitations chapter. + + +.. option:: ALWCOMBORDER + + .. TODO better example + + Warns that an :code:`always_comb` block has a variable which is set + after it is used. This may cause simulation-synthesis mismatches, as + not all simulators allow this ordering. + + .. code-block:: sv + + always_comb begin + a = b; + b = 1; + end + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: ASSIGNDLY + + .. TODO better example + + Warns that the code has an assignment statement with a delayed time in + front of it, for example: + + .. code-block:: sv + + a <= #100 b; + assign #100 a = b; + + Ignoring this warning may make Verilator simulations differ from other + simulators, however at one point this was a common style so disabled by + default as a code style warning. + + +.. option:: ASSIGNIN + + .. TODO better example + + Error that an assignment is being made to an input signal. This is + almost certainly a mistake, though technically legal. + + .. code-block:: sv + + input a; + assign a = 1'b1; + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: BLKANDNBLK + + .. TODO better example + + BLKANDNBLK is an error that a variable comes from a mix of blocking and + non-blocking assignments. + + This is not illegal in SystemVerilog, but a violation of good coding + practice. Verilator reports this as an error, because ignoring this + warning may make Verilator simulations differ from other simulators. + + It is generally safe to disable this error (with a :code:`// verilator + lint_off BLKANDNBLK` metacomment or the :code:`-Wno-BLKANDNBLK` option) + when one of the assignments is inside a public task, or when the + blocking and non-blocking assignments have non-overlapping bits and + structure members. + + Generally, this is caused by a register driven by both combo logic and a + flop: + + .. code-block:: sv + + logic [1:0] foo; + always @(posedge clk) foo[0] <= ... + always_comb foo[1] = ... + + Simply use a different register for the flop: + + .. code-block:: sv + + logic [1:0] foo; + always @(posedge clk) foo_flopped[0] <= ... + always_comb foo[0] = foo_flopped[0]; + always_comb foo[1] = ... + + Or, this may also avoid the error: + + .. code-block:: sv + + logic [1:0] foo /*verilator split_var*/; + + +.. option:: BLKLOOPINIT + + .. TODO better example + + This indicates that the initialization of an array needs to use + non-delayed assignments. This is done in the interest of speed; if + delayed assignments were used, the simulator would have to copy large + arrays every cycle. (In smaller loops, loop unrolling allows the + delayed assignment to work, though it's a bit slower than a non-delayed + assignment.) Here's an example + + .. code-block:: sv + + always @(posedge clk) + if (~reset_l) + for (i=0; i<`ARRAY_SIZE; i++) + array[i] = 0; // Non-delayed for verilator + + + This message is only seen on large or complicated loops because + Verilator generally unrolls small loops. You may want to try increasing + :vlopt:`--unroll-count` (and occasionally :vlopt:`--unroll-stmts`) which + will raise the small loop bar to avoid this error. + + +.. option:: BLKSEQ + + .. TODO better example + + This indicates that a blocking assignment (=) is used in a sequential + block. Generally non-blocking/delayed assignments (<=) are used in + sequential blocks, to avoid the possibility of simulator races. It can + be reasonable to do this if the generated signal is used ONLY later in + the same block, however this style is generally discouraged as it is + error prone. + + .. code-block:: sv + + always @(posedge clk) foo = ...; //<--- Warning + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Other tools with similar warnings: Verible's always-ff-non-blocking, + "Use only non-blocking assignments inside 'always_ff' sequential + blocks." + + +.. option:: BSSPACE + + .. TODO better example + + Warns that a backslash is followed by a space then a newline. Likely the + intent was to have a backslash directly followed by a newline (e.g. when + making a "\`define") and there's accidentally white space at the end of + the line. If the space is not accidental, suggest removing the + backslash in the code as it serves no function. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASEINCOMPLETE + + .. TODO better example + + Warns that inside a case statement there is a stimulus pattern for which + there is no case item specified. This is bad style, if a case is + impossible, it's better to have a :code:`default: $stop;` or just + :code:`default: ;` so that any design assumption violations will be + discovered in simulation. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASEOVERLAP + + .. TODO better example + + Warns that inside a case statement has case values which are detected to + be overlapping. This is bad style, as moving the order of case values + will cause different behavior. Generally the values can be respecified + to not overlap. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASEWITHX + + .. TODO better example + + Warns that a case statement contains a constant with a ``x`` . + Verilator is two-state so interpret such items as always false. Note a + common error is to use a ``X`` in a case or casez statement item; often + what the user instead intended is to use a casez with ``?`` . + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASEX + + .. TODO better example + + Warns that it is simply better style to use casez, and "?" in place of + "x"'s. See + `http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf + `_ + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: CASTCONST + + .. TODO better example + + Warns that a dynamic cast ($cast) is unnecessary as the $cast will + always succeed or fail. If it will always fail, the $cast is + useless. If it will always succeed a static cast may be preferred. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. On other simulators, not fixing CASTCONST may + result in decreased performance. + + +.. option:: CDCRSTLOGIC + + With :vlopt:`--cdc` only, warns that asynchronous flop reset terms come + from other than primary inputs or flopped outputs, creating the + potential for reset glitches. + + +.. option:: CLKDATA + + .. TODO better example + + Warns that clock signal is mixed used with/as data signal. The checking + for this warning is enabled only if user has explicitly marked some + signal as clocker using command line option or in-source meta comment + (see :vlopt:`--clk`). + + The warning can be disabled without affecting the simulation result. But + it is recommended to check the warning as this may degrade the + performance of the Verilated model. + + +.. option:: CMPCONST + + .. TODO better example + + Warns that the code is comparing a value in a way that will always be + constant. For example :code:`X > 1` will always be true when X is a + single bit wide. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: COLONPLUS + + Warns that a :code:`:+` is seen. Likely the intent was to use :code:`+:` + to select a range of bits. If the intent was a range that is explicitly + positive, suggest adding a space, e.g. use :code:`: +`. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: COMBDLY + + .. TODO better example + + Warns that there is a delayed assignment inside of a combinatorial + block. Using delayed assignments in this way is considered bad form, + and may lead to the simulator not matching synthesis. If this message + is suppressed, Verilator, like synthesis, will convert this to a + non-delayed assignment, which may result in logic races or other + nasties. See + `http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf + `_ + + Ignoring this warning may make Verilator simulations differ from other + simulators. + + +.. option:: CONTASSREG + + .. TODO better example + + Error that a continuous assignment is setting a reg. According to IEEE + Verilog, but not SystemVerilog, a wire must be used as the target of + continuous assignments. + + This error is only reported when :vlopt:`--language 1364-1995 + <--language>`, :vlopt:`--language 1364-2001 <--language>`, or + :vlopt:`--language 1364-2005 <--language>` is used. + + Ignoring this error will only suppress the lint check, it will simulate + correctly. + + +.. option:: DECLFILENAME + + .. TODO better example + + Warns that a module or other declaration's name doesn't match the + filename with path and extension stripped that it is declared in. The + filename a modules/interfaces/programs is declared in should match the + name of the module etc. so that :vlopt:`-y` option directory searching + will work. This warning is printed for only the first mismatching + module in any given file, and :vlopt:`-v` library files are ignored. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: DEFPARAM + + Warns that the :code:`defparam` statement was deprecated in Verilog 2001 + and all designs should now be using the :code:`#(...)` format to specify + parameters. + + Defparams may be defined far from the instantiation that is affected by + the defparam, affecting readability. Defparams have been formally + deprecated since IEEE 1800-2005 25.2 and may not work in future language + versions. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 5 + + module parameterized + #(parameter int MY_PARAM = 0); + endmodule + module upper; + defparam p0.MY_PARAM = 1; //<--- Warning + parameterized p0(); + endmodule + + Results in: + + .. code-block:: + + %Warning-DEFPARAM: example.v:5:15: defparam is deprecated (IEEE 1800-2017 C.4.1) + : ... Suggest use instantiation with #(.MY_PARAM(...etc...)) + + To repair use :code:`#(.PARAMETER(...))` syntax. Repaired Example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 6 + + module parameterized + #(parameter int MY_PARAM = 0); + endmodule + module upper + parameterized + #(.MY_PARAM(1)) //<--- Repaired + p0(); + endmodule + + Other tools with similar warnings: Veriable's forbid_defparam_rule. + + +.. option:: DETECTARRAY + + .. TODO better example + + Error when Verilator tries to deal with a combinatorial loop that could + not be flattened, and which involves a datatype which Verilator cannot + handle, such as an unpacked struct or a large unpacked array. This + typically occurs when :vlopt:`-Wno-UNOPTFLAT ` has been used + to override an UNOPTFLAT warning (see below). + + The solution is to break the loop, as described for UNOPTFLAT. + + +.. option:: DIDNOTCONVERGE + + Error at simulation runtime when model did not properly settle. + + Verilator sometimes has to evaluate combinatorial logic multiple times, + usually around code where a UNOPTFLAT warning was issued, but disabled. + + Faulty example: + + .. code-block:: sv + + always_comb b = ~a; + always_comb a = b + + This code will toggle forever, and thus to prevent an infinite loop, the + executable will give the didn't converge error. + + To debug this, first review any UNOPTFLAT warnings that were ignored. + Though typically it is safe to ignore UNOPTFLAT (at a performance cost), + at the time of issuing a UNOPTFLAT Verilator did not know if the logic + would eventually converge and assumed it would. + + Next, run Verilator with :vlopt:`--prof-cfuncs -CFLAGS -DVL_DEBUG + <--prof-cfuncs>`. Rerun the test. Now just before the convergence + error you should see additional output similar to this: + + .. code-block:: + + CHANGE: filename.v:1: b + CHANGE: filename.v:2: a + + This means that signal b and signal a keep changing, inspect the code + that modifies these signals. Note if many signals are getting printed + then most likely all of them are oscillating. It may also be that + e.g. "a" may be oscillating, then "a" feeds signal "c" which then is + also reported as oscillating. + + One way DIDNOTCONVERGE may occur is flops are built out of gate + primitives. error. Verilator does not support building flops or latches + out of gate primitives, and any such code must change to use behavioral + constructs (e.g. always_ff and always_latch). + + Finally, rare, more difficult cases can be debugged like a C++ program; + either enter :command:`gdb` and use its tracing facilities, or edit the + generated C++ code to add appropriate prints to see what is going on. + + +.. option:: ENDLABEL + + Warns that a label attached to a "end"-something statement does not + match the label attached to the block start. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + module mine; + endmodule : not_mine //<--- Warning + + Results in: + + .. code-block:: + + %Warning-ENDLABEL: example.v:2:13: End label 'not_mine' does not match begin label 'mine' + + To repair either fix the end label's name, or remove entirely. + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + module mine; + endmodule : mine //<--- Repaired + + Other tools with similar warnings: Verible's mismatched-labels, + "Begin/end block labels must match." or "Matching begin label is + missing." + + +.. option:: EOFNEWLINE + + Warns that a file does not end in a newline. POSIX defines that a line + must end in newline, as otherwise for example :command:`cat` with the + file as an argument may produce undesirable results. + + Repair by adding a newline to the end of the file. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Other tools with similar warnings: Verible's posix-eof, "File must end + with a newline." + + +.. option:: GENCLK + + Deprecated and no longer used as a warning. Used to indicate that the + specified signal was is generated inside the model, and also being used + as a clock. + + +.. option:: HIERBLOCK + + Warns that the top module is marked as a hierarchy block by the + :option:`/*verilator&32;hier_block*/` metacomment, which is not legal. + This setting on the top module will be ignored. + + +.. option:: IFDEPTH + + Warns that if/if else statements have exceeded the depth specified with + :vlopt:`--if-depth`, as they are likely to result in slow priority + encoders. Statements below unique and priority if statements are + ignored. Solutions include changing the code to a case statement, or a + SystemVerilog :code:`unique if` or :code:`priority if`. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: IGNOREDRETURN + + Warns that a non-void function is being called as a task, and hence the + return value is being ignored. This warning is required by IEEE. + + .. code-block:: sv + :linenos: + :emphasize-lines: 5 + + function int function_being_called_as_task; + return 1; + endfunction + + initial function_being_called_as_task(); //<--- Warning + + Results in: + + .. code-block:: + + %Warning-IGNOREDRETURN: example.v:5:9: Ignoring return value of non-void function (IEEE 1800-2017 13.4.1) + + The portable way to suppress this warning (in SystemVerilog) is to use a + void cast, for example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 5 + + function int function_being_called_as_task; + return 1; + endfunction + + initial void'(function_being_called_as_task()); //<--- Repaired + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: IMPERFECTSCH + + .. TODO better example + + Warns that the scheduling of the model is not absolutely perfect, and + some manual code edits may result in faster performance. This warning + defaults to off, is not part of -Wall, and must be turned on explicitly + before the top module statement is processed. + + +.. option:: IMPLICIT + + .. TODO better example + + Warns that a wire is being implicitly declared (it is a single bit wide + output from a sub-module.) While legal in Verilog, implicit + declarations only work for single bit wide signals (not buses), do not + allow using a signal before it is implicitly declared by an instance, + and can lead to dangling nets. A better option is the + :code:`/*AUTOWIRE*/` feature of Verilog-Mode for Emacs, available from + `https://www.veripool.org/verilog-mode + `_ + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + Other tools with similar warnings: Icarus Verilog's implicit, "warning: + implicit definition of wire '...'". + + +.. option:: IMPORTSTAR + + .. TODO better example + + Warns that an :code:`import {package}::*` statement is in $unit + scope. This causes the imported symbols to pollute the global namespace, + defeating much of the purpose of having a package. Generally + :code:`import ::*` should only be used inside a lower scope such as a + package or module. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: IMPURE + + .. TODO better example + + Warns that a task or function that has been marked with a + :option:`/*verilator&32;no_inline_task*/` metacomment, but it references + variables that are not local to the task. Verilator cannot schedule + these variables correctly. + + Ignoring this warning may make Verilator simulations differ from other + simulators. + + +.. option:: INCABSPATH + + .. TODO better example + + Warns that an "\`include" filename specifies an absolute path. This + means the code will not work on any other system with a different file + system layout. Instead of using absolute paths, relative paths + (preferably without any directory specified whatsoever) should be used, + and +incdir used on the command line to specify the top include source + directories. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: INFINITELOOP + + .. TODO better example + + Warns that a while or for statement has a condition that is always true. + and thus results in an infinite loop if the statement ever executes. + + This might be unintended behavior if the loop body contains statements + that in other simulators would make time pass, which Verilator is + ignoring due to e.g. ``STMTDLY`` warnings being disabled. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly (i.e. hang due to the infinite loop). + + +.. option:: INITIALDLY + + .. TODO better example + + Warns that the code has a delayed assignment inside of an initial or + final block. If this message is suppressed, Verilator will convert this + to a non-delayed assignment. See also :option:`COMBDLY`. + + Ignoring this warning may make Verilator simulations differ from other + simulators. + + +.. option:: INSECURE + + Warns that the combination of options selected may be defeating the + attempt to protect/obscure identifiers or hide information in the model. + Correct the options provided, or inspect the output code to see if the + information exposed is acceptable. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: LATCH + + .. TODO better example + + Warns that a signal is not assigned in all control paths of a + combinational always block, resulting in the inference of a latch. For + intentional latches, consider using the always_latch (SystemVerilog) + keyword instead. The warning may be disabled with a lint_off pragma + around the always block. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: LITENDIAN + + .. TODO better example + + Warns that a packed vector is declared with little endian bit numbering + (i.e. [0:7]). Big endian bit numbering is now the overwhelming + standard, and little numbering is now thus often due to simple oversight + instead of intent. + + Also warns that an instance is declared with little endian range + (i.e. [0:7] or [7]) and is connected to a N-wide signal. Based on IEEE + the bits will likely be backwards from what people may expect + (i.e. instance [0] will connect to signal bit [N-1] not bit [0]). + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: MODDUP + + .. TODO better example + + Warns that a module has multiple definitions. Generally this indicates + a coding error, or a mistake in a library file and it's good practice to + have one module per file (and only put each file once on the command + line) to avoid these issues. For some gate level netlists duplicates + are sometimes unavoidable, and MODDUP should be disabled. + + Ignoring this warning will cause the more recent module definition to be + discarded. + + +.. option:: MULTIDRIVEN + + .. TODO better example + + Warns that the specified signal comes from multiple always blocks. This + is often unsupported by synthesis tools, and is considered bad style. + It will also cause longer simulation runtimes due to reduced + optimizations. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: MULTITOP + + .. TODO better example + + Warns that there are multiple top level modules, that is modules not + instantiated by any other module, and both modules were put on the + command line (not in a library). Three likely cases: + + 1. A single module is intended to be the top. This warning then occurs + because some low level instance is being read in, but is not really + needed as part of the design. The best solution for this situation is + to ensure that only the top module is put on the command line without + any flags, and all remaining library files are read in as libraries with + :vlopt:`-v`, or are automatically resolved by having filenames that + match the module names. + + 2. A single module is intended to be the top, the name of it is known, + and all other modules should be ignored if not part of the design. The + best solution is to use the :vlopt:`--top` option to specify the top module's + name. All other modules that are not part of the design will be for the + most part ignored (they must be clean in syntax and their contents will + be removed as part of the Verilog module elaboration process.) + + 3. Multiple modules are intended to be design tops, e.g. when linting a + library file. As multiple modules are desired, disable the MULTITOP + warning. All input/outputs will go uniquely to each module, with any + conflicting and identical signal names being made unique by adding a + prefix based on the top module name followed by __02E (a + Verilator-encoded ASCII "."). This renaming is done even if the two + modules' signals seem identical, e.g. multiple modules with a "clk" + input. + + +.. option:: NOLATCH + + .. TODO better example + + Warns that no latch was detected in an always_latch block. The warning + may be disabled with a lint_off pragma around the always block, but + recoding using a regular always may be more appropriate. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: NULLPORT + + Warns that a null port was detected in the module definition port + list. Null ports are empty placeholders, i.e. either one ore more commas + at the beginning or the end of a module port list, or two or more + consecutive commas in the middle of a module port list. A null port + cannot be accessed within the module, but when instantiating the module + by port order, it is treated like a regular port and any wire connected + to it is left unconnected. For example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + module a + (a_named_port, ); //<--- Warning + + This is considered a warning because null ports are rarely used, and is + mostly the result of a typing error such as a dangling comma at the end + of a port list. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + +.. option:: PINCONNECTEMPTY + + .. TODO better example + + Warns that an instance has a pin which is connected to + :code:`.pin_name()`, e.g. not another signal, but with an explicit + mention of the pin. It may be desirable to disable PINCONNECTEMPTY, as + this indicates intention to have a no-connect. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: PINMISSING + + .. TODO better example + + Warns that a module has a pin which is not mentioned in an instance. If + a pin is not missing it should still be specified on the instance + declaration with a empty connection, using :code:`(.pin_name())`. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + Other tools with similar warnings: Icarus Verilog's portbind, "warning: + Instantiating module ... with dangling impot port (...)". Slang's + unconnected-port, "port '...' has no connection". + + +.. option:: PINNOCONNECT + + .. TODO better example + + Warns that an instance has a pin which is not connected to another + signal. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: PINNOTFOUND + + Warns that an instance port or Parameter was not found in the module + being instantiated. Note that Verilator raises these errors also on + instances that should be disabled by generate/if/endgenerate constructs: + + .. code-block:: sv + :linenos: + :emphasize-lines: 5-6 + + module a; + localparam A=1; + generate + if (A==0) begin + b b_inst1 (.x(1'b0)); //<--- error nonexistent port + b #(.PX(1'b0)) b_inst2 (); //<--- error nonexistent parameter + end + endgenerate + endmodule + + module b; + endmodule + + In the example above, b is instantiated with a port named x, but module + b has no such port. In the next line, b is instantiated again with a + nonexistent parameter PX. Technically, this code is incorrect because of + this, but other tools may ignore it because module b is not instantiated + due to the generate/if condition being false. + + This error may be disabled with a lint_off PINNOTFOUND metacomment. + + +.. option:: PKGNODECL + + .. TODO better example + + Error that a package/class appears to have been referenced that has not + yet been declared. According to IEEE 1800-2017 26.3 all packages must + be declared before being used. + + +.. option:: PROCASSWIRE + + .. TODO better example + + Error that a procedural assignment is setting a wire. According to IEEE, + a var/reg must be used as the target of procedural assignments. + + +.. option:: RANDC + + Warns that the :code:`randc` keyword is currently unsupported, and that + it is being converted to :code:`rand`. + + +.. option:: REALCVT + + Warns that a real number is being implicitly rounded to an integer, with + possible loss of precision. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + int i; + i = 2.3; //<--- Warning + + Results in: + + .. code-block:: + + %Warning-REALCVT: example.v:2:5: Implicit conversion of real to integer + + If the code is correct, the portable way to suppress the warning is to + add a cast. This will express the intent and should avoid future + warnings on any linting tool. + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + int i; + i = int'(2.3); //<--- Repaired + + +.. option:: REDEFMACRO + + Warns that the code has redefined the same macro with a different value, + for example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 3 + + `define DUP def1 + //... + `define DUP def2 //<--- Warning + + Results in: + + .. code-block:: + + %Warning-REDEFMACRO: example.v:3:20: Redefining existing define: 'DUP', with different value: 'def1' + example.v:1:20: ... Location of previous definition, with value: 'def2' + + The best solution is to use a different name for the second macro. If + this is not possible, add a undef to indicate the code is overriding the + value. This will express the intent and should avoid future warnings on + any linting tool: + + .. code-block:: sv + + `define DUP def1 + //... + `undef DUP //<--- Repaired + `define DUP def2 + + Other tools with similar warnings: Icarus Verilog's macro-redefinition, + "warning: redefinition of macro ... from value '...' to '...'". Yosys's + "Duplicate macro arguments with name". + + +.. option:: SELRANGE + + Warns that a selection index will go out of bounds. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 2 + + wire vec[6:0]; + initial out = vec[7]; //<--- Warning (there is no [7]) + + Verilator will assume zero for this value, instead of X. Note that in + some cases this warning may be false, when a condition upstream or + downstream of the access means the access out of bounds will never + execute or be used. + + Repaired example: + + .. code-block:: sv + :linenos: + + wire vec[6:0]; + initial begin + index = 7; + ... + if (index < 7) out = vec[index]; // Never will use vec[7] + + Other tools with similar warnings: Icarus Verilog's select-range, + "warning: ... [...] is selecting before vector" or "is selecting before + vector". + + +.. option:: SHORTREAL + + Warns that Verilator does not support :code:`shortreal` and they will be + automatically promoted to :code:`real`. + + .. code-block:: sv + :linenos: + :emphasize-lines: 1 + + shortreal sig; //<--- Warning + + The recommendation is to replace any :code:`shortreal` in the code with + :code:`real`, as :code:`shortreal` is not widely supported across + industry tools. + + .. code-block:: sv + :linenos: + :emphasize-lines: 1 + + real sig; //<--- Repaired + + Ignoring this warning may make Verilator simulations differ from other + simulators, if the increased precision of real affects your model or DPI + calls. + + +.. option:: SPLITVAR + + Warns that a variable with a :option:`/*verilator&32;split_var*/` + metacomment was not split. Some possible reasons for this are: + + * The datatype of the variable is not supported for splitting. (e.g. is + a real). + + * The access pattern of the variable can not be determined + statically. (e.g. is accessed as a memory). + + * The index of the array exceeds the array size. + + * The variable is accessed from outside using dotted reference. + (e.g. top.instance0.variable0 = 1). + + * The variable is not declared in a module, but in a package or an + interface. + + * The variable is a parameter, localparam, genvar, or queue. + + * The variable is tristate or bidirectional. (e.g. inout or ref). + + +.. option:: STMTDLY + + Warns that the code has a statement with a delayed time in front of it. + + Ignoring this warning may make Verilator simulations differ from other + simulators. + + Faulty example: + + .. code-block:: sv + + #100 $finish; //<--- Warning + + +.. option:: SYMRSVDWORD + + Warning that a symbol matches a C++ reserved word and using this as a + symbol name would result in odd C++ compiler errors. You may disable + this warning, but the symbol will be renamed by Verilator to avoid the + conflict. + + +.. option:: SYNCASYNCNET + + .. TODO better example + + Warns that the specified net is used in at least two different always + statements with posedge/negedges (i.e. a flop). One usage has the + signal in the sensitivity list and body, probably as an async reset, and + the other usage has the signal only in the body, probably as a sync + reset. Mixing sync and async resets is usually a mistake. The warning + may be disabled with a lint_off pragma around the net, or either flopped + block. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + +.. option:: TASKNSVAR + + Error when a call to a task or function has an inout from that task tied + to a non-simple signal. Instead connect the task output to a temporary + signal of the appropriate width, and use that signal to set the + appropriate expression as the next statement. For example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 4 + + task foo(inout sig); ... endtask + // ... + always @* begin + foo(bus_we_select_from[2]); // Will get TASKNSVAR error + end + + Change this to: + + .. code-block:: sv + + task foo(inout sig); ... endtask + // ... + reg foo_temp_out; + always @* begin + foo(foo_temp_out); + bus_we_select_from[2] = foo_temp_out; + end + + Verilator doesn't do this conversion for you, as some more complicated + cases would result in simulator mismatches. + + +.. option:: TICKCOUNT + + Warns that the number of ticks to delay a $past variable is greater + than 10. At present Verilator effectively creates a flop for each + delayed signals, and as such any large counts may lead to large design + size increases. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: TIMESCALEMOD + + Warns that "\`timescale" is used in some but not all modules. + + This may be disabled similar to other warnings. Ignoring this warning + may result in a module having an unexpected timescale. + + IEEE recommends this be an error, for that behavior use + :vlopt:`-Werror-TIMESCALEMOD <-Werror-\>`. + + Faulty example: + + .. code-block:: sv + :linenos: + :emphasize-lines: 5 + + module mod1; + sub sub(); + endmodule + `timescale 1ns/1ns + module sub; //<--- Warning + endmodule + + Results in: + + .. code-block:: + + %Warning-TIMESCALEMOD: example.v:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.3) + + Recommend using :vlopt:`--timescale` argument, or in front of all + modules use: + + .. code-block:: sv + + `include "timescale.vh" + + Then in that file set the timescale. + + Other tools with similar warnings: Icarus Verilog's timescale, "warning: + Some design elements have no explicit time unit and/or time + precision. This may cause confusing timing results." Slang's: + "[WRN:PA0205] No timescale set for "..."". + + +.. option:: UNDRIVEN + + .. TODO better example + + Warns that the specified signal has no source. Verilator is fairly + liberal in the usage calculations; making a signal public, or setting + only a single array element marks the entire signal as driven. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Other tools with similar warnings: Odin's "[NETLIST] This output is + undriven (...) and will be removed". + + +.. option:: UNOPT + + .. TODO better example + + Warns that due to some construct, optimization of the specified signal + or block is disabled. The construct should be cleaned up to improve + simulation performance. + + A less obvious case of this is when a module instantiates two + submodules. Inside submodule A, signal I is input and signal O is + output. Likewise in submodule B, signal O is an input and I is an + output. A loop exists and a UNOPT warning will result if AI & AO both + come from and go to combinatorial blocks in both submodules, even if + they are unrelated always blocks. This affects performance because + Verilator would have to evaluate each submodule multiple times to + stabilize the signals crossing between the modules. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: UNOPTFLAT + + .. TODO better example + + Warns that due to some construct, optimization of the specified signal + is disabled. The signal reported includes a complete scope to the + signal; it may be only one particular usage of a multiply instantiated + block. The construct should be cleaned up to improve simulation + performance; two times better performance may be possible by fixing + these warnings. + + Unlike the ``UNOPT`` warning, this occurs after flattening the netlist, + and indicates a more basic problem, as the less obvious case described + under ``UNOPT`` does not apply. + + Often UNOPTFLAT is caused by logic that isn't truly circular as viewed by + synthesis which analyzes interconnection per-bit, but is circular to + simulation which analyzes per-bus: + + .. code-block:: sv + + wire [2:0] x = {x[1:0], shift_in}; + + This statement needs to be evaluated multiple times, as a change in + :code:`shift_in` requires "x" to be computed 3 times before it becomes + stable. This is because a change in "x" requires "x" itself to change + value, which causes the warning. + + For significantly better performance, split this into 2 separate signals: + + .. code-block:: sv + + wire [2:0] xout = {x[1:0], shift_in}; + + and change all receiving logic to instead receive "xout". + Alternatively, change it to: + + .. code-block:: sv + + wire [2:0] x = {xin[1:0], shift_in}; + + and change all driving logic to instead drive "xin". + + With this change this assignment needs to be evaluated only once. These + sort of changes may also speed up your traditional event driven + simulator, as it will result in fewer events per cycle. + + The most complicated UNOPTFLAT path we've seen was due to low bits of a + bus being generated from an always statement that consumed high bits of + the same bus processed by another series of always blocks. The fix is + the same; split it into two separate signals generated from each block. + + Occasionally UNOPTFLAT may be indicated when there is a true + circulation. e.g. if trying to implement a flop or latch using + individual gate primitives. If UNOPTFLAT is suppressed the code may get + a DIDNOTCONVERGE error. Verilator does not support building flops or + latches out of gate primitives, and any such code must change to use + behavioral constructs (e.g. always_ff and always_latch). + + Another way to resolve this warning is to add a + :option:`/*verilator&32;split_var*/` metacomment described above. This + will cause the variable to be split internally, potentially resolving + the conflict. If you run with `--report-unoptflat` Verilator will + suggest possible candidates for :option:`/*verilator&32;split_var*/`. + + The UNOPTFLAT warning may also be due to clock enables, identified from + the reported path going through a clock gating instance. To fix these, + use the clock_enable meta comment described above. + + The UNOPTFLAT warning may also occur where outputs from a block of logic + are independent, but occur in the same always block. To fix this, use + the :option:`/*verilator&32;isolate_assignments*/` metacomment described + above. + + To assist in resolving UNOPTFLAT, the option :vlopt:`--report-unoptflat` + can be used, which will provide suggestions for variables that can be + split up, and a graph of all the nodes connected in the loop. See the + Arguments section for more details. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: UNOPTTHREADS + + .. TODO better example + + Warns that the thread scheduler was unable to partition the design to + fill the requested number of threads. + + One workaround is to request fewer threads with :vlopt:`--threads`. + + Another possible workaround is to allow more MTasks in the simulation + runtime, by increasing the value of :vlopt:`--threads-max-mtasks`. More + MTasks will result in more communication and synchronization overhead at + simulation runtime; the scheduler attempts to minimize the number of + MTasks for this reason. + + Ignoring this warning will only slow simulations, it will simulate + correctly. + + +.. option:: UNPACKED + + Warns that unpacked structs and unions are not supported. + + Ignoring this warning will make Verilator treat the structure as packed, + which may make Verilator simulations differ from other simulators. This + downgrading may also result what would normally be a legal unpacked + struct/array inside an unpacked struct/array becoming an illegal + unpacked struct/array inside a packed struct/array. + + +.. option:: UNSIGNED + + .. TODO better example + + Warns that the code is comparing a unsigned value in a way that implies + it is signed, for example "X < 0" will always be false when X is + unsigned. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + +.. option:: UNSUPPORTED + + Error that a construct might be legal according to IEEE but is not + currently supported by Verilator. + + This error may be ignored with :vlopt:`--bbox-unsup`, however this will + make the design simulate incorrectly; see the details under + :vlopt:`--bbox-unsup`. + + +.. option:: UNUSED + + .. TODO better example + + Warns that the specified signal or parameter is never used/consumed. + Verilator is fairly liberal in the usage calculations; making a signal + public, a signal matching the :vlopt:`--unused-regexp` option (default + "\*unused\*" or accessing only a single array element marks the entire + signal as used. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + A recommended style for unused nets is to put at the bottom of a file + code similar to the following: + + .. code-block:: sv + + wire _unused_ok = &{1'b0, + sig_not_used_a, + sig_not_used_yet_b, // To be fixed + 1'b0}; + + The reduction AND and constant zeros mean the net will always be zero, + so won't use simulation runtime. The redundant leading and trailing + zeros avoid syntax errors if there are no signals between them. The + magic name "unused" (controlled by :vlopt:`--unused-regexp` option) is + recognized by Verilator and suppresses warnings; if using other lint + tools, either teach it to the tool to ignore signals with "unused" in + the name, or put the appropriate lint_off around the wire. Having + unused signals in one place makes it easy to find what is unused, and + reduces the number of lint_off pragmas, reducing bugs. + + +.. option:: USERERROR + + A SystemVerilog elaboration-time assertion error was executed. + IEEE 1800-2017 20.11 requires this error. + + Faulty example: + + .. include:: ../../docs/gen/ex_USERERROR_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_USERERROR_msg.rst + + To resolve, examine the code and rectify the cause of the error. + + +.. option:: USERFATAL + + A SystemVerilog elaboration-time assertion fatal was executed. + IEEE 1800-2017 20.11 requires this error. + + Faulty example: + + .. include:: ../../docs/gen/ex_USERFATAL_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_USERFATAL_msg.rst + + To resolve, examine the code and rectify the cause of the fatal. + + +.. option:: USERINFO + + A SystemVerilog elaboration-time assertion print was executed. This is + not an error nor warning. IEEE 1800-2017 20.11 requires this behavior. + + Example: + + .. include:: ../../docs/gen/ex_USERINFO_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_USERINFO_msg.rst + + +.. option:: USERWARN + + A SystemVerilog elaboration-time assertion warning was executed. + IEEE 1800-2017 20.11 requires this warning. + + Faulty example: + + .. include:: ../../docs/gen/ex_USERWARN_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_USERWARN_msg.rst + + To resolve, examine the code and rectify the cause of the error. + + +.. option:: VARHIDDEN + + Warns that a task, function, or begin/end block is declaring a variable + by the same name as a variable in the upper level module or begin/end + block (thus hiding the upper variable from being able to be used.) + Rename the variable to avoid confusion when reading the code. + + Disabled by default as this is a code style warning; it will simulate + correctly. + + Faulty example: + + .. include:: ../../docs/gen/ex_VARHIDDEN_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_VARHIDDEN_msg.rst + + To resolve, rename the variable to a unique name. + + +.. option:: WIDTH + + Warns that based on width rules of Verilog: + + * Two operands have different widths, e.g. adding a 2-bit and 5-bit + number. + + * A part select has a different size then needed to index into the + packed or unpacked array (etc). + + Verilator for attempts to track the minimum width of unsized constants + and will suppress the warning when the minimum width is appropriate to + fit the required size. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + The recommendation is to fix these issues by: + + * Resizing the variable or constant. E.g. :code:`2'd2` instead of :code:`3'd2`. + + * Using :code:`'0` or :code:`'1`. + + * Using part select to narrow a variable. E.g. :code:`too_wide[1:0]`. + + * Using concatenate to widen a variable. E.g. :code:`{1'b1, too_narrow}`. + + * Using cast to resize a variable. E.g. :code:`23'(wrong_sized)`. + + For example this is a missized index: + + .. include:: ../../docs/gen/ex_WIDTH_1_faulty.rst + + Results in: + + .. include:: ../../docs/gen/ex_WIDTH_1_msg.rst + + One possible fix: + + .. include:: ../../docs/gen/ex_WIDTH_1_fixed.rst + + +.. option:: WIDTHCONCAT + + Warns that based on width rules of Verilog, a concatenate or replication + has an indeterminate width. In most cases this violates the Verilog + rule that widths inside concatenates and replicates must be sized, and + should be fixed in the code. + + Faulty example: + + .. code-block:: sv + + wire [63:0] concat = {1, 2}; + + An example where this is technically legal (though still bad form) is: + + .. code-block:: sv + + parameter PAR = 1; + wire [63:0] concat = {PAR, PAR}; + + The correct fix is to either size the 1 (:code:`32'h1`), or add the + width to the parameter definition (:code:`parameter [31:0]`), or add the + width to the parameter usage (:code:`{PAR[31:0], PAR[31:0]}`). diff --git a/docs/install.rst b/docs/install.rst deleted file mode 100644 index f6f7a2031..000000000 --- a/docs/install.rst +++ /dev/null @@ -1,397 +0,0 @@ -|Logo| - -====================== -Verilator Installation -====================== - -.. contents:: - :depth: 3 - -Introduction -============ - -This discusses how to install Verilator. For more general information -please see `verilator.org `__. - - -Quick-start -=========== - - -Install From a Package Manager ------------------------------- - -Using a distribution's package manager is the easiest way to get -started. (Note packages are unlikely to have the most recent version, so -Git, below, maybe a better alternative.) To install as a package: - -:: - - apt-get install verilator - -If this works, skip down to `Running Verilator <#_running_verilator>`__. - - -Docker ------- - -Verilator is available in pre-built Docker containers. See -https://github.com/verilator/verilator/blob/master/ci/docker/run/README.rst - - -Git ---- - -Installing Verilator with Git provides the most flexibility. For -additional options and details see the additional sections below. In -brief: - -:: - - # Prerequisites: - #sudo apt-get install git make autoconf g++ flex bison - #sudo apt-get install libfl2 # Ubuntu only (ignore if gives error) - #sudo apt-get install libfl-dev # Ubuntu only (ignore if gives error) - - git clone https://github.com/verilator/verilator # Only first time - ## Note the URL above is not a page you can see with a browser, it's for git only - - # Every time you need to build: - unsetenv VERILATOR_ROOT # For csh; ignore error if on bash - unset VERILATOR_ROOT # For bash - cd verilator - git pull # Make sure git repository is up-to-date - git tag # See what versions exist - #git checkout master # Use development branch (e.g. recent bug fixes) - #git checkout stable # Use most recent stable release - #git checkout v{version} # Switch to specified release version - - autoconf # Create ./configure script - ./configure - make - sudo make install - # Now see "man verilator" or online verilator.pdf's for the example tutorials - -If this works, skip down to `Running Verilator <#_running_verilator>`__. - - -Detailed Build Instructions -=========================== - -This section describes details of the build process, and assumes you are -building from Git or a tarball. For using a pre-built binary for your -Linux distribution, see instead `Install From a Package -Manager <#_install_from_a_package_manager>`__. - - -OS Requirements ---------------- - -Verilator is developed and has primary testing on Ubuntu, with additional -testing on FreeBSD and Apple OS-X. Versions have also built on Redhat -Linux, HPUX and Solaris. It should run with minor porting on any -GNU/Linux-ish platform. Verilator also works on Windows under Cygwin, and -Windows under MinGW (gcc -mno-cygwin). Verilated output (not Verilator -itself) compiles under all the options above, plus MSVC++. - - -Install Prerequisites ---------------------- - -To build or run Verilator you need these standard packages: - -:: - - sudo apt-get install perl python3 make - sudo apt-get install g++ # Alternatively, clang - sudo apt-get install libgz # Non-Ubuntu (ignore if gives error) - sudo apt-get install libfl2 libfl-dev zlibc zlib1g zlib1g-dev # Ubuntu only (ignore if gives error) - -To build or run the following are optional but should be installed for good -performance: - -:: - - sudo apt-get install ccache # If present at build, needed for run - sudo apt-get install libgoogle-perftools-dev numactl perl-doc - -To build Verilator you will need to install these packages; these do not -need to be present to run Verilator: - -:: - - sudo apt-get install git autoconf flex bison - -Those developing Verilator itself may also want these (see internals.rst): - -:: - - sudo apt-get install gdb asciidoctor graphviz cmake clang clang-format gprof lcov - cpan install Pod::Perldoc - cpan install Parallel::Forker - - -Install SystemC -~~~~~~~~~~~~~~~ - -If you will be using SystemC (vs straight C++ output), download `SystemC -`__. Follow their -installation instructions. You will need to set ``SYSTEMC_INCLUDE`` to -point to the include directory with ``systemc.h`` in it, and -``SYSTEMC_LIBDIR`` to points to the directory with ``libsystemc.a`` in -it. (Older installations may set ``SYSTEMC`` and ``SYSTEMC_ARCH`` instead.) - - -Install GTKWave -~~~~~~~~~~~~~~~ - -To make use of Verilator FST tracing you will want `GTKwave -`__ installed, however this is not -required at Verilator build time. - - -Obtain Sources --------------- - -You may use Git or a tarball for the sources. Git is the supported -option. (If using a historical build that uses a tarball, tarballs are -obtained from `Verilator Downloads -`__; we presume -you know how to use it, and is not described here.) - -Get the sources from the repository: (You need do this only once, ever.) - -:: - - git clone https://github.com/verilator/verilator # Only first time - ## Note the URL above is not a page you can see with a browser, it's for git only - -Enter the checkout and determine what version/branch to use: - -:: - - cd verilator - git pull # Make sure we're up-to-date - git tag # See what versions exist - #git checkout master # Use development branch (e.g. recent bug fix) - #git checkout stable # Use most recent release - #git checkout v{version} # Switch to specified release version - - -Auto Configure --------------- - -Create the configuration script: - -:: - - autoconf # Create ./configure script - - -Eventual Installation Options ------------------------------ - -Before configuring the build, you have to decide how you're going to -eventually install the kit. Verilator will be compiling the current value -of ``VERILATOR_ROOT``, ``SYSTEMC_INCLUDE``, and ``SYSTEMC_LIBDIR`` as -defaults into the executable, so they must be correct before configuring. - -These are the options: - - -1. Run-in-Place from VERILATOR_ROOT -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Our personal favorite is to always run Verilator in-place from its Git -directory. This allows the easiest experimentation and upgrading, and -allows many versions of Verilator to co-exist on a system. - -:: - - export VERILATOR_ROOT=`pwd` # if your shell is bash - setenv VERILATOR_ROOT `pwd` # if your shell is csh - ./configure - # Running will use files from $VERILATOR_ROOT, so no install needed - -Note after installing (below steps), a calling program or shell must set -the environment variable ``VERILATOR_ROOT`` to point to this Git directory, -then execute ``$VERILATOR_ROOT/bin/verilator``, which will find the path to -all needed files. - - -2. Install into a CAD Disk -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -You may eventually be installing onto a project/company-wide "CAD" tools -disk that may support multiple versions of every tool. Target the build to -a destination directory name that includes the Verilator version name: - -:: - - unset VERILATOR_ROOT # if your shell is bash - unsetenv VERILATOR_ROOT # if your shell is csh - # For the tarball, use the version number instead of git describe - ./configure --prefix /CAD_DISK/verilator/`git describe | sed "s/verilator_//"` - -Note after installing (below steps), if you use `modulecmd -`__, you'll want a module file like the -following: - -**modulecmd's verilator/version file.** - -:: - - set install_root /CAD_DISK/verilator/{version-number-used-above} - unsetenv VERILATOR_ROOT - prepend-path PATH $install_root/bin - prepend-path MANPATH $install_root/man - prepend-path PKG_CONFIG_PATH $install_root/share/pkgconfig - - -3. Install into a Specific Path -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -You may eventually install Verilator into a specific installation prefix, -as most GNU tools support: - -:: - - unset VERILATOR_ROOT # if your shell is bash - unsetenv VERILATOR_ROOT # if your shell is csh - ./configure --prefix /opt/verilator-VERSION - -Then after installing (below steps) you will need to add -``/opt/verilator-VERSION/bin`` to ``$PATH``. - - -4. Install System Globally -~~~~~~~~~~~~~~~~~~~~~~~~~~ - -The final option is to eventually install Verilator globally, using the -normal system paths: - -:: - - unset VERILATOR_ROOT # if your shell is bash - unsetenv VERILATOR_ROOT # if your shell is csh - ./configure - -Then after installing (below) the binary directories should already be -in your ``$PATH``. - - -Configure ---------- - -The command to configure the package was described in the previous step. -Developers should configure to have more complete developer tests. -Additional packages may be required for these tests. - -:: - - export VERILATOR_AUTHOR_SITE=1 # Put in your .bashrc - ./configure --enable-longtests ...above options... - - -Compile -------- - -Compile Verilator: - -:: - - make -j - - -Test ----- - -Check the compilation by running self-tests: - -:: - - make test - - -Install -------- - -If you used any but the `1. Run-in-Place from VERILATOR_ROOT -<#_1_run_in_place_from_verilator_root>`__ scheme, install to the -OS-standard place: - -:: - - make install - - -Running Verilator -================= - -To run Verilator, see the example sections in the `Verilator manual (HTML) -`__, or `Verilator manual (PDF) -`__. - -Also see the ``examples/`` directory that is part of the kit, and is -installed (in a OS-specific place, often in e.g. -``/usr/local/share/verilator/examples``). - -:: - - cd examples/make_hello_c - make - -Note if you did a ``make install`` above you should not have -``VERILATOR_ROOT`` set in your environment; it is built into the -executable. - - -Announcements -============= - -To get notified of new releases, go to `Verilator announcement repository -`__ and follow the -instructions there. - - -Directory Structure -=================== - -Some relevant files and directories in this package are as follows: - -:: - - Changes => Version history - README.rst => This document - bin/verilator => Compiler wrapper invoked to Verilate code - docs/ => Additional documentation - examples/make_hello_c => Example GNU-make simple Verilog->C++ conversion - examples/make_hello_sc => Example GNU-make simple Verilog->SystemC conversion - examples/make_tracing_c => Example GNU-make Verilog->C++ with tracing - examples/make_tracing_sc => Example GNU-make Verilog->SystemC with tracing - examples/make_protect_lib => Example using --protect-lib - examples/cmake_hello_c => Example building make_hello_c with CMake - examples/cmake_hello_sc => Example building make_hello_sc with CMake - examples/cmake_tracing_c => Example building make_tracing_c with CMake - examples/cmake_tracing_sc => Example building make_tracing_sc with CMake - examples/cmake_protect_lib => Example building make_protect_lib with CMake - include/ => Files that should be in your -I compiler path - include/verilated*.cpp => Global routines to link into your simulator - include/verilated*.h => Global headers - include/verilated.mk => Common Makefile - src/ => Translator source code - test_regress => Internal tests - -For files created after a design is Verilated, see the `Verilator manual -(HTML) `__, or `Verilator -manual (PDF) `__. - - -License -======= - -Copyright 2008-2021 by Wilson Snyder. Verilator is free software; you can -redistribute it and/or modify it under the terms of either the GNU Lesser -General Public License Version 3 or the Perl Artistic License Version 2.0. - -.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png diff --git a/docs/internals.rst b/docs/internals.rst index af5923188..f40cce27b 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -1,8 +1,8 @@ |Logo| -=================== +******************* Verilator Internals -=================== +******************* .. contents:: :depth: 3 @@ -81,7 +81,7 @@ Key Classes Used in the Verilator Flow ``AstNode`` -~~~~~~~~~~~ +^^^^^^^^^^^ The AST is represented at the top level by the class ``AstNode``. This abstract class has derived classes for the individual components (e.g. @@ -115,7 +115,7 @@ pointer to the ``AstNode`` currently being processed. ``AstNVisitor`` -~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^ The passes are implemented by AST visitor classes. These are implemented by subclasses of the abstract class, ``AstNVisitor``. Each pass creates an @@ -124,7 +124,7 @@ the pass. ``V3Graph`` -~~~~~~~~~~~ +^^^^^^^^^^^ A number of passes use graph algorithms, and the class ``V3Graph`` is provided to represent those graphs. Graphs are directed, and algorithms are @@ -134,7 +134,7 @@ documentation of this class. ``V3GraphVertex`` -~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^ ``V3GraphVertex`` is the base class for vertices in a graph. Vertices have an associated ``fanout``, ``color`` and ``rank``, which may be used in @@ -156,7 +156,7 @@ in the form: ``V3GraphEdge`` -~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^ ``V3GraphEdge`` is the base class for directed edges between pairs of vertices. Edges have an associated ``weight`` and may also be made @@ -171,7 +171,7 @@ used in dot output. Typically users provided derived classes from ``V3GraphAlg`` -~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^ This is the base class for graph algorithms. It implements a ``bool`` method, ``followEdge`` which algorithms can use to decide whether an edge @@ -204,7 +204,7 @@ synchronization cost is not prohibitive with so few nodes. Partitioning -~~~~~~~~~~~~ +^^^^^^^^^^^^ Our partitioner is similar to the one Vivek Sarkar described in his 1989 paper *Partitioning and Scheduling Parallel Programs for Multiprocessors*. @@ -213,7 +213,7 @@ Let's define some terms: Par Factor -~~~~~~~~~~ +^^^^^^^^^^ The available parallelism or "par-factor" of a DAG is the total cost to execute all nodes, divided by the cost to execute the longest critical path @@ -223,7 +223,7 @@ synchronization are zero. Macro Task -~~~~~~~~~~ +^^^^^^^^^^ When the partitioner coarsens the graph, it combines nodes together. Each fine-grained node represents an atomic "task"; combined nodes in the @@ -235,7 +235,7 @@ ends.) Edge Contraction -~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^ Verilator's partitioner, like Sarkar's, primarily relies on "edge contraction" to coarsen the graph. It starts with one macro-task per atomic @@ -243,7 +243,7 @@ task and iteratively combines pairs of edge-connected macro-tasks. Local Critical Path -~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^ Each node in the graph has a "local" critical path. That's the critical path from the start of the graph to the start of the node, plus the node's @@ -263,7 +263,8 @@ it's not guaranteed to produce the best partition (which Sarkar proves is NP-hard). -Estimating Logic Costs ~~~~~~~~~~~~~~~~~~~~~~ +Estimating Logic Costs +^^^^^^^^^^^^^^^^^^^^^^ To compute the cost of any given path through the graph, Verilator estimates an execution cost for each task. Each macro-task has an execution @@ -284,7 +285,7 @@ runtime costs estimates. This is an area to improve. Scheduling Macro-Tasks at Runtime -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ After coarsening the graph, we must schedule the macro-tasks for runtime. Sarkar describes two options: you can dynamically schedule tasks @@ -306,7 +307,7 @@ fragmentation. Locating Variables for Best Spatial Locality -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ After scheduling all code, we attempt to locate variables in memory such that variables accessed by a single macro-task are close together in @@ -339,11 +340,11 @@ locality in serial mode; that is a possible area for improvement.) Improving Multithreaded Performance Further (a TODO list) -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Wave Scheduling -^^^^^^^^^^^^^^^ +""""""""""""""" To allow the Verilated model to run in parallel with the testbench, it might be nice to support "wave" scheduling, in which work on a cycle begins @@ -355,7 +356,7 @@ however, it's probably the best bet for hiding testbench latency. Efficient Dynamic Scheduling -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""""""""""" To scale to more than a few threads, we may revisit a fully dynamic scheduler. For large (>16 core) systems it might make sense to dedicate an @@ -365,7 +366,7 @@ would not be prohibitive. Static Scheduling with Runtime Repack -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +""""""""""""""""""""""""""""""""""""" We could modify the static scheduling approach by gathering actual macro-task execution times at run time, and dynamically re-packing the @@ -377,7 +378,7 @@ or nonuniform competing memory traffic or whatever. Clock Domain Balancing -^^^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""""" Right now Verilator makes no attempt to balance clock domains across macro-tasks. For a multi-domain model, that could lead to bad gantt chart @@ -385,7 +386,7 @@ fragmentation. This could be improved if it's a real problem in practice. Other Forms of MTask Balancing -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""""""""""""" The largest source of runtime overhead is idle CPUs, which happens due to variance between our predicted runtime for each MTask and its actual @@ -406,7 +407,7 @@ option to scramble things. Performance Regression -^^^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""""" It would be nice if we had a regression of large designs, with some diversity of design styles, to test on both single- and multi-threaded @@ -415,7 +416,7 @@ evaluate the optimizations while minimizing the impact of parasitic noise. Per-Instance Classes -^^^^^^^^^^^^^^^^^^^^ +"""""""""""""""""""" If we have multiple instances of the same module, and they partition differently (likely; we make no attempt to partition them the same) then @@ -631,7 +632,7 @@ and takes an argument type ``AstNode*``. Caution on Using Iterators When Child Changes -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Visitors often replace one node with another node; V3Width and V3Const are major examples. A visitor which is the parent of such a replacement @@ -700,7 +701,7 @@ that type (if it is of class ``SOMETYPE``, or a derived class of as that is faster.) -.. _Testing +.. _Testing: Testing ======= @@ -1152,9 +1153,9 @@ Generally what would you do to add a new feature? 4. If a new Ast type is needed, add it to V3AstNodes.h. Follow the convention described above about the AstNode type hierarchy. -5. Now you can run "test_regress/t/t_{new testcase}.pl --debug" and it'll +5. Now you can run "test_regress/t/t_.pl --debug" and it'll probably fail but you'll see a - test_regress/obj_dir/t_{newtestcase}/*.tree file which you can examine + "test_regress/obj_dir/t_/*.tree" file which you can examine to see if the parsing worked. See also the sections above on debugging. 6. Modify the later visitor functions to process the new feature as needed. @@ -1179,8 +1180,6 @@ Verilator ideally would support all of IEEE, and has the goal to get close to full support. However the following IEEE sections and features are not anticipated to be ever implemented for the reasons indicated. -.. list-table:: - IEEE 1800-2017 3.3 recursive modules Little/no tool support, and arguably not a good practice. IEEE 1800-2017 6.12 "shortreal" diff --git a/docs/spelling.txt b/docs/spelling.txt new file mode 100644 index 000000000..278dd6b76 --- /dev/null +++ b/docs/spelling.txt @@ -0,0 +1,850 @@ +ABCp +Accellera +Affe +Aleksander +Ami +Amir +Anastasiadis +Antonin +Antwerpen +Arasanipalai +Arjen +Asciidoc +Ashutosh +Atmel +Aurelien +Bagri +Baltazar +Bardsley +Benchmarking +Berman +Bhagavatula +Bhattacharyya +Binderman +Bleiweiss +Bogdan +Bouchard +Boumenot +Brej +Briquet +Brownlee +Buckenmaier +Bybell +CMake +Cai +Cavium +Cfuncs +Chandan +Chitlesh +Christophe +Cochrane +Cuan +Cygwin +DErrico +Da +Danilo +Dannoritzer +Das +Dcache +Deadman +Debacker +Defparams +Denio +Deprecations +Deroo +Dickol +Diez +Dimitris +Dinotrace +Djordjevic +Dobbie +Dockerfile +Donal +Doorn +Doxygen +Dressler +Duraid +Dutton +Dzetkulic +Eda +Eddleston +Egbert +Egil +Eiler +Eivind +El +Elbourne +Embecosm +Engstrom +Enzo +Eugen +Fabrizio +Fekete +Ferrandi +Flachs +Foletto +Forker +Francillon +Fredieu +GTKWave +Galbi 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+Nalbantis +Narayan +Nauticus +Newgard +Nikana +Niranjan +Nitza +Noack +Nodine +Oleg +Olof +Olofsson +Oyvind +PLI +Patricio +Petr +Piechotka +Piersall +Plunkett +Popov +Prabhat +Prabhu +Prateek +Pre +Preprocess +Priyadharshini +Pullup +Pulver +Puri +Questa +Ralf +Rapp +Redhat +Reitan +Renga +Requin +Rodionov +Rolfe +Roodselaar +Runtime +Ruud +Rystsov +STandarD +Salman +Sanguinetti +Sanjay +Scharrer +Seitz +Shankar +Shanshan +Sharad +Shareef +Sheng +Shi +Shinkarovsky +Shirakawa +Shuba +Slatter +SoC +Sobhan +Sokorac +Solaris +Solomatnikov +Srini +Stamness +Stephane +Stoddard +Stroebel +Strouble +Stucki +Su +Suguimoto +Sundararajan +Suse +Syms +Synopsys +SystemC +SystemVerilog +Takatsukasa +Tambe +Tariq +Tengstrand +Terpstra +Thiede +Thierry +Thyer +Tichelaar +Tomov +Topa +Tota +Tresidder +Tri +Tristate +Turton +UNOPTFLAT +Ubixum +Uints +Undefines +Unsized +Uselib +Usha +Usuario +VERILATOR +Vasu +Vdly +Vemumtab +Vemuri +Veriable +Verialted +Verilate +Verilated +Verilating +Verilation +Verilator +Verilog +Viktor +Vm +Vukobratovic +Wai +Wasson +Welch +Werror +Wfuture +Whatson +Wildman +Wim +Wno +Wojciech +Wolfel +Wouters +Wpedantic +Wwarn +XSim +Xcelium +Xiaoliang +Xuan +Xuanqi +Yazdanbakhsh +Yi +Yinan +Yosys +Yu +Zhang +abirkmanis +accessor +accessors +agrobman +al +ala +andit +ar +architected +args +arrarys +assertOn +async +ato +atoi +autoconf +autoflush +bXXXX +backend +backslashed +backtrace +backtraces +basename +bbox +biguint +biops +bitstoreal +blackbox +bokke +brancoliticus +buf +bufif +buildenv +bv +bvs +callValueCbs +casex +casez +casted +cb +ccache +cdc +ceil +celldefine +cerr +cfunc +cfuncs +chandle +chandles +changeDetect +chenguokai +clk +clocker +cmake +cmos +combinational +combinatorial +commandArgsPlusMatch +compilable +concat +concats +config +const +coredump +countbits +countones +cout +cpp +cpu +ctor +ctrace +cutable +cygwin +dM +da +dat +datadir +datafiles +ddd +deassign +debugi +defenv +defname +defparam +demangling +der +desassign +destructor +detections +dev +devel +dir +displayb +distcc +doxygen +dpiGetContext +dpic +dsvf +dtor +dumpall +dumpfile +dumplimit +dumpoff +dumpon +dumpportlimit +dumpports +dumpportsall +dumpportslimit +dumpportsoff +dumpportson +dumpvars +dut +dx +elab +elsif +endcase +endcelldefine +endfunction +endgenerate +endian +endif +endmodule +endprotect +endspecify +endtask +engr +entrypoint +enum +enums +env +envvar +eof +erroring +et +eval +exe +executables +expr +extern +fanin +fasttrace +fbranch +fclose +fdisplay +feedthrus +feof +ferror +fflush +fgetc +fgets +filesystem +filt +flto +flushCall +fopen +foreach +fprintf +fprofile +fread +frewind +fs +fscanf +fseek +fsiegle +fst +fstrict +ftell +fullskew +func +funcs +fwrite +gantt +gcc +gdb +genblk +genvar +genvars +getenv +getline +gmake +gmon +gotFinish +gprof +gtkwave +hdr +hdzhangdoc +hh +hier +hierCMakeArgs +hierMkArgs +hierVer +hx +hyperthreads +icecream +idmap +ifdef +ifdefed +iff +ifndef +impot +incdir +includer +inferfaces +inhibitSim +initializer +initializers +inits +inlined +inlining +inout +inouts +inserted +instantiation +instantiations +iostream +ish +isunbounded +isunknown +killua +lang +lcov +ld +len +libext +libgoogle +libsystemc +libtcmalloc +linkers +linter +linux +liu +livelock +ln +loc +localparam +localparams +logicals +longint +lsb +lvalue +lxt +macromodule +makefile +makefiles +manpages +metacomment +metacomments +mis +misconnected +misconversion +missized +mk +mno +modport +modports +msg +msvc +mtask +mtasks +mulithreaded +mult +multidim +multiinterfaces +multiline +multipling +multithread +multithreaded +multithreading +mutexes +mux +mysignal +namespace +nand +nanduraj +nasties +negedge +negedges +netlist +netlists +nettype +nmos +noassert +nochange +noconfig +nol +nonblocking +noprivate +noreturn +notif +nullptr +onehot +ooo +oprofile +oversubscription +param +parameterized +params +parens +pc +pdf +perf +perftools +picoChip +pinout +plusargs +pmos +poping +portbind +portlists +posedge +posix +postfix +pragma +pragmas +pre +precisions +predefines +prepend +prepended +preprocess +preprocessed +preprocessing +preprocessor +prerelease +prev +printf +printtimescale +profcfunc +profcfuncs +prototyptes +ps +pthread +pulldown +pulldowns +pullup +pvalue +pwd +qrq +radix +randc +rarr +rdtsc +reStructuredText +readme +readmem +readmemb +readmemh +realpath +realtime +recoding +recrem +redeclaring +regs +reloop +resetall +respecified +rr +rst +runtime +runtimes +rw +sVerilator +sc +scalared +sccanf +seg +setuphold +sformat +sformatf +shortint +shortreal +signame +sp +specparam +splitme +spp +sqrt +srcdir +srcfile +sscanf +stderr +stdin +stdout +stime +stmts +strcasecmp +stringification +stringified +stringify +struct +structs +subcell +subcells +subexpressions +submodule +submodules +sv +svBitVal +svBitVecVal +svGet +svLogicVal +svdpi +swrite +sys +systemc +testbench +threadsafe +threashold +timeInc +timeformat +timeprecision +timeskew +timeunit +tinshark +tm +tolower +toolchain +topcell +toplevel +toupper +traceEverOn +tran +treei +tri +tristate +tristates +trunc +txt +typ +typedef +typedefed +typedefs +typename +uint +un +undef +undefineall +undriven +ungetc +uniquified +unistd +unlink +unlinked +unopt +unoptflat +unoptimizable +unroller +unsized +unsup +untyped +urandom +uselib +uwire +uwires +vc +vcd +vcddiff +vcoverage +vec +ver +verFiles +verible +verilate +verilated +verilator +verilog +verilogmod +verimake +vl +vlopt +vlt +vltstd +vluint +vpi +vpiLeftRange +vpiModule +vpiSize +vpiSuppressVal +vpiTimeUnit +vpiType +vpm +vpp +warmup +waveforms +whitespace +widthed +wreal +writeb +writeme +writemem +writememb +writememh +xin +xml +xnor +xout +xuejiazidi +yanx +yurivict +zdave diff --git a/docs/verilated.dox b/docs/verilated.dox new file mode 100644 index 000000000..eba749428 --- /dev/null +++ b/docs/verilated.dox @@ -0,0 +1,42 @@ +PROJECT_NAME = "Verilog to Routing - ABC" +INPUT = ../../include +OUTPUT_DIRECTORY = _build/doxygen/verilated + +EXTRACT_ALL = NO +EXTRACT_LOCAL_CLASSES = NO +EXTRACT_PRIVATE = NO +EXTRACT_STATIC = YES +FULL_PATH_NAMES = NO +GENERATE_HTML = NO +GENERATE_LATEX = NO +GENERATE_XML = YES +HIDE_FRIEND_COMPOUNDS = YES +HIDE_IN_BODY_DOCS = YES +HIDE_UNDOC_CLASSES = YES +HIDE_UNDOC_MEMBERS = YES +INTERNAL_DOCS = NO +OPTIMIZE_OUTPUT_FOR_C = NO +RECURSIVE = NO +SHOW_INCLUDE_FILES = NO +WARN_IF_UNDOCUMENTED = NO + +ENABLE_PREPROCESSING = YES +MACRO_EXPANSION = YES +EXPAND_ONLY_PREDEF = YES +PREDEFINED = \ + "DOXYGEN=1" \ + "VL_ATTR_NORETURN=" \ + "VL_ATTR_PRINTF()=" \ + "VL_ATTR_WEAK=" \ + "VL_GUARDED_BY()=" \ + "VL_MT_SAFE=" \ + "VL_MT_SAFE_EXCLUDES()=" \ + "VL_MT_SAFE_POSTINIT=" \ + "VL_MT_UNSAFE=" \ + "VL_MT_UNSAFE_ONE=" \ + "VL_NOT_FINAL=" \ + "VL_PURE=" \ + "VL_REQUIRES()=" \ + "VL_THREAD_LOCAL=" \ + "__restrict=" \ + diff --git a/docs/xml.rst b/docs/xml.rst index a6aab1e0c..c145c5991 100644 --- a/docs/xml.rst +++ b/docs/xml.rst @@ -1,8 +1,8 @@ |Logo| -=========================== +*************************** Verilator XML Output Format -=========================== +*************************** Introduction ============ diff --git a/src/pod2latexfix b/src/pod2latexfix deleted file mode 100755 index 6cf21004e..000000000 --- a/src/pod2latexfix +++ /dev/null @@ -1,36 +0,0 @@ -#!/usr/bin/env perl -###################################################################### -# -# Copyright 2002-2021 by Wilson Snyder. This program is free software; you -# can redistribute it and/or modify it under the terms of either the GNU -# Lesser General Public License Version 3 or the Perl Artistic License -# Version 2.0. -# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 -# -###################################################################### -# DESCRIPTION: Edits pod2latex output - -use warnings; - -my $Opt_DistTitle = $ARGV[0] or die "%Error: No disttitle specified,"; -my $Opt_DistDate = $ARGV[1] or die "%Error: No distdate specified,"; - -my $header = - ("\\usepackage[left=1.0in,right=1.0in,top=1.0in,bottom=1.0in]{geometry}\n" - ."\\usepackage[pdftex,bookmarks=true,bookmarksnumbered=true,hypertexnames=false,breaklinks=true,colorlinks=true,linkcolor=blue]{hyperref}\n" - ."\\usepackage{fancyhdr} \\pagestyle{fancy}\n" - ."\\usepackage{graphicx}\n" - ."\n" - ."\\setlength{\\parindent}{0pt} \\setlength{\\parskip}{\\baselineskip}\n" - ."\n" - ."\\title{\\includegraphics[width=6cm]{docs/_static/verilator_logo.png}\\\\ ${Opt_DistTitle}}\n" - ."\\date{${Opt_DistDate}}\n" - ."\\author{https:\/\/verilator.org}\n" - ."\\lhead[${Opt_DistTitle}]{${Opt_DistTitle}}\n" - ); - -foreach my $line () { - $line =~ s/(\\begin\{document\})/${header}$1/; - $line =~ s/(\\tableofcontents)/\\begin\{titlepage\} \\maketitle \\end\{titlepage\}\n$1/; - print "$line"; -} diff --git a/test_regress/driver.pl b/test_regress/driver.pl index c33ebb2bb..26ca19722 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -2388,6 +2388,74 @@ sub file_sed { $self->write_wholefile($outfilename, $contents); } +sub extract { + my $self = (ref $_[0]? shift : $Self); + my %param = (#in =>, + #out => + regexp => qr/.*/, + lineno_adjust => -9999, + lines => undef, #'#, #-#', + @_); + + my $temp_fn = $param{out}; + $temp_fn =~ s!.*/!!g; + $temp_fn = $self->{obj_dir} . "/" . $temp_fn; + + my @out; + my $emph = ""; + my $lineno = 0; + my $lineno_out = 0; + { + my $fh = IO::File->new("<$param{in}") or die "%Error: $! $param{in},"; + while (defined(my $line = $fh->getline)) { + ++$lineno; + if ($line =~ /$param{regexp}/ + && _lineno_match($lineno, $param{lines})) { + if ($line =~ m!t/[A-Za-z0-9_]+.v:(\d+):(\d+):!) { + my $lineno = $1; + my $col = $2; + $lineno += $param{lineno_adjust}; + $lineno = 1 if $lineno < 1; + $line =~ s!t/[A-Za-z0-9_]+.v:(\d+):(\d+):!example.v:${lineno}:${col}!; + } + push @out, " " . $line; + ++$lineno_out; + if ($line =~ /<--/) { + $emph .= "," if $emph; + $emph .= $lineno_out; + } + } + } + } + { + my $fhw = IO::File->new(">$temp_fn") or die "%Error: $! $temp_fn,"; + my $lang = ""; + $lang = " sv" if $param{in} =~ /\.s?vh?$/; + $fhw->print(".. comment: generated by " . $self->{name} . "\n"); + $fhw->print(".. code-block::${lang}\n"); + $fhw->print(" :linenos:\n") if $lang && $#out > 0; + $fhw->print(" :emphasize-lines: ${emph}\n") if $emph; + $fhw->print("\n"); + foreach my $line (@out) { + $fhw->print($line); + } + } + + $self->files_identical($temp_fn, $param{out}); +} + +sub _lineno_match { + my $lineno = shift; + my $lines = shift; + return 1 if !defined $lines; + if ($lines =~ /^(\d+)$/) { + return $1 == $lineno; + } elsif ($lines =~ /^(\d+)-(\d+)$/) { + return $1 <= $lineno && $2 >= $lineno; + } + return 0; +} + ####################################################################### ####################################################################### ####################################################################### diff --git a/test_regress/t/t_assert_comp_bad.pl b/test_regress/t/t_assert_comp_bad.pl index b9699fb8a..403e165d7 100755 --- a/test_regress/t/t_assert_comp_bad.pl +++ b/test_regress/t/t_assert_comp_bad.pl @@ -18,5 +18,45 @@ compile( expect_filename => $Self->{golden_filename}, ); +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_USERWARN_faulty.rst", + regexp => qr/\$warn.*User/); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_USERERROR_faulty.rst", + regexp => qr/\$error.*User/); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_USERINFO_faulty.rst", + regexp => qr/\$info.*User/); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_USERFATAL_faulty.rst", + regexp => qr/\$fatal.*User/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_USERWARN_msg.rst", + regexp => qr/USERWARN:.* User/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_USERERROR_msg.rst", + regexp => qr/USERERROR:.* User/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_USERINFO_msg.rst", + regexp => qr/-Info:.* User/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_USERFATAL_msg.rst", + regexp => qr/USERFATAL/); + ok(1); 1; diff --git a/test_regress/t/t_lint_width_docs_bad.out b/test_regress/t/t_lint_width_docs_bad.out new file mode 100644 index 000000000..132dc2e6d --- /dev/null +++ b/test_regress/t/t_lint_width_docs_bad.out @@ -0,0 +1,6 @@ +%Warning-WIDTH: t/t_lint_width_docs_bad.v:10:29: Bit extraction of array[4:0] requires 3 bit index, not 2 bits. + : ... In instance t + 10 | wire int rd_value = array[rd_addr]; + | ^ + ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_lint_width_docs_bad.pl b/test_regress/t/t_lint_width_docs_bad.pl new file mode 100755 index 000000000..1afe476b9 --- /dev/null +++ b/test_regress/t/t_lint_width_docs_bad.pl @@ -0,0 +1,36 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + verilator_flags2 => ["--lint-only"], + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_WIDTH_1_faulty.rst", + lines => "8-10"); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_WIDTH_1_msg.rst", + lineno_adjust => -7, + regexp => qr/Warning-WIDTH/); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_WIDTH_1_fixed.rst", + lines => "18"); + +ok(1); +1; diff --git a/test_regress/t/t_lint_width_docs_bad.v b/test_regress/t/t_lint_width_docs_bad.v new file mode 100644 index 000000000..1a99073a0 --- /dev/null +++ b/test_regress/t/t_lint_width_docs_bad.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = array[rd_addr]; //<--- Warning + + ok ok(); +endmodule + +module ok; + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = array[{1'b0, rd_addr}]; //<--- Fixed +endmodule; diff --git a/test_regress/t/t_var_bad_hide_docs.out b/test_regress/t/t_var_bad_hide_docs.out new file mode 100644 index 000000000..3ce6c7460 --- /dev/null +++ b/test_regress/t/t_var_bad_hide_docs.out @@ -0,0 +1,8 @@ +%Warning-VARHIDDEN: t/t_var_bad_hide_docs.v:8:12: Declaration of signal hides declaration in upper scope: 't' + 8 | integer t; + | ^ + t/t_var_bad_hide_docs.v:7:8: ... Location of original declaration + 7 | module t; + | ^ + ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. +%Error: Exiting due to diff --git a/test_regress/t/t_var_bad_hide_docs.pl b/test_regress/t/t_var_bad_hide_docs.pl new file mode 100755 index 000000000..f43bd4b48 --- /dev/null +++ b/test_regress/t/t_var_bad_hide_docs.pl @@ -0,0 +1,31 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(linter => 1); + +lint( + verilator_flags2 => ["--lint-only -Wwarn-VARHIDDEN"], + fails => $Self->{vlt_all}, + expect_filename => $Self->{golden_filename}, + ); + +extract( + in => $Self->{top_filename}, + out => "../docs/gen/ex_VARHIDDEN_faulty.rst", + regexp => qr/(module t|integer|endmodule)/); + +extract( + in => $Self->{golden_filename}, + out => "../docs/gen/ex_VARHIDDEN_msg.rst", + lineno_adjust => -6, + regexp => qr/(var_bad_hide)/); + +ok(1); +1; diff --git a/test_regress/t/t_var_bad_hide_docs.v b/test_regress/t/t_var_bad_hide_docs.v new file mode 100644 index 000000000..964f69f5a --- /dev/null +++ b/test_regress/t/t_var_bad_hide_docs.v @@ -0,0 +1,9 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + integer t; //<--- Warning ('t' hidden by module 't') +endmodule diff --git a/test_regress/t/t_width_docs_bad.v b/test_regress/t/t_width_docs_bad.v new file mode 100644 index 000000000..13ed51756 --- /dev/null +++ b/test_regress/t/t_width_docs_bad.v @@ -0,0 +1,19 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2009 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t; + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = read_array[rd_addr]; //<--- Warning + + ok ok(); +endmodule + +module ok; + int array[5]; + bit [1:0] rd_addr; + wire int rd_value = read_array[{1'b0, rd_addr}]; //<--- Fixed +endmodule; From a9bd112e0c04e408acaeb7920bcfdf5e9c05d3d9 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 11 Apr 2021 20:38:37 -0400 Subject: [PATCH 083/110] Fix version number in doc guide --- Makefile.in | 3 +++ docs/_static/css/vlt_sphinx.css | 4 ++++ docs/guide/conf.py | 8 +++++--- 3 files changed, 12 insertions(+), 3 deletions(-) create mode 100644 docs/_static/css/vlt_sphinx.css diff --git a/Makefile.in b/Makefile.in index a2efb887d..10531bae6 100644 --- a/Makefile.in +++ b/Makefile.in @@ -54,6 +54,9 @@ POD2TEXT = pod2text MKINSTALLDIRS = $(SHELL) $(srcdir)/src/mkinstalldirs PERL = @PERL@ +# Version (for docs/guide/conf.py) +PACKAGE_VERSION_NUMBER = @PACKAGE_VERSION_NUMBER@ + # Destination prefix for RPMs DESTDIR = diff --git a/docs/_static/css/vlt_sphinx.css b/docs/_static/css/vlt_sphinx.css new file mode 100644 index 000000000..ab5e13b76 --- /dev/null +++ b/docs/_static/css/vlt_sphinx.css @@ -0,0 +1,4 @@ +/*Verilator blue #008fd7; set in html*/ +.wy-side-nav-search > div.version { + color: #111; +} diff --git a/docs/guide/conf.py b/docs/guide/conf.py index 1a94aa6b1..465fd151d 100644 --- a/docs/guide/conf.py +++ b/docs/guide/conf.py @@ -20,14 +20,16 @@ import sphinx_rtd_theme def get_vlt_version(): - filename = "../../src/config_rev.h" + filename = "../../Makefile" with open(filename) as fh: for line in fh: - match = re.search(r'= "([a-z0-9.]+)', line) + match = re.search(r"PACKAGE_VERSION_NUMBER *= *([a-z0-9.]+)", line) if match: return match.group(1) return "unknown" +def setup(app): + app.add_css_file('css/vlt_sphinx.css') # ---------------------------------------------------------------------- # -- Project information @@ -63,7 +65,7 @@ extensions = [] # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path. exclude_patterns = [ - '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst' + '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*' ] # Warn about refs From 04ebba8667c0af386d66df129df4af79fd02d2e4 Mon Sep 17 00:00:00 2001 From: github action Date: Mon, 12 Apr 2021 00:39:38 +0000 Subject: [PATCH 084/110] Apply clang-format --- docs/guide/conf.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/docs/guide/conf.py b/docs/guide/conf.py index 465fd151d..6a9193246 100644 --- a/docs/guide/conf.py +++ b/docs/guide/conf.py @@ -28,9 +28,11 @@ def get_vlt_version(): return match.group(1) return "unknown" + def setup(app): app.add_css_file('css/vlt_sphinx.css') + # ---------------------------------------------------------------------- # -- Project information From ee875d0166b3c14b68106e3b26c738181e7d3458 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 11 Apr 2021 20:52:40 -0400 Subject: [PATCH 085/110] Fix edit-on-git in sphinx docs --- docs/guide/conf.py | 5 ++++- docs/guide/index.rst | 4 ++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/docs/guide/conf.py b/docs/guide/conf.py index 6a9193246..0602f1250 100644 --- a/docs/guide/conf.py +++ b/docs/guide/conf.py @@ -119,7 +119,7 @@ html_context = { 'display_github': True, 'github_user': 'verilator', 'github_repo': 'verilator', - 'github_version': 'master/docs/user/', + 'github_version': 'master/docs/', } # Add any paths that contain custom static files (such as style sheets) here, @@ -130,6 +130,9 @@ html_static_path = ['../_static'] # If true, "Created using Sphinx" is shown in the HTML footer. Default is True. html_show_sphinx = False +html_copy_source = False +html_show_sourcelink = False + html_use_index = False html_favicon = "../_static/verilator_32x32_min.png" diff --git a/docs/guide/index.rst b/docs/guide/index.rst index 42c18b4c1..d6a60ba57 100644 --- a/docs/guide/index.rst +++ b/docs/guide/index.rst @@ -1,6 +1,10 @@ .. Copyright 2003-2021 by Wilson Snyder. .. SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 +###################### +Verilator User's Guide +###################### + .. toctree:: :maxdepth: 2 :caption: Getting Started From 62b528c2e3a53fdf2954018c8c50283eca5a66f9 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 11 Apr 2021 20:57:32 -0400 Subject: [PATCH 086/110] Fix duplicate figures in sphinx docs --- Makefile.in | 7 +++++-- docs/guide/conf.py | 3 ++- docs/{_static => guide/figures}/fig_gantt_min.png | Bin docs/guide/simulating.rst | 2 +- 4 files changed, 8 insertions(+), 4 deletions(-) rename docs/{_static => guide/figures}/fig_gantt_min.png (100%) diff --git a/Makefile.in b/Makefile.in index 10531bae6..0e0d7607a 100644 --- a/Makefile.in +++ b/Makefile.in @@ -139,10 +139,13 @@ DISTFILES1 = $(INFOS) .gitignore \ docs/CONTRIBUTING.rst \ docs/CONTRIBUTORS \ docs/Makefile \ - docs/_static/* \ + docs/_static/*.png \ + docs/_static/css/* \ docs/bin/* \ docs/gen/* \ - docs/guide/* \ + docs/guide/*.py \ + docs/guide/*.rst \ + docs/guide/figures/* \ docs/install.rst \ docs/internals.rst \ docs/internals.rst \ diff --git a/docs/guide/conf.py b/docs/guide/conf.py index 0602f1250..a4ef9e545 100644 --- a/docs/guide/conf.py +++ b/docs/guide/conf.py @@ -67,7 +67,8 @@ extensions = [] # directories to ignore when looking for source files. # This pattern also affects html_static_path and html_extra_path. exclude_patterns = [ - '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*' + '_build', 'Thumbs.db', '.DS_Store', 'internals.rst', 'xml.rst', 'gen/ex_*', + 'CONTRIBUTING.rst' ] # Warn about refs diff --git a/docs/_static/fig_gantt_min.png b/docs/guide/figures/fig_gantt_min.png similarity index 100% rename from docs/_static/fig_gantt_min.png rename to docs/guide/figures/fig_gantt_min.png diff --git a/docs/guide/simulating.rst b/docs/guide/simulating.rst index e817dae4c..39ebf1464 100644 --- a/docs/guide/simulating.rst +++ b/docs/guide/simulating.rst @@ -304,7 +304,7 @@ The :command:`verilator_gantt` program may then be run to transform the saved profiling file into a nicer visual format and produce some related statistics. -.. figure:: ../_static/fig_gantt_min.png +.. figure:: figures/fig_gantt_min.png Example verilator_gantt output, as viewed with GTKWave. From 136468ca78a538d9d076e4d2514e7bbc59889a85 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 11 Apr 2021 21:49:15 -0400 Subject: [PATCH 087/110] Docs: fix unicode arrows --- docs/_static/css/vlt_sphinx.css | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/docs/_static/css/vlt_sphinx.css b/docs/_static/css/vlt_sphinx.css index ab5e13b76..bb9bc7e1e 100644 --- a/docs/_static/css/vlt_sphinx.css +++ b/docs/_static/css/vlt_sphinx.css @@ -2,3 +2,15 @@ .wy-side-nav-search > div.version { color: #111; } +.fa-github::before, .icon-github::before { + content: ""; +} +.fa-home::before, .icon-home::before { + content: ""; +} +.fa-arrow-circle-right::before, .icon-circle-arrow-right::before { + content: ""; +} +.fa-arrow-circle-left::before, .icon-circle-arrow-left::before { + content: ""; +} From 8fcf9da1ad0bc8d730ef3210fbbca7a48ca0b94a Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 11 Apr 2021 21:49:48 -0400 Subject: [PATCH 088/110] Docs: Move html generation to single directory --- docs/Makefile | 2 +- docs/guide/conf.py | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/Makefile b/docs/Makefile index e9488273f..5884dfddb 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -21,7 +21,7 @@ DOXYGEN = doxygen SPHINXOPTS ?= -c guide SPHINXBUILD ?= sphinx-build -SOURCEDIR = . +SOURCEDIR = guide BUILDDIR = _build ###################################################################### diff --git a/docs/guide/conf.py b/docs/guide/conf.py index a4ef9e545..1d30f1d51 100644 --- a/docs/guide/conf.py +++ b/docs/guide/conf.py @@ -41,7 +41,7 @@ copyright = '2021 by Wilson Snyder, under LGPL-3.0 or Artistic-2.0' author = 'Wilson Snyder' # The master toctree document. -master_doc = "guide/index" +master_doc = "index" version = get_vlt_version() release = get_vlt_version() @@ -120,7 +120,7 @@ html_context = { 'display_github': True, 'github_user': 'verilator', 'github_repo': 'verilator', - 'github_version': 'master/docs/', + 'github_version': 'master/docs/guide/', } # Add any paths that contain custom static files (such as style sheets) here, From ac26d5889fd5bd29cd0648c374531ad28ad064fe Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 11 Apr 2021 22:22:43 -0400 Subject: [PATCH 089/110] Fix whitespace --- docs/guide/example_common_install.rst | 2 -- docs/guide/exe_verilator.rst | 1 - docs/guide/extensions.rst | 2 -- docs/verilated.dox | 1 - 4 files changed, 6 deletions(-) diff --git a/docs/guide/example_common_install.rst b/docs/guide/example_common_install.rst index 4a7795344..5735b5150 100644 --- a/docs/guide/example_common_install.rst +++ b/docs/guide/example_common_install.rst @@ -14,5 +14,3 @@ point to the kit: # See above; don't do this if using an OS-distributed Verilator export VERILATOR_ROOT=/path/to/where/verilator/was/installed export PATH=$VERILATOR_ROOT/bin:$PATH - - diff --git a/docs/guide/exe_verilator.rst b/docs/guide/exe_verilator.rst index 060d80d2d..f7cf6dbd4 100644 --- a/docs/guide/exe_verilator.rst +++ b/docs/guide/exe_verilator.rst @@ -1620,4 +1620,3 @@ The grammar of configuration commands is as follows: For tracing_off, instances below any module in the files/ranges specified will also not be traced. - diff --git a/docs/guide/extensions.rst b/docs/guide/extensions.rst index d88490afe..1d0cbf0f7 100644 --- a/docs/guide/extensions.rst +++ b/docs/guide/extensions.rst @@ -488,5 +488,3 @@ or "`ifdef`"'s may break other tools. Re-enable waveform tracing for all future signals or instances that are declared. - - diff --git a/docs/verilated.dox b/docs/verilated.dox index eba749428..5af927ba6 100644 --- a/docs/verilated.dox +++ b/docs/verilated.dox @@ -39,4 +39,3 @@ PREDEFINED = \ "VL_REQUIRES()=" \ "VL_THREAD_LOCAL=" \ "__restrict=" \ - From 70c1eda17410886f0800d18b9061f35d76d4bc41 Mon Sep 17 00:00:00 2001 From: Todd Strader Date: Mon, 12 Apr 2021 15:00:36 -0400 Subject: [PATCH 090/110] Fix package reported as vpiModule (#2885) --- src/V3EmitCSyms.cpp | 3 ++- test_regress/t/t_vpi_module.v | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index a389d6a7b..8661ac966 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -298,11 +298,12 @@ class EmitCSyms final : EmitCBaseVisitor { m_scopes.emplace_back(std::make_pair(nodep, m_modp)); if (v3Global.opt.vpi() && !nodep->isTop()) { + string type = VN_IS(nodep->modp(), Package) ? "SCOPE_OTHER" : "SCOPE_MODULE"; string name_dedot = AstNode::dedotName(nodep->shortName()); int timeunit = m_modp->timeunit().powerOfTen(); m_vpiScopeCandidates.insert( std::make_pair(nodep->name(), ScopeData(scopeSymString(nodep->name()), name_dedot, - timeunit, "SCOPE_MODULE"))); + timeunit, type))); } } virtual void visit(AstScopeName* nodep) override { diff --git a/test_regress/t/t_vpi_module.v b/test_regress/t/t_vpi_module.v index 8d29e6622..ab6ac8201 100644 --- a/test_regress/t/t_vpi_module.v +++ b/test_regress/t/t_vpi_module.v @@ -12,6 +12,10 @@ import "DPI-C" context function int mon_check(); `endif +package somepackage; + int someint /*verilator public_flat_rw*/; +endpackage + module t (/*AUTOARG*/ // Inputs clk From 4c2a9aac4c21d1f1b95a12eb22c753a3584596c9 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 13 Apr 2021 08:57:51 -0400 Subject: [PATCH 091/110] Docs: Fix make html rule --- docs/Makefile | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/docs/Makefile b/docs/Makefile index 5884dfddb..aac5c9cc8 100644 --- a/docs/Makefile +++ b/docs/Makefile @@ -42,12 +42,7 @@ vl-extract: ../bin/verilator ../Changes ###################################################################### # HTML -htmled: - $(MAKE) vl-extract - $(MAKE) html - $(PYTHON3) bin/vl_sphinx_fix _build - -server: htmled +server: html cd _build/html && $(PYTHON3) -m http.server %.html: %.rst @@ -68,8 +63,10 @@ pdf: ###################################################################### -html latex clean linkcheck spelling:: +html latex linkcheck spelling:: + $(MAKE) vl-extract $(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) + $(PYTHON3) bin/vl_sphinx_fix _build help: @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) From 39d9ecfe51bd2cd6bba01f56a401fa9921d6a7e7 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 13 Apr 2021 09:06:53 -0400 Subject: [PATCH 092/110] Fix cmake version number (#2881) --- Changes | 3 ++- verilator-config-version.cmake.in | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/Changes b/Changes index 8a9220922..8b831699d 100644 --- a/Changes +++ b/Changes @@ -34,6 +34,7 @@ Verilator 4.201 devel * Fix interface localparam access (#2859). [Todd Strader] * Fix Cygwin example compile issues (#2856). [Mark Shaw] * Fix select of with index variable (#2880). [Alexander Grobman] +* Fix cmake version number to be numeric (#2881). [Yuri Victorovich] Verilator 4.200 2021-03-12 @@ -387,7 +388,7 @@ Verilator 4.028 2020-02-08 * Add loc column location in XML (replaces fl). (#2122) [Pieter Kapsenberg] * Add error on misused define. [Topa Tota] * Add parameter to set maximum signal width. (#2082) [Øyvind Harboe] -* Add warning on genvar in normal for loop. (#2143) [yurivict] +* Add warning on genvar in normal for loop. (#2143) [Yuri Victorovich] * Fix VPI scope naming for public modules. [Nandu Raj] * Fix FST tracing of enums inside structs. [fsiegle] * Fix WIDTH warning on Date: Tue, 13 Apr 2021 09:25:11 -0400 Subject: [PATCH 093/110] Docs: Fix cross-references --- README.rst | 27 +++++++++------------------ bin/verilator | 8 ++++---- bin/verilator_coverage | 6 ++++-- bin/verilator_gantt | 6 ++++-- bin/verilator_profcfunc | 6 ++++-- 5 files changed, 25 insertions(+), 28 deletions(-) diff --git a/README.rst b/README.rst index 8591c7587..d13cd58ba 100644 --- a/README.rst +++ b/README.rst @@ -23,15 +23,15 @@ Welcome to Verilator * Compiles into multithreaded C++, or SystemC * Creates XML to front-end your own tools - |Logo| - * - |verilator multithreaded performance bg min| + * - |verilator multithreaded performance| - **Fast** * Outperforms many commercial simulators * Single- and multi-threaded output models * - **Widely Used** * Wide industry and academic deployment * Out-of-the-box support from Arm, and RISC-V vendor IP - - |verilator usage 400x200 min| - * - |verilator community 400x125 min| + - |verilator usage| + * - |verilator community| - **Community Driven & Openly Licensed** * Guided by the `CHIPS Alliance`_ and `Linux Foundation`_ * Open, and free as in both speech and beer @@ -40,7 +40,7 @@ Welcome to Verilator * Commercial support contracts * Design support contracts * Enhancement contracts - - |verilator support 400x125 min| + - |verilator support| What Verilator Does @@ -85,15 +85,6 @@ Modelsim, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on computes rather than licenses. Thus Verilator gives you the best cycles/dollar. -For more information on how Verilator stacks up to some of the other -closed-sourced and open-sourced Verilog simulators, see the `Verilog -Simulator Benchmarks -`_. (If you -benchmark Verilator, please see the notes in the `Verilator manual (PDF) -`_, and also if possible post on -the forums the results; there may be additional tweaks possible.) - - Installation & Documentation ============================ @@ -123,7 +114,7 @@ We appreciate and welcome your contributions in whatever form; please see `Contributing to Verilator `_. Thanks to our `Contributors and Sponsors -`_. +`_. Verilator also supports and encourages commercial support models and organizations; please see `Verilator Commercial Support @@ -154,7 +145,7 @@ Perl Artistic License Version 2.0. See the documentation for more details. .. _Icarus Verilog: http://iverilog.icarus.com .. _Linux Foundation: https://www.linuxfoundation.org .. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png -.. |verilator multithreaded performance bg min| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png -.. |verilator usage 400x200 min| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png -.. |verilator community 400x125 min| image:: https://www.veripool.org/img/verilator_community_400x125-min.png -.. |verilator support 400x125 min| image:: https://www.veripool.org/img/verilator_support_400x125-min.png +.. |verilator multithreaded performance| image:: https://www.veripool.org/img/verilator_multithreaded_performance_bg-min.png +.. |verilator usage| image:: https://www.veripool.org/img/verilator_usage_400x200-min.png +.. |verilator community| image:: https://www.veripool.org/img/verilator_community_400x125-min.png +.. |verilator support| image:: https://www.veripool.org/img/verilator_support_400x125-min.png diff --git a/bin/verilator b/bin/verilator index 59fb5e608..9e1ce7094 100755 --- a/bin/verilator +++ b/bin/verilator @@ -263,8 +263,8 @@ For documentation see L. =head1 ARGUMENT SUMMARY This is a short summary of the arguments to the "verilator" executable. -See L for the detailed -descriptions of these arguments. +See L for the +detailed descriptions of these arguments. =for VL_SPHINX_EXTRACT "_build/gen/args_verilator.rst" @@ -432,8 +432,8 @@ descriptions of these arguments. This is a short summary of the simulation runtime arguments, i.e. for the final Verilated simulation runtime models. See -L for the detailed description of -these arguments. +L for the detailed +description of these arguments. =for VL_SPHINX_EXTRACT "_build/gen/args_verilated.rst" diff --git a/bin/verilator_coverage b/bin/verilator_coverage index e6ecbb77a..ab76d15ba 100755 --- a/bin/verilator_coverage +++ b/bin/verilator_coverage @@ -160,7 +160,8 @@ verilator_coverage - Verilator coverage analyzer Verilator_coverage processes Verilated model-generated coverage reports. -For documentation see L. +For documentation see +L. =head1 ARGUMENT SUMMARY @@ -199,7 +200,8 @@ C, C L which is the source for this document. -and L for detailed documentation. +and L for +detailed documentation. =cut diff --git a/bin/verilator_gantt b/bin/verilator_gantt index 2251d9f6a..8d043670d 100755 --- a/bin/verilator_gantt +++ b/bin/verilator_gantt @@ -539,7 +539,8 @@ Verilator_gantt creates a visual representation to help analyze Verilator multithreaded simulation performance, by showing when each macro-task starts and ends, and showing when each thread is busy or idle. -For documentation see L. +For documentation see +L. =head1 ARGUMENT SUMMARY @@ -564,7 +565,8 @@ SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 C -and L for detailed documentation. +and L for +detailed documentation. =cut diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index 8dade5ef3..e0c5340bf 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -214,7 +214,8 @@ the functions are then transformed, assuming the user used Verilator's --prof-cfuncs, and a report printed showing the percentage of time, etc, in each Verilog block. -For documentation see L. +For documentation see +L. =head1 ARGUMENT SUMMARY @@ -236,7 +237,8 @@ SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 C -and L for detailed documentation. +and L for +detailed documentation. =cut From f579e557060feaabfaae8651d0438c62b344c43f Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 13 Apr 2021 20:19:08 -0400 Subject: [PATCH 094/110] Commentary --- docs/guide/warnings.rst | 43 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/docs/guide/warnings.rst b/docs/guide/warnings.rst index 2e79f4e62..ac0ca9329 100644 --- a/docs/guide/warnings.rst +++ b/docs/guide/warnings.rst @@ -442,6 +442,16 @@ List Of Warnings Other tools with similar warnings: Veriable's forbid_defparam_rule. +.. option:: DEPRECATED + + Warning that a Verilator metacomment, or configuration file command uses + syntax that has been deprecated. Upgrade the code to the replacement + that should be suggested by the warning message. + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + .. option:: DETECTARRAY .. TODO better example @@ -502,6 +512,16 @@ List Of Warnings generated C++ code to add appropriate prints to see what is going on. +.. option:: ENDCAPSULATED + + Warns that a class member is declared is local or protected, but is + being accessed from outside that class (if local) or a derrived class + (if protected). + + Ignoring this warning will only suppress the lint check, it will + simulate correctly. + + .. option:: ENDLABEL Warns that a label attached to a "end"-something statement does not @@ -928,6 +948,29 @@ List Of Warnings This error may be disabled with a lint_off PINNOTFOUND metacomment. +.. option:: PORTSHORT + + Warns that an output port is connected to a constant. + + .. code-block:: sv + :linenos: + :emphasize-lines: 5-6 + + module a; + sub sub + (.out(1'b1)); //<--- error PORTSHORT + endmodule + + module sub (output out); + assign out = '1; + endmodule + + In the example above, out is an output but is connected to a constant + implying it is an input. + + This error may be disabled with a lint_off PORTSHORT metacomment. + + .. option:: PKGNODECL .. TODO better example From f5ad5cf034570d46cee0573e723d548c7ae1c770 Mon Sep 17 00:00:00 2001 From: David Metz Date: Wed, 14 Apr 2021 22:52:14 +0200 Subject: [PATCH 095/110] Fix dumping waveforms to multiple FST files (#2889) --- docs/CONTRIBUTORS | 1 + include/verilated_fst_c.cpp | 1 + test_regress/t/t_trace_cat_fst.cpp | 54 +++++ test_regress/t/t_trace_cat_fst.pl | 29 +++ test_regress/t/t_trace_cat_fst.v | 18 ++ test_regress/t/t_trace_cat_fst_0000.out | 272 ++++++++++++++++++++++++ test_regress/t/t_trace_cat_fst_0100.out | 247 +++++++++++++++++++++ 7 files changed, 622 insertions(+) create mode 100644 test_regress/t/t_trace_cat_fst.cpp create mode 100755 test_regress/t/t_trace_cat_fst.pl create mode 100644 test_regress/t/t_trace_cat_fst.v create mode 100644 test_regress/t/t_trace_cat_fst_0000.out create mode 100644 test_regress/t/t_trace_cat_fst_0100.out diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index a85ea0582..e20735dd4 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -11,6 +11,7 @@ Chris Randall Conor McCullough Dan Petrisko David Horton +David Metz David Stanford David Turner Drew Taussig diff --git a/include/verilated_fst_c.cpp b/include/verilated_fst_c.cpp index 1120e0529..0fccee988 100644 --- a/include/verilated_fst_c.cpp +++ b/include/verilated_fst_c.cpp @@ -105,6 +105,7 @@ void VerilatedFst::open(const char* filename) VL_MT_SAFE_EXCLUDES(m_mutex) { #ifdef VL_TRACE_FST_WRITER_THREAD fstWriterSetParallelMode(m_fst, 1); #endif + fullDump(true); // First dump must be full for fst m_curScope.clear(); diff --git a/test_regress/t/t_trace_cat_fst.cpp b/test_regress/t/t_trace_cat_fst.cpp new file mode 100644 index 000000000..8432da0e3 --- /dev/null +++ b/test_regress/t/t_trace_cat_fst.cpp @@ -0,0 +1,54 @@ +// -*- mode: C++; c-file-style: "cc-mode" -*- +// +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2008 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +#include +#include +#include + +#include VM_PREFIX_INCLUDE + +unsigned long long main_time = 0; +double sc_time_stamp() { return (double)main_time; } + +const char* trace_name() { + static char name[1000]; + VL_SNPRINTF(name, 1000, VL_STRINGIFY(TEST_OBJ_DIR) "/simpart_%04d.fst", (int)main_time); + return name; +} + +int main(int argc, char** argv, char** env) { + std::unique_ptr top{new VM_PREFIX("top")}; + + Verilated::debug(0); + Verilated::traceEverOn(true); + + std::unique_ptr tfp{new VerilatedFstC}; + top->trace(tfp.get(), 99); + + tfp->open(trace_name()); + + top->clk = 0; + + while (main_time < 190) { // Creates 2 files + top->clk = !top->clk; + top->eval(); + + if ((main_time % 100) == 0) { + tfp->close(); + tfp->open(trace_name()); + } + tfp->dump((unsigned int)(main_time)); + ++main_time; + } + tfp->close(); + top->final(); + tfp.reset(); + top.reset(); + printf("*-* All Finished *-*\n"); + return 0; +} diff --git a/test_regress/t/t_trace_cat_fst.pl b/test_regress/t/t_trace_cat_fst.pl new file mode 100755 index 000000000..8715369c7 --- /dev/null +++ b/test_regress/t/t_trace_cat_fst.pl @@ -0,0 +1,29 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003-2013 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(vlt_all => 1); + +compile( + make_top_shell => 0, + make_main => 0, + v_flags2 => ["--trace-fst --exe $Self->{t_dir}/t_trace_cat_fst.cpp"], + ); + +execute( + check_finished => 1, + ); + +fst_identical("$Self->{obj_dir}/simpart_0000.fst", + "t/$Self->{name}_0000.out"); +fst_identical("$Self->{obj_dir}/simpart_0100.fst", + "t/$Self->{name}_0100.out"); + +ok(1); +1; diff --git a/test_regress/t/t_trace_cat_fst.v b/test_regress/t/t_trace_cat_fst.v new file mode 100644 index 000000000..e56dc4a09 --- /dev/null +++ b/test_regress/t/t_trace_cat_fst.v @@ -0,0 +1,18 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2013 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t + ( + input wire clk + ); + + integer cyc; initial cyc = 0; + integer unchanged; initial unchanged = 42; + + always @ (posedge clk) begin + cyc <= cyc + 1; + end +endmodule diff --git a/test_regress/t/t_trace_cat_fst_0000.out b/test_regress/t/t_trace_cat_fst_0000.out new file mode 100644 index 000000000..9797307a3 --- /dev/null +++ b/test_regress/t/t_trace_cat_fst_0000.out @@ -0,0 +1,272 @@ +$date + Wed Apr 14 17:11:07 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$var wire 1 ! clk $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc $end +$var integer 32 # unchanged $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +b00000000000000000000000000101010 # +b00000000000000000000000000000000 " +1! +$end +#1 +0! +#2 +1! +b00000000000000000000000000000001 " +#3 +0! +#4 +1! +b00000000000000000000000000000010 " +#5 +0! +#6 +1! +b00000000000000000000000000000011 " +#7 +0! +#8 +1! +b00000000000000000000000000000100 " +#9 +0! +#10 +1! +b00000000000000000000000000000101 " +#11 +0! +#12 +1! +b00000000000000000000000000000110 " +#13 +0! +#14 +1! +b00000000000000000000000000000111 " +#15 +0! +#16 +1! +b00000000000000000000000000001000 " +#17 +0! +#18 +1! +b00000000000000000000000000001001 " +#19 +0! +#20 +1! +b00000000000000000000000000001010 " +#21 +0! +#22 +1! +b00000000000000000000000000001011 " +#23 +0! +#24 +1! +b00000000000000000000000000001100 " +#25 +0! +#26 +1! +b00000000000000000000000000001101 " +#27 +0! +#28 +1! +b00000000000000000000000000001110 " +#29 +0! +#30 +1! +b00000000000000000000000000001111 " +#31 +0! +#32 +1! +b00000000000000000000000000010000 " +#33 +0! +#34 +1! +b00000000000000000000000000010001 " +#35 +0! +#36 +1! +b00000000000000000000000000010010 " +#37 +0! +#38 +1! +b00000000000000000000000000010011 " +#39 +0! +#40 +1! +b00000000000000000000000000010100 " +#41 +0! +#42 +1! +b00000000000000000000000000010101 " +#43 +0! +#44 +1! +b00000000000000000000000000010110 " +#45 +0! +#46 +1! +b00000000000000000000000000010111 " +#47 +0! +#48 +1! +b00000000000000000000000000011000 " +#49 +0! +#50 +1! +b00000000000000000000000000011001 " +#51 +0! +#52 +1! +b00000000000000000000000000011010 " +#53 +0! +#54 +1! +b00000000000000000000000000011011 " +#55 +0! +#56 +1! +b00000000000000000000000000011100 " +#57 +0! +#58 +1! +b00000000000000000000000000011101 " +#59 +0! +#60 +1! +b00000000000000000000000000011110 " +#61 +0! +#62 +1! +b00000000000000000000000000011111 " +#63 +0! +#64 +1! +b00000000000000000000000000100000 " +#65 +0! +#66 +1! +b00000000000000000000000000100001 " +#67 +0! +#68 +1! +b00000000000000000000000000100010 " +#69 +0! +#70 +1! +b00000000000000000000000000100011 " +#71 +0! +#72 +1! +b00000000000000000000000000100100 " +#73 +0! +#74 +1! +b00000000000000000000000000100101 " +#75 +0! +#76 +1! +b00000000000000000000000000100110 " +#77 +0! +#78 +1! +b00000000000000000000000000100111 " +#79 +0! +#80 +1! +b00000000000000000000000000101000 " +#81 +0! +#82 +1! +b00000000000000000000000000101001 " +#83 +0! +#84 +1! +b00000000000000000000000000101010 " +#85 +0! +#86 +1! +b00000000000000000000000000101011 " +#87 +0! +#88 +1! +b00000000000000000000000000101100 " +#89 +0! +#90 +1! +b00000000000000000000000000101101 " +#91 +0! +#92 +1! +b00000000000000000000000000101110 " +#93 +0! +#94 +1! +b00000000000000000000000000101111 " +#95 +0! +#96 +1! +b00000000000000000000000000110000 " +#97 +0! +#98 +1! +b00000000000000000000000000110001 " +#99 +0! diff --git a/test_regress/t/t_trace_cat_fst_0100.out b/test_regress/t/t_trace_cat_fst_0100.out new file mode 100644 index 000000000..fb24bf654 --- /dev/null +++ b/test_regress/t/t_trace_cat_fst_0100.out @@ -0,0 +1,247 @@ +$date + Wed Apr 14 17:04:26 2021 + +$end +$version + fstWriter +$end +$timescale + 1ps +$end +$scope module top $end +$var wire 1 ! clk $end +$scope module t $end +$var wire 1 ! clk $end +$var integer 32 " cyc $end +$var integer 32 # unchanged $end +$upscope $end +$upscope $end +$enddefinitions $end +#100 +$dumpvars +b00000000000000000000000000101010 # +b00000000000000000000000000110010 " +1! +$end +#101 +0! +#102 +1! +b00000000000000000000000000110011 " +#103 +0! +#104 +1! +b00000000000000000000000000110100 " +#105 +0! +#106 +1! +b00000000000000000000000000110101 " +#107 +0! +#108 +1! +b00000000000000000000000000110110 " +#109 +0! +#110 +1! +b00000000000000000000000000110111 " +#111 +0! +#112 +1! +b00000000000000000000000000111000 " +#113 +0! +#114 +1! +b00000000000000000000000000111001 " +#115 +0! +#116 +1! +b00000000000000000000000000111010 " +#117 +0! +#118 +1! +b00000000000000000000000000111011 " +#119 +0! +#120 +1! +b00000000000000000000000000111100 " +#121 +0! +#122 +1! +b00000000000000000000000000111101 " +#123 +0! +#124 +1! +b00000000000000000000000000111110 " +#125 +0! +#126 +1! +b00000000000000000000000000111111 " +#127 +0! +#128 +1! +b00000000000000000000000001000000 " +#129 +0! +#130 +1! +b00000000000000000000000001000001 " +#131 +0! +#132 +1! +b00000000000000000000000001000010 " +#133 +0! +#134 +1! +b00000000000000000000000001000011 " +#135 +0! +#136 +1! +b00000000000000000000000001000100 " +#137 +0! +#138 +1! +b00000000000000000000000001000101 " +#139 +0! +#140 +1! +b00000000000000000000000001000110 " +#141 +0! +#142 +1! +b00000000000000000000000001000111 " +#143 +0! +#144 +1! +b00000000000000000000000001001000 " +#145 +0! +#146 +1! +b00000000000000000000000001001001 " +#147 +0! +#148 +1! +b00000000000000000000000001001010 " +#149 +0! +#150 +1! +b00000000000000000000000001001011 " +#151 +0! +#152 +1! +b00000000000000000000000001001100 " +#153 +0! +#154 +1! +b00000000000000000000000001001101 " +#155 +0! +#156 +1! +b00000000000000000000000001001110 " +#157 +0! +#158 +1! +b00000000000000000000000001001111 " +#159 +0! +#160 +1! +b00000000000000000000000001010000 " +#161 +0! +#162 +1! +b00000000000000000000000001010001 " +#163 +0! +#164 +1! +b00000000000000000000000001010010 " +#165 +0! +#166 +1! +b00000000000000000000000001010011 " +#167 +0! +#168 +1! +b00000000000000000000000001010100 " +#169 +0! +#170 +1! +b00000000000000000000000001010101 " +#171 +0! +#172 +1! +b00000000000000000000000001010110 " +#173 +0! +#174 +1! +b00000000000000000000000001010111 " +#175 +0! +#176 +1! +b00000000000000000000000001011000 " +#177 +0! +#178 +1! +b00000000000000000000000001011001 " +#179 +0! +#180 +1! +b00000000000000000000000001011010 " +#181 +0! +#182 +1! +b00000000000000000000000001011011 " +#183 +0! +#184 +1! +b00000000000000000000000001011100 " +#185 +0! +#186 +1! +b00000000000000000000000001011101 " +#187 +0! +#188 +1! +b00000000000000000000000001011110 " +#189 +0! From 53a6830f71666c9bd84d811a4f82ca978975f633 Mon Sep 17 00:00:00 2001 From: Todd Strader Date: Fri, 16 Apr 2021 15:25:47 -0400 Subject: [PATCH 096/110] Fix cast from packed, typedef'ed interface signal (#2884) --- src/V3Width.cpp | 11 +++++++++-- test_regress/t/t_cast.v | 21 +++++++++++++++++++++ 2 files changed, 30 insertions(+), 2 deletions(-) diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 06381e587..a36501eb1 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -6026,8 +6026,15 @@ private: toDtp = toDtp->skipRefToEnump(); fromDtp = fromDtp->skipRefToEnump(); if (toDtp == fromDtp) return COMPATIBLE; - bool fromNumericable = VN_IS(fromDtp, BasicDType) || VN_IS(fromDtp, EnumDType) - || VN_IS(fromDtp, NodeUOrStructDType); + AstNodeDType* fromBaseDtp = fromDtp; + while (AstPackArrayDType* packp = VN_CAST(fromBaseDtp, PackArrayDType)) { + fromBaseDtp = packp->subDTypep(); + while (AstRefDType* refp = VN_CAST(fromBaseDtp, RefDType)) { + fromBaseDtp = refp->refDTypep(); + } + } + bool fromNumericable = VN_IS(fromBaseDtp, BasicDType) || VN_IS(fromBaseDtp, EnumDType) + || VN_IS(fromBaseDtp, NodeUOrStructDType); // UNSUP unpacked struct/unions (treated like BasicDType) if (VN_IS(toDtp, BasicDType) || VN_IS(toDtp, NodeUOrStructDType)) { if (fromNumericable) return COMPATIBLE; diff --git a/test_regress/t/t_cast.v b/test_regress/t/t_cast.v index 3a6cfe81c..bf7ca06c5 100644 --- a/test_regress/t/t_cast.v +++ b/test_regress/t/t_cast.v @@ -4,6 +4,13 @@ // any use, without warranty, 2011 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 +interface intf; + typedef logic [7:0] octet; + typedef octet [1:0] word; + octet [1:0] octets; + word [1:0] words; +endinterface + module t; typedef logic [3:0] mc_t; @@ -12,6 +19,9 @@ module t; typedef struct packed { logic [15:0] data; } packed_t; + typedef struct packed { + logic [31:0] data; + } packed2_t; typedef enum [15:0] { ONE = 1 @@ -19,6 +29,7 @@ module t; packed_t pdata; packed_t pdata_reg; + packed2_t pdata2_reg; assign pdata.data = 16'h1234; logic [7:0] logic8bit; assign logic8bit = $bits(logic8bit)'(pdata >> 8); @@ -26,6 +37,8 @@ module t; mc_t o; enum_t e; + intf the_intf(); + logic [15:0] allones = 16'hffff; parameter FOUR = 4; @@ -79,6 +92,14 @@ module t; o = tocast_t'(4'b1); if (o != 4'b1) $stop; + the_intf.octets = 16'd1; + pdata_reg = packed_t'(the_intf.octets); + if (pdata_reg.data != 16'd1) $stop; + + the_intf.words = 32'd1; + pdata2_reg = packed2_t'(the_intf.words); + if (pdata2_reg.data != 32'd1) $stop; + if (15'h6cec != outa) $stop; if (27'h7ffecec != mida) $stop; if (27'h7ffecec != midb) $stop; From 56dd58d259e8d90ebcfb3ee44af494945d92c8f0 Mon Sep 17 00:00:00 2001 From: Yutetsu TAKATSUKASA Date: Sat, 17 Apr 2021 05:50:30 +0900 Subject: [PATCH 097/110] Fix assertion failure in bitOpTree (#2892) * Tests: Add a test to reproduce #2891 * Fix assertion failure in binary op tree opt. --- src/V3Const.cpp | 1 + test_regress/t/t_const_opt_cov.pl | 26 +++++++++++ test_regress/t/t_const_opt_cov.v | 78 +++++++++++++++++++++++++++++++ 3 files changed, 105 insertions(+) create mode 100755 test_regress/t/t_const_opt_cov.pl create mode 100644 test_regress/t/t_const_opt_cov.v diff --git a/src/V3Const.cpp b/src/V3Const.cpp index e1b990513..3d87a2057 100644 --- a/src/V3Const.cpp +++ b/src/V3Const.cpp @@ -98,6 +98,7 @@ class ConstBitOpTreeVisitor final : public AstNVisitor { V3Number m_bitPolarity; // Coefficient of each bit static int widthOfRef(AstVarRef* refp) { if (AstWordSel* selp = VN_CAST(refp->backp(), WordSel)) return selp->width(); + if (AstCCast* castp = VN_CAST(refp->backp(), CCast)) return castp->width(); return refp->width(); } diff --git a/test_regress/t/t_const_opt_cov.pl b/test_regress/t/t_const_opt_cov.pl new file mode 100755 index 000000000..1e0a96b74 --- /dev/null +++ b/test_regress/t/t_const_opt_cov.pl @@ -0,0 +1,26 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2=>["-Wno-UNOPTTHREADS", "--stats", "--coverage"], + ); + +execute( + check_finished => 1, + ); + +if ($Self->{vlt}) { + file_grep($Self->{stats}, qr/Optimizations, Const bit op reduction\s+(\d+)/i, 2); +} + +ok(1); +1; diff --git a/test_regress/t/t_const_opt_cov.v b/test_regress/t/t_const_opt_cov.v new file mode 100644 index 000000000..245309007 --- /dev/null +++ b/test_regress/t/t_const_opt_cov.v @@ -0,0 +1,78 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +module t(/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + // Take CRC data and apply to testblock inputs + wire [32:0] in = crc[32:0]; + + logic bank_rd_vec_m3; + always_ff @(posedge clk) bank_rd_vec_m3 <= crc[33]; + + + wire out; + ecc_check_pipe u_bank_data_ecc_check( + .clk (clk), + .bank_rd_m3 (bank_rd_vec_m3), + .data_i (in), + .ecc_err_o (out) + ); + + + + // Aggregate outputs into a single result vector + wire [63:0] result = {63'b0, out}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc == 0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + sum <= '0; + end + else if (cyc < 10) begin + sum <= '0; + end + else if (cyc == 99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; + // What checksum will we end up with (above print should match) +`define EXPECTED_SUM 64'h768b162c5835e35b + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + +endmodule + +module ecc_check_pipe ( + input logic clk, + input logic bank_rd_m3, + input logic [32:0] data_i, + output logic ecc_err_o + ); + logic [3:0] check_group_6_0; + logic check_group_6_0_q; + + always_comb check_group_6_0 = {data_i[0], data_i[2], data_i[4], data_i[7] }; + always_ff @(posedge clk) if (bank_rd_m3) check_group_6_0_q <=^check_group_6_0; + assign ecc_err_o = check_group_6_0_q; +endmodule From 2e9e4ae11011b72283af1c7bd52c0c9b51af95ed Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 18 Apr 2021 10:16:18 -0400 Subject: [PATCH 098/110] Add an URL on warnings to point to the manual's description. --- Changes | 1 + configure.ac | 1 + src/V3Error.cpp | 14 +++++++++++--- src/V3Error.h | 4 +++- src/config_build.h.in | 2 ++ test_regress/t/t_alias2_unsup.out | 1 + test_regress/t/t_alias_unsup.out | 1 + test_regress/t/t_array_list_bad.out | 1 + test_regress/t/t_assert_comp_bad.out | 1 + test_regress/t/t_assoc_wildcard_unsup.out | 1 + test_regress/t/t_case_x_bad.out | 1 + test_regress/t/t_case_zx_bad.out | 1 + test_regress/t/t_castdyn_castconst_bad.out | 1 + test_regress/t/t_castdyn_unsup_bad.out | 1 + test_regress/t/t_cdc_async_bad.out | 1 + test_regress/t/t_class_class.out | 1 + test_regress/t/t_class_extends_bad.out | 1 + test_regress/t/t_class_local_bad.out | 1 + test_regress/t/t_class_member_bad.out | 1 + test_regress/t/t_class_param.out | 1 + test_regress/t/t_class_param_bad.out | 1 + test_regress/t/t_class_static.out | 1 + test_regress/t/t_class_static_order.out | 1 + test_regress/t/t_class_unsup_bad.out | 1 + test_regress/t/t_class_vparam.out | 1 + test_regress/t/t_clk_first_bad.out | 1 + test_regress/t/t_clk_scope_bad.out | 1 + test_regress/t/t_clocker_bad.out | 1 + test_regress/t/t_concat_large_bad.out | 1 + test_regress/t/t_concat_link_bad.out | 1 + test_regress/t/t_const_bad.out | 1 + test_regress/t/t_delay_stmtdly_bad.out | 1 + test_regress/t/t_dpi_unpack_bad.out | 1 + test_regress/t/t_dynarray_bad.out | 1 + test_regress/t/t_enum_bad_hide.out | 1 + test_regress/t/t_event_control_unsup.out | 1 + test_regress/t/t_event_copy.out | 1 + test_regress/t/t_flag_context_bad.out | 1 + test_regress/t/t_flag_main_sc_bad.out | 1 + test_regress/t/t_flag_topmodule_bad.out | 1 + test_regress/t/t_flag_werror_bad1.out | 1 + test_regress/t/t_flag_werror_bad2.out | 1 + test_regress/t/t_flag_wfatal.out | 1 + test_regress/t/t_for_comma_bad.out | 1 + test_regress/t/t_fork.out | 1 + test_regress/t/t_fork_disable.out | 1 + test_regress/t/t_func_bad.out | 1 + test_regress/t/t_func_bad2.out | 1 + test_regress/t/t_func_bad_width.out | 1 + test_regress/t/t_func_const2_bad.out | 1 + test_regress/t/t_func_const3_bad.out | 1 + test_regress/t/t_func_const_bad.out | 1 + test_regress/t/t_func_const_packed_array_bad.out | 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1 + 185 files changed, 198 insertions(+), 4 deletions(-) diff --git a/Changes b/Changes index 8b831699d..5ffac9a75 100644 --- a/Changes +++ b/Changes @@ -17,6 +17,7 @@ Verilator 4.201 devel **Minor:** +* Add an URL on warnings to point to the manual's description. * Add EOFNEWLINE warning when missing a newline at EOF. * Changed TIMESCALEMOD from error into a warning. * Verilated signals now use VlWide and VlPacked in place of C arrays. diff --git a/configure.ac b/configure.ac index 810812ab0..e8c5ac7f4 100644 --- a/configure.ac +++ b/configure.ac @@ -21,6 +21,7 @@ AC_CONFIG_FILES(Makefile src/Makefile src/Makefile_obj include/verilated.mk incl AC_MSG_RESULT([configuring for $PACKAGE_STRING]) PACKAGE_VERSION_NUMBER=`AS_ECHO("$PACKAGE_VERSION") | sed 's/ .*//g'` AC_SUBST(PACKAGE_VERSION_NUMBER) +AC_DEFINE_UNQUOTED([PACKAGE_VERSION_NUMBER_STRING],["$PACKAGE_VERSION_NUMBER"],[Package version as a number]) # Ignore automake flags passed by Ubuntu builds AC_ARG_ENABLE([dependency-tracking], diff --git a/src/V3Error.cpp b/src/V3Error.cpp index 13e506916..23921b0ee 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -39,6 +39,7 @@ bool V3Error::s_errorSuppressed = false; std::array V3Error::s_describedEachWarn; std::array V3Error::s_pretendError; bool V3Error::s_describedWarnings = false; +bool V3Error::s_describedWeb = false; V3Error::MessagesSet V3Error::s_messages; V3Error::ErrorExitCb V3Error::s_errorExitCb = nullptr; @@ -225,13 +226,20 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { } if (!s_errorSuppressed && !(s_errorCode == V3ErrorCode::EC_INFO || s_errorCode == V3ErrorCode::USERINFO)) { + const bool anError = isError(s_errorCode, s_errorSuppressed); + if (s_errorCode >= V3ErrorCode::EC_FIRST_NAMED && !s_describedWeb) { + s_describedWeb = true; + std::cerr << warnMore() << "... For " << (anError ? "error" : "warning") + << " description see https://verilator.org/warn/" << s_errorCode.ascii() + << "?v=" << PACKAGE_VERSION_NUMBER_STRING << endl; + } if (!s_describedEachWarn[s_errorCode] && !s_pretendError[s_errorCode]) { s_describedEachWarn[s_errorCode] = true; if (s_errorCode >= V3ErrorCode::EC_FIRST_WARN && !s_describedWarnings) { + s_describedWarnings = true; std::cerr << warnMore() << "... Use \"/* verilator lint_off " << s_errorCode.ascii() << " */\" and lint_on around source to disable this message." << endl; - s_describedWarnings = true; } if (s_errorCode.dangerous()) { std::cerr << warnMore() << "*** See the manual before disabling this,\n"; @@ -248,7 +256,7 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { s_tellManual = 2; } } - if (isError(s_errorCode, s_errorSuppressed)) { + if (anError) { incErrors(); } else { incWarnings(); @@ -276,7 +284,7 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { } vlAbortOrExit(); - } else if (isError(s_errorCode, s_errorSuppressed)) { + } else if (anError) { // We don't dump tree on any error because a Visitor may be in middle of // a tree cleanup and cause a false broken problem. if (s_errorExitCb) s_errorExitCb(); diff --git a/src/V3Error.h b/src/V3Error.h index a312fe6e9..eb1cff471 100644 --- a/src/V3Error.h +++ b/src/V3Error.h @@ -44,6 +44,7 @@ public: EC_FATALEXIT, // Kill the program, suppress with --quiet-exit EC_FATALSRC, // Kill the program, for internal source errors EC_ERROR, // General error out, can't suppress + EC_FIRST_NAMED, // Just a code so the program knows where to start info/errors // Boolean information we track per-line, but aren't errors I_CELLDEFINE, // Inside cell define from `celldefine/`endcelldefine I_COVERAGE, // Coverage is on/off from /*verilator coverage_on/off*/ @@ -151,7 +152,7 @@ public: // clang-format off static const char* const names[] = { // Leading spaces indicate it can't be disabled. - " MIN", " INFO", " FATAL", " FATALEXIT", " FATALSRC", " ERROR", + " MIN", " INFO", " FATAL", " FATALEXIT", " FATALSRC", " ERROR", " FIRST_NAMED", // Boolean " I_CELLDEFINE", " I_COVERAGE", " I_TRACING", " I_LINT", " I_DEF_NETTYPE_WIRE", // Errors @@ -235,6 +236,7 @@ class V3Error final { private: static bool s_describedWarnings; // Told user how to disable warns + static bool s_describedWeb; // Told user to see web static std::array s_describedEachWarn; // Told user specifics about this warning static std::array diff --git a/src/config_build.h.in b/src/config_build.h.in index 62ca75a08..a6808d09b 100644 --- a/src/config_build.h.in +++ b/src/config_build.h.in @@ -22,6 +22,8 @@ // Autoconf substitutes this with the strings from AC_INIT. #define PACKAGE_STRING "" +#define PACKAGE_VERSION_NUMBER_STRING "0.000" + #define DTVERSION PACKAGE_STRING //********************************************************************** diff --git a/test_regress/t/t_alias2_unsup.out b/test_regress/t/t_alias2_unsup.out index f3414eed9..5b408a195 100644 --- a/test_regress/t/t_alias2_unsup.out +++ b/test_regress/t/t_alias2_unsup.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_alias2_unsup.v:39:4: Unsupported: alias statements 39 | alias b = {a[3:0],a[7:4]}; | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_alias_unsup.out b/test_regress/t/t_alias_unsup.out index c43253fa9..617b2d923 100644 --- a/test_regress/t/t_alias_unsup.out +++ b/test_regress/t/t_alias_unsup.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_alias_unsup.v:46:4: Unsupported: alias statements 46 | alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b; | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_array_list_bad.out b/test_regress/t/t_array_list_bad.out index 45f539258..ded2a3c8f 100644 --- a/test_regress/t/t_array_list_bad.out +++ b/test_regress/t/t_array_list_bad.out @@ -6,5 +6,6 @@ : ... In instance t 38 | test_out <= '{'0, '0}; | ^~ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_assert_comp_bad.out b/test_regress/t/t_assert_comp_bad.out index 5cf3179a8..dddd9af67 100644 --- a/test_regress/t/t_assert_comp_bad.out +++ b/test_regress/t/t_assert_comp_bad.out @@ -10,6 +10,7 @@ : ... In instance t 12 | $warning; | ^~~~~~~~ + ... For warning description see https://verilator.org/warn/USERWARN?v=4.201 ... Use "/* verilator lint_off USERWARN */" and lint_on around source to disable this message. %Warning-USERWARN: t/t_assert_comp_bad.v:13:7: User elaboration-time warning : ... In instance t diff --git a/test_regress/t/t_assoc_wildcard_unsup.out b/test_regress/t/t_assoc_wildcard_unsup.out index 7d4edc557..5939b8009 100644 --- a/test_regress/t/t_assoc_wildcard_unsup.out +++ b/test_regress/t/t_assoc_wildcard_unsup.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_assoc_wildcard_unsup.v:25:19: Unsupported: [*] wildcard associative arrays 25 | string a [*]; | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_case_x_bad.out b/test_regress/t/t_case_x_bad.out index db1e485fa..7647e1bd8 100644 --- a/test_regress/t/t_case_x_bad.out +++ b/test_regress/t/t_case_x_bad.out @@ -1,6 +1,7 @@ %Warning-CASEX: t/t_case_x_bad.v:14:7: Suggest casez (with ?'s) in place of casex (with X's) 14 | casex (value) | ^~~~~ + ... For warning description see https://verilator.org/warn/CASEX?v=4.201 ... Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message. %Warning-CASEWITHX: t/t_case_x_bad.v:19:9: Use of x/? constant in case statement, (perhaps intended casex/casez) 19 | 4'b1xxx: $stop; diff --git a/test_regress/t/t_case_zx_bad.out b/test_regress/t/t_case_zx_bad.out index ca591019c..77bae7948 100644 --- a/test_regress/t/t_case_zx_bad.out +++ b/test_regress/t/t_case_zx_bad.out @@ -1,5 +1,6 @@ %Warning-CASEWITHX: t/t_case_zx_bad.v:16:9: Use of x constant in casez statement, (perhaps intended ?/z in constant) 16 | 4'b1xxx: $stop; | ^~~~~~~ + ... For warning description see https://verilator.org/warn/CASEWITHX?v=4.201 ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_castdyn_castconst_bad.out b/test_regress/t/t_castdyn_castconst_bad.out index cb8251c49..eb69bf69a 100644 --- a/test_regress/t/t_castdyn_castconst_bad.out +++ b/test_regress/t/t_castdyn_castconst_bad.out @@ -3,6 +3,7 @@ : ... Suggest static cast 20 | i = $cast(v, 1); | ^~~~~ + ... For warning description see https://verilator.org/warn/CASTCONST?v=4.201 ... Use "/* verilator lint_off CASTCONST */" and lint_on around source to disable this message. %Warning-CASTCONST: t/t_castdyn_castconst_bad.v:21:11: $cast will always return one as 'CLASSREFDTYPE 'Base'' is always castable from 'CLASSREFDTYPE 'Base'' : ... In instance t diff --git a/test_regress/t/t_castdyn_unsup_bad.out b/test_regress/t/t_castdyn_unsup_bad.out index bb045d2d7..6fc6e0993 100644 --- a/test_regress/t/t_castdyn_unsup_bad.out +++ b/test_regress/t/t_castdyn_unsup_bad.out @@ -3,4 +3,5 @@ : ... Suggest try static cast 13 | $cast(q, aarray); | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_cdc_async_bad.out b/test_regress/t/t_cdc_async_bad.out index 030217948..29b887c6d 100644 --- a/test_regress/t/t_cdc_async_bad.out +++ b/test_regress/t/t_cdc_async_bad.out @@ -1,6 +1,7 @@ %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:28:21: Logic in path that feeds async reset, via signal: 't.rst2_bad_n' 28 | wire rst2_bad_n = rst0_n | rst1_n; | ^ + ... For warning description see https://verilator.org/warn/CDCRSTLOGIC?v=4.201 ... Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message. %Warning-CDCRSTLOGIC: See details in obj_vlt/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53:21: Logic in path that feeds async reset, via signal: 't.rst6a_bad_n' diff --git a/test_regress/t/t_class_class.out b/test_regress/t/t_class_class.out index 0ea383361..52e4f1a5a 100644 --- a/test_regress/t/t_class_class.out +++ b/test_regress/t/t_class_class.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_class_class.v:12:4: Unsupported: class within class 12 | class SubCls; | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_class_extends_bad.out b/test_regress/t/t_class_extends_bad.out index b382ead9d..ddb6fa925 100644 --- a/test_regress/t/t_class_extends_bad.out +++ b/test_regress/t/t_class_extends_bad.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_class_extends_bad.v:13:26: Multiple inheritance illegal on non-interface classes (IEEE 1800-2017 8.13), and unsupported for interface classes. 13 | class Cls extends Base1, Base2; | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_class_local_bad.out b/test_regress/t/t_class_local_bad.out index 102a251d1..3e302dcb6 100644 --- a/test_regress/t/t_class_local_bad.out +++ b/test_regress/t/t_class_local_bad.out @@ -5,6 +5,7 @@ t/t_class_local_bad.v:71:20: ... Location of definition 15 | local int m_loc = 2; | ^~~~~ + ... For error description see https://verilator.org/warn/ENCAPSULATED?v=4.201 %Error-ENCAPSULATED: t/t_class_local_bad.v:72:20: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2017 8.18) : ... In instance t 72 | bad(); if (c.m_prot != 20) $stop; diff --git a/test_regress/t/t_class_member_bad.out b/test_regress/t/t_class_member_bad.out index ef2eaedc8..9d42c83c6 100644 --- a/test_regress/t/t_class_member_bad.out +++ b/test_regress/t/t_class_member_bad.out @@ -7,5 +7,6 @@ : ... In instance t 18 | c.memb3 = 3; | ^ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_class_param.out b/test_regress/t/t_class_param.out index 1a041787c..9d6a6a7aa 100644 --- a/test_regress/t/t_class_param.out +++ b/test_regress/t/t_class_param.out @@ -2,6 +2,7 @@ : ... In instance t 9 | class Cls #(parameter P = 12); | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_class_param.v:20:11: Unsupported: parameterized classes : ... In instance t 20 | Cls #(.P(4)) c4; diff --git a/test_regress/t/t_class_param_bad.out b/test_regress/t/t_class_param_bad.out index 83375ea19..5b964ef07 100644 --- a/test_regress/t/t_class_param_bad.out +++ b/test_regress/t/t_class_param_bad.out @@ -2,6 +2,7 @@ : ... Suggested alternative: 'PARAMB' 12 | Cls #(.PARAMBAD(1)) c; | ^~~~~~~~ + ... For error description see https://verilator.org/warn/PINNOTFOUND?v=4.201 %Error-PINNOTFOUND: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2' 13 | Cls #(13, 1) cd; | ^ diff --git a/test_regress/t/t_class_static.out b/test_regress/t/t_class_static.out index 678029a0e..acf6927d0 100644 --- a/test_regress/t/t_class_static.out +++ b/test_regress/t/t_class_static.out @@ -2,6 +2,7 @@ : ... In instance t 12 | static int c_st = 2; | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_class_static.v:25:18: Unsupported: 'static' function/task variables : ... In instance t 25 | static int st = 2; st++; return st; diff --git a/test_regress/t/t_class_static_order.out b/test_regress/t/t_class_static_order.out index 9565f5068..c11fb5441 100644 --- a/test_regress/t/t_class_static_order.out +++ b/test_regress/t/t_class_static_order.out @@ -2,6 +2,7 @@ : ... In instance t 23 | static ClsZ z = new; | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_class_static_order.v:34:16: Unsupported: 'static' class members : ... In instance t 34 | static ClsA a = new; diff --git a/test_regress/t/t_class_unsup_bad.out b/test_regress/t/t_class_unsup_bad.out index f5260c57b..2f41c590f 100644 --- a/test_regress/t/t_class_unsup_bad.out +++ b/test_regress/t/t_class_unsup_bad.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_class_unsup_bad.v:7:1: Unsupported: virtual interface 7 | virtual interface vi_t vi; | ^~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_class_unsup_bad.v:8:1: Unsupported: virtual data type 8 | virtual vi_t vi2; | ^~~~~~~ diff --git a/test_regress/t/t_class_vparam.out b/test_regress/t/t_class_vparam.out index 798dea2ca..02394f30e 100644 --- a/test_regress/t/t_class_vparam.out +++ b/test_regress/t/t_class_vparam.out @@ -2,6 +2,7 @@ : ... In instance t 11 | typedef paramed_class_t#(real, 1) paramed_class_double_t; | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_class_vparam.v:13:56: Unsupported: class parameters : ... In instance t 13 | virtual class vclass #(type CTYPE_t = arg_class_t, int I = 0); diff --git a/test_regress/t/t_clk_first_bad.out b/test_regress/t/t_clk_first_bad.out index d12bc84d9..5245ee96d 100644 --- a/test_regress/t/t_clk_first_bad.out +++ b/test_regress/t/t_clk_first_bad.out @@ -1,5 +1,6 @@ %Warning-DEPRECATED: t/t_clk_first_deprecated.v:12:14: sc_clock is ignored 12 | input clk /*verilator sc_clock*/ ; | ^~~~~~~~~~~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/DEPRECATED?v=4.201 ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_clk_scope_bad.out b/test_regress/t/t_clk_scope_bad.out index bec10941c..cae7ba966 100644 --- a/test_regress/t/t_clk_scope_bad.out +++ b/test_regress/t/t_clk_scope_bad.out @@ -2,5 +2,6 @@ : ... In instance t.p2 36 | q <= d; | ^ + ... For warning description see https://verilator.org/warn/CLKDATA?v=4.201 ... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_clocker_bad.out b/test_regress/t/t_clocker_bad.out index eb3477c3c..ec0b9542f 100644 --- a/test_regress/t/t_clocker_bad.out +++ b/test_regress/t/t_clocker_bad.out @@ -1,6 +1,7 @@ %Warning-CLKDATA: t/t_clocker.v:45:17: Clock is assigned to part of data signal 'res8' 45 | assign res8 = {clk_3, 1'b0, clk_4}; | ^ + ... For warning description see https://verilator.org/warn/CLKDATA?v=4.201 ... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message. %Warning-CLKDATA: t/t_clocker.v:46:17: Clock is assigned to part of data signal 'res16' 46 | assign res16 = {count, clk_3, clk_1, clk_4}; diff --git a/test_regress/t/t_concat_large_bad.out b/test_regress/t/t_concat_large_bad.out index a4afc3552..c692aa033 100644 --- a/test_regress/t/t_concat_large_bad.out +++ b/test_regress/t/t_concat_large_bad.out @@ -2,5 +2,6 @@ : ... In instance t 9 | wire [32767:0] a = {32768{1'b1}}; | ^ + ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=4.201 ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_concat_link_bad.out b/test_regress/t/t_concat_link_bad.out index 6760aa004..3af888452 100644 --- a/test_regress/t/t_concat_link_bad.out +++ b/test_regress/t/t_concat_link_bad.out @@ -10,5 +10,6 @@ %Warning-IMPLICIT: t/t_concat_link_bad.v:13:12: Signal definition not found, creating implicitly: 'bar_s' 13 | assign bar_s = {foo_s, foo_s}.f1; | ^~~~~ + ... For warning description see https://verilator.org/warn/IMPLICIT?v=4.201 ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_const_bad.out b/test_regress/t/t_const_bad.out index 6594d207b..ece6e4628 100644 --- a/test_regress/t/t_const_bad.out +++ b/test_regress/t/t_const_bad.out @@ -2,6 +2,7 @@ : ... In instance t 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; | ^~~ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... In instance t diff --git a/test_regress/t/t_delay_stmtdly_bad.out b/test_regress/t/t_delay_stmtdly_bad.out index a5beee6c4..1d0bb8faa 100644 --- a/test_regress/t/t_delay_stmtdly_bad.out +++ b/test_regress/t/t_delay_stmtdly_bad.out @@ -1,6 +1,7 @@ %Warning-ASSIGNDLY: t/t_delay.v:22:13: Unsupported: Ignoring delay on this assignment/primitive. 22 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1; | ^~~~~~~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=4.201 ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message. %Warning-ASSIGNDLY: t/t_delay.v:27:19: Unsupported: Ignoring delay on this assignment/primitive. 27 | dly0 <= #0 32'h11; diff --git a/test_regress/t/t_dpi_unpack_bad.out b/test_regress/t/t_dpi_unpack_bad.out index 735465cf0..fdb556ff2 100644 --- a/test_regress/t/t_dpi_unpack_bad.out +++ b/test_regress/t/t_dpi_unpack_bad.out @@ -2,6 +2,7 @@ : ... In instance t 21 | import_func0(sig0); | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Warning-WIDTH: t/t_dpi_unpack_bad.v:21:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's VARREF 'sig0' generates 3 bits. : ... In instance t 21 | import_func0(sig0); diff --git a/test_regress/t/t_dynarray_bad.out b/test_regress/t/t_dynarray_bad.out index ad5729bd3..ba0ea8ceb 100644 --- a/test_regress/t/t_dynarray_bad.out +++ b/test_regress/t/t_dynarray_bad.out @@ -2,6 +2,7 @@ : ... In instance t 15 | a = new [s]; | ^~~ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Internal Error: t/t_dynarray_bad.v:15:16: ../V3Number.cpp:#: Number operation called with non-logic (double or string) argument: '"str"" 15 | a = new [s]; diff --git a/test_regress/t/t_enum_bad_hide.out b/test_regress/t/t_enum_bad_hide.out index 27ce71294..c1fd3b364 100644 --- a/test_regress/t/t_enum_bad_hide.out +++ b/test_regress/t/t_enum_bad_hide.out @@ -4,5 +4,6 @@ t/t_enum_bad_hide.v:7:16: ... Location of original declaration 11 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; | ^~~~~~~~~~ + ... For warning description see https://verilator.org/warn/VARHIDDEN?v=4.201 ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_event_control_unsup.out b/test_regress/t/t_event_control_unsup.out index 03d17ac22..a3fbe9c7a 100644 --- a/test_regress/t/t_event_control_unsup.out +++ b/test_regress/t/t_event_control_unsup.out @@ -3,6 +3,7 @@ : ... Suggest have one timing control statement per procedure, at the top of the procedure 14 | @(clk); | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_event_control_unsup.v:16:7: Unsupported: timing control statement in this location : ... In instance t : ... Suggest have one timing control statement per procedure, at the top of the procedure diff --git a/test_regress/t/t_event_copy.out b/test_regress/t/t_event_copy.out index 3e54190e6..75578639b 100644 --- a/test_regress/t/t_event_copy.out +++ b/test_regress/t/t_event_copy.out @@ -2,6 +2,7 @@ : ... In instance t 100 | e4 = e3; | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_event_copy.v:101:13: Unsupported: assignment of event data type : ... In instance t 101 | e3 = e2; diff --git a/test_regress/t/t_flag_context_bad.out b/test_regress/t/t_flag_context_bad.out index 2fb7fe3ad..118128d94 100644 --- a/test_regress/t/t_flag_context_bad.out +++ b/test_regress/t/t_flag_context_bad.out @@ -1,5 +1,6 @@ %Warning-WIDTH: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. : ... In instance t + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_flag_context_bad.v:9:15: Signal is not used: 'foo' : ... In instance t diff --git a/test_regress/t/t_flag_main_sc_bad.out b/test_regress/t/t_flag_main_sc_bad.out index 13ba2e390..b4d2bbc94 100644 --- a/test_regress/t/t_flag_main_sc_bad.out +++ b/test_regress/t/t_flag_main_sc_bad.out @@ -1,2 +1,3 @@ %Error-UNSUPPORTED: --main not usable with SystemC. Suggest see examples for sc_main(). + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_flag_topmodule_bad.out b/test_regress/t/t_flag_topmodule_bad.out index 181364e4b..0f3d497dd 100644 --- a/test_regress/t/t_flag_topmodule_bad.out +++ b/test_regress/t/t_flag_topmodule_bad.out @@ -1,5 +1,6 @@ %Warning-MULTITOP: t/t_flag_topmodule.v:15:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. + ... For warning description see https://verilator.org/warn/MULTITOP?v=4.201 ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' 7 | module a; diff --git a/test_regress/t/t_flag_werror_bad1.out b/test_regress/t/t_flag_werror_bad1.out index 389d69336..0d65fde0a 100644 --- a/test_regress/t/t_flag_werror_bad1.out +++ b/test_regress/t/t_flag_werror_bad1.out @@ -2,5 +2,6 @@ : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_flag_werror_bad2.out b/test_regress/t/t_flag_werror_bad2.out index 9bf134b8b..ae9811417 100644 --- a/test_regress/t/t_flag_werror_bad2.out +++ b/test_regress/t/t_flag_werror_bad2.out @@ -2,4 +2,5 @@ : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ + ... For error description see https://verilator.org/warn/WIDTH?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_flag_wfatal.out b/test_regress/t/t_flag_wfatal.out index 78410d838..19da7e11a 100644 --- a/test_regress/t/t_flag_wfatal.out +++ b/test_regress/t/t_flag_wfatal.out @@ -2,4 +2,5 @@ : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_for_comma_bad.out b/test_regress/t/t_for_comma_bad.out index 6b5a4f416..f09139918 100644 --- a/test_regress/t/t_for_comma_bad.out +++ b/test_regress/t/t_for_comma_bad.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_for_comma_bad.v:27:23: Unsupported: for loop initialization after the first comma 27 | for (integer a=0, integer b=0; a<1; ) ; | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_for_comma_bad.v:28:23: Unsupported: for loop initialization after the first comma 28 | for (integer a=0, integer b=0; a<1; a=a+1) ; | ^ diff --git a/test_regress/t/t_fork.out b/test_regress/t/t_fork.out index 03e479d9f..6ecddc01a 100644 --- a/test_regress/t/t_fork.out +++ b/test_regress/t/t_fork.out @@ -2,4 +2,5 @@ : ... In instance t 10 | fork : fblk | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_fork_disable.out b/test_regress/t/t_fork_disable.out index 20a700eb3..1e9b60a94 100644 --- a/test_regress/t/t_fork_disable.out +++ b/test_regress/t/t_fork_disable.out @@ -2,6 +2,7 @@ : ... In instance t 12 | fork | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_fork_disable.v:16:7: Unsupported: disable fork statements : ... In instance t 16 | disable fork; diff --git a/test_regress/t/t_func_bad.out b/test_regress/t/t_func_bad.out index 68a2e95ab..bf3079498 100644 --- a/test_regress/t/t_func_bad.out +++ b/test_regress/t/t_func_bad.out @@ -14,6 +14,7 @@ : ... In instance t 11 | x; | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: t/t_func_bad.v:14:17: No such argument 'no_such' in function call to FUNC 'f' : ... In instance t 14 | f(.j(1), .no_such(2)); diff --git a/test_regress/t/t_func_bad2.out b/test_regress/t/t_func_bad2.out index 0666509d5..45ebfd990 100644 --- a/test_regress/t/t_func_bad2.out +++ b/test_regress/t/t_func_bad2.out @@ -2,4 +2,5 @@ : ... In instance t 8 | function recurse; | ^~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_func_bad_width.out b/test_regress/t/t_func_bad_width.out index 8948c688a..257dd5a85 100644 --- a/test_regress/t/t_func_bad_width.out +++ b/test_regress/t/t_func_bad_width.out @@ -2,6 +2,7 @@ : ... In instance t 13 | out = MUX (in); | ^~~ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. : ... In instance t diff --git a/test_regress/t/t_func_const2_bad.out b/test_regress/t/t_func_const2_bad.out index 8efe45a6e..551d44cd7 100644 --- a/test_regress/t/t_func_const2_bad.out +++ b/test_regress/t/t_func_const2_bad.out @@ -1,4 +1,5 @@ %Warning-USERFATAL: "f_add = 15" + ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const2_bad.v:22:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t.b8_a7.c9 diff --git a/test_regress/t/t_func_const3_bad.out b/test_regress/t/t_func_const3_bad.out index 02585e023..6c9c15118 100644 --- a/test_regress/t/t_func_const3_bad.out +++ b/test_regress/t/t_func_const3_bad.out @@ -2,5 +2,6 @@ : ... In instance t.b9k.c9 12 | localparam SOMEP = {BITS{1'b0}}; | ^ + ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=4.201 ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_func_const_bad.out b/test_regress/t/t_func_const_bad.out index 9871a8a45..7ce99926e 100644 --- a/test_regress/t/t_func_const_bad.out +++ b/test_regress/t/t_func_const_bad.out @@ -35,6 +35,7 @@ -Info: "Printing in loop: 1" -Info: "Printing in loop: 2" %Warning-USERFATAL: "Fatal Error" + ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_bad.v:50:24: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal' : ... In instance t diff --git a/test_regress/t/t_func_const_packed_array_bad.out b/test_regress/t/t_func_const_packed_array_bad.out index 25a3580a6..b8f7bd61c 100644 --- a/test_regress/t/t_func_const_packed_array_bad.out +++ b/test_regress/t/t_func_const_packed_array_bad.out @@ -1,4 +1,5 @@ %Warning-USERFATAL: "f_add = 15" + ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_array_bad.v:12:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t diff --git a/test_regress/t/t_func_const_packed_struct_bad.out b/test_regress/t/t_func_const_packed_struct_bad.out index 48e0f996f..ebfcf4d4f 100644 --- a/test_regress/t/t_func_const_packed_struct_bad.out +++ b/test_regress/t/t_func_const_packed_struct_bad.out @@ -1,4 +1,5 @@ %Warning-USERFATAL: "f_add = 15" + ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_struct_bad.v:14:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t diff --git a/test_regress/t/t_func_const_packed_struct_bad2.out b/test_regress/t/t_func_const_packed_struct_bad2.out index 7e6d1dcb6..27f87fb17 100644 --- a/test_regress/t/t_func_const_packed_struct_bad2.out +++ b/test_regress/t/t_func_const_packed_struct_bad2.out @@ -1,4 +1,5 @@ %Warning-USERFATAL: "f_add = 15" + ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_struct_bad2.v:20:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t diff --git a/test_regress/t/t_func_const_struct_bad.out b/test_regress/t/t_func_const_struct_bad.out index 804a7d608..00d82b32d 100644 --- a/test_regress/t/t_func_const_struct_bad.out +++ b/test_regress/t/t_func_const_struct_bad.out @@ -1,4 +1,5 @@ %Warning-USERFATAL: "f_add = 15" + ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_struct_bad.v:17:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t diff --git a/test_regress/t/t_func_impure_bad.out b/test_regress/t/t_func_impure_bad.out index 17a896993..9fb2a10f0 100644 --- a/test_regress/t/t_func_impure_bad.out +++ b/test_regress/t/t_func_impure_bad.out @@ -4,4 +4,5 @@ t/t_func_impure_bad.v:13:7: ... Location of the external reference: 't.sig' 13 | sig = '1; | ^~~ + ... For error description see https://verilator.org/warn/IMPURE?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_func_tasknsvar_bad.out b/test_regress/t/t_func_tasknsvar_bad.out index d7bb3f57c..ffcd633c9 100644 --- a/test_regress/t/t_func_tasknsvar_bad.out +++ b/test_regress/t/t_func_tasknsvar_bad.out @@ -1,6 +1,7 @@ %Error-TASKNSVAR: t/t_func_tasknsvar_bad.v:16:29: Unsupported: Function/task input argument is not simple variable 16 | foo(bus_we_select_from[2]); | ^ + ... For error description see https://verilator.org/warn/TASKNSVAR?v=4.201 %Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): m_varScopep && !m_varScopep->brokeExists() 10 | sig = '1; | ^~~ diff --git a/test_regress/t/t_func_void_bad.out b/test_regress/t/t_func_void_bad.out index 2eaf6b65c..068f830ac 100644 --- a/test_regress/t/t_func_void_bad.out +++ b/test_regress/t/t_func_void_bad.out @@ -1,5 +1,6 @@ %Warning-IGNOREDRETURN: t/t_func_void_bad.v:26:7: Ignoring return value of non-void function (IEEE 1800-2017 13.4.1) 26 | f1(20); | ^~ + ... For warning description see https://verilator.org/warn/IGNOREDRETURN?v=4.201 ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_func_wide_out_bad.out b/test_regress/t/t_func_wide_out_bad.out index 19c2df709..63a6fe26f 100644 --- a/test_regress/t/t_func_wide_out_bad.out +++ b/test_regress/t/t_func_wide_out_bad.out @@ -2,4 +2,5 @@ : ... In instance t 17 | func(msg); | ^~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_fuzz_always_bad.out b/test_regress/t/t_fuzz_always_bad.out index c5691ffd4..d79c7be5c 100644 --- a/test_regress/t/t_fuzz_always_bad.out +++ b/test_regress/t/t_fuzz_always_bad.out @@ -7,4 +7,5 @@ %Error-UNSUPPORTED: t/t_fuzz_always_bad.v:10:14: Unsupported: Complex statement in sensitivity list 10 | always @ c.a c:h; | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_fuzz_genintf_bad.out b/test_regress/t/t_fuzz_genintf_bad.out index e9ecf42b4..485e7289b 100644 --- a/test_regress/t/t_fuzz_genintf_bad.out +++ b/test_regress/t/t_fuzz_genintf_bad.out @@ -2,6 +2,7 @@ : ... In instance t 24 | j.e(0), | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Internal Error: t/t_fuzz_genintf_bad.v:24:11: ../V3Width.cpp:#: Unlinked pin data type : ... In instance t 24 | j.e(0), diff --git a/test_regress/t/t_fuzz_triand_bad.out b/test_regress/t/t_fuzz_triand_bad.out index c143c25ba..3343c190b 100644 --- a/test_regress/t/t_fuzz_triand_bad.out +++ b/test_regress/t/t_fuzz_triand_bad.out @@ -2,6 +2,7 @@ : ... In instance t 8 | tri g=g.and.g; | ^~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Internal Error: t/t_fuzz_triand_bad.v:8:12: ../V3Width.cpp:#: Unlinked data type : ... In instance t 8 | tri g=g.and.g; diff --git a/test_regress/t/t_gen_cond_bitrange_bad.out b/test_regress/t/t_gen_cond_bitrange_bad.out index 0c77f2e84..f8856e188 100644 --- a/test_regress/t/t_gen_cond_bitrange_bad.out +++ b/test_regress/t/t_gen_cond_bitrange_bad.out @@ -2,6 +2,7 @@ : ... In instance t.i_test_gen 58 | if ((g < (SIZE + 1)) && MASK[g]) begin | ^ + ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70:32: Selection index out of range: 2:2 outside 1:0 : ... In instance t.i_test_gen diff --git a/test_regress/t/t_gen_defparam_unsup_bad.out b/test_regress/t/t_gen_defparam_unsup_bad.out index c876f67af..c6af09329 100644 --- a/test_regress/t/t_gen_defparam_unsup_bad.out +++ b/test_regress/t/t_gen_defparam_unsup_bad.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_gen_defparam_unsup_bad.v:9:16: Unsupported: defparam with more than one dot 9 | defparam a.b.W = 3; | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: t/t_gen_defparam_unsup_bad.v:9:17: syntax error, unexpected IDENTIFIER, expecting ',' or ';' 9 | defparam a.b.W = 3; | ^ diff --git a/test_regress/t/t_generate_fatal_bad.out b/test_regress/t/t_generate_fatal_bad.out index c23052748..f35ff52e7 100644 --- a/test_regress/t/t_generate_fatal_bad.out +++ b/test_regress/t/t_generate_fatal_bad.out @@ -1,4 +1,5 @@ %Warning-USERFATAL: "boom" + ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst diff --git a/test_regress/t/t_hier_block1_bad.out b/test_regress/t/t_hier_block1_bad.out index ba3f864b1..beffcd4ec 100644 --- a/test_regress/t/t_hier_block1_bad.out +++ b/test_regress/t/t_hier_block1_bad.out @@ -3,6 +3,7 @@ ... Suggest remove verilator hier_block on this module 15 | module t ( | ^ + ... For warning description see https://verilator.org/warn/HIERBLOCK?v=4.201 ... Use "/* verilator lint_off HIERBLOCK */" and lint_on around source to disable this message. %Error: t/t_hier_block1_bad.v:44:32: Modport cannot be used at the hierarchical block boundary : ... In instance t.i_sub1 diff --git a/test_regress/t/t_hierarchy_identifier_bad.out b/test_regress/t/t_hierarchy_identifier_bad.out index 35817198e..3a82d7ef6 100644 --- a/test_regress/t/t_hierarchy_identifier_bad.out +++ b/test_regress/t/t_hierarchy_identifier_bad.out @@ -1,6 +1,7 @@ %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:34:10: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' 34 | end : if_cnt_finish_bad | ^~~~~~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/ENDLABEL?v=4.201 ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message. %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:40:10: End label 'generate_for_bad' does not match begin label 'generate_for' 40 | end : generate_for_bad diff --git a/test_regress/t/t_increment_bad.out b/test_regress/t/t_increment_bad.out index 1c07b5c25..41c181a17 100644 --- a/test_regress/t/t_increment_bad.out +++ b/test_regress/t/t_increment_bad.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_increment_bad.v:15:31: Unsupported: Incrementation in this context. 15 | if (0 && test_string[pos++] != "e"); | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_increment_bad.v:16:19: Unsupported: Incrementation in this context. 16 | if (1 || pos-- != 1); | ^~ diff --git a/test_regress/t/t_initial_dlyass_bad.out b/test_regress/t/t_initial_dlyass_bad.out index 315854b57..457395681 100644 --- a/test_regress/t/t_initial_dlyass_bad.out +++ b/test_regress/t/t_initial_dlyass_bad.out @@ -2,6 +2,7 @@ : ... Suggest blocking assignments (=) 18 | a <= 22; | ^~ + ... For warning description see https://verilator.org/warn/INITIALDLY?v=4.201 ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. %Warning-INITIALDLY: t/t_initial_dlyass.v:19:9: Delayed assignments (<=) in initial or final block : ... Suggest blocking assignments (=) diff --git a/test_regress/t/t_inst_missing_bad.out b/test_regress/t/t_inst_missing_bad.out index 38937a462..9bcc8c3a3 100644 --- a/test_regress/t/t_inst_missing_bad.out +++ b/test_regress/t/t_inst_missing_bad.out @@ -1,6 +1,7 @@ %Warning-PINNOCONNECT: t/t_inst_missing_bad.v:9:22: Cell pin is not connected: '__pinNumber2' 9 | sub sub (.ok(ok), , .nc()); | ^ + ... For warning description see https://verilator.org/warn/PINNOCONNECT?v=4.201 ... Use "/* verilator lint_off PINNOCONNECT */" and lint_on around source to disable this message. %Warning-PINCONNECTEMPTY: t/t_inst_missing_bad.v:9:25: Cell pin connected by name with empty reference: 'nc' 9 | sub sub (.ok(ok), , .nc()); diff --git a/test_regress/t/t_inst_overwide_bad.out b/test_regress/t/t_inst_overwide_bad.out index ba813dbf5..1faa3842d 100644 --- a/test_regress/t/t_inst_overwide_bad.out +++ b/test_regress/t/t_inst_overwide_bad.out @@ -2,6 +2,7 @@ : ... In instance t 23 | .outy_w92 (outc_w30), | ^~~~~~~~ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. : ... In instance t diff --git a/test_regress/t/t_inst_pin_realnreal.out b/test_regress/t/t_inst_pin_realnreal.out index 34eade000..81ab9079e 100755 --- a/test_regress/t/t_inst_pin_realnreal.out +++ b/test_regress/t/t_inst_pin_realnreal.out @@ -2,4 +2,5 @@ : ... In instance t.netlist 51 | pga_model pga0(.in, .gain, .out(pga_out)); | ^~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse2_bad.out b/test_regress/t/t_inst_recurse2_bad.out index dbd22cb94..56c231a8e 100644 --- a/test_regress/t/t_inst_recurse2_bad.out +++ b/test_regress/t/t_inst_recurse2_bad.out @@ -2,4 +2,5 @@ : ... In instance t.looped.looped 18 | module looped ( ); | ^~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse_bad.out b/test_regress/t/t_inst_recurse_bad.out index 68085b345..71d014671 100644 --- a/test_regress/t/t_inst_recurse_bad.out +++ b/test_regress/t/t_inst_recurse_bad.out @@ -2,4 +2,5 @@ ... note: self-recursion (module instantiating itself directly) is supported. 18 | module looped ( ); | ^~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_interface_array_nocolon_bad.out b/test_regress/t/t_interface_array_nocolon_bad.out index 546031d0c..e20652d3d 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.out +++ b/test_regress/t/t_interface_array_nocolon_bad.out @@ -2,6 +2,7 @@ : ... In instance t 26 | foo_intf foos [N] (.x(X)); | ^ + ... For warning description see https://verilator.org/warn/LITENDIAN?v=4.201 ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian instance range connecting to vector: left < right of instance range: [1:3] : ... In instance t diff --git a/test_regress/t/t_interface_top_bad.out b/test_regress/t/t_interface_top_bad.out index 9ff12283c..198d9832b 100644 --- a/test_regress/t/t_interface_top_bad.out +++ b/test_regress/t/t_interface_top_bad.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_interface_top_bad.v:17:19: Unsupported: Interfaced port on top level module 17 | ifc.counter_mp c_data | ^~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: t/t_interface_top_bad.v:17:4: Parent instance's interface is not found: 'ifc' 17 | ifc.counter_mp c_data | ^~~ diff --git a/test_regress/t/t_interface_typedef.out b/test_regress/t/t_interface_typedef.out index 73fe2430f..7780462e8 100644 --- a/test_regress/t/t_interface_typedef.out +++ b/test_regress/t/t_interface_typedef.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_interface_typedef.v:46:4: Unsupported: SystemVerilog 2005 typedef in this context 46 | typedef ifc_if.struct_t struct_t; | ^~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: t/t_interface_typedef.v:51:16: syntax error, unexpected IDENTIFIER 51 | struct_t substruct; | ^~~~~~~~~ diff --git a/test_regress/t/t_lint_always_comb_bad.out b/test_regress/t/t_lint_always_comb_bad.out index 7f198d9e9..190e629fa 100644 --- a/test_regress/t/t_lint_always_comb_bad.out +++ b/test_regress/t/t_lint_always_comb_bad.out @@ -2,6 +2,7 @@ : ... In instance t 29 | temp1 = 'h0; | ^~~~~ + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1' : ... In instance t 31 | temp1 = (temp1_d1r - 'h1); diff --git a/test_regress/t/t_lint_blksync_bad.out b/test_regress/t/t_lint_blksync_bad.out index 3a5104638..ec1d772e9 100644 --- a/test_regress/t/t_lint_blksync_bad.out +++ b/test_regress/t/t_lint_blksync_bad.out @@ -2,6 +2,7 @@ : ... Suggest delayed assignments (<=) 24 | sync_blk = 1'b1; | ^ + ... For warning description see https://verilator.org/warn/BLKSEQ?v=4.201 ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. %Warning-COMBDLY: t/t_lint_blksync_bad.v:31:18: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) diff --git a/test_regress/t/t_lint_bsspace_bad.out b/test_regress/t/t_lint_bsspace_bad.out index e7d583699..a201e346f 100644 --- a/test_regress/t/t_lint_bsspace_bad.out +++ b/test_regress/t/t_lint_bsspace_bad.out @@ -1,6 +1,7 @@ %Warning-BSSPACE: t/t_lint_bsspace_bad.v:10:21: Backslash followed by whitespace, perhaps the whitespace is accidental? 10 | `define FOO blak \ | ^ + ... For warning description see https://verilator.org/warn/BSSPACE?v=4.201 ... Use "/* verilator lint_off BSSPACE */" and lint_on around source to disable this message. %Error: t/t_lint_bsspace_bad.v:11:4: syntax error, unexpected IDENTIFIER 11 | blak diff --git a/test_regress/t/t_lint_caseincomplete_bad.out b/test_regress/t/t_lint_caseincomplete_bad.out index ab527489b..270deb3b8 100644 --- a/test_regress/t/t_lint_caseincomplete_bad.out +++ b/test_regress/t/t_lint_caseincomplete_bad.out @@ -1,5 +1,6 @@ %Warning-CASEINCOMPLETE: t/t_lint_caseincomplete_bad.v:15:7: Case values incompletely covered (example pattern 0x1) 15 | case (i) | ^~~~ + ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=4.201 ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_cmpconst_bad.out b/test_regress/t/t_lint_cmpconst_bad.out index a2c156ebf..dd681d790 100644 --- a/test_regress/t/t_lint_cmpconst_bad.out +++ b/test_regress/t/t_lint_cmpconst_bad.out @@ -2,5 +2,6 @@ : ... In instance t 13 | if (uns > 3'b111) $stop; | ^ + ... For warning description see https://verilator.org/warn/CMPCONST?v=4.201 ... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_colonplus_bad.out b/test_regress/t/t_lint_colonplus_bad.out index 745bf6ae6..c9a14f7fe 100644 --- a/test_regress/t/t_lint_colonplus_bad.out +++ b/test_regress/t/t_lint_colonplus_bad.out @@ -1,5 +1,6 @@ %Warning-COLONPLUS: t/t_lint_colonplus_bad.v:13:25: Perhaps instead of ':+' the intent was '+:'? 13 | output [2:1] z = r[2 :+ 1]; | ^~ + ... For warning description see https://verilator.org/warn/COLONPLUS?v=4.201 ... Use "/* verilator lint_off COLONPLUS */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_declfilename_bad.out b/test_regress/t/t_lint_declfilename_bad.out index 9f9a150d7..781bed362 100644 --- a/test_regress/t/t_lint_declfilename_bad.out +++ b/test_regress/t/t_lint_declfilename_bad.out @@ -1,5 +1,6 @@ %Warning-DECLFILENAME: t/t_lint_declfilename.v:7:8: Filename 't_lint_declfilename' does not match MODULE name: 't' 7 | module t; | ^ + ... For warning description see https://verilator.org/warn/DECLFILENAME?v=4.201 ... Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_defparam_bad.out b/test_regress/t/t_lint_defparam_bad.out index 15a90af01..92e0c2afe 100644 --- a/test_regress/t/t_lint_defparam_bad.out +++ b/test_regress/t/t_lint_defparam_bad.out @@ -2,5 +2,6 @@ : ... Suggest use instantiation with #(.P(...etc...)) 10 | defparam sub.P = 2; | ^ + ... For warning description see https://verilator.org/warn/DEFPARAM?v=4.201 ... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_eofline_bad.out b/test_regress/t/t_lint_eofline_bad.out index ee6a52af0..fb29efe09 100644 --- a/test_regress/t/t_lint_eofline_bad.out +++ b/test_regress/t/t_lint_eofline_bad.out @@ -1,5 +1,6 @@ %Warning-EOFNEWLINE: obj_vlt/t_lint_eofline_bad/t_lint_eofline_bad.v:4:10: Missing newline at end of file (POSIX 3.206). : ... Suggest add newline. 4 | endmodule | ^ + ... For warning description see https://verilator.org/warn/EOFNEWLINE?v=4.201 ... Use "/* verilator lint_off EOFNEWLINE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_ifdepth_bad.out b/test_regress/t/t_lint_ifdepth_bad.out index 494d7100b..7ebbe3ae0 100644 --- a/test_regress/t/t_lint_ifdepth_bad.out +++ b/test_regress/t/t_lint_ifdepth_bad.out @@ -2,5 +2,6 @@ : ... In instance t 22 | else if (value==11) begin end | ^~ + ... For warning description see https://verilator.org/warn/IFDEPTH?v=4.201 ... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_bad.out b/test_regress/t/t_lint_implicit_bad.out index 111126806..8b6f56209 100644 --- a/test_regress/t/t_lint_implicit_bad.out +++ b/test_regress/t/t_lint_implicit_bad.out @@ -1,6 +1,7 @@ %Warning-IMPLICIT: t/t_lint_implicit.v:11:11: Signal definition not found, creating implicitly: 'b' 11 | assign b = 1'b1; | ^ + ... For warning description see https://verilator.org/warn/IMPLICIT?v=4.201 ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Warning-IMPLICIT: t/t_lint_implicit.v:13:14: Signal definition not found, creating implicitly: 'nt0' 13 | or OR0 (nt0, a, b); diff --git a/test_regress/t/t_lint_implicit_def_bad.out b/test_regress/t/t_lint_implicit_def_bad.out index c6248d083..db0db28dd 100644 --- a/test_regress/t/t_lint_implicit_def_bad.out +++ b/test_regress/t/t_lint_implicit_def_bad.out @@ -1,6 +1,7 @@ %Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:13:11: Signal definition not found, creating implicitly: 'imp_warn' 13 | assign imp_warn = 1'b1; | ^~~~~~~~ + ... For warning description see https://verilator.org/warn/IMPLICIT?v=4.201 ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: t/t_lint_implicit_def_bad.v:18:11: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err' 18 | assign imp_err = 1'b1; diff --git a/test_regress/t/t_lint_import_name2_bad.out b/test_regress/t/t_lint_import_name2_bad.out index 2bcdce56d..dff3c722b 100644 --- a/test_regress/t/t_lint_import_name2_bad.out +++ b/test_regress/t/t_lint_import_name2_bad.out @@ -1,6 +1,7 @@ %Error-PKGNODECL: t/t_lint_import_name2_bad.v:7:8: Package/class 'missing' not found, and needs to be predeclared (IEEE 1800-2017 26.3) 7 | import missing::sigs; | ^~~~~~~ + ... For error description see https://verilator.org/warn/PKGNODECL?v=4.201 %Error: t/t_lint_import_name2_bad.v:7:8: Importing from missing package 'missing' 7 | import missing::sigs; | ^~~~~~~ diff --git a/test_regress/t/t_lint_importstar_bad.out b/test_regress/t/t_lint_importstar_bad.out index 7eaf12bc7..73618c306 100644 --- a/test_regress/t/t_lint_importstar_bad.out +++ b/test_regress/t/t_lint_importstar_bad.out @@ -1,5 +1,6 @@ %Warning-IMPORTSTAR: t/t_lint_importstar_bad.v:11:12: Import::* in $unit scope may pollute global namespace 11 | import defs::*; | ^~ + ... For warning description see https://verilator.org/warn/IMPORTSTAR?v=4.201 ... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_incabspath_bad.out b/test_regress/t/t_lint_incabspath_bad.out index c90e6372b..34f4f9b1e 100644 --- a/test_regress/t/t_lint_incabspath_bad.out +++ b/test_regress/t/t_lint_incabspath_bad.out @@ -1,5 +1,6 @@ %Warning-INCABSPATH: t/t_lint_incabspath.v:7:10: Suggest `include with absolute path be made relative, and use +include: /dev/null 7 | `include "/dev/null" | ^~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/INCABSPATH?v=4.201 ... Use "/* verilator lint_off INCABSPATH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_infinite.out b/test_regress/t/t_lint_infinite.out index 04de98f39..afbbe8b41 100644 --- a/test_regress/t/t_lint_infinite.out +++ b/test_regress/t/t_lint_infinite.out @@ -2,6 +2,7 @@ : ... In instance t 10 | forever begin end | ^~~~~~~ + ... For warning description see https://verilator.org/warn/INFINITELOOP?v=4.201 ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. %Warning-INFINITELOOP: t/t_lint_infinite.v:12:7: Infinite loop (condition always true) : ... In instance t diff --git a/test_regress/t/t_lint_input_eq_bad.out b/test_regress/t/t_lint_input_eq_bad.out index f189a6b88..0ed24b966 100644 --- a/test_regress/t/t_lint_input_eq_bad.out +++ b/test_regress/t/t_lint_input_eq_bad.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_lint_input_eq_bad.v:10:15: Unsupported: Default value on module input: 'i2' 10 | input wire i2 = i | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad.out b/test_regress/t/t_lint_latch_bad.out index eeeb70548..2cd7ce388 100644 --- a/test_regress/t/t_lint_latch_bad.out +++ b/test_regress/t/t_lint_latch_bad.out @@ -1,6 +1,7 @@ %Warning-NOLATCH: t/t_lint_latch_bad.v:17:4: No latches detected in always_latch block 17 | always_latch begin | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/NOLATCH?v=4.201 ... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message. %Warning-COMBDLY: t/t_lint_latch_bad.v:25:10: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) diff --git a/test_regress/t/t_lint_latch_bad_2.out b/test_regress/t/t_lint_latch_bad_2.out index ea37dddf6..c909baf38 100644 --- a/test_regress/t/t_lint_latch_bad_2.out +++ b/test_regress/t/t_lint_latch_bad_2.out @@ -2,5 +2,6 @@ : ... Suggest use of always_latch for intentional latches 11 | always @(a or b) | ^~~~~~ + ... For warning description see https://verilator.org/warn/LATCH?v=4.201 ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad_3.out b/test_regress/t/t_lint_latch_bad_3.out index 9b132b899..809fea09a 100644 --- a/test_regress/t/t_lint_latch_bad_3.out +++ b/test_regress/t/t_lint_latch_bad_3.out @@ -2,6 +2,7 @@ : ... Suggest use of always_latch for intentional latches 18 | always @(reset or en or a or b) | ^~~~~~ + ... For warning description see https://verilator.org/warn/LATCH?v=4.201 ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Warning-COMBDLY: t/t_lint_latch_bad_3.v:70:12: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) diff --git a/test_regress/t/t_lint_literal_bad.out b/test_regress/t/t_lint_literal_bad.out index 88f210ea5..077054d07 100644 --- a/test_regress/t/t_lint_literal_bad.out +++ b/test_regress/t/t_lint_literal_bad.out @@ -1,5 +1,6 @@ %Warning-WIDTH: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256 10 | localparam the_localparam = 8'd256; | ^~~~~~ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_multidriven_bad.out b/test_regress/t/t_lint_multidriven_bad.out index 5839d7898..019c1db6f 100644 --- a/test_regress/t/t_lint_multidriven_bad.out +++ b/test_regress/t/t_lint_multidriven_bad.out @@ -5,6 +5,7 @@ t/t_lint_multidriven_bad.v:24:7: ... Location of other driving block 24 | mem[a0] <= d0; | ^~~ + ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=4.201 ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:22: Signal has multiple driving blocks with different clocking: 'out2' t/t_lint_multidriven_bad.v:35:7: ... Location of first driving block diff --git a/test_regress/t/t_lint_nolatch_bad.out b/test_regress/t/t_lint_nolatch_bad.out index 2cdc19da9..dd733be55 100644 --- a/test_regress/t/t_lint_nolatch_bad.out +++ b/test_regress/t/t_lint_nolatch_bad.out @@ -1,5 +1,6 @@ %Warning-NOLATCH: t/t_lint_nolatch_bad.v:11:4: No latches detected in always_latch block 11 | always_latch @(a or b) | ^~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/NOLATCH?v=4.201 ... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_nullport.out b/test_regress/t/t_lint_nullport.out index f35a775cd..f784bfd69 100644 --- a/test_regress/t/t_lint_nullport.out +++ b/test_regress/t/t_lint_nullport.out @@ -1,6 +1,7 @@ %Warning-NULLPORT: t/t_lint_nullport.v:23:13: Null port on module (perhaps extraneous comma) 23 | module t5(a,); | ^ + ... For warning description see https://verilator.org/warn/NULLPORT?v=4.201 ... Use "/* verilator lint_off NULLPORT */" and lint_on around source to disable this message. %Warning-NULLPORT: t/t_lint_nullport.v:27:13: Null port on module (perhaps extraneous comma) 27 | module t6(a,,); diff --git a/test_regress/t/t_lint_once_bad.out b/test_regress/t/t_lint_once_bad.out index fd18cfd0d..f2faa4809 100644 --- a/test_regress/t/t_lint_once_bad.out +++ b/test_regress/t/t_lint_once_bad.out @@ -2,6 +2,7 @@ : ... In instance t.sub3 19 | reg [A:0] unus1; reg [A:0] unus2; | ^~~~~ + ... For warning description see https://verilator.org/warn/UNUSED?v=4.201 ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_lint_once_bad.v:19:34: Signal is not driven, nor used: 'unus2' : ... In instance t.sub3 diff --git a/test_regress/t/t_lint_pindup_bad.out b/test_regress/t/t_lint_pindup_bad.out index a34830565..06f37dba0 100644 --- a/test_regress/t/t_lint_pindup_bad.out +++ b/test_regress/t/t_lint_pindup_bad.out @@ -1,6 +1,7 @@ %Warning-PINMISSING: t/t_lint_pindup_bad.v:19:4: Cell has missing pin: 'exists' 19 | sub (.o(o), | ^~~ + ... For warning description see https://verilator.org/warn/PINMISSING?v=4.201 ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_lint_pindup_bad.v:21:10: Duplicate pin connection: 'i' 21 | .i(i2), diff --git a/test_regress/t/t_lint_pinnotfound_bad.out b/test_regress/t/t_lint_pinnotfound_bad.out index e10eaa161..ddab6577d 100644 --- a/test_regress/t/t_lint_pinnotfound_bad.out +++ b/test_regress/t/t_lint_pinnotfound_bad.out @@ -1,6 +1,7 @@ %Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:12:13: Pin not found: 'x' 12 | b b_inst1 (.x(1'b0)); | ^ + ... For error description see https://verilator.org/warn/PINNOTFOUND?v=4.201 %Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:13:6: Parameter pin not found: 'PX' 13 | b #(.PX(1'b0)) b_inst2 (); | ^~ diff --git a/test_regress/t/t_lint_pkg_colon_bad.out b/test_regress/t/t_lint_pkg_colon_bad.out index f6a9c2149..3b7702707 100644 --- a/test_regress/t/t_lint_pkg_colon_bad.out +++ b/test_regress/t/t_lint_pkg_colon_bad.out @@ -1,6 +1,7 @@ %Error-PKGNODECL: t/t_lint_pkg_colon_bad.v:7:17: Package/class 'mispkg' not found, and needs to be predeclared (IEEE 1800-2017 26.3) 7 | module t (input mispkg::foo_t a); | ^~~~~~ + ... For error description see https://verilator.org/warn/PKGNODECL?v=4.201 %Error: t/t_lint_pkg_colon_bad.v:7:25: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER 7 | module t (input mispkg::foo_t a); | ^~~~~ diff --git a/test_regress/t/t_lint_realcvt_bad.out b/test_regress/t/t_lint_realcvt_bad.out index b21a18477..a240a3eb0 100644 --- a/test_regress/t/t_lint_realcvt_bad.out +++ b/test_regress/t/t_lint_realcvt_bad.out @@ -1,5 +1,6 @@ %Warning-REALCVT: t/t_lint_realcvt_bad.v:10:11: Implicit conversion of real to integer 10 | i = 23.2; | ^~~~ + ... For warning description see https://verilator.org/warn/REALCVT?v=4.201 ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_repeat_bad.out b/test_regress/t/t_lint_repeat_bad.out index 234280873..80c9ae7ca 100644 --- a/test_regress/t/t_lint_repeat_bad.out +++ b/test_regress/t/t_lint_repeat_bad.out @@ -2,5 +2,6 @@ : ... In instance t.sub2 18 | wire [0:0] b = a; | ^ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_restore_bad.out b/test_regress/t/t_lint_restore_bad.out index b01c1a699..7af6654bb 100644 --- a/test_regress/t/t_lint_restore_bad.out +++ b/test_regress/t/t_lint_restore_bad.out @@ -2,5 +2,6 @@ : ... In instance t 19 | initial five = 64'h1; | ^ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_rsvd_bad.out b/test_regress/t/t_lint_rsvd_bad.out index c2fd258da..ceba8abfa 100644 --- a/test_regress/t/t_lint_rsvd_bad.out +++ b/test_regress/t/t_lint_rsvd_bad.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:7:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config' 7 | config cfgBad; | ^~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: t/t_lint_rsvd_bad.v:7:8: syntax error, unexpected IDENTIFIER 7 | config cfgBad; | ^~~~~~ diff --git a/test_regress/t/t_lint_setout_bad.out b/test_regress/t/t_lint_setout_bad.out index 2ed7227db..7271445c3 100644 --- a/test_regress/t/t_lint_setout_bad.out +++ b/test_regress/t/t_lint_setout_bad.out @@ -2,4 +2,5 @@ : ... In instance t 17 | .cpu_if_timeout(1'b0) | ^~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/PORTSHORT?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_lint_setout_bad_noinl.out b/test_regress/t/t_lint_setout_bad_noinl.out index 2ed7227db..7271445c3 100644 --- a/test_regress/t/t_lint_setout_bad_noinl.out +++ b/test_regress/t/t_lint_setout_bad_noinl.out @@ -2,4 +2,5 @@ : ... In instance t 17 | .cpu_if_timeout(1'b0) | ^~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/PORTSHORT?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_lint_subout_bad.out b/test_regress/t/t_lint_subout_bad.out index 32c40ece4..fa5b64ae6 100644 --- a/test_regress/t/t_lint_subout_bad.out +++ b/test_regress/t/t_lint_subout_bad.out @@ -2,6 +2,7 @@ : ... In instance t 12 | sub sub1(.out({32'b0, sig})); | ^~~ + ... For error description see https://verilator.org/warn/PORTSHORT?v=4.201 %Error-PORTSHORT: t/t_lint_subout_bad.v:13:14: Output port is connected to a constant pin, electrical short : ... In instance t 13 | sub sub2(.out({32'b1, sig})); diff --git a/test_regress/t/t_lint_syncasyncnet_bad.out b/test_regress/t/t_lint_syncasyncnet_bad.out index dd4ca5627..8508061a7 100644 --- a/test_regress/t/t_lint_syncasyncnet_bad.out +++ b/test_regress/t/t_lint_syncasyncnet_bad.out @@ -5,5 +5,6 @@ t/t_lint_syncasyncnet_bad.v:34:14: ... Location of sync usage 34 | q2 <= (rst_both_l) ? d : 1'b0; | ^~~~~~~~~~ + ... For warning description see https://verilator.org/warn/SYNCASYNCNET?v=4.201 ... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_unsigned_bad.out b/test_regress/t/t_lint_unsigned_bad.out index 861d13a58..8fcfa685a 100644 --- a/test_regress/t/t_lint_unsigned_bad.out +++ b/test_regress/t/t_lint_unsigned_bad.out @@ -2,5 +2,6 @@ : ... In instance t 13 | if (uns < 0) $stop; | ^ + ... For warning description see https://verilator.org/warn/UNSIGNED?v=4.201 ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_unused_bad.out b/test_regress/t/t_lint_unused_bad.out index 745ca8336..2bc76ead2 100644 --- a/test_regress/t/t_lint_unused_bad.out +++ b/test_regress/t/t_lint_unused_bad.out @@ -2,6 +2,7 @@ : ... In instance t.sub 17 | wire [5:0] assunu1 = 0; | ^~~~~~~ + ... For warning description see https://verilator.org/warn/UNUSED?v=4.201 ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. %Warning-UNDRIVEN: t/t_lint_unused_bad.v:21:17: Bits of signal are not driven: 'udrb2'[14:13,11] : ... In instance t.sub diff --git a/test_regress/t/t_lint_unused_iface_bad.out b/test_regress/t/t_lint_unused_iface_bad.out index 917ccb9fe..691d50820 100644 --- a/test_regress/t/t_lint_unused_iface_bad.out +++ b/test_regress/t/t_lint_unused_iface_bad.out @@ -2,6 +2,7 @@ : ... In instance t.sub 8 | logic sig_udrv; | ^~~~~~~~ + ... For warning description see https://verilator.org/warn/UNDRIVEN?v=4.201 ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_lint_unused_iface_bad.v:9:10: Signal is not used: 'sig_uusd' : ... In instance t.sub diff --git a/test_regress/t/t_lint_width_bad.out b/test_regress/t/t_lint_width_bad.out index fc4484be1..9fb7e5660 100644 --- a/test_regress/t/t_lint_width_bad.out +++ b/test_regress/t/t_lint_width_bad.out @@ -2,6 +2,7 @@ : ... In instance t 17 | localparam [3:0] XS = 'hx; | ^~ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_lint_width_bad.v:47:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. : ... In instance t.p4 diff --git a/test_regress/t/t_lint_width_docs_bad.out b/test_regress/t/t_lint_width_docs_bad.out index 132dc2e6d..91057def8 100644 --- a/test_regress/t/t_lint_width_docs_bad.out +++ b/test_regress/t/t_lint_width_docs_bad.out @@ -2,5 +2,6 @@ : ... In instance t 10 | wire int rd_value = array[rd_addr]; | ^ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_genfor_bad.out b/test_regress/t/t_lint_width_genfor_bad.out index a814e38a8..915fc6c3c 100644 --- a/test_regress/t/t_lint_width_genfor_bad.out +++ b/test_regress/t/t_lint_width_genfor_bad.out @@ -2,6 +2,7 @@ : ... In instance t 25 | rg = g; | ^ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. : ... In instance t diff --git a/test_regress/t/t_math_countbits_bad.out b/test_regress/t/t_math_countbits_bad.out index def07da32..693cd2dfa 100755 --- a/test_regress/t/t_math_countbits_bad.out +++ b/test_regress/t/t_math_countbits_bad.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_math_countbits_bad.v:14:54: Unsupported: $countbits with more than 3 control fields 14 | assign count = $countbits(32'h123456, '0, '1, 'x, 'z); | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_math_shortreal_unsup_bad.out b/test_regress/t/t_math_shortreal_unsup_bad.out index b73e9626c..c3401572b 100644 --- a/test_regress/t/t_math_shortreal_unsup_bad.out +++ b/test_regress/t/t_math_shortreal_unsup_bad.out @@ -1,5 +1,6 @@ %Warning-SHORTREAL: t/t_math_shortreal_unsup_bad.v:9:4: Unsupported: shortreal being promoted to real (suggest use real instead) 9 | shortreal s; | ^~~~~~~~~ + ... For warning description see https://verilator.org/warn/SHORTREAL?v=4.201 ... Use "/* verilator lint_off SHORTREAL */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_math_wide_bad.out b/test_regress/t/t_math_wide_bad.out index 1c4516c1d..e30757c0f 100644 --- a/test_regress/t/t_math_wide_bad.out +++ b/test_regress/t/t_math_wide_bad.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_math_wide_bad.v:22:18: Unsupported: operator POWSS operator of 576 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 22 | assign z2 = a ** 3; | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_math_wide_bad.v:23:15: Unsupported: operator ISTORD operator of 64 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 23 | assign r = real'(a); | ^~~~ diff --git a/test_regress/t/t_mem_multi_ref_bad.out b/test_regress/t/t_mem_multi_ref_bad.out index 558de331d..8ad024efe 100644 --- a/test_regress/t/t_mem_multi_ref_bad.out +++ b/test_regress/t/t_mem_multi_ref_bad.out @@ -6,6 +6,7 @@ : ... In instance t 15 | dimn[1:0] = 0; | ^ + ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: t/t_mem_multi_ref_bad.v:16:14: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... In instance t diff --git a/test_regress/t/t_metacmt_onoff.out b/test_regress/t/t_metacmt_onoff.out index 7001223a5..46ae4fc1c 100644 --- a/test_regress/t/t_metacmt_onoff.out +++ b/test_regress/t/t_metacmt_onoff.out @@ -2,6 +2,7 @@ : ... In instance t 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; | ^ + ... For warning description see https://verilator.org/warn/LITENDIAN?v=4.201 ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-LITENDIAN: t/t_metacmt_onoff.v:8:109: Little bit endian vector: left < right of bit range: [0:3] : ... In instance t diff --git a/test_regress/t/t_mod_dup_bad.out b/test_regress/t/t_mod_dup_bad.out index 87b31425b..d194b4b22 100644 --- a/test_regress/t/t_mod_dup_bad.out +++ b/test_regress/t/t_mod_dup_bad.out @@ -4,6 +4,7 @@ t/t_mod_dup_bad.v:7:8: ... Location of original declaration 7 | module a(); | ^ + ... For warning description see https://verilator.org/warn/MODDUP?v=4.201 ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. %Warning-MULTITOP: t/t_mod_dup_bad.v:17:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. diff --git a/test_regress/t/t_mod_interface_array3.out b/test_regress/t/t_mod_interface_array3.out index 34ca8e708..1d4e3404f 100644 --- a/test_regress/t/t_mod_interface_array3.out +++ b/test_regress/t/t_mod_interface_array3.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_mod_interface_array3.v:25:20: Unsupported: Multidimensional instances/interfaces. 25 | a_if iface [2:0][1:0]; | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_mod_interface_array3.v:27:18: Unsupported: Multidimensional instances/interfaces. 27 | sub i_sub[2:0][1:0] (.s(str)); | ^ diff --git a/test_regress/t/t_multitop_sig_bad.out b/test_regress/t/t_multitop_sig_bad.out index b905115db..9d1b70468 100644 --- a/test_regress/t/t_multitop_sig_bad.out +++ b/test_regress/t/t_multitop_sig_bad.out @@ -1,5 +1,6 @@ %Warning-MULTITOP: t/t_multitop_sig.v:15:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. + ... For warning description see https://verilator.org/warn/MULTITOP?v=4.201 ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' 7 | module a(in, out); diff --git a/test_regress/t/t_order_blkandnblk_bad.out b/test_regress/t/t_order_blkandnblk_bad.out index 67d333e77..387bf9d05 100644 --- a/test_regress/t/t_order_blkandnblk_bad.out +++ b/test_regress/t/t_order_blkandnblk_bad.out @@ -7,4 +7,5 @@ t/t_order_blkandnblk_bad.v:22:6: ... Location of nonblocking assignment 22 | array[1] <= array[0]; | ^~~~~ + ... For error description see https://verilator.org/warn/BLKANDNBLK?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_order_blkloopinit_bad.out b/test_regress/t/t_order_blkloopinit_bad.out index ec6d432f5..dc78ecf0b 100644 --- a/test_regress/t/t_order_blkloopinit_bad.out +++ b/test_regress/t/t_order_blkloopinit_bad.out @@ -1,4 +1,5 @@ %Error-BLKLOOPINIT: t/t_order_blkloopinit_bad.v:21:19: Unsupported: Delayed assignment to array inside for loops (non-delayed is ok - see docs) 21 | array[i] <= 0; | ^~ + ... For error description see https://verilator.org/warn/BLKLOOPINIT?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_order_clkinst_bad.out b/test_regress/t/t_order_clkinst_bad.out index 2e369155a..4d9f3562d 100644 --- a/test_regress/t/t_order_clkinst_bad.out +++ b/test_regress/t/t_order_clkinst_bad.out @@ -1,6 +1,7 @@ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:19:16: Imperfect scheduling of variable: 't.c1_start' 19 | reg c1_start; initial c1_start = 0; | ^~~~~~~~ + ... For warning description see https://verilator.org/warn/IMPERFECTSCH?v=4.201 ... Use "/* verilator lint_off IMPERFECTSCH */" and lint_on around source to disable this message. %Warning-IMPERFECTSCH: t/t_order_clkinst.v:20:16: Imperfect scheduling of variable: 't.c1_count' 20 | wire [31:0] c1_count; diff --git a/test_regress/t/t_packed_concat_bad.out b/test_regress/t/t_packed_concat_bad.out index 3bbac473d..a0e92e05d 100644 --- a/test_regress/t/t_packed_concat_bad.out +++ b/test_regress/t/t_packed_concat_bad.out @@ -2,6 +2,7 @@ : ... In instance t 17 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; | ^~~~~ + ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=4.201 ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:46: Unsized numbers/parameters not allowed in concatenations. : ... In instance t diff --git a/test_regress/t/t_param_concat_bad.out b/test_regress/t/t_param_concat_bad.out index 5c7036e34..1cc22b953 100644 --- a/test_regress/t/t_param_concat_bad.out +++ b/test_regress/t/t_param_concat_bad.out @@ -2,6 +2,7 @@ : ... In instance t 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; | ^~~~~~~ + ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=4.201 ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_param_concat.v:19:22: Unsized numbers/parameters not allowed in replications. : ... In instance t diff --git a/test_regress/t/t_param_in_func_bad.out b/test_regress/t/t_param_in_func_bad.out index 683490111..11d333858 100644 --- a/test_regress/t/t_param_in_func_bad.out +++ b/test_regress/t/t_param_in_func_bad.out @@ -2,4 +2,5 @@ : ... In instance t 24 | localparam logic[7:0] digits[10] | ^~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_param_noval_bad.out b/test_regress/t/t_param_noval_bad.out index 606fca350..bac882641 100644 --- a/test_regress/t/t_param_noval_bad.out +++ b/test_regress/t/t_param_noval_bad.out @@ -6,6 +6,7 @@ : ... In instance t 10 | for (j=0; P; j++) | ^~~ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: t/t_param_noval_bad.v:10:7: Non-genvar used in generate for: 'j' : ... In instance t diff --git a/test_regress/t/t_param_scope_bad.out b/test_regress/t/t_param_scope_bad.out index ca3fc7560..d9286ecb4 100644 --- a/test_regress/t/t_param_scope_bad.out +++ b/test_regress/t/t_param_scope_bad.out @@ -1,5 +1,6 @@ %Warning-CASEOVERLAP: t/t_param_scope_bad.v:28:9: Case values overlap (example pattern 0x2) 28 | 2'h2: $stop; | ^~~~ + ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=4.201 ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_param_sel_range_bad.out b/test_regress/t/t_param_sel_range_bad.out index a4dec58b9..8e8cf5f93 100644 --- a/test_regress/t/t_param_sel_range_bad.out +++ b/test_regress/t/t_param_sel_range_bad.out @@ -2,5 +2,6 @@ : ... In instance t.u2 43 | r_rst[i] <= r_rst[i-1]; | ^ + ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_past_bad.out b/test_regress/t/t_past_bad.out index 39a14b562..70144f13b 100644 --- a/test_regress/t/t_past_bad.out +++ b/test_regress/t/t_past_bad.out @@ -14,5 +14,6 @@ : ... In instance t 18 | if ($past(d, 10000)) $stop; | ^~~~~ + ... For warning description see https://verilator.org/warn/TICKCOUNT?v=4.201 ... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_past_unsup_bad.out b/test_regress/t/t_past_unsup_bad.out index 9f8b2bb83..5115fdf14 100644 --- a/test_regress/t/t_past_unsup_bad.out +++ b/test_regress/t/t_past_unsup_bad.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_past_unsup_bad.v:13:11: Unsupported: $past expr2 and clock arguments 13 | if ($past(d, 0, 0)) $stop; | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_past_unsup_bad.v:14:11: Unsupported: $past expr2 and clock arguments 14 | if ($past(d, 0, 0, clk)) $stop; | ^~~~~ diff --git a/test_regress/t/t_pp_dupdef_bad.out b/test_regress/t/t_pp_dupdef_bad.out index cb207f1d3..af9756bc6 100644 --- a/test_regress/t/t_pp_dupdef_bad.out +++ b/test_regress/t/t_pp_dupdef_bad.out @@ -1,5 +1,6 @@ %Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Redefining existing define: 'DUP', with different value: 'barney' t/t_pp_dupdef.v:11:20: ... Location of previous definition, with value: 'fred' + ... For warning description see https://verilator.org/warn/REDEFMACRO?v=4.201 ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message. %Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Redefining existing define: 'DUPP', with different value: 'paramed(x,z) (x*z)' t/t_pp_dupdef.v:14:33: ... Location of previous definition, with value: 'paramed(x) (x)' diff --git a/test_regress/t/t_priority_case.out b/test_regress/t/t_priority_case.out index f3e336f9d..e2705c6d9 100644 --- a/test_regress/t/t_priority_case.out +++ b/test_regress/t/t_priority_case.out @@ -1,6 +1,7 @@ %Warning-CASEOVERLAP: t/t_priority_case.v:34:7: Case item ignored: every matching value is covered by an earlier item 34 | 2'b ?1: out1 = 3'd1; | ^~~~~~ + ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=4.201 ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Warning-CASEOVERLAP: t/t_priority_case.v:44:7: Case item ignored: every matching value is covered by an earlier item 44 | 2'b ?1: out1 = 3'd1; diff --git a/test_regress/t/t_process.out b/test_regress/t/t_process.out index 7f135af7b..4d1f1a1b8 100644 --- a/test_regress/t/t_process.out +++ b/test_regress/t/t_process.out @@ -4,6 +4,7 @@ %Error-UNSUPPORTED: t/t_process.v:26:20: Unsupported: 'process' 26 | p = process::self(); | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Internal Error: t/t_process.v:26:11: ../V3LinkDot.cpp:#: Bad package link 26 | p = process::self(); | ^~~~~~~ diff --git a/test_regress/t/t_prot_lib_inout_bad.out b/test_regress/t/t_prot_lib_inout_bad.out index b33360f10..733fcc80c 100644 --- a/test_regress/t/t_prot_lib_inout_bad.out +++ b/test_regress/t/t_prot_lib_inout_bad.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_prot_lib_inout_bad.v:9:28: Unsupported: protect-lib port direction: INOUT 9 | inout z, | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_protect_ids_bad.out b/test_regress/t/t_protect_ids_bad.out index da5ad8345..7e32b4b2c 100644 --- a/test_regress/t/t_protect_ids_bad.out +++ b/test_regress/t/t_protect_ids_bad.out @@ -1,5 +1,6 @@ %Error-UNSUPPORTED: Unsupported: Using --protect-ids with --public ... Suggest remove --public. + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Warning-INSECURE: Using --protect-ids with --trace may expose private design details ... Suggest remove --trace. ... Use "/* verilator lint_off INSECURE */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_randc_unsup.out b/test_regress/t/t_randc_unsup.out index 4ca619d14..3e4ca214d 100644 --- a/test_regress/t/t_randc_unsup.out +++ b/test_regress/t/t_randc_unsup.out @@ -1,5 +1,6 @@ %Warning-RANDC: t/t_randc_unsup.v:8:14: Unsupported: Converting 'randc' to 'rand' 8 | randc int i; | ^ + ... For warning description see https://verilator.org/warn/RANDC?v=4.201 ... Use "/* verilator lint_off RANDC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_randomize.out b/test_regress/t/t_randomize.out index 7f05355de..c51190262 100644 --- a/test_regress/t/t_randomize.out +++ b/test_regress/t/t_randomize.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_randomize.v:11:4: Unsupported: extern constraint 11 | extern constraint ex; | ^~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_randomize.v:29:29: Unsupported: solve before 29 | constraint order { solve length before header; } | ^~~~~~ diff --git a/test_regress/t/t_randomize_method_types_unsup.out b/test_regress/t/t_randomize_method_types_unsup.out index a84c9ae0e..1f5c2bf5d 100644 --- a/test_regress/t/t_randomize_method_types_unsup.out +++ b/test_regress/t/t_randomize_method_types_unsup.out @@ -2,6 +2,7 @@ : ... In instance t 12 | rand int assocarr[string]; | ^~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:13:13: Unsupported: random member variables with type 'int[]' : ... In instance t 13 | rand int dynarr[]; diff --git a/test_regress/t/t_randomize_method_unsup.out b/test_regress/t/t_randomize_method_unsup.out index 5012993da..b394b34f1 100644 --- a/test_regress/t/t_randomize_method_unsup.out +++ b/test_regress/t/t_randomize_method_unsup.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_randomize_method_unsup.v:8:18: Unsupported: 'pre_randomize' 8 | function void pre_randomize; | ^~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_randomize_method_unsup.v:11:18: Unsupported: 'post_randomize' 11 | function void post_randomize; | ^~~~~~~~~~~~~~ diff --git a/test_regress/t/t_savable_class_bad.out b/test_regress/t/t_savable_class_bad.out index 08c051e17..56b78a4de 100644 --- a/test_regress/t/t_savable_class_bad.out +++ b/test_regress/t/t_savable_class_bad.out @@ -1,2 +1,3 @@ %Error-UNSUPPORTED: Unsupported: --savable with dynamic new + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_msb.out b/test_regress/t/t_select_bad_msb.out index 2401969bb..f288d49e1 100644 --- a/test_regress/t/t_select_bad_msb.out +++ b/test_regress/t/t_select_bad_msb.out @@ -2,6 +2,7 @@ : ... In instance t 12 | reg [0:22] backwd; | ^ + ... For warning description see https://verilator.org/warn/LITENDIAN?v=4.201 ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_msb.v:16:16: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1] : ... In instance t diff --git a/test_regress/t/t_select_bad_range.out b/test_regress/t/t_select_bad_range.out index c72a978d5..97f6beeef 100644 --- a/test_regress/t/t_select_bad_range.out +++ b/test_regress/t/t_select_bad_range.out @@ -2,6 +2,7 @@ : ... In instance t 16 | sel = mi[44]; | ^ + ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range.v:17:16: Selection index out of range: 44:41 outside 43:0 : ... In instance t diff --git a/test_regress/t/t_select_bad_range2.out b/test_regress/t/t_select_bad_range2.out index fc2bb2d0d..b45732a65 100644 --- a/test_regress/t/t_select_bad_range2.out +++ b/test_regress/t/t_select_bad_range2.out @@ -2,5 +2,6 @@ : ... In instance t.test 51 | assign out32 = in[3:2]; | ^ + ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range3.out b/test_regress/t/t_select_bad_range3.out index 30c14d08d..ad9ce0380 100644 --- a/test_regress/t/t_select_bad_range3.out +++ b/test_regress/t/t_select_bad_range3.out @@ -2,5 +2,6 @@ : ... In instance t 19 | assign outwires[12] = inwires[13]; | ^ + ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_split_var_1_bad.out b/test_regress/t/t_split_var_1_bad.out index d606c7a08..b55cafcf3 100644 --- a/test_regress/t/t_split_var_1_bad.out +++ b/test_regress/t/t_split_var_1_bad.out @@ -1,6 +1,7 @@ %Warning-SPLITVAR: t/t_split_var_1_bad.v:7:13: 'should_show_warning_global0' has split_var metacomment, but will not be split because it is not declared in a module. 7 | logic [7:0] should_show_warning_global0 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ + ... For warning description see https://verilator.org/warn/SPLITVAR?v=4.201 ... Use "/* verilator lint_off SPLITVAR */" and lint_on around source to disable this message. %Warning-SPLITVAR: t/t_split_var_1_bad.v:8:13: 'should_show_warning_global1' has split_var metacomment, but will not be split because it is not declared in a module. 8 | logic [7:0] should_show_warning_global1 [1:0] /*verilator split_var*/ ; diff --git a/test_regress/t/t_stream_integer_type.out b/test_regress/t/t_stream_integer_type.out index e6d1b0876..a8fd0cf20 100644 --- a/test_regress/t/t_stream_integer_type.out +++ b/test_regress/t/t_stream_integer_type.out @@ -2,6 +2,7 @@ : ... In instance t 118 | packed_data_32 = {<<8{byte_in}}; | ^ + ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_stream_integer_type.v:119:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits. : ... In instance t diff --git a/test_regress/t/t_struct_unpacked2.out b/test_regress/t/t_struct_unpacked2.out index aa812216b..b5f430c28 100644 --- a/test_regress/t/t_struct_unpacked2.out +++ b/test_regress/t/t_struct_unpacked2.out @@ -1,6 +1,7 @@ %Warning-UNPACKED: t/t_struct_unpacked2.v:10:13: Unsupported: Unpacked array in packed struct/union (struct/union converted to unpacked) 10 | int b [2]; | ^ + ... For warning description see https://verilator.org/warn/UNPACKED?v=4.201 ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message. %Warning-UNPACKED: t/t_struct_unpacked2.v:9:12: Unsupported: Unpacked struct/union : ... In instance x diff --git a/test_regress/t/t_struct_unpacked_bad.out b/test_regress/t/t_struct_unpacked_bad.out index 6e9356b6d..29d8c0208 100644 --- a/test_regress/t/t_struct_unpacked_bad.out +++ b/test_regress/t/t_struct_unpacked_bad.out @@ -2,5 +2,6 @@ : ... In instance x 9 | typedef struct { | ^~~~~~ + ... For warning description see https://verilator.org/warn/UNPACKED?v=4.201 ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_sys_readmem_assoc_bad.out b/test_regress/t/t_sys_readmem_assoc_bad.out index bc09fd9cd..220cfebcc 100644 --- a/test_regress/t/t_sys_readmem_assoc_bad.out +++ b/test_regress/t/t_sys_readmem_assoc_bad.out @@ -6,4 +6,5 @@ : ... In instance t 14 | $readmemb("not", assoc_bad_value); | ^~~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_timescale_lint_bad.out b/test_regress/t/t_timescale_lint_bad.out index dea8a0a8c..771e03304 100644 --- a/test_regress/t/t_timescale_lint_bad.out +++ b/test_regress/t/t_timescale_lint_bad.out @@ -4,5 +4,6 @@ t/t_timescale_lint.v:12:8: ... Location of module with timescale 12 | module t; | ^ + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=4.201 ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_tri_compass_bad.out b/test_regress/t/t_tri_compass_bad.out index b07623a7d..b48142931 100644 --- a/test_regress/t/t_tri_compass_bad.out +++ b/test_regress/t/t_tri_compass_bad.out @@ -2,4 +2,5 @@ : ... In instance t 16 | sub sub(i, o); | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_tri_pull2_bad.out b/test_regress/t/t_tri_pull2_bad.out index 98baf9520..67d77c7bc 100644 --- a/test_regress/t/t_tri_pull2_bad.out +++ b/test_regress/t/t_tri_pull2_bad.out @@ -5,4 +5,5 @@ t/t_tri_pull2_bad.v:22:13: ... Location of conflicting pull. 22 | pulldown p2(A); | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_tri_pull_bad.out b/test_regress/t/t_tri_pull_bad.out index e59dcf535..15889fc4f 100644 --- a/test_regress/t/t_tri_pull_bad.out +++ b/test_regress/t/t_tri_pull_bad.out @@ -5,4 +5,5 @@ t/t_tri_pull_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p1(A); | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_tri_pullvec_bad.out b/test_regress/t/t_tri_pullvec_bad.out index 1c5594298..e4b2ce9ca 100644 --- a/test_regress/t/t_tri_pullvec_bad.out +++ b/test_regress/t/t_tri_pullvec_bad.out @@ -5,6 +5,7 @@ t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p0 (w[0]); | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_tri_pullvec_bad.v:14:13: Unsupported: Conflicting pull directions. : ... In instance t 14 | pulldown p2 (w[2]); diff --git a/test_regress/t/t_udp.out b/test_regress/t/t_udp.out index 852e2eef0..6cf8a41f4 100644 --- a/test_regress/t/t_udp.out +++ b/test_regress/t/t_udp.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_udp.v:104:4: Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables. 104 | table | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad.out b/test_regress/t/t_udp_bad.out index 451595dd6..f190c275f 100644 --- a/test_regress/t/t_udp_bad.out +++ b/test_regress/t/t_udp_bad.out @@ -1,6 +1,7 @@ %Warning-PINMISSING: t/t_udp_bad.v:10:10: Cell has missing pin: 'c_bad' 10 | udp_x x (a, b); | ^ + ... For warning description see https://verilator.org/warn/PINMISSING?v=4.201 ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_udp_bad.v:14:18: Pin is not an in/out/inout/interface: 'a_bad' 14 | primitive udp_x (a_bad, b, c_bad); diff --git a/test_regress/t/t_unopt_combo_bad.out b/test_regress/t/t_unopt_combo_bad.out index a4be2fab5..7b31be8ab 100644 --- a/test_regress/t/t_unopt_combo_bad.out +++ b/test_regress/t/t_unopt_combo_bad.out @@ -1,6 +1,7 @@ %Warning-UNOPTFLAT: t/t_unopt_combo.v:24:25: Signal unoptimizable: Feedback to clock or circular logic: 't.c' 24 | wire [31:0] c; | ^ + ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=4.201 ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unopt_combo.v:24:25: Example path: t.c t/t_unopt_combo.v:81:4: Example path: ALWAYS diff --git a/test_regress/t/t_unopt_converge_unopt_bad.out b/test_regress/t/t_unopt_converge_unopt_bad.out index 2a978fa65..51fd138ee 100644 --- a/test_regress/t/t_unopt_converge_unopt_bad.out +++ b/test_regress/t/t_unopt_converge_unopt_bad.out @@ -1,6 +1,7 @@ %Warning-UNOPT: t/t_unopt_converge.v:19:11: Signal unoptimizable: Feedback to public clock or circular logic: 'x' 19 | output x; | ^ + ... For warning description see https://verilator.org/warn/UNOPT?v=4.201 ... Use "/* verilator lint_off UNOPT */" and lint_on around source to disable this message. t/t_unopt_converge.v:19:11: Example path: x t/t_unopt_converge.v:22:4: Example path: ALWAYS diff --git a/test_regress/t/t_unoptflat_simple_2_bad.out b/test_regress/t/t_unoptflat_simple_2_bad.out index e03cad9b2..3ba06168f 100644 --- a/test_regress/t/t_unoptflat_simple_2_bad.out +++ b/test_regress/t/t_unoptflat_simple_2_bad.out @@ -1,6 +1,7 @@ %Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:15:15: Signal unoptimizable: Feedback to clock or circular logic: 't.x' 15 | wire [2:0] x; | ^ + ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=4.201 ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unoptflat_simple_2.v:15:15: Example path: t.x t/t_unoptflat_simple_2.v:17:18: Example path: ASSIGNW diff --git a/test_regress/t/t_unpacked_concat_bad.out b/test_regress/t/t_unpacked_concat_bad.out index 67309b1bd..fccb233a3 100644 --- a/test_regress/t/t_unpacked_concat_bad.out +++ b/test_regress/t/t_unpacked_concat_bad.out @@ -2,6 +2,7 @@ : ... In instance t 17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; | ^ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:17:47: Unsized numbers/parameters not allowed in replications. : ... In instance t 17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; diff --git a/test_regress/t/t_vams_kwd_bad.out b/test_regress/t/t_vams_kwd_bad.out index cc4a86cc1..500595296 100644 --- a/test_regress/t/t_vams_kwd_bad.out +++ b/test_regress/t/t_vams_kwd_bad.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:12:8: Unsupported: AMS reserved word not implemented: 'above' 12 | int above; | ^~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: t/t_vams_kwd_bad.v:12:13: syntax error, unexpected ';', expecting IDENTIFIER or randomize 12 | int above; | ^ diff --git a/test_regress/t/t_var_bad_hide.out b/test_regress/t/t_var_bad_hide.out index 7746fd863..27599dc26 100644 --- a/test_regress/t/t_var_bad_hide.out +++ b/test_regress/t/t_var_bad_hide.out @@ -4,6 +4,7 @@ t/t_var_bad_hide.v:13:12: ... Location of original declaration 13 | integer top; | ^~~ + ... For warning description see https://verilator.org/warn/VARHIDDEN?v=4.201 ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Warning-VARHIDDEN: t/t_var_bad_hide.v:22:18: Declaration of signal hides declaration in upper scope: 'top' 22 | integer top; diff --git a/test_regress/t/t_var_bad_hide2.out b/test_regress/t/t_var_bad_hide2.out index 3318750c1..ee41a5f0c 100644 --- a/test_regress/t/t_var_bad_hide2.out +++ b/test_regress/t/t_var_bad_hide2.out @@ -4,5 +4,6 @@ t/t_var_bad_hide2.v:7:8: ... Location of original declaration 7 | module t; | ^ + ... For warning description see https://verilator.org/warn/VARHIDDEN?v=4.201 ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_hide_docs.out b/test_regress/t/t_var_bad_hide_docs.out index 3ce6c7460..86ee16b64 100644 --- a/test_regress/t/t_var_bad_hide_docs.out +++ b/test_regress/t/t_var_bad_hide_docs.out @@ -4,5 +4,6 @@ t/t_var_bad_hide_docs.v:7:8: ... Location of original declaration 7 | module t; | ^ + ... For warning description see https://verilator.org/warn/VARHIDDEN?v=4.201 ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_var_in_assign_bad.out b/test_regress/t/t_var_in_assign_bad.out index 87acaf9f1..a32dcc803 100644 --- a/test_regress/t/t_var_in_assign_bad.out +++ b/test_regress/t/t_var_in_assign_bad.out @@ -1,6 +1,7 @@ %Error-ASSIGNIN: t/t_var_in_assign_bad.v:12:16: Assigning to input/const variable: 'value' 12 | assign value = 4'h0; | ^~~~~ + ... For error description see https://verilator.org/warn/ASSIGNIN?v=4.201 %Error-ASSIGNIN: t/t_var_in_assign_bad.v:21:16: Assigning to input/const variable: 'valueSub' 21 | assign valueSub = 4'h0; | ^~~~~~~~ diff --git a/test_regress/t/t_var_ref_bad3.out b/test_regress/t/t_var_ref_bad3.out index 6ae8e9307..2dc201162 100644 --- a/test_regress/t/t_var_ref_bad3.out +++ b/test_regress/t/t_var_ref_bad3.out @@ -1,4 +1,5 @@ %Error-UNSUPPORTED: t/t_var_ref_bad3.v:10:18: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' 10 | module t(ref int bad_primary_ref | ^~~~~~~~~~~~~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_var_rsvd_bad.out b/test_regress/t/t_var_rsvd_bad.out index 5a4cd49ab..04bc62b04 100644 --- a/test_regress/t/t_var_rsvd_bad.out +++ b/test_regress/t/t_var_rsvd_bad.out @@ -1,6 +1,7 @@ %Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:12:10: Symbol matches C++ keyword: 'bool' 12 | input bool; | ^~~~ + ... For warning description see https://verilator.org/warn/SYMRSVDWORD?v=4.201 ... Use "/* verilator lint_off SYMRSVDWORD */" and lint_on around source to disable this message. %Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:15:9: Symbol matches C++ keyword: 'switch' : ... In instance t diff --git a/test_regress/t/t_var_static.out b/test_regress/t/t_var_static.out index f6d7a524e..3781d41ac 100644 --- a/test_regress/t/t_var_static.out +++ b/test_regress/t/t_var_static.out @@ -2,6 +2,7 @@ : ... In instance t 20 | static int st = 2; st++; return st; | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_var_static.v:30:18: Unsupported: 'static' function/task variables : ... In instance t 30 | static int st = 2; st++; return st; diff --git a/test_regress/t/t_var_static_param.out b/test_regress/t/t_var_static_param.out index f58144faa..a87e35d6c 100644 --- a/test_regress/t/t_var_static_param.out +++ b/test_regress/t/t_var_static_param.out @@ -2,4 +2,5 @@ : ... In instance t.subb 32 | static int st = 2; st += P; return st; | ^~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error: Exiting due to diff --git a/test_regress/t/t_var_types_bad.out b/test_regress/t/t_var_types_bad.out index e4c100627..291a3db6a 100644 --- a/test_regress/t/t_var_types_bad.out +++ b/test_regress/t/t_var_types_bad.out @@ -21,6 +21,7 @@ %Warning-REALCVT: t/t_var_types_bad.v:46:7: Implicit conversion of real to integer 46 | d_real[0] = 1'b1; | ^~~~~~ + ... For warning description see https://verilator.org/warn/REALCVT?v=4.201 ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: t/t_var_types_bad.v:47:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' : ... In instance t diff --git a/test_regress/t/t_vlt_warn_bad.out b/test_regress/t/t_vlt_warn_bad.out index 4e5fcde5a..646936098 100644 --- a/test_regress/t/t_vlt_warn_bad.out +++ b/test_regress/t/t_vlt_warn_bad.out @@ -1,6 +1,7 @@ %Warning-DEPRECATED: t/t_vlt_warn_bad.vlt:12:10: Deprecated -msg in configuration files, use -rule instead. 12 | lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 19-19 | ^~~~ + ... For warning description see https://verilator.org/warn/DEPRECATED?v=4.201 ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_vlt_warn.v:21:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits. : ... In instance t diff --git a/test_regress/t/t_wait.out b/test_regress/t/t_wait.out index bc88a4f78..d71745e4f 100644 --- a/test_regress/t/t_wait.out +++ b/test_regress/t/t_wait.out @@ -1,6 +1,7 @@ %Error-UNSUPPORTED: t/t_wait.v:12:7: Unsupported: wait statements 12 | wait (value == 1); | ^~~~ + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 %Error-UNSUPPORTED: t/t_wait.v:14:7: Unsupported: wait statements 14 | wait (0); | ^~~~ diff --git a/test_regress/t/t_wire_beh1364_bad.out b/test_regress/t/t_wire_beh1364_bad.out index 18834bf3a..c53c1ab06 100644 --- a/test_regress/t/t_wire_beh1364_bad.out +++ b/test_regress/t/t_wire_beh1364_bad.out @@ -2,6 +2,7 @@ : ... In instance t 25 | w = '0; | ^ + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 26 | o = '0; diff --git a/test_regress/t/t_wire_beh1800_bad.out b/test_regress/t/t_wire_beh1800_bad.out index 4300d3caf..8d48b7ac1 100644 --- a/test_regress/t/t_wire_beh1800_bad.out +++ b/test_regress/t/t_wire_beh1800_bad.out @@ -2,6 +2,7 @@ : ... In instance t 25 | w = '0; | ^ + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 26 | o = '0; diff --git a/test_regress/t/t_wire_behp1364_bad.out b/test_regress/t/t_wire_behp1364_bad.out index 73e9d1c53..ed4055430 100644 --- a/test_regress/t/t_wire_behp1364_bad.out +++ b/test_regress/t/t_wire_behp1364_bad.out @@ -2,6 +2,7 @@ : ... In instance t 23 | w = '0; | ^ + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 %Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 24 | o = '0; diff --git a/test_regress/t/t_wire_behp1800_bad.out b/test_regress/t/t_wire_behp1800_bad.out index ec76bc00c..200179d4c 100644 --- a/test_regress/t/t_wire_behp1800_bad.out +++ b/test_regress/t/t_wire_behp1800_bad.out @@ -2,6 +2,7 @@ : ... In instance t 23 | w = '0; | ^ + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 24 | o = '0; From c443e229eea8473d755e43c9f0c914a796898948 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sun, 18 Apr 2021 11:52:29 -0400 Subject: [PATCH 099/110] Fix URL references. --- docs/internals.rst | 2 +- src/V3EmitC.cpp | 3 ++- src/V3Error.cpp | 11 ++++++----- test_regress/t/t_debug_fatalsrc_bad.pl | 2 +- test_regress/t/t_debug_fatalsrc_bt_bad.pl | 2 +- test_regress/t/t_dpi_accessors.v | 2 +- test_regress/t/t_enum_type_methods_bad.out | 2 +- test_regress/t/t_func_tasknsvar_bad.out | 2 +- test_regress/t/t_fuzz_genintf_bad.out | 2 +- test_regress/t/t_fuzz_triand_bad.out | 2 +- test_regress/t/t_interface_ar3.out | 2 +- test_regress/t/t_lint_blksync_bad.out | 2 +- test_regress/t/t_lint_latch_bad.out | 2 +- test_regress/t/t_lint_latch_bad_3.out | 2 +- 14 files changed, 20 insertions(+), 18 deletions(-) diff --git a/docs/internals.rst b/docs/internals.rst index f40cce27b..71eebfb41 100644 --- a/docs/internals.rst +++ b/docs/internals.rst @@ -707,7 +707,7 @@ Testing ======= For an overview of how to write a test see the BUGS section of the -Verilator primary manual. +`Verilator Manual `_. It is important to add tests for failures as well as success (for example to check that an error message is correctly triggered). diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 48ad6de4a..0785b4f75 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -1097,6 +1097,7 @@ public: iterateAndNextNull(nodep->fhsp()); puts(")"); } + virtual void visit(AstInitItem* nodep) override { iterateChildren(nodep); } // Terminals virtual void visit(AstVarRef* nodep) override { puts(nodep->hiernameProtect()); @@ -2734,7 +2735,7 @@ void EmitCImp::emitSettleLoop(const std::string& eval_call, bool initial) { puts("\"Verilated model didn't "); if (initial) puts("DC "); puts("converge\\n\"\n"); - puts("\"- See DIDNOTCONVERGE in the Verilator manual\");\n"); + puts("\"- See https://verilator.org/warn/DIDNOTCONVERGE\");\n"); puts("} else {\n"); puts("__Vchange = " + protect("_change_request") + "(vlSymsp);\n"); puts("}\n"); diff --git a/src/V3Error.cpp b/src/V3Error.cpp index 23921b0ee..d1f4b4a4f 100644 --- a/src/V3Error.cpp +++ b/src/V3Error.cpp @@ -242,7 +242,8 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { << " */\" and lint_on around source to disable this message." << endl; } if (s_errorCode.dangerous()) { - std::cerr << warnMore() << "*** See the manual before disabling this,\n"; + std::cerr << warnMore() << "*** See https://verilator.org/warn/" + << s_errorCode.ascii() << " before disabling this,\n"; std::cerr << warnMore() << "else you may end up with different sim results." << endl; } @@ -267,10 +268,10 @@ void V3Error::v3errorEnd(std::ostringstream& sstr, const string& locationStr) { if (!inFatal) { inFatal = true; if (s_tellManual == 1) { - std::cerr - << warnMore() - << "... See the manual and https://verilator.org for more assistance." - << endl; + std::cerr << warnMore() + << "... See the manual at https://verilator.org/verilator_doc.html " + "for more assistance." + << endl; s_tellManual = 2; } #ifndef V3ERROR_NO_GLOBAL_ diff --git a/test_regress/t/t_debug_fatalsrc_bad.pl b/test_regress/t/t_debug_fatalsrc_bad.pl index 6f50286a8..c11da33d9 100755 --- a/test_regress/t/t_debug_fatalsrc_bad.pl +++ b/test_regress/t/t_debug_fatalsrc_bad.pl @@ -15,7 +15,7 @@ lint( fails => $Self->{vlt_all}, expect => '%Error: Internal Error: .*: --debug-fatal-src -.* See the manual and .*', +.* See the manual .*', ); ok(1); diff --git a/test_regress/t/t_debug_fatalsrc_bt_bad.pl b/test_regress/t/t_debug_fatalsrc_bt_bad.pl index ad5a9ae03..8be054a7b 100755 --- a/test_regress/t/t_debug_fatalsrc_bt_bad.pl +++ b/test_regress/t/t_debug_fatalsrc_bt_bad.pl @@ -16,7 +16,7 @@ lint( fails => 1, expect => '%Error: Internal Error: .*: --debug-fatal-src -.*See the manual and .* +.*See the manual .* .*in V3Options::.* .*%Error: Command Failed.*', ); diff --git a/test_regress/t/t_dpi_accessors.v b/test_regress/t/t_dpi_accessors.v index 9fe29f04f..c41fea0bc 100644 --- a/test_regress/t/t_dpi_accessors.v +++ b/test_regress/t/t_dpi_accessors.v @@ -9,7 +9,7 @@ // This test exercises the use of DPI to access signals and registers in a // module hierarchy in a uniform fashion. See the discussion at // -// https://www.veripool.org/boards/3/topics/show/752-Verilator-Command-line-specification-of-public-access-to-variables +// https://github.com/verilator/verilator/issues/1750 // // We need to test read and write access to: // - scalars diff --git a/test_regress/t/t_enum_type_methods_bad.out b/test_regress/t/t_enum_type_methods_bad.out index 7bcf19162..41c5834a1 100644 --- a/test_regress/t/t_enum_type_methods_bad.out +++ b/test_regress/t/t_enum_type_methods_bad.out @@ -2,4 +2,4 @@ : ... In instance t 24 | e.next(increment); | ^~~~~~~~~ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_func_tasknsvar_bad.out b/test_regress/t/t_func_tasknsvar_bad.out index ffcd633c9..b60d15c95 100644 --- a/test_regress/t/t_func_tasknsvar_bad.out +++ b/test_regress/t/t_func_tasknsvar_bad.out @@ -5,4 +5,4 @@ %Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): m_varScopep && !m_varScopep->brokeExists() 10 | sig = '1; | ^~~ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_fuzz_genintf_bad.out b/test_regress/t/t_fuzz_genintf_bad.out index 485e7289b..df5d490ef 100644 --- a/test_regress/t/t_fuzz_genintf_bad.out +++ b/test_regress/t/t_fuzz_genintf_bad.out @@ -7,4 +7,4 @@ : ... In instance t 24 | j.e(0), | ^ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_fuzz_triand_bad.out b/test_regress/t/t_fuzz_triand_bad.out index 3343c190b..3af71a1ba 100644 --- a/test_regress/t/t_fuzz_triand_bad.out +++ b/test_regress/t/t_fuzz_triand_bad.out @@ -7,4 +7,4 @@ : ... In instance t 8 | tri g=g.and.g; | ^~~ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_interface_ar3.out b/test_regress/t/t_interface_ar3.out index e28530a56..49bc89443 100644 --- a/test_regress/t/t_interface_ar3.out +++ b/test_regress/t/t_interface_ar3.out @@ -6,4 +6,4 @@ : ... In instance t 16 | sub sub01 [2] (.clk, .infc(iinst[0:1])); | ^ - ... See the manual and https://verilator.org for more assistance. + ... See the manual at https://verilator.org/verilator_doc.html for more assistance. diff --git a/test_regress/t/t_lint_blksync_bad.out b/test_regress/t/t_lint_blksync_bad.out index ec1d772e9..4e09d0d77 100644 --- a/test_regress/t/t_lint_blksync_bad.out +++ b/test_regress/t/t_lint_blksync_bad.out @@ -8,6 +8,6 @@ : ... Suggest blocking assignments (=) 31 | combo_nblk <= 1'b1; | ^~ - *** See the manual before disabling this, + *** See https://verilator.org/warn/COMBDLY before disabling this, else you may end up with different sim results. %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad.out b/test_regress/t/t_lint_latch_bad.out index 2cd7ce388..1d5cd253a 100644 --- a/test_regress/t/t_lint_latch_bad.out +++ b/test_regress/t/t_lint_latch_bad.out @@ -7,6 +7,6 @@ : ... Suggest blocking assignments (=) 25 | bc <= a; | ^~ - *** See the manual before disabling this, + *** See https://verilator.org/warn/COMBDLY before disabling this, else you may end up with different sim results. %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad_3.out b/test_regress/t/t_lint_latch_bad_3.out index 809fea09a..94f96de5e 100644 --- a/test_regress/t/t_lint_latch_bad_3.out +++ b/test_regress/t/t_lint_latch_bad_3.out @@ -8,6 +8,6 @@ : ... Suggest blocking assignments (=) 70 | o4 <= 1'b0; | ^~ - *** See the manual before disabling this, + *** See https://verilator.org/warn/COMBDLY before disabling this, else you may end up with different sim results. %Error: Exiting due to From 6660627558eb8ef9b6380b84532f726cd5d094c6 Mon Sep 17 00:00:00 2001 From: Graham Rushton Date: Tue, 20 Apr 2021 14:08:29 +0100 Subject: [PATCH 100/110] Fix concat of long hashed names in traces etc (#2854) --- docs/CONTRIBUTORS | 1 + src/V3String.cpp | 52 ++++++++++++++++--- test_regress/t/t_trace_complex.out | 4 ++ test_regress/t/t_trace_complex.v | 2 + test_regress/t/t_trace_complex_fst.out | 11 ++-- test_regress/t/t_trace_complex_fst_sc.out | 13 +++-- test_regress/t/t_trace_complex_params.out | 4 ++ test_regress/t/t_trace_complex_params_fst.out | 11 ++-- .../t/t_trace_complex_params_fst_sc.out | 13 +++-- 9 files changed, 87 insertions(+), 24 deletions(-) diff --git a/docs/CONTRIBUTORS b/docs/CONTRIBUTORS index e20735dd4..f8c20a846 100644 --- a/docs/CONTRIBUTORS +++ b/docs/CONTRIBUTORS @@ -23,6 +23,7 @@ Garrett Smith Geza Lore Gianfranco Costamagna Glen Gibb +Graham Rushton Harald Heckmann Howard Su Huang Rui diff --git a/src/V3String.cpp b/src/V3String.cpp index 5e4bcada6..b3d6a153f 100644 --- a/src/V3String.cpp +++ b/src/V3String.cpp @@ -380,12 +380,52 @@ void VHashSha256::selfTest() { // VName string VName::dehash(const string& in) { - const string::size_type pos = in.find("__Vhsh"); - if (VL_LIKELY(pos == string::npos)) return in; - const string vhsh = in.substr(pos); - const auto& it = s_dehashMap.find(vhsh); - UASSERT(it != s_dehashMap.end(), "String not in reverse hash map '" << vhsh << "'"); - return in.substr(0, pos) + it->second; + static const char VHSH[] = "__Vhsh"; + static const size_t DOT_LEN = strlen("__DOT__"); + std::string dehashed; + + // Need to split 'in' into components separated by __DOT__, 'last_dot_pos' + // keeps track of the position after the most recently found instance of __DOT__ + for (string::size_type last_dot_pos = 0; last_dot_pos < in.size(); ) { + const string::size_type next_dot_pos = in.find("__DOT__", last_dot_pos); + // Two iterators defining the range between the last and next dots. + auto search_begin = std::begin(in) + last_dot_pos; + auto search_end = next_dot_pos == string::npos ? std::end(in) + : std::begin(in) + next_dot_pos; + + // Search for __Vhsh between the two dots. + auto begin_vhsh = std::search(search_begin, search_end, + std::begin(VHSH), std::end(VHSH) - 1); + if (begin_vhsh != search_end) { + std::string vhsh(begin_vhsh, search_end); + const auto& it = s_dehashMap.find(vhsh); + UASSERT(it != s_dehashMap.end(), "String not in reverse hash map '" << vhsh << "'"); + // Is this not the first component, but the first to require dehashing? + if (last_dot_pos > 0 && dehashed.empty()) { + // Seed 'dehashed' with the previously processed components. + dehashed = in.substr(0, last_dot_pos); + } + // Append the unhashed part of the component. + dehashed += std::string(search_begin, begin_vhsh); + // Append the bit that was lost to truncation but retrieved from the dehash map. + dehashed += it->second; + } + // This component doesn't need dehashing but a previous one might have. + else if (!dehashed.empty()) { + dehashed += std::string(search_begin, search_end); + } + + if (next_dot_pos != string::npos) { + // Is there a __DOT__ to add to the dehashed version of 'in'? + if (!dehashed.empty()) { + dehashed += "__DOT__"; + } + last_dot_pos = next_dot_pos + DOT_LEN; + } else { + last_dot_pos = string::npos; + } + } + return dehashed.empty() ? in : dehashed; } string VName::hashedName() { diff --git a/test_regress/t/t_trace_complex.out b/test_regress/t/t_trace_complex.out index e57a057af..74c7eb8c7 100644 --- a/test_regress/t/t_trace_complex.out +++ b/test_regress/t/t_trace_complex.out @@ -39,6 +39,9 @@ $timescale 1ps $end $var wire 2 % v_strp [1:0] $end $var wire 4 & v_strp_strp [3:0] $end $var wire 2 ' v_unip_strp [1:0] $end + $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end + $var wire 32 J PARAM [31:0] $end + $upscope $end $scope module p2 $end $var wire 32 H PARAM [31:0] $end $upscope $end @@ -92,6 +95,7 @@ b00000000 F 0G b00000000000000000000000000000010 H b00000000000000000000000000000011 I +b00000000000000000000000000000100 J #10 b00000000000000000000000000000001 $ b11 % diff --git a/test_regress/t/t_trace_complex.v b/test_regress/t/t_trace_complex.v index 14489e9c5..baae75453 100644 --- a/test_regress/t/t_trace_complex.v +++ b/test_regress/t/t_trace_complex.v @@ -78,6 +78,8 @@ module t (clk); p #(.PARAM(2)) p2 (); p #(.PARAM(3)) p3 (); + p #(.PARAM(4)) a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed (); + always @ (posedge clk) begin cyc <= cyc + 1; v_strp <= ~v_strp; diff --git a/test_regress/t/t_trace_complex_fst.out b/test_regress/t/t_trace_complex_fst.out index e4f264a8e..d57c690c6 100644 --- a/test_regress/t/t_trace_complex_fst.out +++ b/test_regress/t/t_trace_complex_fst.out @@ -58,15 +58,19 @@ $upscope $end $scope module p3 $end $var parameter 32 B PARAM $end $upscope $end +$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end +$var parameter 32 C PARAM $end +$upscope $end $upscope $end $scope module $unit $end -$var bit 1 C global_bit $end +$var bit 1 D global_bit $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars -1C +#0 +1D +b00000000000000000000000000000100 C b00000000000000000000000000000011 B b00000000000000000000000000000010 A b00000000000000000000000000000000 @ @@ -101,7 +105,6 @@ b0000 $ b00 # b00000000000000000000000000000000 " 0! -$end #10 1! b00000000000000000000000000000001 " diff --git a/test_regress/t/t_trace_complex_fst_sc.out b/test_regress/t/t_trace_complex_fst_sc.out index 85c002638..f3da1ace4 100644 --- a/test_regress/t/t_trace_complex_fst_sc.out +++ b/test_regress/t/t_trace_complex_fst_sc.out @@ -1,5 +1,5 @@ $date - Thu Apr 1 15:12:03 2021 + Mon Apr 19 17:05:53 2021 $end $version @@ -57,15 +57,19 @@ $upscope $end $scope module p3 $end $var parameter 32 B PARAM $end $upscope $end +$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end +$var parameter 32 C PARAM $end +$upscope $end $upscope $end $scope module $unit $end -$var bit 1 C global_bit $end +$var bit 1 D global_bit $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars -1C +#0 +1D +b00000000000000000000000000000100 C b00000000000000000000000000000011 B b00000000000000000000000000000010 A b00000000000000000000000000000000 @ @@ -100,7 +104,6 @@ b0000 $ b00 # b00000000000000000000000000000000 " 0! -$end #10 1! b00000000000000000000000000000001 " diff --git a/test_regress/t/t_trace_complex_params.out b/test_regress/t/t_trace_complex_params.out index 88690fd62..8d2cd1890 100644 --- a/test_regress/t/t_trace_complex_params.out +++ b/test_regress/t/t_trace_complex_params.out @@ -39,6 +39,9 @@ $timescale 1ps $end $var wire 2 % v_strp [1:0] $end $var wire 4 & v_strp_strp [3:0] $end $var wire 2 ' v_unip_strp [1:0] $end + $scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end + $var wire 32 J PARAM [31:0] $end + $upscope $end $scope module p2 $end $var wire 32 H PARAM [31:0] $end $upscope $end @@ -92,6 +95,7 @@ b00000000 F 0G b00000000000000000000000000000010 H b00000000000000000000000000000011 I +b00000000000000000000000000000100 J #10 b00000000000000000000000000000001 $ b11 % diff --git a/test_regress/t/t_trace_complex_params_fst.out b/test_regress/t/t_trace_complex_params_fst.out index e4f264a8e..d57c690c6 100644 --- a/test_regress/t/t_trace_complex_params_fst.out +++ b/test_regress/t/t_trace_complex_params_fst.out @@ -58,15 +58,19 @@ $upscope $end $scope module p3 $end $var parameter 32 B PARAM $end $upscope $end +$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end +$var parameter 32 C PARAM $end +$upscope $end $upscope $end $scope module $unit $end -$var bit 1 C global_bit $end +$var bit 1 D global_bit $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars -1C +#0 +1D +b00000000000000000000000000000100 C b00000000000000000000000000000011 B b00000000000000000000000000000010 A b00000000000000000000000000000000 @ @@ -101,7 +105,6 @@ b0000 $ b00 # b00000000000000000000000000000000 " 0! -$end #10 1! b00000000000000000000000000000001 " diff --git a/test_regress/t/t_trace_complex_params_fst_sc.out b/test_regress/t/t_trace_complex_params_fst_sc.out index dcfa501c1..b5e67d184 100644 --- a/test_regress/t/t_trace_complex_params_fst_sc.out +++ b/test_regress/t/t_trace_complex_params_fst_sc.out @@ -1,5 +1,5 @@ $date - Thu Apr 1 15:17:39 2021 + Mon Apr 19 17:07:10 2021 $end $version @@ -57,15 +57,19 @@ $upscope $end $scope module p3 $end $var parameter 32 B PARAM $end $upscope $end +$scope module a_module_instantiation_with_a_very_long_name_that_once_its_signals_get_concatenated_and_inlined_will_almost_certainly_result_in_them_getting_hashed $end +$var parameter 32 C PARAM $end +$upscope $end $upscope $end $scope module $unit $end -$var bit 1 C global_bit $end +$var bit 1 D global_bit $end $upscope $end $upscope $end $enddefinitions $end -#0 $dumpvars -1C +#0 +1D +b00000000000000000000000000000100 C b00000000000000000000000000000011 B b00000000000000000000000000000010 A b00000000000000000000000000000000 @ @@ -100,7 +104,6 @@ b0000 $ b00 # b00000000000000000000000000000000 " 0! -$end #10 1! b00000000000000000000000000000001 " From 47e7e217067b36b1e6e35be4e2323f6df9036b1b Mon Sep 17 00:00:00 2001 From: github action Date: Tue, 20 Apr 2021 13:09:24 +0000 Subject: [PATCH 101/110] Apply clang-format --- src/V3String.cpp | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/V3String.cpp b/src/V3String.cpp index b3d6a153f..487643a4f 100644 --- a/src/V3String.cpp +++ b/src/V3String.cpp @@ -386,16 +386,16 @@ string VName::dehash(const string& in) { // Need to split 'in' into components separated by __DOT__, 'last_dot_pos' // keeps track of the position after the most recently found instance of __DOT__ - for (string::size_type last_dot_pos = 0; last_dot_pos < in.size(); ) { + for (string::size_type last_dot_pos = 0; last_dot_pos < in.size();) { const string::size_type next_dot_pos = in.find("__DOT__", last_dot_pos); // Two iterators defining the range between the last and next dots. auto search_begin = std::begin(in) + last_dot_pos; - auto search_end = next_dot_pos == string::npos ? std::end(in) - : std::begin(in) + next_dot_pos; + auto search_end + = next_dot_pos == string::npos ? std::end(in) : std::begin(in) + next_dot_pos; // Search for __Vhsh between the two dots. - auto begin_vhsh = std::search(search_begin, search_end, - std::begin(VHSH), std::end(VHSH) - 1); + auto begin_vhsh + = std::search(search_begin, search_end, std::begin(VHSH), std::end(VHSH) - 1); if (begin_vhsh != search_end) { std::string vhsh(begin_vhsh, search_end); const auto& it = s_dehashMap.find(vhsh); @@ -417,9 +417,7 @@ string VName::dehash(const string& in) { if (next_dot_pos != string::npos) { // Is there a __DOT__ to add to the dehashed version of 'in'? - if (!dehashed.empty()) { - dehashed += "__DOT__"; - } + if (!dehashed.empty()) { dehashed += "__DOT__"; } last_dot_pos = next_dot_pos + DOT_LEN; } else { last_dot_pos = string::npos; From a1cd55225c5261f7b780c8a7186804861e919187 Mon Sep 17 00:00:00 2001 From: Todd Strader Date: Wed, 21 Apr 2021 08:09:19 -0400 Subject: [PATCH 102/110] more vpi_get_str() (#2894) --- include/verilated_vpi.cpp | 225 ++++++++++++++++++++++++++++++-------- 1 file changed, 178 insertions(+), 47 deletions(-) diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 39fb58b7d..01412094f 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -862,40 +862,40 @@ const char* VerilatedVpiError::strFromVpiObjType(PLI_INT32 vpiVal) VL_MT_SAFE { "vpiVarSelect", "vpiWait", "vpiWhile", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", + "vpiCondition", + "vpiDelay", + "vpiElseStmt", + "vpiForIncStmt", + "vpiForInitStmt", + "vpiHighConn", + "vpiLhs", + "vpiIndex", + "vpiLeftRange", + "vpiLowConn", + "vpiParent", + "vpiRhs", + "vpiRightRange", + "vpiScope", + "vpiSysTfCall", + "vpiTchkDataTerm", + "vpiTchkNotifier", + "vpiTchkRefTerm", + "vpiArgument", + "vpiBit", + "vpiDriver", + "vpiInternalScope", + "vpiLoad", + "vpiModDataPathIn", + "vpiModPathIn", + "vpiModPathOut", + "vpiOperand", + "vpiPortInst", + "vpiProcess", + "vpiVariables", + "vpiUse", + "vpiExpr", + "vpiPrimitive", + "vpiStmt", "vpiAttribute", "vpiBitSelect", "vpiCallback", @@ -910,27 +910,28 @@ const char* VerilatedVpiError::strFromVpiObjType(PLI_INT32 vpiVal) VL_MT_SAFE { "vpiRegArray", "vpiSwitchArray", "vpiUdpArray", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", - "*undefined*", + "vpiActiveTimeFormat", + "vpiInTerm", + "vpiInstanceArray", + "vpiLocalDriver", + "vpiLocalLoad", + "vpiOutTerm", + "vpiPorts", + "vpiSimNet", + "vpiTaskFunc", "vpiContAssignBit", "vpiNamedEventArray", "vpiIndexedPartSelect", - "*undefined*", - "*undefined*", + "vpiBaseExpr", + "vpiWidthExpr", "vpiGenScopeArray", "vpiGenScope", - "vpiGenVar" + "vpiGenVar", + "vpiAutomatics" }; // clang-format on if (VL_UNCOVERABLE(vpiVal < 0)) return names[0]; - return names[(vpiVal <= vpiGenVar) ? vpiVal : 0]; + return names[(vpiVal <= vpiAutomatics) ? vpiVal : 0]; } const char* VerilatedVpiError::strFromVpiMethod(PLI_INT32 vpiVal) VL_MT_SAFE { // clang-format off @@ -1121,11 +1122,141 @@ void VerilatedVpiError::selfTest() VL_MT_UNSAFE_ONE { SELF_CHECK_ENUM_STR(strFromVpiVal, vpiRawFourStateVal); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAlways); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAssignStmt); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAssignment); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBegin); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCase); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCaseItem); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiConstant); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiContAssign); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDeassign); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDefParam); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDelayControl); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDisable); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiEventControl); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiEventStmt); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFor); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiForce); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiForever); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFork); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFuncCall); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFunction); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGate); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIf); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIfElse); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInitial); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIntegerVar); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInterModPath); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIterator); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIODecl); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiMemory); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiMemoryWord); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModPath); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModule); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNamedBegin); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNamedEvent); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNamedFork); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNet); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNetBit); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNullStmt); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiOperation); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiParamAssign); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiParameter); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPartSelect); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPathTerm); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPort); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPortBit); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPrimTerm); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRealVar); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiReg); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRegBit); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRelease); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRepeat); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRepeatControl); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSchedEvent); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSpecParam); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSwitch); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSysFuncCall); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSysTaskCall); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTableEntry); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTask); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTaskCall); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchk); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchkTerm); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTimeVar); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTimeQueue); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUdp); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUdpDefn); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUserSystf); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiVarSelect); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiWait); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiWhile); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCondition); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDelay); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiElseStmt); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiForIncStmt); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiForInitStmt); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiHighConn); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLhs); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIndex); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLeftRange); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLowConn); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiParent); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRhs); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRightRange); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiScope); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSysTfCall); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchkDataTerm); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchkNotifier); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTchkRefTerm); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiArgument); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBit); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDriver); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInternalScope); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLoad); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModDataPathIn); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModPathIn); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModPathOut); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiOperand); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPortInst); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiProcess); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiVariables); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUse); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiExpr); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPrimitive); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiStmt); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAttribute); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBitSelect); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiCallback); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDelayTerm); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiDelayDevice); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiFrame); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGateArray); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiModuleArray); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPrimitiveArray); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNetArray); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRange); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiRegArray); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSwitchArray); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiUdpArray); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiActiveTimeFormat); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInTerm); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiInstanceArray); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLocalDriver); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiLocalLoad); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiOutTerm); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiPorts); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiSimNet); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiTaskFunc); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiContAssignBit); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiNamedEventArray); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiIndexedPartSelect); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiBaseExpr); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiWidthExpr); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGenScopeArray); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGenScope); SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiGenVar); + SELF_CHECK_ENUM_STR(strFromVpiObjType, vpiAutomatics); SELF_CHECK_ENUM_STR(strFromVpiMethod, vpiCondition); SELF_CHECK_ENUM_STR(strFromVpiMethod, vpiStmt); From dd0c2cac9b7b2befa5f4ee3cbac35fab57e879aa Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 21 Apr 2021 09:21:06 -0400 Subject: [PATCH 103/110] Fix V3Premit infinite loop on always read-and-write (#2898). --- Changes | 1 + src/V3Premit.cpp | 2 ++ test_regress/t/t_premit_rw.pl | 21 +++++++++++++++++++++ test_regress/t/t_premit_rw.v | 31 +++++++++++++++++++++++++++++++ 4 files changed, 55 insertions(+) create mode 100755 test_regress/t/t_premit_rw.pl create mode 100644 test_regress/t/t_premit_rw.v diff --git a/Changes b/Changes index 5ffac9a75..e605d1378 100644 --- a/Changes +++ b/Changes @@ -36,6 +36,7 @@ Verilator 4.201 devel * Fix Cygwin example compile issues (#2856). [Mark Shaw] * Fix select of with index variable (#2880). [Alexander Grobman] * Fix cmake version number to be numeric (#2881). [Yuri Victorovich] +* Fix V3Premit infinite loop on always read-and-write (#2898). [Raynard Qiao] Verilator 4.200 2021-03-12 diff --git a/src/V3Premit.cpp b/src/V3Premit.cpp index 465bc93b5..97bb3357f 100644 --- a/src/V3Premit.cpp +++ b/src/V3Premit.cpp @@ -167,6 +167,7 @@ private: } void createDeepTemp(AstNode* nodep, bool noSubst) { + if (nodep->user1()) return; if (debug() > 8) nodep->dumpTree(cout, "deepin:"); AstNRelinker linker; @@ -224,6 +225,7 @@ private: { bool noopt = PremitAssignVisitor(nodep).noOpt(); if (noopt && !nodep->user1()) { + nodep->user1(true); // Need to do this even if not wide, as e.g. a select may be on a wide operator UINFO(4, "Deep temp for LHS/RHS\n"); createDeepTemp(nodep->rhsp(), false); diff --git a/test_regress/t/t_premit_rw.pl b/test_regress/t/t_premit_rw.pl new file mode 100755 index 000000000..691e0fb35 --- /dev/null +++ b/test_regress/t/t_premit_rw.pl @@ -0,0 +1,21 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2021 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +#execute( +# check_finished => 1, +# ); + +ok(1); +1; diff --git a/test_regress/t/t_premit_rw.v b/test_regress/t/t_premit_rw.v new file mode 100644 index 000000000..ba7872a43 --- /dev/null +++ b/test_regress/t/t_premit_rw.v @@ -0,0 +1,31 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2021 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +typedef struct packed { + logic car_enable; + logic [3-1:0] car_rpv; + logic [2-1:0] car_sn; +} car_s; + +module t (/*AUTOARG*/ + // Outputs + action, + // Inputs + rsp + ); + input rsp; + output action; + car_s rsp; + car_s action; + always @(*) begin + action = rsp; + if (rsp.car_enable == 1'b1) begin + action.car_rpv[ action.car_sn] = 1'b0; // causing problem + // OK + //action.car_rpv[ rsp.car_sn] = 1'b0; + end + end +endmodule From f450d51de1380b11fcb0a4224a1247835a181899 Mon Sep 17 00:00:00 2001 From: Todd Strader Date: Wed, 21 Apr 2021 12:35:18 -0400 Subject: [PATCH 104/110] expose packed vectors via the VPI (#2900) --- src/V3EmitCSyms.cpp | 2 +- test_regress/t/t_vpi_get.cpp | 1 + test_regress/t/t_vpi_get.v | 3 ++- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/V3EmitCSyms.cpp b/src/V3EmitCSyms.cpp index 8661ac966..bf3953e8e 100644 --- a/src/V3EmitCSyms.cpp +++ b/src/V3EmitCSyms.cpp @@ -789,7 +789,7 @@ void EmitCSyms::emitSymImp() { } } // - if (pdim > 1 || udim > 1) { + if (udim > 1 && (pdim && udim)) { puts("//UNSUP "); // VerilatedImp can't deal with >2d or packed arrays } puts(protect("__Vscope_" + it->second.m_scopeName) + ".varInsert(__Vfinal,"); diff --git a/test_regress/t/t_vpi_get.cpp b/test_regress/t/t_vpi_get.cpp index b07104480..5e7e2b83e 100644 --- a/test_regress/t/t_vpi_get.cpp +++ b/test_regress/t/t_vpi_get.cpp @@ -168,6 +168,7 @@ int mon_check_props() { {"testout", {24, vpiOutput, 0, vpiPort}, {0, 0, 0, 0}}, {"sub.subin", {1, vpiInput, 1, vpiPort}, {0, 0, 0, 0}}, {"sub.subout", {1, vpiOutput, 1, vpiPort}, {0, 0, 0, 0}}, + {"twobytwo", {2, vpiNoDirection, 0, vpiMemory}, {2, vpiNoDirection, 0, vpiMemoryWord}}, {NULL, {0, 0, 0, 0}, {0, 0, 0, 0}}}; struct params* value = values; while (value->signal) { diff --git a/test_regress/t/t_vpi_get.v b/test_regress/t/t_vpi_get.v index 0782339c1..fe22e9e95 100644 --- a/test_regress/t/t_vpi_get.v +++ b/test_regress/t/t_vpi_get.v @@ -42,12 +42,13 @@ extern "C" int mon_check(); reg [2:1] twoone `PUBLIC_FLAT_RW; reg onetwo [1:2] `PUBLIC_FLAT_RW; reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW; + reg [1:0] [1:0] twobytwo `PUBLIC_FLAT_RW; integer status; `ifdef IVERILOG // stop icarus optimizing signals away - wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3]; + wire redundant = onebit | onetwo[1] | twoone | fourthreetwoone[3] | twobytwo; `endif wire subin `PUBLIC_FLAT_RD; From f44629527474d5e598e4c2a33f70cbf606dc0de8 Mon Sep 17 00:00:00 2001 From: Todd Strader Date: Wed, 21 Apr 2021 13:46:13 -0400 Subject: [PATCH 105/110] Public interface params (#2901) --- include/verilated_vpi.cpp | 80 +++++++++++++++++++----------------- src/V3LinkParse.cpp | 2 + test_regress/t/t_vpi_get.cpp | 7 +++- test_regress/t/t_vpi_get.v | 13 +++++- 4 files changed, 61 insertions(+), 41 deletions(-) diff --git a/include/verilated_vpi.cpp b/include/verilated_vpi.cpp index 01412094f..c3346429e 100644 --- a/include/verilated_vpi.cpp +++ b/include/verilated_vpi.cpp @@ -171,23 +171,32 @@ public: vlsint32_t num() const { return m_num; } }; -class VerilatedVpioParam final : public VerilatedVpio { - const VerilatedVar* m_varp; - const VerilatedScope* m_scopep; +class VerilatedVpioVarBase VL_NOT_FINAL : public VerilatedVpio { +protected: + const VerilatedVar* m_varp = nullptr; + const VerilatedScope* m_scopep = nullptr; + const VerilatedRange& get_range() const { + // Determine number of dimensions and return outermost + return (m_varp->dims() > 1) ? m_varp->unpacked() : m_varp->packed(); + } public: - VerilatedVpioParam(const VerilatedVar* varp, const VerilatedScope* scopep) + VerilatedVpioVarBase(const VerilatedVar* varp, const VerilatedScope* scopep) : m_varp{varp} , m_scopep{scopep} {} - virtual ~VerilatedVpioParam() override = default; - - static VerilatedVpioParam* castp(vpiHandle h) { - return dynamic_cast(reinterpret_cast(h)); + explicit VerilatedVpioVarBase(const VerilatedVpioVarBase* varp) { + if (varp) { + m_varp = varp->m_varp; + m_scopep = varp->m_scopep; + } + } + static VerilatedVpioVarBase* castp(vpiHandle h) { + return dynamic_cast(reinterpret_cast(h)); } - virtual vluint32_t type() const override { return vpiParameter; } const VerilatedVar* varp() const { return m_varp; } - void* varDatap() const { return m_varp->datap(); } const VerilatedScope* scopep() const { return m_scopep; } + virtual vluint32_t size() const override { return get_range().elements(); } + virtual const VerilatedRange* rangep() const override { return &get_range(); } virtual const char* name() const override { return m_varp->name(); } virtual const char* fullname() const override { static VL_THREAD_LOCAL std::string t_out; @@ -196,6 +205,19 @@ public: } }; +class VerilatedVpioParam final : public VerilatedVpioVarBase { +public: + VerilatedVpioParam(const VerilatedVar* varp, const VerilatedScope* scopep) + : VerilatedVpioVarBase(varp, scopep) {} + virtual ~VerilatedVpioParam() override = default; + + static VerilatedVpioParam* castp(vpiHandle h) { + return dynamic_cast(reinterpret_cast(h)); + } + virtual vluint32_t type() const override { return vpiParameter; } + void* varDatap() const { return m_varp->datap(); } +}; + class VerilatedVpioRange final : public VerilatedVpio { const VerilatedRange* m_range; @@ -251,9 +273,7 @@ public: virtual const char* fullname() const override { return m_scopep->name(); } }; -class VerilatedVpioVar VL_NOT_FINAL : public VerilatedVpio { - const VerilatedVar* m_varp = nullptr; - const VerilatedScope* m_scopep = nullptr; +class VerilatedVpioVar VL_NOT_FINAL : public VerilatedVpioVarBase { vluint8_t* m_prevDatap = nullptr; // Previous value of data, for cbValueChange union { vluint8_t u8[4]; @@ -263,23 +283,17 @@ class VerilatedVpioVar VL_NOT_FINAL : public VerilatedVpio { protected: void* m_varDatap = nullptr; // varp()->datap() adjusted for array entries vlsint32_t m_index = 0; - const VerilatedRange& get_range() const { - // Determine number of dimensions and return outermost - return (m_varp->dims() > 1) ? m_varp->unpacked() : m_varp->packed(); - } public: VerilatedVpioVar(const VerilatedVar* varp, const VerilatedScope* scopep) - : m_varp{varp} - , m_scopep{scopep} { + : VerilatedVpioVarBase(varp, scopep) { m_mask.u32 = VL_MASK_I(varp->packed().elements()); m_entSize = varp->entSize(); m_varDatap = varp->datap(); } - explicit VerilatedVpioVar(const VerilatedVpioVar* varp) { + explicit VerilatedVpioVar(const VerilatedVpioVar* varp) + : VerilatedVpioVarBase(varp) { if (varp) { - m_varp = varp->m_varp; - m_scopep = varp->m_scopep; m_mask.u32 = varp->m_mask.u32; m_entSize = varp->m_entSize; m_varDatap = varp->m_varDatap; @@ -295,8 +309,6 @@ public: static VerilatedVpioVar* castp(vpiHandle h) { return dynamic_cast(reinterpret_cast(h)); } - const VerilatedVar* varp() const { return m_varp; } - const VerilatedScope* scopep() const { return m_scopep; } vluint32_t mask() const { return m_mask.u32; } vluint8_t mask_byte(int idx) { return m_mask.u8[idx & 3]; } vluint32_t entSize() const { return m_entSize; } @@ -304,14 +316,6 @@ public: virtual vluint32_t type() const override { return (varp()->dims() > 1) ? vpiMemory : vpiReg; // but might be wire, logic } - virtual vluint32_t size() const override { return get_range().elements(); } - virtual const VerilatedRange* rangep() const override { return &get_range(); } - virtual const char* name() const override { return m_varp->name(); } - virtual const char* fullname() const override { - static VL_THREAD_LOCAL std::string t_out; - t_out = std::string(m_scopep->name()) + "." + name(); - return t_out.c_str(); - } void* prevDatap() const { return m_prevDatap; } void* varDatap() const { return m_varDatap; } void createPrevDatap() { @@ -1433,7 +1437,7 @@ vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { VL_VPI_ERROR_RESET_(); switch (type) { case vpiLeftRange: { - if (VerilatedVpioVar* vop = VerilatedVpioVar::castp(object)) { + if (VerilatedVpioVarBase* vop = VerilatedVpioVarBase::castp(object)) { if (VL_UNLIKELY(!vop->rangep())) return nullptr; return (new VerilatedVpioConst(vop->rangep()->left()))->castVpiHandle(); } else if (VerilatedVpioRange* vop = VerilatedVpioRange::castp(object)) { @@ -1446,7 +1450,7 @@ vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { return nullptr; } case vpiRightRange: { - if (VerilatedVpioVar* vop = VerilatedVpioVar::castp(object)) { + if (VerilatedVpioVarBase* vop = VerilatedVpioVarBase::castp(object)) { if (VL_UNLIKELY(!vop->rangep())) return nullptr; return (new VerilatedVpioConst(vop->rangep()->right()))->castVpiHandle(); } else if (VerilatedVpioRange* vop = VerilatedVpioRange::castp(object)) { @@ -1464,7 +1468,7 @@ vpiHandle vpi_handle(PLI_INT32 type, vpiHandle object) { return (new VerilatedVpioConst(vop->index()))->castVpiHandle(); } case vpiScope: { - VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); + VerilatedVpioVarBase* vop = VerilatedVpioVarBase::castp(object); if (VL_UNLIKELY(!vop)) return nullptr; return (new VerilatedVpioScope(vop->scopep()))->castVpiHandle(); } @@ -1568,18 +1572,18 @@ PLI_INT32 vpi_get(PLI_INT32 property, vpiHandle object) { } case vpiDirection: { // By forthought, the directions already are vpi enumerated - VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); + VerilatedVpioVarBase* vop = VerilatedVpioVarBase::castp(object); if (VL_UNLIKELY(!vop)) return 0; return vop->varp()->vldir(); } case vpiScalar: // FALLTHRU case vpiVector: { - VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); + VerilatedVpioVarBase* vop = VerilatedVpioVarBase::castp(object); if (VL_UNLIKELY(!vop)) return 0; return (property == vpiVector) ^ (vop->varp()->dims() == 0); } case vpiSize: { - VerilatedVpioVar* vop = VerilatedVpioVar::castp(object); + VerilatedVpioVarBase* vop = VerilatedVpioVarBase::castp(object); if (VL_UNLIKELY(!vop)) return 0; return vop->size(); } diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp index 73af3f7ca..7744e6bfb 100644 --- a/src/V3LinkParse.cpp +++ b/src/V3LinkParse.cpp @@ -218,6 +218,8 @@ private: if (v3Global.opt.publicFlatRW()) { switch (nodep->varType()) { case AstVarType::VAR: // FALLTHRU + case AstVarType::GPARAM: // FALLTHRU + case AstVarType::LPARAM: // FALLTHRU case AstVarType::PORT: // FALLTHRU case AstVarType::WIRE: nodep->sigUserRWPublic(true); break; default: break; diff --git a/test_regress/t/t_vpi_get.cpp b/test_regress/t/t_vpi_get.cpp index 5e7e2b83e..fa97e5095 100644 --- a/test_regress/t/t_vpi_get.cpp +++ b/test_regress/t/t_vpi_get.cpp @@ -163,18 +163,23 @@ int mon_check_props() { {"fourthreetwoone", {2, vpiNoDirection, 0, vpiMemory}, {2, vpiNoDirection, 0, vpiMemoryWord}}, + {"theint", {32, vpiNoDirection, 0, vpiReg}, {0, 0, 0, 0}}, {"clk", {1, vpiInput, 1, vpiPort}, {0, 0, 0, 0}}, {"testin", {16, vpiInput, 0, vpiPort}, {0, 0, 0, 0}}, {"testout", {24, vpiOutput, 0, vpiPort}, {0, 0, 0, 0}}, {"sub.subin", {1, vpiInput, 1, vpiPort}, {0, 0, 0, 0}}, {"sub.subout", {1, vpiOutput, 1, vpiPort}, {0, 0, 0, 0}}, + {"sub.subparam", {32, vpiNoDirection, 0, vpiParameter}, {0, 0, 0, 0}}, + {"sub.the_intf.bytesig", {8, vpiNoDirection, 0, vpiReg}, {0, 0, 0, 0}}, + {"sub.the_intf.param", {32, vpiNoDirection, 0, vpiParameter}, {0, 0, 0, 0}}, + {"sub.the_intf.lparam", {32, vpiNoDirection, 0, vpiParameter}, {0, 0, 0, 0}}, {"twobytwo", {2, vpiNoDirection, 0, vpiMemory}, {2, vpiNoDirection, 0, vpiMemoryWord}}, {NULL, {0, 0, 0, 0}, {0, 0, 0, 0}}}; struct params* value = values; while (value->signal) { TestVpiHandle h = VPI_HANDLE(value->signal); - CHECK_RESULT_NZ(h); TEST_MSG("%s\n", value->signal); + CHECK_RESULT_NZ(h); if (int status = _mon_check_props(h, value->attributes.size, value->attributes.direction, value->attributes.scalar, value->attributes.type)) return status; diff --git a/test_regress/t/t_vpi_get.v b/test_regress/t/t_vpi_get.v index fe22e9e95..b52f87282 100644 --- a/test_regress/t/t_vpi_get.v +++ b/test_regress/t/t_vpi_get.v @@ -22,6 +22,11 @@ import "DPI-C" function void dpi_print(input string somestring); `define PUBLIC_FLAT_RW `endif +interface intf #(parameter int param `PUBLIC_FLAT_RD = 7); + localparam int lparam `PUBLIC_FLAT_RD = param + 1; + logic [7:0] bytesig `PUBLIC_FLAT_RD; +endinterface + module t (/*AUTOARG*/ // Inputs input clk `PUBLIC_FLAT_RD, @@ -43,6 +48,7 @@ extern "C" int mon_check(); reg onetwo [1:2] `PUBLIC_FLAT_RW; reg [2:1] fourthreetwoone[4:3] `PUBLIC_FLAT_RW; reg [1:0] [1:0] twobytwo `PUBLIC_FLAT_RW; + int theint `PUBLIC_FLAT_RW; integer status; @@ -68,7 +74,7 @@ extern "C" int mon_check(); status = mon_check(); `endif if (status!=0) begin - $write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status); + $write("%%Error: t_vpi_get.cpp:%0d: C Test failed\n", status); $stop; end $write("*-* All Finished *-*\n"); @@ -77,8 +83,11 @@ extern "C" int mon_check(); endmodule : t -module sub ( +module sub #( + parameter int subparam `PUBLIC_FLAT_RD = 2 +) ( input subin `PUBLIC_FLAT_RD, output subout `PUBLIC_FLAT_RD ); + intf the_intf(); endmodule : sub From 15802dadf1510adc1150ca4db71a4a62d8511be5 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 24 Apr 2021 09:23:53 -0400 Subject: [PATCH 106/110] Commentary --- Changes | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index e605d1378..d7ab1ecfe 100644 --- a/Changes +++ b/Changes @@ -14,29 +14,42 @@ Verilator 4.201 devel **Major:** * Documentation has been rewritten into a book format. +* Verilated signals now use VlWide and VlPacked in place of C arrays. **Minor:** * Add an URL on warnings to point to the manual's description. * Add EOFNEWLINE warning when missing a newline at EOF. * Changed TIMESCALEMOD from error into a warning. -* Verilated signals now use VlWide and VlPacked in place of C arrays. * Mark --no-relative-cfuncs as scheduled for deprecation. * Add --coverage-max-width (#2853). [xuejiazidi] * Add VerilatedCovContext::forcePerInstance (#2793). [Kevin Laeufer] +* Add FST SystemC tracing (#2806). [Alex Torregrosa] +* Add PINNOTFOUND warning in place of error (#2868). [Udi Finkelstein] +* Support overlaps in priority case statements (#2864). [Rupert Swarbrick] +* Support for null ports (#2875). [Udi Finkelstein] * Fix class unpacked-array compile error (#2774). [Iru Cai] +* Fix scope types in FST and VCD traces (#2805). [Alex Torregrosa] * Fix exceeding command-line ar limit (#2834). [Yinan Xu] * Fix false $dumpfile warning on model save (#2834). [Yinan Xu] * Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett] * Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett] * Fix --output-split with class extends (#2839). [Iru Cai] * Fix false WIDTHCONCAT on casted constant (#2849). [Rupert Swarbrick] +* Fix tracing of long hashed names (#2854). [Graham Rushton] * Fix --public-flat-rw / DPI issue (#2858). [Todd Strader] * Fix interface localparam access (#2859). [Todd Strader] * Fix Cygwin example compile issues (#2856). [Mark Shaw] * Fix select of with index variable (#2880). [Alexander Grobman] * Fix cmake version number to be numeric (#2881). [Yuri Victorovich] +* Fix MinGW not supportting 'localtime_r' (#2882). [HyungKi Jeong] +* Fix cast from packed, typedef'ed interface signal (#2884). [Todd Strader] +* Fix VPI package reported as vpiModule (#2885). [Todd Strader] +* Fix dumping waveforms to multiple FST files (#2889). [David Metz] +* Fix assertion failure in bitOpTree (#2892). [Yutetsu TAKATSUKASA] * Fix V3Premit infinite loop on always read-and-write (#2898). [Raynard Qiao] +* Fix VPI packed vectors (#2900). [Todd Strader] +* Fix VPI public interface parameters (#2901). [Todd Strader] Verilator 4.200 2021-03-12 From 82b878ce423b0a1cc4e462a88eb69641850b04b0 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 24 Apr 2021 09:38:38 -0400 Subject: [PATCH 107/110] Internal coverage: locally download codecov script for security (#2904) --- ci/ci-script.bash | 4 +- ci/coverage-upload.sh | 1884 +++++++++++++++++++++++++++++++++++++++++ nodist/code_coverage | 2 +- 3 files changed, 1887 insertions(+), 3 deletions(-) create mode 100755 ci/coverage-upload.sh diff --git a/ci/ci-script.bash b/ci/ci-script.bash index c8a822d5c..498531eed 100755 --- a/ci/ci-script.bash +++ b/ci/ci-script.bash @@ -166,9 +166,9 @@ elif [ "$CI_BUILD_STAGE_NAME" = "test" ]; then fatal "Unknown test: $TESTS" ;; esac - # Upload coverage data to codecov.io + # Upload coverage data if [[ $TESTS == coverage-* ]]; then - bash <(curl -s https://codecov.io/bash) -f nodist/obj_dir/coverage/app_total.info + bash <(cat ci/coverage-upload.sh) -f nodist/obj_dir/coverage/app_total.info fi else ############################################################################## diff --git a/ci/coverage-upload.sh b/ci/coverage-upload.sh new file mode 100755 index 000000000..9c5514092 --- /dev/null +++ b/ci/coverage-upload.sh @@ -0,0 +1,1884 @@ +#!/usr/bin/env bash + +# Apache License Version 2.0, January 2004 +# https://github.com/codecov/codecov-bash/blob/master/LICENSE + +set -e +o pipefail + +VERSION="1.0.2" + +codecov_flags=( ) +url="https://codecov.io" +env="$CODECOV_ENV" +service="" +token="" +search_in="" +# shellcheck disable=SC2153 +flags="$CODECOV_FLAGS" +exit_with=0 +curlargs="" +curlawsargs="" +dump="0" +clean="0" +curl_s="-s" +name="$CODECOV_NAME" +include_cov="" +exclude_cov="" +ddp="$HOME/Library/Developer/Xcode/DerivedData" +xp="" +files="" +save_to="" +direct_file_upload="" +cacert="$CODECOV_CA_BUNDLE" +gcov_ignore="-not -path './bower_components/**' -not -path './node_modules/**' -not -path './vendor/**'" +gcov_include="" + +ft_gcov="1" +ft_coveragepy="1" +ft_fix="1" +ft_search="1" +ft_s3="1" +ft_network="1" +ft_xcodellvm="1" +ft_xcodeplist="0" +ft_gcovout="1" +ft_html="0" +ft_yaml="0" + +_git_root=$(git rev-parse --show-toplevel 2>/dev/null || hg root 2>/dev/null || echo "$PWD") +git_root="$_git_root" +remote_addr="" +if [ "$git_root" = "$PWD" ]; +then + git_root="." +fi + +branch_o="" +build_o="" +commit_o="" +pr_o="" +prefix_o="" +network_filter_o="" +search_in_o="" +slug_o="" +tag_o="" +url_o="" +git_ls_files_recurse_submodules_o="" +package="bash" + +commit="$VCS_COMMIT_ID" +branch="$VCS_BRANCH_NAME" +pr="$VCS_PULL_REQUEST" +slug="$VCS_SLUG" +tag="$VCS_TAG" +build_url="$CI_BUILD_URL" +build="$CI_BUILD_ID" +job="$CI_JOB_ID" + +beta_xcode_partials="" + +proj_root="$git_root" +gcov_exe="gcov" +gcov_arg="" + +b="\033[0;36m" +g="\033[0;32m" +r="\033[0;31m" +e="\033[0;90m" +y="\033[0;33m" +x="\033[0m" + +show_help() { +cat << EOF + + Codecov Bash $VERSION + + Global report uploading tool for Codecov + Documentation at https://docs.codecov.io/docs + Contribute at https://github.com/codecov/codecov-bash + + + -h Display this help and exit + -f FILE Target file(s) to upload + + -f "path/to/file" only upload this file + skips searching unless provided patterns below + + -f '!*.bar' ignore all files at pattern *.bar + -f '*.foo' include all files at pattern *.foo + Must use single quotes. + This is non-exclusive, use -s "*.foo" to match specific paths. + + -s DIR Directory to search for coverage reports. + Already searches project root and artifact folders. + -t TOKEN Set the private repository token + (option) set environment variable CODECOV_TOKEN=:uuid + + -t @/path/to/token_file + -t uuid + + -n NAME Custom defined name of the upload. Visible in Codecov UI + + -e ENV Specify environment variables to be included with this build + Also accepting environment variables: CODECOV_ENV=VAR,VAR2 + + -e VAR,VAR2 + + -k prefix Prefix filepaths to help resolve path fixing + + -i prefix Only include files in the network with a certain prefix. Useful for upload-specific path fixing + + -X feature Toggle functionalities + + -X gcov Disable gcov + -X coveragepy Disable python coverage + -X fix Disable report fixing + -X search Disable searching for reports + -X xcode Disable xcode processing + -X network Disable uploading the file network + -X gcovout Disable gcov output + -X html Enable coverage for HTML files + -X recursesubs Enable recurse submodules in git projects when searching for source files + -X yaml Enable coverage for YAML files + + -N The commit SHA of the parent for which you are uploading coverage. If not present, + the parent will be determined using the API of your repository provider. + When using the repository provider's API, the parent is determined via finding + the closest ancestor to the commit. + + -R root dir Used when not in git/hg project to identify project root directory + -F flag Flag the upload to group coverage metrics + + -F unittests This upload is only unittests + -F integration This upload is only integration tests + -F ui,chrome This upload is Chrome - UI tests + + -c Move discovered coverage reports to the trash + -z FILE Upload specified file directly to Codecov and bypass all report generation. + This is inteded to be used only with a pre-formatted Codecov report and is not + expected to work under any other circumstances. + -Z Exit with 1 if not successful. Default will Exit with 0 + + -- xcode -- + -D Custom Derived Data Path for Coverage.profdata and gcov processing + Default '~/Library/Developer/Xcode/DerivedData' + -J Specify packages to build coverage. Uploader will only build these packages. + This can significantly reduces time to build coverage reports. + + -J 'MyAppName' Will match "MyAppName" and "MyAppNameTests" + -J '^ExampleApp$' Will match only "ExampleApp" not "ExampleAppTests" + + -- gcov -- + -g GLOB Paths to ignore during gcov gathering + -G GLOB Paths to include during gcov gathering + -p dir Project root directory + Also used when preparing gcov + -x gcovexe gcov executable to run. Defaults to 'gcov' + -a gcovargs extra arguments to pass to gcov + + -- Override CI Environment Variables -- + These variables are automatically detected by popular CI providers + + -B branch Specify the branch name + -C sha Specify the commit sha + -P pr Specify the pull request number + -b build Specify the build number + -T tag Specify the git tag + + -- Enterprise -- + -u URL Set the target url for Enterprise customers + Not required when retrieving the bash uploader from your CCE + (option) Set environment variable CODECOV_URL=https://my-hosted-codecov.com + -r SLUG owner/repo slug used instead of the private repo token in Enterprise + (option) set environment variable CODECOV_SLUG=:owner/:repo + (option) set in your codecov.yml "codecov.slug" + -S PATH File path to your cacert.pem file used to verify ssl with Codecov Enterprise (optional) + (option) Set environment variable: CODECOV_CA_BUNDLE="/path/to/ca.pem" + -U curlargs Extra curl arguments to communicate with Codecov. e.g., -U "--proxy http://http-proxy" + -A curlargs Extra curl arguments to communicate with AWS. + + -- Debugging -- + -d Don't upload, but dump upload file to stdout + -q PATH Write upload file to path + -K Remove color from the output + -v Verbose mode + +EOF +} + + +say() { + echo -e "$1" +} + + +urlencode() { + echo "$1" | curl -Gso /dev/null -w "%{url_effective}" --data-urlencode @- "" | cut -c 3- | sed -e 's/%0A//' +} + +swiftcov() { + _dir=$(dirname "$1" | sed 's/\(Build\).*/\1/g') + for _type in app framework xctest + do + find "$_dir" -name "*.$_type" | while read -r f + do + _proj=${f##*/} + _proj=${_proj%."$_type"} + if [ "$2" = "" ] || [ "$(echo "$_proj" | grep -i "$2")" != "" ]; + then + say " $g+$x Building reports for $_proj $_type" + dest=$([ -f "$f/$_proj" ] && echo "$f/$_proj" || echo "$f/Contents/MacOS/$_proj") + # shellcheck disable=SC2001 + _proj_name=$(echo "$_proj" | sed -e 's/[[:space:]]//g') + # shellcheck disable=SC2086 + xcrun llvm-cov show $beta_xcode_partials -instr-profile "$1" "$dest" > "$_proj_name.$_type.coverage.txt" \ + || say " ${r}x>${x} llvm-cov failed to produce results for $dest" + fi + done + done +} + + +# Credits to: https://gist.github.com/pkuczynski/8665367 +parse_yaml() { + local prefix=$2 + local s='[[:space:]]*' w='[a-zA-Z0-9_]*' + local fs + fs=$(echo @|tr @ '\034') + sed -ne "s|^\($s\)\($w\)$s:$s\"\(.*\)\"$s\$|\1$fs\2$fs\3|p" \ + -e "s|^\($s\)\($w\)$s:$s\(.*\)$s\$|\1$fs\2$fs\3|p" "$1" | + awk -F"$fs" '{ + indent = length($1)/2; + vname[indent] = $2; + for (i in vname) {if (i > indent) {delete vname[i]}} + if (length($3) > 0) { + vn=""; if (indent > 0) {vn=(vn)(vname[0])("_")} + printf("%s%s%s=\"%s\"\n", "'"$prefix"'",vn, $2, $3); + } + }' +} + +if [ $# != 0 ]; +then + while getopts "a:A:b:B:cC:dD:e:f:F:g:G:hi:J:k:Kn:p:P:Q:q:r:R:s:S:t:T:u:U:vx:X:Zz:N:-" o + do + codecov_flags+=( "$o" ) + case "$o" in + "-") + echo -e "${r}Long options are not supported${x}" + exit 2 + ;; + "?") + ;; + "N") + parent=$OPTARG + ;; + "a") + gcov_arg=$OPTARG + ;; + "A") + curlawsargs="$OPTARG" + ;; + "b") + build_o="$OPTARG" + ;; + "B") + branch_o="$OPTARG" + ;; + "c") + clean="1" + ;; + "C") + commit_o="$OPTARG" + ;; + "d") + dump="1" + ;; + "D") + ddp="$OPTARG" + ;; + "e") + env="$env,$OPTARG" + ;; + "f") + if [ "${OPTARG::1}" = "!" ]; + then + exclude_cov="$exclude_cov -not -path '${OPTARG:1}'" + + elif [[ "$OPTARG" = *"*"* ]]; + then + include_cov="$include_cov -or -path '$OPTARG'" + + else + ft_search=0 + if [ "$files" = "" ]; + then + files="$OPTARG" + else + files="$files +$OPTARG" + fi + fi + ;; + "F") + if [ "$flags" = "" ]; + then + flags="$OPTARG" + else + flags="$flags,$OPTARG" + fi + ;; + "g") + gcov_ignore="$gcov_ignore -not -path '$OPTARG'" + ;; + "G") + gcov_include="$gcov_include -path '$OPTARG'" + ;; + "h") + show_help + exit 0; + ;; + "i") + network_filter_o="$OPTARG" + ;; + "J") + ft_xcodellvm="1" + ft_xcodeplist="0" + if [ "$xp" = "" ]; + then + xp="$OPTARG" + else + xp="$xp\|$OPTARG" + fi + ;; + "k") + prefix_o=$(echo "$OPTARG" | sed -e 's:^/*::' -e 's:/*$::') + ;; + "K") + b="" + g="" + r="" + e="" + x="" + ;; + "n") + name="$OPTARG" + ;; + "p") + proj_root="$OPTARG" + ;; + "P") + pr_o="$OPTARG" + ;; + "Q") + # this is only meant for Codecov packages to overwrite + package="$OPTARG" + ;; + "q") + save_to="$OPTARG" + ;; + "r") + slug_o="$OPTARG" + ;; + "R") + git_root="$OPTARG" + ;; + "s") + if [ "$search_in_o" = "" ]; + then + search_in_o="$OPTARG" + else + search_in_o="$search_in_o $OPTARG" + fi + ;; + "S") + # shellcheck disable=SC2089 + cacert="--cacert \"$OPTARG\"" + ;; + "t") + if [ "${OPTARG::1}" = "@" ]; + then + token=$(< "${OPTARG:1}" tr -d ' \n') + else + token="$OPTARG" + fi + ;; + "T") + tag_o="$OPTARG" + ;; + "u") + url_o=$(echo "$OPTARG" | sed -e 's/\/$//') + ;; + "U") + curlargs="$OPTARG" + ;; + "v") + set -x + curl_s="" + ;; + "x") + gcov_exe=$OPTARG + ;; + "X") + if [ "$OPTARG" = "gcov" ]; + then + ft_gcov="0" + elif [ "$OPTARG" = "coveragepy" ] || [ "$OPTARG" = "py" ]; + then + ft_coveragepy="0" + elif [ "$OPTARG" = "gcovout" ]; + then + ft_gcovout="0" + elif [ "$OPTARG" = "xcodellvm" ]; + then + ft_xcodellvm="1" + ft_xcodeplist="0" + elif [ "$OPTARG" = "fix" ] || [ "$OPTARG" = "fixes" ]; + then + ft_fix="0" + elif [ "$OPTARG" = "xcode" ]; + then + ft_xcodellvm="0" + ft_xcodeplist="0" + elif [ "$OPTARG" = "search" ]; + then + ft_search="0" + elif [ "$OPTARG" = "xcodepartials" ]; + then + beta_xcode_partials="-use-color" + elif [ "$OPTARG" = "network" ]; + then + ft_network="0" + elif [ "$OPTARG" = "s3" ]; + then + ft_s3="0" + elif [ "$OPTARG" = "html" ]; + then + ft_html="1" + elif [ "$OPTARG" = "recursesubs" ]; + then + git_ls_files_recurse_submodules_o="--recurse-submodules" + elif [ "$OPTARG" = "yaml" ]; + then + ft_yaml="1" + fi + ;; + "Z") + exit_with=1 + ;; + "z") + direct_file_upload="$OPTARG" + ft_gcov="0" + ft_coveragepy="0" + ft_fix="0" + ft_search="0" + ft_network="0" + ft_xcodellvm="0" + ft_gcovout="0" + include_cov="" + ;; + *) + echo -e "${r}Unexpected flag not supported${x}" + ;; + esac + done +fi + +say " + _____ _ + / ____| | | +| | ___ __| | ___ ___ _____ __ +| | / _ \\ / _\` |/ _ \\/ __/ _ \\ \\ / / +| |___| (_) | (_| | __/ (_| (_) \\ V / + \\_____\\___/ \\__,_|\\___|\\___\\___/ \\_/ + Bash-$VERSION + +" + +# check for installed tools +# git/hg +if [ "$direct_file_upload" = "" ]; +then + if [ -x "$(command -v git)" ]; + then + say "$b==>$x $(git --version) found" + else + say "$y==>$x git not installed, testing for mercurial" + if [ -x "$(command -v hg)" ]; + then + say "$b==>$x $(hg --version) found" + else + say "$r==>$x git nor mercurial are installed. Uploader may fail or have unintended consequences" + fi + fi +fi +# curl +if [ -x "$(command -v curl)" ]; +then + say "$b==>$x $(curl --version)" +else + say "$r==>$x curl not installed. Exiting." + exit ${exit_with}; +fi + +search_in="$proj_root" + +#shellcheck disable=SC2154 +if [ "$JENKINS_URL" != "" ]; +then + say "$e==>$x Jenkins CI detected." + # https://wiki.jenkins-ci.org/display/JENKINS/Building+a+software+project + # https://wiki.jenkins-ci.org/display/JENKINS/GitHub+pull+request+builder+plugin#GitHubpullrequestbuilderplugin-EnvironmentVariables + service="jenkins" + + # shellcheck disable=SC2154 + if [ "$ghprbSourceBranch" != "" ]; + then + branch="$ghprbSourceBranch" + elif [ "$GIT_BRANCH" != "" ]; + then + branch="$GIT_BRANCH" + elif [ "$BRANCH_NAME" != "" ]; + then + branch="$BRANCH_NAME" + fi + + # shellcheck disable=SC2154 + if [ "$ghprbActualCommit" != "" ]; + then + commit="$ghprbActualCommit" + elif [ "$GIT_COMMIT" != "" ]; + then + commit="$GIT_COMMIT" + fi + + # shellcheck disable=SC2154 + if [ "$ghprbPullId" != "" ]; + then + pr="$ghprbPullId" + elif [ "$CHANGE_ID" != "" ]; + then + pr="$CHANGE_ID" + fi + + build="$BUILD_NUMBER" + # shellcheck disable=SC2153 + build_url=$(urlencode "$BUILD_URL") + +elif [ "$CI" = "true" ] && [ "$TRAVIS" = "true" ] && [ "$SHIPPABLE" != "true" ]; +then + say "$e==>$x Travis CI detected." + # https://docs.travis-ci.com/user/environment-variables/ + service="travis" + commit="${TRAVIS_PULL_REQUEST_SHA:-$TRAVIS_COMMIT}" + build="$TRAVIS_JOB_NUMBER" + pr="$TRAVIS_PULL_REQUEST" + job="$TRAVIS_JOB_ID" + slug="$TRAVIS_REPO_SLUG" + env="$env,TRAVIS_OS_NAME" + tag="$TRAVIS_TAG" + if [ "$TRAVIS_BRANCH" != "$TRAVIS_TAG" ]; + then + branch="${TRAVIS_PULL_REQUEST_BRANCH:-$TRAVIS_BRANCH}" + fi + + language=$(compgen -A variable | grep "^TRAVIS_.*_VERSION$" | head -1) + if [ "$language" != "" ]; + then + env="$env,${!language}" + fi + +elif [ "$CODEBUILD_CI" = "true" ]; +then + say "$e==>$x AWS Codebuild detected." + # https://docs.aws.amazon.com/codebuild/latest/userguide/build-env-ref-env-vars.html + service="codebuild" + commit="$CODEBUILD_RESOLVED_SOURCE_VERSION" + build="$CODEBUILD_BUILD_ID" + branch="$(echo "$CODEBUILD_WEBHOOK_HEAD_REF" | sed 's/^refs\/heads\///')" + if [ "${CODEBUILD_SOURCE_VERSION/pr}" = "$CODEBUILD_SOURCE_VERSION" ] ; then + pr="false" + else + pr="$(echo "$CODEBUILD_SOURCE_VERSION" | sed 's/^pr\///')" + fi + job="$CODEBUILD_BUILD_ID" + slug="$(echo "$CODEBUILD_SOURCE_REPO_URL" | sed 's/^.*:\/\/[^\/]*\///' | sed 's/\.git$//')" + +elif [ "$CI" = "true" ] && [ "$CI_NAME" = "codeship" ]; +then + say "$e==>$x Codeship CI detected." + # https://www.codeship.io/documentation/continuous-integration/set-environment-variables/ + service="codeship" + branch="$CI_BRANCH" + build="$CI_BUILD_NUMBER" + build_url=$(urlencode "$CI_BUILD_URL") + commit="$CI_COMMIT_ID" + +elif [ -n "$CF_BUILD_URL" ] && [ -n "$CF_BUILD_ID" ]; +then + say "$e==>$x Codefresh CI detected." + # https://docs.codefresh.io/v1.0/docs/variables + service="codefresh" + branch="$CF_BRANCH" + build="$CF_BUILD_ID" + build_url=$(urlencode "$CF_BUILD_URL") + commit="$CF_REVISION" + +elif [ "$TEAMCITY_VERSION" != "" ]; +then + say "$e==>$x TeamCity CI detected." + # https://confluence.jetbrains.com/display/TCD8/Predefined+Build+Parameters + # https://confluence.jetbrains.com/plugins/servlet/mobile#content/view/74847298 + if [ "$TEAMCITY_BUILD_BRANCH" = '' ]; + then + echo " Teamcity does not automatically make build parameters available as environment variables." + echo " Add the following environment parameters to the build configuration" + echo " env.TEAMCITY_BUILD_BRANCH = %teamcity.build.branch%" + echo " env.TEAMCITY_BUILD_ID = %teamcity.build.id%" + echo " env.TEAMCITY_BUILD_URL = %teamcity.serverUrl%/viewLog.html?buildId=%teamcity.build.id%" + echo " env.TEAMCITY_BUILD_COMMIT = %system.build.vcs.number%" + echo " env.TEAMCITY_BUILD_REPOSITORY = %vcsroot..url%" + fi + service="teamcity" + branch="$TEAMCITY_BUILD_BRANCH" + build="$TEAMCITY_BUILD_ID" + build_url=$(urlencode "$TEAMCITY_BUILD_URL") + if [ "$TEAMCITY_BUILD_COMMIT" != "" ]; + then + commit="$TEAMCITY_BUILD_COMMIT" + else + commit="$BUILD_VCS_NUMBER" + fi + remote_addr="$TEAMCITY_BUILD_REPOSITORY" + +elif [ "$CI" = "true" ] && [ "$CIRCLECI" = "true" ]; +then + say "$e==>$x Circle CI detected." + # https://circleci.com/docs/environment-variables + service="circleci" + branch="$CIRCLE_BRANCH" + build="$CIRCLE_BUILD_NUM" + job="$CIRCLE_NODE_INDEX" + if [ "$CIRCLE_PROJECT_REPONAME" != "" ]; + then + slug="$CIRCLE_PROJECT_USERNAME/$CIRCLE_PROJECT_REPONAME" + else + # git@github.com:owner/repo.git + slug="${CIRCLE_REPOSITORY_URL##*:}" + # owner/repo.git + slug="${slug%%.git}" + fi + pr="${CIRCLE_PULL_REQUEST##*/}" + commit="$CIRCLE_SHA1" + search_in="$search_in $CIRCLE_ARTIFACTS $CIRCLE_TEST_REPORTS" + +elif [ "$BUDDYBUILD_BRANCH" != "" ]; +then + say "$e==>$x buddybuild detected" + # http://docs.buddybuild.com/v6/docs/custom-prebuild-and-postbuild-steps + service="buddybuild" + branch="$BUDDYBUILD_BRANCH" + build="$BUDDYBUILD_BUILD_NUMBER" + build_url="https://dashboard.buddybuild.com/public/apps/$BUDDYBUILD_APP_ID/build/$BUDDYBUILD_BUILD_ID" + # BUDDYBUILD_TRIGGERED_BY + if [ "$ddp" = "$HOME/Library/Developer/Xcode/DerivedData" ]; + then + ddp="/private/tmp/sandbox/${BUDDYBUILD_APP_ID}/bbtest" + fi + +elif [ "${bamboo_planRepository_revision}" != "" ]; +then + say "$e==>$x Bamboo detected" + # https://confluence.atlassian.com/bamboo/bamboo-variables-289277087.html#Bamboovariables-Build-specificvariables + service="bamboo" + commit="${bamboo_planRepository_revision}" + # shellcheck disable=SC2154 + branch="${bamboo_planRepository_branch}" + # shellcheck disable=SC2154 + build="${bamboo_buildNumber}" + # shellcheck disable=SC2154 + build_url="${bamboo_buildResultsUrl}" + # shellcheck disable=SC2154 + remote_addr="${bamboo_planRepository_repositoryUrl}" + +elif [ "$CI" = "true" ] && [ "$BITRISE_IO" = "true" ]; +then + # http://devcenter.bitrise.io/faq/available-environment-variables/ + say "$e==>$x Bitrise CI detected." + service="bitrise" + branch="$BITRISE_GIT_BRANCH" + build="$BITRISE_BUILD_NUMBER" + build_url=$(urlencode "$BITRISE_BUILD_URL") + pr="$BITRISE_PULL_REQUEST" + if [ "$GIT_CLONE_COMMIT_HASH" != "" ]; + then + commit="$GIT_CLONE_COMMIT_HASH" + fi + +elif [ "$CI" = "true" ] && [ "$SEMAPHORE" = "true" ]; +then + say "$e==>$x Semaphore CI detected." +# https://docs.semaphoreci.com/ci-cd-environment/environment-variables/#semaphore-related + service="semaphore" + branch="$SEMAPHORE_GIT_BRANCH" + build="$SEMAPHORE_WORKFLOW_NUMBER" + job="$SEMAPHORE_JOB_ID" + pr="$PULL_REQUEST_NUMBER" + slug="$SEMAPHORE_REPO_SLUG" + commit="$REVISION" + env="$env,SEMAPHORE_TRIGGER_SOURCE" + +elif [ "$CI" = "true" ] && [ "$BUILDKITE" = "true" ]; +then + say "$e==>$x Buildkite CI detected." + # https://buildkite.com/docs/guides/environment-variables + service="buildkite" + branch="$BUILDKITE_BRANCH" + build="$BUILDKITE_BUILD_NUMBER" + job="$BUILDKITE_JOB_ID" + build_url=$(urlencode "$BUILDKITE_BUILD_URL") + slug="$BUILDKITE_PROJECT_SLUG" + commit="$BUILDKITE_COMMIT" + if [[ "$BUILDKITE_PULL_REQUEST" != "false" ]]; then + pr="$BUILDKITE_PULL_REQUEST" + fi + tag="$BUILDKITE_TAG" + +elif [ "$CI" = "drone" ] || [ "$DRONE" = "true" ]; +then + say "$e==>$x Drone CI detected." + # http://docs.drone.io/env.html + # drone commits are not full shas + service="drone.io" + branch="$DRONE_BRANCH" + build="$DRONE_BUILD_NUMBER" + build_url=$(urlencode "${DRONE_BUILD_LINK}") + pr="$DRONE_PULL_REQUEST" + job="$DRONE_JOB_NUMBER" + tag="$DRONE_TAG" + +elif [ "$CI" = "true" ] && [ "$HEROKU_TEST_RUN_BRANCH" != "" ]; +then + say "$e==>$x Heroku CI detected." + # https://devcenter.heroku.com/articles/heroku-ci#environment-variables + service="heroku" + branch="$HEROKU_TEST_RUN_BRANCH" + build="$HEROKU_TEST_RUN_ID" + commit="$HEROKU_TEST_RUN_COMMIT_VERSION" + +elif [[ "$CI" = "true" || "$CI" = "True" ]] && [[ "$APPVEYOR" = "true" || "$APPVEYOR" = "True" ]]; +then + say "$e==>$x Appveyor CI detected." + # http://www.appveyor.com/docs/environment-variables + service="appveyor" + branch="$APPVEYOR_REPO_BRANCH" + build=$(urlencode "$APPVEYOR_JOB_ID") + pr="$APPVEYOR_PULL_REQUEST_NUMBER" + job="$APPVEYOR_ACCOUNT_NAME%2F$APPVEYOR_PROJECT_SLUG%2F$APPVEYOR_BUILD_VERSION" + slug="$APPVEYOR_REPO_NAME" + commit="$APPVEYOR_REPO_COMMIT" + build_url=$(urlencode "${APPVEYOR_URL}/project/${APPVEYOR_REPO_NAME}/builds/$APPVEYOR_BUILD_ID/job/${APPVEYOR_JOB_ID}") + +elif [ "$CI" = "true" ] && [ "$WERCKER_GIT_BRANCH" != "" ]; +then + say "$e==>$x Wercker CI detected." + # http://devcenter.wercker.com/articles/steps/variables.html + service="wercker" + branch="$WERCKER_GIT_BRANCH" + build="$WERCKER_MAIN_PIPELINE_STARTED" + slug="$WERCKER_GIT_OWNER/$WERCKER_GIT_REPOSITORY" + commit="$WERCKER_GIT_COMMIT" + +elif [ "$CI" = "true" ] && [ "$MAGNUM" = "true" ]; +then + say "$e==>$x Magnum CI detected." + # https://magnum-ci.com/docs/environment + service="magnum" + branch="$CI_BRANCH" + build="$CI_BUILD_NUMBER" + commit="$CI_COMMIT" + +elif [ "$SHIPPABLE" = "true" ]; +then + say "$e==>$x Shippable CI detected." + # http://docs.shippable.com/ci_configure/ + service="shippable" + # shellcheck disable=SC2153 + branch=$([ "$HEAD_BRANCH" != "" ] && echo "$HEAD_BRANCH" || echo "$BRANCH") + build="$BUILD_NUMBER" + build_url=$(urlencode "$BUILD_URL") + pr="$PULL_REQUEST" + slug="$REPO_FULL_NAME" + # shellcheck disable=SC2153 + commit="$COMMIT" + +elif [ "$TDDIUM" = "true" ]; +then + say "Solano CI detected." + # http://docs.solanolabs.com/Setup/tddium-set-environment-variables/ + service="solano" + commit="$TDDIUM_CURRENT_COMMIT" + branch="$TDDIUM_CURRENT_BRANCH" + build="$TDDIUM_TID" + pr="$TDDIUM_PR_ID" + +elif [ "$GREENHOUSE" = "true" ]; +then + say "$e==>$x Greenhouse CI detected." + # http://docs.greenhouseci.com/docs/environment-variables-files + service="greenhouse" + branch="$GREENHOUSE_BRANCH" + build="$GREENHOUSE_BUILD_NUMBER" + build_url=$(urlencode "$GREENHOUSE_BUILD_URL") + pr="$GREENHOUSE_PULL_REQUEST" + commit="$GREENHOUSE_COMMIT" + search_in="$search_in $GREENHOUSE_EXPORT_DIR" + +elif [ "$GITLAB_CI" != "" ]; +then + say "$e==>$x GitLab CI detected." + # http://doc.gitlab.com/ce/ci/variables/README.html + service="gitlab" + branch="${CI_BUILD_REF_NAME:-$CI_COMMIT_REF_NAME}" + build="${CI_BUILD_ID:-$CI_JOB_ID}" + remote_addr="${CI_BUILD_REPO:-$CI_REPOSITORY_URL}" + commit="${CI_BUILD_REF:-$CI_COMMIT_SHA}" + slug="${CI_PROJECT_PATH}" + +elif [ "$GITHUB_ACTIONS" != "" ]; +then + say "$e==>$x GitHub Actions detected." + say " Env vars used:" + say " -> GITHUB_ACTIONS: ${GITHUB_ACTIONS}" + say " -> GITHUB_HEAD_REF: ${GITHUB_HEAD_REF}" + say " -> GITHUB_REF: ${GITHUB_REF}" + say " -> GITHUB_REPOSITORY: ${GITHUB_REPOSITORY}" + say " -> GITHUB_RUN_ID: ${GITHUB_RUN_ID}" + say " -> GITHUB_SHA: ${GITHUB_SHA}" + say " -> GITHUB_WORKFLOW: ${GITHUB_WORKFLOW}" + + # https://github.com/features/actions + service="github-actions" + + # https://help.github.com/en/articles/virtual-environments-for-github-actions#environment-variables + branch="${GITHUB_REF#refs/heads/}" + if [ "$GITHUB_HEAD_REF" != "" ]; + then + # PR refs are in the format: refs/pull/7/merge + pr="${GITHUB_REF#refs/pull/}" + pr="${pr%/merge}" + branch="${GITHUB_HEAD_REF}" + fi + commit="${GITHUB_SHA}" + slug="${GITHUB_REPOSITORY}" + build="${GITHUB_RUN_ID}" + build_url=$(urlencode "http://github.com/${GITHUB_REPOSITORY}/actions/runs/${GITHUB_RUN_ID}") + job="$(urlencode "${GITHUB_WORKFLOW}")" + + # actions/checkout runs in detached HEAD + mc= + if [ -n "$pr" ] && [ "$pr" != false ] && [ "$commit_o" == "" ]; + then + mc=$(git show --no-patch --format="%P" 2>/dev/null || echo "") + + if [[ "$mc" =~ ^[a-z0-9]{40}[[:space:]][a-z0-9]{40}$ ]]; + then + mc=$(echo "$mc" | cut -d' ' -f2) + say " Fixing merge commit SHA $commit -> $mc" + commit=$mc + elif [[ "$mc" = "" ]]; + then + say "$r-> Issue detecting commit SHA. Please run actions/checkout with fetch-depth > 1 or set to 0$x" + fi + fi + +elif [ "$SYSTEM_TEAMFOUNDATIONSERVERURI" != "" ]; +then + say "$e==>$x Azure Pipelines detected." + # https://docs.microsoft.com/en-us/azure/devops/pipelines/build/variables?view=vsts + # https://docs.microsoft.com/en-us/azure/devops/pipelines/build/variables?view=azure-devops&viewFallbackFrom=vsts&tabs=yaml + service="azure_pipelines" + commit="$BUILD_SOURCEVERSION" + build="$BUILD_BUILDNUMBER" + if [ -z "$SYSTEM_PULLREQUEST_PULLREQUESTNUMBER" ]; + then + pr="$SYSTEM_PULLREQUEST_PULLREQUESTID" + else + pr="$SYSTEM_PULLREQUEST_PULLREQUESTNUMBER" + fi + project="${SYSTEM_TEAMPROJECT}" + server_uri="${SYSTEM_TEAMFOUNDATIONSERVERURI}" + job="${BUILD_BUILDID}" + branch="${BUILD_SOURCEBRANCH#"refs/heads/"}" + build_url=$(urlencode "${SYSTEM_TEAMFOUNDATIONSERVERURI}${SYSTEM_TEAMPROJECT}/_build/results?buildId=${BUILD_BUILDID}") + + # azure/pipelines runs in detached HEAD + mc= + if [ -n "$pr" ] && [ "$pr" != false ]; + then + mc=$(git show --no-patch --format="%P" 2>/dev/null || echo "") + + if [[ "$mc" =~ ^[a-z0-9]{40}[[:space:]][a-z0-9]{40}$ ]]; + then + mc=$(echo "$mc" | cut -d' ' -f2) + say " Fixing merge commit SHA $commit -> $mc" + commit=$mc + fi + fi + +elif [ "$CI" = "true" ] && [ "$BITBUCKET_BUILD_NUMBER" != "" ]; +then + say "$e==>$x Bitbucket detected." + # https://confluence.atlassian.com/bitbucket/variables-in-pipelines-794502608.html + service="bitbucket" + branch="$BITBUCKET_BRANCH" + build="$BITBUCKET_BUILD_NUMBER" + slug="$BITBUCKET_REPO_OWNER/$BITBUCKET_REPO_SLUG" + job="$BITBUCKET_BUILD_NUMBER" + pr="$BITBUCKET_PR_ID" + commit="$BITBUCKET_COMMIT" + # See https://jira.atlassian.com/browse/BCLOUD-19393 + if [ "${#commit}" = 12 ]; + then + commit=$(git rev-parse "$BITBUCKET_COMMIT") + fi + +elif [ "$CI" = "true" ] && [ "$BUDDY" = "true" ]; +then + say "$e==>$x Buddy CI detected." + # https://buddy.works/docs/pipelines/environment-variables + service="buddy" + branch="$BUDDY_EXECUTION_BRANCH" + build="$BUDDY_EXECUTION_ID" + build_url=$(urlencode "$BUDDY_EXECUTION_URL") + commit="$BUDDY_EXECUTION_REVISION" + pr="$BUDDY_EXECUTION_PULL_REQUEST_NO" + tag="$BUDDY_EXECUTION_TAG" + slug="$BUDDY_REPO_SLUG" + +elif [ "$CIRRUS_CI" != "" ]; +then + say "$e==>$x Cirrus CI detected." + # https://cirrus-ci.org/guide/writing-tasks/#environment-variables + service="cirrus-ci" + slug="$CIRRUS_REPO_FULL_NAME" + branch="$CIRRUS_BRANCH" + pr="$CIRRUS_PR" + commit="$CIRRUS_CHANGE_IN_REPO" + build="$CIRRUS_BUILD_ID" + build_url=$(urlencode "https://cirrus-ci.com/task/$CIRRUS_TASK_ID") + job="$CIRRUS_TASK_NAME" + +elif [ "$DOCKER_REPO" != "" ]; +then + say "$e==>$x Docker detected." + # https://docs.docker.com/docker-cloud/builds/advanced/ + service="docker" + branch="$SOURCE_BRANCH" + commit="$SOURCE_COMMIT" + slug="$DOCKER_REPO" + tag="$CACHE_TAG" + env="$env,IMAGE_NAME" + +else + say "${r}x>${x} No CI provider detected." + say " Testing inside Docker? ${b}http://docs.codecov.io/docs/testing-with-docker${x}" + say " Testing with Tox? ${b}https://docs.codecov.io/docs/python#section-testing-with-tox${x}" + +fi + +say " ${e}project root:${x} $git_root" + +# find branch, commit, repo from git command +if [ "$GIT_BRANCH" != "" ]; +then + branch="$GIT_BRANCH" + +elif [ "$branch" = "" ]; +then + branch=$(git rev-parse --abbrev-ref HEAD 2>/dev/null || hg branch 2>/dev/null || echo "") + if [ "$branch" = "HEAD" ]; + then + branch="" + fi +fi + +if [ "$commit_o" = "" ]; +then + if [ "$GIT_COMMIT" != "" ]; + then + commit="$GIT_COMMIT" + elif [ "$commit" = "" ]; + then + commit=$(git log -1 --format="%H" 2>/dev/null || hg id -i --debug 2>/dev/null | tr -d '+' || echo "") + fi +else + commit="$commit_o" +fi + +if [ "$CODECOV_TOKEN" != "" ] && [ "$token" = "" ]; +then + say "${e}-->${x} token set from env" + token="$CODECOV_TOKEN" +fi + +if [ "$CODECOV_URL" != "" ] && [ "$url_o" = "" ]; +then + say "${e}-->${x} url set from env" + url_o=$(echo "$CODECOV_URL" | sed -e 's/\/$//') +fi + +if [ "$CODECOV_SLUG" != "" ]; +then + say "${e}-->${x} slug set from env" + slug_o="$CODECOV_SLUG" + +elif [ "$slug" = "" ]; +then + if [ "$remote_addr" = "" ]; + then + remote_addr=$(git config --get remote.origin.url || hg paths default || echo '') + fi + if [ "$remote_addr" != "" ]; + then + if echo "$remote_addr" | grep -q "//"; then + # https + slug=$(echo "$remote_addr" | cut -d / -f 4,5 | sed -e 's/\.git$//') + else + # ssh + slug=$(echo "$remote_addr" | cut -d : -f 2 | sed -e 's/\.git$//') + fi + fi + if [ "$slug" = "/" ]; + then + slug="" + fi +fi + +yaml=$(cd "$git_root" && \ + git ls-files "*codecov.yml" "*codecov.yaml" 2>/dev/null \ + || hg locate "*codecov.yml" "*codecov.yaml" 2>/dev/null \ + || cd "$proj_root" && find . -maxdepth 1 -type f -name '*codecov.y*ml' 2>/dev/null \ + || echo '') +yaml=$(echo "$yaml" | head -1) + +if [ "$yaml" != "" ]; +then + say " ${e}Yaml found at:${x} $yaml" + if [[ "$yaml" != /* ]]; then + # relative path for yaml file given, assume relative to the repo root + yaml="$git_root/$yaml" + fi + config=$(parse_yaml "$yaml" || echo '') + + # TODO validate the yaml here + + if [ "$(echo "$config" | grep 'codecov_token="')" != "" ] && [ "$token" = "" ]; + then + say "${e}-->${x} token set from yaml" + token="$(echo "$config" | grep 'codecov_token="' | sed -e 's/codecov_token="//' | sed -e 's/"\.*//')" + fi + + if [ "$(echo "$config" | grep 'codecov_url="')" != "" ] && [ "$url_o" = "" ]; + then + say "${e}-->${x} url set from yaml" + url_o="$(echo "$config" | grep 'codecov_url="' | sed -e 's/codecov_url="//' | sed -e 's/"\.*//')" + fi + + if [ "$(echo "$config" | grep 'codecov_slug="')" != "" ] && [ "$slug_o" = "" ]; + then + say "${e}-->${x} slug set from yaml" + slug_o="$(echo "$config" | grep 'codecov_slug="' | sed -e 's/codecov_slug="//' | sed -e 's/"\.*//')" + fi +else + say " ${g}Yaml not found, that's ok! Learn more at${x} ${b}http://docs.codecov.io/docs/codecov-yaml${x}" +fi + +if [ "$branch_o" != "" ]; +then + branch=$(urlencode "$branch_o") +else + branch=$(urlencode "$branch") +fi + +if [ "$slug_o" = "" ]; +then + urlencoded_slug=$(urlencode "$slug") +else + urlencoded_slug=$(urlencode "$slug_o") +fi + +query="branch=$branch\ + &commit=$commit\ + &build=$([ "$build_o" = "" ] && echo "$build" || echo "$build_o")\ + &build_url=$build_url\ + &name=$(urlencode "$name")\ + &tag=$([ "$tag_o" = "" ] && echo "$tag" || echo "$tag_o")\ + &slug=$urlencoded_slug\ + &service=$service\ + &flags=$flags\ + &pr=$([ "$pr_o" = "" ] && echo "${pr##\#}" || echo "${pr_o##\#}")\ + &job=$job\ + &cmd_args=$(IFS=,; echo "${codecov_flags[*]}")" + +if [ -n "$project" ] && [ -n "$server_uri" ]; +then + query=$(echo "$query&project=$project&server_uri=$server_uri" | tr -d ' ') +fi + +if [ "$parent" != "" ]; +then + query=$(echo "parent=$parent&$query" | tr -d ' ') +fi + +if [ "$ft_search" = "1" ]; +then + # detect bower comoponents location + bower_components="bower_components" + bower_rc=$(cd "$git_root" && cat .bowerrc 2>/dev/null || echo "") + if [ "$bower_rc" != "" ]; + then + bower_components=$(echo "$bower_rc" | tr -d '\n' | grep '"directory"' | cut -d'"' -f4 | sed -e 's/\/$//') + if [ "$bower_components" = "" ]; + then + bower_components="bower_components" + fi + fi + + # Swift Coverage + if [ "$ft_xcodellvm" = "1" ] && [ -d "$ddp" ]; + then + say "${e}==>${x} Processing Xcode reports via llvm-cov" + say " DerivedData folder: $ddp" + profdata_files=$(find "$ddp" -name '*.profdata' 2>/dev/null || echo '') + if [ "$profdata_files" != "" ]; + then + # xcode via profdata + if [ "$xp" = "" ]; + then + # xp=$(xcodebuild -showBuildSettings 2>/dev/null | grep -i "^\s*PRODUCT_NAME" | sed -e 's/.*= \(.*\)/\1/') + # say " ${e}->${x} Speed up Xcode processing by adding ${e}-J '$xp'${x}" + say " ${g}hint${x} Speed up Swift processing by using use ${g}-J 'AppName'${x} (regexp accepted)" + say " ${g}hint${x} This will remove Pods/ from your report. Also ${b}https://docs.codecov.io/docs/ignoring-paths${x}" + fi + while read -r profdata; + do + if [ "$profdata" != "" ]; + then + swiftcov "$profdata" "$xp" + fi + done <<< "$profdata_files" + else + say " ${e}->${x} No Swift coverage found" + fi + + # Obj-C Gcov Coverage + if [ "$ft_gcov" = "1" ]; + then + say " ${e}->${x} Running $gcov_exe for Obj-C" + if [ "$ft_gcovout" = "0" ]; + then + # suppress gcov output + bash -c "find $ddp -type f -name '*.gcda' $gcov_include $gcov_ignore -exec $gcov_exe -p $gcov_arg {} +" >/dev/null 2>&1 || true + else + bash -c "find $ddp -type f -name '*.gcda' $gcov_include $gcov_ignore -exec $gcov_exe -p $gcov_arg {} +" || true + fi + fi + fi + + if [ "$ft_xcodeplist" = "1" ] && [ -d "$ddp" ]; + then + say "${e}==>${x} Processing Xcode plists" + plists_files=$(find "$ddp" -name '*.xccoverage' 2>/dev/null || echo '') + if [ "$plists_files" != "" ]; + then + while read -r plist; + do + if [ "$plist" != "" ]; + then + say " ${g}Found${x} plist file at $plist" + plutil -convert xml1 -o "$(basename "$plist").plist" -- "$plist" + fi + done <<< "$plists_files" + fi + fi + + # Gcov Coverage + if [ "$ft_gcov" = "1" ]; + then + say "${e}==>${x} Running $gcov_exe in $proj_root ${e}(disable via -X gcov)${x}" + if [ "$ft_gcovout" = "0" ]; + then + # suppress gcov output + bash -c "find $proj_root -type f -name '*.gcno' $gcov_include $gcov_ignore -exec $gcov_exe -pb $gcov_arg {} +" >/dev/null 2>&1 || true + else + bash -c "find $proj_root -type f -name '*.gcno' $gcov_include $gcov_ignore -exec $gcov_exe -pb $gcov_arg {} +" || true + fi + else + say "${e}==>${x} gcov disabled" + fi + + # Python Coverage + if [ "$ft_coveragepy" = "1" ]; + then + if [ ! -f coverage.xml ]; + then + if command -v coverage >/dev/null 2>&1; + then + say "${e}==>${x} Python coveragepy exists ${e}disable via -X coveragepy${x}" + + dotcoverage=$(find "$git_root" -name '.coverage' -or -name '.coverage.*' | head -1 || echo '') + if [ "$dotcoverage" != "" ]; + then + cd "$(dirname "$dotcoverage")" + if [ ! -f .coverage ]; + then + say " ${e}->${x} Running coverage combine" + coverage combine -a + fi + say " ${e}->${x} Running coverage xml" + if [ "$(coverage xml -i)" != "No data to report." ]; + then + files="$files +$PWD/coverage.xml" + else + say " ${r}No data to report.${x}" + fi + cd "$proj_root" + else + say " ${r}No .coverage file found.${x}" + fi + else + say "${e}==>${x} Python coveragepy not found" + fi + fi + else + say "${e}==>${x} Python coveragepy disabled" + fi + + if [ "$search_in_o" != "" ]; + then + # location override + search_in="$search_in_o" + fi + + say "$e==>$x Searching for coverage reports in:" + for _path in $search_in + do + say " ${g}+${x} $_path" + done + + patterns="find $search_in \( \ + -name vendor \ + -or -name '$bower_components' \ + -or -name '.egg-info*' \ + -or -name 'conftest_*.c.gcov' \ + -or -name .env \ + -or -name .envs \ + -or -name .git \ + -or -name .hg \ + -or -name .tox \ + -or -name .venv \ + -or -name .venvs \ + -or -name .virtualenv \ + -or -name .virtualenvs \ + -or -name .yarn-cache \ + -or -name __pycache__ \ + -or -name env \ + -or -name envs \ + -or -name htmlcov \ + -or -name js/generated/coverage \ + -or -name node_modules \ + -or -name venv \ + -or -name venvs \ + -or -name virtualenv \ + -or -name virtualenvs \ + \) -prune -or \ + -type f \( -name '*coverage*.*' \ + -or -name '*.clover' \ + -or -name '*.codecov.*' \ + -or -name '*.gcov' \ + -or -name '*.lcov' \ + -or -name '*.lst' \ + -or -name 'clover.xml' \ + -or -name 'cobertura.xml' \ + -or -name 'codecov.*' \ + -or -name 'cover.out' \ + -or -name 'codecov-result.json' \ + -or -name 'coverage-final.json' \ + -or -name 'excoveralls.json' \ + -or -name 'gcov.info' \ + -or -name 'jacoco*.xml' \ + -or -name '*Jacoco*.xml' \ + -or -name 'lcov.dat' \ + -or -name 'lcov.info' \ + -or -name 'luacov.report.out' \ + -or -name 'naxsi.info' \ + -or -name 'nosetests.xml' \ + -or -name 'report.xml' \ + $include_cov \) \ + $exclude_cov \ + -not -name '*.am' \ + -not -name '*.bash' \ + -not -name '*.bat' \ + -not -name '*.bw' \ + -not -name '*.cfg' \ + -not -name '*.class' \ + -not -name '*.cmake' \ + -not -name '*.cmake' \ + -not -name '*.conf' \ + -not -name '*.coverage' \ + -not -name '*.cp' \ + -not -name '*.cpp' \ + -not -name '*.crt' \ + -not -name '*.css' \ + -not -name '*.csv' \ + -not -name '*.csv' \ + -not -name '*.data' \ + -not -name '*.db' \ + -not -name '*.dox' \ + -not -name '*.ec' \ + -not -name '*.ec' \ + -not -name '*.egg' \ + -not -name '*.el' \ + -not -name '*.env' \ + -not -name '*.erb' \ + -not -name '*.exe' \ + -not -name '*.ftl' \ + -not -name '*.gif' \ + -not -name '*.gradle' \ + -not -name '*.gz' \ + -not -name '*.h' \ + -not -name '*.html' \ + -not -name '*.in' \ + -not -name '*.jade' \ + -not -name '*.jar*' \ + -not -name '*.jpeg' \ + -not -name '*.jpg' \ + -not -name '*.js' \ + -not -name '*.less' \ + -not -name '*.log' \ + -not -name '*.m4' \ + -not -name '*.mak*' \ + -not -name '*.md' \ + -not -name '*.o' \ + -not -name '*.p12' \ + -not -name '*.pem' \ + -not -name '*.png' \ + -not -name '*.pom*' \ + -not -name '*.profdata' \ + -not -name '*.proto' \ + -not -name '*.ps1' \ + -not -name '*.pth' \ + -not -name '*.py' \ + -not -name '*.pyc' \ + -not -name '*.pyo' \ + -not -name '*.rb' \ + -not -name '*.rsp' \ + -not -name '*.rst' \ + -not -name '*.ru' \ + -not -name '*.sbt' \ + -not -name '*.scss' \ + -not -name '*.scss' \ + -not -name '*.serialized' \ + -not -name '*.sh' \ + -not -name '*.snapshot' \ + -not -name '*.sql' \ + -not -name '*.svg' \ + -not -name '*.tar.tz' \ + -not -name '*.template' \ + -not -name '*.whl' \ + -not -name '*.xcconfig' \ + -not -name '*.xcoverage.*' \ + -not -name '*/classycle/report.xml' \ + -not -name '*codecov.yml' \ + -not -name '*~' \ + -not -name '.*coveragerc' \ + -not -name '.coverage*' \ + -not -name 'coverage-summary.json' \ + -not -name 'createdFiles.lst' \ + -not -name 'fullLocaleNames.lst' \ + -not -name 'include.lst' \ + -not -name 'inputFiles.lst' \ + -not -name 'phpunit-code-coverage.xml' \ + -not -name 'phpunit-coverage.xml' \ + -not -name 'remapInstanbul.coverage*.json' \ + -not -name 'scoverage.measurements.*' \ + -not -name 'test_*_coverage.txt' \ + -not -name 'testrunner-coverage*' \ + -print 2>/dev/null" + files=$(eval "$patterns" || echo '') + +elif [ "$include_cov" != "" ]; +then + files=$(eval "find $search_in -type f \( ${include_cov:5} \)$exclude_cov 2>/dev/null" || echo '') +elif [ "$direct_file_upload" != "" ]; +then + files=$direct_file_upload +fi + +num_of_files=$(echo "$files" | wc -l | tr -d ' ') +if [ "$num_of_files" != '' ] && [ "$files" != '' ]; +then + say " ${e}->${x} Found $num_of_files reports" +fi + +# no files found +if [ "$files" = "" ]; +then + say "${r}-->${x} No coverage report found." + say " Please visit ${b}http://docs.codecov.io/docs/supported-languages${x}" + exit ${exit_with}; +fi + +if [ "$ft_network" == "1" ]; +then + say "${e}==>${x} Detecting git/mercurial file structure" + network=$(cd "$git_root" && git ls-files $git_ls_files_recurse_submodules_o 2>/dev/null || hg locate 2>/dev/null || echo "") + if [ "$network" = "" ]; + then + network=$(find "$git_root" \( \ + -name virtualenv \ + -name .virtualenv \ + -name virtualenvs \ + -name .virtualenvs \ + -name '*.png' \ + -name '*.gif' \ + -name '*.jpg' \ + -name '*.jpeg' \ + -name '*.md' \ + -name .env \ + -name .envs \ + -name env \ + -name envs \ + -name .venv \ + -name .venvs \ + -name venv \ + -name venvs \ + -name .git \ + -name .egg-info \ + -name shunit2-2.1.6 \ + -name vendor \ + -name __pycache__ \ + -name node_modules \ + -path "*/$bower_components/*" \ + -path '*/target/delombok/*' \ + -path '*/build/lib/*' \ + -path '*/js/generated/coverage/*' \ + \) -prune -or \ + -type f -print 2>/dev/null || echo '') + fi + + if [ "$network_filter_o" != "" ]; + then + network=$(echo "$network" | grep -e "$network_filter_o/*") + fi + if [ "$prefix_o" != "" ]; + then + network=$(echo "$network" | awk "{print \"$prefix_o/\"\$0}") + fi +fi + +upload_file=$(mktemp /tmp/codecov.XXXXXX) +adjustments_file=$(mktemp /tmp/codecov.adjustments.XXXXXX) + +cleanup() { + rm -f "$upload_file" "$adjustments_file" "$upload_file.gz" +} + +trap cleanup INT ABRT TERM + + +if [ "$env" != "" ]; +then + inc_env="" + say "${e}==>${x} Appending build variables" + for varname in $(echo "$env" | tr ',' ' ') + do + if [ "$varname" != "" ]; + then + say " ${g}+${x} $varname" + inc_env="${inc_env}${varname}=$(eval echo "\$${varname}") +" + fi + done + echo "$inc_env<<<<<< ENV" >> "$upload_file" +fi + +# Append git file list +# write discovered yaml location +if [ "$direct_file_upload" = "" ]; +then + echo "$yaml" >> "$upload_file" +fi + +if [ "$ft_network" == "1" ]; +then + i="woff|eot|otf" # fonts + i="$i|gif|png|jpg|jpeg|psd" # images + i="$i|ptt|pptx|numbers|pages|md|txt|xlsx|docx|doc|pdf|csv" # docs + i="$i|.gitignore" # supporting docs + + if [ "$ft_html" != "1" ]; + then + i="$i|html" + fi + + if [ "$ft_yaml" != "1" ]; + then + i="$i|yml|yaml" + fi + + echo "$network" | grep -vwE "($i)$" >> "$upload_file" +fi +echo "<<<<<< network" >> "$upload_file" + +if [ "$direct_file_upload" = "" ]; +then + fr=0 + say "${e}==>${x} Reading reports" + while IFS='' read -r file; + do + # read the coverage file + if [ "$(echo "$file" | tr -d ' ')" != '' ]; + then + if [ -f "$file" ]; + then + report_len=$(wc -c < "$file") + if [ "$report_len" -ne 0 ]; + then + say " ${g}+${x} $file ${e}bytes=$(echo "$report_len" | tr -d ' ')${x}" + # append to to upload + _filename=$(basename "$file") + if [ "${_filename##*.}" = 'gcov' ]; + then + { + echo "# path=$(echo "$file.reduced" | sed "s|^$git_root/||")"; + # get file name + head -1 "$file"; + } >> "$upload_file" + # 1. remove source code + # 2. remove ending bracket lines + # 3. remove whitespace + # 4. remove contextual lines + # 5. remove function names + awk -F': *' '{print $1":"$2":"}' "$file" \ + | sed '\/: *} *$/d' \ + | sed 's/^ *//' \ + | sed '/^-/d' \ + | sed 's/^function.*/func/' >> "$upload_file" + else + { + echo "# path=${file//^$git_root/||}"; + cat "$file"; + } >> "$upload_file" + fi + echo "<<<<<< EOF" >> "$upload_file" + fr=1 + if [ "$clean" = "1" ]; + then + rm "$file" + fi + else + say " ${r}-${x} Skipping empty file $file" + fi + else + say " ${r}-${x} file not found at $file" + fi + fi + done <<< "$(echo -e "$files")" + + if [ "$fr" = "0" ]; + then + say "${r}-->${x} No coverage data found." + say " Please visit ${b}http://docs.codecov.io/docs/supported-languages${x}" + say " search for your projects language to learn how to collect reports." + exit ${exit_with}; + fi +else + cp "$direct_file_upload" "$upload_file" + if [ "$clean" = "1" ]; + then + rm "$direct_file_upload" + fi +fi + +if [ "$ft_fix" = "1" ]; +then + say "${e}==>${x} Appending adjustments" + say " ${b}https://docs.codecov.io/docs/fixing-reports${x}" + + empty_line='^[[:space:]]*$' + # // + syntax_comment='^[[:space:]]*//.*' + # /* or */ + syntax_comment_block='^[[:space:]]*(\/\*|\*\/)[[:space:]]*$' + # { or } + syntax_bracket='^[[:space:]]*[\{\}][[:space:]]*(//.*)?$' + # [ or ] + syntax_list='^[[:space:]]*[][][[:space:]]*(//.*)?$' + # func ... { + syntax_go_func='^[[:space:]]*[func].*[\{][[:space:]]*$' + + # shellcheck disable=SC2089 + skip_dirs="-not -path '*/$bower_components/*' \ + -not -path '*/node_modules/*'" + + cut_and_join() { + awk 'BEGIN { FS=":" } + $3 ~ /\/\*/ || $3 ~ /\*\// { print $0 ; next } + $1!=key { if (key!="") print out ; key=$1 ; out=$1":"$2 ; next } + { out=out","$2 } + END { print out }' 2>/dev/null + } + + if echo "$network" | grep -m1 '.kt$' 1>/dev/null; + then + # skip brackets and comments + cd "$git_root" && \ + find . -type f \ + -name '*.kt' \ + -exec \ + grep -nIHE -e "$syntax_bracket" \ + -e "$syntax_comment_block" {} \; \ + | cut_and_join \ + >> "$adjustments_file" \ + || echo '' + + # last line in file + cd "$git_root" && \ + find . -type f \ + -name '*.kt' -exec \ + wc -l {} \; \ + | while read -r l; do echo "EOF: $l"; done \ + 2>/dev/null \ + >> "$adjustments_file" \ + || echo '' + fi + + if echo "$network" | grep -m1 '.go$' 1>/dev/null; + then + # skip empty lines, comments, and brackets + cd "$git_root" && \ + find . -type f \ + -not -path '*/vendor/*' \ + -not -path '*/caches/*' \ + -name '*.go' \ + -exec \ + grep -nIHE \ + -e "$empty_line" \ + -e "$syntax_comment" \ + -e "$syntax_comment_block" \ + -e "$syntax_bracket" \ + -e "$syntax_go_func" \ + {} \; \ + | cut_and_join \ + >> "$adjustments_file" \ + || echo '' + fi + + if echo "$network" | grep -m1 '.dart$' 1>/dev/null; + then + # skip brackets + cd "$git_root" && \ + find . -type f \ + -name '*.dart' \ + -exec \ + grep -nIHE \ + -e "$syntax_bracket" \ + {} \; \ + | cut_and_join \ + >> "$adjustments_file" \ + || echo '' + fi + + if echo "$network" | grep -m1 '.php$' 1>/dev/null; + then + # skip empty lines, comments, and brackets + cd "$git_root" && \ + find . -type f \ + -not -path "*/vendor/*" \ + -name '*.php' \ + -exec \ + grep -nIHE \ + -e "$syntax_list" \ + -e "$syntax_bracket" \ + -e '^[[:space:]]*\);[[:space:]]*(//.*)?$' \ + {} \; \ + | cut_and_join \ + >> "$adjustments_file" \ + || echo '' + fi + + if echo "$network" | grep -m1 '\(.c\.cpp\|.cxx\|.h\|.hpp\|.m\|.swift\|.vala\)$' 1>/dev/null; + then + # skip brackets + # shellcheck disable=SC2086,SC2090 + cd "$git_root" && \ + find . -type f \ + $skip_dirs \ + \( \ + -name '*.c' \ + -or -name '*.cpp' \ + -or -name '*.cxx' \ + -or -name '*.h' \ + -or -name '*.hpp' \ + -or -name '*.m' \ + -or -name '*.swift' \ + -or -name '*.vala' \ + \) -exec \ + grep -nIHE \ + -e "$empty_line" \ + -e "$syntax_bracket" \ + -e '// LCOV_EXCL' \ + {} \; \ + | cut_and_join \ + >> "$adjustments_file" \ + || echo '' + + # skip brackets + # shellcheck disable=SC2086,SC2090 + cd "$git_root" && \ + find . -type f \ + $skip_dirs \ + \( \ + -name '*.c' \ + -or -name '*.cpp' \ + -or -name '*.cxx' \ + -or -name '*.h' \ + -or -name '*.hpp' \ + -or -name '*.m' \ + -or -name '*.swift' \ + -or -name '*.vala' \ + \) -exec \ + grep -nIH '// LCOV_EXCL' \ + {} \; \ + >> "$adjustments_file" \ + || echo '' + + fi + + found=$(< "$adjustments_file" tr -d ' ') + + if [ "$found" != "" ]; + then + say " ${g}+${x} Found adjustments" + { + echo "# path=fixes"; + cat "$adjustments_file"; + echo "<<<<<< EOF"; + } >> "$upload_file" + rm -rf "$adjustments_file" + else + say " ${e}->${x} No adjustments found" + fi +fi + +if [ "$url_o" != "" ]; +then + url="$url_o" +fi + +if [ "$dump" != "0" ]; +then + # trim whitespace from query + say " ${e}->${x} Dumping upload file (no upload)" + echo "$url/upload/v4?$(echo "package=$package-$VERSION&token=$token&$query" | tr -d ' ')" + cat "$upload_file" +else + if [ "$save_to" != "" ]; + then + say "${e}==>${x} Copying upload file to ${save_to}" + mkdir -p "$(dirname "$save_to")" + cp "$upload_file" "$save_to" + fi + + say "${e}==>${x} Gzipping contents" + gzip -nf9 "$upload_file" + say " $(du -h "$upload_file.gz")" + + query=$(echo "${query}" | tr -d ' ') + say "${e}==>${x} Uploading reports" + say " ${e}url:${x} $url" + say " ${e}query:${x} $query" + + # Full query without token (to display on terminal output) + queryNoToken=$(echo "package=$package-$VERSION&token=secret&$query" | tr -d ' ') + # now add token to query + query=$(echo "package=$package-$VERSION&token=$token&$query" | tr -d ' ') + + if [ "$ft_s3" = "1" ]; + then + say "${e}->${x} Pinging Codecov" + say "$url/upload/v4?$queryNoToken" + # shellcheck disable=SC2086,2090 + res=$(curl $curl_s -X POST $cacert \ + --retry 5 --retry-delay 2 --connect-timeout 2 \ + -H 'X-Reduced-Redundancy: false' \ + -H 'X-Content-Type: application/x-gzip' \ + -H 'Content-Length: 0' \ + --write-out "\n%{response_code}\n" \ + $curlargs \ + "$url/upload/v4?$query" || true) + # a good reply is "https://codecov.io" + "\n" + "https://storage.googleapis.com/codecov/..." + s3target=$(echo "$res" | sed -n 2p) + status=$(tail -n1 <<< "$res") + + if [ "$status" = "200" ] && [ "$s3target" != "" ]; + then + say "${e}->${x} Uploading to" + say "${s3target}" + + # shellcheck disable=SC2086 + s3=$(curl -fiX PUT \ + --data-binary @"$upload_file.gz" \ + -H 'Content-Type: application/x-gzip' \ + -H 'Content-Encoding: gzip' \ + $curlawsargs \ + "$s3target" || true) + + if [ "$s3" != "" ]; + then + say " ${g}->${x} Reports have been successfully queued for processing at ${b}$(echo "$res" | sed -n 1p)${x}" + exit 0 + else + say " ${r}X>${x} Failed to upload" + fi + elif [ "$status" = "400" ]; + then + # 400 Error + say "${r}${res}${x}" + exit ${exit_with} + else + say "${r}${res}${x}" + fi + fi + + say "${e}==>${x} Uploading to Codecov" + + # shellcheck disable=SC2086,2090 + res=$(curl -X POST $cacert \ + --data-binary @"$upload_file.gz" \ + --retry 5 --retry-delay 2 --connect-timeout 2 \ + -H 'Content-Type: text/plain' \ + -H 'Content-Encoding: gzip' \ + -H 'X-Content-Encoding: gzip' \ + -H 'Accept: text/plain' \ + $curlargs \ + "$url/upload/v2?$query&attempt=$i" || echo 'HTTP 500') + # HTTP 200 + # http://.... + status=$(echo "$res" | head -1 | cut -d' ' -f2) + if [ "$status" = "" ] || [ "$status" = "200" ]; + then + say " Reports have been successfully queued for processing at ${b}$(echo "$res" | head -2 | tail -1)${x}" + exit 0 + else + say " ${g}${res}${x}" + exit ${exit_with} + fi + + say " ${r}X> Failed to upload coverage reports${x}" +fi + +exit ${exit_with} diff --git a/nodist/code_coverage b/nodist/code_coverage index 3e70bbb36..0a3cc0e08 100755 --- a/nodist/code_coverage +++ b/nodist/code_coverage @@ -194,7 +194,7 @@ def test(): if Args.stage_enabled[18]: ci_fold_start("upload") print("Stage 18: Upload") - cmd = "bash <(curl -s https://codecov.io/bash) -f " + cc_dir + "/app_total.info" + cmd = "bash <(cat ci/coverage-upload.sh) -f " + cc_dir + "/app_total.info" print("print: Not running: export CODECOV_TOKEN=") print("print: Not running: " + cmd) ci_fold_end() From 8749f545b67e58b18155b80632bb02ba6d2d5026 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 24 Apr 2021 09:44:00 -0400 Subject: [PATCH 108/110] Partial fix to avoid init error on lint-only (#2895) --- src/V3EmitC.cpp | 4 +++- test_regress/t/t_unpacked_str_init.pl | 20 +++++++++++++++++++ test_regress/t/t_unpacked_str_init.v | 28 +++++++++++++++++++++++++++ 3 files changed, 51 insertions(+), 1 deletion(-) create mode 100755 test_regress/t/t_unpacked_str_init.pl create mode 100644 test_regress/t/t_unpacked_str_init.v diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 0785b4f75..eae2581cd 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -1266,7 +1266,9 @@ public: virtual void visit(AstNode* nodep) override { puts(string("\n???? // ") + nodep->prettyTypeName() + "\n"); iterateChildren(nodep); - nodep->v3fatalSrc("Unknown node type reached emitter: " << nodep->prettyTypeName()); + if (!v3Global.opt.lintOnly()) { // An internal problem, so suppress + nodep->v3fatalSrc("Unknown node type reached emitter: " << nodep->prettyTypeName()); + } } EmitCStmts() { diff --git a/test_regress/t/t_unpacked_str_init.pl b/test_regress/t/t_unpacked_str_init.pl new file mode 100755 index 000000000..235ca326a --- /dev/null +++ b/test_regress/t/t_unpacked_str_init.pl @@ -0,0 +1,20 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +# TODO change to compile() +lint( + ); + +# No execute, not self-checking + +ok(1); +1; diff --git a/test_regress/t/t_unpacked_str_init.v b/test_regress/t/t_unpacked_str_init.v new file mode 100644 index 000000000..d7bce5f71 --- /dev/null +++ b/test_regress/t/t_unpacked_str_init.v @@ -0,0 +1,28 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2020 by Wilson Snyder. +// SPDX-License-Identifier: CC0-1.0 + +package pkg; + localparam string REGS [0:31] + = '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", + "s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5", + "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", + "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", + "ft10", "ft11"}; + function string disasm32(logic [4:0] op); + return $sformatf("lui %s" , REGS[op]); + endfunction +endpackage + +module t(/*AUTOARG*/ + // Inputs + op + ); + import pkg::*; + input [4:0] op; + always_comb begin + $display("OP: 0x%08x: %s", op, disasm32(op)); + end +endmodule From aedd16225a729a39661fdaa8cf4cb58609497922 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 24 Apr 2021 10:33:49 -0400 Subject: [PATCH 109/110] Tests: Don't expose version numbers --- test_regress/driver.pl | 1 + test_regress/t/t_alias2_unsup.out | 2 +- test_regress/t/t_alias_unsup.out | 2 +- test_regress/t/t_array_list_bad.out | 2 +- test_regress/t/t_assert_comp_bad.out | 2 +- test_regress/t/t_assoc_wildcard_unsup.out | 2 +- test_regress/t/t_case_x_bad.out | 2 +- test_regress/t/t_case_zx_bad.out | 2 +- test_regress/t/t_castdyn_castconst_bad.out | 2 +- test_regress/t/t_castdyn_unsup_bad.out | 2 +- test_regress/t/t_cdc_async_bad.out | 2 +- test_regress/t/t_class_class.out | 2 +- test_regress/t/t_class_extends_bad.out | 2 +- test_regress/t/t_class_local_bad.out | 2 +- test_regress/t/t_class_member_bad.out | 2 +- test_regress/t/t_class_param.out | 2 +- test_regress/t/t_class_param_bad.out | 2 +- test_regress/t/t_class_static.out | 2 +- test_regress/t/t_class_static_order.out | 2 +- test_regress/t/t_class_unsup_bad.out | 2 +- test_regress/t/t_class_vparam.out | 2 +- test_regress/t/t_clk_first_bad.out | 2 +- test_regress/t/t_clk_scope_bad.out | 2 +- test_regress/t/t_clocker_bad.out | 2 +- test_regress/t/t_concat_large_bad.out | 2 +- test_regress/t/t_concat_link_bad.out | 2 +- test_regress/t/t_const_bad.out | 2 +- test_regress/t/t_delay_stmtdly_bad.out | 2 +- test_regress/t/t_dpi_unpack_bad.out | 2 +- test_regress/t/t_dynarray_bad.out | 2 +- test_regress/t/t_enum_bad_hide.out | 2 +- test_regress/t/t_event_control_unsup.out | 2 +- test_regress/t/t_event_copy.out | 2 +- test_regress/t/t_flag_context_bad.out | 2 +- test_regress/t/t_flag_main_sc_bad.out | 2 +- test_regress/t/t_flag_topmodule_bad.out | 2 +- test_regress/t/t_flag_werror_bad1.out | 2 +- test_regress/t/t_flag_werror_bad2.out | 2 +- test_regress/t/t_flag_wfatal.out | 2 +- test_regress/t/t_for_comma_bad.out | 2 +- test_regress/t/t_fork.out | 2 +- test_regress/t/t_fork_disable.out | 2 +- test_regress/t/t_func_bad.out | 2 +- test_regress/t/t_func_bad2.out | 2 +- test_regress/t/t_func_bad_width.out | 2 +- test_regress/t/t_func_const2_bad.out | 2 +- test_regress/t/t_func_const3_bad.out | 2 +- test_regress/t/t_func_const_bad.out | 2 +- test_regress/t/t_func_const_packed_array_bad.out | 2 +- test_regress/t/t_func_const_packed_struct_bad.out | 2 +- test_regress/t/t_func_const_packed_struct_bad2.out | 2 +- test_regress/t/t_func_const_struct_bad.out | 2 +- test_regress/t/t_func_impure_bad.out | 2 +- test_regress/t/t_func_tasknsvar_bad.out | 2 +- test_regress/t/t_func_void_bad.out | 2 +- test_regress/t/t_func_wide_out_bad.out | 2 +- test_regress/t/t_fuzz_always_bad.out | 2 +- test_regress/t/t_fuzz_genintf_bad.out | 2 +- test_regress/t/t_fuzz_triand_bad.out | 2 +- test_regress/t/t_gen_cond_bitrange_bad.out | 2 +- test_regress/t/t_gen_defparam_unsup_bad.out | 2 +- test_regress/t/t_generate_fatal_bad.out | 2 +- test_regress/t/t_hier_block1_bad.out | 2 +- test_regress/t/t_hierarchy_identifier_bad.out | 2 +- test_regress/t/t_increment_bad.out | 2 +- test_regress/t/t_initial_dlyass_bad.out | 2 +- test_regress/t/t_inst_missing_bad.out | 2 +- test_regress/t/t_inst_overwide_bad.out | 2 +- test_regress/t/t_inst_pin_realnreal.out | 2 +- test_regress/t/t_inst_recurse2_bad.out | 2 +- test_regress/t/t_inst_recurse_bad.out | 2 +- test_regress/t/t_interface_array_nocolon_bad.out | 2 +- test_regress/t/t_interface_top_bad.out | 2 +- test_regress/t/t_interface_typedef.out | 2 +- test_regress/t/t_lint_always_comb_bad.out | 2 +- test_regress/t/t_lint_blksync_bad.out | 2 +- test_regress/t/t_lint_bsspace_bad.out | 2 +- test_regress/t/t_lint_caseincomplete_bad.out | 2 +- test_regress/t/t_lint_cmpconst_bad.out | 2 +- test_regress/t/t_lint_colonplus_bad.out | 2 +- test_regress/t/t_lint_declfilename_bad.out | 2 +- test_regress/t/t_lint_defparam_bad.out | 2 +- test_regress/t/t_lint_eofline_bad.out | 2 +- test_regress/t/t_lint_ifdepth_bad.out | 2 +- test_regress/t/t_lint_implicit_bad.out | 2 +- test_regress/t/t_lint_implicit_def_bad.out | 2 +- test_regress/t/t_lint_import_name2_bad.out | 2 +- test_regress/t/t_lint_importstar_bad.out | 2 +- test_regress/t/t_lint_incabspath_bad.out | 2 +- test_regress/t/t_lint_infinite.out | 2 +- test_regress/t/t_lint_input_eq_bad.out | 2 +- test_regress/t/t_lint_latch_bad.out | 2 +- test_regress/t/t_lint_latch_bad_2.out | 2 +- test_regress/t/t_lint_latch_bad_3.out | 2 +- test_regress/t/t_lint_literal_bad.out | 2 +- test_regress/t/t_lint_multidriven_bad.out | 2 +- test_regress/t/t_lint_nolatch_bad.out | 2 +- test_regress/t/t_lint_nullport.out | 2 +- test_regress/t/t_lint_once_bad.out | 2 +- test_regress/t/t_lint_pindup_bad.out | 2 +- test_regress/t/t_lint_pinnotfound_bad.out | 2 +- test_regress/t/t_lint_pkg_colon_bad.out | 2 +- test_regress/t/t_lint_realcvt_bad.out | 2 +- test_regress/t/t_lint_repeat_bad.out | 2 +- test_regress/t/t_lint_restore_bad.out | 2 +- test_regress/t/t_lint_rsvd_bad.out | 2 +- test_regress/t/t_lint_setout_bad.out | 2 +- test_regress/t/t_lint_setout_bad_noinl.out | 2 +- test_regress/t/t_lint_subout_bad.out | 2 +- test_regress/t/t_lint_syncasyncnet_bad.out | 2 +- test_regress/t/t_lint_unsigned_bad.out | 2 +- test_regress/t/t_lint_unused_bad.out | 2 +- test_regress/t/t_lint_unused_iface_bad.out | 2 +- test_regress/t/t_lint_width_bad.out | 2 +- test_regress/t/t_lint_width_docs_bad.out | 2 +- test_regress/t/t_lint_width_genfor_bad.out | 2 +- test_regress/t/t_math_countbits_bad.out | 2 +- test_regress/t/t_math_shortreal_unsup_bad.out | 2 +- test_regress/t/t_math_wide_bad.out | 2 +- test_regress/t/t_mem_multi_ref_bad.out | 2 +- test_regress/t/t_metacmt_onoff.out | 2 +- test_regress/t/t_mod_dup_bad.out | 2 +- test_regress/t/t_mod_interface_array3.out | 2 +- test_regress/t/t_multitop_sig_bad.out | 2 +- test_regress/t/t_order_blkandnblk_bad.out | 2 +- test_regress/t/t_order_blkloopinit_bad.out | 2 +- test_regress/t/t_order_clkinst_bad.out | 2 +- test_regress/t/t_packed_concat_bad.out | 2 +- test_regress/t/t_param_concat_bad.out | 2 +- test_regress/t/t_param_in_func_bad.out | 2 +- test_regress/t/t_param_noval_bad.out | 2 +- test_regress/t/t_param_scope_bad.out | 2 +- test_regress/t/t_param_sel_range_bad.out | 2 +- test_regress/t/t_past_bad.out | 2 +- test_regress/t/t_past_unsup_bad.out | 2 +- test_regress/t/t_pp_dupdef_bad.out | 2 +- test_regress/t/t_priority_case.out | 2 +- test_regress/t/t_process.out | 2 +- test_regress/t/t_prot_lib_inout_bad.out | 2 +- test_regress/t/t_protect_ids_bad.out | 2 +- test_regress/t/t_randc_unsup.out | 2 +- test_regress/t/t_randomize.out | 2 +- test_regress/t/t_randomize_method_types_unsup.out | 2 +- test_regress/t/t_randomize_method_unsup.out | 2 +- test_regress/t/t_savable_class_bad.out | 2 +- test_regress/t/t_select_bad_msb.out | 2 +- test_regress/t/t_select_bad_range.out | 2 +- test_regress/t/t_select_bad_range2.out | 2 +- test_regress/t/t_select_bad_range3.out | 2 +- test_regress/t/t_split_var_1_bad.out | 2 +- test_regress/t/t_stream_integer_type.out | 2 +- test_regress/t/t_struct_unpacked2.out | 2 +- test_regress/t/t_struct_unpacked_bad.out | 2 +- test_regress/t/t_sys_readmem_assoc_bad.out | 2 +- test_regress/t/t_timescale_lint_bad.out | 2 +- test_regress/t/t_tri_compass_bad.out | 2 +- test_regress/t/t_tri_pull2_bad.out | 2 +- test_regress/t/t_tri_pull_bad.out | 2 +- test_regress/t/t_tri_pullvec_bad.out | 2 +- test_regress/t/t_udp.out | 2 +- test_regress/t/t_udp_bad.out | 2 +- test_regress/t/t_unopt_combo_bad.out | 2 +- test_regress/t/t_unopt_converge_unopt_bad.out | 2 +- test_regress/t/t_unoptflat_simple_2_bad.out | 2 +- test_regress/t/t_unpacked_concat_bad.out | 2 +- test_regress/t/t_vams_kwd_bad.out | 2 +- test_regress/t/t_var_bad_hide.out | 2 +- test_regress/t/t_var_bad_hide2.out | 2 +- test_regress/t/t_var_bad_hide_docs.out | 2 +- test_regress/t/t_var_in_assign_bad.out | 2 +- test_regress/t/t_var_ref_bad3.out | 2 +- test_regress/t/t_var_rsvd_bad.out | 2 +- test_regress/t/t_var_static.out | 2 +- test_regress/t/t_var_static_param.out | 2 +- test_regress/t/t_var_types_bad.out | 2 +- test_regress/t/t_vlt_warn_bad.out | 2 +- test_regress/t/t_wait.out | 2 +- test_regress/t/t_wire_beh1364_bad.out | 2 +- test_regress/t/t_wire_beh1800_bad.out | 2 +- test_regress/t/t_wire_behp1364_bad.out | 2 +- test_regress/t/t_wire_behp1800_bad.out | 2 +- 181 files changed, 181 insertions(+), 180 deletions(-) diff --git a/test_regress/driver.pl b/test_regress/driver.pl index 26ca19722..4bd0ccc70 100755 --- a/test_regress/driver.pl +++ b/test_regress/driver.pl @@ -2144,6 +2144,7 @@ sub files_identical { $l1[$l] =~ s/Command Failed[^\n]+/Command Failed/mig; $l1[$l] =~ s/Version: Verilator[^\n]+/Version: Verilator ###/mig; $l1[$l] =~ s/CPU Time: +[0-9.]+ seconds[^\n]+/CPU Time: ###/mig; + $l1[$l] =~ s/\?v=[0-9.]+/?v=latest/mig; # warning URL if ($l1[$l] =~ s/Exiting due to.*/Exiting due to/mig) { splice @l1, $l+1; # Trunc rest last; diff --git a/test_regress/t/t_alias2_unsup.out b/test_regress/t/t_alias2_unsup.out index 5b408a195..41d9b4ee2 100644 --- a/test_regress/t/t_alias2_unsup.out +++ b/test_regress/t/t_alias2_unsup.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_alias2_unsup.v:39:4: Unsupported: alias statements 39 | alias b = {a[3:0],a[7:4]}; | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_alias_unsup.out b/test_regress/t/t_alias_unsup.out index 617b2d923..1288ef83f 100644 --- a/test_regress/t/t_alias_unsup.out +++ b/test_regress/t/t_alias_unsup.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_alias_unsup.v:46:4: Unsupported: alias statements 46 | alias {a[7:0],a[15:8],a[23:16],a[31:24]} = b; | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_array_list_bad.out b/test_regress/t/t_array_list_bad.out index ded2a3c8f..edf0db3e8 100644 --- a/test_regress/t/t_array_list_bad.out +++ b/test_regress/t/t_array_list_bad.out @@ -6,6 +6,6 @@ : ... In instance t 38 | test_out <= '{'0, '0}; | ^~ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_assert_comp_bad.out b/test_regress/t/t_assert_comp_bad.out index dddd9af67..759fcf96a 100644 --- a/test_regress/t/t_assert_comp_bad.out +++ b/test_regress/t/t_assert_comp_bad.out @@ -10,7 +10,7 @@ : ... In instance t 12 | $warning; | ^~~~~~~~ - ... For warning description see https://verilator.org/warn/USERWARN?v=4.201 + ... For warning description see https://verilator.org/warn/USERWARN?v=latest ... Use "/* verilator lint_off USERWARN */" and lint_on around source to disable this message. %Warning-USERWARN: t/t_assert_comp_bad.v:13:7: User elaboration-time warning : ... In instance t diff --git a/test_regress/t/t_assoc_wildcard_unsup.out b/test_regress/t/t_assoc_wildcard_unsup.out index 5939b8009..209295f7f 100644 --- a/test_regress/t/t_assoc_wildcard_unsup.out +++ b/test_regress/t/t_assoc_wildcard_unsup.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_assoc_wildcard_unsup.v:25:19: Unsupported: [*] wildcard associative arrays 25 | string a [*]; | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_case_x_bad.out b/test_regress/t/t_case_x_bad.out index 7647e1bd8..7c13a125b 100644 --- a/test_regress/t/t_case_x_bad.out +++ b/test_regress/t/t_case_x_bad.out @@ -1,7 +1,7 @@ %Warning-CASEX: t/t_case_x_bad.v:14:7: Suggest casez (with ?'s) in place of casex (with X's) 14 | casex (value) | ^~~~~ - ... For warning description see https://verilator.org/warn/CASEX?v=4.201 + ... For warning description see https://verilator.org/warn/CASEX?v=latest ... Use "/* verilator lint_off CASEX */" and lint_on around source to disable this message. %Warning-CASEWITHX: t/t_case_x_bad.v:19:9: Use of x/? constant in case statement, (perhaps intended casex/casez) 19 | 4'b1xxx: $stop; diff --git a/test_regress/t/t_case_zx_bad.out b/test_regress/t/t_case_zx_bad.out index 77bae7948..70c6a855e 100644 --- a/test_regress/t/t_case_zx_bad.out +++ b/test_regress/t/t_case_zx_bad.out @@ -1,6 +1,6 @@ %Warning-CASEWITHX: t/t_case_zx_bad.v:16:9: Use of x constant in casez statement, (perhaps intended ?/z in constant) 16 | 4'b1xxx: $stop; | ^~~~~~~ - ... For warning description see https://verilator.org/warn/CASEWITHX?v=4.201 + ... For warning description see https://verilator.org/warn/CASEWITHX?v=latest ... Use "/* verilator lint_off CASEWITHX */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_castdyn_castconst_bad.out b/test_regress/t/t_castdyn_castconst_bad.out index eb69bf69a..0251dc59e 100644 --- a/test_regress/t/t_castdyn_castconst_bad.out +++ b/test_regress/t/t_castdyn_castconst_bad.out @@ -3,7 +3,7 @@ : ... Suggest static cast 20 | i = $cast(v, 1); | ^~~~~ - ... For warning description see https://verilator.org/warn/CASTCONST?v=4.201 + ... For warning description see https://verilator.org/warn/CASTCONST?v=latest ... Use "/* verilator lint_off CASTCONST */" and lint_on around source to disable this message. %Warning-CASTCONST: t/t_castdyn_castconst_bad.v:21:11: $cast will always return one as 'CLASSREFDTYPE 'Base'' is always castable from 'CLASSREFDTYPE 'Base'' : ... In instance t diff --git a/test_regress/t/t_castdyn_unsup_bad.out b/test_regress/t/t_castdyn_unsup_bad.out index 6fc6e0993..328f9b91b 100644 --- a/test_regress/t/t_castdyn_unsup_bad.out +++ b/test_regress/t/t_castdyn_unsup_bad.out @@ -3,5 +3,5 @@ : ... Suggest try static cast 13 | $cast(q, aarray); | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_cdc_async_bad.out b/test_regress/t/t_cdc_async_bad.out index 29b887c6d..64dd3783f 100644 --- a/test_regress/t/t_cdc_async_bad.out +++ b/test_regress/t/t_cdc_async_bad.out @@ -1,7 +1,7 @@ %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:28:21: Logic in path that feeds async reset, via signal: 't.rst2_bad_n' 28 | wire rst2_bad_n = rst0_n | rst1_n; | ^ - ... For warning description see https://verilator.org/warn/CDCRSTLOGIC?v=4.201 + ... For warning description see https://verilator.org/warn/CDCRSTLOGIC?v=latest ... Use "/* verilator lint_off CDCRSTLOGIC */" and lint_on around source to disable this message. %Warning-CDCRSTLOGIC: See details in obj_vlt/t_cdc_async_bad/Vt_cdc_async_bad__cdc.txt %Warning-CDCRSTLOGIC: t/t_cdc_async_bad.v:53:21: Logic in path that feeds async reset, via signal: 't.rst6a_bad_n' diff --git a/test_regress/t/t_class_class.out b/test_regress/t/t_class_class.out index 52e4f1a5a..2ec79ad39 100644 --- a/test_regress/t/t_class_class.out +++ b/test_regress/t/t_class_class.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_class_class.v:12:4: Unsupported: class within class 12 | class SubCls; | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_class_extends_bad.out b/test_regress/t/t_class_extends_bad.out index ddb6fa925..eed5066dd 100644 --- a/test_regress/t/t_class_extends_bad.out +++ b/test_regress/t/t_class_extends_bad.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_class_extends_bad.v:13:26: Multiple inheritance illegal on non-interface classes (IEEE 1800-2017 8.13), and unsupported for interface classes. 13 | class Cls extends Base1, Base2; | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_class_local_bad.out b/test_regress/t/t_class_local_bad.out index 3e302dcb6..994f36a69 100644 --- a/test_regress/t/t_class_local_bad.out +++ b/test_regress/t/t_class_local_bad.out @@ -5,7 +5,7 @@ t/t_class_local_bad.v:71:20: ... Location of definition 15 | local int m_loc = 2; | ^~~~~ - ... For error description see https://verilator.org/warn/ENCAPSULATED?v=4.201 + ... For error description see https://verilator.org/warn/ENCAPSULATED?v=latest %Error-ENCAPSULATED: t/t_class_local_bad.v:72:20: 'm_prot' is hidden as 'protected' within this context (IEEE 1800-2017 8.18) : ... In instance t 72 | bad(); if (c.m_prot != 20) $stop; diff --git a/test_regress/t/t_class_member_bad.out b/test_regress/t/t_class_member_bad.out index 9d42c83c6..6488c1673 100644 --- a/test_regress/t/t_class_member_bad.out +++ b/test_regress/t/t_class_member_bad.out @@ -7,6 +7,6 @@ : ... In instance t 18 | c.memb3 = 3; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_class_param.out b/test_regress/t/t_class_param.out index 9d6a6a7aa..6e28c9b3d 100644 --- a/test_regress/t/t_class_param.out +++ b/test_regress/t/t_class_param.out @@ -2,7 +2,7 @@ : ... In instance t 9 | class Cls #(parameter P = 12); | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_class_param.v:20:11: Unsupported: parameterized classes : ... In instance t 20 | Cls #(.P(4)) c4; diff --git a/test_regress/t/t_class_param_bad.out b/test_regress/t/t_class_param_bad.out index 5b964ef07..ef96bc2f3 100644 --- a/test_regress/t/t_class_param_bad.out +++ b/test_regress/t/t_class_param_bad.out @@ -2,7 +2,7 @@ : ... Suggested alternative: 'PARAMB' 12 | Cls #(.PARAMBAD(1)) c; | ^~~~~~~~ - ... For error description see https://verilator.org/warn/PINNOTFOUND?v=4.201 + ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2' 13 | Cls #(13, 1) cd; | ^ diff --git a/test_regress/t/t_class_static.out b/test_regress/t/t_class_static.out index acf6927d0..922e3f434 100644 --- a/test_regress/t/t_class_static.out +++ b/test_regress/t/t_class_static.out @@ -2,7 +2,7 @@ : ... In instance t 12 | static int c_st = 2; | ^~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_class_static.v:25:18: Unsupported: 'static' function/task variables : ... In instance t 25 | static int st = 2; st++; return st; diff --git a/test_regress/t/t_class_static_order.out b/test_regress/t/t_class_static_order.out index c11fb5441..211d7e595 100644 --- a/test_regress/t/t_class_static_order.out +++ b/test_regress/t/t_class_static_order.out @@ -2,7 +2,7 @@ : ... In instance t 23 | static ClsZ z = new; | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_class_static_order.v:34:16: Unsupported: 'static' class members : ... In instance t 34 | static ClsA a = new; diff --git a/test_regress/t/t_class_unsup_bad.out b/test_regress/t/t_class_unsup_bad.out index 2f41c590f..9b2c8fa30 100644 --- a/test_regress/t/t_class_unsup_bad.out +++ b/test_regress/t/t_class_unsup_bad.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_class_unsup_bad.v:7:1: Unsupported: virtual interface 7 | virtual interface vi_t vi; | ^~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_class_unsup_bad.v:8:1: Unsupported: virtual data type 8 | virtual vi_t vi2; | ^~~~~~~ diff --git a/test_regress/t/t_class_vparam.out b/test_regress/t/t_class_vparam.out index 02394f30e..7c4a4ba3d 100644 --- a/test_regress/t/t_class_vparam.out +++ b/test_regress/t/t_class_vparam.out @@ -2,7 +2,7 @@ : ... In instance t 11 | typedef paramed_class_t#(real, 1) paramed_class_double_t; | ^~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_class_vparam.v:13:56: Unsupported: class parameters : ... In instance t 13 | virtual class vclass #(type CTYPE_t = arg_class_t, int I = 0); diff --git a/test_regress/t/t_clk_first_bad.out b/test_regress/t/t_clk_first_bad.out index 5245ee96d..6ed468978 100644 --- a/test_regress/t/t_clk_first_bad.out +++ b/test_regress/t/t_clk_first_bad.out @@ -1,6 +1,6 @@ %Warning-DEPRECATED: t/t_clk_first_deprecated.v:12:14: sc_clock is ignored 12 | input clk /*verilator sc_clock*/ ; | ^~~~~~~~~~~~~~~~~~~~~~ - ... For warning description see https://verilator.org/warn/DEPRECATED?v=4.201 + ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_clk_scope_bad.out b/test_regress/t/t_clk_scope_bad.out index cae7ba966..024049366 100644 --- a/test_regress/t/t_clk_scope_bad.out +++ b/test_regress/t/t_clk_scope_bad.out @@ -2,6 +2,6 @@ : ... In instance t.p2 36 | q <= d; | ^ - ... For warning description see https://verilator.org/warn/CLKDATA?v=4.201 + ... For warning description see https://verilator.org/warn/CLKDATA?v=latest ... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_clocker_bad.out b/test_regress/t/t_clocker_bad.out index ec0b9542f..c32ce2551 100644 --- a/test_regress/t/t_clocker_bad.out +++ b/test_regress/t/t_clocker_bad.out @@ -1,7 +1,7 @@ %Warning-CLKDATA: t/t_clocker.v:45:17: Clock is assigned to part of data signal 'res8' 45 | assign res8 = {clk_3, 1'b0, clk_4}; | ^ - ... For warning description see https://verilator.org/warn/CLKDATA?v=4.201 + ... For warning description see https://verilator.org/warn/CLKDATA?v=latest ... Use "/* verilator lint_off CLKDATA */" and lint_on around source to disable this message. %Warning-CLKDATA: t/t_clocker.v:46:17: Clock is assigned to part of data signal 'res16' 46 | assign res16 = {count, clk_3, clk_1, clk_4}; diff --git a/test_regress/t/t_concat_large_bad.out b/test_regress/t/t_concat_large_bad.out index c692aa033..1874895ef 100644 --- a/test_regress/t/t_concat_large_bad.out +++ b/test_regress/t/t_concat_large_bad.out @@ -2,6 +2,6 @@ : ... In instance t 9 | wire [32767:0] a = {32768{1'b1}}; | ^ - ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_concat_link_bad.out b/test_regress/t/t_concat_link_bad.out index 3af888452..5a1719518 100644 --- a/test_regress/t/t_concat_link_bad.out +++ b/test_regress/t/t_concat_link_bad.out @@ -10,6 +10,6 @@ %Warning-IMPLICIT: t/t_concat_link_bad.v:13:12: Signal definition not found, creating implicitly: 'bar_s' 13 | assign bar_s = {foo_s, foo_s}.f1; | ^~~~~ - ... For warning description see https://verilator.org/warn/IMPLICIT?v=4.201 + ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_const_bad.out b/test_regress/t/t_const_bad.out index ece6e4628..7aace9782 100644 --- a/test_regress/t/t_const_bad.out +++ b/test_regress/t/t_const_bad.out @@ -2,7 +2,7 @@ : ... In instance t 13 | if (68'hx_xxxxxxxx_xxxxxxxx !== 'dX) $stop; | ^~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_const_bad.v:14:39: Unsized constant being X/Z extended to 68 bits: ?32?bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz : ... In instance t diff --git a/test_regress/t/t_delay_stmtdly_bad.out b/test_regress/t/t_delay_stmtdly_bad.out index 1d0bb8faa..8b8482f3e 100644 --- a/test_regress/t/t_delay_stmtdly_bad.out +++ b/test_regress/t/t_delay_stmtdly_bad.out @@ -1,7 +1,7 @@ %Warning-ASSIGNDLY: t/t_delay.v:22:13: Unsupported: Ignoring delay on this assignment/primitive. 22 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1; | ^~~~~~~~~~~~~~~~~~ - ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=4.201 + ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message. %Warning-ASSIGNDLY: t/t_delay.v:27:19: Unsupported: Ignoring delay on this assignment/primitive. 27 | dly0 <= #0 32'h11; diff --git a/test_regress/t/t_dpi_unpack_bad.out b/test_regress/t/t_dpi_unpack_bad.out index fdb556ff2..0c7aa4fec 100644 --- a/test_regress/t/t_dpi_unpack_bad.out +++ b/test_regress/t/t_dpi_unpack_bad.out @@ -2,7 +2,7 @@ : ... In instance t 21 | import_func0(sig0); | ^~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Warning-WIDTH: t/t_dpi_unpack_bad.v:21:7: Operator TASKREF 'import_func0' expects 4 bits on the Function Argument, but Function Argument's VARREF 'sig0' generates 3 bits. : ... In instance t 21 | import_func0(sig0); diff --git a/test_regress/t/t_dynarray_bad.out b/test_regress/t/t_dynarray_bad.out index ba0ea8ceb..af5fe4a48 100644 --- a/test_regress/t/t_dynarray_bad.out +++ b/test_regress/t/t_dynarray_bad.out @@ -2,7 +2,7 @@ : ... In instance t 15 | a = new [s]; | ^~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Internal Error: t/t_dynarray_bad.v:15:16: ../V3Number.cpp:#: Number operation called with non-logic (double or string) argument: '"str"" 15 | a = new [s]; diff --git a/test_regress/t/t_enum_bad_hide.out b/test_regress/t/t_enum_bad_hide.out index c1fd3b364..037bd0eae 100644 --- a/test_regress/t/t_enum_bad_hide.out +++ b/test_regress/t/t_enum_bad_hide.out @@ -4,6 +4,6 @@ t/t_enum_bad_hide.v:7:16: ... Location of original declaration 11 | typedef enum { HIDE_VALUE = 0 } hide_enum_t; | ^~~~~~~~~~ - ... For warning description see https://verilator.org/warn/VARHIDDEN?v=4.201 + ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_event_control_unsup.out b/test_regress/t/t_event_control_unsup.out index a3fbe9c7a..1b0a26e28 100644 --- a/test_regress/t/t_event_control_unsup.out +++ b/test_regress/t/t_event_control_unsup.out @@ -3,7 +3,7 @@ : ... Suggest have one timing control statement per procedure, at the top of the procedure 14 | @(clk); | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_event_control_unsup.v:16:7: Unsupported: timing control statement in this location : ... In instance t : ... Suggest have one timing control statement per procedure, at the top of the procedure diff --git a/test_regress/t/t_event_copy.out b/test_regress/t/t_event_copy.out index 75578639b..9965cd23e 100644 --- a/test_regress/t/t_event_copy.out +++ b/test_regress/t/t_event_copy.out @@ -2,7 +2,7 @@ : ... In instance t 100 | e4 = e3; | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_event_copy.v:101:13: Unsupported: assignment of event data type : ... In instance t 101 | e3 = e2; diff --git a/test_regress/t/t_flag_context_bad.out b/test_regress/t/t_flag_context_bad.out index 118128d94..bfe90fd33 100644 --- a/test_regress/t/t_flag_context_bad.out +++ b/test_regress/t/t_flag_context_bad.out @@ -1,6 +1,6 @@ %Warning-WIDTH: t/t_flag_context_bad.v:9:19: Operator ASSIGNW expects 3 bits on the Assign RHS, but Assign RHS's CONST '5'h1f' generates 5 bits. : ... In instance t - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_flag_context_bad.v:9:15: Signal is not used: 'foo' : ... In instance t diff --git a/test_regress/t/t_flag_main_sc_bad.out b/test_regress/t/t_flag_main_sc_bad.out index b4d2bbc94..adff55338 100644 --- a/test_regress/t/t_flag_main_sc_bad.out +++ b/test_regress/t/t_flag_main_sc_bad.out @@ -1,3 +1,3 @@ %Error-UNSUPPORTED: --main not usable with SystemC. Suggest see examples for sc_main(). - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_flag_topmodule_bad.out b/test_regress/t/t_flag_topmodule_bad.out index 0f3d497dd..1267f0b5d 100644 --- a/test_regress/t/t_flag_topmodule_bad.out +++ b/test_regress/t/t_flag_topmodule_bad.out @@ -1,6 +1,6 @@ %Warning-MULTITOP: t/t_flag_topmodule.v:15:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. - ... For warning description see https://verilator.org/warn/MULTITOP?v=4.201 + ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' 7 | module a; diff --git a/test_regress/t/t_flag_werror_bad1.out b/test_regress/t/t_flag_werror_bad1.out index 0d65fde0a..844fdafb0 100644 --- a/test_regress/t/t_flag_werror_bad1.out +++ b/test_regress/t/t_flag_werror_bad1.out @@ -2,6 +2,6 @@ : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_flag_werror_bad2.out b/test_regress/t/t_flag_werror_bad2.out index ae9811417..169d7bcc5 100644 --- a/test_regress/t/t_flag_werror_bad2.out +++ b/test_regress/t/t_flag_werror_bad2.out @@ -2,5 +2,5 @@ : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ - ... For error description see https://verilator.org/warn/WIDTH?v=4.201 + ... For error description see https://verilator.org/warn/WIDTH?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_flag_wfatal.out b/test_regress/t/t_flag_wfatal.out index 19da7e11a..6ce45b931 100644 --- a/test_regress/t/t_flag_wfatal.out +++ b/test_regress/t/t_flag_wfatal.out @@ -2,5 +2,5 @@ : ... In instance t 10 | wire [3:0] foo = 6'h2e; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_for_comma_bad.out b/test_regress/t/t_for_comma_bad.out index f09139918..d430f98c9 100644 --- a/test_regress/t/t_for_comma_bad.out +++ b/test_regress/t/t_for_comma_bad.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_for_comma_bad.v:27:23: Unsupported: for loop initialization after the first comma 27 | for (integer a=0, integer b=0; a<1; ) ; | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_for_comma_bad.v:28:23: Unsupported: for loop initialization after the first comma 28 | for (integer a=0, integer b=0; a<1; a=a+1) ; | ^ diff --git a/test_regress/t/t_fork.out b/test_regress/t/t_fork.out index 6ecddc01a..f0f3b3489 100644 --- a/test_regress/t/t_fork.out +++ b/test_regress/t/t_fork.out @@ -2,5 +2,5 @@ : ... In instance t 10 | fork : fblk | ^~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_fork_disable.out b/test_regress/t/t_fork_disable.out index 1e9b60a94..9c589b372 100644 --- a/test_regress/t/t_fork_disable.out +++ b/test_regress/t/t_fork_disable.out @@ -2,7 +2,7 @@ : ... In instance t 12 | fork | ^~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_fork_disable.v:16:7: Unsupported: disable fork statements : ... In instance t 16 | disable fork; diff --git a/test_regress/t/t_func_bad.out b/test_regress/t/t_func_bad.out index bf3079498..cac076c15 100644 --- a/test_regress/t/t_func_bad.out +++ b/test_regress/t/t_func_bad.out @@ -14,7 +14,7 @@ : ... In instance t 11 | x; | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_func_bad.v:14:17: No such argument 'no_such' in function call to FUNC 'f' : ... In instance t 14 | f(.j(1), .no_such(2)); diff --git a/test_regress/t/t_func_bad2.out b/test_regress/t/t_func_bad2.out index 45ebfd990..ee66206cb 100644 --- a/test_regress/t/t_func_bad2.out +++ b/test_regress/t/t_func_bad2.out @@ -2,5 +2,5 @@ : ... In instance t 8 | function recurse; | ^~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_func_bad_width.out b/test_regress/t/t_func_bad_width.out index 257dd5a85..03b1ee7dd 100644 --- a/test_regress/t/t_func_bad_width.out +++ b/test_regress/t/t_func_bad_width.out @@ -2,7 +2,7 @@ : ... In instance t 13 | out = MUX (in); | ^~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_func_bad_width.v:13:11: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's FUNCREF 'MUX' generates 32 bits. : ... In instance t diff --git a/test_regress/t/t_func_const2_bad.out b/test_regress/t/t_func_const2_bad.out index 551d44cd7..05647a61d 100644 --- a/test_regress/t/t_func_const2_bad.out +++ b/test_regress/t/t_func_const2_bad.out @@ -1,5 +1,5 @@ %Warning-USERFATAL: "f_add = 15" - ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 + ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const2_bad.v:22:23: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t.b8_a7.c9 diff --git a/test_regress/t/t_func_const3_bad.out b/test_regress/t/t_func_const3_bad.out index 6c9c15118..5390514c9 100644 --- a/test_regress/t/t_func_const3_bad.out +++ b/test_regress/t/t_func_const3_bad.out @@ -2,6 +2,6 @@ : ... In instance t.b9k.c9 12 | localparam SOMEP = {BITS{1'b0}}; | ^ - ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_func_const_bad.out b/test_regress/t/t_func_const_bad.out index 7ce99926e..22ecf6b39 100644 --- a/test_regress/t/t_func_const_bad.out +++ b/test_regress/t/t_func_const_bad.out @@ -35,7 +35,7 @@ -Info: "Printing in loop: 1" -Info: "Printing in loop: 2" %Warning-USERFATAL: "Fatal Error" - ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 + ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_bad.v:50:24: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_bad_fatal' : ... In instance t diff --git a/test_regress/t/t_func_const_packed_array_bad.out b/test_regress/t/t_func_const_packed_array_bad.out index b8f7bd61c..19284f0eb 100644 --- a/test_regress/t/t_func_const_packed_array_bad.out +++ b/test_regress/t/t_func_const_packed_array_bad.out @@ -1,5 +1,5 @@ %Warning-USERFATAL: "f_add = 15" - ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 + ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_array_bad.v:12:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t diff --git a/test_regress/t/t_func_const_packed_struct_bad.out b/test_regress/t/t_func_const_packed_struct_bad.out index ebfcf4d4f..6cc4a4d8e 100644 --- a/test_regress/t/t_func_const_packed_struct_bad.out +++ b/test_regress/t/t_func_const_packed_struct_bad.out @@ -1,5 +1,5 @@ %Warning-USERFATAL: "f_add = 15" - ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 + ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_struct_bad.v:14:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t diff --git a/test_regress/t/t_func_const_packed_struct_bad2.out b/test_regress/t/t_func_const_packed_struct_bad2.out index 27f87fb17..5090203c3 100644 --- a/test_regress/t/t_func_const_packed_struct_bad2.out +++ b/test_regress/t/t_func_const_packed_struct_bad2.out @@ -1,5 +1,5 @@ %Warning-USERFATAL: "f_add = 15" - ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 + ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_packed_struct_bad2.v:20:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t diff --git a/test_regress/t/t_func_const_struct_bad.out b/test_regress/t/t_func_const_struct_bad.out index 00d82b32d..a8fd8baf8 100644 --- a/test_regress/t/t_func_const_struct_bad.out +++ b/test_regress/t/t_func_const_struct_bad.out @@ -1,5 +1,5 @@ %Warning-USERFATAL: "f_add = 15" - ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 + ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_func_const_struct_bad.v:17:21: Expecting expression to be constant, but can't determine constant for FUNCREF 'f_add2' : ... In instance t diff --git a/test_regress/t/t_func_impure_bad.out b/test_regress/t/t_func_impure_bad.out index 9fb2a10f0..2174bcf9f 100644 --- a/test_regress/t/t_func_impure_bad.out +++ b/test_regress/t/t_func_impure_bad.out @@ -4,5 +4,5 @@ t/t_func_impure_bad.v:13:7: ... Location of the external reference: 't.sig' 13 | sig = '1; | ^~~ - ... For error description see https://verilator.org/warn/IMPURE?v=4.201 + ... For error description see https://verilator.org/warn/IMPURE?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_func_tasknsvar_bad.out b/test_regress/t/t_func_tasknsvar_bad.out index b60d15c95..b2338cb62 100644 --- a/test_regress/t/t_func_tasknsvar_bad.out +++ b/test_regress/t/t_func_tasknsvar_bad.out @@ -1,7 +1,7 @@ %Error-TASKNSVAR: t/t_func_tasknsvar_bad.v:16:29: Unsupported: Function/task input argument is not simple variable 16 | foo(bus_we_select_from[2]); | ^ - ... For error description see https://verilator.org/warn/TASKNSVAR?v=4.201 + ... For error description see https://verilator.org/warn/TASKNSVAR?v=latest %Error: Internal Error: t/t_func_tasknsvar_bad.v:10:7: ../V3Broken.cpp:#: Broken link in node (or something without maybePointedTo): m_varScopep && !m_varScopep->brokeExists() 10 | sig = '1; | ^~~ diff --git a/test_regress/t/t_func_void_bad.out b/test_regress/t/t_func_void_bad.out index 068f830ac..5671bb604 100644 --- a/test_regress/t/t_func_void_bad.out +++ b/test_regress/t/t_func_void_bad.out @@ -1,6 +1,6 @@ %Warning-IGNOREDRETURN: t/t_func_void_bad.v:26:7: Ignoring return value of non-void function (IEEE 1800-2017 13.4.1) 26 | f1(20); | ^~ - ... For warning description see https://verilator.org/warn/IGNOREDRETURN?v=4.201 + ... For warning description see https://verilator.org/warn/IGNOREDRETURN?v=latest ... Use "/* verilator lint_off IGNOREDRETURN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_func_wide_out_bad.out b/test_regress/t/t_func_wide_out_bad.out index 63a6fe26f..e10df9ce9 100644 --- a/test_regress/t/t_func_wide_out_bad.out +++ b/test_regress/t/t_func_wide_out_bad.out @@ -2,5 +2,5 @@ : ... In instance t 17 | func(msg); | ^~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_fuzz_always_bad.out b/test_regress/t/t_fuzz_always_bad.out index d79c7be5c..63a43015a 100644 --- a/test_regress/t/t_fuzz_always_bad.out +++ b/test_regress/t/t_fuzz_always_bad.out @@ -7,5 +7,5 @@ %Error-UNSUPPORTED: t/t_fuzz_always_bad.v:10:14: Unsupported: Complex statement in sensitivity list 10 | always @ c.a c:h; | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_fuzz_genintf_bad.out b/test_regress/t/t_fuzz_genintf_bad.out index df5d490ef..407d8e478 100644 --- a/test_regress/t/t_fuzz_genintf_bad.out +++ b/test_regress/t/t_fuzz_genintf_bad.out @@ -2,7 +2,7 @@ : ... In instance t 24 | j.e(0), | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Internal Error: t/t_fuzz_genintf_bad.v:24:11: ../V3Width.cpp:#: Unlinked pin data type : ... In instance t 24 | j.e(0), diff --git a/test_regress/t/t_fuzz_triand_bad.out b/test_regress/t/t_fuzz_triand_bad.out index 3af71a1ba..d2186a59e 100644 --- a/test_regress/t/t_fuzz_triand_bad.out +++ b/test_regress/t/t_fuzz_triand_bad.out @@ -2,7 +2,7 @@ : ... In instance t 8 | tri g=g.and.g; | ^~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Internal Error: t/t_fuzz_triand_bad.v:8:12: ../V3Width.cpp:#: Unlinked data type : ... In instance t 8 | tri g=g.and.g; diff --git a/test_regress/t/t_gen_cond_bitrange_bad.out b/test_regress/t/t_gen_cond_bitrange_bad.out index f8856e188..98d3aad6b 100644 --- a/test_regress/t/t_gen_cond_bitrange_bad.out +++ b/test_regress/t/t_gen_cond_bitrange_bad.out @@ -2,7 +2,7 @@ : ... In instance t.i_test_gen 58 | if ((g < (SIZE + 1)) && MASK[g]) begin | ^ - ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 + ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_gen_cond_bitrange_bad.v:70:32: Selection index out of range: 2:2 outside 1:0 : ... In instance t.i_test_gen diff --git a/test_regress/t/t_gen_defparam_unsup_bad.out b/test_regress/t/t_gen_defparam_unsup_bad.out index c6af09329..97a834b03 100644 --- a/test_regress/t/t_gen_defparam_unsup_bad.out +++ b/test_regress/t/t_gen_defparam_unsup_bad.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_gen_defparam_unsup_bad.v:9:16: Unsupported: defparam with more than one dot 9 | defparam a.b.W = 3; | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_gen_defparam_unsup_bad.v:9:17: syntax error, unexpected IDENTIFIER, expecting ',' or ';' 9 | defparam a.b.W = 3; | ^ diff --git a/test_regress/t/t_generate_fatal_bad.out b/test_regress/t/t_generate_fatal_bad.out index f35ff52e7..5eb417f9d 100644 --- a/test_regress/t/t_generate_fatal_bad.out +++ b/test_regress/t/t_generate_fatal_bad.out @@ -1,5 +1,5 @@ %Warning-USERFATAL: "boom" - ... For warning description see https://verilator.org/warn/USERFATAL?v=4.201 + ... For warning description see https://verilator.org/warn/USERFATAL?v=latest ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' : ... In instance t.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst diff --git a/test_regress/t/t_hier_block1_bad.out b/test_regress/t/t_hier_block1_bad.out index beffcd4ec..84af5a79c 100644 --- a/test_regress/t/t_hier_block1_bad.out +++ b/test_regress/t/t_hier_block1_bad.out @@ -3,7 +3,7 @@ ... Suggest remove verilator hier_block on this module 15 | module t ( | ^ - ... For warning description see https://verilator.org/warn/HIERBLOCK?v=4.201 + ... For warning description see https://verilator.org/warn/HIERBLOCK?v=latest ... Use "/* verilator lint_off HIERBLOCK */" and lint_on around source to disable this message. %Error: t/t_hier_block1_bad.v:44:32: Modport cannot be used at the hierarchical block boundary : ... In instance t.i_sub1 diff --git a/test_regress/t/t_hierarchy_identifier_bad.out b/test_regress/t/t_hierarchy_identifier_bad.out index 3a82d7ef6..b18adbb8e 100644 --- a/test_regress/t/t_hierarchy_identifier_bad.out +++ b/test_regress/t/t_hierarchy_identifier_bad.out @@ -1,7 +1,7 @@ %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:34:10: End label 'if_cnt_finish_bad' does not match begin label 'if_cnt_finish' 34 | end : if_cnt_finish_bad | ^~~~~~~~~~~~~~~~~ - ... For warning description see https://verilator.org/warn/ENDLABEL?v=4.201 + ... For warning description see https://verilator.org/warn/ENDLABEL?v=latest ... Use "/* verilator lint_off ENDLABEL */" and lint_on around source to disable this message. %Warning-ENDLABEL: t/t_hierarchy_identifier_bad.v:40:10: End label 'generate_for_bad' does not match begin label 'generate_for' 40 | end : generate_for_bad diff --git a/test_regress/t/t_increment_bad.out b/test_regress/t/t_increment_bad.out index 41c181a17..ef339225a 100644 --- a/test_regress/t/t_increment_bad.out +++ b/test_regress/t/t_increment_bad.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_increment_bad.v:15:31: Unsupported: Incrementation in this context. 15 | if (0 && test_string[pos++] != "e"); | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_increment_bad.v:16:19: Unsupported: Incrementation in this context. 16 | if (1 || pos-- != 1); | ^~ diff --git a/test_regress/t/t_initial_dlyass_bad.out b/test_regress/t/t_initial_dlyass_bad.out index 457395681..686788c11 100644 --- a/test_regress/t/t_initial_dlyass_bad.out +++ b/test_regress/t/t_initial_dlyass_bad.out @@ -2,7 +2,7 @@ : ... Suggest blocking assignments (=) 18 | a <= 22; | ^~ - ... For warning description see https://verilator.org/warn/INITIALDLY?v=4.201 + ... For warning description see https://verilator.org/warn/INITIALDLY?v=latest ... Use "/* verilator lint_off INITIALDLY */" and lint_on around source to disable this message. %Warning-INITIALDLY: t/t_initial_dlyass.v:19:9: Delayed assignments (<=) in initial or final block : ... Suggest blocking assignments (=) diff --git a/test_regress/t/t_inst_missing_bad.out b/test_regress/t/t_inst_missing_bad.out index 9bcc8c3a3..8f676d048 100644 --- a/test_regress/t/t_inst_missing_bad.out +++ b/test_regress/t/t_inst_missing_bad.out @@ -1,7 +1,7 @@ %Warning-PINNOCONNECT: t/t_inst_missing_bad.v:9:22: Cell pin is not connected: '__pinNumber2' 9 | sub sub (.ok(ok), , .nc()); | ^ - ... For warning description see https://verilator.org/warn/PINNOCONNECT?v=4.201 + ... For warning description see https://verilator.org/warn/PINNOCONNECT?v=latest ... Use "/* verilator lint_off PINNOCONNECT */" and lint_on around source to disable this message. %Warning-PINCONNECTEMPTY: t/t_inst_missing_bad.v:9:25: Cell pin connected by name with empty reference: 'nc' 9 | sub sub (.ok(ok), , .nc()); diff --git a/test_regress/t/t_inst_overwide_bad.out b/test_regress/t/t_inst_overwide_bad.out index 1faa3842d..5a2a10068 100644 --- a/test_regress/t/t_inst_overwide_bad.out +++ b/test_regress/t/t_inst_overwide_bad.out @@ -2,7 +2,7 @@ : ... In instance t 23 | .outy_w92 (outc_w30), | ^~~~~~~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_inst_overwide.v:24:14: Output port connection 'outz_w22' expects 22 bits on the pin connection, but pin connection's VARREF 'outd_w73' generates 73 bits. : ... In instance t diff --git a/test_regress/t/t_inst_pin_realnreal.out b/test_regress/t/t_inst_pin_realnreal.out index 81ab9079e..d78ce9a1e 100755 --- a/test_regress/t/t_inst_pin_realnreal.out +++ b/test_regress/t/t_inst_pin_realnreal.out @@ -2,5 +2,5 @@ : ... In instance t.netlist 51 | pga_model pga0(.in, .gain, .out(pga_out)); | ^~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse2_bad.out b/test_regress/t/t_inst_recurse2_bad.out index 56c231a8e..312a2bf48 100644 --- a/test_regress/t/t_inst_recurse2_bad.out +++ b/test_regress/t/t_inst_recurse2_bad.out @@ -2,5 +2,5 @@ : ... In instance t.looped.looped 18 | module looped ( ); | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_inst_recurse_bad.out b/test_regress/t/t_inst_recurse_bad.out index 71d014671..c9bbe810a 100644 --- a/test_regress/t/t_inst_recurse_bad.out +++ b/test_regress/t/t_inst_recurse_bad.out @@ -2,5 +2,5 @@ ... note: self-recursion (module instantiating itself directly) is supported. 18 | module looped ( ); | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_interface_array_nocolon_bad.out b/test_regress/t/t_interface_array_nocolon_bad.out index e20652d3d..f741b3b24 100644 --- a/test_regress/t/t_interface_array_nocolon_bad.out +++ b/test_regress/t/t_interface_array_nocolon_bad.out @@ -2,7 +2,7 @@ : ... In instance t 26 | foo_intf foos [N] (.x(X)); | ^ - ... For warning description see https://verilator.org/warn/LITENDIAN?v=4.201 + ... For warning description see https://verilator.org/warn/LITENDIAN?v=latest ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:27:28: Little endian instance range connecting to vector: left < right of instance range: [1:3] : ... In instance t diff --git a/test_regress/t/t_interface_top_bad.out b/test_regress/t/t_interface_top_bad.out index 198d9832b..bc52c39ba 100644 --- a/test_regress/t/t_interface_top_bad.out +++ b/test_regress/t/t_interface_top_bad.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_interface_top_bad.v:17:19: Unsupported: Interfaced port on top level module 17 | ifc.counter_mp c_data | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_interface_top_bad.v:17:4: Parent instance's interface is not found: 'ifc' 17 | ifc.counter_mp c_data | ^~~ diff --git a/test_regress/t/t_interface_typedef.out b/test_regress/t/t_interface_typedef.out index 7780462e8..c334ee402 100644 --- a/test_regress/t/t_interface_typedef.out +++ b/test_regress/t/t_interface_typedef.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_interface_typedef.v:46:4: Unsupported: SystemVerilog 2005 typedef in this context 46 | typedef ifc_if.struct_t struct_t; | ^~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_interface_typedef.v:51:16: syntax error, unexpected IDENTIFIER 51 | struct_t substruct; | ^~~~~~~~~ diff --git a/test_regress/t/t_lint_always_comb_bad.out b/test_regress/t/t_lint_always_comb_bad.out index 190e629fa..10d0e1dfb 100644 --- a/test_regress/t/t_lint_always_comb_bad.out +++ b/test_regress/t/t_lint_always_comb_bad.out @@ -2,7 +2,7 @@ : ... In instance t 29 | temp1 = 'h0; | ^~~~~ - ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_lint_always_comb_bad.v:31:9: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'temp1' : ... In instance t 31 | temp1 = (temp1_d1r - 'h1); diff --git a/test_regress/t/t_lint_blksync_bad.out b/test_regress/t/t_lint_blksync_bad.out index 4e09d0d77..5491f6d0e 100644 --- a/test_regress/t/t_lint_blksync_bad.out +++ b/test_regress/t/t_lint_blksync_bad.out @@ -2,7 +2,7 @@ : ... Suggest delayed assignments (<=) 24 | sync_blk = 1'b1; | ^ - ... For warning description see https://verilator.org/warn/BLKSEQ?v=4.201 + ... For warning description see https://verilator.org/warn/BLKSEQ?v=latest ... Use "/* verilator lint_off BLKSEQ */" and lint_on around source to disable this message. %Warning-COMBDLY: t/t_lint_blksync_bad.v:31:18: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) diff --git a/test_regress/t/t_lint_bsspace_bad.out b/test_regress/t/t_lint_bsspace_bad.out index a201e346f..a9093384c 100644 --- a/test_regress/t/t_lint_bsspace_bad.out +++ b/test_regress/t/t_lint_bsspace_bad.out @@ -1,7 +1,7 @@ %Warning-BSSPACE: t/t_lint_bsspace_bad.v:10:21: Backslash followed by whitespace, perhaps the whitespace is accidental? 10 | `define FOO blak \ | ^ - ... For warning description see https://verilator.org/warn/BSSPACE?v=4.201 + ... For warning description see https://verilator.org/warn/BSSPACE?v=latest ... Use "/* verilator lint_off BSSPACE */" and lint_on around source to disable this message. %Error: t/t_lint_bsspace_bad.v:11:4: syntax error, unexpected IDENTIFIER 11 | blak diff --git a/test_regress/t/t_lint_caseincomplete_bad.out b/test_regress/t/t_lint_caseincomplete_bad.out index 270deb3b8..30c63943d 100644 --- a/test_regress/t/t_lint_caseincomplete_bad.out +++ b/test_regress/t/t_lint_caseincomplete_bad.out @@ -1,6 +1,6 @@ %Warning-CASEINCOMPLETE: t/t_lint_caseincomplete_bad.v:15:7: Case values incompletely covered (example pattern 0x1) 15 | case (i) | ^~~~ - ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=4.201 + ... For warning description see https://verilator.org/warn/CASEINCOMPLETE?v=latest ... Use "/* verilator lint_off CASEINCOMPLETE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_cmpconst_bad.out b/test_regress/t/t_lint_cmpconst_bad.out index dd681d790..39cb5e47c 100644 --- a/test_regress/t/t_lint_cmpconst_bad.out +++ b/test_regress/t/t_lint_cmpconst_bad.out @@ -2,6 +2,6 @@ : ... In instance t 13 | if (uns > 3'b111) $stop; | ^ - ... For warning description see https://verilator.org/warn/CMPCONST?v=4.201 + ... For warning description see https://verilator.org/warn/CMPCONST?v=latest ... Use "/* verilator lint_off CMPCONST */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_colonplus_bad.out b/test_regress/t/t_lint_colonplus_bad.out index c9a14f7fe..afd366f72 100644 --- a/test_regress/t/t_lint_colonplus_bad.out +++ b/test_regress/t/t_lint_colonplus_bad.out @@ -1,6 +1,6 @@ %Warning-COLONPLUS: t/t_lint_colonplus_bad.v:13:25: Perhaps instead of ':+' the intent was '+:'? 13 | output [2:1] z = r[2 :+ 1]; | ^~ - ... For warning description see https://verilator.org/warn/COLONPLUS?v=4.201 + ... For warning description see https://verilator.org/warn/COLONPLUS?v=latest ... Use "/* verilator lint_off COLONPLUS */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_declfilename_bad.out b/test_regress/t/t_lint_declfilename_bad.out index 781bed362..a369cbf1a 100644 --- a/test_regress/t/t_lint_declfilename_bad.out +++ b/test_regress/t/t_lint_declfilename_bad.out @@ -1,6 +1,6 @@ %Warning-DECLFILENAME: t/t_lint_declfilename.v:7:8: Filename 't_lint_declfilename' does not match MODULE name: 't' 7 | module t; | ^ - ... For warning description see https://verilator.org/warn/DECLFILENAME?v=4.201 + ... For warning description see https://verilator.org/warn/DECLFILENAME?v=latest ... Use "/* verilator lint_off DECLFILENAME */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_defparam_bad.out b/test_regress/t/t_lint_defparam_bad.out index 92e0c2afe..a43768c0f 100644 --- a/test_regress/t/t_lint_defparam_bad.out +++ b/test_regress/t/t_lint_defparam_bad.out @@ -2,6 +2,6 @@ : ... Suggest use instantiation with #(.P(...etc...)) 10 | defparam sub.P = 2; | ^ - ... For warning description see https://verilator.org/warn/DEFPARAM?v=4.201 + ... For warning description see https://verilator.org/warn/DEFPARAM?v=latest ... Use "/* verilator lint_off DEFPARAM */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_eofline_bad.out b/test_regress/t/t_lint_eofline_bad.out index fb29efe09..6d20a0dc1 100644 --- a/test_regress/t/t_lint_eofline_bad.out +++ b/test_regress/t/t_lint_eofline_bad.out @@ -1,6 +1,6 @@ %Warning-EOFNEWLINE: obj_vlt/t_lint_eofline_bad/t_lint_eofline_bad.v:4:10: Missing newline at end of file (POSIX 3.206). : ... Suggest add newline. 4 | endmodule | ^ - ... For warning description see https://verilator.org/warn/EOFNEWLINE?v=4.201 + ... For warning description see https://verilator.org/warn/EOFNEWLINE?v=latest ... Use "/* verilator lint_off EOFNEWLINE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_ifdepth_bad.out b/test_regress/t/t_lint_ifdepth_bad.out index 7ebbe3ae0..01c910555 100644 --- a/test_regress/t/t_lint_ifdepth_bad.out +++ b/test_regress/t/t_lint_ifdepth_bad.out @@ -2,6 +2,6 @@ : ... In instance t 22 | else if (value==11) begin end | ^~ - ... For warning description see https://verilator.org/warn/IFDEPTH?v=4.201 + ... For warning description see https://verilator.org/warn/IFDEPTH?v=latest ... Use "/* verilator lint_off IFDEPTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_implicit_bad.out b/test_regress/t/t_lint_implicit_bad.out index 8b6f56209..95dda11c3 100644 --- a/test_regress/t/t_lint_implicit_bad.out +++ b/test_regress/t/t_lint_implicit_bad.out @@ -1,7 +1,7 @@ %Warning-IMPLICIT: t/t_lint_implicit.v:11:11: Signal definition not found, creating implicitly: 'b' 11 | assign b = 1'b1; | ^ - ... For warning description see https://verilator.org/warn/IMPLICIT?v=4.201 + ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Warning-IMPLICIT: t/t_lint_implicit.v:13:14: Signal definition not found, creating implicitly: 'nt0' 13 | or OR0 (nt0, a, b); diff --git a/test_regress/t/t_lint_implicit_def_bad.out b/test_regress/t/t_lint_implicit_def_bad.out index db0db28dd..c6c5dd5b1 100644 --- a/test_regress/t/t_lint_implicit_def_bad.out +++ b/test_regress/t/t_lint_implicit_def_bad.out @@ -1,7 +1,7 @@ %Warning-IMPLICIT: t/t_lint_implicit_def_bad.v:13:11: Signal definition not found, creating implicitly: 'imp_warn' 13 | assign imp_warn = 1'b1; | ^~~~~~~~ - ... For warning description see https://verilator.org/warn/IMPLICIT?v=4.201 + ... For warning description see https://verilator.org/warn/IMPLICIT?v=latest ... Use "/* verilator lint_off IMPLICIT */" and lint_on around source to disable this message. %Error: t/t_lint_implicit_def_bad.v:18:11: Signal definition not found, and implicit disabled with `default_nettype: 'imp_err' 18 | assign imp_err = 1'b1; diff --git a/test_regress/t/t_lint_import_name2_bad.out b/test_regress/t/t_lint_import_name2_bad.out index dff3c722b..3ab8d55b2 100644 --- a/test_regress/t/t_lint_import_name2_bad.out +++ b/test_regress/t/t_lint_import_name2_bad.out @@ -1,7 +1,7 @@ %Error-PKGNODECL: t/t_lint_import_name2_bad.v:7:8: Package/class 'missing' not found, and needs to be predeclared (IEEE 1800-2017 26.3) 7 | import missing::sigs; | ^~~~~~~ - ... For error description see https://verilator.org/warn/PKGNODECL?v=4.201 + ... For error description see https://verilator.org/warn/PKGNODECL?v=latest %Error: t/t_lint_import_name2_bad.v:7:8: Importing from missing package 'missing' 7 | import missing::sigs; | ^~~~~~~ diff --git a/test_regress/t/t_lint_importstar_bad.out b/test_regress/t/t_lint_importstar_bad.out index 73618c306..620847848 100644 --- a/test_regress/t/t_lint_importstar_bad.out +++ b/test_regress/t/t_lint_importstar_bad.out @@ -1,6 +1,6 @@ %Warning-IMPORTSTAR: t/t_lint_importstar_bad.v:11:12: Import::* in $unit scope may pollute global namespace 11 | import defs::*; | ^~ - ... For warning description see https://verilator.org/warn/IMPORTSTAR?v=4.201 + ... For warning description see https://verilator.org/warn/IMPORTSTAR?v=latest ... Use "/* verilator lint_off IMPORTSTAR */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_incabspath_bad.out b/test_regress/t/t_lint_incabspath_bad.out index 34f4f9b1e..c1baf4eb9 100644 --- a/test_regress/t/t_lint_incabspath_bad.out +++ b/test_regress/t/t_lint_incabspath_bad.out @@ -1,6 +1,6 @@ %Warning-INCABSPATH: t/t_lint_incabspath.v:7:10: Suggest `include with absolute path be made relative, and use +include: /dev/null 7 | `include "/dev/null" | ^~~~~~~~~~~ - ... For warning description see https://verilator.org/warn/INCABSPATH?v=4.201 + ... For warning description see https://verilator.org/warn/INCABSPATH?v=latest ... Use "/* verilator lint_off INCABSPATH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_infinite.out b/test_regress/t/t_lint_infinite.out index afbbe8b41..a47ba62d6 100644 --- a/test_regress/t/t_lint_infinite.out +++ b/test_regress/t/t_lint_infinite.out @@ -2,7 +2,7 @@ : ... In instance t 10 | forever begin end | ^~~~~~~ - ... For warning description see https://verilator.org/warn/INFINITELOOP?v=4.201 + ... For warning description see https://verilator.org/warn/INFINITELOOP?v=latest ... Use "/* verilator lint_off INFINITELOOP */" and lint_on around source to disable this message. %Warning-INFINITELOOP: t/t_lint_infinite.v:12:7: Infinite loop (condition always true) : ... In instance t diff --git a/test_regress/t/t_lint_input_eq_bad.out b/test_regress/t/t_lint_input_eq_bad.out index 0ed24b966..72e0fe5e3 100644 --- a/test_regress/t/t_lint_input_eq_bad.out +++ b/test_regress/t/t_lint_input_eq_bad.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_lint_input_eq_bad.v:10:15: Unsupported: Default value on module input: 'i2' 10 | input wire i2 = i | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad.out b/test_regress/t/t_lint_latch_bad.out index 1d5cd253a..e4c196c62 100644 --- a/test_regress/t/t_lint_latch_bad.out +++ b/test_regress/t/t_lint_latch_bad.out @@ -1,7 +1,7 @@ %Warning-NOLATCH: t/t_lint_latch_bad.v:17:4: No latches detected in always_latch block 17 | always_latch begin | ^~~~~~~~~~~~ - ... For warning description see https://verilator.org/warn/NOLATCH?v=4.201 + ... For warning description see https://verilator.org/warn/NOLATCH?v=latest ... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message. %Warning-COMBDLY: t/t_lint_latch_bad.v:25:10: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) diff --git a/test_regress/t/t_lint_latch_bad_2.out b/test_regress/t/t_lint_latch_bad_2.out index c909baf38..129267f09 100644 --- a/test_regress/t/t_lint_latch_bad_2.out +++ b/test_regress/t/t_lint_latch_bad_2.out @@ -2,6 +2,6 @@ : ... Suggest use of always_latch for intentional latches 11 | always @(a or b) | ^~~~~~ - ... For warning description see https://verilator.org/warn/LATCH?v=4.201 + ... For warning description see https://verilator.org/warn/LATCH?v=latest ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_latch_bad_3.out b/test_regress/t/t_lint_latch_bad_3.out index 94f96de5e..17b014783 100644 --- a/test_regress/t/t_lint_latch_bad_3.out +++ b/test_regress/t/t_lint_latch_bad_3.out @@ -2,7 +2,7 @@ : ... Suggest use of always_latch for intentional latches 18 | always @(reset or en or a or b) | ^~~~~~ - ... For warning description see https://verilator.org/warn/LATCH?v=4.201 + ... For warning description see https://verilator.org/warn/LATCH?v=latest ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message. %Warning-COMBDLY: t/t_lint_latch_bad_3.v:70:12: Delayed assignments (<=) in non-clocked (non flop or latch) block : ... Suggest blocking assignments (=) diff --git a/test_regress/t/t_lint_literal_bad.out b/test_regress/t/t_lint_literal_bad.out index 077054d07..5cab1d60b 100644 --- a/test_regress/t/t_lint_literal_bad.out +++ b/test_regress/t/t_lint_literal_bad.out @@ -1,6 +1,6 @@ %Warning-WIDTH: t/t_lint_literal_bad.v:10:33: Value too large for 8 bit number: 256 10 | localparam the_localparam = 8'd256; | ^~~~~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_multidriven_bad.out b/test_regress/t/t_lint_multidriven_bad.out index 019c1db6f..ad7fb6500 100644 --- a/test_regress/t/t_lint_multidriven_bad.out +++ b/test_regress/t/t_lint_multidriven_bad.out @@ -5,7 +5,7 @@ t/t_lint_multidriven_bad.v:24:7: ... Location of other driving block 24 | mem[a0] <= d0; | ^~~ - ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=4.201 + ... For warning description see https://verilator.org/warn/MULTIDRIVEN?v=latest ... Use "/* verilator lint_off MULTIDRIVEN */" and lint_on around source to disable this message. %Warning-MULTIDRIVEN: t/t_lint_multidriven_bad.v:19:22: Signal has multiple driving blocks with different clocking: 'out2' t/t_lint_multidriven_bad.v:35:7: ... Location of first driving block diff --git a/test_regress/t/t_lint_nolatch_bad.out b/test_regress/t/t_lint_nolatch_bad.out index dd733be55..f4683645e 100644 --- a/test_regress/t/t_lint_nolatch_bad.out +++ b/test_regress/t/t_lint_nolatch_bad.out @@ -1,6 +1,6 @@ %Warning-NOLATCH: t/t_lint_nolatch_bad.v:11:4: No latches detected in always_latch block 11 | always_latch @(a or b) | ^~~~~~~~~~~~ - ... For warning description see https://verilator.org/warn/NOLATCH?v=4.201 + ... For warning description see https://verilator.org/warn/NOLATCH?v=latest ... Use "/* verilator lint_off NOLATCH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_nullport.out b/test_regress/t/t_lint_nullport.out index f784bfd69..f08b86c22 100644 --- a/test_regress/t/t_lint_nullport.out +++ b/test_regress/t/t_lint_nullport.out @@ -1,7 +1,7 @@ %Warning-NULLPORT: t/t_lint_nullport.v:23:13: Null port on module (perhaps extraneous comma) 23 | module t5(a,); | ^ - ... For warning description see https://verilator.org/warn/NULLPORT?v=4.201 + ... For warning description see https://verilator.org/warn/NULLPORT?v=latest ... Use "/* verilator lint_off NULLPORT */" and lint_on around source to disable this message. %Warning-NULLPORT: t/t_lint_nullport.v:27:13: Null port on module (perhaps extraneous comma) 27 | module t6(a,,); diff --git a/test_regress/t/t_lint_once_bad.out b/test_regress/t/t_lint_once_bad.out index f2faa4809..4a8917764 100644 --- a/test_regress/t/t_lint_once_bad.out +++ b/test_regress/t/t_lint_once_bad.out @@ -2,7 +2,7 @@ : ... In instance t.sub3 19 | reg [A:0] unus1; reg [A:0] unus2; | ^~~~~ - ... For warning description see https://verilator.org/warn/UNUSED?v=4.201 + ... For warning description see https://verilator.org/warn/UNUSED?v=latest ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_lint_once_bad.v:19:34: Signal is not driven, nor used: 'unus2' : ... In instance t.sub3 diff --git a/test_regress/t/t_lint_pindup_bad.out b/test_regress/t/t_lint_pindup_bad.out index 06f37dba0..94b81c87b 100644 --- a/test_regress/t/t_lint_pindup_bad.out +++ b/test_regress/t/t_lint_pindup_bad.out @@ -1,7 +1,7 @@ %Warning-PINMISSING: t/t_lint_pindup_bad.v:19:4: Cell has missing pin: 'exists' 19 | sub (.o(o), | ^~~ - ... For warning description see https://verilator.org/warn/PINMISSING?v=4.201 + ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_lint_pindup_bad.v:21:10: Duplicate pin connection: 'i' 21 | .i(i2), diff --git a/test_regress/t/t_lint_pinnotfound_bad.out b/test_regress/t/t_lint_pinnotfound_bad.out index ddab6577d..81a6f40e5 100644 --- a/test_regress/t/t_lint_pinnotfound_bad.out +++ b/test_regress/t/t_lint_pinnotfound_bad.out @@ -1,7 +1,7 @@ %Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:12:13: Pin not found: 'x' 12 | b b_inst1 (.x(1'b0)); | ^ - ... For error description see https://verilator.org/warn/PINNOTFOUND?v=4.201 + ... For error description see https://verilator.org/warn/PINNOTFOUND?v=latest %Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:13:6: Parameter pin not found: 'PX' 13 | b #(.PX(1'b0)) b_inst2 (); | ^~ diff --git a/test_regress/t/t_lint_pkg_colon_bad.out b/test_regress/t/t_lint_pkg_colon_bad.out index 3b7702707..7e261c4ff 100644 --- a/test_regress/t/t_lint_pkg_colon_bad.out +++ b/test_regress/t/t_lint_pkg_colon_bad.out @@ -1,7 +1,7 @@ %Error-PKGNODECL: t/t_lint_pkg_colon_bad.v:7:17: Package/class 'mispkg' not found, and needs to be predeclared (IEEE 1800-2017 26.3) 7 | module t (input mispkg::foo_t a); | ^~~~~~ - ... For error description see https://verilator.org/warn/PKGNODECL?v=4.201 + ... For error description see https://verilator.org/warn/PKGNODECL?v=latest %Error: t/t_lint_pkg_colon_bad.v:7:25: syntax error, unexpected IDENTIFIER, expecting TYPE-IDENTIFIER 7 | module t (input mispkg::foo_t a); | ^~~~~ diff --git a/test_regress/t/t_lint_realcvt_bad.out b/test_regress/t/t_lint_realcvt_bad.out index a240a3eb0..41625798c 100644 --- a/test_regress/t/t_lint_realcvt_bad.out +++ b/test_regress/t/t_lint_realcvt_bad.out @@ -1,6 +1,6 @@ %Warning-REALCVT: t/t_lint_realcvt_bad.v:10:11: Implicit conversion of real to integer 10 | i = 23.2; | ^~~~ - ... For warning description see https://verilator.org/warn/REALCVT?v=4.201 + ... For warning description see https://verilator.org/warn/REALCVT?v=latest ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_repeat_bad.out b/test_regress/t/t_lint_repeat_bad.out index 80c9ae7ca..2d8287e78 100644 --- a/test_regress/t/t_lint_repeat_bad.out +++ b/test_regress/t/t_lint_repeat_bad.out @@ -2,6 +2,6 @@ : ... In instance t.sub2 18 | wire [0:0] b = a; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_restore_bad.out b/test_regress/t/t_lint_restore_bad.out index 7af6654bb..a38fcff3e 100644 --- a/test_regress/t/t_lint_restore_bad.out +++ b/test_regress/t/t_lint_restore_bad.out @@ -2,6 +2,6 @@ : ... In instance t 19 | initial five = 64'h1; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_rsvd_bad.out b/test_regress/t/t_lint_rsvd_bad.out index ceba8abfa..40c04db1e 100644 --- a/test_regress/t/t_lint_rsvd_bad.out +++ b/test_regress/t/t_lint_rsvd_bad.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_lint_rsvd_bad.v:7:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config' 7 | config cfgBad; | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_lint_rsvd_bad.v:7:8: syntax error, unexpected IDENTIFIER 7 | config cfgBad; | ^~~~~~ diff --git a/test_regress/t/t_lint_setout_bad.out b/test_regress/t/t_lint_setout_bad.out index 7271445c3..19e21e7d3 100644 --- a/test_regress/t/t_lint_setout_bad.out +++ b/test_regress/t/t_lint_setout_bad.out @@ -2,5 +2,5 @@ : ... In instance t 17 | .cpu_if_timeout(1'b0) | ^~~~~~~~~~~~~~ - ... For error description see https://verilator.org/warn/PORTSHORT?v=4.201 + ... For error description see https://verilator.org/warn/PORTSHORT?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_lint_setout_bad_noinl.out b/test_regress/t/t_lint_setout_bad_noinl.out index 7271445c3..19e21e7d3 100644 --- a/test_regress/t/t_lint_setout_bad_noinl.out +++ b/test_regress/t/t_lint_setout_bad_noinl.out @@ -2,5 +2,5 @@ : ... In instance t 17 | .cpu_if_timeout(1'b0) | ^~~~~~~~~~~~~~ - ... For error description see https://verilator.org/warn/PORTSHORT?v=4.201 + ... For error description see https://verilator.org/warn/PORTSHORT?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_lint_subout_bad.out b/test_regress/t/t_lint_subout_bad.out index fa5b64ae6..846d5de89 100644 --- a/test_regress/t/t_lint_subout_bad.out +++ b/test_regress/t/t_lint_subout_bad.out @@ -2,7 +2,7 @@ : ... In instance t 12 | sub sub1(.out({32'b0, sig})); | ^~~ - ... For error description see https://verilator.org/warn/PORTSHORT?v=4.201 + ... For error description see https://verilator.org/warn/PORTSHORT?v=latest %Error-PORTSHORT: t/t_lint_subout_bad.v:13:14: Output port is connected to a constant pin, electrical short : ... In instance t 13 | sub sub2(.out({32'b1, sig})); diff --git a/test_regress/t/t_lint_syncasyncnet_bad.out b/test_regress/t/t_lint_syncasyncnet_bad.out index 8508061a7..d675d43ad 100644 --- a/test_regress/t/t_lint_syncasyncnet_bad.out +++ b/test_regress/t/t_lint_syncasyncnet_bad.out @@ -5,6 +5,6 @@ t/t_lint_syncasyncnet_bad.v:34:14: ... Location of sync usage 34 | q2 <= (rst_both_l) ? d : 1'b0; | ^~~~~~~~~~ - ... For warning description see https://verilator.org/warn/SYNCASYNCNET?v=4.201 + ... For warning description see https://verilator.org/warn/SYNCASYNCNET?v=latest ... Use "/* verilator lint_off SYNCASYNCNET */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_unsigned_bad.out b/test_regress/t/t_lint_unsigned_bad.out index 8fcfa685a..8f9d385b1 100644 --- a/test_regress/t/t_lint_unsigned_bad.out +++ b/test_regress/t/t_lint_unsigned_bad.out @@ -2,6 +2,6 @@ : ... In instance t 13 | if (uns < 0) $stop; | ^ - ... For warning description see https://verilator.org/warn/UNSIGNED?v=4.201 + ... For warning description see https://verilator.org/warn/UNSIGNED?v=latest ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_unused_bad.out b/test_regress/t/t_lint_unused_bad.out index 2bc76ead2..e8ebe7df3 100644 --- a/test_regress/t/t_lint_unused_bad.out +++ b/test_regress/t/t_lint_unused_bad.out @@ -2,7 +2,7 @@ : ... In instance t.sub 17 | wire [5:0] assunu1 = 0; | ^~~~~~~ - ... For warning description see https://verilator.org/warn/UNUSED?v=4.201 + ... For warning description see https://verilator.org/warn/UNUSED?v=latest ... Use "/* verilator lint_off UNUSED */" and lint_on around source to disable this message. %Warning-UNDRIVEN: t/t_lint_unused_bad.v:21:17: Bits of signal are not driven: 'udrb2'[14:13,11] : ... In instance t.sub diff --git a/test_regress/t/t_lint_unused_iface_bad.out b/test_regress/t/t_lint_unused_iface_bad.out index 691d50820..2615f6433 100644 --- a/test_regress/t/t_lint_unused_iface_bad.out +++ b/test_regress/t/t_lint_unused_iface_bad.out @@ -2,7 +2,7 @@ : ... In instance t.sub 8 | logic sig_udrv; | ^~~~~~~~ - ... For warning description see https://verilator.org/warn/UNDRIVEN?v=4.201 + ... For warning description see https://verilator.org/warn/UNDRIVEN?v=latest ... Use "/* verilator lint_off UNDRIVEN */" and lint_on around source to disable this message. %Warning-UNUSED: t/t_lint_unused_iface_bad.v:9:10: Signal is not used: 'sig_uusd' : ... In instance t.sub diff --git a/test_regress/t/t_lint_width_bad.out b/test_regress/t/t_lint_width_bad.out index 9fb7e5660..d1faa06e6 100644 --- a/test_regress/t/t_lint_width_bad.out +++ b/test_regress/t/t_lint_width_bad.out @@ -2,7 +2,7 @@ : ... In instance t 17 | localparam [3:0] XS = 'hx; | ^~ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_lint_width_bad.v:47:19: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits. : ... In instance t.p4 diff --git a/test_regress/t/t_lint_width_docs_bad.out b/test_regress/t/t_lint_width_docs_bad.out index 91057def8..0ecd7edd9 100644 --- a/test_regress/t/t_lint_width_docs_bad.out +++ b/test_regress/t/t_lint_width_docs_bad.out @@ -2,6 +2,6 @@ : ... In instance t 10 | wire int rd_value = array[rd_addr]; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_lint_width_genfor_bad.out b/test_regress/t/t_lint_width_genfor_bad.out index 915fc6c3c..e94e66164 100644 --- a/test_regress/t/t_lint_width_genfor_bad.out +++ b/test_regress/t/t_lint_width_genfor_bad.out @@ -2,7 +2,7 @@ : ... In instance t 25 | rg = g; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_lint_width_genfor_bad.v:26:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'P' generates 32 or 5 bits. : ... In instance t diff --git a/test_regress/t/t_math_countbits_bad.out b/test_regress/t/t_math_countbits_bad.out index 693cd2dfa..7b4675c8f 100755 --- a/test_regress/t/t_math_countbits_bad.out +++ b/test_regress/t/t_math_countbits_bad.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_math_countbits_bad.v:14:54: Unsupported: $countbits with more than 3 control fields 14 | assign count = $countbits(32'h123456, '0, '1, 'x, 'z); | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_math_shortreal_unsup_bad.out b/test_regress/t/t_math_shortreal_unsup_bad.out index c3401572b..df3739360 100644 --- a/test_regress/t/t_math_shortreal_unsup_bad.out +++ b/test_regress/t/t_math_shortreal_unsup_bad.out @@ -1,6 +1,6 @@ %Warning-SHORTREAL: t/t_math_shortreal_unsup_bad.v:9:4: Unsupported: shortreal being promoted to real (suggest use real instead) 9 | shortreal s; | ^~~~~~~~~ - ... For warning description see https://verilator.org/warn/SHORTREAL?v=4.201 + ... For warning description see https://verilator.org/warn/SHORTREAL?v=latest ... Use "/* verilator lint_off SHORTREAL */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_math_wide_bad.out b/test_regress/t/t_math_wide_bad.out index e30757c0f..ec2179c13 100644 --- a/test_regress/t/t_math_wide_bad.out +++ b/test_regress/t/t_math_wide_bad.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_math_wide_bad.v:22:18: Unsupported: operator POWSS operator of 576 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 22 | assign z2 = a ** 3; | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_math_wide_bad.v:23:15: Unsupported: operator ISTORD operator of 64 bits exceeds hardcoded limit VL_MULS_MAX_WORDS in verilatedos.h 23 | assign r = real'(a); | ^~~~ diff --git a/test_regress/t/t_mem_multi_ref_bad.out b/test_regress/t/t_mem_multi_ref_bad.out index 8ad024efe..8a43b779e 100644 --- a/test_regress/t/t_mem_multi_ref_bad.out +++ b/test_regress/t/t_mem_multi_ref_bad.out @@ -6,7 +6,7 @@ : ... In instance t 15 | dimn[1:0] = 0; | ^ - ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 + ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: t/t_mem_multi_ref_bad.v:16:14: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'logic' : ... In instance t diff --git a/test_regress/t/t_metacmt_onoff.out b/test_regress/t/t_metacmt_onoff.out index 46ae4fc1c..f57aee5e4 100644 --- a/test_regress/t/t_metacmt_onoff.out +++ b/test_regress/t/t_metacmt_onoff.out @@ -2,7 +2,7 @@ : ... In instance t 8 | reg [0:1] show1; /*verilator lint_off LITENDIAN*/ reg [0:2] ign2; /*verilator lint_on LITENDIAN*/ reg [0:3] show3; | ^ - ... For warning description see https://verilator.org/warn/LITENDIAN?v=4.201 + ... For warning description see https://verilator.org/warn/LITENDIAN?v=latest ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-LITENDIAN: t/t_metacmt_onoff.v:8:109: Little bit endian vector: left < right of bit range: [0:3] : ... In instance t diff --git a/test_regress/t/t_mod_dup_bad.out b/test_regress/t/t_mod_dup_bad.out index d194b4b22..fec90c643 100644 --- a/test_regress/t/t_mod_dup_bad.out +++ b/test_regress/t/t_mod_dup_bad.out @@ -4,7 +4,7 @@ t/t_mod_dup_bad.v:7:8: ... Location of original declaration 7 | module a(); | ^ - ... For warning description see https://verilator.org/warn/MODDUP?v=4.201 + ... For warning description see https://verilator.org/warn/MODDUP?v=latest ... Use "/* verilator lint_off MODDUP */" and lint_on around source to disable this message. %Warning-MULTITOP: t/t_mod_dup_bad.v:17:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. diff --git a/test_regress/t/t_mod_interface_array3.out b/test_regress/t/t_mod_interface_array3.out index 1d4e3404f..c3e75afa3 100644 --- a/test_regress/t/t_mod_interface_array3.out +++ b/test_regress/t/t_mod_interface_array3.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_mod_interface_array3.v:25:20: Unsupported: Multidimensional instances/interfaces. 25 | a_if iface [2:0][1:0]; | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_mod_interface_array3.v:27:18: Unsupported: Multidimensional instances/interfaces. 27 | sub i_sub[2:0][1:0] (.s(str)); | ^ diff --git a/test_regress/t/t_multitop_sig_bad.out b/test_regress/t/t_multitop_sig_bad.out index 9d1b70468..6221eab1b 100644 --- a/test_regress/t/t_multitop_sig_bad.out +++ b/test_regress/t/t_multitop_sig_bad.out @@ -1,6 +1,6 @@ %Warning-MULTITOP: t/t_multitop_sig.v:15:8: Multiple top level modules : ... Suggest see manual; fix the duplicates, or use --top-module to select top. - ... For warning description see https://verilator.org/warn/MULTITOP?v=4.201 + ... For warning description see https://verilator.org/warn/MULTITOP?v=latest ... Use "/* verilator lint_off MULTITOP */" and lint_on around source to disable this message. : ... Top module 'a' 7 | module a(in, out); diff --git a/test_regress/t/t_order_blkandnblk_bad.out b/test_regress/t/t_order_blkandnblk_bad.out index 387bf9d05..709176366 100644 --- a/test_regress/t/t_order_blkandnblk_bad.out +++ b/test_regress/t/t_order_blkandnblk_bad.out @@ -7,5 +7,5 @@ t/t_order_blkandnblk_bad.v:22:6: ... Location of nonblocking assignment 22 | array[1] <= array[0]; | ^~~~~ - ... For error description see https://verilator.org/warn/BLKANDNBLK?v=4.201 + ... For error description see https://verilator.org/warn/BLKANDNBLK?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_order_blkloopinit_bad.out b/test_regress/t/t_order_blkloopinit_bad.out index dc78ecf0b..56fd5c3ec 100644 --- a/test_regress/t/t_order_blkloopinit_bad.out +++ b/test_regress/t/t_order_blkloopinit_bad.out @@ -1,5 +1,5 @@ %Error-BLKLOOPINIT: t/t_order_blkloopinit_bad.v:21:19: Unsupported: Delayed assignment to array inside for loops (non-delayed is ok - see docs) 21 | array[i] <= 0; | ^~ - ... For error description see https://verilator.org/warn/BLKLOOPINIT?v=4.201 + ... For error description see https://verilator.org/warn/BLKLOOPINIT?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_order_clkinst_bad.out b/test_regress/t/t_order_clkinst_bad.out index 4d9f3562d..843d81b45 100644 --- a/test_regress/t/t_order_clkinst_bad.out +++ b/test_regress/t/t_order_clkinst_bad.out @@ -1,7 +1,7 @@ %Warning-IMPERFECTSCH: t/t_order_clkinst.v:19:16: Imperfect scheduling of variable: 't.c1_start' 19 | reg c1_start; initial c1_start = 0; | ^~~~~~~~ - ... For warning description see https://verilator.org/warn/IMPERFECTSCH?v=4.201 + ... For warning description see https://verilator.org/warn/IMPERFECTSCH?v=latest ... Use "/* verilator lint_off IMPERFECTSCH */" and lint_on around source to disable this message. %Warning-IMPERFECTSCH: t/t_order_clkinst.v:20:16: Imperfect scheduling of variable: 't.c1_count' 20 | wire [31:0] c1_count; diff --git a/test_regress/t/t_packed_concat_bad.out b/test_regress/t/t_packed_concat_bad.out index a0e92e05d..559a8c1ca 100644 --- a/test_regress/t/t_packed_concat_bad.out +++ b/test_regress/t/t_packed_concat_bad.out @@ -2,7 +2,7 @@ : ... In instance t 17 | localparam bit_int_t [1:0] count_bits = {2{$bits(count_t)}}; | ^~~~~ - ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_packed_concat_bad.v:18:46: Unsized numbers/parameters not allowed in concatenations. : ... In instance t diff --git a/test_regress/t/t_param_concat_bad.out b/test_regress/t/t_param_concat_bad.out index 1cc22b953..008022682 100644 --- a/test_regress/t/t_param_concat_bad.out +++ b/test_regress/t/t_param_concat_bad.out @@ -2,7 +2,7 @@ : ... In instance t 19 | if ({UNSIZED,UNSIZED+1} != {32'd10, 32'd11}) $stop; | ^~~~~~~ - ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTHCONCAT?v=latest ... Use "/* verilator lint_off WIDTHCONCAT */" and lint_on around source to disable this message. %Warning-WIDTHCONCAT: t/t_param_concat.v:19:22: Unsized numbers/parameters not allowed in replications. : ... In instance t diff --git a/test_regress/t/t_param_in_func_bad.out b/test_regress/t/t_param_in_func_bad.out index 11d333858..73820ed23 100644 --- a/test_regress/t/t_param_in_func_bad.out +++ b/test_regress/t/t_param_in_func_bad.out @@ -2,5 +2,5 @@ : ... In instance t 24 | localparam logic[7:0] digits[10] | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_param_noval_bad.out b/test_regress/t/t_param_noval_bad.out index bac882641..66b235cac 100644 --- a/test_regress/t/t_param_noval_bad.out +++ b/test_regress/t/t_param_noval_bad.out @@ -6,7 +6,7 @@ : ... In instance t 10 | for (j=0; P; j++) | ^~~ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Error: t/t_param_noval_bad.v:10:7: Non-genvar used in generate for: 'j' : ... In instance t diff --git a/test_regress/t/t_param_scope_bad.out b/test_regress/t/t_param_scope_bad.out index d9286ecb4..eddd36bd1 100644 --- a/test_regress/t/t_param_scope_bad.out +++ b/test_regress/t/t_param_scope_bad.out @@ -1,6 +1,6 @@ %Warning-CASEOVERLAP: t/t_param_scope_bad.v:28:9: Case values overlap (example pattern 0x2) 28 | 2'h2: $stop; | ^~~~ - ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=4.201 + ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=latest ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_param_sel_range_bad.out b/test_regress/t/t_param_sel_range_bad.out index 8e8cf5f93..9316728ba 100644 --- a/test_regress/t/t_param_sel_range_bad.out +++ b/test_regress/t/t_param_sel_range_bad.out @@ -2,6 +2,6 @@ : ... In instance t.u2 43 | r_rst[i] <= r_rst[i-1]; | ^ - ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 + ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_past_bad.out b/test_regress/t/t_past_bad.out index 70144f13b..f1e1ea1b8 100644 --- a/test_regress/t/t_past_bad.out +++ b/test_regress/t/t_past_bad.out @@ -14,6 +14,6 @@ : ... In instance t 18 | if ($past(d, 10000)) $stop; | ^~~~~ - ... For warning description see https://verilator.org/warn/TICKCOUNT?v=4.201 + ... For warning description see https://verilator.org/warn/TICKCOUNT?v=latest ... Use "/* verilator lint_off TICKCOUNT */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_past_unsup_bad.out b/test_regress/t/t_past_unsup_bad.out index 5115fdf14..e55f867f2 100644 --- a/test_regress/t/t_past_unsup_bad.out +++ b/test_regress/t/t_past_unsup_bad.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_past_unsup_bad.v:13:11: Unsupported: $past expr2 and clock arguments 13 | if ($past(d, 0, 0)) $stop; | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_past_unsup_bad.v:14:11: Unsupported: $past expr2 and clock arguments 14 | if ($past(d, 0, 0, clk)) $stop; | ^~~~~ diff --git a/test_regress/t/t_pp_dupdef_bad.out b/test_regress/t/t_pp_dupdef_bad.out index af9756bc6..76125b347 100644 --- a/test_regress/t/t_pp_dupdef_bad.out +++ b/test_regress/t/t_pp_dupdef_bad.out @@ -1,6 +1,6 @@ %Warning-REDEFMACRO: t/t_pp_dupdef.v:11:20: Redefining existing define: 'DUP', with different value: 'barney' t/t_pp_dupdef.v:11:20: ... Location of previous definition, with value: 'fred' - ... For warning description see https://verilator.org/warn/REDEFMACRO?v=4.201 + ... For warning description see https://verilator.org/warn/REDEFMACRO?v=latest ... Use "/* verilator lint_off REDEFMACRO */" and lint_on around source to disable this message. %Warning-REDEFMACRO: t/t_pp_dupdef.v:14:33: Redefining existing define: 'DUPP', with different value: 'paramed(x,z) (x*z)' t/t_pp_dupdef.v:14:33: ... Location of previous definition, with value: 'paramed(x) (x)' diff --git a/test_regress/t/t_priority_case.out b/test_regress/t/t_priority_case.out index e2705c6d9..468773b6c 100644 --- a/test_regress/t/t_priority_case.out +++ b/test_regress/t/t_priority_case.out @@ -1,7 +1,7 @@ %Warning-CASEOVERLAP: t/t_priority_case.v:34:7: Case item ignored: every matching value is covered by an earlier item 34 | 2'b ?1: out1 = 3'd1; | ^~~~~~ - ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=4.201 + ... For warning description see https://verilator.org/warn/CASEOVERLAP?v=latest ... Use "/* verilator lint_off CASEOVERLAP */" and lint_on around source to disable this message. %Warning-CASEOVERLAP: t/t_priority_case.v:44:7: Case item ignored: every matching value is covered by an earlier item 44 | 2'b ?1: out1 = 3'd1; diff --git a/test_regress/t/t_process.out b/test_regress/t/t_process.out index 4d1f1a1b8..a4ada3778 100644 --- a/test_regress/t/t_process.out +++ b/test_regress/t/t_process.out @@ -4,7 +4,7 @@ %Error-UNSUPPORTED: t/t_process.v:26:20: Unsupported: 'process' 26 | p = process::self(); | ^~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Internal Error: t/t_process.v:26:11: ../V3LinkDot.cpp:#: Bad package link 26 | p = process::self(); | ^~~~~~~ diff --git a/test_regress/t/t_prot_lib_inout_bad.out b/test_regress/t/t_prot_lib_inout_bad.out index 733fcc80c..df36c979d 100644 --- a/test_regress/t/t_prot_lib_inout_bad.out +++ b/test_regress/t/t_prot_lib_inout_bad.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_prot_lib_inout_bad.v:9:28: Unsupported: protect-lib port direction: INOUT 9 | inout z, | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_protect_ids_bad.out b/test_regress/t/t_protect_ids_bad.out index 7e32b4b2c..8487cf844 100644 --- a/test_regress/t/t_protect_ids_bad.out +++ b/test_regress/t/t_protect_ids_bad.out @@ -1,6 +1,6 @@ %Error-UNSUPPORTED: Unsupported: Using --protect-ids with --public ... Suggest remove --public. - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Warning-INSECURE: Using --protect-ids with --trace may expose private design details ... Suggest remove --trace. ... Use "/* verilator lint_off INSECURE */" and lint_on around source to disable this message. diff --git a/test_regress/t/t_randc_unsup.out b/test_regress/t/t_randc_unsup.out index 3e4ca214d..7d3436a4a 100644 --- a/test_regress/t/t_randc_unsup.out +++ b/test_regress/t/t_randc_unsup.out @@ -1,6 +1,6 @@ %Warning-RANDC: t/t_randc_unsup.v:8:14: Unsupported: Converting 'randc' to 'rand' 8 | randc int i; | ^ - ... For warning description see https://verilator.org/warn/RANDC?v=4.201 + ... For warning description see https://verilator.org/warn/RANDC?v=latest ... Use "/* verilator lint_off RANDC */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_randomize.out b/test_regress/t/t_randomize.out index c51190262..e46ab03c5 100644 --- a/test_regress/t/t_randomize.out +++ b/test_regress/t/t_randomize.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_randomize.v:11:4: Unsupported: extern constraint 11 | extern constraint ex; | ^~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_randomize.v:29:29: Unsupported: solve before 29 | constraint order { solve length before header; } | ^~~~~~ diff --git a/test_regress/t/t_randomize_method_types_unsup.out b/test_regress/t/t_randomize_method_types_unsup.out index 1f5c2bf5d..66d2da0d7 100644 --- a/test_regress/t/t_randomize_method_types_unsup.out +++ b/test_regress/t/t_randomize_method_types_unsup.out @@ -2,7 +2,7 @@ : ... In instance t 12 | rand int assocarr[string]; | ^~~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_randomize_method_types_unsup.v:13:13: Unsupported: random member variables with type 'int[]' : ... In instance t 13 | rand int dynarr[]; diff --git a/test_regress/t/t_randomize_method_unsup.out b/test_regress/t/t_randomize_method_unsup.out index b394b34f1..42f6c65fa 100644 --- a/test_regress/t/t_randomize_method_unsup.out +++ b/test_regress/t/t_randomize_method_unsup.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_randomize_method_unsup.v:8:18: Unsupported: 'pre_randomize' 8 | function void pre_randomize; | ^~~~~~~~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_randomize_method_unsup.v:11:18: Unsupported: 'post_randomize' 11 | function void post_randomize; | ^~~~~~~~~~~~~~ diff --git a/test_regress/t/t_savable_class_bad.out b/test_regress/t/t_savable_class_bad.out index 56b78a4de..58f83f479 100644 --- a/test_regress/t/t_savable_class_bad.out +++ b/test_regress/t/t_savable_class_bad.out @@ -1,3 +1,3 @@ %Error-UNSUPPORTED: Unsupported: --savable with dynamic new - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_msb.out b/test_regress/t/t_select_bad_msb.out index f288d49e1..6c52f62b3 100644 --- a/test_regress/t/t_select_bad_msb.out +++ b/test_regress/t/t_select_bad_msb.out @@ -2,7 +2,7 @@ : ... In instance t 12 | reg [0:22] backwd; | ^ - ... For warning description see https://verilator.org/warn/LITENDIAN?v=4.201 + ... For warning description see https://verilator.org/warn/LITENDIAN?v=latest ... Use "/* verilator lint_off LITENDIAN */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_msb.v:16:16: [1:4] Range extract has backward bit ordering, perhaps you wanted [4:1] : ... In instance t diff --git a/test_regress/t/t_select_bad_range.out b/test_regress/t/t_select_bad_range.out index 97f6beeef..c0b031982 100644 --- a/test_regress/t/t_select_bad_range.out +++ b/test_regress/t/t_select_bad_range.out @@ -2,7 +2,7 @@ : ... In instance t 16 | sel = mi[44]; | ^ - ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 + ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Warning-SELRANGE: t/t_select_bad_range.v:17:16: Selection index out of range: 44:41 outside 43:0 : ... In instance t diff --git a/test_regress/t/t_select_bad_range2.out b/test_regress/t/t_select_bad_range2.out index b45732a65..f648d7c2b 100644 --- a/test_regress/t/t_select_bad_range2.out +++ b/test_regress/t/t_select_bad_range2.out @@ -2,6 +2,6 @@ : ... In instance t.test 51 | assign out32 = in[3:2]; | ^ - ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 + ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_select_bad_range3.out b/test_regress/t/t_select_bad_range3.out index ad9ce0380..fa19b0512 100644 --- a/test_regress/t/t_select_bad_range3.out +++ b/test_regress/t/t_select_bad_range3.out @@ -2,6 +2,6 @@ : ... In instance t 19 | assign outwires[12] = inwires[13]; | ^ - ... For warning description see https://verilator.org/warn/SELRANGE?v=4.201 + ... For warning description see https://verilator.org/warn/SELRANGE?v=latest ... Use "/* verilator lint_off SELRANGE */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_split_var_1_bad.out b/test_regress/t/t_split_var_1_bad.out index b55cafcf3..40dab2d0e 100644 --- a/test_regress/t/t_split_var_1_bad.out +++ b/test_regress/t/t_split_var_1_bad.out @@ -1,7 +1,7 @@ %Warning-SPLITVAR: t/t_split_var_1_bad.v:7:13: 'should_show_warning_global0' has split_var metacomment, but will not be split because it is not declared in a module. 7 | logic [7:0] should_show_warning_global0 /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ - ... For warning description see https://verilator.org/warn/SPLITVAR?v=4.201 + ... For warning description see https://verilator.org/warn/SPLITVAR?v=latest ... Use "/* verilator lint_off SPLITVAR */" and lint_on around source to disable this message. %Warning-SPLITVAR: t/t_split_var_1_bad.v:8:13: 'should_show_warning_global1' has split_var metacomment, but will not be split because it is not declared in a module. 8 | logic [7:0] should_show_warning_global1 [1:0] /*verilator split_var*/ ; diff --git a/test_regress/t/t_stream_integer_type.out b/test_regress/t/t_stream_integer_type.out index a8fd0cf20..59b6a116d 100644 --- a/test_regress/t/t_stream_integer_type.out +++ b/test_regress/t/t_stream_integer_type.out @@ -2,7 +2,7 @@ : ... In instance t 118 | packed_data_32 = {<<8{byte_in}}; | ^ - ... For warning description see https://verilator.org/warn/WIDTH?v=4.201 + ... For warning description see https://verilator.org/warn/WIDTH?v=latest ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_stream_integer_type.v:119:28: Operator ASSIGN expects 64 bits on the Assign RHS, but Assign RHS's STREAML generates 16 bits. : ... In instance t diff --git a/test_regress/t/t_struct_unpacked2.out b/test_regress/t/t_struct_unpacked2.out index b5f430c28..d31ee7fcd 100644 --- a/test_regress/t/t_struct_unpacked2.out +++ b/test_regress/t/t_struct_unpacked2.out @@ -1,7 +1,7 @@ %Warning-UNPACKED: t/t_struct_unpacked2.v:10:13: Unsupported: Unpacked array in packed struct/union (struct/union converted to unpacked) 10 | int b [2]; | ^ - ... For warning description see https://verilator.org/warn/UNPACKED?v=4.201 + ... For warning description see https://verilator.org/warn/UNPACKED?v=latest ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message. %Warning-UNPACKED: t/t_struct_unpacked2.v:9:12: Unsupported: Unpacked struct/union : ... In instance x diff --git a/test_regress/t/t_struct_unpacked_bad.out b/test_regress/t/t_struct_unpacked_bad.out index 29d8c0208..6b83b545a 100644 --- a/test_regress/t/t_struct_unpacked_bad.out +++ b/test_regress/t/t_struct_unpacked_bad.out @@ -2,6 +2,6 @@ : ... In instance x 9 | typedef struct { | ^~~~~~ - ... For warning description see https://verilator.org/warn/UNPACKED?v=4.201 + ... For warning description see https://verilator.org/warn/UNPACKED?v=latest ... Use "/* verilator lint_off UNPACKED */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_sys_readmem_assoc_bad.out b/test_regress/t/t_sys_readmem_assoc_bad.out index 220cfebcc..2a1695a99 100644 --- a/test_regress/t/t_sys_readmem_assoc_bad.out +++ b/test_regress/t/t_sys_readmem_assoc_bad.out @@ -6,5 +6,5 @@ : ... In instance t 14 | $readmemb("not", assoc_bad_value); | ^~~~~~~~~~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_timescale_lint_bad.out b/test_regress/t/t_timescale_lint_bad.out index 771e03304..eedb4e17f 100644 --- a/test_regress/t/t_timescale_lint_bad.out +++ b/test_regress/t/t_timescale_lint_bad.out @@ -4,6 +4,6 @@ t/t_timescale_lint.v:12:8: ... Location of module with timescale 12 | module t; | ^ - ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=4.201 + ... For warning description see https://verilator.org/warn/TIMESCALEMOD?v=latest ... Use "/* verilator lint_off TIMESCALEMOD */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_tri_compass_bad.out b/test_regress/t/t_tri_compass_bad.out index b48142931..d9c240860 100644 --- a/test_regress/t/t_tri_compass_bad.out +++ b/test_regress/t/t_tri_compass_bad.out @@ -2,5 +2,5 @@ : ... In instance t 16 | sub sub(i, o); | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_tri_pull2_bad.out b/test_regress/t/t_tri_pull2_bad.out index 67d77c7bc..ea60ddfd2 100644 --- a/test_regress/t/t_tri_pull2_bad.out +++ b/test_regress/t/t_tri_pull2_bad.out @@ -5,5 +5,5 @@ t/t_tri_pull2_bad.v:22:13: ... Location of conflicting pull. 22 | pulldown p2(A); | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_tri_pull_bad.out b/test_regress/t/t_tri_pull_bad.out index 15889fc4f..6d7960c19 100644 --- a/test_regress/t/t_tri_pull_bad.out +++ b/test_regress/t/t_tri_pull_bad.out @@ -5,5 +5,5 @@ t/t_tri_pull_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p1(A); | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_tri_pullvec_bad.out b/test_regress/t/t_tri_pullvec_bad.out index e4b2ce9ca..ae95a7c27 100644 --- a/test_regress/t/t_tri_pullvec_bad.out +++ b/test_regress/t/t_tri_pullvec_bad.out @@ -5,7 +5,7 @@ t/t_tri_pullvec_bad.v:12:11: ... Location of conflicting pull. 12 | pullup p0 (w[0]); | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_tri_pullvec_bad.v:14:13: Unsupported: Conflicting pull directions. : ... In instance t 14 | pulldown p2 (w[2]); diff --git a/test_regress/t/t_udp.out b/test_regress/t/t_udp.out index 6cf8a41f4..3f274bfa6 100644 --- a/test_regress/t/t_udp.out +++ b/test_regress/t/t_udp.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_udp.v:104:4: Unsupported: Verilog 1995 UDP Tables. Use --bbox-unsup to ignore tables. 104 | table | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_udp_bad.out b/test_regress/t/t_udp_bad.out index f190c275f..4484513c6 100644 --- a/test_regress/t/t_udp_bad.out +++ b/test_regress/t/t_udp_bad.out @@ -1,7 +1,7 @@ %Warning-PINMISSING: t/t_udp_bad.v:10:10: Cell has missing pin: 'c_bad' 10 | udp_x x (a, b); | ^ - ... For warning description see https://verilator.org/warn/PINMISSING?v=4.201 + ... For warning description see https://verilator.org/warn/PINMISSING?v=latest ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Error: t/t_udp_bad.v:14:18: Pin is not an in/out/inout/interface: 'a_bad' 14 | primitive udp_x (a_bad, b, c_bad); diff --git a/test_regress/t/t_unopt_combo_bad.out b/test_regress/t/t_unopt_combo_bad.out index 7b31be8ab..4e0c5f49b 100644 --- a/test_regress/t/t_unopt_combo_bad.out +++ b/test_regress/t/t_unopt_combo_bad.out @@ -1,7 +1,7 @@ %Warning-UNOPTFLAT: t/t_unopt_combo.v:24:25: Signal unoptimizable: Feedback to clock or circular logic: 't.c' 24 | wire [31:0] c; | ^ - ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=4.201 + ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unopt_combo.v:24:25: Example path: t.c t/t_unopt_combo.v:81:4: Example path: ALWAYS diff --git a/test_regress/t/t_unopt_converge_unopt_bad.out b/test_regress/t/t_unopt_converge_unopt_bad.out index 51fd138ee..41c20b620 100644 --- a/test_regress/t/t_unopt_converge_unopt_bad.out +++ b/test_regress/t/t_unopt_converge_unopt_bad.out @@ -1,7 +1,7 @@ %Warning-UNOPT: t/t_unopt_converge.v:19:11: Signal unoptimizable: Feedback to public clock or circular logic: 'x' 19 | output x; | ^ - ... For warning description see https://verilator.org/warn/UNOPT?v=4.201 + ... For warning description see https://verilator.org/warn/UNOPT?v=latest ... Use "/* verilator lint_off UNOPT */" and lint_on around source to disable this message. t/t_unopt_converge.v:19:11: Example path: x t/t_unopt_converge.v:22:4: Example path: ALWAYS diff --git a/test_regress/t/t_unoptflat_simple_2_bad.out b/test_regress/t/t_unoptflat_simple_2_bad.out index 3ba06168f..15d38a892 100644 --- a/test_regress/t/t_unoptflat_simple_2_bad.out +++ b/test_regress/t/t_unoptflat_simple_2_bad.out @@ -1,7 +1,7 @@ %Warning-UNOPTFLAT: t/t_unoptflat_simple_2.v:15:15: Signal unoptimizable: Feedback to clock or circular logic: 't.x' 15 | wire [2:0] x; | ^ - ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=4.201 + ... For warning description see https://verilator.org/warn/UNOPTFLAT?v=latest ... Use "/* verilator lint_off UNOPTFLAT */" and lint_on around source to disable this message. t/t_unoptflat_simple_2.v:15:15: Example path: t.x t/t_unoptflat_simple_2.v:17:18: Example path: ASSIGNW diff --git a/test_regress/t/t_unpacked_concat_bad.out b/test_regress/t/t_unpacked_concat_bad.out index fccb233a3..4c89adfe6 100644 --- a/test_regress/t/t_unpacked_concat_bad.out +++ b/test_regress/t/t_unpacked_concat_bad.out @@ -2,7 +2,7 @@ : ... In instance t 17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; | ^ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Warning-WIDTHCONCAT: t/t_unpacked_concat_bad.v:17:47: Unsized numbers/parameters not allowed in replications. : ... In instance t 17 | localparam bit_int_t count_bits [1:0] = {2{$bits(count_t)}}; diff --git a/test_regress/t/t_vams_kwd_bad.out b/test_regress/t/t_vams_kwd_bad.out index 500595296..0d6fac32e 100644 --- a/test_regress/t/t_vams_kwd_bad.out +++ b/test_regress/t/t_vams_kwd_bad.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_vams_kwd_bad.v:12:8: Unsupported: AMS reserved word not implemented: 'above' 12 | int above; | ^~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: t/t_vams_kwd_bad.v:12:13: syntax error, unexpected ';', expecting IDENTIFIER or randomize 12 | int above; | ^ diff --git a/test_regress/t/t_var_bad_hide.out b/test_regress/t/t_var_bad_hide.out index 27599dc26..2abf987c3 100644 --- a/test_regress/t/t_var_bad_hide.out +++ b/test_regress/t/t_var_bad_hide.out @@ -4,7 +4,7 @@ t/t_var_bad_hide.v:13:12: ... Location of original declaration 13 | integer top; | ^~~ - ... For warning description see https://verilator.org/warn/VARHIDDEN?v=4.201 + ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Warning-VARHIDDEN: t/t_var_bad_hide.v:22:18: Declaration of signal hides declaration in upper scope: 'top' 22 | integer top; diff --git a/test_regress/t/t_var_bad_hide2.out b/test_regress/t/t_var_bad_hide2.out index ee41a5f0c..fbb05eba6 100644 --- a/test_regress/t/t_var_bad_hide2.out +++ b/test_regress/t/t_var_bad_hide2.out @@ -4,6 +4,6 @@ t/t_var_bad_hide2.v:7:8: ... Location of original declaration 7 | module t; | ^ - ... For warning description see https://verilator.org/warn/VARHIDDEN?v=4.201 + ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_var_bad_hide_docs.out b/test_regress/t/t_var_bad_hide_docs.out index 86ee16b64..78467eb5a 100644 --- a/test_regress/t/t_var_bad_hide_docs.out +++ b/test_regress/t/t_var_bad_hide_docs.out @@ -4,6 +4,6 @@ t/t_var_bad_hide_docs.v:7:8: ... Location of original declaration 7 | module t; | ^ - ... For warning description see https://verilator.org/warn/VARHIDDEN?v=4.201 + ... For warning description see https://verilator.org/warn/VARHIDDEN?v=latest ... Use "/* verilator lint_off VARHIDDEN */" and lint_on around source to disable this message. %Error: Exiting due to diff --git a/test_regress/t/t_var_in_assign_bad.out b/test_regress/t/t_var_in_assign_bad.out index a32dcc803..5d8b116c1 100644 --- a/test_regress/t/t_var_in_assign_bad.out +++ b/test_regress/t/t_var_in_assign_bad.out @@ -1,7 +1,7 @@ %Error-ASSIGNIN: t/t_var_in_assign_bad.v:12:16: Assigning to input/const variable: 'value' 12 | assign value = 4'h0; | ^~~~~ - ... For error description see https://verilator.org/warn/ASSIGNIN?v=4.201 + ... For error description see https://verilator.org/warn/ASSIGNIN?v=latest %Error-ASSIGNIN: t/t_var_in_assign_bad.v:21:16: Assigning to input/const variable: 'valueSub' 21 | assign valueSub = 4'h0; | ^~~~~~~~ diff --git a/test_regress/t/t_var_ref_bad3.out b/test_regress/t/t_var_ref_bad3.out index 2dc201162..d71495978 100644 --- a/test_regress/t/t_var_ref_bad3.out +++ b/test_regress/t/t_var_ref_bad3.out @@ -1,5 +1,5 @@ %Error-UNSUPPORTED: t/t_var_ref_bad3.v:10:18: Unsupported: ref/const ref as primary input/output: 'bad_primary_ref' 10 | module t(ref int bad_primary_ref | ^~~~~~~~~~~~~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_var_rsvd_bad.out b/test_regress/t/t_var_rsvd_bad.out index 04bc62b04..ef3f32fc0 100644 --- a/test_regress/t/t_var_rsvd_bad.out +++ b/test_regress/t/t_var_rsvd_bad.out @@ -1,7 +1,7 @@ %Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:12:10: Symbol matches C++ keyword: 'bool' 12 | input bool; | ^~~~ - ... For warning description see https://verilator.org/warn/SYMRSVDWORD?v=4.201 + ... For warning description see https://verilator.org/warn/SYMRSVDWORD?v=latest ... Use "/* verilator lint_off SYMRSVDWORD */" and lint_on around source to disable this message. %Warning-SYMRSVDWORD: t/t_var_rsvd_port.v:15:9: Symbol matches C++ keyword: 'switch' : ... In instance t diff --git a/test_regress/t/t_var_static.out b/test_regress/t/t_var_static.out index 3781d41ac..01e0c2fa9 100644 --- a/test_regress/t/t_var_static.out +++ b/test_regress/t/t_var_static.out @@ -2,7 +2,7 @@ : ... In instance t 20 | static int st = 2; st++; return st; | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_var_static.v:30:18: Unsupported: 'static' function/task variables : ... In instance t 30 | static int st = 2; st++; return st; diff --git a/test_regress/t/t_var_static_param.out b/test_regress/t/t_var_static_param.out index a87e35d6c..ac3c941a9 100644 --- a/test_regress/t/t_var_static_param.out +++ b/test_regress/t/t_var_static_param.out @@ -2,5 +2,5 @@ : ... In instance t.subb 32 | static int st = 2; st += P; return st; | ^~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error: Exiting due to diff --git a/test_regress/t/t_var_types_bad.out b/test_regress/t/t_var_types_bad.out index 291a3db6a..47c3d490b 100644 --- a/test_regress/t/t_var_types_bad.out +++ b/test_regress/t/t_var_types_bad.out @@ -21,7 +21,7 @@ %Warning-REALCVT: t/t_var_types_bad.v:46:7: Implicit conversion of real to integer 46 | d_real[0] = 1'b1; | ^~~~~~ - ... For warning description see https://verilator.org/warn/REALCVT?v=4.201 + ... For warning description see https://verilator.org/warn/REALCVT?v=latest ... Use "/* verilator lint_off REALCVT */" and lint_on around source to disable this message. %Error: t/t_var_types_bad.v:47:17: Illegal bit or array select; type does not have a bit range, or bad dimension: data type is 'real' : ... In instance t diff --git a/test_regress/t/t_vlt_warn_bad.out b/test_regress/t/t_vlt_warn_bad.out index 646936098..29c29c3b9 100644 --- a/test_regress/t/t_vlt_warn_bad.out +++ b/test_regress/t/t_vlt_warn_bad.out @@ -1,7 +1,7 @@ %Warning-DEPRECATED: t/t_vlt_warn_bad.vlt:12:10: Deprecated -msg in configuration files, use -rule instead. 12 | lint_off -msg WIDTH -file "*/t_vlt_warn.v" -lines 19-19 | ^~~~ - ... For warning description see https://verilator.org/warn/DEPRECATED?v=4.201 + ... For warning description see https://verilator.org/warn/DEPRECATED?v=latest ... Use "/* verilator lint_off DEPRECATED */" and lint_on around source to disable this message. %Warning-WIDTH: t/t_vlt_warn.v:21:33: Operator ASSIGN expects 1 bits on the Assign RHS, but Assign RHS's CONST '2'h3' generates 2 bits. : ... In instance t diff --git a/test_regress/t/t_wait.out b/test_regress/t/t_wait.out index d71745e4f..409170e8e 100644 --- a/test_regress/t/t_wait.out +++ b/test_regress/t/t_wait.out @@ -1,7 +1,7 @@ %Error-UNSUPPORTED: t/t_wait.v:12:7: Unsupported: wait statements 12 | wait (value == 1); | ^~~~ - ... For error description see https://verilator.org/warn/UNSUPPORTED?v=4.201 + ... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest %Error-UNSUPPORTED: t/t_wait.v:14:7: Unsupported: wait statements 14 | wait (0); | ^~~~ diff --git a/test_regress/t/t_wire_beh1364_bad.out b/test_regress/t/t_wire_beh1364_bad.out index c53c1ab06..e9ff7ee3d 100644 --- a/test_regress/t/t_wire_beh1364_bad.out +++ b/test_regress/t/t_wire_beh1364_bad.out @@ -2,7 +2,7 @@ : ... In instance t 25 | w = '0; | ^ - ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_wire_beh1364_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 26 | o = '0; diff --git a/test_regress/t/t_wire_beh1800_bad.out b/test_regress/t/t_wire_beh1800_bad.out index 8d48b7ac1..7f6881e18 100644 --- a/test_regress/t/t_wire_beh1800_bad.out +++ b/test_regress/t/t_wire_beh1800_bad.out @@ -2,7 +2,7 @@ : ... In instance t 25 | w = '0; | ^ - ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_wire_beh1800_bad.v:26:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 26 | o = '0; diff --git a/test_regress/t/t_wire_behp1364_bad.out b/test_regress/t/t_wire_behp1364_bad.out index ed4055430..68b6db330 100644 --- a/test_regress/t/t_wire_behp1364_bad.out +++ b/test_regress/t/t_wire_behp1364_bad.out @@ -2,7 +2,7 @@ : ... In instance t 23 | w = '0; | ^ - ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_wire_behp1364_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 24 | o = '0; diff --git a/test_regress/t/t_wire_behp1800_bad.out b/test_regress/t/t_wire_behp1800_bad.out index 200179d4c..658c081e0 100644 --- a/test_regress/t/t_wire_behp1800_bad.out +++ b/test_regress/t/t_wire_behp1800_bad.out @@ -2,7 +2,7 @@ : ... In instance t 23 | w = '0; | ^ - ... For error description see https://verilator.org/warn/PROCASSWIRE?v=4.201 + ... For error description see https://verilator.org/warn/PROCASSWIRE?v=latest %Error-PROCASSWIRE: t/t_wire_behp1800_bad.v:24:7: Procedural assignment to wire, perhaps intended var (IEEE 1800-2017 6.5): 'o' : ... In instance t 24 | o = '0; From 15f7741eaf0e24e8527927f9f10ac9f811d0d30b Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 24 Apr 2021 10:34:05 -0400 Subject: [PATCH 110/110] Version bump --- Changes | 2 +- configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Changes b/Changes index d7ab1ecfe..3a0460c94 100644 --- a/Changes +++ b/Changes @@ -8,7 +8,7 @@ The changes in each Verilator version are described below. The contributors that suggested a given feature are shown in []. Thanks! -Verilator 4.201 devel +Verilator 4.202 2021-04-24 ========================== **Major:** diff --git a/configure.ac b/configure.ac index e8c5ac7f4..fce513b17 100644 --- a/configure.ac +++ b/configure.ac @@ -7,7 +7,7 @@ #AC_INIT([Verilator],[#.### YYYY-MM-DD]) #AC_INIT([Verilator],[#.### devel]) -AC_INIT([Verilator],[4.201 devel], +AC_INIT([Verilator],[4.202 2021-04-24], [https://verilator.org], [verilator],[https://verilator.org]) # When releasing, also update header of Changes file